1 /* 2 * wm8995.c -- WM8995 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Wolfson Microelectronics plc 5 * 6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 7 * 8 * Based on wm8994.c and wm_hubs.c by Mark Brown 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/regmap.h> 22 #include <linux/spi/spi.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "wm8995.h" 34 35 #define WM8995_NUM_SUPPLIES 8 36 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { 37 "DCVDD", 38 "DBVDD1", 39 "DBVDD2", 40 "DBVDD3", 41 "AVDD1", 42 "AVDD2", 43 "CPVDD", 44 "MICVDD" 45 }; 46 47 static struct reg_default wm8995_reg_defaults[] = { 48 { 0, 0x8995 }, 49 { 5, 0x0100 }, 50 { 16, 0x000b }, 51 { 17, 0x000b }, 52 { 24, 0x02c0 }, 53 { 25, 0x02c0 }, 54 { 26, 0x02c0 }, 55 { 27, 0x02c0 }, 56 { 28, 0x000f }, 57 { 32, 0x0005 }, 58 { 33, 0x0005 }, 59 { 40, 0x0003 }, 60 { 41, 0x0013 }, 61 { 48, 0x0004 }, 62 { 56, 0x09f8 }, 63 { 64, 0x1f25 }, 64 { 69, 0x0004 }, 65 { 82, 0xaaaa }, 66 { 84, 0x2a2a }, 67 { 146, 0x0060 }, 68 { 256, 0x0002 }, 69 { 257, 0x8004 }, 70 { 520, 0x0010 }, 71 { 528, 0x0083 }, 72 { 529, 0x0083 }, 73 { 548, 0x0c80 }, 74 { 580, 0x0c80 }, 75 { 768, 0x4050 }, 76 { 769, 0x4000 }, 77 { 771, 0x0040 }, 78 { 772, 0x0040 }, 79 { 773, 0x0040 }, 80 { 774, 0x0004 }, 81 { 775, 0x0100 }, 82 { 784, 0x4050 }, 83 { 785, 0x4000 }, 84 { 787, 0x0040 }, 85 { 788, 0x0040 }, 86 { 789, 0x0040 }, 87 { 1024, 0x00c0 }, 88 { 1025, 0x00c0 }, 89 { 1026, 0x00c0 }, 90 { 1027, 0x00c0 }, 91 { 1028, 0x00c0 }, 92 { 1029, 0x00c0 }, 93 { 1030, 0x00c0 }, 94 { 1031, 0x00c0 }, 95 { 1056, 0x0200 }, 96 { 1057, 0x0010 }, 97 { 1058, 0x0200 }, 98 { 1059, 0x0010 }, 99 { 1088, 0x0098 }, 100 { 1089, 0x0845 }, 101 { 1104, 0x0098 }, 102 { 1105, 0x0845 }, 103 { 1152, 0x6318 }, 104 { 1153, 0x6300 }, 105 { 1154, 0x0fca }, 106 { 1155, 0x0400 }, 107 { 1156, 0x00d8 }, 108 { 1157, 0x1eb5 }, 109 { 1158, 0xf145 }, 110 { 1159, 0x0b75 }, 111 { 1160, 0x01c5 }, 112 { 1161, 0x1c58 }, 113 { 1162, 0xf373 }, 114 { 1163, 0x0a54 }, 115 { 1164, 0x0558 }, 116 { 1165, 0x168e }, 117 { 1166, 0xf829 }, 118 { 1167, 0x07ad }, 119 { 1168, 0x1103 }, 120 { 1169, 0x0564 }, 121 { 1170, 0x0559 }, 122 { 1171, 0x4000 }, 123 { 1184, 0x6318 }, 124 { 1185, 0x6300 }, 125 { 1186, 0x0fca }, 126 { 1187, 0x0400 }, 127 { 1188, 0x00d8 }, 128 { 1189, 0x1eb5 }, 129 { 1190, 0xf145 }, 130 { 1191, 0x0b75 }, 131 { 1192, 0x01c5 }, 132 { 1193, 0x1c58 }, 133 { 1194, 0xf373 }, 134 { 1195, 0x0a54 }, 135 { 1196, 0x0558 }, 136 { 1197, 0x168e }, 137 { 1198, 0xf829 }, 138 { 1199, 0x07ad }, 139 { 1200, 0x1103 }, 140 { 1201, 0x0564 }, 141 { 1202, 0x0559 }, 142 { 1203, 0x4000 }, 143 { 1280, 0x00c0 }, 144 { 1281, 0x00c0 }, 145 { 1282, 0x00c0 }, 146 { 1283, 0x00c0 }, 147 { 1312, 0x0200 }, 148 { 1313, 0x0010 }, 149 { 1344, 0x0098 }, 150 { 1345, 0x0845 }, 151 { 1408, 0x6318 }, 152 { 1409, 0x6300 }, 153 { 1410, 0x0fca }, 154 { 1411, 0x0400 }, 155 { 1412, 0x00d8 }, 156 { 1413, 0x1eb5 }, 157 { 1414, 0xf145 }, 158 { 1415, 0x0b75 }, 159 { 1416, 0x01c5 }, 160 { 1417, 0x1c58 }, 161 { 1418, 0xf373 }, 162 { 1419, 0x0a54 }, 163 { 1420, 0x0558 }, 164 { 1421, 0x168e }, 165 { 1422, 0xf829 }, 166 { 1423, 0x07ad }, 167 { 1424, 0x1103 }, 168 { 1425, 0x0564 }, 169 { 1426, 0x0559 }, 170 { 1427, 0x4000 }, 171 { 1568, 0x0002 }, 172 { 1792, 0xa100 }, 173 { 1793, 0xa101 }, 174 { 1794, 0xa101 }, 175 { 1795, 0xa101 }, 176 { 1796, 0xa101 }, 177 { 1797, 0xa101 }, 178 { 1798, 0xa101 }, 179 { 1799, 0xa101 }, 180 { 1800, 0xa101 }, 181 { 1801, 0xa101 }, 182 { 1802, 0xa101 }, 183 { 1803, 0xa101 }, 184 { 1804, 0xa101 }, 185 { 1805, 0xa101 }, 186 { 1825, 0x0055 }, 187 { 1848, 0x3fff }, 188 { 1849, 0x1fff }, 189 { 2049, 0x0001 }, 190 { 2050, 0x0069 }, 191 { 2056, 0x0002 }, 192 { 2057, 0x0003 }, 193 { 2058, 0x0069 }, 194 { 12288, 0x0001 }, 195 { 12289, 0x0001 }, 196 { 12291, 0x0006 }, 197 { 12292, 0x0040 }, 198 { 12293, 0x0001 }, 199 { 12294, 0x000f }, 200 { 12295, 0x0006 }, 201 { 12296, 0x0001 }, 202 { 12297, 0x0003 }, 203 { 12298, 0x0104 }, 204 { 12300, 0x0060 }, 205 { 12301, 0x0011 }, 206 { 12302, 0x0401 }, 207 { 12304, 0x0050 }, 208 { 12305, 0x0003 }, 209 { 12306, 0x0100 }, 210 { 12308, 0x0051 }, 211 { 12309, 0x0003 }, 212 { 12310, 0x0104 }, 213 { 12311, 0x000a }, 214 { 12312, 0x0060 }, 215 { 12313, 0x003b }, 216 { 12314, 0x0502 }, 217 { 12315, 0x0100 }, 218 { 12316, 0x2fff }, 219 { 12320, 0x2fff }, 220 { 12324, 0x2fff }, 221 { 12328, 0x2fff }, 222 { 12332, 0x2fff }, 223 { 12336, 0x2fff }, 224 { 12340, 0x2fff }, 225 { 12344, 0x2fff }, 226 { 12348, 0x2fff }, 227 { 12352, 0x0001 }, 228 { 12353, 0x0001 }, 229 { 12355, 0x0006 }, 230 { 12356, 0x0040 }, 231 { 12357, 0x0001 }, 232 { 12358, 0x000f }, 233 { 12359, 0x0006 }, 234 { 12360, 0x0001 }, 235 { 12361, 0x0003 }, 236 { 12362, 0x0104 }, 237 { 12364, 0x0060 }, 238 { 12365, 0x0011 }, 239 { 12366, 0x0401 }, 240 { 12368, 0x0050 }, 241 { 12369, 0x0003 }, 242 { 12370, 0x0100 }, 243 { 12372, 0x0060 }, 244 { 12373, 0x003b }, 245 { 12374, 0x0502 }, 246 { 12375, 0x0100 }, 247 { 12376, 0x2fff }, 248 { 12380, 0x2fff }, 249 { 12384, 0x2fff }, 250 { 12388, 0x2fff }, 251 { 12392, 0x2fff }, 252 { 12396, 0x2fff }, 253 { 12400, 0x2fff }, 254 { 12404, 0x2fff }, 255 { 12408, 0x2fff }, 256 { 12412, 0x2fff }, 257 { 12416, 0x0001 }, 258 { 12417, 0x0001 }, 259 { 12419, 0x0006 }, 260 { 12420, 0x0040 }, 261 { 12421, 0x0001 }, 262 { 12422, 0x000f }, 263 { 12423, 0x0006 }, 264 { 12424, 0x0001 }, 265 { 12425, 0x0003 }, 266 { 12426, 0x0106 }, 267 { 12428, 0x0061 }, 268 { 12429, 0x0011 }, 269 { 12430, 0x0401 }, 270 { 12432, 0x0050 }, 271 { 12433, 0x0003 }, 272 { 12434, 0x0102 }, 273 { 12436, 0x0051 }, 274 { 12437, 0x0003 }, 275 { 12438, 0x0106 }, 276 { 12439, 0x000a }, 277 { 12440, 0x0061 }, 278 { 12441, 0x003b }, 279 { 12442, 0x0502 }, 280 { 12443, 0x0100 }, 281 { 12444, 0x2fff }, 282 { 12448, 0x2fff }, 283 { 12452, 0x2fff }, 284 { 12456, 0x2fff }, 285 { 12460, 0x2fff }, 286 { 12464, 0x2fff }, 287 { 12468, 0x2fff }, 288 { 12472, 0x2fff }, 289 { 12476, 0x2fff }, 290 { 12480, 0x0001 }, 291 { 12481, 0x0001 }, 292 { 12483, 0x0006 }, 293 { 12484, 0x0040 }, 294 { 12485, 0x0001 }, 295 { 12486, 0x000f }, 296 { 12487, 0x0006 }, 297 { 12488, 0x0001 }, 298 { 12489, 0x0003 }, 299 { 12490, 0x0106 }, 300 { 12492, 0x0061 }, 301 { 12493, 0x0011 }, 302 { 12494, 0x0401 }, 303 { 12496, 0x0050 }, 304 { 12497, 0x0003 }, 305 { 12498, 0x0102 }, 306 { 12500, 0x0061 }, 307 { 12501, 0x003b }, 308 { 12502, 0x0502 }, 309 { 12503, 0x0100 }, 310 { 12504, 0x2fff }, 311 { 12508, 0x2fff }, 312 { 12512, 0x2fff }, 313 { 12516, 0x2fff }, 314 { 12520, 0x2fff }, 315 { 12524, 0x2fff }, 316 { 12528, 0x2fff }, 317 { 12532, 0x2fff }, 318 { 12536, 0x2fff }, 319 { 12540, 0x2fff }, 320 { 12544, 0x0060 }, 321 { 12546, 0x0601 }, 322 { 12548, 0x0050 }, 323 { 12550, 0x0100 }, 324 { 12552, 0x0001 }, 325 { 12554, 0x0104 }, 326 { 12555, 0x0100 }, 327 { 12556, 0x2fff }, 328 { 12560, 0x2fff }, 329 { 12564, 0x2fff }, 330 { 12568, 0x2fff }, 331 { 12572, 0x2fff }, 332 { 12576, 0x2fff }, 333 { 12580, 0x2fff }, 334 { 12584, 0x2fff }, 335 { 12588, 0x2fff }, 336 { 12592, 0x2fff }, 337 { 12596, 0x2fff }, 338 { 12600, 0x2fff }, 339 { 12604, 0x2fff }, 340 { 12608, 0x0061 }, 341 { 12610, 0x0601 }, 342 { 12612, 0x0050 }, 343 { 12614, 0x0102 }, 344 { 12616, 0x0001 }, 345 { 12618, 0x0106 }, 346 { 12619, 0x0100 }, 347 { 12620, 0x2fff }, 348 { 12624, 0x2fff }, 349 { 12628, 0x2fff }, 350 { 12632, 0x2fff }, 351 { 12636, 0x2fff }, 352 { 12640, 0x2fff }, 353 { 12644, 0x2fff }, 354 { 12648, 0x2fff }, 355 { 12652, 0x2fff }, 356 { 12656, 0x2fff }, 357 { 12660, 0x2fff }, 358 { 12664, 0x2fff }, 359 { 12668, 0x2fff }, 360 { 12672, 0x0060 }, 361 { 12674, 0x0601 }, 362 { 12676, 0x0061 }, 363 { 12678, 0x0601 }, 364 { 12680, 0x0050 }, 365 { 12682, 0x0300 }, 366 { 12684, 0x0001 }, 367 { 12686, 0x0304 }, 368 { 12688, 0x0040 }, 369 { 12690, 0x000f }, 370 { 12692, 0x0001 }, 371 { 12695, 0x0100 }, 372 }; 373 374 struct fll_config { 375 int src; 376 int in; 377 int out; 378 }; 379 380 struct wm8995_priv { 381 struct regmap *regmap; 382 int sysclk[2]; 383 int mclk[2]; 384 int aifclk[2]; 385 struct fll_config fll[2], fll_suspend[2]; 386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; 387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; 388 struct snd_soc_codec *codec; 389 }; 390 391 /* 392 * We can't use the same notifier block for more than one supply and 393 * there's no way I can see to get from a callback to the caller 394 * except container_of(). 395 */ 396 #define WM8995_REGULATOR_EVENT(n) \ 397 static int wm8995_regulator_event_##n(struct notifier_block *nb, \ 398 unsigned long event, void *data) \ 399 { \ 400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ 401 disable_nb[n]); \ 402 if (event & REGULATOR_EVENT_DISABLE) { \ 403 regcache_mark_dirty(wm8995->regmap); \ 404 } \ 405 return 0; \ 406 } 407 408 WM8995_REGULATOR_EVENT(0) 409 WM8995_REGULATOR_EVENT(1) 410 WM8995_REGULATOR_EVENT(2) 411 WM8995_REGULATOR_EVENT(3) 412 WM8995_REGULATOR_EVENT(4) 413 WM8995_REGULATOR_EVENT(5) 414 WM8995_REGULATOR_EVENT(6) 415 WM8995_REGULATOR_EVENT(7) 416 417 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 418 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); 419 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); 420 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 421 422 static const char *in1l_text[] = { 423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP" 424 }; 425 426 static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 427 2, in1l_text); 428 429 static const char *in1r_text[] = { 430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP" 431 }; 432 433 static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 434 0, in1r_text); 435 436 static const char *dmic_src_text[] = { 437 "DMICDAT1", "DMICDAT2", "DMICDAT3" 438 }; 439 440 static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, 441 8, dmic_src_text); 442 static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, 443 6, dmic_src_text); 444 445 static const struct snd_kcontrol_new wm8995_snd_controls[] = { 446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, 447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, 449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), 450 451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, 452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, 454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), 455 456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, 457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, 459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, 461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 462 463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, 464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), 465 466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, 467 4, 3, 0, in1l_boost_tlv), 468 469 SOC_ENUM("IN1L Mode", in1l_enum), 470 SOC_ENUM("IN1R Mode", in1r_enum), 471 472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum), 473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum), 474 475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, 476 24, 0, sidetone_tlv), 477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, 478 24, 0, sidetone_tlv), 479 480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, 481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, 483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, 485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) 486 }; 487 488 static void wm8995_update_class_w(struct snd_soc_codec *codec) 489 { 490 int enable = 1; 491 int source = 0; /* GCC flow analysis can't track enable */ 492 int reg, reg_r; 493 494 /* We also need the same setting for L/R and only one path */ 495 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); 496 switch (reg) { 497 case WM8995_AIF2DACL_TO_DAC1L: 498 dev_dbg(codec->dev, "Class W source AIF2DAC\n"); 499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; 500 break; 501 case WM8995_AIF1DAC2L_TO_DAC1L: 502 dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); 503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; 504 break; 505 case WM8995_AIF1DAC1L_TO_DAC1L: 506 dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); 507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; 508 break; 509 default: 510 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); 511 enable = 0; 512 break; 513 } 514 515 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); 516 if (reg_r != reg) { 517 dev_dbg(codec->dev, "Left and right DAC mixers different\n"); 518 enable = 0; 519 } 520 521 if (enable) { 522 dev_dbg(codec->dev, "Class W enabled\n"); 523 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 524 WM8995_CP_DYN_PWR_MASK | 525 WM8995_CP_DYN_SRC_SEL_MASK, 526 source | WM8995_CP_DYN_PWR); 527 } else { 528 dev_dbg(codec->dev, "Class W disabled\n"); 529 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 530 WM8995_CP_DYN_PWR_MASK, 0); 531 } 532 } 533 534 static int check_clk_sys(struct snd_soc_dapm_widget *source, 535 struct snd_soc_dapm_widget *sink) 536 { 537 unsigned int reg; 538 const char *clk; 539 540 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); 541 /* Check what we're currently using for CLK_SYS */ 542 if (reg & WM8995_SYSCLK_SRC) 543 clk = "AIF2CLK"; 544 else 545 clk = "AIF1CLK"; 546 return !strcmp(source->name, clk); 547 } 548 549 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, 550 struct snd_ctl_elem_value *ucontrol) 551 { 552 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 553 int ret; 554 555 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 556 wm8995_update_class_w(codec); 557 return ret; 558 } 559 560 static int hp_supply_event(struct snd_soc_dapm_widget *w, 561 struct snd_kcontrol *kcontrol, int event) 562 { 563 struct snd_soc_codec *codec; 564 565 codec = w->codec; 566 567 switch (event) { 568 case SND_SOC_DAPM_PRE_PMU: 569 /* Enable the headphone amp */ 570 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 571 WM8995_HPOUT1L_ENA_MASK | 572 WM8995_HPOUT1R_ENA_MASK, 573 WM8995_HPOUT1L_ENA | 574 WM8995_HPOUT1R_ENA); 575 576 /* Enable the second stage */ 577 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 578 WM8995_HPOUT1L_DLY_MASK | 579 WM8995_HPOUT1R_DLY_MASK, 580 WM8995_HPOUT1L_DLY | 581 WM8995_HPOUT1R_DLY); 582 break; 583 case SND_SOC_DAPM_PRE_PMD: 584 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 585 WM8995_CP_ENA_MASK, 0); 586 break; 587 } 588 589 return 0; 590 } 591 592 static void dc_servo_cmd(struct snd_soc_codec *codec, 593 unsigned int reg, unsigned int val, unsigned int mask) 594 { 595 int timeout = 10; 596 597 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", 598 __func__, reg, val, mask); 599 600 snd_soc_write(codec, reg, val); 601 while (timeout--) { 602 msleep(10); 603 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); 604 if ((val & mask) == mask) 605 return; 606 } 607 608 dev_err(codec->dev, "Timed out waiting for DC Servo\n"); 609 } 610 611 static int hp_event(struct snd_soc_dapm_widget *w, 612 struct snd_kcontrol *kcontrol, int event) 613 { 614 struct snd_soc_codec *codec; 615 unsigned int reg; 616 617 codec = w->codec; 618 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); 619 620 switch (event) { 621 case SND_SOC_DAPM_POST_PMU: 622 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 623 WM8995_CP_ENA_MASK, WM8995_CP_ENA); 624 625 msleep(5); 626 627 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 628 WM8995_HPOUT1L_ENA_MASK | 629 WM8995_HPOUT1R_ENA_MASK, 630 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); 631 632 udelay(20); 633 634 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; 635 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 636 637 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | 638 WM8995_DCS_ENA_CHAN_1); 639 640 dc_servo_cmd(codec, WM8995_DC_SERVO_2, 641 WM8995_DCS_TRIG_STARTUP_0 | 642 WM8995_DCS_TRIG_STARTUP_1, 643 WM8995_DCS_TRIG_DAC_WR_0 | 644 WM8995_DCS_TRIG_DAC_WR_1); 645 646 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | 647 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; 648 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 649 650 break; 651 case SND_SOC_DAPM_PRE_PMD: 652 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 653 WM8995_HPOUT1L_OUTP_MASK | 654 WM8995_HPOUT1R_OUTP_MASK | 655 WM8995_HPOUT1L_RMV_SHORT_MASK | 656 WM8995_HPOUT1R_RMV_SHORT_MASK, 0); 657 658 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 659 WM8995_HPOUT1L_DLY_MASK | 660 WM8995_HPOUT1R_DLY_MASK, 0); 661 662 snd_soc_write(codec, WM8995_DC_SERVO_1, 0); 663 664 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 665 WM8995_HPOUT1L_ENA_MASK | 666 WM8995_HPOUT1R_ENA_MASK, 667 0); 668 break; 669 } 670 671 return 0; 672 } 673 674 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 675 { 676 struct wm8995_priv *wm8995; 677 int rate; 678 int reg1 = 0; 679 int offset; 680 681 wm8995 = snd_soc_codec_get_drvdata(codec); 682 683 if (aif) 684 offset = 4; 685 else 686 offset = 0; 687 688 switch (wm8995->sysclk[aif]) { 689 case WM8995_SYSCLK_MCLK1: 690 rate = wm8995->mclk[0]; 691 break; 692 case WM8995_SYSCLK_MCLK2: 693 reg1 |= 0x8; 694 rate = wm8995->mclk[1]; 695 break; 696 case WM8995_SYSCLK_FLL1: 697 reg1 |= 0x10; 698 rate = wm8995->fll[0].out; 699 break; 700 case WM8995_SYSCLK_FLL2: 701 reg1 |= 0x18; 702 rate = wm8995->fll[1].out; 703 break; 704 default: 705 return -EINVAL; 706 } 707 708 if (rate >= 13500000) { 709 rate /= 2; 710 reg1 |= WM8995_AIF1CLK_DIV; 711 712 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 713 aif + 1, rate); 714 } 715 716 wm8995->aifclk[aif] = rate; 717 718 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, 719 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, 720 reg1); 721 return 0; 722 } 723 724 static int configure_clock(struct snd_soc_codec *codec) 725 { 726 struct wm8995_priv *wm8995; 727 int change, new; 728 729 wm8995 = snd_soc_codec_get_drvdata(codec); 730 731 /* Bring up the AIF clocks first */ 732 configure_aif_clock(codec, 0); 733 configure_aif_clock(codec, 1); 734 735 /* 736 * Then switch CLK_SYS over to the higher of them; a change 737 * can only happen as a result of a clocking change which can 738 * only be made outside of DAPM so we can safely redo the 739 * clocking. 740 */ 741 742 /* If they're equal it doesn't matter which is used */ 743 if (wm8995->aifclk[0] == wm8995->aifclk[1]) 744 return 0; 745 746 if (wm8995->aifclk[0] < wm8995->aifclk[1]) 747 new = WM8995_SYSCLK_SRC; 748 else 749 new = 0; 750 751 change = snd_soc_update_bits(codec, WM8995_CLOCKING_1, 752 WM8995_SYSCLK_SRC_MASK, new); 753 if (!change) 754 return 0; 755 756 snd_soc_dapm_sync(&codec->dapm); 757 758 return 0; 759 } 760 761 static int clk_sys_event(struct snd_soc_dapm_widget *w, 762 struct snd_kcontrol *kcontrol, int event) 763 { 764 struct snd_soc_codec *codec; 765 766 codec = w->codec; 767 768 switch (event) { 769 case SND_SOC_DAPM_PRE_PMU: 770 return configure_clock(codec); 771 772 case SND_SOC_DAPM_POST_PMD: 773 configure_clock(codec); 774 break; 775 } 776 777 return 0; 778 } 779 780 static const char *sidetone_text[] = { 781 "ADC/DMIC1", "DMIC2", 782 }; 783 784 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text); 785 786 static const struct snd_kcontrol_new sidetone1_mux = 787 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 788 789 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text); 790 791 static const struct snd_kcontrol_new sidetone2_mux = 792 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 793 794 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 795 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 796 1, 1, 0), 797 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 798 0, 1, 0), 799 }; 800 801 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 802 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 803 1, 1, 0), 804 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 805 0, 1, 0), 806 }; 807 808 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 809 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 810 1, 1, 0), 811 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 812 0, 1, 0), 813 }; 814 815 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 816 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 817 1, 1, 0), 818 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 819 0, 1, 0), 820 }; 821 822 static const struct snd_kcontrol_new dac1l_mix[] = { 823 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 824 5, 1, 0), 825 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 826 4, 1, 0), 827 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 828 2, 1, 0), 829 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 830 1, 1, 0), 831 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 832 0, 1, 0), 833 }; 834 835 static const struct snd_kcontrol_new dac1r_mix[] = { 836 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 837 5, 1, 0), 838 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 839 4, 1, 0), 840 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 841 2, 1, 0), 842 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 843 1, 1, 0), 844 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 845 0, 1, 0), 846 }; 847 848 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 849 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 850 5, 1, 0), 851 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 852 4, 1, 0), 853 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 854 2, 1, 0), 855 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 856 1, 1, 0), 857 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 858 0, 1, 0), 859 }; 860 861 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 862 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 863 5, 1, 0), 864 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 865 4, 1, 0), 866 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 867 2, 1, 0), 868 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 869 1, 1, 0), 870 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 871 0, 1, 0), 872 }; 873 874 static const struct snd_kcontrol_new in1l_pga = 875 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); 876 877 static const struct snd_kcontrol_new in1r_pga = 878 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); 879 880 static const char *adc_mux_text[] = { 881 "ADC", 882 "DMIC", 883 }; 884 885 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 886 887 static const struct snd_kcontrol_new adcl_mux = 888 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 889 890 static const struct snd_kcontrol_new adcr_mux = 891 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 892 893 static const char *spk_src_text[] = { 894 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 895 }; 896 897 static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, 898 0, spk_src_text); 899 static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, 900 0, spk_src_text); 901 static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, 902 0, spk_src_text); 903 static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, 904 0, spk_src_text); 905 906 static const struct snd_kcontrol_new spk1l_mux = 907 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); 908 static const struct snd_kcontrol_new spk1r_mux = 909 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); 910 static const struct snd_kcontrol_new spk2l_mux = 911 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); 912 static const struct snd_kcontrol_new spk2r_mux = 913 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); 914 915 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { 916 SND_SOC_DAPM_INPUT("DMIC1DAT"), 917 SND_SOC_DAPM_INPUT("DMIC2DAT"), 918 919 SND_SOC_DAPM_INPUT("IN1L"), 920 SND_SOC_DAPM_INPUT("IN1R"), 921 922 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, 923 &in1l_pga, 1), 924 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, 925 &in1r_pga, 1), 926 927 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0, 928 NULL, 0), 929 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0, 930 NULL, 0), 931 932 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), 933 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), 934 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), 935 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), 936 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), 937 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 938 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 939 940 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, 941 WM8995_POWER_MANAGEMENT_3, 9, 0), 942 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, 943 WM8995_POWER_MANAGEMENT_3, 8, 0), 944 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, 945 SND_SOC_NOPM, 0, 0), 946 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 947 0, WM8995_POWER_MANAGEMENT_3, 11, 0), 948 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 949 0, WM8995_POWER_MANAGEMENT_3, 10, 0), 950 951 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux), 952 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux), 953 954 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), 955 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), 956 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), 957 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), 958 959 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), 960 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), 961 962 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 963 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 964 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 965 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 966 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 967 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 968 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 969 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 970 971 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 972 9, 0), 973 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 974 8, 0), 975 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 976 0, 0), 977 978 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 979 11, 0), 980 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 981 10, 0), 982 983 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 984 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 985 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 986 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 987 988 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), 989 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), 990 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), 991 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), 992 993 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, 994 ARRAY_SIZE(dac1l_mix)), 995 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, 996 ARRAY_SIZE(dac1r_mix)), 997 998 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 999 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1000 1001 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1002 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1003 1004 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, 1005 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1006 1007 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, 1008 4, 0, &spk1l_mux), 1009 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, 1010 4, 0, &spk1r_mux), 1011 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, 1012 4, 0, &spk2l_mux), 1013 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, 1014 4, 0, &spk2r_mux), 1015 1016 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 1017 1018 SND_SOC_DAPM_OUTPUT("HP1L"), 1019 SND_SOC_DAPM_OUTPUT("HP1R"), 1020 SND_SOC_DAPM_OUTPUT("SPK1L"), 1021 SND_SOC_DAPM_OUTPUT("SPK1R"), 1022 SND_SOC_DAPM_OUTPUT("SPK2L"), 1023 SND_SOC_DAPM_OUTPUT("SPK2R") 1024 }; 1025 1026 static const struct snd_soc_dapm_route wm8995_intercon[] = { 1027 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1028 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1029 1030 { "DSP1CLK", NULL, "CLK_SYS" }, 1031 { "DSP2CLK", NULL, "CLK_SYS" }, 1032 { "SYSDSPCLK", NULL, "CLK_SYS" }, 1033 1034 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1035 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1036 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1037 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1038 { "AIF1ADC1R", NULL, "SYSDSPCLK" }, 1039 1040 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1041 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1042 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1043 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1044 { "AIF1ADC2R", NULL, "SYSDSPCLK" }, 1045 1046 { "DMIC1L", NULL, "DMIC1DAT" }, 1047 { "DMIC1L", NULL, "CLK_SYS" }, 1048 { "DMIC1R", NULL, "DMIC1DAT" }, 1049 { "DMIC1R", NULL, "CLK_SYS" }, 1050 { "DMIC2L", NULL, "DMIC2DAT" }, 1051 { "DMIC2L", NULL, "CLK_SYS" }, 1052 { "DMIC2R", NULL, "DMIC2DAT" }, 1053 { "DMIC2R", NULL, "CLK_SYS" }, 1054 1055 { "ADCL", NULL, "AIF1CLK" }, 1056 { "ADCL", NULL, "DSP1CLK" }, 1057 { "ADCL", NULL, "SYSDSPCLK" }, 1058 1059 { "ADCR", NULL, "AIF1CLK" }, 1060 { "ADCR", NULL, "DSP1CLK" }, 1061 { "ADCR", NULL, "SYSDSPCLK" }, 1062 1063 { "IN1L PGA", "IN1L Switch", "IN1L" }, 1064 { "IN1R PGA", "IN1R Switch", "IN1R" }, 1065 { "IN1L PGA", NULL, "LDO2" }, 1066 { "IN1R PGA", NULL, "LDO2" }, 1067 1068 { "ADCL", NULL, "IN1L PGA" }, 1069 { "ADCR", NULL, "IN1R PGA" }, 1070 1071 { "ADCL Mux", "ADC", "ADCL" }, 1072 { "ADCL Mux", "DMIC", "DMIC1L" }, 1073 { "ADCR Mux", "ADC", "ADCR" }, 1074 { "ADCR Mux", "DMIC", "DMIC1R" }, 1075 1076 /* AIF1 outputs */ 1077 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1078 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1079 1080 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1081 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1082 1083 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1084 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1085 1086 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1087 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1088 1089 /* Sidetone */ 1090 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, 1091 { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, 1092 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, 1093 { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, 1094 1095 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1096 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1097 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1098 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1099 { "AIF1DAC1R", NULL, "SYSDSPCLK" }, 1100 1101 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1102 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1103 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1104 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1105 { "AIF1DAC2R", NULL, "SYSDSPCLK" }, 1106 1107 { "DAC1L", NULL, "AIF1CLK" }, 1108 { "DAC1L", NULL, "DSP1CLK" }, 1109 { "DAC1L", NULL, "SYSDSPCLK" }, 1110 1111 { "DAC1R", NULL, "AIF1CLK" }, 1112 { "DAC1R", NULL, "DSP1CLK" }, 1113 { "DAC1R", NULL, "SYSDSPCLK" }, 1114 1115 { "AIF1DAC1L", NULL, "AIF1DACDAT" }, 1116 { "AIF1DAC1R", NULL, "AIF1DACDAT" }, 1117 { "AIF1DAC2L", NULL, "AIF1DACDAT" }, 1118 { "AIF1DAC2R", NULL, "AIF1DACDAT" }, 1119 1120 /* DAC1 inputs */ 1121 { "DAC1L", NULL, "DAC1L Mixer" }, 1122 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1123 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1124 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1125 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1126 1127 { "DAC1R", NULL, "DAC1R Mixer" }, 1128 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1129 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1130 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1131 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1132 1133 /* DAC2/AIF2 outputs */ 1134 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1135 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1136 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1137 1138 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1139 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1140 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1141 1142 /* Output stages */ 1143 { "Headphone PGA", NULL, "DAC1L" }, 1144 { "Headphone PGA", NULL, "DAC1R" }, 1145 1146 { "Headphone PGA", NULL, "DAC2L" }, 1147 { "Headphone PGA", NULL, "DAC2R" }, 1148 1149 { "Headphone PGA", NULL, "Headphone Supply" }, 1150 { "Headphone PGA", NULL, "CLK_SYS" }, 1151 { "Headphone PGA", NULL, "LDO2" }, 1152 1153 { "HP1L", NULL, "Headphone PGA" }, 1154 { "HP1R", NULL, "Headphone PGA" }, 1155 1156 { "SPK1L Driver", "DAC1L", "DAC1L" }, 1157 { "SPK1L Driver", "DAC1R", "DAC1R" }, 1158 { "SPK1L Driver", "DAC2L", "DAC2L" }, 1159 { "SPK1L Driver", "DAC2R", "DAC2R" }, 1160 { "SPK1L Driver", NULL, "CLK_SYS" }, 1161 1162 { "SPK1R Driver", "DAC1L", "DAC1L" }, 1163 { "SPK1R Driver", "DAC1R", "DAC1R" }, 1164 { "SPK1R Driver", "DAC2L", "DAC2L" }, 1165 { "SPK1R Driver", "DAC2R", "DAC2R" }, 1166 { "SPK1R Driver", NULL, "CLK_SYS" }, 1167 1168 { "SPK2L Driver", "DAC1L", "DAC1L" }, 1169 { "SPK2L Driver", "DAC1R", "DAC1R" }, 1170 { "SPK2L Driver", "DAC2L", "DAC2L" }, 1171 { "SPK2L Driver", "DAC2R", "DAC2R" }, 1172 { "SPK2L Driver", NULL, "CLK_SYS" }, 1173 1174 { "SPK2R Driver", "DAC1L", "DAC1L" }, 1175 { "SPK2R Driver", "DAC1R", "DAC1R" }, 1176 { "SPK2R Driver", "DAC2L", "DAC2L" }, 1177 { "SPK2R Driver", "DAC2R", "DAC2R" }, 1178 { "SPK2R Driver", NULL, "CLK_SYS" }, 1179 1180 { "SPK1L", NULL, "SPK1L Driver" }, 1181 { "SPK1R", NULL, "SPK1R Driver" }, 1182 { "SPK2L", NULL, "SPK2L Driver" }, 1183 { "SPK2R", NULL, "SPK2R Driver" } 1184 }; 1185 1186 static bool wm8995_readable(struct device *dev, unsigned int reg) 1187 { 1188 switch (reg) { 1189 case WM8995_SOFTWARE_RESET: 1190 case WM8995_POWER_MANAGEMENT_1: 1191 case WM8995_POWER_MANAGEMENT_2: 1192 case WM8995_POWER_MANAGEMENT_3: 1193 case WM8995_POWER_MANAGEMENT_4: 1194 case WM8995_POWER_MANAGEMENT_5: 1195 case WM8995_LEFT_LINE_INPUT_1_VOLUME: 1196 case WM8995_RIGHT_LINE_INPUT_1_VOLUME: 1197 case WM8995_LEFT_LINE_INPUT_CONTROL: 1198 case WM8995_DAC1_LEFT_VOLUME: 1199 case WM8995_DAC1_RIGHT_VOLUME: 1200 case WM8995_DAC2_LEFT_VOLUME: 1201 case WM8995_DAC2_RIGHT_VOLUME: 1202 case WM8995_OUTPUT_VOLUME_ZC_1: 1203 case WM8995_MICBIAS_1: 1204 case WM8995_MICBIAS_2: 1205 case WM8995_LDO_1: 1206 case WM8995_LDO_2: 1207 case WM8995_ACCESSORY_DETECT_MODE1: 1208 case WM8995_ACCESSORY_DETECT_MODE2: 1209 case WM8995_HEADPHONE_DETECT1: 1210 case WM8995_HEADPHONE_DETECT2: 1211 case WM8995_MIC_DETECT_1: 1212 case WM8995_MIC_DETECT_2: 1213 case WM8995_CHARGE_PUMP_1: 1214 case WM8995_CLASS_W_1: 1215 case WM8995_DC_SERVO_1: 1216 case WM8995_DC_SERVO_2: 1217 case WM8995_DC_SERVO_3: 1218 case WM8995_DC_SERVO_5: 1219 case WM8995_DC_SERVO_6: 1220 case WM8995_DC_SERVO_7: 1221 case WM8995_DC_SERVO_READBACK_0: 1222 case WM8995_ANALOGUE_HP_1: 1223 case WM8995_ANALOGUE_HP_2: 1224 case WM8995_CHIP_REVISION: 1225 case WM8995_CONTROL_INTERFACE_1: 1226 case WM8995_CONTROL_INTERFACE_2: 1227 case WM8995_WRITE_SEQUENCER_CTRL_1: 1228 case WM8995_WRITE_SEQUENCER_CTRL_2: 1229 case WM8995_AIF1_CLOCKING_1: 1230 case WM8995_AIF1_CLOCKING_2: 1231 case WM8995_AIF2_CLOCKING_1: 1232 case WM8995_AIF2_CLOCKING_2: 1233 case WM8995_CLOCKING_1: 1234 case WM8995_CLOCKING_2: 1235 case WM8995_AIF1_RATE: 1236 case WM8995_AIF2_RATE: 1237 case WM8995_RATE_STATUS: 1238 case WM8995_FLL1_CONTROL_1: 1239 case WM8995_FLL1_CONTROL_2: 1240 case WM8995_FLL1_CONTROL_3: 1241 case WM8995_FLL1_CONTROL_4: 1242 case WM8995_FLL1_CONTROL_5: 1243 case WM8995_FLL2_CONTROL_1: 1244 case WM8995_FLL2_CONTROL_2: 1245 case WM8995_FLL2_CONTROL_3: 1246 case WM8995_FLL2_CONTROL_4: 1247 case WM8995_FLL2_CONTROL_5: 1248 case WM8995_AIF1_CONTROL_1: 1249 case WM8995_AIF1_CONTROL_2: 1250 case WM8995_AIF1_MASTER_SLAVE: 1251 case WM8995_AIF1_BCLK: 1252 case WM8995_AIF1ADC_LRCLK: 1253 case WM8995_AIF1DAC_LRCLK: 1254 case WM8995_AIF1DAC_DATA: 1255 case WM8995_AIF1ADC_DATA: 1256 case WM8995_AIF2_CONTROL_1: 1257 case WM8995_AIF2_CONTROL_2: 1258 case WM8995_AIF2_MASTER_SLAVE: 1259 case WM8995_AIF2_BCLK: 1260 case WM8995_AIF2ADC_LRCLK: 1261 case WM8995_AIF2DAC_LRCLK: 1262 case WM8995_AIF2DAC_DATA: 1263 case WM8995_AIF2ADC_DATA: 1264 case WM8995_AIF1_ADC1_LEFT_VOLUME: 1265 case WM8995_AIF1_ADC1_RIGHT_VOLUME: 1266 case WM8995_AIF1_DAC1_LEFT_VOLUME: 1267 case WM8995_AIF1_DAC1_RIGHT_VOLUME: 1268 case WM8995_AIF1_ADC2_LEFT_VOLUME: 1269 case WM8995_AIF1_ADC2_RIGHT_VOLUME: 1270 case WM8995_AIF1_DAC2_LEFT_VOLUME: 1271 case WM8995_AIF1_DAC2_RIGHT_VOLUME: 1272 case WM8995_AIF1_ADC1_FILTERS: 1273 case WM8995_AIF1_ADC2_FILTERS: 1274 case WM8995_AIF1_DAC1_FILTERS_1: 1275 case WM8995_AIF1_DAC1_FILTERS_2: 1276 case WM8995_AIF1_DAC2_FILTERS_1: 1277 case WM8995_AIF1_DAC2_FILTERS_2: 1278 case WM8995_AIF1_DRC1_1: 1279 case WM8995_AIF1_DRC1_2: 1280 case WM8995_AIF1_DRC1_3: 1281 case WM8995_AIF1_DRC1_4: 1282 case WM8995_AIF1_DRC1_5: 1283 case WM8995_AIF1_DRC2_1: 1284 case WM8995_AIF1_DRC2_2: 1285 case WM8995_AIF1_DRC2_3: 1286 case WM8995_AIF1_DRC2_4: 1287 case WM8995_AIF1_DRC2_5: 1288 case WM8995_AIF1_DAC1_EQ_GAINS_1: 1289 case WM8995_AIF1_DAC1_EQ_GAINS_2: 1290 case WM8995_AIF1_DAC1_EQ_BAND_1_A: 1291 case WM8995_AIF1_DAC1_EQ_BAND_1_B: 1292 case WM8995_AIF1_DAC1_EQ_BAND_1_PG: 1293 case WM8995_AIF1_DAC1_EQ_BAND_2_A: 1294 case WM8995_AIF1_DAC1_EQ_BAND_2_B: 1295 case WM8995_AIF1_DAC1_EQ_BAND_2_C: 1296 case WM8995_AIF1_DAC1_EQ_BAND_2_PG: 1297 case WM8995_AIF1_DAC1_EQ_BAND_3_A: 1298 case WM8995_AIF1_DAC1_EQ_BAND_3_B: 1299 case WM8995_AIF1_DAC1_EQ_BAND_3_C: 1300 case WM8995_AIF1_DAC1_EQ_BAND_3_PG: 1301 case WM8995_AIF1_DAC1_EQ_BAND_4_A: 1302 case WM8995_AIF1_DAC1_EQ_BAND_4_B: 1303 case WM8995_AIF1_DAC1_EQ_BAND_4_C: 1304 case WM8995_AIF1_DAC1_EQ_BAND_4_PG: 1305 case WM8995_AIF1_DAC1_EQ_BAND_5_A: 1306 case WM8995_AIF1_DAC1_EQ_BAND_5_B: 1307 case WM8995_AIF1_DAC1_EQ_BAND_5_PG: 1308 case WM8995_AIF1_DAC2_EQ_GAINS_1: 1309 case WM8995_AIF1_DAC2_EQ_GAINS_2: 1310 case WM8995_AIF1_DAC2_EQ_BAND_1_A: 1311 case WM8995_AIF1_DAC2_EQ_BAND_1_B: 1312 case WM8995_AIF1_DAC2_EQ_BAND_1_PG: 1313 case WM8995_AIF1_DAC2_EQ_BAND_2_A: 1314 case WM8995_AIF1_DAC2_EQ_BAND_2_B: 1315 case WM8995_AIF1_DAC2_EQ_BAND_2_C: 1316 case WM8995_AIF1_DAC2_EQ_BAND_2_PG: 1317 case WM8995_AIF1_DAC2_EQ_BAND_3_A: 1318 case WM8995_AIF1_DAC2_EQ_BAND_3_B: 1319 case WM8995_AIF1_DAC2_EQ_BAND_3_C: 1320 case WM8995_AIF1_DAC2_EQ_BAND_3_PG: 1321 case WM8995_AIF1_DAC2_EQ_BAND_4_A: 1322 case WM8995_AIF1_DAC2_EQ_BAND_4_B: 1323 case WM8995_AIF1_DAC2_EQ_BAND_4_C: 1324 case WM8995_AIF1_DAC2_EQ_BAND_4_PG: 1325 case WM8995_AIF1_DAC2_EQ_BAND_5_A: 1326 case WM8995_AIF1_DAC2_EQ_BAND_5_B: 1327 case WM8995_AIF1_DAC2_EQ_BAND_5_PG: 1328 case WM8995_AIF2_ADC_LEFT_VOLUME: 1329 case WM8995_AIF2_ADC_RIGHT_VOLUME: 1330 case WM8995_AIF2_DAC_LEFT_VOLUME: 1331 case WM8995_AIF2_DAC_RIGHT_VOLUME: 1332 case WM8995_AIF2_ADC_FILTERS: 1333 case WM8995_AIF2_DAC_FILTERS_1: 1334 case WM8995_AIF2_DAC_FILTERS_2: 1335 case WM8995_AIF2_DRC_1: 1336 case WM8995_AIF2_DRC_2: 1337 case WM8995_AIF2_DRC_3: 1338 case WM8995_AIF2_DRC_4: 1339 case WM8995_AIF2_DRC_5: 1340 case WM8995_AIF2_EQ_GAINS_1: 1341 case WM8995_AIF2_EQ_GAINS_2: 1342 case WM8995_AIF2_EQ_BAND_1_A: 1343 case WM8995_AIF2_EQ_BAND_1_B: 1344 case WM8995_AIF2_EQ_BAND_1_PG: 1345 case WM8995_AIF2_EQ_BAND_2_A: 1346 case WM8995_AIF2_EQ_BAND_2_B: 1347 case WM8995_AIF2_EQ_BAND_2_C: 1348 case WM8995_AIF2_EQ_BAND_2_PG: 1349 case WM8995_AIF2_EQ_BAND_3_A: 1350 case WM8995_AIF2_EQ_BAND_3_B: 1351 case WM8995_AIF2_EQ_BAND_3_C: 1352 case WM8995_AIF2_EQ_BAND_3_PG: 1353 case WM8995_AIF2_EQ_BAND_4_A: 1354 case WM8995_AIF2_EQ_BAND_4_B: 1355 case WM8995_AIF2_EQ_BAND_4_C: 1356 case WM8995_AIF2_EQ_BAND_4_PG: 1357 case WM8995_AIF2_EQ_BAND_5_A: 1358 case WM8995_AIF2_EQ_BAND_5_B: 1359 case WM8995_AIF2_EQ_BAND_5_PG: 1360 case WM8995_DAC1_MIXER_VOLUMES: 1361 case WM8995_DAC1_LEFT_MIXER_ROUTING: 1362 case WM8995_DAC1_RIGHT_MIXER_ROUTING: 1363 case WM8995_DAC2_MIXER_VOLUMES: 1364 case WM8995_DAC2_LEFT_MIXER_ROUTING: 1365 case WM8995_DAC2_RIGHT_MIXER_ROUTING: 1366 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING: 1367 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING: 1368 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING: 1369 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING: 1370 case WM8995_DAC_SOFTMUTE: 1371 case WM8995_OVERSAMPLING: 1372 case WM8995_SIDETONE: 1373 case WM8995_GPIO_1: 1374 case WM8995_GPIO_2: 1375 case WM8995_GPIO_3: 1376 case WM8995_GPIO_4: 1377 case WM8995_GPIO_5: 1378 case WM8995_GPIO_6: 1379 case WM8995_GPIO_7: 1380 case WM8995_GPIO_8: 1381 case WM8995_GPIO_9: 1382 case WM8995_GPIO_10: 1383 case WM8995_GPIO_11: 1384 case WM8995_GPIO_12: 1385 case WM8995_GPIO_13: 1386 case WM8995_GPIO_14: 1387 case WM8995_PULL_CONTROL_1: 1388 case WM8995_PULL_CONTROL_2: 1389 case WM8995_INTERRUPT_STATUS_1: 1390 case WM8995_INTERRUPT_STATUS_2: 1391 case WM8995_INTERRUPT_RAW_STATUS_2: 1392 case WM8995_INTERRUPT_STATUS_1_MASK: 1393 case WM8995_INTERRUPT_STATUS_2_MASK: 1394 case WM8995_INTERRUPT_CONTROL: 1395 case WM8995_LEFT_PDM_SPEAKER_1: 1396 case WM8995_RIGHT_PDM_SPEAKER_1: 1397 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE: 1398 case WM8995_LEFT_PDM_SPEAKER_2: 1399 case WM8995_RIGHT_PDM_SPEAKER_2: 1400 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE: 1401 return true; 1402 default: 1403 return false; 1404 } 1405 } 1406 1407 static bool wm8995_volatile(struct device *dev, unsigned int reg) 1408 { 1409 switch (reg) { 1410 case WM8995_SOFTWARE_RESET: 1411 case WM8995_DC_SERVO_READBACK_0: 1412 case WM8995_INTERRUPT_STATUS_1: 1413 case WM8995_INTERRUPT_STATUS_2: 1414 case WM8995_INTERRUPT_CONTROL: 1415 case WM8995_ACCESSORY_DETECT_MODE1: 1416 case WM8995_ACCESSORY_DETECT_MODE2: 1417 case WM8995_HEADPHONE_DETECT1: 1418 case WM8995_HEADPHONE_DETECT2: 1419 case WM8995_RATE_STATUS: 1420 return true; 1421 default: 1422 return false; 1423 } 1424 } 1425 1426 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) 1427 { 1428 struct snd_soc_codec *codec = dai->codec; 1429 int mute_reg; 1430 1431 switch (dai->id) { 1432 case 0: 1433 mute_reg = WM8995_AIF1_DAC1_FILTERS_1; 1434 break; 1435 case 1: 1436 mute_reg = WM8995_AIF2_DAC_FILTERS_1; 1437 break; 1438 default: 1439 return -EINVAL; 1440 } 1441 1442 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, 1443 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); 1444 return 0; 1445 } 1446 1447 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1448 { 1449 struct snd_soc_codec *codec; 1450 int master; 1451 int aif; 1452 1453 codec = dai->codec; 1454 1455 master = 0; 1456 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1457 case SND_SOC_DAIFMT_CBS_CFS: 1458 break; 1459 case SND_SOC_DAIFMT_CBM_CFM: 1460 master = WM8995_AIF1_MSTR; 1461 break; 1462 default: 1463 dev_err(dai->dev, "Unknown master/slave configuration\n"); 1464 return -EINVAL; 1465 } 1466 1467 aif = 0; 1468 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1469 case SND_SOC_DAIFMT_DSP_B: 1470 aif |= WM8995_AIF1_LRCLK_INV; 1471 case SND_SOC_DAIFMT_DSP_A: 1472 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); 1473 break; 1474 case SND_SOC_DAIFMT_I2S: 1475 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); 1476 break; 1477 case SND_SOC_DAIFMT_RIGHT_J: 1478 break; 1479 case SND_SOC_DAIFMT_LEFT_J: 1480 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); 1481 break; 1482 default: 1483 dev_err(dai->dev, "Unknown dai format\n"); 1484 return -EINVAL; 1485 } 1486 1487 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1488 case SND_SOC_DAIFMT_DSP_A: 1489 case SND_SOC_DAIFMT_DSP_B: 1490 /* frame inversion not valid for DSP modes */ 1491 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1492 case SND_SOC_DAIFMT_NB_NF: 1493 break; 1494 case SND_SOC_DAIFMT_IB_NF: 1495 aif |= WM8995_AIF1_BCLK_INV; 1496 break; 1497 default: 1498 return -EINVAL; 1499 } 1500 break; 1501 1502 case SND_SOC_DAIFMT_I2S: 1503 case SND_SOC_DAIFMT_RIGHT_J: 1504 case SND_SOC_DAIFMT_LEFT_J: 1505 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1506 case SND_SOC_DAIFMT_NB_NF: 1507 break; 1508 case SND_SOC_DAIFMT_IB_IF: 1509 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; 1510 break; 1511 case SND_SOC_DAIFMT_IB_NF: 1512 aif |= WM8995_AIF1_BCLK_INV; 1513 break; 1514 case SND_SOC_DAIFMT_NB_IF: 1515 aif |= WM8995_AIF1_LRCLK_INV; 1516 break; 1517 default: 1518 return -EINVAL; 1519 } 1520 break; 1521 default: 1522 return -EINVAL; 1523 } 1524 1525 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, 1526 WM8995_AIF1_BCLK_INV_MASK | 1527 WM8995_AIF1_LRCLK_INV_MASK | 1528 WM8995_AIF1_FMT_MASK, aif); 1529 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, 1530 WM8995_AIF1_MSTR_MASK, master); 1531 return 0; 1532 } 1533 1534 static const int srs[] = { 1535 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 1536 48000, 88200, 96000 1537 }; 1538 1539 static const int fs_ratios[] = { 1540 -1 /* reserved */, 1541 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 1542 }; 1543 1544 static const int bclk_divs[] = { 1545 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 1546 }; 1547 1548 static int wm8995_hw_params(struct snd_pcm_substream *substream, 1549 struct snd_pcm_hw_params *params, 1550 struct snd_soc_dai *dai) 1551 { 1552 struct snd_soc_codec *codec; 1553 struct wm8995_priv *wm8995; 1554 int aif1_reg; 1555 int bclk_reg; 1556 int lrclk_reg; 1557 int rate_reg; 1558 int bclk_rate; 1559 int aif1; 1560 int lrclk, bclk; 1561 int i, rate_val, best, best_val, cur_val; 1562 1563 codec = dai->codec; 1564 wm8995 = snd_soc_codec_get_drvdata(codec); 1565 1566 switch (dai->id) { 1567 case 0: 1568 aif1_reg = WM8995_AIF1_CONTROL_1; 1569 bclk_reg = WM8995_AIF1_BCLK; 1570 rate_reg = WM8995_AIF1_RATE; 1571 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1572 wm8995->lrclk_shared[0] */) { 1573 lrclk_reg = WM8995_AIF1DAC_LRCLK; 1574 } else { 1575 lrclk_reg = WM8995_AIF1ADC_LRCLK; 1576 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 1577 } 1578 break; 1579 case 1: 1580 aif1_reg = WM8995_AIF2_CONTROL_1; 1581 bclk_reg = WM8995_AIF2_BCLK; 1582 rate_reg = WM8995_AIF2_RATE; 1583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1584 wm8995->lrclk_shared[1] */) { 1585 lrclk_reg = WM8995_AIF2DAC_LRCLK; 1586 } else { 1587 lrclk_reg = WM8995_AIF2ADC_LRCLK; 1588 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 1589 } 1590 break; 1591 default: 1592 return -EINVAL; 1593 } 1594 1595 bclk_rate = snd_soc_params_to_bclk(params); 1596 if (bclk_rate < 0) 1597 return bclk_rate; 1598 1599 aif1 = 0; 1600 switch (params_width(params)) { 1601 case 16: 1602 break; 1603 case 20: 1604 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); 1605 break; 1606 case 24: 1607 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); 1608 break; 1609 case 32: 1610 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); 1611 break; 1612 default: 1613 dev_err(dai->dev, "Unsupported word length %u\n", 1614 params_width(params)); 1615 return -EINVAL; 1616 } 1617 1618 /* try to find a suitable sample rate */ 1619 for (i = 0; i < ARRAY_SIZE(srs); ++i) 1620 if (srs[i] == params_rate(params)) 1621 break; 1622 if (i == ARRAY_SIZE(srs)) { 1623 dev_err(dai->dev, "Sample rate %d is not supported\n", 1624 params_rate(params)); 1625 return -EINVAL; 1626 } 1627 rate_val = i << WM8995_AIF1_SR_SHIFT; 1628 1629 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); 1630 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 1631 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); 1632 1633 /* AIFCLK/fs ratio; look for a close match in either direction */ 1634 best = 1; 1635 best_val = abs((fs_ratios[1] * params_rate(params)) 1636 - wm8995->aifclk[dai->id]); 1637 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { 1638 cur_val = abs((fs_ratios[i] * params_rate(params)) 1639 - wm8995->aifclk[dai->id]); 1640 if (cur_val >= best_val) 1641 continue; 1642 best = i; 1643 best_val = cur_val; 1644 } 1645 rate_val |= best; 1646 1647 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 1648 dai->id + 1, fs_ratios[best]); 1649 1650 /* 1651 * We may not get quite the right frequency if using 1652 * approximate clocks so look for the closest match that is 1653 * higher than the target (we need to ensure that there enough 1654 * BCLKs to clock out the samples). 1655 */ 1656 best = 0; 1657 bclk = 0; 1658 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1659 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; 1660 if (cur_val < 0) /* BCLK table is sorted */ 1661 break; 1662 best = i; 1663 } 1664 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; 1665 1666 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; 1667 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1668 bclk_divs[best], bclk_rate); 1669 1670 lrclk = bclk_rate / params_rate(params); 1671 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1672 lrclk, bclk_rate / lrclk); 1673 1674 snd_soc_update_bits(codec, aif1_reg, 1675 WM8995_AIF1_WL_MASK, aif1); 1676 snd_soc_update_bits(codec, bclk_reg, 1677 WM8995_AIF1_BCLK_DIV_MASK, bclk); 1678 snd_soc_update_bits(codec, lrclk_reg, 1679 WM8995_AIF1DAC_RATE_MASK, lrclk); 1680 snd_soc_update_bits(codec, rate_reg, 1681 WM8995_AIF1_SR_MASK | 1682 WM8995_AIF1CLK_RATE_MASK, rate_val); 1683 return 0; 1684 } 1685 1686 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 1687 { 1688 struct snd_soc_codec *codec = codec_dai->codec; 1689 int reg, val, mask; 1690 1691 switch (codec_dai->id) { 1692 case 0: 1693 reg = WM8995_AIF1_MASTER_SLAVE; 1694 mask = WM8995_AIF1_TRI; 1695 break; 1696 case 1: 1697 reg = WM8995_AIF2_MASTER_SLAVE; 1698 mask = WM8995_AIF2_TRI; 1699 break; 1700 case 2: 1701 reg = WM8995_POWER_MANAGEMENT_5; 1702 mask = WM8995_AIF3_TRI; 1703 break; 1704 default: 1705 return -EINVAL; 1706 } 1707 1708 if (tristate) 1709 val = mask; 1710 else 1711 val = 0; 1712 1713 return snd_soc_update_bits(codec, reg, mask, val); 1714 } 1715 1716 /* The size in bits of the FLL divide multiplied by 10 1717 * to allow rounding later */ 1718 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1719 1720 struct fll_div { 1721 u16 outdiv; 1722 u16 n; 1723 u16 k; 1724 u16 clk_ref_div; 1725 u16 fll_fratio; 1726 }; 1727 1728 static int wm8995_get_fll_config(struct fll_div *fll, 1729 int freq_in, int freq_out) 1730 { 1731 u64 Kpart; 1732 unsigned int K, Ndiv, Nmod; 1733 1734 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1735 1736 /* Scale the input frequency down to <= 13.5MHz */ 1737 fll->clk_ref_div = 0; 1738 while (freq_in > 13500000) { 1739 fll->clk_ref_div++; 1740 freq_in /= 2; 1741 1742 if (fll->clk_ref_div > 3) 1743 return -EINVAL; 1744 } 1745 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1746 1747 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1748 fll->outdiv = 3; 1749 while (freq_out * (fll->outdiv + 1) < 90000000) { 1750 fll->outdiv++; 1751 if (fll->outdiv > 63) 1752 return -EINVAL; 1753 } 1754 freq_out *= fll->outdiv + 1; 1755 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1756 1757 if (freq_in > 1000000) { 1758 fll->fll_fratio = 0; 1759 } else if (freq_in > 256000) { 1760 fll->fll_fratio = 1; 1761 freq_in *= 2; 1762 } else if (freq_in > 128000) { 1763 fll->fll_fratio = 2; 1764 freq_in *= 4; 1765 } else if (freq_in > 64000) { 1766 fll->fll_fratio = 3; 1767 freq_in *= 8; 1768 } else { 1769 fll->fll_fratio = 4; 1770 freq_in *= 16; 1771 } 1772 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1773 1774 /* Now, calculate N.K */ 1775 Ndiv = freq_out / freq_in; 1776 1777 fll->n = Ndiv; 1778 Nmod = freq_out % freq_in; 1779 pr_debug("Nmod=%d\n", Nmod); 1780 1781 /* Calculate fractional part - scale up so we can round. */ 1782 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1783 1784 do_div(Kpart, freq_in); 1785 1786 K = Kpart & 0xFFFFFFFF; 1787 1788 if ((K % 10) >= 5) 1789 K += 5; 1790 1791 /* Move down to proper range now rounding is done */ 1792 fll->k = K / 10; 1793 1794 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1795 1796 return 0; 1797 } 1798 1799 static int wm8995_set_fll(struct snd_soc_dai *dai, int id, 1800 int src, unsigned int freq_in, 1801 unsigned int freq_out) 1802 { 1803 struct snd_soc_codec *codec; 1804 struct wm8995_priv *wm8995; 1805 int reg_offset, ret; 1806 struct fll_div fll; 1807 u16 reg, aif1, aif2; 1808 1809 codec = dai->codec; 1810 wm8995 = snd_soc_codec_get_drvdata(codec); 1811 1812 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) 1813 & WM8995_AIF1CLK_ENA; 1814 1815 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) 1816 & WM8995_AIF2CLK_ENA; 1817 1818 switch (id) { 1819 case WM8995_FLL1: 1820 reg_offset = 0; 1821 id = 0; 1822 break; 1823 case WM8995_FLL2: 1824 reg_offset = 0x20; 1825 id = 1; 1826 break; 1827 default: 1828 return -EINVAL; 1829 } 1830 1831 switch (src) { 1832 case 0: 1833 /* Allow no source specification when stopping */ 1834 if (freq_out) 1835 return -EINVAL; 1836 break; 1837 case WM8995_FLL_SRC_MCLK1: 1838 case WM8995_FLL_SRC_MCLK2: 1839 case WM8995_FLL_SRC_LRCLK: 1840 case WM8995_FLL_SRC_BCLK: 1841 break; 1842 default: 1843 return -EINVAL; 1844 } 1845 1846 /* Are we changing anything? */ 1847 if (wm8995->fll[id].src == src && 1848 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) 1849 return 0; 1850 1851 /* If we're stopping the FLL redo the old config - no 1852 * registers will actually be written but we avoid GCC flow 1853 * analysis bugs spewing warnings. 1854 */ 1855 if (freq_out) 1856 ret = wm8995_get_fll_config(&fll, freq_in, freq_out); 1857 else 1858 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, 1859 wm8995->fll[id].out); 1860 if (ret < 0) 1861 return ret; 1862 1863 /* Gate the AIF clocks while we reclock */ 1864 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1865 WM8995_AIF1CLK_ENA_MASK, 0); 1866 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1867 WM8995_AIF2CLK_ENA_MASK, 0); 1868 1869 /* We always need to disable the FLL while reconfiguring */ 1870 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1871 WM8995_FLL1_ENA_MASK, 0); 1872 1873 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | 1874 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); 1875 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, 1876 WM8995_FLL1_OUTDIV_MASK | 1877 WM8995_FLL1_FRATIO_MASK, reg); 1878 1879 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); 1880 1881 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, 1882 WM8995_FLL1_N_MASK, 1883 fll.n << WM8995_FLL1_N_SHIFT); 1884 1885 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, 1886 WM8995_FLL1_REFCLK_DIV_MASK | 1887 WM8995_FLL1_REFCLK_SRC_MASK, 1888 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | 1889 (src - 1)); 1890 1891 if (freq_out) 1892 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1893 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); 1894 1895 wm8995->fll[id].in = freq_in; 1896 wm8995->fll[id].out = freq_out; 1897 wm8995->fll[id].src = src; 1898 1899 /* Enable any gated AIF clocks */ 1900 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1901 WM8995_AIF1CLK_ENA_MASK, aif1); 1902 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1903 WM8995_AIF2CLK_ENA_MASK, aif2); 1904 1905 configure_clock(codec); 1906 1907 return 0; 1908 } 1909 1910 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, 1911 int clk_id, unsigned int freq, int dir) 1912 { 1913 struct snd_soc_codec *codec; 1914 struct wm8995_priv *wm8995; 1915 1916 codec = dai->codec; 1917 wm8995 = snd_soc_codec_get_drvdata(codec); 1918 1919 switch (dai->id) { 1920 case 0: 1921 case 1: 1922 break; 1923 default: 1924 /* AIF3 shares clocking with AIF1/2 */ 1925 return -EINVAL; 1926 } 1927 1928 switch (clk_id) { 1929 case WM8995_SYSCLK_MCLK1: 1930 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1931 wm8995->mclk[0] = freq; 1932 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 1933 dai->id + 1, freq); 1934 break; 1935 case WM8995_SYSCLK_MCLK2: 1936 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1937 wm8995->mclk[1] = freq; 1938 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 1939 dai->id + 1, freq); 1940 break; 1941 case WM8995_SYSCLK_FLL1: 1942 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; 1943 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); 1944 break; 1945 case WM8995_SYSCLK_FLL2: 1946 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; 1947 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); 1948 break; 1949 case WM8995_SYSCLK_OPCLK: 1950 default: 1951 dev_err(dai->dev, "Unknown clock source %d\n", clk_id); 1952 return -EINVAL; 1953 } 1954 1955 configure_clock(codec); 1956 1957 return 0; 1958 } 1959 1960 static int wm8995_set_bias_level(struct snd_soc_codec *codec, 1961 enum snd_soc_bias_level level) 1962 { 1963 struct wm8995_priv *wm8995; 1964 int ret; 1965 1966 wm8995 = snd_soc_codec_get_drvdata(codec); 1967 switch (level) { 1968 case SND_SOC_BIAS_ON: 1969 case SND_SOC_BIAS_PREPARE: 1970 break; 1971 case SND_SOC_BIAS_STANDBY: 1972 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1973 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 1974 wm8995->supplies); 1975 if (ret) 1976 return ret; 1977 1978 ret = regcache_sync(wm8995->regmap); 1979 if (ret) { 1980 dev_err(codec->dev, 1981 "Failed to sync cache: %d\n", ret); 1982 return ret; 1983 } 1984 1985 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1986 WM8995_BG_ENA_MASK, WM8995_BG_ENA); 1987 } 1988 break; 1989 case SND_SOC_BIAS_OFF: 1990 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1991 WM8995_BG_ENA_MASK, 0); 1992 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), 1993 wm8995->supplies); 1994 break; 1995 } 1996 1997 codec->dapm.bias_level = level; 1998 return 0; 1999 } 2000 2001 static int wm8995_remove(struct snd_soc_codec *codec) 2002 { 2003 struct wm8995_priv *wm8995; 2004 int i; 2005 2006 wm8995 = snd_soc_codec_get_drvdata(codec); 2007 2008 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i) 2009 regulator_unregister_notifier(wm8995->supplies[i].consumer, 2010 &wm8995->disable_nb[i]); 2011 2012 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2013 return 0; 2014 } 2015 2016 static int wm8995_probe(struct snd_soc_codec *codec) 2017 { 2018 struct wm8995_priv *wm8995; 2019 int i; 2020 int ret; 2021 2022 wm8995 = snd_soc_codec_get_drvdata(codec); 2023 wm8995->codec = codec; 2024 2025 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) 2026 wm8995->supplies[i].supply = wm8995_supply_names[i]; 2027 2028 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies), 2029 wm8995->supplies); 2030 if (ret) { 2031 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2032 return ret; 2033 } 2034 2035 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; 2036 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; 2037 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; 2038 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; 2039 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; 2040 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; 2041 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; 2042 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; 2043 2044 /* This should really be moved into the regulator core */ 2045 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { 2046 ret = regulator_register_notifier(wm8995->supplies[i].consumer, 2047 &wm8995->disable_nb[i]); 2048 if (ret) { 2049 dev_err(codec->dev, 2050 "Failed to register regulator notifier: %d\n", 2051 ret); 2052 } 2053 } 2054 2055 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 2056 wm8995->supplies); 2057 if (ret) { 2058 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2059 goto err_reg_get; 2060 } 2061 2062 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); 2063 if (ret < 0) { 2064 dev_err(codec->dev, "Failed to read device ID: %d\n", ret); 2065 goto err_reg_enable; 2066 } 2067 2068 if (ret != 0x8995) { 2069 dev_err(codec->dev, "Invalid device ID: %#x\n", ret); 2070 ret = -EINVAL; 2071 goto err_reg_enable; 2072 } 2073 2074 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); 2075 if (ret < 0) { 2076 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); 2077 goto err_reg_enable; 2078 } 2079 2080 /* Latch volume updates (right only; we always do left then right). */ 2081 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, 2082 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); 2083 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, 2084 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); 2085 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, 2086 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); 2087 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, 2088 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); 2089 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, 2090 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); 2091 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, 2092 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); 2093 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, 2094 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); 2095 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, 2096 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); 2097 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, 2098 WM8995_IN1_VU_MASK, WM8995_IN1_VU); 2099 2100 wm8995_update_class_w(codec); 2101 2102 return 0; 2103 2104 err_reg_enable: 2105 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2106 err_reg_get: 2107 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2108 return ret; 2109 } 2110 2111 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2112 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2113 2114 static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = { 2115 .set_sysclk = wm8995_set_dai_sysclk, 2116 .set_fmt = wm8995_set_dai_fmt, 2117 .hw_params = wm8995_hw_params, 2118 .digital_mute = wm8995_aif_mute, 2119 .set_pll = wm8995_set_fll, 2120 .set_tristate = wm8995_set_tristate, 2121 }; 2122 2123 static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = { 2124 .set_sysclk = wm8995_set_dai_sysclk, 2125 .set_fmt = wm8995_set_dai_fmt, 2126 .hw_params = wm8995_hw_params, 2127 .digital_mute = wm8995_aif_mute, 2128 .set_pll = wm8995_set_fll, 2129 .set_tristate = wm8995_set_tristate, 2130 }; 2131 2132 static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = { 2133 .set_tristate = wm8995_set_tristate, 2134 }; 2135 2136 static struct snd_soc_dai_driver wm8995_dai[] = { 2137 { 2138 .name = "wm8995-aif1", 2139 .playback = { 2140 .stream_name = "AIF1 Playback", 2141 .channels_min = 2, 2142 .channels_max = 2, 2143 .rates = SNDRV_PCM_RATE_8000_96000, 2144 .formats = WM8995_FORMATS 2145 }, 2146 .capture = { 2147 .stream_name = "AIF1 Capture", 2148 .channels_min = 2, 2149 .channels_max = 2, 2150 .rates = SNDRV_PCM_RATE_8000_48000, 2151 .formats = WM8995_FORMATS 2152 }, 2153 .ops = &wm8995_aif1_dai_ops 2154 }, 2155 { 2156 .name = "wm8995-aif2", 2157 .playback = { 2158 .stream_name = "AIF2 Playback", 2159 .channels_min = 2, 2160 .channels_max = 2, 2161 .rates = SNDRV_PCM_RATE_8000_96000, 2162 .formats = WM8995_FORMATS 2163 }, 2164 .capture = { 2165 .stream_name = "AIF2 Capture", 2166 .channels_min = 2, 2167 .channels_max = 2, 2168 .rates = SNDRV_PCM_RATE_8000_48000, 2169 .formats = WM8995_FORMATS 2170 }, 2171 .ops = &wm8995_aif2_dai_ops 2172 }, 2173 { 2174 .name = "wm8995-aif3", 2175 .playback = { 2176 .stream_name = "AIF3 Playback", 2177 .channels_min = 2, 2178 .channels_max = 2, 2179 .rates = SNDRV_PCM_RATE_8000_96000, 2180 .formats = WM8995_FORMATS 2181 }, 2182 .capture = { 2183 .stream_name = "AIF3 Capture", 2184 .channels_min = 2, 2185 .channels_max = 2, 2186 .rates = SNDRV_PCM_RATE_8000_48000, 2187 .formats = WM8995_FORMATS 2188 }, 2189 .ops = &wm8995_aif3_dai_ops 2190 } 2191 }; 2192 2193 static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { 2194 .probe = wm8995_probe, 2195 .remove = wm8995_remove, 2196 .set_bias_level = wm8995_set_bias_level, 2197 .idle_bias_off = true, 2198 2199 .controls = wm8995_snd_controls, 2200 .num_controls = ARRAY_SIZE(wm8995_snd_controls), 2201 .dapm_widgets = wm8995_dapm_widgets, 2202 .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets), 2203 .dapm_routes = wm8995_intercon, 2204 .num_dapm_routes = ARRAY_SIZE(wm8995_intercon), 2205 }; 2206 2207 static struct regmap_config wm8995_regmap = { 2208 .reg_bits = 16, 2209 .val_bits = 16, 2210 2211 .max_register = WM8995_MAX_REGISTER, 2212 .reg_defaults = wm8995_reg_defaults, 2213 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults), 2214 .volatile_reg = wm8995_volatile, 2215 .readable_reg = wm8995_readable, 2216 .cache_type = REGCACHE_RBTREE, 2217 }; 2218 2219 #if defined(CONFIG_SPI_MASTER) 2220 static int wm8995_spi_probe(struct spi_device *spi) 2221 { 2222 struct wm8995_priv *wm8995; 2223 int ret; 2224 2225 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL); 2226 if (!wm8995) 2227 return -ENOMEM; 2228 2229 spi_set_drvdata(spi, wm8995); 2230 2231 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap); 2232 if (IS_ERR(wm8995->regmap)) { 2233 ret = PTR_ERR(wm8995->regmap); 2234 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret); 2235 return ret; 2236 } 2237 2238 ret = snd_soc_register_codec(&spi->dev, 2239 &soc_codec_dev_wm8995, wm8995_dai, 2240 ARRAY_SIZE(wm8995_dai)); 2241 return ret; 2242 } 2243 2244 static int wm8995_spi_remove(struct spi_device *spi) 2245 { 2246 snd_soc_unregister_codec(&spi->dev); 2247 return 0; 2248 } 2249 2250 static struct spi_driver wm8995_spi_driver = { 2251 .driver = { 2252 .name = "wm8995", 2253 .owner = THIS_MODULE, 2254 }, 2255 .probe = wm8995_spi_probe, 2256 .remove = wm8995_spi_remove 2257 }; 2258 #endif 2259 2260 #if IS_ENABLED(CONFIG_I2C) 2261 static int wm8995_i2c_probe(struct i2c_client *i2c, 2262 const struct i2c_device_id *id) 2263 { 2264 struct wm8995_priv *wm8995; 2265 int ret; 2266 2267 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL); 2268 if (!wm8995) 2269 return -ENOMEM; 2270 2271 i2c_set_clientdata(i2c, wm8995); 2272 2273 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap); 2274 if (IS_ERR(wm8995->regmap)) { 2275 ret = PTR_ERR(wm8995->regmap); 2276 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret); 2277 return ret; 2278 } 2279 2280 ret = snd_soc_register_codec(&i2c->dev, 2281 &soc_codec_dev_wm8995, wm8995_dai, 2282 ARRAY_SIZE(wm8995_dai)); 2283 if (ret < 0) 2284 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 2285 2286 return ret; 2287 } 2288 2289 static int wm8995_i2c_remove(struct i2c_client *client) 2290 { 2291 snd_soc_unregister_codec(&client->dev); 2292 return 0; 2293 } 2294 2295 static const struct i2c_device_id wm8995_i2c_id[] = { 2296 {"wm8995", 0}, 2297 {} 2298 }; 2299 2300 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); 2301 2302 static struct i2c_driver wm8995_i2c_driver = { 2303 .driver = { 2304 .name = "wm8995", 2305 .owner = THIS_MODULE, 2306 }, 2307 .probe = wm8995_i2c_probe, 2308 .remove = wm8995_i2c_remove, 2309 .id_table = wm8995_i2c_id 2310 }; 2311 #endif 2312 2313 static int __init wm8995_modinit(void) 2314 { 2315 int ret = 0; 2316 2317 #if IS_ENABLED(CONFIG_I2C) 2318 ret = i2c_add_driver(&wm8995_i2c_driver); 2319 if (ret) { 2320 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", 2321 ret); 2322 } 2323 #endif 2324 #if defined(CONFIG_SPI_MASTER) 2325 ret = spi_register_driver(&wm8995_spi_driver); 2326 if (ret) { 2327 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", 2328 ret); 2329 } 2330 #endif 2331 return ret; 2332 } 2333 2334 module_init(wm8995_modinit); 2335 2336 static void __exit wm8995_exit(void) 2337 { 2338 #if IS_ENABLED(CONFIG_I2C) 2339 i2c_del_driver(&wm8995_i2c_driver); 2340 #endif 2341 #if defined(CONFIG_SPI_MASTER) 2342 spi_unregister_driver(&wm8995_spi_driver); 2343 #endif 2344 } 2345 2346 module_exit(wm8995_exit); 2347 2348 MODULE_DESCRIPTION("ASoC WM8995 driver"); 2349 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); 2350 MODULE_LICENSE("GPL"); 2351