1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8994.c -- WM8994 ALSA SoC Audio driver 4 * 5 * Copyright 2009-12 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/gcd.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <trace/events/asoc.h> 29 30 #include <linux/mfd/wm8994/core.h> 31 #include <linux/mfd/wm8994/registers.h> 32 #include <linux/mfd/wm8994/pdata.h> 33 #include <linux/mfd/wm8994/gpio.h> 34 35 #include "wm8994.h" 36 #include "wm_hubs.h" 37 38 #define WM1811_JACKDET_MODE_NONE 0x0000 39 #define WM1811_JACKDET_MODE_JACK 0x0100 40 #define WM1811_JACKDET_MODE_MIC 0x0080 41 #define WM1811_JACKDET_MODE_AUDIO 0x0180 42 43 #define WM8994_NUM_DRC 3 44 #define WM8994_NUM_EQ 3 45 46 static struct { 47 unsigned int reg; 48 unsigned int mask; 49 } wm8994_vu_bits[] = { 50 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 51 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 52 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 53 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 54 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 55 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 56 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 57 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 58 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 59 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 60 61 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 62 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 63 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 64 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 65 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 66 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 67 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 68 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 69 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 70 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 71 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 72 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 73 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 74 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 75 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 76 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 77 }; 78 79 static int wm8994_drc_base[] = { 80 WM8994_AIF1_DRC1_1, 81 WM8994_AIF1_DRC2_1, 82 WM8994_AIF2_DRC_1, 83 }; 84 85 static int wm8994_retune_mobile_base[] = { 86 WM8994_AIF1_DAC1_EQ_GAINS_1, 87 WM8994_AIF1_DAC2_EQ_GAINS_1, 88 WM8994_AIF2_EQ_GAINS_1, 89 }; 90 91 static const struct wm8958_micd_rate micdet_rates[] = { 92 { 32768, true, 1, 4 }, 93 { 32768, false, 1, 1 }, 94 { 44100 * 256, true, 7, 10 }, 95 { 44100 * 256, false, 7, 10 }, 96 }; 97 98 static const struct wm8958_micd_rate jackdet_rates[] = { 99 { 32768, true, 0, 1 }, 100 { 32768, false, 0, 1 }, 101 { 44100 * 256, true, 10, 10 }, 102 { 44100 * 256, false, 7, 8 }, 103 }; 104 105 static void wm8958_micd_set_rate(struct snd_soc_component *component) 106 { 107 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 108 struct wm8994 *control = wm8994->wm8994; 109 int best, i, sysclk, val; 110 bool idle; 111 const struct wm8958_micd_rate *rates; 112 int num_rates; 113 114 idle = !wm8994->jack_mic; 115 116 sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1); 117 if (sysclk & WM8994_SYSCLK_SRC) 118 sysclk = wm8994->aifclk[1]; 119 else 120 sysclk = wm8994->aifclk[0]; 121 122 if (control->pdata.micd_rates) { 123 rates = control->pdata.micd_rates; 124 num_rates = control->pdata.num_micd_rates; 125 } else if (wm8994->jackdet) { 126 rates = jackdet_rates; 127 num_rates = ARRAY_SIZE(jackdet_rates); 128 } else { 129 rates = micdet_rates; 130 num_rates = ARRAY_SIZE(micdet_rates); 131 } 132 133 best = 0; 134 for (i = 0; i < num_rates; i++) { 135 if (rates[i].idle != idle) 136 continue; 137 if (abs(rates[i].sysclk - sysclk) < 138 abs(rates[best].sysclk - sysclk)) 139 best = i; 140 else if (rates[best].idle != idle) 141 best = i; 142 } 143 144 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 145 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 146 147 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n", 148 rates[best].start, rates[best].rate, sysclk, 149 idle ? "idle" : "active"); 150 151 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 152 WM8958_MICD_BIAS_STARTTIME_MASK | 153 WM8958_MICD_RATE_MASK, val); 154 } 155 156 static int configure_aif_clock(struct snd_soc_component *component, int aif) 157 { 158 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 159 int rate; 160 int reg1 = 0; 161 int offset; 162 163 if (aif) 164 offset = 4; 165 else 166 offset = 0; 167 168 switch (wm8994->sysclk[aif]) { 169 case WM8994_SYSCLK_MCLK1: 170 rate = wm8994->mclk[0]; 171 break; 172 173 case WM8994_SYSCLK_MCLK2: 174 reg1 |= 0x8; 175 rate = wm8994->mclk[1]; 176 break; 177 178 case WM8994_SYSCLK_FLL1: 179 reg1 |= 0x10; 180 rate = wm8994->fll[0].out; 181 break; 182 183 case WM8994_SYSCLK_FLL2: 184 reg1 |= 0x18; 185 rate = wm8994->fll[1].out; 186 break; 187 188 default: 189 return -EINVAL; 190 } 191 192 if (rate >= 13500000) { 193 rate /= 2; 194 reg1 |= WM8994_AIF1CLK_DIV; 195 196 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n", 197 aif + 1, rate); 198 } 199 200 wm8994->aifclk[aif] = rate; 201 202 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset, 203 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 204 reg1); 205 206 return 0; 207 } 208 209 static int configure_clock(struct snd_soc_component *component) 210 { 211 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 212 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 213 int change, new; 214 215 /* Bring up the AIF clocks first */ 216 configure_aif_clock(component, 0); 217 configure_aif_clock(component, 1); 218 219 /* Then switch CLK_SYS over to the higher of them; a change 220 * can only happen as a result of a clocking change which can 221 * only be made outside of DAPM so we can safely redo the 222 * clocking. 223 */ 224 225 /* If they're equal it doesn't matter which is used */ 226 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 227 wm8958_micd_set_rate(component); 228 return 0; 229 } 230 231 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 232 new = WM8994_SYSCLK_SRC; 233 else 234 new = 0; 235 236 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 237 WM8994_SYSCLK_SRC, new); 238 if (change) 239 snd_soc_dapm_sync(dapm); 240 241 wm8958_micd_set_rate(component); 242 243 return 0; 244 } 245 246 static int check_clk_sys(struct snd_soc_dapm_widget *source, 247 struct snd_soc_dapm_widget *sink) 248 { 249 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 250 int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); 251 const char *clk; 252 253 /* Check what we're currently using for CLK_SYS */ 254 if (reg & WM8994_SYSCLK_SRC) 255 clk = "AIF2CLK"; 256 else 257 clk = "AIF1CLK"; 258 259 return strcmp(source->name, clk) == 0; 260 } 261 262 static const char *sidetone_hpf_text[] = { 263 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 264 }; 265 266 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 267 WM8994_SIDETONE, 7, sidetone_hpf_text); 268 269 static const char *adc_hpf_text[] = { 270 "HiFi", "Voice 1", "Voice 2", "Voice 3" 271 }; 272 273 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf, 274 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text); 275 276 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf, 277 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text); 278 279 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf, 280 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text); 281 282 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 283 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 284 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 285 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 286 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 287 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 288 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); 289 290 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 291 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ 292 snd_soc_get_volsw, wm8994_put_drc_sw) 293 294 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct soc_mixer_control *mc = 298 (struct soc_mixer_control *)kcontrol->private_value; 299 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 300 int mask, ret; 301 302 /* Can't enable both ADC and DAC paths simultaneously */ 303 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 304 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 305 WM8994_AIF1ADC1R_DRC_ENA_MASK; 306 else 307 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 308 309 ret = snd_soc_component_read32(component, mc->reg); 310 if (ret < 0) 311 return ret; 312 if (ret & mask) 313 return -EINVAL; 314 315 return snd_soc_put_volsw(kcontrol, ucontrol); 316 } 317 318 static void wm8994_set_drc(struct snd_soc_component *component, int drc) 319 { 320 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 321 struct wm8994 *control = wm8994->wm8994; 322 struct wm8994_pdata *pdata = &control->pdata; 323 int base = wm8994_drc_base[drc]; 324 int cfg = wm8994->drc_cfg[drc]; 325 int save, i; 326 327 /* Save any enables; the configuration should clear them. */ 328 save = snd_soc_component_read32(component, base); 329 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 330 WM8994_AIF1ADC1R_DRC_ENA; 331 332 for (i = 0; i < WM8994_DRC_REGS; i++) 333 snd_soc_component_update_bits(component, base + i, 0xffff, 334 pdata->drc_cfgs[cfg].regs[i]); 335 336 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA | 337 WM8994_AIF1ADC1L_DRC_ENA | 338 WM8994_AIF1ADC1R_DRC_ENA, save); 339 } 340 341 /* Icky as hell but saves code duplication */ 342 static int wm8994_get_drc(const char *name) 343 { 344 if (strcmp(name, "AIF1DRC1 Mode") == 0) 345 return 0; 346 if (strcmp(name, "AIF1DRC2 Mode") == 0) 347 return 1; 348 if (strcmp(name, "AIF2DRC Mode") == 0) 349 return 2; 350 return -EINVAL; 351 } 352 353 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 354 struct snd_ctl_elem_value *ucontrol) 355 { 356 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 357 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 358 struct wm8994 *control = wm8994->wm8994; 359 struct wm8994_pdata *pdata = &control->pdata; 360 int drc = wm8994_get_drc(kcontrol->id.name); 361 int value = ucontrol->value.enumerated.item[0]; 362 363 if (drc < 0) 364 return drc; 365 366 if (value >= pdata->num_drc_cfgs) 367 return -EINVAL; 368 369 wm8994->drc_cfg[drc] = value; 370 371 wm8994_set_drc(component, drc); 372 373 return 0; 374 } 375 376 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 377 struct snd_ctl_elem_value *ucontrol) 378 { 379 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 380 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 381 int drc = wm8994_get_drc(kcontrol->id.name); 382 383 if (drc < 0) 384 return drc; 385 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 386 387 return 0; 388 } 389 390 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block) 391 { 392 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 393 struct wm8994 *control = wm8994->wm8994; 394 struct wm8994_pdata *pdata = &control->pdata; 395 int base = wm8994_retune_mobile_base[block]; 396 int iface, best, best_val, save, i, cfg; 397 398 if (!pdata || !wm8994->num_retune_mobile_texts) 399 return; 400 401 switch (block) { 402 case 0: 403 case 1: 404 iface = 0; 405 break; 406 case 2: 407 iface = 1; 408 break; 409 default: 410 return; 411 } 412 413 /* Find the version of the currently selected configuration 414 * with the nearest sample rate. */ 415 cfg = wm8994->retune_mobile_cfg[block]; 416 best = 0; 417 best_val = INT_MAX; 418 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 419 if (strcmp(pdata->retune_mobile_cfgs[i].name, 420 wm8994->retune_mobile_texts[cfg]) == 0 && 421 abs(pdata->retune_mobile_cfgs[i].rate 422 - wm8994->dac_rates[iface]) < best_val) { 423 best = i; 424 best_val = abs(pdata->retune_mobile_cfgs[i].rate 425 - wm8994->dac_rates[iface]); 426 } 427 } 428 429 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 430 block, 431 pdata->retune_mobile_cfgs[best].name, 432 pdata->retune_mobile_cfgs[best].rate, 433 wm8994->dac_rates[iface]); 434 435 /* The EQ will be disabled while reconfiguring it, remember the 436 * current configuration. 437 */ 438 save = snd_soc_component_read32(component, base); 439 save &= WM8994_AIF1DAC1_EQ_ENA; 440 441 for (i = 0; i < WM8994_EQ_REGS; i++) 442 snd_soc_component_update_bits(component, base + i, 0xffff, 443 pdata->retune_mobile_cfgs[best].regs[i]); 444 445 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save); 446 } 447 448 /* Icky as hell but saves code duplication */ 449 static int wm8994_get_retune_mobile_block(const char *name) 450 { 451 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 452 return 0; 453 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 454 return 1; 455 if (strcmp(name, "AIF2 EQ Mode") == 0) 456 return 2; 457 return -EINVAL; 458 } 459 460 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 461 struct snd_ctl_elem_value *ucontrol) 462 { 463 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 464 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 465 struct wm8994 *control = wm8994->wm8994; 466 struct wm8994_pdata *pdata = &control->pdata; 467 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 468 int value = ucontrol->value.enumerated.item[0]; 469 470 if (block < 0) 471 return block; 472 473 if (value >= pdata->num_retune_mobile_cfgs) 474 return -EINVAL; 475 476 wm8994->retune_mobile_cfg[block] = value; 477 478 wm8994_set_retune_mobile(component, block); 479 480 return 0; 481 } 482 483 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 484 struct snd_ctl_elem_value *ucontrol) 485 { 486 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 487 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 488 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 489 490 if (block < 0) 491 return block; 492 493 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 494 495 return 0; 496 } 497 498 static const char *aif_chan_src_text[] = { 499 "Left", "Right" 500 }; 501 502 static SOC_ENUM_SINGLE_DECL(aif1adcl_src, 503 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text); 504 505 static SOC_ENUM_SINGLE_DECL(aif1adcr_src, 506 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text); 507 508 static SOC_ENUM_SINGLE_DECL(aif2adcl_src, 509 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text); 510 511 static SOC_ENUM_SINGLE_DECL(aif2adcr_src, 512 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text); 513 514 static SOC_ENUM_SINGLE_DECL(aif1dacl_src, 515 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text); 516 517 static SOC_ENUM_SINGLE_DECL(aif1dacr_src, 518 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text); 519 520 static SOC_ENUM_SINGLE_DECL(aif2dacl_src, 521 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text); 522 523 static SOC_ENUM_SINGLE_DECL(aif2dacr_src, 524 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text); 525 526 static const char *osr_text[] = { 527 "Low Power", "High Performance", 528 }; 529 530 static SOC_ENUM_SINGLE_DECL(dac_osr, 531 WM8994_OVERSAMPLING, 0, osr_text); 532 533 static SOC_ENUM_SINGLE_DECL(adc_osr, 534 WM8994_OVERSAMPLING, 1, osr_text); 535 536 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 537 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 538 WM8994_AIF1_ADC1_RIGHT_VOLUME, 539 1, 119, 0, digital_tlv), 540 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 541 WM8994_AIF1_ADC2_RIGHT_VOLUME, 542 1, 119, 0, digital_tlv), 543 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 544 WM8994_AIF2_ADC_RIGHT_VOLUME, 545 1, 119, 0, digital_tlv), 546 547 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 548 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 549 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 550 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 551 552 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 553 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 554 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 555 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 556 557 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 558 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 559 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 560 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 561 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 562 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 563 564 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 565 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 566 567 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 568 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 569 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 570 571 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 572 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 573 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 574 575 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 576 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 577 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 578 579 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 580 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 581 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 582 583 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 584 5, 12, 0, st_tlv), 585 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 586 0, 12, 0, st_tlv), 587 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 588 5, 12, 0, st_tlv), 589 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 590 0, 12, 0, st_tlv), 591 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 592 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 593 594 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 595 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 596 597 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 598 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 599 600 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 601 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 602 603 SOC_ENUM("ADC OSR", adc_osr), 604 SOC_ENUM("DAC OSR", dac_osr), 605 606 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 607 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 608 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 609 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 610 611 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 612 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 613 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 614 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 615 616 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 617 6, 1, 1, wm_hubs_spkmix_tlv), 618 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 619 2, 1, 1, wm_hubs_spkmix_tlv), 620 621 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 622 6, 1, 1, wm_hubs_spkmix_tlv), 623 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 624 2, 1, 1, wm_hubs_spkmix_tlv), 625 626 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 627 10, 15, 0, wm8994_3d_tlv), 628 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 629 8, 1, 0), 630 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 631 10, 15, 0, wm8994_3d_tlv), 632 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 633 8, 1, 0), 634 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 635 10, 15, 0, wm8994_3d_tlv), 636 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 637 8, 1, 0), 638 }; 639 640 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 641 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 642 eq_tlv), 643 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 644 eq_tlv), 645 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 646 eq_tlv), 647 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 648 eq_tlv), 649 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 650 eq_tlv), 651 652 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 653 eq_tlv), 654 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 655 eq_tlv), 656 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 659 eq_tlv), 660 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 661 eq_tlv), 662 663 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 664 eq_tlv), 665 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 666 eq_tlv), 667 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 670 eq_tlv), 671 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 672 eq_tlv), 673 }; 674 675 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 676 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 677 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 678 WM8994_AIF1ADC1R_DRC_ENA), 679 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 680 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 681 WM8994_AIF1ADC2R_DRC_ENA), 682 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 683 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 684 WM8994_AIF2ADCR_DRC_ENA), 685 }; 686 687 static const char *wm8958_ng_text[] = { 688 "30ms", "125ms", "250ms", "500ms", 689 }; 690 691 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold, 692 WM8958_AIF1_DAC1_NOISE_GATE, 693 WM8958_AIF1DAC1_NG_THR_SHIFT, 694 wm8958_ng_text); 695 696 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold, 697 WM8958_AIF1_DAC2_NOISE_GATE, 698 WM8958_AIF1DAC2_NG_THR_SHIFT, 699 wm8958_ng_text); 700 701 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold, 702 WM8958_AIF2_DAC_NOISE_GATE, 703 WM8958_AIF2DAC_NG_THR_SHIFT, 704 wm8958_ng_text); 705 706 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 707 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 708 709 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 710 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 711 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 712 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 713 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 714 7, 1, ng_tlv), 715 716 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 717 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 718 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 719 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 720 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 721 7, 1, ng_tlv), 722 723 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 724 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 725 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 726 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 727 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 728 7, 1, ng_tlv), 729 }; 730 731 static const struct snd_kcontrol_new wm1811_snd_controls[] = { 732 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, 733 mixin_boost_tlv), 734 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, 735 mixin_boost_tlv), 736 }; 737 738 /* We run all mode setting through a function to enforce audio mode */ 739 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode) 740 { 741 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 742 743 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 744 return; 745 746 if (wm8994->active_refcount) 747 mode = WM1811_JACKDET_MODE_AUDIO; 748 749 if (mode == wm8994->jackdet_mode) 750 return; 751 752 wm8994->jackdet_mode = mode; 753 754 /* Always use audio mode to detect while the system is active */ 755 if (mode != WM1811_JACKDET_MODE_NONE) 756 mode = WM1811_JACKDET_MODE_AUDIO; 757 758 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 759 WM1811_JACKDET_MODE_MASK, mode); 760 } 761 762 static void active_reference(struct snd_soc_component *component) 763 { 764 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 765 766 mutex_lock(&wm8994->accdet_lock); 767 768 wm8994->active_refcount++; 769 770 dev_dbg(component->dev, "Active refcount incremented, now %d\n", 771 wm8994->active_refcount); 772 773 /* If we're using jack detection go into audio mode */ 774 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO); 775 776 mutex_unlock(&wm8994->accdet_lock); 777 } 778 779 static void active_dereference(struct snd_soc_component *component) 780 { 781 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 782 u16 mode; 783 784 mutex_lock(&wm8994->accdet_lock); 785 786 wm8994->active_refcount--; 787 788 dev_dbg(component->dev, "Active refcount decremented, now %d\n", 789 wm8994->active_refcount); 790 791 if (wm8994->active_refcount == 0) { 792 /* Go into appropriate detection only mode */ 793 if (wm8994->jack_mic || wm8994->mic_detecting) 794 mode = WM1811_JACKDET_MODE_MIC; 795 else 796 mode = WM1811_JACKDET_MODE_JACK; 797 798 wm1811_jackdet_set_mode(component, mode); 799 } 800 801 mutex_unlock(&wm8994->accdet_lock); 802 } 803 804 static int clk_sys_event(struct snd_soc_dapm_widget *w, 805 struct snd_kcontrol *kcontrol, int event) 806 { 807 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 808 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 809 810 switch (event) { 811 case SND_SOC_DAPM_PRE_PMU: 812 return configure_clock(component); 813 814 case SND_SOC_DAPM_POST_PMU: 815 /* 816 * JACKDET won't run until we start the clock and it 817 * only reports deltas, make sure we notify the state 818 * up the stack on startup. Use a *very* generous 819 * timeout for paranoia, there's no urgency and we 820 * don't want false reports. 821 */ 822 if (wm8994->jackdet && !wm8994->clk_has_run) { 823 queue_delayed_work(system_power_efficient_wq, 824 &wm8994->jackdet_bootstrap, 825 msecs_to_jiffies(1000)); 826 wm8994->clk_has_run = true; 827 } 828 break; 829 830 case SND_SOC_DAPM_POST_PMD: 831 configure_clock(component); 832 break; 833 } 834 835 return 0; 836 } 837 838 static void vmid_reference(struct snd_soc_component *component) 839 { 840 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 841 842 pm_runtime_get_sync(component->dev); 843 844 wm8994->vmid_refcount++; 845 846 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n", 847 wm8994->vmid_refcount); 848 849 if (wm8994->vmid_refcount == 1) { 850 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 851 WM8994_LINEOUT1_DISCH | 852 WM8994_LINEOUT2_DISCH, 0); 853 854 wm_hubs_vmid_ena(component); 855 856 switch (wm8994->vmid_mode) { 857 default: 858 WARN_ON(NULL == "Invalid VMID mode"); 859 /* fall through */ 860 case WM8994_VMID_NORMAL: 861 /* Startup bias, VMID ramp & buffer */ 862 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 863 WM8994_BIAS_SRC | 864 WM8994_VMID_DISCH | 865 WM8994_STARTUP_BIAS_ENA | 866 WM8994_VMID_BUF_ENA | 867 WM8994_VMID_RAMP_MASK, 868 WM8994_BIAS_SRC | 869 WM8994_STARTUP_BIAS_ENA | 870 WM8994_VMID_BUF_ENA | 871 (0x2 << WM8994_VMID_RAMP_SHIFT)); 872 873 /* Main bias enable, VMID=2x40k */ 874 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 875 WM8994_BIAS_ENA | 876 WM8994_VMID_SEL_MASK, 877 WM8994_BIAS_ENA | 0x2); 878 879 msleep(300); 880 881 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 882 WM8994_VMID_RAMP_MASK | 883 WM8994_BIAS_SRC, 884 0); 885 break; 886 887 case WM8994_VMID_FORCE: 888 /* Startup bias, slow VMID ramp & buffer */ 889 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 890 WM8994_BIAS_SRC | 891 WM8994_VMID_DISCH | 892 WM8994_STARTUP_BIAS_ENA | 893 WM8994_VMID_BUF_ENA | 894 WM8994_VMID_RAMP_MASK, 895 WM8994_BIAS_SRC | 896 WM8994_STARTUP_BIAS_ENA | 897 WM8994_VMID_BUF_ENA | 898 (0x2 << WM8994_VMID_RAMP_SHIFT)); 899 900 /* Main bias enable, VMID=2x40k */ 901 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 902 WM8994_BIAS_ENA | 903 WM8994_VMID_SEL_MASK, 904 WM8994_BIAS_ENA | 0x2); 905 906 msleep(400); 907 908 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 909 WM8994_VMID_RAMP_MASK | 910 WM8994_BIAS_SRC, 911 0); 912 break; 913 } 914 } 915 } 916 917 static void vmid_dereference(struct snd_soc_component *component) 918 { 919 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 920 921 wm8994->vmid_refcount--; 922 923 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n", 924 wm8994->vmid_refcount); 925 926 if (wm8994->vmid_refcount == 0) { 927 if (wm8994->hubs.lineout1_se) 928 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 929 WM8994_LINEOUT1N_ENA | 930 WM8994_LINEOUT1P_ENA, 931 WM8994_LINEOUT1N_ENA | 932 WM8994_LINEOUT1P_ENA); 933 934 if (wm8994->hubs.lineout2_se) 935 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 936 WM8994_LINEOUT2N_ENA | 937 WM8994_LINEOUT2P_ENA, 938 WM8994_LINEOUT2N_ENA | 939 WM8994_LINEOUT2P_ENA); 940 941 /* Start discharging VMID */ 942 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 943 WM8994_BIAS_SRC | 944 WM8994_VMID_DISCH, 945 WM8994_BIAS_SRC | 946 WM8994_VMID_DISCH); 947 948 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 949 WM8994_VMID_SEL_MASK, 0); 950 951 msleep(400); 952 953 /* Active discharge */ 954 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 955 WM8994_LINEOUT1_DISCH | 956 WM8994_LINEOUT2_DISCH, 957 WM8994_LINEOUT1_DISCH | 958 WM8994_LINEOUT2_DISCH); 959 960 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 961 WM8994_LINEOUT1N_ENA | 962 WM8994_LINEOUT1P_ENA | 963 WM8994_LINEOUT2N_ENA | 964 WM8994_LINEOUT2P_ENA, 0); 965 966 /* Switch off startup biases */ 967 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 968 WM8994_BIAS_SRC | 969 WM8994_STARTUP_BIAS_ENA | 970 WM8994_VMID_BUF_ENA | 971 WM8994_VMID_RAMP_MASK, 0); 972 973 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 974 WM8994_VMID_SEL_MASK, 0); 975 } 976 977 pm_runtime_put(component->dev); 978 } 979 980 static int vmid_event(struct snd_soc_dapm_widget *w, 981 struct snd_kcontrol *kcontrol, int event) 982 { 983 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 984 985 switch (event) { 986 case SND_SOC_DAPM_PRE_PMU: 987 vmid_reference(component); 988 break; 989 990 case SND_SOC_DAPM_POST_PMD: 991 vmid_dereference(component); 992 break; 993 } 994 995 return 0; 996 } 997 998 static bool wm8994_check_class_w_digital(struct snd_soc_component *component) 999 { 1000 int source = 0; /* GCC flow analysis can't track enable */ 1001 int reg, reg_r; 1002 1003 /* We also need the same AIF source for L/R and only one path */ 1004 reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING); 1005 switch (reg) { 1006 case WM8994_AIF2DACL_TO_DAC1L: 1007 dev_vdbg(component->dev, "Class W source AIF2DAC\n"); 1008 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1009 break; 1010 case WM8994_AIF1DAC2L_TO_DAC1L: 1011 dev_vdbg(component->dev, "Class W source AIF1DAC2\n"); 1012 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1013 break; 1014 case WM8994_AIF1DAC1L_TO_DAC1L: 1015 dev_vdbg(component->dev, "Class W source AIF1DAC1\n"); 1016 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1017 break; 1018 default: 1019 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg); 1020 return false; 1021 } 1022 1023 reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1024 if (reg_r != reg) { 1025 dev_vdbg(component->dev, "Left and right DAC mixers different\n"); 1026 return false; 1027 } 1028 1029 /* Set the source up */ 1030 snd_soc_component_update_bits(component, WM8994_CLASS_W_1, 1031 WM8994_CP_DYN_SRC_SEL_MASK, source); 1032 1033 return true; 1034 } 1035 1036 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1037 struct snd_kcontrol *kcontrol, int event) 1038 { 1039 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1040 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1041 struct wm8994 *control = wm8994->wm8994; 1042 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1043 int i; 1044 int dac; 1045 int adc; 1046 int val; 1047 1048 switch (control->type) { 1049 case WM8994: 1050 case WM8958: 1051 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 switch (event) { 1058 case SND_SOC_DAPM_PRE_PMU: 1059 /* Don't enable timeslot 2 if not in use */ 1060 if (wm8994->channels[0] <= 2) 1061 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1062 1063 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1); 1064 if ((val & WM8994_AIF1ADCL_SRC) && 1065 (val & WM8994_AIF1ADCR_SRC)) 1066 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1067 else if (!(val & WM8994_AIF1ADCL_SRC) && 1068 !(val & WM8994_AIF1ADCR_SRC)) 1069 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1070 else 1071 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1072 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1073 1074 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2); 1075 if ((val & WM8994_AIF1DACL_SRC) && 1076 (val & WM8994_AIF1DACR_SRC)) 1077 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1078 else if (!(val & WM8994_AIF1DACL_SRC) && 1079 !(val & WM8994_AIF1DACR_SRC)) 1080 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1081 else 1082 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1083 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1084 1085 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1086 mask, adc); 1087 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1088 mask, dac); 1089 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1090 WM8994_AIF1DSPCLK_ENA | 1091 WM8994_SYSDSPCLK_ENA, 1092 WM8994_AIF1DSPCLK_ENA | 1093 WM8994_SYSDSPCLK_ENA); 1094 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask, 1095 WM8994_AIF1ADC1R_ENA | 1096 WM8994_AIF1ADC1L_ENA | 1097 WM8994_AIF1ADC2R_ENA | 1098 WM8994_AIF1ADC2L_ENA); 1099 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask, 1100 WM8994_AIF1DAC1R_ENA | 1101 WM8994_AIF1DAC1L_ENA | 1102 WM8994_AIF1DAC2R_ENA | 1103 WM8994_AIF1DAC2L_ENA); 1104 break; 1105 1106 case SND_SOC_DAPM_POST_PMU: 1107 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1108 snd_soc_component_write(component, wm8994_vu_bits[i].reg, 1109 snd_soc_component_read32(component, 1110 wm8994_vu_bits[i].reg)); 1111 break; 1112 1113 case SND_SOC_DAPM_PRE_PMD: 1114 case SND_SOC_DAPM_POST_PMD: 1115 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1116 mask, 0); 1117 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1118 mask, 0); 1119 1120 val = snd_soc_component_read32(component, WM8994_CLOCKING_1); 1121 if (val & WM8994_AIF2DSPCLK_ENA) 1122 val = WM8994_SYSDSPCLK_ENA; 1123 else 1124 val = 0; 1125 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1126 WM8994_SYSDSPCLK_ENA | 1127 WM8994_AIF1DSPCLK_ENA, val); 1128 break; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1135 struct snd_kcontrol *kcontrol, int event) 1136 { 1137 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1138 int i; 1139 int dac; 1140 int adc; 1141 int val; 1142 1143 switch (event) { 1144 case SND_SOC_DAPM_PRE_PMU: 1145 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1); 1146 if ((val & WM8994_AIF2ADCL_SRC) && 1147 (val & WM8994_AIF2ADCR_SRC)) 1148 adc = WM8994_AIF2ADCR_ENA; 1149 else if (!(val & WM8994_AIF2ADCL_SRC) && 1150 !(val & WM8994_AIF2ADCR_SRC)) 1151 adc = WM8994_AIF2ADCL_ENA; 1152 else 1153 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1154 1155 1156 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2); 1157 if ((val & WM8994_AIF2DACL_SRC) && 1158 (val & WM8994_AIF2DACR_SRC)) 1159 dac = WM8994_AIF2DACR_ENA; 1160 else if (!(val & WM8994_AIF2DACL_SRC) && 1161 !(val & WM8994_AIF2DACR_SRC)) 1162 dac = WM8994_AIF2DACL_ENA; 1163 else 1164 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1165 1166 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1167 WM8994_AIF2ADCL_ENA | 1168 WM8994_AIF2ADCR_ENA, adc); 1169 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1170 WM8994_AIF2DACL_ENA | 1171 WM8994_AIF2DACR_ENA, dac); 1172 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1173 WM8994_AIF2DSPCLK_ENA | 1174 WM8994_SYSDSPCLK_ENA, 1175 WM8994_AIF2DSPCLK_ENA | 1176 WM8994_SYSDSPCLK_ENA); 1177 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1178 WM8994_AIF2ADCL_ENA | 1179 WM8994_AIF2ADCR_ENA, 1180 WM8994_AIF2ADCL_ENA | 1181 WM8994_AIF2ADCR_ENA); 1182 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1183 WM8994_AIF2DACL_ENA | 1184 WM8994_AIF2DACR_ENA, 1185 WM8994_AIF2DACL_ENA | 1186 WM8994_AIF2DACR_ENA); 1187 break; 1188 1189 case SND_SOC_DAPM_POST_PMU: 1190 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1191 snd_soc_component_write(component, wm8994_vu_bits[i].reg, 1192 snd_soc_component_read32(component, 1193 wm8994_vu_bits[i].reg)); 1194 break; 1195 1196 case SND_SOC_DAPM_PRE_PMD: 1197 case SND_SOC_DAPM_POST_PMD: 1198 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1199 WM8994_AIF2DACL_ENA | 1200 WM8994_AIF2DACR_ENA, 0); 1201 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1202 WM8994_AIF2ADCL_ENA | 1203 WM8994_AIF2ADCR_ENA, 0); 1204 1205 val = snd_soc_component_read32(component, WM8994_CLOCKING_1); 1206 if (val & WM8994_AIF1DSPCLK_ENA) 1207 val = WM8994_SYSDSPCLK_ENA; 1208 else 1209 val = 0; 1210 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1211 WM8994_SYSDSPCLK_ENA | 1212 WM8994_AIF2DSPCLK_ENA, val); 1213 break; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1220 struct snd_kcontrol *kcontrol, int event) 1221 { 1222 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1223 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1224 1225 switch (event) { 1226 case SND_SOC_DAPM_PRE_PMU: 1227 wm8994->aif1clk_enable = 1; 1228 break; 1229 case SND_SOC_DAPM_POST_PMD: 1230 wm8994->aif1clk_disable = 1; 1231 break; 1232 } 1233 1234 return 0; 1235 } 1236 1237 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1238 struct snd_kcontrol *kcontrol, int event) 1239 { 1240 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1241 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1242 1243 switch (event) { 1244 case SND_SOC_DAPM_PRE_PMU: 1245 wm8994->aif2clk_enable = 1; 1246 break; 1247 case SND_SOC_DAPM_POST_PMD: 1248 wm8994->aif2clk_disable = 1; 1249 break; 1250 } 1251 1252 return 0; 1253 } 1254 1255 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1256 struct snd_kcontrol *kcontrol, int event) 1257 { 1258 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1259 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1260 1261 switch (event) { 1262 case SND_SOC_DAPM_PRE_PMU: 1263 if (wm8994->aif1clk_enable) { 1264 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1265 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1266 WM8994_AIF1CLK_ENA_MASK, 1267 WM8994_AIF1CLK_ENA); 1268 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1269 wm8994->aif1clk_enable = 0; 1270 } 1271 if (wm8994->aif2clk_enable) { 1272 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1273 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1274 WM8994_AIF2CLK_ENA_MASK, 1275 WM8994_AIF2CLK_ENA); 1276 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1277 wm8994->aif2clk_enable = 0; 1278 } 1279 break; 1280 } 1281 1282 /* We may also have postponed startup of DSP, handle that. */ 1283 wm8958_aif_ev(w, kcontrol, event); 1284 1285 return 0; 1286 } 1287 1288 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1289 struct snd_kcontrol *kcontrol, int event) 1290 { 1291 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1292 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1293 1294 switch (event) { 1295 case SND_SOC_DAPM_POST_PMD: 1296 if (wm8994->aif1clk_disable) { 1297 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1298 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1299 WM8994_AIF1CLK_ENA_MASK, 0); 1300 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1301 wm8994->aif1clk_disable = 0; 1302 } 1303 if (wm8994->aif2clk_disable) { 1304 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1305 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1306 WM8994_AIF2CLK_ENA_MASK, 0); 1307 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1308 wm8994->aif2clk_disable = 0; 1309 } 1310 break; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1317 struct snd_kcontrol *kcontrol, int event) 1318 { 1319 late_enable_ev(w, kcontrol, event); 1320 return 0; 1321 } 1322 1323 static int micbias_ev(struct snd_soc_dapm_widget *w, 1324 struct snd_kcontrol *kcontrol, int event) 1325 { 1326 late_enable_ev(w, kcontrol, event); 1327 return 0; 1328 } 1329 1330 static int dac_ev(struct snd_soc_dapm_widget *w, 1331 struct snd_kcontrol *kcontrol, int event) 1332 { 1333 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1334 unsigned int mask = 1 << w->shift; 1335 1336 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1337 mask, mask); 1338 return 0; 1339 } 1340 1341 static const char *adc_mux_text[] = { 1342 "ADC", 1343 "DMIC", 1344 }; 1345 1346 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 1347 1348 static const struct snd_kcontrol_new adcl_mux = 1349 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 1350 1351 static const struct snd_kcontrol_new adcr_mux = 1352 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 1353 1354 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1355 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1356 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1357 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1358 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1359 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1360 }; 1361 1362 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1363 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1364 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1365 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1366 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1367 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1368 }; 1369 1370 /* Debugging; dump chip status after DAPM transitions */ 1371 static int post_ev(struct snd_soc_dapm_widget *w, 1372 struct snd_kcontrol *kcontrol, int event) 1373 { 1374 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1375 dev_dbg(component->dev, "SRC status: %x\n", 1376 snd_soc_component_read32(component, 1377 WM8994_RATE_STATUS)); 1378 return 0; 1379 } 1380 1381 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1382 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1383 1, 1, 0), 1384 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1385 0, 1, 0), 1386 }; 1387 1388 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1389 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1390 1, 1, 0), 1391 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1392 0, 1, 0), 1393 }; 1394 1395 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1396 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1397 1, 1, 0), 1398 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1399 0, 1, 0), 1400 }; 1401 1402 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1403 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1404 1, 1, 0), 1405 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1406 0, 1, 0), 1407 }; 1408 1409 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1410 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1411 5, 1, 0), 1412 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1413 4, 1, 0), 1414 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1415 2, 1, 0), 1416 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1417 1, 1, 0), 1418 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1419 0, 1, 0), 1420 }; 1421 1422 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1423 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1424 5, 1, 0), 1425 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1426 4, 1, 0), 1427 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1428 2, 1, 0), 1429 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1430 1, 1, 0), 1431 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1432 0, 1, 0), 1433 }; 1434 1435 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1436 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 1437 snd_soc_dapm_get_volsw, wm8994_put_class_w) 1438 1439 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1440 struct snd_ctl_elem_value *ucontrol) 1441 { 1442 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 1443 int ret; 1444 1445 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1446 1447 wm_hubs_update_class_w(component); 1448 1449 return ret; 1450 } 1451 1452 static const struct snd_kcontrol_new dac1l_mix[] = { 1453 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1454 5, 1, 0), 1455 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1456 4, 1, 0), 1457 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1458 2, 1, 0), 1459 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1460 1, 1, 0), 1461 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1462 0, 1, 0), 1463 }; 1464 1465 static const struct snd_kcontrol_new dac1r_mix[] = { 1466 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1467 5, 1, 0), 1468 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1469 4, 1, 0), 1470 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1471 2, 1, 0), 1472 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1473 1, 1, 0), 1474 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1475 0, 1, 0), 1476 }; 1477 1478 static const char *sidetone_text[] = { 1479 "ADC/DMIC1", "DMIC2", 1480 }; 1481 1482 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, 1483 WM8994_SIDETONE, 0, sidetone_text); 1484 1485 static const struct snd_kcontrol_new sidetone1_mux = 1486 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1487 1488 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, 1489 WM8994_SIDETONE, 1, sidetone_text); 1490 1491 static const struct snd_kcontrol_new sidetone2_mux = 1492 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1493 1494 static const char *aif1dac_text[] = { 1495 "AIF1DACDAT", "AIF3DACDAT", 1496 }; 1497 1498 static const char *loopback_text[] = { 1499 "None", "ADCDAT", 1500 }; 1501 1502 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum, 1503 WM8994_AIF1_CONTROL_2, 1504 WM8994_AIF1_LOOPBACK_SHIFT, 1505 loopback_text); 1506 1507 static const struct snd_kcontrol_new aif1_loopback = 1508 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum); 1509 1510 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum, 1511 WM8994_AIF2_CONTROL_2, 1512 WM8994_AIF2_LOOPBACK_SHIFT, 1513 loopback_text); 1514 1515 static const struct snd_kcontrol_new aif2_loopback = 1516 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum); 1517 1518 static SOC_ENUM_SINGLE_DECL(aif1dac_enum, 1519 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text); 1520 1521 static const struct snd_kcontrol_new aif1dac_mux = 1522 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1523 1524 static const char *aif2dac_text[] = { 1525 "AIF2DACDAT", "AIF3DACDAT", 1526 }; 1527 1528 static SOC_ENUM_SINGLE_DECL(aif2dac_enum, 1529 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text); 1530 1531 static const struct snd_kcontrol_new aif2dac_mux = 1532 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1533 1534 static const char *aif2adc_text[] = { 1535 "AIF2ADCDAT", "AIF3DACDAT", 1536 }; 1537 1538 static SOC_ENUM_SINGLE_DECL(aif2adc_enum, 1539 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text); 1540 1541 static const struct snd_kcontrol_new aif2adc_mux = 1542 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1543 1544 static const char *aif3adc_text[] = { 1545 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1546 }; 1547 1548 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum, 1549 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1550 1551 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1552 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1553 1554 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum, 1555 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1556 1557 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1558 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1559 1560 static const char *mono_pcm_out_text[] = { 1561 "None", "AIF2ADCL", "AIF2ADCR", 1562 }; 1563 1564 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum, 1565 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text); 1566 1567 static const struct snd_kcontrol_new mono_pcm_out_mux = 1568 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1569 1570 static const char *aif2dac_src_text[] = { 1571 "AIF2", "AIF3", 1572 }; 1573 1574 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1575 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum, 1576 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text); 1577 1578 static const struct snd_kcontrol_new aif2dacl_src_mux = 1579 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1580 1581 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum, 1582 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text); 1583 1584 static const struct snd_kcontrol_new aif2dacr_src_mux = 1585 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1586 1587 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1588 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1590 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1592 1593 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1594 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1595 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1597 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1599 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1601 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1602 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1603 1604 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1605 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1606 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1607 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1608 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1609 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1610 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1612 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1614 1615 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1616 }; 1617 1618 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1619 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1621 SND_SOC_DAPM_PRE_PMD), 1622 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1624 SND_SOC_DAPM_PRE_PMD), 1625 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1626 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1627 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1628 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1629 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1630 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1631 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1632 }; 1633 1634 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1635 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1636 dac_ev, SND_SOC_DAPM_PRE_PMU), 1637 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1638 dac_ev, SND_SOC_DAPM_PRE_PMU), 1639 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1640 dac_ev, SND_SOC_DAPM_PRE_PMU), 1641 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1642 dac_ev, SND_SOC_DAPM_PRE_PMU), 1643 }; 1644 1645 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1646 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1647 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1648 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1649 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1650 }; 1651 1652 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1653 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1654 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1655 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1656 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1657 }; 1658 1659 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1660 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1661 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1662 }; 1663 1664 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1665 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1666 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1667 SND_SOC_DAPM_INPUT("Clock"), 1668 1669 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1670 SND_SOC_DAPM_PRE_PMU), 1671 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1673 1674 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1676 SND_SOC_DAPM_PRE_PMD), 1677 1678 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1679 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1680 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1681 1682 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1683 0, SND_SOC_NOPM, 9, 0), 1684 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1685 0, SND_SOC_NOPM, 8, 0), 1686 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1687 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1688 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1689 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1690 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1691 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1692 1693 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1694 0, SND_SOC_NOPM, 11, 0), 1695 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1696 0, SND_SOC_NOPM, 10, 0), 1697 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1698 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1699 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1700 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1701 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1702 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1703 1704 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1705 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1706 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1707 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1708 1709 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1710 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1711 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1712 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1713 1714 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1715 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1716 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1717 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1718 1719 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1720 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1721 1722 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1723 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1724 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1725 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1726 1727 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1728 SND_SOC_NOPM, 13, 0), 1729 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1730 SND_SOC_NOPM, 12, 0), 1731 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1732 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1733 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1734 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1735 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1736 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1737 1738 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1739 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1740 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1741 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1742 1743 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1744 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1745 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1746 1747 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1748 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1749 1750 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1751 1752 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1753 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1754 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1755 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1756 1757 /* Power is done with the muxes since the ADC power also controls the 1758 * downsampling chain, the chip will automatically manage the analogue 1759 * specific portions. 1760 */ 1761 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1762 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1763 1764 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback), 1765 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback), 1766 1767 SND_SOC_DAPM_POST("Debug log", post_ev), 1768 }; 1769 1770 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1771 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1772 }; 1773 1774 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1775 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1776 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1777 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1778 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1779 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1780 }; 1781 1782 static const struct snd_soc_dapm_route intercon[] = { 1783 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1784 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1785 1786 { "DSP1CLK", NULL, "CLK_SYS" }, 1787 { "DSP2CLK", NULL, "CLK_SYS" }, 1788 { "DSPINTCLK", NULL, "CLK_SYS" }, 1789 1790 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1791 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1792 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1793 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1794 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1795 1796 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1797 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1798 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1799 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1800 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1801 1802 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1803 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1804 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1805 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1806 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1807 1808 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1809 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1810 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1811 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1812 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1813 1814 { "AIF2ADCL", NULL, "AIF2CLK" }, 1815 { "AIF2ADCL", NULL, "DSP2CLK" }, 1816 { "AIF2ADCR", NULL, "AIF2CLK" }, 1817 { "AIF2ADCR", NULL, "DSP2CLK" }, 1818 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1819 1820 { "AIF2DACL", NULL, "AIF2CLK" }, 1821 { "AIF2DACL", NULL, "DSP2CLK" }, 1822 { "AIF2DACR", NULL, "AIF2CLK" }, 1823 { "AIF2DACR", NULL, "DSP2CLK" }, 1824 { "AIF2DACR", NULL, "DSPINTCLK" }, 1825 1826 { "DMIC1L", NULL, "DMIC1DAT" }, 1827 { "DMIC1L", NULL, "CLK_SYS" }, 1828 { "DMIC1R", NULL, "DMIC1DAT" }, 1829 { "DMIC1R", NULL, "CLK_SYS" }, 1830 { "DMIC2L", NULL, "DMIC2DAT" }, 1831 { "DMIC2L", NULL, "CLK_SYS" }, 1832 { "DMIC2R", NULL, "DMIC2DAT" }, 1833 { "DMIC2R", NULL, "CLK_SYS" }, 1834 1835 { "ADCL", NULL, "AIF1CLK" }, 1836 { "ADCL", NULL, "DSP1CLK" }, 1837 { "ADCL", NULL, "DSPINTCLK" }, 1838 1839 { "ADCR", NULL, "AIF1CLK" }, 1840 { "ADCR", NULL, "DSP1CLK" }, 1841 { "ADCR", NULL, "DSPINTCLK" }, 1842 1843 { "ADCL Mux", "ADC", "ADCL" }, 1844 { "ADCL Mux", "DMIC", "DMIC1L" }, 1845 { "ADCR Mux", "ADC", "ADCR" }, 1846 { "ADCR Mux", "DMIC", "DMIC1R" }, 1847 1848 { "DAC1L", NULL, "AIF1CLK" }, 1849 { "DAC1L", NULL, "DSP1CLK" }, 1850 { "DAC1L", NULL, "DSPINTCLK" }, 1851 1852 { "DAC1R", NULL, "AIF1CLK" }, 1853 { "DAC1R", NULL, "DSP1CLK" }, 1854 { "DAC1R", NULL, "DSPINTCLK" }, 1855 1856 { "DAC2L", NULL, "AIF2CLK" }, 1857 { "DAC2L", NULL, "DSP2CLK" }, 1858 { "DAC2L", NULL, "DSPINTCLK" }, 1859 1860 { "DAC2R", NULL, "AIF2DACR" }, 1861 { "DAC2R", NULL, "AIF2CLK" }, 1862 { "DAC2R", NULL, "DSP2CLK" }, 1863 { "DAC2R", NULL, "DSPINTCLK" }, 1864 1865 { "TOCLK", NULL, "CLK_SYS" }, 1866 1867 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1868 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1869 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1870 1871 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1872 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1873 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1874 1875 /* AIF1 outputs */ 1876 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1877 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1878 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1879 1880 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1881 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1882 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1883 1884 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1885 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1886 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1887 1888 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1889 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1890 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1891 1892 /* Pin level routing for AIF3 */ 1893 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1894 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1895 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1896 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1897 1898 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" }, 1899 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1900 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" }, 1901 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1902 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1903 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1904 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1905 1906 /* DAC1 inputs */ 1907 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1908 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1909 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1910 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1911 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1912 1913 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1914 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1915 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1916 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1917 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1918 1919 /* DAC2/AIF2 outputs */ 1920 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1921 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1922 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1923 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1924 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1925 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1926 1927 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1928 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1929 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1930 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1931 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1932 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1933 1934 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1935 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1936 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1937 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1938 1939 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1940 1941 /* AIF3 output */ 1942 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" }, 1943 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" }, 1944 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" }, 1945 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" }, 1946 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1947 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1948 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" }, 1949 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" }, 1950 1951 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" }, 1952 1953 /* Loopback */ 1954 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" }, 1955 { "AIF1 Loopback", "None", "AIF1DACDAT" }, 1956 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" }, 1957 { "AIF2 Loopback", "None", "AIF2DACDAT" }, 1958 1959 /* Sidetone */ 1960 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1961 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1962 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1963 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1964 1965 /* Output stages */ 1966 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1967 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1968 1969 { "SPKL", "DAC1 Switch", "DAC1L" }, 1970 { "SPKL", "DAC2 Switch", "DAC2L" }, 1971 1972 { "SPKR", "DAC1 Switch", "DAC1R" }, 1973 { "SPKR", "DAC2 Switch", "DAC2R" }, 1974 1975 { "Left Headphone Mux", "DAC", "DAC1L" }, 1976 { "Right Headphone Mux", "DAC", "DAC1R" }, 1977 }; 1978 1979 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1980 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1981 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1982 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1983 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1984 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1985 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1986 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1987 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1988 }; 1989 1990 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1991 { "DAC1L", NULL, "DAC1L Mixer" }, 1992 { "DAC1R", NULL, "DAC1R Mixer" }, 1993 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1994 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1995 }; 1996 1997 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1998 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1999 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 2000 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 2001 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 2002 { "MICBIAS1", NULL, "CLK_SYS" }, 2003 { "MICBIAS1", NULL, "MICBIAS Supply" }, 2004 { "MICBIAS2", NULL, "CLK_SYS" }, 2005 { "MICBIAS2", NULL, "MICBIAS Supply" }, 2006 }; 2007 2008 static const struct snd_soc_dapm_route wm8994_intercon[] = { 2009 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2010 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2011 { "MICBIAS1", NULL, "VMID" }, 2012 { "MICBIAS2", NULL, "VMID" }, 2013 }; 2014 2015 static const struct snd_soc_dapm_route wm8958_intercon[] = { 2016 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 2017 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 2018 2019 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 2020 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 2021 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 2022 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 2023 2024 { "AIF3DACDAT", NULL, "AIF3" }, 2025 { "AIF3ADCDAT", NULL, "AIF3" }, 2026 2027 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2028 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2029 2030 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2031 }; 2032 2033 /* The size in bits of the FLL divide multiplied by 10 2034 * to allow rounding later */ 2035 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2036 2037 struct fll_div { 2038 u16 outdiv; 2039 u16 n; 2040 u16 k; 2041 u16 lambda; 2042 u16 clk_ref_div; 2043 u16 fll_fratio; 2044 }; 2045 2046 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll, 2047 int freq_in, int freq_out) 2048 { 2049 u64 Kpart; 2050 unsigned int K, Ndiv, Nmod, gcd_fll; 2051 2052 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2053 2054 /* Scale the input frequency down to <= 13.5MHz */ 2055 fll->clk_ref_div = 0; 2056 while (freq_in > 13500000) { 2057 fll->clk_ref_div++; 2058 freq_in /= 2; 2059 2060 if (fll->clk_ref_div > 3) 2061 return -EINVAL; 2062 } 2063 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2064 2065 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2066 fll->outdiv = 3; 2067 while (freq_out * (fll->outdiv + 1) < 90000000) { 2068 fll->outdiv++; 2069 if (fll->outdiv > 63) 2070 return -EINVAL; 2071 } 2072 freq_out *= fll->outdiv + 1; 2073 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2074 2075 if (freq_in > 1000000) { 2076 fll->fll_fratio = 0; 2077 } else if (freq_in > 256000) { 2078 fll->fll_fratio = 1; 2079 freq_in *= 2; 2080 } else if (freq_in > 128000) { 2081 fll->fll_fratio = 2; 2082 freq_in *= 4; 2083 } else if (freq_in > 64000) { 2084 fll->fll_fratio = 3; 2085 freq_in *= 8; 2086 } else { 2087 fll->fll_fratio = 4; 2088 freq_in *= 16; 2089 } 2090 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2091 2092 /* Now, calculate N.K */ 2093 Ndiv = freq_out / freq_in; 2094 2095 fll->n = Ndiv; 2096 Nmod = freq_out % freq_in; 2097 pr_debug("Nmod=%d\n", Nmod); 2098 2099 switch (control->type) { 2100 case WM8994: 2101 /* Calculate fractional part - scale up so we can round. */ 2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2103 2104 do_div(Kpart, freq_in); 2105 2106 K = Kpart & 0xFFFFFFFF; 2107 2108 if ((K % 10) >= 5) 2109 K += 5; 2110 2111 /* Move down to proper range now rounding is done */ 2112 fll->k = K / 10; 2113 fll->lambda = 0; 2114 2115 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2116 break; 2117 2118 default: 2119 gcd_fll = gcd(freq_out, freq_in); 2120 2121 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; 2122 fll->lambda = freq_in / gcd_fll; 2123 2124 } 2125 2126 return 0; 2127 } 2128 2129 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, 2130 unsigned int freq_in, unsigned int freq_out) 2131 { 2132 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2133 struct wm8994 *control = wm8994->wm8994; 2134 int reg_offset, ret; 2135 struct fll_div fll; 2136 u16 reg, clk1, aif_reg, aif_src; 2137 unsigned long timeout; 2138 bool was_enabled; 2139 2140 switch (id) { 2141 case WM8994_FLL1: 2142 reg_offset = 0; 2143 id = 0; 2144 aif_src = 0x10; 2145 break; 2146 case WM8994_FLL2: 2147 reg_offset = 0x20; 2148 id = 1; 2149 aif_src = 0x18; 2150 break; 2151 default: 2152 return -EINVAL; 2153 } 2154 2155 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset); 2156 was_enabled = reg & WM8994_FLL1_ENA; 2157 2158 switch (src) { 2159 case 0: 2160 /* Allow no source specification when stopping */ 2161 if (freq_out) 2162 return -EINVAL; 2163 src = wm8994->fll[id].src; 2164 break; 2165 case WM8994_FLL_SRC_MCLK1: 2166 case WM8994_FLL_SRC_MCLK2: 2167 case WM8994_FLL_SRC_LRCLK: 2168 case WM8994_FLL_SRC_BCLK: 2169 break; 2170 case WM8994_FLL_SRC_INTERNAL: 2171 freq_in = 12000000; 2172 freq_out = 12000000; 2173 break; 2174 default: 2175 return -EINVAL; 2176 } 2177 2178 /* Are we changing anything? */ 2179 if (wm8994->fll[id].src == src && 2180 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2181 return 0; 2182 2183 /* If we're stopping the FLL redo the old config - no 2184 * registers will actually be written but we avoid GCC flow 2185 * analysis bugs spewing warnings. 2186 */ 2187 if (freq_out) 2188 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out); 2189 else 2190 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in, 2191 wm8994->fll[id].out); 2192 if (ret < 0) 2193 return ret; 2194 2195 /* Make sure that we're not providing SYSCLK right now */ 2196 clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1); 2197 if (clk1 & WM8994_SYSCLK_SRC) 2198 aif_reg = WM8994_AIF2_CLOCKING_1; 2199 else 2200 aif_reg = WM8994_AIF1_CLOCKING_1; 2201 reg = snd_soc_component_read32(component, aif_reg); 2202 2203 if ((reg & WM8994_AIF1CLK_ENA) && 2204 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2205 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n", 2206 id + 1); 2207 return -EBUSY; 2208 } 2209 2210 /* We always need to disable the FLL while reconfiguring */ 2211 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2212 WM8994_FLL1_ENA, 0); 2213 2214 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2215 freq_in == freq_out && freq_out) { 2216 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1); 2217 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2218 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2219 goto out; 2220 } 2221 2222 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2223 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2224 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset, 2225 WM8994_FLL1_OUTDIV_MASK | 2226 WM8994_FLL1_FRATIO_MASK, reg); 2227 2228 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset, 2229 WM8994_FLL1_K_MASK, fll.k); 2230 2231 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset, 2232 WM8994_FLL1_N_MASK, 2233 fll.n << WM8994_FLL1_N_SHIFT); 2234 2235 if (fll.lambda) { 2236 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset, 2237 WM8958_FLL1_LAMBDA_MASK, 2238 fll.lambda); 2239 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2240 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA); 2241 } else { 2242 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2243 WM8958_FLL1_EFS_ENA, 0); 2244 } 2245 2246 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2247 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2248 WM8994_FLL1_REFCLK_DIV_MASK | 2249 WM8994_FLL1_REFCLK_SRC_MASK, 2250 ((src == WM8994_FLL_SRC_INTERNAL) 2251 << WM8994_FLL1_FRC_NCO_SHIFT) | 2252 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2253 (src - 1)); 2254 2255 /* Clear any pending completion from a previous failure */ 2256 try_wait_for_completion(&wm8994->fll_locked[id]); 2257 2258 /* Enable (with fractional mode if required) */ 2259 if (freq_out) { 2260 /* Enable VMID if we need it */ 2261 if (!was_enabled) { 2262 active_reference(component); 2263 2264 switch (control->type) { 2265 case WM8994: 2266 vmid_reference(component); 2267 break; 2268 case WM8958: 2269 if (control->revision < 1) 2270 vmid_reference(component); 2271 break; 2272 default: 2273 break; 2274 } 2275 } 2276 2277 reg = WM8994_FLL1_ENA; 2278 2279 if (fll.k) 2280 reg |= WM8994_FLL1_FRAC; 2281 if (src == WM8994_FLL_SRC_INTERNAL) 2282 reg |= WM8994_FLL1_OSC_ENA; 2283 2284 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2285 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2286 WM8994_FLL1_FRAC, reg); 2287 2288 if (wm8994->fll_locked_irq) { 2289 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2290 msecs_to_jiffies(10)); 2291 if (timeout == 0) 2292 dev_warn(component->dev, 2293 "Timed out waiting for FLL lock\n"); 2294 } else { 2295 msleep(5); 2296 } 2297 } else { 2298 if (was_enabled) { 2299 switch (control->type) { 2300 case WM8994: 2301 vmid_dereference(component); 2302 break; 2303 case WM8958: 2304 if (control->revision < 1) 2305 vmid_dereference(component); 2306 break; 2307 default: 2308 break; 2309 } 2310 2311 active_dereference(component); 2312 } 2313 } 2314 2315 out: 2316 wm8994->fll[id].in = freq_in; 2317 wm8994->fll[id].out = freq_out; 2318 wm8994->fll[id].src = src; 2319 2320 configure_clock(component); 2321 2322 /* 2323 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2324 * for detection. 2325 */ 2326 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2327 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2328 2329 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE) 2330 & WM8994_AIF1CLK_RATE_MASK; 2331 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE) 2332 & WM8994_AIF1CLK_RATE_MASK; 2333 2334 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2335 WM8994_AIF1CLK_RATE_MASK, 0x1); 2336 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2337 WM8994_AIF2CLK_RATE_MASK, 0x1); 2338 } else if (wm8994->aifdiv[0]) { 2339 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2340 WM8994_AIF1CLK_RATE_MASK, 2341 wm8994->aifdiv[0]); 2342 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2343 WM8994_AIF2CLK_RATE_MASK, 2344 wm8994->aifdiv[1]); 2345 2346 wm8994->aifdiv[0] = 0; 2347 wm8994->aifdiv[1] = 0; 2348 } 2349 2350 return 0; 2351 } 2352 2353 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2354 { 2355 struct completion *completion = data; 2356 2357 complete(completion); 2358 2359 return IRQ_HANDLED; 2360 } 2361 2362 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2363 2364 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2365 unsigned int freq_in, unsigned int freq_out) 2366 { 2367 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out); 2368 } 2369 2370 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2371 int clk_id, unsigned int freq, int dir) 2372 { 2373 struct snd_soc_component *component = dai->component; 2374 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2375 int i; 2376 2377 switch (dai->id) { 2378 case 1: 2379 case 2: 2380 break; 2381 2382 default: 2383 /* AIF3 shares clocking with AIF1/2 */ 2384 return -EINVAL; 2385 } 2386 2387 switch (clk_id) { 2388 case WM8994_SYSCLK_MCLK1: 2389 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2390 wm8994->mclk[0] = freq; 2391 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2392 dai->id, freq); 2393 break; 2394 2395 case WM8994_SYSCLK_MCLK2: 2396 /* TODO: Set GPIO AF */ 2397 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2398 wm8994->mclk[1] = freq; 2399 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2400 dai->id, freq); 2401 break; 2402 2403 case WM8994_SYSCLK_FLL1: 2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2405 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2406 break; 2407 2408 case WM8994_SYSCLK_FLL2: 2409 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2410 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2411 break; 2412 2413 case WM8994_SYSCLK_OPCLK: 2414 /* Special case - a division (times 10) is given and 2415 * no effect on main clocking. 2416 */ 2417 if (freq) { 2418 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2419 if (opclk_divs[i] == freq) 2420 break; 2421 if (i == ARRAY_SIZE(opclk_divs)) 2422 return -EINVAL; 2423 snd_soc_component_update_bits(component, WM8994_CLOCKING_2, 2424 WM8994_OPCLK_DIV_MASK, i); 2425 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2426 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2427 } else { 2428 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2429 WM8994_OPCLK_ENA, 0); 2430 } 2431 break; 2432 2433 default: 2434 return -EINVAL; 2435 } 2436 2437 configure_clock(component); 2438 2439 /* 2440 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2441 * for detection. 2442 */ 2443 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2444 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2445 2446 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE) 2447 & WM8994_AIF1CLK_RATE_MASK; 2448 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE) 2449 & WM8994_AIF1CLK_RATE_MASK; 2450 2451 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2452 WM8994_AIF1CLK_RATE_MASK, 0x1); 2453 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2454 WM8994_AIF2CLK_RATE_MASK, 0x1); 2455 } else if (wm8994->aifdiv[0]) { 2456 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2457 WM8994_AIF1CLK_RATE_MASK, 2458 wm8994->aifdiv[0]); 2459 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2460 WM8994_AIF2CLK_RATE_MASK, 2461 wm8994->aifdiv[1]); 2462 2463 wm8994->aifdiv[0] = 0; 2464 wm8994->aifdiv[1] = 0; 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int wm8994_set_bias_level(struct snd_soc_component *component, 2471 enum snd_soc_bias_level level) 2472 { 2473 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2474 struct wm8994 *control = wm8994->wm8994; 2475 2476 wm_hubs_set_bias_level(component, level); 2477 2478 switch (level) { 2479 case SND_SOC_BIAS_ON: 2480 break; 2481 2482 case SND_SOC_BIAS_PREPARE: 2483 /* MICBIAS into regulating mode */ 2484 switch (control->type) { 2485 case WM8958: 2486 case WM1811: 2487 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2488 WM8958_MICB1_MODE, 0); 2489 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2490 WM8958_MICB2_MODE, 0); 2491 break; 2492 default: 2493 break; 2494 } 2495 2496 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 2497 active_reference(component); 2498 break; 2499 2500 case SND_SOC_BIAS_STANDBY: 2501 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2502 switch (control->type) { 2503 case WM8958: 2504 if (control->revision == 0) { 2505 /* Optimise performance for rev A */ 2506 snd_soc_component_update_bits(component, 2507 WM8958_CHARGE_PUMP_2, 2508 WM8958_CP_DISCH, 2509 WM8958_CP_DISCH); 2510 } 2511 break; 2512 2513 default: 2514 break; 2515 } 2516 2517 /* Discharge LINEOUT1 & 2 */ 2518 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 2519 WM8994_LINEOUT1_DISCH | 2520 WM8994_LINEOUT2_DISCH, 2521 WM8994_LINEOUT1_DISCH | 2522 WM8994_LINEOUT2_DISCH); 2523 } 2524 2525 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) 2526 active_dereference(component); 2527 2528 /* MICBIAS into bypass mode on newer devices */ 2529 switch (control->type) { 2530 case WM8958: 2531 case WM1811: 2532 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2533 WM8958_MICB1_MODE, 2534 WM8958_MICB1_MODE); 2535 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2536 WM8958_MICB2_MODE, 2537 WM8958_MICB2_MODE); 2538 break; 2539 default: 2540 break; 2541 } 2542 break; 2543 2544 case SND_SOC_BIAS_OFF: 2545 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 2546 wm8994->cur_fw = NULL; 2547 break; 2548 } 2549 2550 return 0; 2551 } 2552 2553 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode) 2554 { 2555 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2556 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2557 2558 switch (mode) { 2559 case WM8994_VMID_NORMAL: 2560 snd_soc_dapm_mutex_lock(dapm); 2561 2562 if (wm8994->hubs.lineout1_se) { 2563 snd_soc_dapm_disable_pin_unlocked(dapm, 2564 "LINEOUT1N Driver"); 2565 snd_soc_dapm_disable_pin_unlocked(dapm, 2566 "LINEOUT1P Driver"); 2567 } 2568 if (wm8994->hubs.lineout2_se) { 2569 snd_soc_dapm_disable_pin_unlocked(dapm, 2570 "LINEOUT2N Driver"); 2571 snd_soc_dapm_disable_pin_unlocked(dapm, 2572 "LINEOUT2P Driver"); 2573 } 2574 2575 /* Do the sync with the old mode to allow it to clean up */ 2576 snd_soc_dapm_sync_unlocked(dapm); 2577 wm8994->vmid_mode = mode; 2578 2579 snd_soc_dapm_mutex_unlock(dapm); 2580 break; 2581 2582 case WM8994_VMID_FORCE: 2583 snd_soc_dapm_mutex_lock(dapm); 2584 2585 if (wm8994->hubs.lineout1_se) { 2586 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2587 "LINEOUT1N Driver"); 2588 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2589 "LINEOUT1P Driver"); 2590 } 2591 if (wm8994->hubs.lineout2_se) { 2592 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2593 "LINEOUT2N Driver"); 2594 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2595 "LINEOUT2P Driver"); 2596 } 2597 2598 wm8994->vmid_mode = mode; 2599 snd_soc_dapm_sync_unlocked(dapm); 2600 2601 snd_soc_dapm_mutex_unlock(dapm); 2602 break; 2603 2604 default: 2605 return -EINVAL; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2612 { 2613 struct snd_soc_component *component = dai->component; 2614 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2615 struct wm8994 *control = wm8994->wm8994; 2616 int ms_reg; 2617 int aif1_reg; 2618 int dac_reg; 2619 int adc_reg; 2620 int ms = 0; 2621 int aif1 = 0; 2622 int lrclk = 0; 2623 2624 switch (dai->id) { 2625 case 1: 2626 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2627 aif1_reg = WM8994_AIF1_CONTROL_1; 2628 dac_reg = WM8994_AIF1DAC_LRCLK; 2629 adc_reg = WM8994_AIF1ADC_LRCLK; 2630 break; 2631 case 2: 2632 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2633 aif1_reg = WM8994_AIF2_CONTROL_1; 2634 dac_reg = WM8994_AIF1DAC_LRCLK; 2635 adc_reg = WM8994_AIF1ADC_LRCLK; 2636 break; 2637 default: 2638 return -EINVAL; 2639 } 2640 2641 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2642 case SND_SOC_DAIFMT_CBS_CFS: 2643 break; 2644 case SND_SOC_DAIFMT_CBM_CFM: 2645 ms = WM8994_AIF1_MSTR; 2646 break; 2647 default: 2648 return -EINVAL; 2649 } 2650 2651 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2652 case SND_SOC_DAIFMT_DSP_B: 2653 aif1 |= WM8994_AIF1_LRCLK_INV; 2654 lrclk |= WM8958_AIF1_LRCLK_INV; 2655 /* fall through */ 2656 case SND_SOC_DAIFMT_DSP_A: 2657 aif1 |= 0x18; 2658 break; 2659 case SND_SOC_DAIFMT_I2S: 2660 aif1 |= 0x10; 2661 break; 2662 case SND_SOC_DAIFMT_RIGHT_J: 2663 break; 2664 case SND_SOC_DAIFMT_LEFT_J: 2665 aif1 |= 0x8; 2666 break; 2667 default: 2668 return -EINVAL; 2669 } 2670 2671 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2672 case SND_SOC_DAIFMT_DSP_A: 2673 case SND_SOC_DAIFMT_DSP_B: 2674 /* frame inversion not valid for DSP modes */ 2675 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2676 case SND_SOC_DAIFMT_NB_NF: 2677 break; 2678 case SND_SOC_DAIFMT_IB_NF: 2679 aif1 |= WM8994_AIF1_BCLK_INV; 2680 break; 2681 default: 2682 return -EINVAL; 2683 } 2684 break; 2685 2686 case SND_SOC_DAIFMT_I2S: 2687 case SND_SOC_DAIFMT_RIGHT_J: 2688 case SND_SOC_DAIFMT_LEFT_J: 2689 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2690 case SND_SOC_DAIFMT_NB_NF: 2691 break; 2692 case SND_SOC_DAIFMT_IB_IF: 2693 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2694 lrclk |= WM8958_AIF1_LRCLK_INV; 2695 break; 2696 case SND_SOC_DAIFMT_IB_NF: 2697 aif1 |= WM8994_AIF1_BCLK_INV; 2698 break; 2699 case SND_SOC_DAIFMT_NB_IF: 2700 aif1 |= WM8994_AIF1_LRCLK_INV; 2701 lrclk |= WM8958_AIF1_LRCLK_INV; 2702 break; 2703 default: 2704 return -EINVAL; 2705 } 2706 break; 2707 default: 2708 return -EINVAL; 2709 } 2710 2711 /* The AIF2 format configuration needs to be mirrored to AIF3 2712 * on WM8958 if it's in use so just do it all the time. */ 2713 switch (control->type) { 2714 case WM1811: 2715 case WM8958: 2716 if (dai->id == 2) 2717 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1, 2718 WM8994_AIF1_LRCLK_INV | 2719 WM8958_AIF3_FMT_MASK, aif1); 2720 break; 2721 2722 default: 2723 break; 2724 } 2725 2726 snd_soc_component_update_bits(component, aif1_reg, 2727 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2728 WM8994_AIF1_FMT_MASK, 2729 aif1); 2730 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR, 2731 ms); 2732 snd_soc_component_update_bits(component, dac_reg, 2733 WM8958_AIF1_LRCLK_INV, lrclk); 2734 snd_soc_component_update_bits(component, adc_reg, 2735 WM8958_AIF1_LRCLK_INV, lrclk); 2736 2737 return 0; 2738 } 2739 2740 static struct { 2741 int val, rate; 2742 } srs[] = { 2743 { 0, 8000 }, 2744 { 1, 11025 }, 2745 { 2, 12000 }, 2746 { 3, 16000 }, 2747 { 4, 22050 }, 2748 { 5, 24000 }, 2749 { 6, 32000 }, 2750 { 7, 44100 }, 2751 { 8, 48000 }, 2752 { 9, 88200 }, 2753 { 10, 96000 }, 2754 }; 2755 2756 static int fs_ratios[] = { 2757 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 2758 }; 2759 2760 static int bclk_divs[] = { 2761 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2762 640, 880, 960, 1280, 1760, 1920 2763 }; 2764 2765 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2766 struct snd_pcm_hw_params *params, 2767 struct snd_soc_dai *dai) 2768 { 2769 struct snd_soc_component *component = dai->component; 2770 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2771 struct wm8994 *control = wm8994->wm8994; 2772 struct wm8994_pdata *pdata = &control->pdata; 2773 int aif1_reg; 2774 int aif2_reg; 2775 int bclk_reg; 2776 int lrclk_reg; 2777 int rate_reg; 2778 int aif1 = 0; 2779 int aif2 = 0; 2780 int bclk = 0; 2781 int lrclk = 0; 2782 int rate_val = 0; 2783 int id = dai->id - 1; 2784 2785 int i, cur_val, best_val, bclk_rate, best; 2786 2787 switch (dai->id) { 2788 case 1: 2789 aif1_reg = WM8994_AIF1_CONTROL_1; 2790 aif2_reg = WM8994_AIF1_CONTROL_2; 2791 bclk_reg = WM8994_AIF1_BCLK; 2792 rate_reg = WM8994_AIF1_RATE; 2793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2794 wm8994->lrclk_shared[0]) { 2795 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2796 } else { 2797 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2798 dev_dbg(component->dev, "AIF1 using split LRCLK\n"); 2799 } 2800 break; 2801 case 2: 2802 aif1_reg = WM8994_AIF2_CONTROL_1; 2803 aif2_reg = WM8994_AIF2_CONTROL_2; 2804 bclk_reg = WM8994_AIF2_BCLK; 2805 rate_reg = WM8994_AIF2_RATE; 2806 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2807 wm8994->lrclk_shared[1]) { 2808 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2809 } else { 2810 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2811 dev_dbg(component->dev, "AIF2 using split LRCLK\n"); 2812 } 2813 break; 2814 default: 2815 return -EINVAL; 2816 } 2817 2818 bclk_rate = params_rate(params); 2819 switch (params_width(params)) { 2820 case 16: 2821 bclk_rate *= 16; 2822 break; 2823 case 20: 2824 bclk_rate *= 20; 2825 aif1 |= 0x20; 2826 break; 2827 case 24: 2828 bclk_rate *= 24; 2829 aif1 |= 0x40; 2830 break; 2831 case 32: 2832 bclk_rate *= 32; 2833 aif1 |= 0x60; 2834 break; 2835 default: 2836 return -EINVAL; 2837 } 2838 2839 wm8994->channels[id] = params_channels(params); 2840 if (pdata->max_channels_clocked[id] && 2841 wm8994->channels[id] > pdata->max_channels_clocked[id]) { 2842 dev_dbg(dai->dev, "Constraining channels to %d from %d\n", 2843 pdata->max_channels_clocked[id], wm8994->channels[id]); 2844 wm8994->channels[id] = pdata->max_channels_clocked[id]; 2845 } 2846 2847 switch (wm8994->channels[id]) { 2848 case 1: 2849 case 2: 2850 bclk_rate *= 2; 2851 break; 2852 default: 2853 bclk_rate *= 4; 2854 break; 2855 } 2856 2857 /* Try to find an appropriate sample rate; look for an exact match. */ 2858 for (i = 0; i < ARRAY_SIZE(srs); i++) 2859 if (srs[i].rate == params_rate(params)) 2860 break; 2861 if (i == ARRAY_SIZE(srs)) 2862 return -EINVAL; 2863 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2864 2865 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2866 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2867 dai->id, wm8994->aifclk[id], bclk_rate); 2868 2869 if (wm8994->channels[id] == 1 && 2870 (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18) 2871 aif2 |= WM8994_AIF1_MONO; 2872 2873 if (wm8994->aifclk[id] == 0) { 2874 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2875 return -EINVAL; 2876 } 2877 2878 /* AIFCLK/fs ratio; look for a close match in either direction */ 2879 best = 0; 2880 best_val = abs((fs_ratios[0] * params_rate(params)) 2881 - wm8994->aifclk[id]); 2882 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2883 cur_val = abs((fs_ratios[i] * params_rate(params)) 2884 - wm8994->aifclk[id]); 2885 if (cur_val >= best_val) 2886 continue; 2887 best = i; 2888 best_val = cur_val; 2889 } 2890 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2891 dai->id, fs_ratios[best]); 2892 rate_val |= best; 2893 2894 /* We may not get quite the right frequency if using 2895 * approximate clocks so look for the closest match that is 2896 * higher than the target (we need to ensure that there enough 2897 * BCLKs to clock out the samples). 2898 */ 2899 best = 0; 2900 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2901 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2902 if (cur_val < 0) /* BCLK table is sorted */ 2903 break; 2904 best = i; 2905 } 2906 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2907 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2908 bclk_divs[best], bclk_rate); 2909 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2910 2911 lrclk = bclk_rate / params_rate(params); 2912 if (!lrclk) { 2913 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 2914 bclk_rate); 2915 return -EINVAL; 2916 } 2917 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2918 lrclk, bclk_rate / lrclk); 2919 2920 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2921 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2); 2922 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2923 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2924 lrclk); 2925 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK | 2926 WM8994_AIF1CLK_RATE_MASK, rate_val); 2927 2928 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2929 switch (dai->id) { 2930 case 1: 2931 wm8994->dac_rates[0] = params_rate(params); 2932 wm8994_set_retune_mobile(component, 0); 2933 wm8994_set_retune_mobile(component, 1); 2934 break; 2935 case 2: 2936 wm8994->dac_rates[1] = params_rate(params); 2937 wm8994_set_retune_mobile(component, 2); 2938 break; 2939 } 2940 } 2941 2942 return 0; 2943 } 2944 2945 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2946 struct snd_pcm_hw_params *params, 2947 struct snd_soc_dai *dai) 2948 { 2949 struct snd_soc_component *component = dai->component; 2950 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2951 struct wm8994 *control = wm8994->wm8994; 2952 int aif1_reg; 2953 int aif1 = 0; 2954 2955 switch (dai->id) { 2956 case 3: 2957 switch (control->type) { 2958 case WM1811: 2959 case WM8958: 2960 aif1_reg = WM8958_AIF3_CONTROL_1; 2961 break; 2962 default: 2963 return 0; 2964 } 2965 break; 2966 default: 2967 return 0; 2968 } 2969 2970 switch (params_width(params)) { 2971 case 16: 2972 break; 2973 case 20: 2974 aif1 |= 0x20; 2975 break; 2976 case 24: 2977 aif1 |= 0x40; 2978 break; 2979 case 32: 2980 aif1 |= 0x60; 2981 break; 2982 default: 2983 return -EINVAL; 2984 } 2985 2986 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2987 } 2988 2989 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2990 { 2991 struct snd_soc_component *component = codec_dai->component; 2992 int mute_reg; 2993 int reg; 2994 2995 switch (codec_dai->id) { 2996 case 1: 2997 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2998 break; 2999 case 2: 3000 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 3001 break; 3002 default: 3003 return -EINVAL; 3004 } 3005 3006 if (mute) 3007 reg = WM8994_AIF1DAC1_MUTE; 3008 else 3009 reg = 0; 3010 3011 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 3012 3013 return 0; 3014 } 3015 3016 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3017 { 3018 struct snd_soc_component *component = codec_dai->component; 3019 int reg, val, mask; 3020 3021 switch (codec_dai->id) { 3022 case 1: 3023 reg = WM8994_AIF1_MASTER_SLAVE; 3024 mask = WM8994_AIF1_TRI; 3025 break; 3026 case 2: 3027 reg = WM8994_AIF2_MASTER_SLAVE; 3028 mask = WM8994_AIF2_TRI; 3029 break; 3030 default: 3031 return -EINVAL; 3032 } 3033 3034 if (tristate) 3035 val = mask; 3036 else 3037 val = 0; 3038 3039 return snd_soc_component_update_bits(component, reg, mask, val); 3040 } 3041 3042 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 3043 { 3044 struct snd_soc_component *component = dai->component; 3045 3046 /* Disable the pulls on the AIF if we're using it to save power. */ 3047 snd_soc_component_update_bits(component, WM8994_GPIO_3, 3048 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3049 snd_soc_component_update_bits(component, WM8994_GPIO_4, 3050 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3051 snd_soc_component_update_bits(component, WM8994_GPIO_5, 3052 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3053 3054 return 0; 3055 } 3056 3057 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3058 3059 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3060 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3061 3062 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3063 .set_sysclk = wm8994_set_dai_sysclk, 3064 .set_fmt = wm8994_set_dai_fmt, 3065 .hw_params = wm8994_hw_params, 3066 .digital_mute = wm8994_aif_mute, 3067 .set_pll = wm8994_set_fll, 3068 .set_tristate = wm8994_set_tristate, 3069 }; 3070 3071 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3072 .set_sysclk = wm8994_set_dai_sysclk, 3073 .set_fmt = wm8994_set_dai_fmt, 3074 .hw_params = wm8994_hw_params, 3075 .digital_mute = wm8994_aif_mute, 3076 .set_pll = wm8994_set_fll, 3077 .set_tristate = wm8994_set_tristate, 3078 }; 3079 3080 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3081 .hw_params = wm8994_aif3_hw_params, 3082 }; 3083 3084 static struct snd_soc_dai_driver wm8994_dai[] = { 3085 { 3086 .name = "wm8994-aif1", 3087 .id = 1, 3088 .playback = { 3089 .stream_name = "AIF1 Playback", 3090 .channels_min = 1, 3091 .channels_max = 2, 3092 .rates = WM8994_RATES, 3093 .formats = WM8994_FORMATS, 3094 .sig_bits = 24, 3095 }, 3096 .capture = { 3097 .stream_name = "AIF1 Capture", 3098 .channels_min = 1, 3099 .channels_max = 2, 3100 .rates = WM8994_RATES, 3101 .formats = WM8994_FORMATS, 3102 .sig_bits = 24, 3103 }, 3104 .ops = &wm8994_aif1_dai_ops, 3105 }, 3106 { 3107 .name = "wm8994-aif2", 3108 .id = 2, 3109 .playback = { 3110 .stream_name = "AIF2 Playback", 3111 .channels_min = 1, 3112 .channels_max = 2, 3113 .rates = WM8994_RATES, 3114 .formats = WM8994_FORMATS, 3115 .sig_bits = 24, 3116 }, 3117 .capture = { 3118 .stream_name = "AIF2 Capture", 3119 .channels_min = 1, 3120 .channels_max = 2, 3121 .rates = WM8994_RATES, 3122 .formats = WM8994_FORMATS, 3123 .sig_bits = 24, 3124 }, 3125 .probe = wm8994_aif2_probe, 3126 .ops = &wm8994_aif2_dai_ops, 3127 }, 3128 { 3129 .name = "wm8994-aif3", 3130 .id = 3, 3131 .playback = { 3132 .stream_name = "AIF3 Playback", 3133 .channels_min = 1, 3134 .channels_max = 2, 3135 .rates = WM8994_RATES, 3136 .formats = WM8994_FORMATS, 3137 .sig_bits = 24, 3138 }, 3139 .capture = { 3140 .stream_name = "AIF3 Capture", 3141 .channels_min = 1, 3142 .channels_max = 2, 3143 .rates = WM8994_RATES, 3144 .formats = WM8994_FORMATS, 3145 .sig_bits = 24, 3146 }, 3147 .ops = &wm8994_aif3_dai_ops, 3148 } 3149 }; 3150 3151 #ifdef CONFIG_PM 3152 static int wm8994_component_suspend(struct snd_soc_component *component) 3153 { 3154 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3155 int i, ret; 3156 3157 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3158 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3159 sizeof(struct wm8994_fll_config)); 3160 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0); 3161 if (ret < 0) 3162 dev_warn(component->dev, "Failed to stop FLL%d: %d\n", 3163 i + 1, ret); 3164 } 3165 3166 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 3167 3168 return 0; 3169 } 3170 3171 static int wm8994_component_resume(struct snd_soc_component *component) 3172 { 3173 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3174 int i, ret; 3175 3176 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3177 if (!wm8994->fll_suspend[i].out) 3178 continue; 3179 3180 ret = _wm8994_set_fll(component, i + 1, 3181 wm8994->fll_suspend[i].src, 3182 wm8994->fll_suspend[i].in, 3183 wm8994->fll_suspend[i].out); 3184 if (ret < 0) 3185 dev_warn(component->dev, "Failed to restore FLL%d: %d\n", 3186 i + 1, ret); 3187 } 3188 3189 return 0; 3190 } 3191 #else 3192 #define wm8994_component_suspend NULL 3193 #define wm8994_component_resume NULL 3194 #endif 3195 3196 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3197 { 3198 struct snd_soc_component *component = wm8994->hubs.component; 3199 struct wm8994 *control = wm8994->wm8994; 3200 struct wm8994_pdata *pdata = &control->pdata; 3201 struct snd_kcontrol_new controls[] = { 3202 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3203 wm8994->retune_mobile_enum, 3204 wm8994_get_retune_mobile_enum, 3205 wm8994_put_retune_mobile_enum), 3206 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3207 wm8994->retune_mobile_enum, 3208 wm8994_get_retune_mobile_enum, 3209 wm8994_put_retune_mobile_enum), 3210 SOC_ENUM_EXT("AIF2 EQ Mode", 3211 wm8994->retune_mobile_enum, 3212 wm8994_get_retune_mobile_enum, 3213 wm8994_put_retune_mobile_enum), 3214 }; 3215 int ret, i, j; 3216 const char **t; 3217 3218 /* We need an array of texts for the enum API but the number 3219 * of texts is likely to be less than the number of 3220 * configurations due to the sample rate dependency of the 3221 * configurations. */ 3222 wm8994->num_retune_mobile_texts = 0; 3223 wm8994->retune_mobile_texts = NULL; 3224 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3225 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3226 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3227 wm8994->retune_mobile_texts[j]) == 0) 3228 break; 3229 } 3230 3231 if (j != wm8994->num_retune_mobile_texts) 3232 continue; 3233 3234 /* Expand the array... */ 3235 t = krealloc(wm8994->retune_mobile_texts, 3236 sizeof(char *) * 3237 (wm8994->num_retune_mobile_texts + 1), 3238 GFP_KERNEL); 3239 if (t == NULL) 3240 continue; 3241 3242 /* ...store the new entry... */ 3243 t[wm8994->num_retune_mobile_texts] = 3244 pdata->retune_mobile_cfgs[i].name; 3245 3246 /* ...and remember the new version. */ 3247 wm8994->num_retune_mobile_texts++; 3248 wm8994->retune_mobile_texts = t; 3249 } 3250 3251 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 3252 wm8994->num_retune_mobile_texts); 3253 3254 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts; 3255 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3256 3257 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3258 ARRAY_SIZE(controls)); 3259 if (ret != 0) 3260 dev_err(wm8994->hubs.component->dev, 3261 "Failed to add ReTune Mobile controls: %d\n", ret); 3262 } 3263 3264 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3265 { 3266 struct snd_soc_component *component = wm8994->hubs.component; 3267 struct wm8994 *control = wm8994->wm8994; 3268 struct wm8994_pdata *pdata = &control->pdata; 3269 int ret, i; 3270 3271 if (!pdata) 3272 return; 3273 3274 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff, 3275 pdata->lineout2_diff, 3276 pdata->lineout1fb, 3277 pdata->lineout2fb, 3278 pdata->jd_scthr, 3279 pdata->jd_thr, 3280 pdata->micb1_delay, 3281 pdata->micb2_delay, 3282 pdata->micbias1_lvl, 3283 pdata->micbias2_lvl); 3284 3285 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3286 3287 if (pdata->num_drc_cfgs) { 3288 struct snd_kcontrol_new controls[] = { 3289 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3290 wm8994_get_drc_enum, wm8994_put_drc_enum), 3291 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3292 wm8994_get_drc_enum, wm8994_put_drc_enum), 3293 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3294 wm8994_get_drc_enum, wm8994_put_drc_enum), 3295 }; 3296 3297 /* We need an array of texts for the enum API */ 3298 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev, 3299 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL); 3300 if (!wm8994->drc_texts) 3301 return; 3302 3303 for (i = 0; i < pdata->num_drc_cfgs; i++) 3304 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3305 3306 wm8994->drc_enum.items = pdata->num_drc_cfgs; 3307 wm8994->drc_enum.texts = wm8994->drc_texts; 3308 3309 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3310 ARRAY_SIZE(controls)); 3311 for (i = 0; i < WM8994_NUM_DRC; i++) 3312 wm8994_set_drc(component, i); 3313 } else { 3314 ret = snd_soc_add_component_controls(wm8994->hubs.component, 3315 wm8994_drc_controls, 3316 ARRAY_SIZE(wm8994_drc_controls)); 3317 } 3318 3319 if (ret != 0) 3320 dev_err(wm8994->hubs.component->dev, 3321 "Failed to add DRC mode controls: %d\n", ret); 3322 3323 3324 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 3325 pdata->num_retune_mobile_cfgs); 3326 3327 if (pdata->num_retune_mobile_cfgs) 3328 wm8994_handle_retune_mobile_pdata(wm8994); 3329 else 3330 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls, 3331 ARRAY_SIZE(wm8994_eq_controls)); 3332 3333 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3334 if (pdata->micbias[i]) { 3335 snd_soc_component_write(component, WM8958_MICBIAS1 + i, 3336 pdata->micbias[i] & 0xffff); 3337 } 3338 } 3339 } 3340 3341 /** 3342 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3343 * 3344 * @component: WM8994 component 3345 * @jack: jack to report detection events on 3346 * @micbias: microphone bias to detect on 3347 * 3348 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3349 * being used to bring out signals to the processor then only platform 3350 * data configuration is needed for WM8994 and processor GPIOs should 3351 * be configured using snd_soc_jack_add_gpios() instead. 3352 * 3353 * Configuration of detection levels is available via the micbias1_lvl 3354 * and micbias2_lvl platform data members. 3355 */ 3356 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3357 int micbias) 3358 { 3359 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3360 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3361 struct wm8994_micdet *micdet; 3362 struct wm8994 *control = wm8994->wm8994; 3363 int reg, ret; 3364 3365 if (control->type != WM8994) { 3366 dev_warn(component->dev, "Not a WM8994\n"); 3367 return -EINVAL; 3368 } 3369 3370 switch (micbias) { 3371 case 1: 3372 micdet = &wm8994->micdet[0]; 3373 if (jack) 3374 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3375 else 3376 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3377 break; 3378 case 2: 3379 micdet = &wm8994->micdet[1]; 3380 if (jack) 3381 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3382 else 3383 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3384 break; 3385 default: 3386 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias); 3387 return -EINVAL; 3388 } 3389 3390 if (ret != 0) 3391 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n", 3392 micbias, ret); 3393 3394 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n", 3395 micbias, jack); 3396 3397 /* Store the configuration */ 3398 micdet->jack = jack; 3399 micdet->detecting = true; 3400 3401 /* If either of the jacks is set up then enable detection */ 3402 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3403 reg = WM8994_MICD_ENA; 3404 else 3405 reg = 0; 3406 3407 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3408 3409 /* enable MICDET and MICSHRT deboune */ 3410 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE, 3411 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3412 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3413 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3414 3415 snd_soc_dapm_sync(dapm); 3416 3417 return 0; 3418 } 3419 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3420 3421 static void wm8994_mic_work(struct work_struct *work) 3422 { 3423 struct wm8994_priv *priv = container_of(work, 3424 struct wm8994_priv, 3425 mic_work.work); 3426 struct regmap *regmap = priv->wm8994->regmap; 3427 struct device *dev = priv->wm8994->dev; 3428 unsigned int reg; 3429 int ret; 3430 int report; 3431 3432 pm_runtime_get_sync(dev); 3433 3434 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3435 if (ret < 0) { 3436 dev_err(dev, "Failed to read microphone status: %d\n", 3437 ret); 3438 pm_runtime_put(dev); 3439 return; 3440 } 3441 3442 dev_dbg(dev, "Microphone status: %x\n", reg); 3443 3444 report = 0; 3445 if (reg & WM8994_MIC1_DET_STS) { 3446 if (priv->micdet[0].detecting) 3447 report = SND_JACK_HEADSET; 3448 } 3449 if (reg & WM8994_MIC1_SHRT_STS) { 3450 if (priv->micdet[0].detecting) 3451 report = SND_JACK_HEADPHONE; 3452 else 3453 report |= SND_JACK_BTN_0; 3454 } 3455 if (report) 3456 priv->micdet[0].detecting = false; 3457 else 3458 priv->micdet[0].detecting = true; 3459 3460 snd_soc_jack_report(priv->micdet[0].jack, report, 3461 SND_JACK_HEADSET | SND_JACK_BTN_0); 3462 3463 report = 0; 3464 if (reg & WM8994_MIC2_DET_STS) { 3465 if (priv->micdet[1].detecting) 3466 report = SND_JACK_HEADSET; 3467 } 3468 if (reg & WM8994_MIC2_SHRT_STS) { 3469 if (priv->micdet[1].detecting) 3470 report = SND_JACK_HEADPHONE; 3471 else 3472 report |= SND_JACK_BTN_0; 3473 } 3474 if (report) 3475 priv->micdet[1].detecting = false; 3476 else 3477 priv->micdet[1].detecting = true; 3478 3479 snd_soc_jack_report(priv->micdet[1].jack, report, 3480 SND_JACK_HEADSET | SND_JACK_BTN_0); 3481 3482 pm_runtime_put(dev); 3483 } 3484 3485 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3486 { 3487 struct wm8994_priv *priv = data; 3488 struct snd_soc_component *component = priv->hubs.component; 3489 3490 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3491 trace_snd_soc_jack_irq(dev_name(component->dev)); 3492 #endif 3493 3494 pm_wakeup_event(component->dev, 300); 3495 3496 queue_delayed_work(system_power_efficient_wq, 3497 &priv->mic_work, msecs_to_jiffies(250)); 3498 3499 return IRQ_HANDLED; 3500 } 3501 3502 /* Should be called with accdet_lock held */ 3503 static void wm1811_micd_stop(struct snd_soc_component *component) 3504 { 3505 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3506 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3507 3508 if (!wm8994->jackdet) 3509 return; 3510 3511 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3512 3513 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3514 3515 if (wm8994->wm8994->pdata.jd_ext_cap) 3516 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3517 } 3518 3519 static void wm8958_button_det(struct snd_soc_component *component, u16 status) 3520 { 3521 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3522 int report; 3523 3524 report = 0; 3525 if (status & 0x4) 3526 report |= SND_JACK_BTN_0; 3527 3528 if (status & 0x8) 3529 report |= SND_JACK_BTN_1; 3530 3531 if (status & 0x10) 3532 report |= SND_JACK_BTN_2; 3533 3534 if (status & 0x20) 3535 report |= SND_JACK_BTN_3; 3536 3537 if (status & 0x40) 3538 report |= SND_JACK_BTN_4; 3539 3540 if (status & 0x80) 3541 report |= SND_JACK_BTN_5; 3542 3543 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3544 wm8994->btn_mask); 3545 } 3546 3547 static void wm8958_open_circuit_work(struct work_struct *work) 3548 { 3549 struct wm8994_priv *wm8994 = container_of(work, 3550 struct wm8994_priv, 3551 open_circuit_work.work); 3552 struct device *dev = wm8994->wm8994->dev; 3553 3554 mutex_lock(&wm8994->accdet_lock); 3555 3556 wm1811_micd_stop(wm8994->hubs.component); 3557 3558 dev_dbg(dev, "Reporting open circuit\n"); 3559 3560 wm8994->jack_mic = false; 3561 wm8994->mic_detecting = true; 3562 3563 wm8958_micd_set_rate(wm8994->hubs.component); 3564 3565 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3566 wm8994->btn_mask | 3567 SND_JACK_HEADSET); 3568 3569 mutex_unlock(&wm8994->accdet_lock); 3570 } 3571 3572 static void wm8958_mic_id(void *data, u16 status) 3573 { 3574 struct snd_soc_component *component = data; 3575 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3576 3577 /* Either nothing present or just starting detection */ 3578 if (!(status & WM8958_MICD_STS)) { 3579 /* If nothing present then clear our statuses */ 3580 dev_dbg(component->dev, "Detected open circuit\n"); 3581 3582 queue_delayed_work(system_power_efficient_wq, 3583 &wm8994->open_circuit_work, 3584 msecs_to_jiffies(2500)); 3585 return; 3586 } 3587 3588 /* If the measurement is showing a high impedence we've got a 3589 * microphone. 3590 */ 3591 if (status & 0x600) { 3592 dev_dbg(component->dev, "Detected microphone\n"); 3593 3594 wm8994->mic_detecting = false; 3595 wm8994->jack_mic = true; 3596 3597 wm8958_micd_set_rate(component); 3598 3599 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3600 SND_JACK_HEADSET); 3601 } 3602 3603 3604 if (status & 0xfc) { 3605 dev_dbg(component->dev, "Detected headphone\n"); 3606 wm8994->mic_detecting = false; 3607 3608 wm8958_micd_set_rate(component); 3609 3610 /* If we have jackdet that will detect removal */ 3611 wm1811_micd_stop(component); 3612 3613 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3614 SND_JACK_HEADSET); 3615 } 3616 } 3617 3618 /* Deferred mic detection to allow for extra settling time */ 3619 static void wm1811_mic_work(struct work_struct *work) 3620 { 3621 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3622 mic_work.work); 3623 struct wm8994 *control = wm8994->wm8994; 3624 struct snd_soc_component *component = wm8994->hubs.component; 3625 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3626 3627 pm_runtime_get_sync(component->dev); 3628 3629 /* If required for an external cap force MICBIAS on */ 3630 if (control->pdata.jd_ext_cap) { 3631 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 3632 snd_soc_dapm_sync(dapm); 3633 } 3634 3635 mutex_lock(&wm8994->accdet_lock); 3636 3637 dev_dbg(component->dev, "Starting mic detection\n"); 3638 3639 /* Use a user-supplied callback if we have one */ 3640 if (wm8994->micd_cb) { 3641 wm8994->micd_cb(wm8994->micd_cb_data); 3642 } else { 3643 /* 3644 * Start off measument of microphone impedence to find out 3645 * what's actually there. 3646 */ 3647 wm8994->mic_detecting = true; 3648 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC); 3649 3650 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3651 WM8958_MICD_ENA, WM8958_MICD_ENA); 3652 } 3653 3654 mutex_unlock(&wm8994->accdet_lock); 3655 3656 pm_runtime_put(component->dev); 3657 } 3658 3659 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3660 { 3661 struct wm8994_priv *wm8994 = data; 3662 struct wm8994 *control = wm8994->wm8994; 3663 struct snd_soc_component *component = wm8994->hubs.component; 3664 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3665 int reg, delay; 3666 bool present; 3667 3668 pm_runtime_get_sync(component->dev); 3669 3670 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3671 3672 mutex_lock(&wm8994->accdet_lock); 3673 3674 reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL); 3675 if (reg < 0) { 3676 dev_err(component->dev, "Failed to read jack status: %d\n", reg); 3677 mutex_unlock(&wm8994->accdet_lock); 3678 pm_runtime_put(component->dev); 3679 return IRQ_NONE; 3680 } 3681 3682 dev_dbg(component->dev, "JACKDET %x\n", reg); 3683 3684 present = reg & WM1811_JACKDET_LVL; 3685 3686 if (present) { 3687 dev_dbg(component->dev, "Jack detected\n"); 3688 3689 wm8958_micd_set_rate(component); 3690 3691 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3692 WM8958_MICB2_DISCH, 0); 3693 3694 /* Disable debounce while inserted */ 3695 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3696 WM1811_JACKDET_DB, 0); 3697 3698 delay = control->pdata.micdet_delay; 3699 queue_delayed_work(system_power_efficient_wq, 3700 &wm8994->mic_work, 3701 msecs_to_jiffies(delay)); 3702 } else { 3703 dev_dbg(component->dev, "Jack not detected\n"); 3704 3705 cancel_delayed_work_sync(&wm8994->mic_work); 3706 3707 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3708 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3709 3710 /* Enable debounce while removed */ 3711 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3712 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3713 3714 wm8994->mic_detecting = false; 3715 wm8994->jack_mic = false; 3716 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3717 WM8958_MICD_ENA, 0); 3718 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3719 } 3720 3721 mutex_unlock(&wm8994->accdet_lock); 3722 3723 /* Turn off MICBIAS if it was on for an external cap */ 3724 if (control->pdata.jd_ext_cap && !present) 3725 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3726 3727 if (present) 3728 snd_soc_jack_report(wm8994->micdet[0].jack, 3729 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3730 else 3731 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3732 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3733 wm8994->btn_mask); 3734 3735 /* Since we only report deltas force an update, ensures we 3736 * avoid bootstrapping issues with the core. */ 3737 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3738 3739 pm_runtime_put(component->dev); 3740 return IRQ_HANDLED; 3741 } 3742 3743 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3744 { 3745 struct wm8994_priv *wm8994 = container_of(work, 3746 struct wm8994_priv, 3747 jackdet_bootstrap.work); 3748 wm1811_jackdet_irq(0, wm8994); 3749 } 3750 3751 /** 3752 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3753 * 3754 * @component: WM8958 component 3755 * @jack: jack to report detection events on 3756 * 3757 * Enable microphone detection functionality for the WM8958. By 3758 * default simple detection which supports the detection of up to 6 3759 * buttons plus video and microphone functionality is supported. 3760 * 3761 * The WM8958 has an advanced jack detection facility which is able to 3762 * support complex accessory detection, especially when used in 3763 * conjunction with external circuitry. In order to provide maximum 3764 * flexiblity a callback is provided which allows a completely custom 3765 * detection algorithm. 3766 */ 3767 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3768 wm1811_micdet_cb det_cb, void *det_cb_data, 3769 wm1811_mic_id_cb id_cb, void *id_cb_data) 3770 { 3771 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3772 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3773 struct wm8994 *control = wm8994->wm8994; 3774 u16 micd_lvl_sel; 3775 3776 switch (control->type) { 3777 case WM1811: 3778 case WM8958: 3779 break; 3780 default: 3781 return -EINVAL; 3782 } 3783 3784 if (jack) { 3785 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS"); 3786 snd_soc_dapm_sync(dapm); 3787 3788 wm8994->micdet[0].jack = jack; 3789 3790 if (det_cb) { 3791 wm8994->micd_cb = det_cb; 3792 wm8994->micd_cb_data = det_cb_data; 3793 } else { 3794 wm8994->mic_detecting = true; 3795 wm8994->jack_mic = false; 3796 } 3797 3798 if (id_cb) { 3799 wm8994->mic_id_cb = id_cb; 3800 wm8994->mic_id_cb_data = id_cb_data; 3801 } else { 3802 wm8994->mic_id_cb = wm8958_mic_id; 3803 wm8994->mic_id_cb_data = component; 3804 } 3805 3806 wm8958_micd_set_rate(component); 3807 3808 /* Detect microphones and short circuits by default */ 3809 if (control->pdata.micd_lvl_sel) 3810 micd_lvl_sel = control->pdata.micd_lvl_sel; 3811 else 3812 micd_lvl_sel = 0x41; 3813 3814 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3815 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3816 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3817 3818 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2, 3819 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3820 3821 WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY); 3822 3823 /* 3824 * If we can use jack detection start off with that, 3825 * otherwise jump straight to microphone detection. 3826 */ 3827 if (wm8994->jackdet) { 3828 /* Disable debounce for the initial detect */ 3829 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3830 WM1811_JACKDET_DB, 0); 3831 3832 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3833 WM8958_MICB2_DISCH, 3834 WM8958_MICB2_DISCH); 3835 snd_soc_component_update_bits(component, WM8994_LDO_1, 3836 WM8994_LDO1_DISCH, 0); 3837 wm1811_jackdet_set_mode(component, 3838 WM1811_JACKDET_MODE_JACK); 3839 } else { 3840 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3841 WM8958_MICD_ENA, WM8958_MICD_ENA); 3842 } 3843 3844 } else { 3845 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3846 WM8958_MICD_ENA, 0); 3847 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE); 3848 snd_soc_dapm_disable_pin(dapm, "CLK_SYS"); 3849 snd_soc_dapm_sync(dapm); 3850 } 3851 3852 return 0; 3853 } 3854 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3855 3856 static void wm8958_mic_work(struct work_struct *work) 3857 { 3858 struct wm8994_priv *wm8994 = container_of(work, 3859 struct wm8994_priv, 3860 mic_complete_work.work); 3861 struct snd_soc_component *component = wm8994->hubs.component; 3862 3863 pm_runtime_get_sync(component->dev); 3864 3865 mutex_lock(&wm8994->accdet_lock); 3866 3867 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status); 3868 3869 mutex_unlock(&wm8994->accdet_lock); 3870 3871 pm_runtime_put(component->dev); 3872 } 3873 3874 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3875 { 3876 struct wm8994_priv *wm8994 = data; 3877 struct snd_soc_component *component = wm8994->hubs.component; 3878 int reg, count, ret, id_delay; 3879 3880 /* 3881 * Jack detection may have detected a removal simulataneously 3882 * with an update of the MICDET status; if so it will have 3883 * stopped detection and we can ignore this interrupt. 3884 */ 3885 if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 3886 return IRQ_HANDLED; 3887 3888 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3889 cancel_delayed_work_sync(&wm8994->open_circuit_work); 3890 3891 pm_runtime_get_sync(component->dev); 3892 3893 /* We may occasionally read a detection without an impedence 3894 * range being provided - if that happens loop again. 3895 */ 3896 count = 10; 3897 do { 3898 reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3); 3899 if (reg < 0) { 3900 dev_err(component->dev, 3901 "Failed to read mic detect status: %d\n", 3902 reg); 3903 pm_runtime_put(component->dev); 3904 return IRQ_NONE; 3905 } 3906 3907 if (!(reg & WM8958_MICD_VALID)) { 3908 dev_dbg(component->dev, "Mic detect data not valid\n"); 3909 goto out; 3910 } 3911 3912 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 3913 break; 3914 3915 msleep(1); 3916 } while (count--); 3917 3918 if (count == 0) 3919 dev_warn(component->dev, "No impedance range reported for jack\n"); 3920 3921 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3922 trace_snd_soc_jack_irq(dev_name(component->dev)); 3923 #endif 3924 3925 /* Avoid a transient report when the accessory is being removed */ 3926 if (wm8994->jackdet) { 3927 ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL); 3928 if (ret < 0) { 3929 dev_err(component->dev, "Failed to read jack status: %d\n", 3930 ret); 3931 } else if (!(ret & WM1811_JACKDET_LVL)) { 3932 dev_dbg(component->dev, "Ignoring removed jack\n"); 3933 goto out; 3934 } 3935 } else if (!(reg & WM8958_MICD_STS)) { 3936 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3937 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3938 wm8994->btn_mask); 3939 wm8994->mic_detecting = true; 3940 goto out; 3941 } 3942 3943 wm8994->mic_status = reg; 3944 id_delay = wm8994->wm8994->pdata.mic_id_delay; 3945 3946 if (wm8994->mic_detecting) 3947 queue_delayed_work(system_power_efficient_wq, 3948 &wm8994->mic_complete_work, 3949 msecs_to_jiffies(id_delay)); 3950 else 3951 wm8958_button_det(component, reg); 3952 3953 out: 3954 pm_runtime_put(component->dev); 3955 return IRQ_HANDLED; 3956 } 3957 3958 static irqreturn_t wm8994_fifo_error(int irq, void *data) 3959 { 3960 struct snd_soc_component *component = data; 3961 3962 dev_err(component->dev, "FIFO error\n"); 3963 3964 return IRQ_HANDLED; 3965 } 3966 3967 static irqreturn_t wm8994_temp_warn(int irq, void *data) 3968 { 3969 struct snd_soc_component *component = data; 3970 3971 dev_err(component->dev, "Thermal warning\n"); 3972 3973 return IRQ_HANDLED; 3974 } 3975 3976 static irqreturn_t wm8994_temp_shut(int irq, void *data) 3977 { 3978 struct snd_soc_component *component = data; 3979 3980 dev_crit(component->dev, "Thermal shutdown\n"); 3981 3982 return IRQ_HANDLED; 3983 } 3984 3985 static int wm8994_component_probe(struct snd_soc_component *component) 3986 { 3987 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3988 struct wm8994 *control = dev_get_drvdata(component->dev->parent); 3989 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3990 unsigned int reg; 3991 int ret, i; 3992 3993 snd_soc_component_init_regmap(component, control->regmap); 3994 3995 wm8994->hubs.component = component; 3996 3997 mutex_init(&wm8994->accdet_lock); 3998 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 3999 wm1811_jackdet_bootstrap); 4000 INIT_DELAYED_WORK(&wm8994->open_circuit_work, 4001 wm8958_open_circuit_work); 4002 4003 switch (control->type) { 4004 case WM8994: 4005 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 4006 break; 4007 case WM1811: 4008 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 4009 break; 4010 default: 4011 break; 4012 } 4013 4014 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work); 4015 4016 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4017 init_completion(&wm8994->fll_locked[i]); 4018 4019 wm8994->micdet_irq = control->pdata.micdet_irq; 4020 4021 /* By default use idle_bias_off, will override for WM8994 */ 4022 dapm->idle_bias_off = 1; 4023 4024 /* Set revision-specific configuration */ 4025 switch (control->type) { 4026 case WM8994: 4027 /* Single ended line outputs should have VMID on. */ 4028 if (!control->pdata.lineout1_diff || 4029 !control->pdata.lineout2_diff) 4030 dapm->idle_bias_off = 0; 4031 4032 switch (control->revision) { 4033 case 2: 4034 case 3: 4035 wm8994->hubs.dcs_codes_l = -5; 4036 wm8994->hubs.dcs_codes_r = -5; 4037 wm8994->hubs.hp_startup_mode = 1; 4038 wm8994->hubs.dcs_readback_mode = 1; 4039 wm8994->hubs.series_startup = 1; 4040 break; 4041 default: 4042 wm8994->hubs.dcs_readback_mode = 2; 4043 break; 4044 } 4045 break; 4046 4047 case WM8958: 4048 wm8994->hubs.dcs_readback_mode = 1; 4049 wm8994->hubs.hp_startup_mode = 1; 4050 4051 switch (control->revision) { 4052 case 0: 4053 break; 4054 default: 4055 wm8994->fll_byp = true; 4056 break; 4057 } 4058 break; 4059 4060 case WM1811: 4061 wm8994->hubs.dcs_readback_mode = 2; 4062 wm8994->hubs.no_series_update = 1; 4063 wm8994->hubs.hp_startup_mode = 1; 4064 wm8994->hubs.no_cache_dac_hp_direct = true; 4065 wm8994->fll_byp = true; 4066 4067 wm8994->hubs.dcs_codes_l = -9; 4068 wm8994->hubs.dcs_codes_r = -7; 4069 4070 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1, 4071 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 4072 break; 4073 4074 default: 4075 break; 4076 } 4077 4078 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 4079 wm8994_fifo_error, "FIFO error", component); 4080 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 4081 wm8994_temp_warn, "Thermal warning", component); 4082 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 4083 wm8994_temp_shut, "Thermal shutdown", component); 4084 4085 switch (control->type) { 4086 case WM8994: 4087 if (wm8994->micdet_irq) 4088 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4089 wm8994_mic_irq, 4090 IRQF_TRIGGER_RISING | 4091 IRQF_ONESHOT, 4092 "Mic1 detect", 4093 wm8994); 4094 else 4095 ret = wm8994_request_irq(wm8994->wm8994, 4096 WM8994_IRQ_MIC1_DET, 4097 wm8994_mic_irq, "Mic 1 detect", 4098 wm8994); 4099 4100 if (ret != 0) 4101 dev_warn(component->dev, 4102 "Failed to request Mic1 detect IRQ: %d\n", 4103 ret); 4104 4105 4106 ret = wm8994_request_irq(wm8994->wm8994, 4107 WM8994_IRQ_MIC1_SHRT, 4108 wm8994_mic_irq, "Mic 1 short", 4109 wm8994); 4110 if (ret != 0) 4111 dev_warn(component->dev, 4112 "Failed to request Mic1 short IRQ: %d\n", 4113 ret); 4114 4115 ret = wm8994_request_irq(wm8994->wm8994, 4116 WM8994_IRQ_MIC2_DET, 4117 wm8994_mic_irq, "Mic 2 detect", 4118 wm8994); 4119 if (ret != 0) 4120 dev_warn(component->dev, 4121 "Failed to request Mic2 detect IRQ: %d\n", 4122 ret); 4123 4124 ret = wm8994_request_irq(wm8994->wm8994, 4125 WM8994_IRQ_MIC2_SHRT, 4126 wm8994_mic_irq, "Mic 2 short", 4127 wm8994); 4128 if (ret != 0) 4129 dev_warn(component->dev, 4130 "Failed to request Mic2 short IRQ: %d\n", 4131 ret); 4132 break; 4133 4134 case WM8958: 4135 case WM1811: 4136 if (wm8994->micdet_irq) { 4137 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4138 wm8958_mic_irq, 4139 IRQF_TRIGGER_RISING | 4140 IRQF_ONESHOT, 4141 "Mic detect", 4142 wm8994); 4143 if (ret != 0) 4144 dev_warn(component->dev, 4145 "Failed to request Mic detect IRQ: %d\n", 4146 ret); 4147 } else { 4148 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4149 wm8958_mic_irq, "Mic detect", 4150 wm8994); 4151 } 4152 } 4153 4154 switch (control->type) { 4155 case WM1811: 4156 if (control->cust_id > 1 || control->revision > 1) { 4157 ret = wm8994_request_irq(wm8994->wm8994, 4158 WM8994_IRQ_GPIO(6), 4159 wm1811_jackdet_irq, "JACKDET", 4160 wm8994); 4161 if (ret == 0) 4162 wm8994->jackdet = true; 4163 } 4164 break; 4165 default: 4166 break; 4167 } 4168 4169 wm8994->fll_locked_irq = true; 4170 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4171 ret = wm8994_request_irq(wm8994->wm8994, 4172 WM8994_IRQ_FLL1_LOCK + i, 4173 wm8994_fll_locked_irq, "FLL lock", 4174 &wm8994->fll_locked[i]); 4175 if (ret != 0) 4176 wm8994->fll_locked_irq = false; 4177 } 4178 4179 /* Make sure we can read from the GPIOs if they're inputs */ 4180 pm_runtime_get_sync(component->dev); 4181 4182 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4183 * configured on init - if a system wants to do this dynamically 4184 * at runtime we can deal with that then. 4185 */ 4186 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4187 if (ret < 0) { 4188 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret); 4189 goto err_irq; 4190 } 4191 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4192 wm8994->lrclk_shared[0] = 1; 4193 wm8994_dai[0].symmetric_rates = 1; 4194 } else { 4195 wm8994->lrclk_shared[0] = 0; 4196 } 4197 4198 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4199 if (ret < 0) { 4200 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret); 4201 goto err_irq; 4202 } 4203 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4204 wm8994->lrclk_shared[1] = 1; 4205 wm8994_dai[1].symmetric_rates = 1; 4206 } else { 4207 wm8994->lrclk_shared[1] = 0; 4208 } 4209 4210 pm_runtime_put(component->dev); 4211 4212 /* Latch volume update bits */ 4213 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4214 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg, 4215 wm8994_vu_bits[i].mask, 4216 wm8994_vu_bits[i].mask); 4217 4218 /* Set the low bit of the 3D stereo depth so TLV matches */ 4219 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2, 4220 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4221 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4222 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2, 4223 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4224 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4225 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2, 4226 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4227 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4228 4229 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4230 * use this; it only affects behaviour on idle TDM clock 4231 * cycles. */ 4232 switch (control->type) { 4233 case WM8994: 4234 case WM8958: 4235 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1, 4236 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4237 break; 4238 default: 4239 break; 4240 } 4241 4242 /* Put MICBIAS into bypass mode by default on newer devices */ 4243 switch (control->type) { 4244 case WM8958: 4245 case WM1811: 4246 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 4247 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4248 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 4249 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4250 break; 4251 default: 4252 break; 4253 } 4254 4255 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4256 wm_hubs_update_class_w(component); 4257 4258 wm8994_handle_pdata(wm8994); 4259 4260 wm_hubs_add_analogue_controls(component); 4261 snd_soc_add_component_controls(component, wm8994_snd_controls, 4262 ARRAY_SIZE(wm8994_snd_controls)); 4263 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4264 ARRAY_SIZE(wm8994_dapm_widgets)); 4265 4266 switch (control->type) { 4267 case WM8994: 4268 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4269 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4270 if (control->revision < 4) { 4271 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4272 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4273 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4274 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4275 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4276 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4277 } else { 4278 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4279 ARRAY_SIZE(wm8994_lateclk_widgets)); 4280 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4281 ARRAY_SIZE(wm8994_adc_widgets)); 4282 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4283 ARRAY_SIZE(wm8994_dac_widgets)); 4284 } 4285 break; 4286 case WM8958: 4287 snd_soc_add_component_controls(component, wm8958_snd_controls, 4288 ARRAY_SIZE(wm8958_snd_controls)); 4289 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4290 ARRAY_SIZE(wm8958_dapm_widgets)); 4291 if (control->revision < 1) { 4292 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4293 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4294 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4295 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4296 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4297 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4298 } else { 4299 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4300 ARRAY_SIZE(wm8994_lateclk_widgets)); 4301 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4302 ARRAY_SIZE(wm8994_adc_widgets)); 4303 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4304 ARRAY_SIZE(wm8994_dac_widgets)); 4305 } 4306 break; 4307 4308 case WM1811: 4309 snd_soc_add_component_controls(component, wm8958_snd_controls, 4310 ARRAY_SIZE(wm8958_snd_controls)); 4311 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4312 ARRAY_SIZE(wm8958_dapm_widgets)); 4313 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4314 ARRAY_SIZE(wm8994_lateclk_widgets)); 4315 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4316 ARRAY_SIZE(wm8994_adc_widgets)); 4317 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4318 ARRAY_SIZE(wm8994_dac_widgets)); 4319 break; 4320 } 4321 4322 wm_hubs_add_analogue_routes(component, 0, 0); 4323 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4324 wm_hubs_dcs_done, "DC servo done", 4325 &wm8994->hubs); 4326 if (ret == 0) 4327 wm8994->hubs.dcs_done_irq = true; 4328 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4329 4330 switch (control->type) { 4331 case WM8994: 4332 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4333 ARRAY_SIZE(wm8994_intercon)); 4334 4335 if (control->revision < 4) { 4336 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4337 ARRAY_SIZE(wm8994_revd_intercon)); 4338 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4339 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4340 } else { 4341 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4342 ARRAY_SIZE(wm8994_lateclk_intercon)); 4343 } 4344 break; 4345 case WM8958: 4346 if (control->revision < 1) { 4347 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4348 ARRAY_SIZE(wm8994_intercon)); 4349 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4350 ARRAY_SIZE(wm8994_revd_intercon)); 4351 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4352 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4353 } else { 4354 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4355 ARRAY_SIZE(wm8994_lateclk_intercon)); 4356 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4357 ARRAY_SIZE(wm8958_intercon)); 4358 } 4359 4360 wm8958_dsp2_init(component); 4361 break; 4362 case WM1811: 4363 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4364 ARRAY_SIZE(wm8994_lateclk_intercon)); 4365 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4366 ARRAY_SIZE(wm8958_intercon)); 4367 break; 4368 } 4369 4370 return 0; 4371 4372 err_irq: 4373 if (wm8994->jackdet) 4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4376 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4377 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4378 if (wm8994->micdet_irq) 4379 free_irq(wm8994->micdet_irq, wm8994); 4380 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4381 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4382 &wm8994->fll_locked[i]); 4383 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4384 &wm8994->hubs); 4385 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4386 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4387 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4388 4389 return ret; 4390 } 4391 4392 static void wm8994_component_remove(struct snd_soc_component *component) 4393 { 4394 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 4395 struct wm8994 *control = wm8994->wm8994; 4396 int i; 4397 4398 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4400 &wm8994->fll_locked[i]); 4401 4402 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4403 &wm8994->hubs); 4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4407 4408 if (wm8994->jackdet) 4409 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4410 4411 switch (control->type) { 4412 case WM8994: 4413 if (wm8994->micdet_irq) 4414 free_irq(wm8994->micdet_irq, wm8994); 4415 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4416 wm8994); 4417 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4418 wm8994); 4419 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4420 wm8994); 4421 break; 4422 4423 case WM1811: 4424 case WM8958: 4425 if (wm8994->micdet_irq) 4426 free_irq(wm8994->micdet_irq, wm8994); 4427 break; 4428 } 4429 release_firmware(wm8994->mbc); 4430 release_firmware(wm8994->mbc_vss); 4431 release_firmware(wm8994->enh_eq); 4432 kfree(wm8994->retune_mobile_texts); 4433 } 4434 4435 static const struct snd_soc_component_driver soc_component_dev_wm8994 = { 4436 .probe = wm8994_component_probe, 4437 .remove = wm8994_component_remove, 4438 .suspend = wm8994_component_suspend, 4439 .resume = wm8994_component_resume, 4440 .set_bias_level = wm8994_set_bias_level, 4441 .idle_bias_on = 1, 4442 .use_pmdown_time = 1, 4443 .endianness = 1, 4444 .non_legacy_dai_naming = 1, 4445 }; 4446 4447 static int wm8994_probe(struct platform_device *pdev) 4448 { 4449 struct wm8994_priv *wm8994; 4450 4451 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4452 GFP_KERNEL); 4453 if (wm8994 == NULL) 4454 return -ENOMEM; 4455 platform_set_drvdata(pdev, wm8994); 4456 4457 mutex_init(&wm8994->fw_lock); 4458 4459 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4460 4461 pm_runtime_enable(&pdev->dev); 4462 pm_runtime_idle(&pdev->dev); 4463 4464 return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994, 4465 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4466 } 4467 4468 static int wm8994_remove(struct platform_device *pdev) 4469 { 4470 pm_runtime_disable(&pdev->dev); 4471 4472 return 0; 4473 } 4474 4475 #ifdef CONFIG_PM_SLEEP 4476 static int wm8994_suspend(struct device *dev) 4477 { 4478 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4479 4480 /* Drop down to power saving mode when system is suspended */ 4481 if (wm8994->jackdet && !wm8994->active_refcount) 4482 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4483 WM1811_JACKDET_MODE_MASK, 4484 wm8994->jackdet_mode); 4485 4486 return 0; 4487 } 4488 4489 static int wm8994_resume(struct device *dev) 4490 { 4491 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4492 4493 if (wm8994->jackdet && wm8994->jackdet_mode) 4494 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4495 WM1811_JACKDET_MODE_MASK, 4496 WM1811_JACKDET_MODE_AUDIO); 4497 4498 return 0; 4499 } 4500 #endif 4501 4502 static const struct dev_pm_ops wm8994_pm_ops = { 4503 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4504 }; 4505 4506 static struct platform_driver wm8994_codec_driver = { 4507 .driver = { 4508 .name = "wm8994-codec", 4509 .pm = &wm8994_pm_ops, 4510 }, 4511 .probe = wm8994_probe, 4512 .remove = wm8994_remove, 4513 }; 4514 4515 module_platform_driver(wm8994_codec_driver); 4516 4517 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4518 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4519 MODULE_LICENSE("GPL"); 4520 MODULE_ALIAS("platform:wm8994-codec"); 4521