1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <trace/events/asoc.h> 32 33 #include <linux/mfd/wm8994/core.h> 34 #include <linux/mfd/wm8994/registers.h> 35 #include <linux/mfd/wm8994/pdata.h> 36 #include <linux/mfd/wm8994/gpio.h> 37 38 #include "wm8994.h" 39 #include "wm_hubs.h" 40 41 #define WM8994_NUM_DRC 3 42 #define WM8994_NUM_EQ 3 43 44 static int wm8994_drc_base[] = { 45 WM8994_AIF1_DRC1_1, 46 WM8994_AIF1_DRC2_1, 47 WM8994_AIF2_DRC_1, 48 }; 49 50 static int wm8994_retune_mobile_base[] = { 51 WM8994_AIF1_DAC1_EQ_GAINS_1, 52 WM8994_AIF1_DAC2_EQ_GAINS_1, 53 WM8994_AIF2_EQ_GAINS_1, 54 }; 55 56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg) 57 { 58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 59 struct wm8994 *control = wm8994->control_data; 60 61 switch (reg) { 62 case WM8994_GPIO_1: 63 case WM8994_GPIO_2: 64 case WM8994_GPIO_3: 65 case WM8994_GPIO_4: 66 case WM8994_GPIO_5: 67 case WM8994_GPIO_6: 68 case WM8994_GPIO_7: 69 case WM8994_GPIO_8: 70 case WM8994_GPIO_9: 71 case WM8994_GPIO_10: 72 case WM8994_GPIO_11: 73 case WM8994_INTERRUPT_STATUS_1: 74 case WM8994_INTERRUPT_STATUS_2: 75 case WM8994_INTERRUPT_RAW_STATUS_2: 76 return 1; 77 78 case WM8958_DSP2_PROGRAM: 79 case WM8958_DSP2_CONFIG: 80 case WM8958_DSP2_EXECCONTROL: 81 if (control->type == WM8958) 82 return 1; 83 else 84 return 0; 85 86 default: 87 break; 88 } 89 90 if (reg >= WM8994_CACHE_SIZE) 91 return 0; 92 return wm8994_access_masks[reg].readable != 0; 93 } 94 95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg) 96 { 97 if (reg >= WM8994_CACHE_SIZE) 98 return 1; 99 100 switch (reg) { 101 case WM8994_SOFTWARE_RESET: 102 case WM8994_CHIP_REVISION: 103 case WM8994_DC_SERVO_1: 104 case WM8994_DC_SERVO_READBACK: 105 case WM8994_RATE_STATUS: 106 case WM8994_LDO_1: 107 case WM8994_LDO_2: 108 case WM8958_DSP2_EXECCONTROL: 109 case WM8958_MIC_DETECT_3: 110 return 1; 111 default: 112 return 0; 113 } 114 } 115 116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 117 unsigned int value) 118 { 119 int ret; 120 121 BUG_ON(reg > WM8994_MAX_REGISTER); 122 123 if (!wm8994_volatile(codec, reg)) { 124 ret = snd_soc_cache_write(codec, reg, value); 125 if (ret != 0) 126 dev_err(codec->dev, "Cache write to %x failed: %d\n", 127 reg, ret); 128 } 129 130 return wm8994_reg_write(codec->control_data, reg, value); 131 } 132 133 static unsigned int wm8994_read(struct snd_soc_codec *codec, 134 unsigned int reg) 135 { 136 unsigned int val; 137 int ret; 138 139 BUG_ON(reg > WM8994_MAX_REGISTER); 140 141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) && 142 reg < codec->driver->reg_cache_size) { 143 ret = snd_soc_cache_read(codec, reg, &val); 144 if (ret >= 0) 145 return val; 146 else 147 dev_err(codec->dev, "Cache read from %x failed: %d\n", 148 reg, ret); 149 } 150 151 return wm8994_reg_read(codec->control_data, reg); 152 } 153 154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 155 { 156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 157 int rate; 158 int reg1 = 0; 159 int offset; 160 161 if (aif) 162 offset = 4; 163 else 164 offset = 0; 165 166 switch (wm8994->sysclk[aif]) { 167 case WM8994_SYSCLK_MCLK1: 168 rate = wm8994->mclk[0]; 169 break; 170 171 case WM8994_SYSCLK_MCLK2: 172 reg1 |= 0x8; 173 rate = wm8994->mclk[1]; 174 break; 175 176 case WM8994_SYSCLK_FLL1: 177 reg1 |= 0x10; 178 rate = wm8994->fll[0].out; 179 break; 180 181 case WM8994_SYSCLK_FLL2: 182 reg1 |= 0x18; 183 rate = wm8994->fll[1].out; 184 break; 185 186 default: 187 return -EINVAL; 188 } 189 190 if (rate >= 13500000) { 191 rate /= 2; 192 reg1 |= WM8994_AIF1CLK_DIV; 193 194 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 195 aif + 1, rate); 196 } 197 198 wm8994->aifclk[aif] = rate; 199 200 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 201 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 202 reg1); 203 204 return 0; 205 } 206 207 static int configure_clock(struct snd_soc_codec *codec) 208 { 209 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 210 int old, new; 211 212 /* Bring up the AIF clocks first */ 213 configure_aif_clock(codec, 0); 214 configure_aif_clock(codec, 1); 215 216 /* Then switch CLK_SYS over to the higher of them; a change 217 * can only happen as a result of a clocking change which can 218 * only be made outside of DAPM so we can safely redo the 219 * clocking. 220 */ 221 222 /* If they're equal it doesn't matter which is used */ 223 if (wm8994->aifclk[0] == wm8994->aifclk[1]) 224 return 0; 225 226 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 227 new = WM8994_SYSCLK_SRC; 228 else 229 new = 0; 230 231 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; 232 233 /* If there's no change then we're done. */ 234 if (old == new) 235 return 0; 236 237 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 238 239 snd_soc_dapm_sync(&codec->dapm); 240 241 return 0; 242 } 243 244 static int check_clk_sys(struct snd_soc_dapm_widget *source, 245 struct snd_soc_dapm_widget *sink) 246 { 247 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 248 const char *clk; 249 250 /* Check what we're currently using for CLK_SYS */ 251 if (reg & WM8994_SYSCLK_SRC) 252 clk = "AIF2CLK"; 253 else 254 clk = "AIF1CLK"; 255 256 return strcmp(source->name, clk) == 0; 257 } 258 259 static const char *sidetone_hpf_text[] = { 260 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 261 }; 262 263 static const struct soc_enum sidetone_hpf = 264 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 265 266 static const char *adc_hpf_text[] = { 267 "HiFi", "Voice 1", "Voice 2", "Voice 3" 268 }; 269 270 static const struct soc_enum aif1adc1_hpf = 271 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 272 273 static const struct soc_enum aif1adc2_hpf = 274 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 275 276 static const struct soc_enum aif2adc_hpf = 277 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 278 279 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 280 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 281 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 282 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 283 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 284 285 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 286 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 287 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 288 .put = wm8994_put_drc_sw, \ 289 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 290 291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 292 struct snd_ctl_elem_value *ucontrol) 293 { 294 struct soc_mixer_control *mc = 295 (struct soc_mixer_control *)kcontrol->private_value; 296 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 297 int mask, ret; 298 299 /* Can't enable both ADC and DAC paths simultaneously */ 300 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 301 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 302 WM8994_AIF1ADC1R_DRC_ENA_MASK; 303 else 304 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 305 306 ret = snd_soc_read(codec, mc->reg); 307 if (ret < 0) 308 return ret; 309 if (ret & mask) 310 return -EINVAL; 311 312 return snd_soc_put_volsw(kcontrol, ucontrol); 313 } 314 315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 316 { 317 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 318 struct wm8994_pdata *pdata = wm8994->pdata; 319 int base = wm8994_drc_base[drc]; 320 int cfg = wm8994->drc_cfg[drc]; 321 int save, i; 322 323 /* Save any enables; the configuration should clear them. */ 324 save = snd_soc_read(codec, base); 325 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 326 WM8994_AIF1ADC1R_DRC_ENA; 327 328 for (i = 0; i < WM8994_DRC_REGS; i++) 329 snd_soc_update_bits(codec, base + i, 0xffff, 330 pdata->drc_cfgs[cfg].regs[i]); 331 332 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 333 WM8994_AIF1ADC1L_DRC_ENA | 334 WM8994_AIF1ADC1R_DRC_ENA, save); 335 } 336 337 /* Icky as hell but saves code duplication */ 338 static int wm8994_get_drc(const char *name) 339 { 340 if (strcmp(name, "AIF1DRC1 Mode") == 0) 341 return 0; 342 if (strcmp(name, "AIF1DRC2 Mode") == 0) 343 return 1; 344 if (strcmp(name, "AIF2DRC Mode") == 0) 345 return 2; 346 return -EINVAL; 347 } 348 349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 350 struct snd_ctl_elem_value *ucontrol) 351 { 352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 354 struct wm8994_pdata *pdata = wm8994->pdata; 355 int drc = wm8994_get_drc(kcontrol->id.name); 356 int value = ucontrol->value.integer.value[0]; 357 358 if (drc < 0) 359 return drc; 360 361 if (value >= pdata->num_drc_cfgs) 362 return -EINVAL; 363 364 wm8994->drc_cfg[drc] = value; 365 366 wm8994_set_drc(codec, drc); 367 368 return 0; 369 } 370 371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 372 struct snd_ctl_elem_value *ucontrol) 373 { 374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 375 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 376 int drc = wm8994_get_drc(kcontrol->id.name); 377 378 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 379 380 return 0; 381 } 382 383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 384 { 385 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 386 struct wm8994_pdata *pdata = wm8994->pdata; 387 int base = wm8994_retune_mobile_base[block]; 388 int iface, best, best_val, save, i, cfg; 389 390 if (!pdata || !wm8994->num_retune_mobile_texts) 391 return; 392 393 switch (block) { 394 case 0: 395 case 1: 396 iface = 0; 397 break; 398 case 2: 399 iface = 1; 400 break; 401 default: 402 return; 403 } 404 405 /* Find the version of the currently selected configuration 406 * with the nearest sample rate. */ 407 cfg = wm8994->retune_mobile_cfg[block]; 408 best = 0; 409 best_val = INT_MAX; 410 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 411 if (strcmp(pdata->retune_mobile_cfgs[i].name, 412 wm8994->retune_mobile_texts[cfg]) == 0 && 413 abs(pdata->retune_mobile_cfgs[i].rate 414 - wm8994->dac_rates[iface]) < best_val) { 415 best = i; 416 best_val = abs(pdata->retune_mobile_cfgs[i].rate 417 - wm8994->dac_rates[iface]); 418 } 419 } 420 421 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 422 block, 423 pdata->retune_mobile_cfgs[best].name, 424 pdata->retune_mobile_cfgs[best].rate, 425 wm8994->dac_rates[iface]); 426 427 /* The EQ will be disabled while reconfiguring it, remember the 428 * current configuration. 429 */ 430 save = snd_soc_read(codec, base); 431 save &= WM8994_AIF1DAC1_EQ_ENA; 432 433 for (i = 0; i < WM8994_EQ_REGS; i++) 434 snd_soc_update_bits(codec, base + i, 0xffff, 435 pdata->retune_mobile_cfgs[best].regs[i]); 436 437 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 438 } 439 440 /* Icky as hell but saves code duplication */ 441 static int wm8994_get_retune_mobile_block(const char *name) 442 { 443 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 444 return 0; 445 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 446 return 1; 447 if (strcmp(name, "AIF2 EQ Mode") == 0) 448 return 2; 449 return -EINVAL; 450 } 451 452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 453 struct snd_ctl_elem_value *ucontrol) 454 { 455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 456 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 457 struct wm8994_pdata *pdata = wm8994->pdata; 458 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 459 int value = ucontrol->value.integer.value[0]; 460 461 if (block < 0) 462 return block; 463 464 if (value >= pdata->num_retune_mobile_cfgs) 465 return -EINVAL; 466 467 wm8994->retune_mobile_cfg[block] = value; 468 469 wm8994_set_retune_mobile(codec, block); 470 471 return 0; 472 } 473 474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 475 struct snd_ctl_elem_value *ucontrol) 476 { 477 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 478 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 479 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 480 481 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 482 483 return 0; 484 } 485 486 static const char *aif_chan_src_text[] = { 487 "Left", "Right" 488 }; 489 490 static const struct soc_enum aif1adcl_src = 491 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 492 493 static const struct soc_enum aif1adcr_src = 494 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 495 496 static const struct soc_enum aif2adcl_src = 497 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 498 499 static const struct soc_enum aif2adcr_src = 500 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 501 502 static const struct soc_enum aif1dacl_src = 503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 504 505 static const struct soc_enum aif1dacr_src = 506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 507 508 static const struct soc_enum aif2dacl_src = 509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 510 511 static const struct soc_enum aif2dacr_src = 512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 513 514 static const char *osr_text[] = { 515 "Low Power", "High Performance", 516 }; 517 518 static const struct soc_enum dac_osr = 519 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 520 521 static const struct soc_enum adc_osr = 522 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 523 524 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 526 WM8994_AIF1_ADC1_RIGHT_VOLUME, 527 1, 119, 0, digital_tlv), 528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 529 WM8994_AIF1_ADC2_RIGHT_VOLUME, 530 1, 119, 0, digital_tlv), 531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 532 WM8994_AIF2_ADC_RIGHT_VOLUME, 533 1, 119, 0, digital_tlv), 534 535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 539 540 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 541 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 542 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 543 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 544 545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 546 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 548 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 550 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 551 552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 554 555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 558 559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 562 563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 566 567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 570 571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 572 5, 12, 0, st_tlv), 573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 574 0, 12, 0, st_tlv), 575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 576 5, 12, 0, st_tlv), 577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 578 0, 12, 0, st_tlv), 579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 581 582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 584 585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 587 588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 590 591 SOC_ENUM("ADC OSR", adc_osr), 592 SOC_ENUM("DAC OSR", dac_osr), 593 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 595 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 597 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 598 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 600 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 602 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 603 604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 605 6, 1, 1, wm_hubs_spkmix_tlv), 606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 607 2, 1, 1, wm_hubs_spkmix_tlv), 608 609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 610 6, 1, 1, wm_hubs_spkmix_tlv), 611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 612 2, 1, 1, wm_hubs_spkmix_tlv), 613 614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 615 10, 15, 0, wm8994_3d_tlv), 616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 617 8, 1, 0), 618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 619 10, 15, 0, wm8994_3d_tlv), 620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 621 8, 1, 0), 622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 623 10, 15, 0, wm8994_3d_tlv), 624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 625 8, 1, 0), 626 }; 627 628 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 630 eq_tlv), 631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 632 eq_tlv), 633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 634 eq_tlv), 635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 636 eq_tlv), 637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 638 eq_tlv), 639 640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 641 eq_tlv), 642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 643 eq_tlv), 644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 645 eq_tlv), 646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 647 eq_tlv), 648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 649 eq_tlv), 650 651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 652 eq_tlv), 653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 654 eq_tlv), 655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 656 eq_tlv), 657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 658 eq_tlv), 659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 660 eq_tlv), 661 }; 662 663 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 664 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 665 }; 666 667 static int clk_sys_event(struct snd_soc_dapm_widget *w, 668 struct snd_kcontrol *kcontrol, int event) 669 { 670 struct snd_soc_codec *codec = w->codec; 671 672 switch (event) { 673 case SND_SOC_DAPM_PRE_PMU: 674 return configure_clock(codec); 675 676 case SND_SOC_DAPM_POST_PMD: 677 configure_clock(codec); 678 break; 679 } 680 681 return 0; 682 } 683 684 static void wm8994_update_class_w(struct snd_soc_codec *codec) 685 { 686 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 687 int enable = 1; 688 int source = 0; /* GCC flow analysis can't track enable */ 689 int reg, reg_r; 690 691 /* Only support direct DAC->headphone paths */ 692 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); 693 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { 694 dev_vdbg(codec->dev, "HPL connected to output mixer\n"); 695 enable = 0; 696 } 697 698 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); 699 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { 700 dev_vdbg(codec->dev, "HPR connected to output mixer\n"); 701 enable = 0; 702 } 703 704 /* We also need the same setting for L/R and only one path */ 705 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 706 switch (reg) { 707 case WM8994_AIF2DACL_TO_DAC1L: 708 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 709 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 710 break; 711 case WM8994_AIF1DAC2L_TO_DAC1L: 712 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 713 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 714 break; 715 case WM8994_AIF1DAC1L_TO_DAC1L: 716 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 717 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 718 break; 719 default: 720 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 721 enable = 0; 722 break; 723 } 724 725 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 726 if (reg_r != reg) { 727 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 728 enable = 0; 729 } 730 731 if (enable) { 732 dev_dbg(codec->dev, "Class W enabled\n"); 733 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 734 WM8994_CP_DYN_PWR | 735 WM8994_CP_DYN_SRC_SEL_MASK, 736 source | WM8994_CP_DYN_PWR); 737 wm8994->hubs.class_w = true; 738 739 } else { 740 dev_dbg(codec->dev, "Class W disabled\n"); 741 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 742 WM8994_CP_DYN_PWR, 0); 743 wm8994->hubs.class_w = false; 744 } 745 } 746 747 static int late_enable_ev(struct snd_soc_dapm_widget *w, 748 struct snd_kcontrol *kcontrol, int event) 749 { 750 struct snd_soc_codec *codec = w->codec; 751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 752 753 switch (event) { 754 case SND_SOC_DAPM_PRE_PMU: 755 if (wm8994->aif1clk_enable) { 756 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 757 WM8994_AIF1CLK_ENA_MASK, 758 WM8994_AIF1CLK_ENA); 759 wm8994->aif1clk_enable = 0; 760 } 761 if (wm8994->aif2clk_enable) { 762 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 763 WM8994_AIF2CLK_ENA_MASK, 764 WM8994_AIF2CLK_ENA); 765 wm8994->aif2clk_enable = 0; 766 } 767 break; 768 } 769 770 /* We may also have postponed startup of DSP, handle that. */ 771 wm8958_aif_ev(w, kcontrol, event); 772 773 return 0; 774 } 775 776 static int late_disable_ev(struct snd_soc_dapm_widget *w, 777 struct snd_kcontrol *kcontrol, int event) 778 { 779 struct snd_soc_codec *codec = w->codec; 780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 781 782 switch (event) { 783 case SND_SOC_DAPM_POST_PMD: 784 if (wm8994->aif1clk_disable) { 785 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 786 WM8994_AIF1CLK_ENA_MASK, 0); 787 wm8994->aif1clk_disable = 0; 788 } 789 if (wm8994->aif2clk_disable) { 790 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 791 WM8994_AIF2CLK_ENA_MASK, 0); 792 wm8994->aif2clk_disable = 0; 793 } 794 break; 795 } 796 797 return 0; 798 } 799 800 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 801 struct snd_kcontrol *kcontrol, int event) 802 { 803 struct snd_soc_codec *codec = w->codec; 804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 805 806 switch (event) { 807 case SND_SOC_DAPM_PRE_PMU: 808 wm8994->aif1clk_enable = 1; 809 break; 810 case SND_SOC_DAPM_POST_PMD: 811 wm8994->aif1clk_disable = 1; 812 break; 813 } 814 815 return 0; 816 } 817 818 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 819 struct snd_kcontrol *kcontrol, int event) 820 { 821 struct snd_soc_codec *codec = w->codec; 822 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 823 824 switch (event) { 825 case SND_SOC_DAPM_PRE_PMU: 826 wm8994->aif2clk_enable = 1; 827 break; 828 case SND_SOC_DAPM_POST_PMD: 829 wm8994->aif2clk_disable = 1; 830 break; 831 } 832 833 return 0; 834 } 835 836 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 837 struct snd_kcontrol *kcontrol, int event) 838 { 839 late_enable_ev(w, kcontrol, event); 840 return 0; 841 } 842 843 static int micbias_ev(struct snd_soc_dapm_widget *w, 844 struct snd_kcontrol *kcontrol, int event) 845 { 846 late_enable_ev(w, kcontrol, event); 847 return 0; 848 } 849 850 static int dac_ev(struct snd_soc_dapm_widget *w, 851 struct snd_kcontrol *kcontrol, int event) 852 { 853 struct snd_soc_codec *codec = w->codec; 854 unsigned int mask = 1 << w->shift; 855 856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 857 mask, mask); 858 return 0; 859 } 860 861 static const char *hp_mux_text[] = { 862 "Mixer", 863 "DAC", 864 }; 865 866 #define WM8994_HP_ENUM(xname, xenum) \ 867 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 868 .info = snd_soc_info_enum_double, \ 869 .get = snd_soc_dapm_get_enum_double, \ 870 .put = wm8994_put_hp_enum, \ 871 .private_value = (unsigned long)&xenum } 872 873 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, 874 struct snd_ctl_elem_value *ucontrol) 875 { 876 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 877 struct snd_soc_dapm_widget *w = wlist->widgets[0]; 878 struct snd_soc_codec *codec = w->codec; 879 int ret; 880 881 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 882 883 wm8994_update_class_w(codec); 884 885 return ret; 886 } 887 888 static const struct soc_enum hpl_enum = 889 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); 890 891 static const struct snd_kcontrol_new hpl_mux = 892 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); 893 894 static const struct soc_enum hpr_enum = 895 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); 896 897 static const struct snd_kcontrol_new hpr_mux = 898 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); 899 900 static const char *adc_mux_text[] = { 901 "ADC", 902 "DMIC", 903 }; 904 905 static const struct soc_enum adc_enum = 906 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 907 908 static const struct snd_kcontrol_new adcl_mux = 909 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 910 911 static const struct snd_kcontrol_new adcr_mux = 912 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 913 914 static const struct snd_kcontrol_new left_speaker_mixer[] = { 915 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 916 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 917 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 918 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 919 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 920 }; 921 922 static const struct snd_kcontrol_new right_speaker_mixer[] = { 923 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 924 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 925 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 926 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 927 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 928 }; 929 930 /* Debugging; dump chip status after DAPM transitions */ 931 static int post_ev(struct snd_soc_dapm_widget *w, 932 struct snd_kcontrol *kcontrol, int event) 933 { 934 struct snd_soc_codec *codec = w->codec; 935 dev_dbg(codec->dev, "SRC status: %x\n", 936 snd_soc_read(codec, 937 WM8994_RATE_STATUS)); 938 return 0; 939 } 940 941 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 942 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 943 1, 1, 0), 944 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 945 0, 1, 0), 946 }; 947 948 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 949 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 950 1, 1, 0), 951 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 952 0, 1, 0), 953 }; 954 955 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 956 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 957 1, 1, 0), 958 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 959 0, 1, 0), 960 }; 961 962 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 963 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 964 1, 1, 0), 965 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 966 0, 1, 0), 967 }; 968 969 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 970 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 971 5, 1, 0), 972 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 973 4, 1, 0), 974 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 975 2, 1, 0), 976 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 977 1, 1, 0), 978 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 979 0, 1, 0), 980 }; 981 982 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 983 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 984 5, 1, 0), 985 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 986 4, 1, 0), 987 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 988 2, 1, 0), 989 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 990 1, 1, 0), 991 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 992 0, 1, 0), 993 }; 994 995 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 996 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 997 .info = snd_soc_info_volsw, \ 998 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 999 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 1000 1001 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1002 struct snd_ctl_elem_value *ucontrol) 1003 { 1004 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 1005 struct snd_soc_dapm_widget *w = wlist->widgets[0]; 1006 struct snd_soc_codec *codec = w->codec; 1007 int ret; 1008 1009 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1010 1011 wm8994_update_class_w(codec); 1012 1013 return ret; 1014 } 1015 1016 static const struct snd_kcontrol_new dac1l_mix[] = { 1017 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1018 5, 1, 0), 1019 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1020 4, 1, 0), 1021 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1022 2, 1, 0), 1023 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1024 1, 1, 0), 1025 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1026 0, 1, 0), 1027 }; 1028 1029 static const struct snd_kcontrol_new dac1r_mix[] = { 1030 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1031 5, 1, 0), 1032 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1033 4, 1, 0), 1034 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1035 2, 1, 0), 1036 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1037 1, 1, 0), 1038 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1039 0, 1, 0), 1040 }; 1041 1042 static const char *sidetone_text[] = { 1043 "ADC/DMIC1", "DMIC2", 1044 }; 1045 1046 static const struct soc_enum sidetone1_enum = 1047 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1048 1049 static const struct snd_kcontrol_new sidetone1_mux = 1050 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1051 1052 static const struct soc_enum sidetone2_enum = 1053 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1054 1055 static const struct snd_kcontrol_new sidetone2_mux = 1056 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1057 1058 static const char *aif1dac_text[] = { 1059 "AIF1DACDAT", "AIF3DACDAT", 1060 }; 1061 1062 static const struct soc_enum aif1dac_enum = 1063 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1064 1065 static const struct snd_kcontrol_new aif1dac_mux = 1066 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1067 1068 static const char *aif2dac_text[] = { 1069 "AIF2DACDAT", "AIF3DACDAT", 1070 }; 1071 1072 static const struct soc_enum aif2dac_enum = 1073 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1074 1075 static const struct snd_kcontrol_new aif2dac_mux = 1076 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1077 1078 static const char *aif2adc_text[] = { 1079 "AIF2ADCDAT", "AIF3DACDAT", 1080 }; 1081 1082 static const struct soc_enum aif2adc_enum = 1083 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1084 1085 static const struct snd_kcontrol_new aif2adc_mux = 1086 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1087 1088 static const char *aif3adc_text[] = { 1089 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1090 }; 1091 1092 static const struct soc_enum wm8994_aif3adc_enum = 1093 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1094 1095 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1096 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1097 1098 static const struct soc_enum wm8958_aif3adc_enum = 1099 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1100 1101 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1102 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1103 1104 static const char *mono_pcm_out_text[] = { 1105 "None", "AIF2ADCL", "AIF2ADCR", 1106 }; 1107 1108 static const struct soc_enum mono_pcm_out_enum = 1109 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1110 1111 static const struct snd_kcontrol_new mono_pcm_out_mux = 1112 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1113 1114 static const char *aif2dac_src_text[] = { 1115 "AIF2", "AIF3", 1116 }; 1117 1118 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1119 static const struct soc_enum aif2dacl_src_enum = 1120 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1121 1122 static const struct snd_kcontrol_new aif2dacl_src_mux = 1123 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1124 1125 static const struct soc_enum aif2dacr_src_enum = 1126 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1127 1128 static const struct snd_kcontrol_new aif2dacr_src_mux = 1129 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1130 1131 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1132 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev, 1133 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1134 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev, 1135 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1136 1137 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1138 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1139 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1140 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1141 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1143 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1145 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1147 1148 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1149 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1150 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1151 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1152 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1153 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1154 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux, 1155 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1156 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux, 1157 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1158 1159 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1160 }; 1161 1162 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1163 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 1164 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), 1165 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1166 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1167 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1168 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1169 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1170 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1171 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1172 }; 1173 1174 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1175 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1176 dac_ev, SND_SOC_DAPM_PRE_PMU), 1177 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1178 dac_ev, SND_SOC_DAPM_PRE_PMU), 1179 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1180 dac_ev, SND_SOC_DAPM_PRE_PMU), 1181 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1182 dac_ev, SND_SOC_DAPM_PRE_PMU), 1183 }; 1184 1185 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1186 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1187 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1188 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1189 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1190 }; 1191 1192 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1193 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1194 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1195 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1196 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1197 }; 1198 1199 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1200 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1201 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1202 }; 1203 1204 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1205 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1206 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1207 SND_SOC_DAPM_INPUT("Clock"), 1208 1209 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1210 SND_SOC_DAPM_PRE_PMU), 1211 1212 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1213 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1214 1215 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), 1216 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 1217 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 1218 1219 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1220 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1221 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1222 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1223 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1224 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, 1225 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1226 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1227 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, 1228 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1229 1230 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1231 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1232 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1233 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1234 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1235 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, 1236 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1237 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1238 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, 1239 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1240 1241 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1242 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1243 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1244 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1245 1246 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1247 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1248 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1249 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1250 1251 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1252 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1253 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1254 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1255 1256 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1257 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1258 1259 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1260 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1261 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1262 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1263 1264 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1265 WM8994_POWER_MANAGEMENT_4, 13, 0), 1266 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1267 WM8994_POWER_MANAGEMENT_4, 12, 0), 1268 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1269 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev, 1270 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1271 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1272 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev, 1273 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1274 1275 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1276 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1277 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1278 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1279 1280 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1281 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1282 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1283 1284 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1285 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1286 1287 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1288 1289 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1290 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1291 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1292 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1293 1294 /* Power is done with the muxes since the ADC power also controls the 1295 * downsampling chain, the chip will automatically manage the analogue 1296 * specific portions. 1297 */ 1298 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1299 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1300 1301 SND_SOC_DAPM_POST("Debug log", post_ev), 1302 }; 1303 1304 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1305 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1306 }; 1307 1308 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1309 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1310 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1311 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1312 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1313 }; 1314 1315 static const struct snd_soc_dapm_route intercon[] = { 1316 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1317 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1318 1319 { "DSP1CLK", NULL, "CLK_SYS" }, 1320 { "DSP2CLK", NULL, "CLK_SYS" }, 1321 { "DSPINTCLK", NULL, "CLK_SYS" }, 1322 1323 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1324 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1325 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1326 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1327 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1328 1329 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1330 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1331 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1332 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1333 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1334 1335 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1336 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1337 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1338 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1339 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1340 1341 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1342 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1343 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1344 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1345 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1346 1347 { "AIF2ADCL", NULL, "AIF2CLK" }, 1348 { "AIF2ADCL", NULL, "DSP2CLK" }, 1349 { "AIF2ADCR", NULL, "AIF2CLK" }, 1350 { "AIF2ADCR", NULL, "DSP2CLK" }, 1351 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1352 1353 { "AIF2DACL", NULL, "AIF2CLK" }, 1354 { "AIF2DACL", NULL, "DSP2CLK" }, 1355 { "AIF2DACR", NULL, "AIF2CLK" }, 1356 { "AIF2DACR", NULL, "DSP2CLK" }, 1357 { "AIF2DACR", NULL, "DSPINTCLK" }, 1358 1359 { "DMIC1L", NULL, "DMIC1DAT" }, 1360 { "DMIC1L", NULL, "CLK_SYS" }, 1361 { "DMIC1R", NULL, "DMIC1DAT" }, 1362 { "DMIC1R", NULL, "CLK_SYS" }, 1363 { "DMIC2L", NULL, "DMIC2DAT" }, 1364 { "DMIC2L", NULL, "CLK_SYS" }, 1365 { "DMIC2R", NULL, "DMIC2DAT" }, 1366 { "DMIC2R", NULL, "CLK_SYS" }, 1367 1368 { "ADCL", NULL, "AIF1CLK" }, 1369 { "ADCL", NULL, "DSP1CLK" }, 1370 { "ADCL", NULL, "DSPINTCLK" }, 1371 1372 { "ADCR", NULL, "AIF1CLK" }, 1373 { "ADCR", NULL, "DSP1CLK" }, 1374 { "ADCR", NULL, "DSPINTCLK" }, 1375 1376 { "ADCL Mux", "ADC", "ADCL" }, 1377 { "ADCL Mux", "DMIC", "DMIC1L" }, 1378 { "ADCR Mux", "ADC", "ADCR" }, 1379 { "ADCR Mux", "DMIC", "DMIC1R" }, 1380 1381 { "DAC1L", NULL, "AIF1CLK" }, 1382 { "DAC1L", NULL, "DSP1CLK" }, 1383 { "DAC1L", NULL, "DSPINTCLK" }, 1384 1385 { "DAC1R", NULL, "AIF1CLK" }, 1386 { "DAC1R", NULL, "DSP1CLK" }, 1387 { "DAC1R", NULL, "DSPINTCLK" }, 1388 1389 { "DAC2L", NULL, "AIF2CLK" }, 1390 { "DAC2L", NULL, "DSP2CLK" }, 1391 { "DAC2L", NULL, "DSPINTCLK" }, 1392 1393 { "DAC2R", NULL, "AIF2DACR" }, 1394 { "DAC2R", NULL, "AIF2CLK" }, 1395 { "DAC2R", NULL, "DSP2CLK" }, 1396 { "DAC2R", NULL, "DSPINTCLK" }, 1397 1398 { "TOCLK", NULL, "CLK_SYS" }, 1399 1400 /* AIF1 outputs */ 1401 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1402 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1403 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1404 1405 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1406 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1407 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1408 1409 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1410 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1411 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1412 1413 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1414 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1415 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1416 1417 /* Pin level routing for AIF3 */ 1418 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1419 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1420 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1421 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1422 1423 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1424 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1425 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1426 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1427 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1428 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1429 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1430 1431 /* DAC1 inputs */ 1432 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1433 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1434 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1435 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1436 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1437 1438 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1439 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1440 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1441 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1442 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1443 1444 /* DAC2/AIF2 outputs */ 1445 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1446 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1447 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1448 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1449 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1450 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1451 1452 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1453 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1454 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1455 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1456 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1457 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1458 1459 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1460 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1461 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1462 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1463 1464 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1465 1466 /* AIF3 output */ 1467 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1468 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1471 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1472 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1473 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1474 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1475 1476 /* Sidetone */ 1477 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1478 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1479 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1480 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1481 1482 /* Output stages */ 1483 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1484 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1485 1486 { "SPKL", "DAC1 Switch", "DAC1L" }, 1487 { "SPKL", "DAC2 Switch", "DAC2L" }, 1488 1489 { "SPKR", "DAC1 Switch", "DAC1R" }, 1490 { "SPKR", "DAC2 Switch", "DAC2R" }, 1491 1492 { "Left Headphone Mux", "DAC", "DAC1L" }, 1493 { "Right Headphone Mux", "DAC", "DAC1R" }, 1494 }; 1495 1496 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1497 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1498 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1499 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1500 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1501 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1502 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1503 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1504 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1505 }; 1506 1507 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1508 { "DAC1L", NULL, "DAC1L Mixer" }, 1509 { "DAC1R", NULL, "DAC1R Mixer" }, 1510 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1511 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1512 }; 1513 1514 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1515 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1516 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 1517 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 1518 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 1519 { "MICBIAS1", NULL, "CLK_SYS" }, 1520 { "MICBIAS1", NULL, "MICBIAS Supply" }, 1521 { "MICBIAS2", NULL, "CLK_SYS" }, 1522 { "MICBIAS2", NULL, "MICBIAS Supply" }, 1523 }; 1524 1525 static const struct snd_soc_dapm_route wm8994_intercon[] = { 1526 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 1527 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 1528 }; 1529 1530 static const struct snd_soc_dapm_route wm8958_intercon[] = { 1531 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 1532 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 1533 1534 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 1535 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 1536 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1537 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1538 1539 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 1540 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 1541 1542 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 1543 }; 1544 1545 /* The size in bits of the FLL divide multiplied by 10 1546 * to allow rounding later */ 1547 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1548 1549 struct fll_div { 1550 u16 outdiv; 1551 u16 n; 1552 u16 k; 1553 u16 clk_ref_div; 1554 u16 fll_fratio; 1555 }; 1556 1557 static int wm8994_get_fll_config(struct fll_div *fll, 1558 int freq_in, int freq_out) 1559 { 1560 u64 Kpart; 1561 unsigned int K, Ndiv, Nmod; 1562 1563 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1564 1565 /* Scale the input frequency down to <= 13.5MHz */ 1566 fll->clk_ref_div = 0; 1567 while (freq_in > 13500000) { 1568 fll->clk_ref_div++; 1569 freq_in /= 2; 1570 1571 if (fll->clk_ref_div > 3) 1572 return -EINVAL; 1573 } 1574 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1575 1576 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1577 fll->outdiv = 3; 1578 while (freq_out * (fll->outdiv + 1) < 90000000) { 1579 fll->outdiv++; 1580 if (fll->outdiv > 63) 1581 return -EINVAL; 1582 } 1583 freq_out *= fll->outdiv + 1; 1584 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1585 1586 if (freq_in > 1000000) { 1587 fll->fll_fratio = 0; 1588 } else if (freq_in > 256000) { 1589 fll->fll_fratio = 1; 1590 freq_in *= 2; 1591 } else if (freq_in > 128000) { 1592 fll->fll_fratio = 2; 1593 freq_in *= 4; 1594 } else if (freq_in > 64000) { 1595 fll->fll_fratio = 3; 1596 freq_in *= 8; 1597 } else { 1598 fll->fll_fratio = 4; 1599 freq_in *= 16; 1600 } 1601 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1602 1603 /* Now, calculate N.K */ 1604 Ndiv = freq_out / freq_in; 1605 1606 fll->n = Ndiv; 1607 Nmod = freq_out % freq_in; 1608 pr_debug("Nmod=%d\n", Nmod); 1609 1610 /* Calculate fractional part - scale up so we can round. */ 1611 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1612 1613 do_div(Kpart, freq_in); 1614 1615 K = Kpart & 0xFFFFFFFF; 1616 1617 if ((K % 10) >= 5) 1618 K += 5; 1619 1620 /* Move down to proper range now rounding is done */ 1621 fll->k = K / 10; 1622 1623 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1624 1625 return 0; 1626 } 1627 1628 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 1629 unsigned int freq_in, unsigned int freq_out) 1630 { 1631 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1632 int reg_offset, ret; 1633 struct fll_div fll; 1634 u16 reg, aif1, aif2; 1635 unsigned long timeout; 1636 1637 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) 1638 & WM8994_AIF1CLK_ENA; 1639 1640 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) 1641 & WM8994_AIF2CLK_ENA; 1642 1643 switch (id) { 1644 case WM8994_FLL1: 1645 reg_offset = 0; 1646 id = 0; 1647 break; 1648 case WM8994_FLL2: 1649 reg_offset = 0x20; 1650 id = 1; 1651 break; 1652 default: 1653 return -EINVAL; 1654 } 1655 1656 switch (src) { 1657 case 0: 1658 /* Allow no source specification when stopping */ 1659 if (freq_out) 1660 return -EINVAL; 1661 src = wm8994->fll[id].src; 1662 break; 1663 case WM8994_FLL_SRC_MCLK1: 1664 case WM8994_FLL_SRC_MCLK2: 1665 case WM8994_FLL_SRC_LRCLK: 1666 case WM8994_FLL_SRC_BCLK: 1667 break; 1668 default: 1669 return -EINVAL; 1670 } 1671 1672 /* Are we changing anything? */ 1673 if (wm8994->fll[id].src == src && 1674 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 1675 return 0; 1676 1677 /* If we're stopping the FLL redo the old config - no 1678 * registers will actually be written but we avoid GCC flow 1679 * analysis bugs spewing warnings. 1680 */ 1681 if (freq_out) 1682 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 1683 else 1684 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 1685 wm8994->fll[id].out); 1686 if (ret < 0) 1687 return ret; 1688 1689 /* Gate the AIF clocks while we reclock */ 1690 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1691 WM8994_AIF1CLK_ENA, 0); 1692 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1693 WM8994_AIF2CLK_ENA, 0); 1694 1695 /* We always need to disable the FLL while reconfiguring */ 1696 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1697 WM8994_FLL1_ENA, 0); 1698 1699 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 1700 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 1701 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 1702 WM8994_FLL1_OUTDIV_MASK | 1703 WM8994_FLL1_FRATIO_MASK, reg); 1704 1705 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); 1706 1707 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 1708 WM8994_FLL1_N_MASK, 1709 fll.n << WM8994_FLL1_N_SHIFT); 1710 1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 1712 WM8994_FLL1_REFCLK_DIV_MASK | 1713 WM8994_FLL1_REFCLK_SRC_MASK, 1714 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 1715 (src - 1)); 1716 1717 /* Clear any pending completion from a previous failure */ 1718 try_wait_for_completion(&wm8994->fll_locked[id]); 1719 1720 /* Enable (with fractional mode if required) */ 1721 if (freq_out) { 1722 if (fll.k) 1723 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; 1724 else 1725 reg = WM8994_FLL1_ENA; 1726 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1727 WM8994_FLL1_ENA | WM8994_FLL1_FRAC, 1728 reg); 1729 1730 if (wm8994->fll_locked_irq) { 1731 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 1732 msecs_to_jiffies(10)); 1733 if (timeout == 0) 1734 dev_warn(codec->dev, 1735 "Timed out waiting for FLL lock\n"); 1736 } else { 1737 msleep(5); 1738 } 1739 } 1740 1741 wm8994->fll[id].in = freq_in; 1742 wm8994->fll[id].out = freq_out; 1743 wm8994->fll[id].src = src; 1744 1745 /* Enable any gated AIF clocks */ 1746 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1747 WM8994_AIF1CLK_ENA, aif1); 1748 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1749 WM8994_AIF2CLK_ENA, aif2); 1750 1751 configure_clock(codec); 1752 1753 return 0; 1754 } 1755 1756 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 1757 { 1758 struct completion *completion = data; 1759 1760 complete(completion); 1761 1762 return IRQ_HANDLED; 1763 } 1764 1765 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 1766 1767 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 1768 unsigned int freq_in, unsigned int freq_out) 1769 { 1770 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 1771 } 1772 1773 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 1774 int clk_id, unsigned int freq, int dir) 1775 { 1776 struct snd_soc_codec *codec = dai->codec; 1777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1778 int i; 1779 1780 switch (dai->id) { 1781 case 1: 1782 case 2: 1783 break; 1784 1785 default: 1786 /* AIF3 shares clocking with AIF1/2 */ 1787 return -EINVAL; 1788 } 1789 1790 switch (clk_id) { 1791 case WM8994_SYSCLK_MCLK1: 1792 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 1793 wm8994->mclk[0] = freq; 1794 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 1795 dai->id, freq); 1796 break; 1797 1798 case WM8994_SYSCLK_MCLK2: 1799 /* TODO: Set GPIO AF */ 1800 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 1801 wm8994->mclk[1] = freq; 1802 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 1803 dai->id, freq); 1804 break; 1805 1806 case WM8994_SYSCLK_FLL1: 1807 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 1808 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 1809 break; 1810 1811 case WM8994_SYSCLK_FLL2: 1812 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 1813 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 1814 break; 1815 1816 case WM8994_SYSCLK_OPCLK: 1817 /* Special case - a division (times 10) is given and 1818 * no effect on main clocking. 1819 */ 1820 if (freq) { 1821 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 1822 if (opclk_divs[i] == freq) 1823 break; 1824 if (i == ARRAY_SIZE(opclk_divs)) 1825 return -EINVAL; 1826 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 1827 WM8994_OPCLK_DIV_MASK, i); 1828 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 1829 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 1830 } else { 1831 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 1832 WM8994_OPCLK_ENA, 0); 1833 } 1834 1835 default: 1836 return -EINVAL; 1837 } 1838 1839 configure_clock(codec); 1840 1841 return 0; 1842 } 1843 1844 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 1845 enum snd_soc_bias_level level) 1846 { 1847 struct wm8994 *control = codec->control_data; 1848 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1849 1850 switch (level) { 1851 case SND_SOC_BIAS_ON: 1852 break; 1853 1854 case SND_SOC_BIAS_PREPARE: 1855 /* VMID=2x40k */ 1856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1857 WM8994_VMID_SEL_MASK, 0x2); 1858 break; 1859 1860 case SND_SOC_BIAS_STANDBY: 1861 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1862 pm_runtime_get_sync(codec->dev); 1863 1864 switch (control->type) { 1865 case WM8994: 1866 if (wm8994->revision < 4) { 1867 /* Tweak DC servo and DSP 1868 * configuration for improved 1869 * performance. */ 1870 snd_soc_write(codec, 0x102, 0x3); 1871 snd_soc_write(codec, 0x56, 0x3); 1872 snd_soc_write(codec, 0x817, 0); 1873 snd_soc_write(codec, 0x102, 0); 1874 } 1875 break; 1876 1877 case WM8958: 1878 if (wm8994->revision == 0) { 1879 /* Optimise performance for rev A */ 1880 snd_soc_write(codec, 0x102, 0x3); 1881 snd_soc_write(codec, 0xcb, 0x81); 1882 snd_soc_write(codec, 0x817, 0); 1883 snd_soc_write(codec, 0x102, 0); 1884 1885 snd_soc_update_bits(codec, 1886 WM8958_CHARGE_PUMP_2, 1887 WM8958_CP_DISCH, 1888 WM8958_CP_DISCH); 1889 } 1890 break; 1891 } 1892 1893 /* Discharge LINEOUT1 & 2 */ 1894 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 1895 WM8994_LINEOUT1_DISCH | 1896 WM8994_LINEOUT2_DISCH, 1897 WM8994_LINEOUT1_DISCH | 1898 WM8994_LINEOUT2_DISCH); 1899 1900 /* Startup bias, VMID ramp & buffer */ 1901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1902 WM8994_STARTUP_BIAS_ENA | 1903 WM8994_VMID_BUF_ENA | 1904 WM8994_VMID_RAMP_MASK, 1905 WM8994_STARTUP_BIAS_ENA | 1906 WM8994_VMID_BUF_ENA | 1907 (0x11 << WM8994_VMID_RAMP_SHIFT)); 1908 1909 /* Main bias enable, VMID=2x40k */ 1910 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1911 WM8994_BIAS_ENA | 1912 WM8994_VMID_SEL_MASK, 1913 WM8994_BIAS_ENA | 0x2); 1914 1915 msleep(20); 1916 } 1917 1918 /* VMID=2x500k */ 1919 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1920 WM8994_VMID_SEL_MASK, 0x4); 1921 1922 break; 1923 1924 case SND_SOC_BIAS_OFF: 1925 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 1926 /* Switch over to startup biases */ 1927 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1928 WM8994_BIAS_SRC | 1929 WM8994_STARTUP_BIAS_ENA | 1930 WM8994_VMID_BUF_ENA | 1931 WM8994_VMID_RAMP_MASK, 1932 WM8994_BIAS_SRC | 1933 WM8994_STARTUP_BIAS_ENA | 1934 WM8994_VMID_BUF_ENA | 1935 (1 << WM8994_VMID_RAMP_SHIFT)); 1936 1937 /* Disable main biases */ 1938 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1939 WM8994_BIAS_ENA | 1940 WM8994_VMID_SEL_MASK, 0); 1941 1942 /* Discharge line */ 1943 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 1944 WM8994_LINEOUT1_DISCH | 1945 WM8994_LINEOUT2_DISCH, 1946 WM8994_LINEOUT1_DISCH | 1947 WM8994_LINEOUT2_DISCH); 1948 1949 msleep(5); 1950 1951 /* Switch off startup biases */ 1952 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1953 WM8994_BIAS_SRC | 1954 WM8994_STARTUP_BIAS_ENA | 1955 WM8994_VMID_BUF_ENA | 1956 WM8994_VMID_RAMP_MASK, 0); 1957 1958 wm8994->cur_fw = NULL; 1959 1960 pm_runtime_put(codec->dev); 1961 } 1962 break; 1963 } 1964 codec->dapm.bias_level = level; 1965 return 0; 1966 } 1967 1968 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1969 { 1970 struct snd_soc_codec *codec = dai->codec; 1971 struct wm8994 *control = codec->control_data; 1972 int ms_reg; 1973 int aif1_reg; 1974 int ms = 0; 1975 int aif1 = 0; 1976 1977 switch (dai->id) { 1978 case 1: 1979 ms_reg = WM8994_AIF1_MASTER_SLAVE; 1980 aif1_reg = WM8994_AIF1_CONTROL_1; 1981 break; 1982 case 2: 1983 ms_reg = WM8994_AIF2_MASTER_SLAVE; 1984 aif1_reg = WM8994_AIF2_CONTROL_1; 1985 break; 1986 default: 1987 return -EINVAL; 1988 } 1989 1990 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1991 case SND_SOC_DAIFMT_CBS_CFS: 1992 break; 1993 case SND_SOC_DAIFMT_CBM_CFM: 1994 ms = WM8994_AIF1_MSTR; 1995 break; 1996 default: 1997 return -EINVAL; 1998 } 1999 2000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2001 case SND_SOC_DAIFMT_DSP_B: 2002 aif1 |= WM8994_AIF1_LRCLK_INV; 2003 case SND_SOC_DAIFMT_DSP_A: 2004 aif1 |= 0x18; 2005 break; 2006 case SND_SOC_DAIFMT_I2S: 2007 aif1 |= 0x10; 2008 break; 2009 case SND_SOC_DAIFMT_RIGHT_J: 2010 break; 2011 case SND_SOC_DAIFMT_LEFT_J: 2012 aif1 |= 0x8; 2013 break; 2014 default: 2015 return -EINVAL; 2016 } 2017 2018 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2019 case SND_SOC_DAIFMT_DSP_A: 2020 case SND_SOC_DAIFMT_DSP_B: 2021 /* frame inversion not valid for DSP modes */ 2022 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2023 case SND_SOC_DAIFMT_NB_NF: 2024 break; 2025 case SND_SOC_DAIFMT_IB_NF: 2026 aif1 |= WM8994_AIF1_BCLK_INV; 2027 break; 2028 default: 2029 return -EINVAL; 2030 } 2031 break; 2032 2033 case SND_SOC_DAIFMT_I2S: 2034 case SND_SOC_DAIFMT_RIGHT_J: 2035 case SND_SOC_DAIFMT_LEFT_J: 2036 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2037 case SND_SOC_DAIFMT_NB_NF: 2038 break; 2039 case SND_SOC_DAIFMT_IB_IF: 2040 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2041 break; 2042 case SND_SOC_DAIFMT_IB_NF: 2043 aif1 |= WM8994_AIF1_BCLK_INV; 2044 break; 2045 case SND_SOC_DAIFMT_NB_IF: 2046 aif1 |= WM8994_AIF1_LRCLK_INV; 2047 break; 2048 default: 2049 return -EINVAL; 2050 } 2051 break; 2052 default: 2053 return -EINVAL; 2054 } 2055 2056 /* The AIF2 format configuration needs to be mirrored to AIF3 2057 * on WM8958 if it's in use so just do it all the time. */ 2058 if (control->type == WM8958 && dai->id == 2) 2059 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2060 WM8994_AIF1_LRCLK_INV | 2061 WM8958_AIF3_FMT_MASK, aif1); 2062 2063 snd_soc_update_bits(codec, aif1_reg, 2064 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2065 WM8994_AIF1_FMT_MASK, 2066 aif1); 2067 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2068 ms); 2069 2070 return 0; 2071 } 2072 2073 static struct { 2074 int val, rate; 2075 } srs[] = { 2076 { 0, 8000 }, 2077 { 1, 11025 }, 2078 { 2, 12000 }, 2079 { 3, 16000 }, 2080 { 4, 22050 }, 2081 { 5, 24000 }, 2082 { 6, 32000 }, 2083 { 7, 44100 }, 2084 { 8, 48000 }, 2085 { 9, 88200 }, 2086 { 10, 96000 }, 2087 }; 2088 2089 static int fs_ratios[] = { 2090 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2091 }; 2092 2093 static int bclk_divs[] = { 2094 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2095 640, 880, 960, 1280, 1760, 1920 2096 }; 2097 2098 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2099 struct snd_pcm_hw_params *params, 2100 struct snd_soc_dai *dai) 2101 { 2102 struct snd_soc_codec *codec = dai->codec; 2103 struct wm8994 *control = codec->control_data; 2104 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2105 int aif1_reg; 2106 int aif2_reg; 2107 int bclk_reg; 2108 int lrclk_reg; 2109 int rate_reg; 2110 int aif1 = 0; 2111 int aif2 = 0; 2112 int bclk = 0; 2113 int lrclk = 0; 2114 int rate_val = 0; 2115 int id = dai->id - 1; 2116 2117 int i, cur_val, best_val, bclk_rate, best; 2118 2119 switch (dai->id) { 2120 case 1: 2121 aif1_reg = WM8994_AIF1_CONTROL_1; 2122 aif2_reg = WM8994_AIF1_CONTROL_2; 2123 bclk_reg = WM8994_AIF1_BCLK; 2124 rate_reg = WM8994_AIF1_RATE; 2125 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2126 wm8994->lrclk_shared[0]) { 2127 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2128 } else { 2129 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2130 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2131 } 2132 break; 2133 case 2: 2134 aif1_reg = WM8994_AIF2_CONTROL_1; 2135 aif2_reg = WM8994_AIF2_CONTROL_2; 2136 bclk_reg = WM8994_AIF2_BCLK; 2137 rate_reg = WM8994_AIF2_RATE; 2138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2139 wm8994->lrclk_shared[1]) { 2140 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2141 } else { 2142 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2143 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2144 } 2145 break; 2146 case 3: 2147 switch (control->type) { 2148 case WM8958: 2149 aif1_reg = WM8958_AIF3_CONTROL_1; 2150 break; 2151 default: 2152 return 0; 2153 } 2154 default: 2155 return -EINVAL; 2156 } 2157 2158 bclk_rate = params_rate(params) * 2; 2159 switch (params_format(params)) { 2160 case SNDRV_PCM_FORMAT_S16_LE: 2161 bclk_rate *= 16; 2162 break; 2163 case SNDRV_PCM_FORMAT_S20_3LE: 2164 bclk_rate *= 20; 2165 aif1 |= 0x20; 2166 break; 2167 case SNDRV_PCM_FORMAT_S24_LE: 2168 bclk_rate *= 24; 2169 aif1 |= 0x40; 2170 break; 2171 case SNDRV_PCM_FORMAT_S32_LE: 2172 bclk_rate *= 32; 2173 aif1 |= 0x60; 2174 break; 2175 default: 2176 return -EINVAL; 2177 } 2178 2179 /* Try to find an appropriate sample rate; look for an exact match. */ 2180 for (i = 0; i < ARRAY_SIZE(srs); i++) 2181 if (srs[i].rate == params_rate(params)) 2182 break; 2183 if (i == ARRAY_SIZE(srs)) 2184 return -EINVAL; 2185 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2186 2187 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2188 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2189 dai->id, wm8994->aifclk[id], bclk_rate); 2190 2191 if (params_channels(params) == 1 && 2192 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2193 aif2 |= WM8994_AIF1_MONO; 2194 2195 if (wm8994->aifclk[id] == 0) { 2196 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2197 return -EINVAL; 2198 } 2199 2200 /* AIFCLK/fs ratio; look for a close match in either direction */ 2201 best = 0; 2202 best_val = abs((fs_ratios[0] * params_rate(params)) 2203 - wm8994->aifclk[id]); 2204 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2205 cur_val = abs((fs_ratios[i] * params_rate(params)) 2206 - wm8994->aifclk[id]); 2207 if (cur_val >= best_val) 2208 continue; 2209 best = i; 2210 best_val = cur_val; 2211 } 2212 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2213 dai->id, fs_ratios[best]); 2214 rate_val |= best; 2215 2216 /* We may not get quite the right frequency if using 2217 * approximate clocks so look for the closest match that is 2218 * higher than the target (we need to ensure that there enough 2219 * BCLKs to clock out the samples). 2220 */ 2221 best = 0; 2222 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2223 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2224 if (cur_val < 0) /* BCLK table is sorted */ 2225 break; 2226 best = i; 2227 } 2228 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2229 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2230 bclk_divs[best], bclk_rate); 2231 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2232 2233 lrclk = bclk_rate / params_rate(params); 2234 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2235 lrclk, bclk_rate / lrclk); 2236 2237 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2238 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2239 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2240 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2241 lrclk); 2242 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2243 WM8994_AIF1CLK_RATE_MASK, rate_val); 2244 2245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2246 switch (dai->id) { 2247 case 1: 2248 wm8994->dac_rates[0] = params_rate(params); 2249 wm8994_set_retune_mobile(codec, 0); 2250 wm8994_set_retune_mobile(codec, 1); 2251 break; 2252 case 2: 2253 wm8994->dac_rates[1] = params_rate(params); 2254 wm8994_set_retune_mobile(codec, 2); 2255 break; 2256 } 2257 } 2258 2259 return 0; 2260 } 2261 2262 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2263 struct snd_pcm_hw_params *params, 2264 struct snd_soc_dai *dai) 2265 { 2266 struct snd_soc_codec *codec = dai->codec; 2267 struct wm8994 *control = codec->control_data; 2268 int aif1_reg; 2269 int aif1 = 0; 2270 2271 switch (dai->id) { 2272 case 3: 2273 switch (control->type) { 2274 case WM8958: 2275 aif1_reg = WM8958_AIF3_CONTROL_1; 2276 break; 2277 default: 2278 return 0; 2279 } 2280 default: 2281 return 0; 2282 } 2283 2284 switch (params_format(params)) { 2285 case SNDRV_PCM_FORMAT_S16_LE: 2286 break; 2287 case SNDRV_PCM_FORMAT_S20_3LE: 2288 aif1 |= 0x20; 2289 break; 2290 case SNDRV_PCM_FORMAT_S24_LE: 2291 aif1 |= 0x40; 2292 break; 2293 case SNDRV_PCM_FORMAT_S32_LE: 2294 aif1 |= 0x60; 2295 break; 2296 default: 2297 return -EINVAL; 2298 } 2299 2300 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2301 } 2302 2303 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream, 2304 struct snd_soc_dai *dai) 2305 { 2306 struct snd_soc_codec *codec = dai->codec; 2307 int rate_reg = 0; 2308 2309 switch (dai->id) { 2310 case 1: 2311 rate_reg = WM8994_AIF1_RATE; 2312 break; 2313 case 2: 2314 rate_reg = WM8994_AIF1_RATE; 2315 break; 2316 default: 2317 break; 2318 } 2319 2320 /* If the DAI is idle then configure the divider tree for the 2321 * lowest output rate to save a little power if the clock is 2322 * still active (eg, because it is system clock). 2323 */ 2324 if (rate_reg && !dai->playback_active && !dai->capture_active) 2325 snd_soc_update_bits(codec, rate_reg, 2326 WM8994_AIF1_SR_MASK | 2327 WM8994_AIF1CLK_RATE_MASK, 0x9); 2328 } 2329 2330 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2331 { 2332 struct snd_soc_codec *codec = codec_dai->codec; 2333 int mute_reg; 2334 int reg; 2335 2336 switch (codec_dai->id) { 2337 case 1: 2338 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2339 break; 2340 case 2: 2341 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2342 break; 2343 default: 2344 return -EINVAL; 2345 } 2346 2347 if (mute) 2348 reg = WM8994_AIF1DAC1_MUTE; 2349 else 2350 reg = 0; 2351 2352 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2353 2354 return 0; 2355 } 2356 2357 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 2358 { 2359 struct snd_soc_codec *codec = codec_dai->codec; 2360 int reg, val, mask; 2361 2362 switch (codec_dai->id) { 2363 case 1: 2364 reg = WM8994_AIF1_MASTER_SLAVE; 2365 mask = WM8994_AIF1_TRI; 2366 break; 2367 case 2: 2368 reg = WM8994_AIF2_MASTER_SLAVE; 2369 mask = WM8994_AIF2_TRI; 2370 break; 2371 case 3: 2372 reg = WM8994_POWER_MANAGEMENT_6; 2373 mask = WM8994_AIF3_TRI; 2374 break; 2375 default: 2376 return -EINVAL; 2377 } 2378 2379 if (tristate) 2380 val = mask; 2381 else 2382 val = 0; 2383 2384 return snd_soc_update_bits(codec, reg, mask, val); 2385 } 2386 2387 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2388 2389 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2390 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2391 2392 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2393 .set_sysclk = wm8994_set_dai_sysclk, 2394 .set_fmt = wm8994_set_dai_fmt, 2395 .hw_params = wm8994_hw_params, 2396 .shutdown = wm8994_aif_shutdown, 2397 .digital_mute = wm8994_aif_mute, 2398 .set_pll = wm8994_set_fll, 2399 .set_tristate = wm8994_set_tristate, 2400 }; 2401 2402 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2403 .set_sysclk = wm8994_set_dai_sysclk, 2404 .set_fmt = wm8994_set_dai_fmt, 2405 .hw_params = wm8994_hw_params, 2406 .shutdown = wm8994_aif_shutdown, 2407 .digital_mute = wm8994_aif_mute, 2408 .set_pll = wm8994_set_fll, 2409 .set_tristate = wm8994_set_tristate, 2410 }; 2411 2412 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2413 .hw_params = wm8994_aif3_hw_params, 2414 .set_tristate = wm8994_set_tristate, 2415 }; 2416 2417 static struct snd_soc_dai_driver wm8994_dai[] = { 2418 { 2419 .name = "wm8994-aif1", 2420 .id = 1, 2421 .playback = { 2422 .stream_name = "AIF1 Playback", 2423 .channels_min = 1, 2424 .channels_max = 2, 2425 .rates = WM8994_RATES, 2426 .formats = WM8994_FORMATS, 2427 }, 2428 .capture = { 2429 .stream_name = "AIF1 Capture", 2430 .channels_min = 1, 2431 .channels_max = 2, 2432 .rates = WM8994_RATES, 2433 .formats = WM8994_FORMATS, 2434 }, 2435 .ops = &wm8994_aif1_dai_ops, 2436 }, 2437 { 2438 .name = "wm8994-aif2", 2439 .id = 2, 2440 .playback = { 2441 .stream_name = "AIF2 Playback", 2442 .channels_min = 1, 2443 .channels_max = 2, 2444 .rates = WM8994_RATES, 2445 .formats = WM8994_FORMATS, 2446 }, 2447 .capture = { 2448 .stream_name = "AIF2 Capture", 2449 .channels_min = 1, 2450 .channels_max = 2, 2451 .rates = WM8994_RATES, 2452 .formats = WM8994_FORMATS, 2453 }, 2454 .ops = &wm8994_aif2_dai_ops, 2455 }, 2456 { 2457 .name = "wm8994-aif3", 2458 .id = 3, 2459 .playback = { 2460 .stream_name = "AIF3 Playback", 2461 .channels_min = 1, 2462 .channels_max = 2, 2463 .rates = WM8994_RATES, 2464 .formats = WM8994_FORMATS, 2465 }, 2466 .capture = { 2467 .stream_name = "AIF3 Capture", 2468 .channels_min = 1, 2469 .channels_max = 2, 2470 .rates = WM8994_RATES, 2471 .formats = WM8994_FORMATS, 2472 }, 2473 .ops = &wm8994_aif3_dai_ops, 2474 } 2475 }; 2476 2477 #ifdef CONFIG_PM 2478 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) 2479 { 2480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2481 struct wm8994 *control = codec->control_data; 2482 int i, ret; 2483 2484 switch (control->type) { 2485 case WM8994: 2486 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0); 2487 break; 2488 case WM8958: 2489 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2490 WM8958_MICD_ENA, 0); 2491 break; 2492 } 2493 2494 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2495 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 2496 sizeof(struct wm8994_fll_config)); 2497 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 2498 if (ret < 0) 2499 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 2500 i + 1, ret); 2501 } 2502 2503 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 2504 2505 return 0; 2506 } 2507 2508 static int wm8994_resume(struct snd_soc_codec *codec) 2509 { 2510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2511 struct wm8994 *control = codec->control_data; 2512 int i, ret; 2513 unsigned int val, mask; 2514 2515 if (wm8994->revision < 4) { 2516 /* force a HW read */ 2517 val = wm8994_reg_read(codec->control_data, 2518 WM8994_POWER_MANAGEMENT_5); 2519 2520 /* modify the cache only */ 2521 codec->cache_only = 1; 2522 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | 2523 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; 2524 val &= mask; 2525 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 2526 mask, val); 2527 codec->cache_only = 0; 2528 } 2529 2530 /* Restore the registers */ 2531 ret = snd_soc_cache_sync(codec); 2532 if (ret != 0) 2533 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 2534 2535 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2536 2537 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2538 if (!wm8994->fll_suspend[i].out) 2539 continue; 2540 2541 ret = _wm8994_set_fll(codec, i + 1, 2542 wm8994->fll_suspend[i].src, 2543 wm8994->fll_suspend[i].in, 2544 wm8994->fll_suspend[i].out); 2545 if (ret < 0) 2546 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 2547 i + 1, ret); 2548 } 2549 2550 switch (control->type) { 2551 case WM8994: 2552 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 2553 snd_soc_update_bits(codec, WM8994_MICBIAS, 2554 WM8994_MICD_ENA, WM8994_MICD_ENA); 2555 break; 2556 case WM8958: 2557 if (wm8994->jack_cb) 2558 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2559 WM8958_MICD_ENA, WM8958_MICD_ENA); 2560 break; 2561 } 2562 2563 return 0; 2564 } 2565 #else 2566 #define wm8994_suspend NULL 2567 #define wm8994_resume NULL 2568 #endif 2569 2570 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 2571 { 2572 struct snd_soc_codec *codec = wm8994->codec; 2573 struct wm8994_pdata *pdata = wm8994->pdata; 2574 struct snd_kcontrol_new controls[] = { 2575 SOC_ENUM_EXT("AIF1.1 EQ Mode", 2576 wm8994->retune_mobile_enum, 2577 wm8994_get_retune_mobile_enum, 2578 wm8994_put_retune_mobile_enum), 2579 SOC_ENUM_EXT("AIF1.2 EQ Mode", 2580 wm8994->retune_mobile_enum, 2581 wm8994_get_retune_mobile_enum, 2582 wm8994_put_retune_mobile_enum), 2583 SOC_ENUM_EXT("AIF2 EQ Mode", 2584 wm8994->retune_mobile_enum, 2585 wm8994_get_retune_mobile_enum, 2586 wm8994_put_retune_mobile_enum), 2587 }; 2588 int ret, i, j; 2589 const char **t; 2590 2591 /* We need an array of texts for the enum API but the number 2592 * of texts is likely to be less than the number of 2593 * configurations due to the sample rate dependency of the 2594 * configurations. */ 2595 wm8994->num_retune_mobile_texts = 0; 2596 wm8994->retune_mobile_texts = NULL; 2597 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2598 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 2599 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2600 wm8994->retune_mobile_texts[j]) == 0) 2601 break; 2602 } 2603 2604 if (j != wm8994->num_retune_mobile_texts) 2605 continue; 2606 2607 /* Expand the array... */ 2608 t = krealloc(wm8994->retune_mobile_texts, 2609 sizeof(char *) * 2610 (wm8994->num_retune_mobile_texts + 1), 2611 GFP_KERNEL); 2612 if (t == NULL) 2613 continue; 2614 2615 /* ...store the new entry... */ 2616 t[wm8994->num_retune_mobile_texts] = 2617 pdata->retune_mobile_cfgs[i].name; 2618 2619 /* ...and remember the new version. */ 2620 wm8994->num_retune_mobile_texts++; 2621 wm8994->retune_mobile_texts = t; 2622 } 2623 2624 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2625 wm8994->num_retune_mobile_texts); 2626 2627 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 2628 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 2629 2630 ret = snd_soc_add_controls(wm8994->codec, controls, 2631 ARRAY_SIZE(controls)); 2632 if (ret != 0) 2633 dev_err(wm8994->codec->dev, 2634 "Failed to add ReTune Mobile controls: %d\n", ret); 2635 } 2636 2637 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 2638 { 2639 struct snd_soc_codec *codec = wm8994->codec; 2640 struct wm8994_pdata *pdata = wm8994->pdata; 2641 int ret, i; 2642 2643 if (!pdata) 2644 return; 2645 2646 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 2647 pdata->lineout2_diff, 2648 pdata->lineout1fb, 2649 pdata->lineout2fb, 2650 pdata->jd_scthr, 2651 pdata->jd_thr, 2652 pdata->micbias1_lvl, 2653 pdata->micbias2_lvl); 2654 2655 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2656 2657 if (pdata->num_drc_cfgs) { 2658 struct snd_kcontrol_new controls[] = { 2659 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 2660 wm8994_get_drc_enum, wm8994_put_drc_enum), 2661 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 2662 wm8994_get_drc_enum, wm8994_put_drc_enum), 2663 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 2664 wm8994_get_drc_enum, wm8994_put_drc_enum), 2665 }; 2666 2667 /* We need an array of texts for the enum API */ 2668 wm8994->drc_texts = kmalloc(sizeof(char *) 2669 * pdata->num_drc_cfgs, GFP_KERNEL); 2670 if (!wm8994->drc_texts) { 2671 dev_err(wm8994->codec->dev, 2672 "Failed to allocate %d DRC config texts\n", 2673 pdata->num_drc_cfgs); 2674 return; 2675 } 2676 2677 for (i = 0; i < pdata->num_drc_cfgs; i++) 2678 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 2679 2680 wm8994->drc_enum.max = pdata->num_drc_cfgs; 2681 wm8994->drc_enum.texts = wm8994->drc_texts; 2682 2683 ret = snd_soc_add_controls(wm8994->codec, controls, 2684 ARRAY_SIZE(controls)); 2685 if (ret != 0) 2686 dev_err(wm8994->codec->dev, 2687 "Failed to add DRC mode controls: %d\n", ret); 2688 2689 for (i = 0; i < WM8994_NUM_DRC; i++) 2690 wm8994_set_drc(codec, i); 2691 } 2692 2693 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2694 pdata->num_retune_mobile_cfgs); 2695 2696 if (pdata->num_retune_mobile_cfgs) 2697 wm8994_handle_retune_mobile_pdata(wm8994); 2698 else 2699 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, 2700 ARRAY_SIZE(wm8994_eq_controls)); 2701 2702 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 2703 if (pdata->micbias[i]) { 2704 snd_soc_write(codec, WM8958_MICBIAS1 + i, 2705 pdata->micbias[i] & 0xffff); 2706 } 2707 } 2708 } 2709 2710 /** 2711 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 2712 * 2713 * @codec: WM8994 codec 2714 * @jack: jack to report detection events on 2715 * @micbias: microphone bias to detect on 2716 * @det: value to report for presence detection 2717 * @shrt: value to report for short detection 2718 * 2719 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 2720 * being used to bring out signals to the processor then only platform 2721 * data configuration is needed for WM8994 and processor GPIOs should 2722 * be configured using snd_soc_jack_add_gpios() instead. 2723 * 2724 * Configuration of detection levels is available via the micbias1_lvl 2725 * and micbias2_lvl platform data members. 2726 */ 2727 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2728 int micbias, int det, int shrt) 2729 { 2730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2731 struct wm8994_micdet *micdet; 2732 struct wm8994 *control = codec->control_data; 2733 int reg; 2734 2735 if (control->type != WM8994) 2736 return -EINVAL; 2737 2738 switch (micbias) { 2739 case 1: 2740 micdet = &wm8994->micdet[0]; 2741 break; 2742 case 2: 2743 micdet = &wm8994->micdet[1]; 2744 break; 2745 default: 2746 return -EINVAL; 2747 } 2748 2749 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", 2750 micbias, det, shrt); 2751 2752 /* Store the configuration */ 2753 micdet->jack = jack; 2754 micdet->det = det; 2755 micdet->shrt = shrt; 2756 2757 /* If either of the jacks is set up then enable detection */ 2758 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 2759 reg = WM8994_MICD_ENA; 2760 else 2761 reg = 0; 2762 2763 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 2764 2765 return 0; 2766 } 2767 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 2768 2769 static irqreturn_t wm8994_mic_irq(int irq, void *data) 2770 { 2771 struct wm8994_priv *priv = data; 2772 struct snd_soc_codec *codec = priv->codec; 2773 int reg; 2774 int report; 2775 2776 #ifndef CONFIG_SND_SOC_WM8994_MODULE 2777 trace_snd_soc_jack_irq(dev_name(codec->dev)); 2778 #endif 2779 2780 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2781 if (reg < 0) { 2782 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2783 reg); 2784 return IRQ_HANDLED; 2785 } 2786 2787 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 2788 2789 report = 0; 2790 if (reg & WM8994_MIC1_DET_STS) 2791 report |= priv->micdet[0].det; 2792 if (reg & WM8994_MIC1_SHRT_STS) 2793 report |= priv->micdet[0].shrt; 2794 snd_soc_jack_report(priv->micdet[0].jack, report, 2795 priv->micdet[0].det | priv->micdet[0].shrt); 2796 2797 report = 0; 2798 if (reg & WM8994_MIC2_DET_STS) 2799 report |= priv->micdet[1].det; 2800 if (reg & WM8994_MIC2_SHRT_STS) 2801 report |= priv->micdet[1].shrt; 2802 snd_soc_jack_report(priv->micdet[1].jack, report, 2803 priv->micdet[1].det | priv->micdet[1].shrt); 2804 2805 return IRQ_HANDLED; 2806 } 2807 2808 /* Default microphone detection handler for WM8958 - the user can 2809 * override this if they wish. 2810 */ 2811 static void wm8958_default_micdet(u16 status, void *data) 2812 { 2813 struct snd_soc_codec *codec = data; 2814 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2815 int report = 0; 2816 2817 /* If nothing present then clear our statuses */ 2818 if (!(status & WM8958_MICD_STS)) 2819 goto done; 2820 2821 report = SND_JACK_MICROPHONE; 2822 2823 /* Everything else is buttons; just assign slots */ 2824 if (status & 0x1c) 2825 report |= SND_JACK_BTN_0; 2826 2827 done: 2828 snd_soc_jack_report(wm8994->micdet[0].jack, report, 2829 SND_JACK_BTN_0 | SND_JACK_MICROPHONE); 2830 } 2831 2832 /** 2833 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 2834 * 2835 * @codec: WM8958 codec 2836 * @jack: jack to report detection events on 2837 * 2838 * Enable microphone detection functionality for the WM8958. By 2839 * default simple detection which supports the detection of up to 6 2840 * buttons plus video and microphone functionality is supported. 2841 * 2842 * The WM8958 has an advanced jack detection facility which is able to 2843 * support complex accessory detection, especially when used in 2844 * conjunction with external circuitry. In order to provide maximum 2845 * flexiblity a callback is provided which allows a completely custom 2846 * detection algorithm. 2847 */ 2848 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2849 wm8958_micdet_cb cb, void *cb_data) 2850 { 2851 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2852 struct wm8994 *control = codec->control_data; 2853 2854 if (control->type != WM8958) 2855 return -EINVAL; 2856 2857 if (jack) { 2858 if (!cb) { 2859 dev_dbg(codec->dev, "Using default micdet callback\n"); 2860 cb = wm8958_default_micdet; 2861 cb_data = codec; 2862 } 2863 2864 wm8994->micdet[0].jack = jack; 2865 wm8994->jack_cb = cb; 2866 wm8994->jack_cb_data = cb_data; 2867 2868 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2869 WM8958_MICD_ENA, WM8958_MICD_ENA); 2870 } else { 2871 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2872 WM8958_MICD_ENA, 0); 2873 } 2874 2875 return 0; 2876 } 2877 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 2878 2879 static irqreturn_t wm8958_mic_irq(int irq, void *data) 2880 { 2881 struct wm8994_priv *wm8994 = data; 2882 struct snd_soc_codec *codec = wm8994->codec; 2883 int reg; 2884 2885 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 2886 if (reg < 0) { 2887 dev_err(codec->dev, "Failed to read mic detect status: %d\n", 2888 reg); 2889 return IRQ_NONE; 2890 } 2891 2892 if (!(reg & WM8958_MICD_VALID)) { 2893 dev_dbg(codec->dev, "Mic detect data not valid\n"); 2894 goto out; 2895 } 2896 2897 #ifndef CONFIG_SND_SOC_WM8994_MODULE 2898 trace_snd_soc_jack_irq(dev_name(codec->dev)); 2899 #endif 2900 2901 if (wm8994->jack_cb) 2902 wm8994->jack_cb(reg, wm8994->jack_cb_data); 2903 else 2904 dev_warn(codec->dev, "Accessory detection with no callback\n"); 2905 2906 out: 2907 return IRQ_HANDLED; 2908 } 2909 2910 static irqreturn_t wm8994_fifo_error(int irq, void *data) 2911 { 2912 struct snd_soc_codec *codec = data; 2913 2914 dev_err(codec->dev, "FIFO error\n"); 2915 2916 return IRQ_HANDLED; 2917 } 2918 2919 static int wm8994_codec_probe(struct snd_soc_codec *codec) 2920 { 2921 struct wm8994 *control; 2922 struct wm8994_priv *wm8994; 2923 struct snd_soc_dapm_context *dapm = &codec->dapm; 2924 int ret, i; 2925 2926 codec->control_data = dev_get_drvdata(codec->dev->parent); 2927 control = codec->control_data; 2928 2929 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 2930 if (wm8994 == NULL) 2931 return -ENOMEM; 2932 snd_soc_codec_set_drvdata(codec, wm8994); 2933 2934 wm8994->pdata = dev_get_platdata(codec->dev->parent); 2935 wm8994->codec = codec; 2936 2937 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 2938 init_completion(&wm8994->fll_locked[i]); 2939 2940 if (wm8994->pdata && wm8994->pdata->micdet_irq) 2941 wm8994->micdet_irq = wm8994->pdata->micdet_irq; 2942 else if (wm8994->pdata && wm8994->pdata->irq_base) 2943 wm8994->micdet_irq = wm8994->pdata->irq_base + 2944 WM8994_IRQ_MIC1_DET; 2945 2946 pm_runtime_enable(codec->dev); 2947 pm_runtime_resume(codec->dev); 2948 2949 /* Read our current status back from the chip - we don't want to 2950 * reset as this may interfere with the GPIO or LDO operation. */ 2951 for (i = 0; i < WM8994_CACHE_SIZE; i++) { 2952 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i)) 2953 continue; 2954 2955 ret = wm8994_reg_read(codec->control_data, i); 2956 if (ret <= 0) 2957 continue; 2958 2959 ret = snd_soc_cache_write(codec, i, ret); 2960 if (ret != 0) { 2961 dev_err(codec->dev, 2962 "Failed to initialise cache for 0x%x: %d\n", 2963 i, ret); 2964 goto err; 2965 } 2966 } 2967 2968 /* Set revision-specific configuration */ 2969 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 2970 switch (control->type) { 2971 case WM8994: 2972 switch (wm8994->revision) { 2973 case 2: 2974 case 3: 2975 wm8994->hubs.dcs_codes = -5; 2976 wm8994->hubs.hp_startup_mode = 1; 2977 wm8994->hubs.dcs_readback_mode = 1; 2978 wm8994->hubs.series_startup = 1; 2979 break; 2980 default: 2981 wm8994->hubs.dcs_readback_mode = 1; 2982 break; 2983 } 2984 break; 2985 2986 case WM8958: 2987 wm8994->hubs.dcs_readback_mode = 1; 2988 break; 2989 2990 default: 2991 break; 2992 } 2993 2994 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, 2995 wm8994_fifo_error, "FIFO error", codec); 2996 2997 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE, 2998 wm_hubs_dcs_done, "DC servo done", 2999 &wm8994->hubs); 3000 if (ret == 0) 3001 wm8994->hubs.dcs_done_irq = true; 3002 3003 switch (control->type) { 3004 case WM8994: 3005 if (wm8994->micdet_irq) { 3006 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3007 wm8994_mic_irq, 3008 IRQF_TRIGGER_RISING, 3009 "Mic1 detect", 3010 wm8994); 3011 if (ret != 0) 3012 dev_warn(codec->dev, 3013 "Failed to request Mic1 detect IRQ: %d\n", 3014 ret); 3015 } 3016 3017 ret = wm8994_request_irq(codec->control_data, 3018 WM8994_IRQ_MIC1_SHRT, 3019 wm8994_mic_irq, "Mic 1 short", 3020 wm8994); 3021 if (ret != 0) 3022 dev_warn(codec->dev, 3023 "Failed to request Mic1 short IRQ: %d\n", 3024 ret); 3025 3026 ret = wm8994_request_irq(codec->control_data, 3027 WM8994_IRQ_MIC2_DET, 3028 wm8994_mic_irq, "Mic 2 detect", 3029 wm8994); 3030 if (ret != 0) 3031 dev_warn(codec->dev, 3032 "Failed to request Mic2 detect IRQ: %d\n", 3033 ret); 3034 3035 ret = wm8994_request_irq(codec->control_data, 3036 WM8994_IRQ_MIC2_SHRT, 3037 wm8994_mic_irq, "Mic 2 short", 3038 wm8994); 3039 if (ret != 0) 3040 dev_warn(codec->dev, 3041 "Failed to request Mic2 short IRQ: %d\n", 3042 ret); 3043 break; 3044 3045 case WM8958: 3046 if (wm8994->micdet_irq) { 3047 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3048 wm8958_mic_irq, 3049 IRQF_TRIGGER_RISING, 3050 "Mic detect", 3051 wm8994); 3052 if (ret != 0) 3053 dev_warn(codec->dev, 3054 "Failed to request Mic detect IRQ: %d\n", 3055 ret); 3056 } 3057 } 3058 3059 wm8994->fll_locked_irq = true; 3060 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 3061 ret = wm8994_request_irq(codec->control_data, 3062 WM8994_IRQ_FLL1_LOCK + i, 3063 wm8994_fll_locked_irq, "FLL lock", 3064 &wm8994->fll_locked[i]); 3065 if (ret != 0) 3066 wm8994->fll_locked_irq = false; 3067 } 3068 3069 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3070 * configured on init - if a system wants to do this dynamically 3071 * at runtime we can deal with that then. 3072 */ 3073 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); 3074 if (ret < 0) { 3075 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 3076 goto err_irq; 3077 } 3078 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3079 wm8994->lrclk_shared[0] = 1; 3080 wm8994_dai[0].symmetric_rates = 1; 3081 } else { 3082 wm8994->lrclk_shared[0] = 0; 3083 } 3084 3085 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); 3086 if (ret < 0) { 3087 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 3088 goto err_irq; 3089 } 3090 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3091 wm8994->lrclk_shared[1] = 1; 3092 wm8994_dai[1].symmetric_rates = 1; 3093 } else { 3094 wm8994->lrclk_shared[1] = 0; 3095 } 3096 3097 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3098 3099 /* Latch volume updates (right only; we always do left then right). */ 3100 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME, 3101 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3102 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, 3103 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3104 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME, 3105 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3106 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, 3107 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3108 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME, 3109 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3110 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, 3111 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3112 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME, 3113 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3114 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, 3115 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3116 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME, 3117 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3118 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, 3119 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3120 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME, 3121 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3122 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, 3123 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3124 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME, 3125 WM8994_DAC1_VU, WM8994_DAC1_VU); 3126 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, 3127 WM8994_DAC1_VU, WM8994_DAC1_VU); 3128 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME, 3129 WM8994_DAC2_VU, WM8994_DAC2_VU); 3130 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, 3131 WM8994_DAC2_VU, WM8994_DAC2_VU); 3132 3133 /* Set the low bit of the 3D stereo depth so TLV matches */ 3134 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 3135 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 3136 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 3137 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 3138 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 3139 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 3140 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 3141 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 3142 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 3143 3144 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 3145 * use this; it only affects behaviour on idle TDM clock 3146 * cycles. */ 3147 switch (control->type) { 3148 case WM8994: 3149 case WM8958: 3150 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 3151 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 3152 break; 3153 default: 3154 break; 3155 } 3156 3157 wm8994_update_class_w(codec); 3158 3159 wm8994_handle_pdata(wm8994); 3160 3161 wm_hubs_add_analogue_controls(codec); 3162 snd_soc_add_controls(codec, wm8994_snd_controls, 3163 ARRAY_SIZE(wm8994_snd_controls)); 3164 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 3165 ARRAY_SIZE(wm8994_dapm_widgets)); 3166 3167 switch (control->type) { 3168 case WM8994: 3169 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 3170 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 3171 if (wm8994->revision < 4) { 3172 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 3173 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 3174 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 3175 ARRAY_SIZE(wm8994_adc_revd_widgets)); 3176 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 3177 ARRAY_SIZE(wm8994_dac_revd_widgets)); 3178 } else { 3179 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 3180 ARRAY_SIZE(wm8994_lateclk_widgets)); 3181 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 3182 ARRAY_SIZE(wm8994_adc_widgets)); 3183 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 3184 ARRAY_SIZE(wm8994_dac_widgets)); 3185 } 3186 break; 3187 case WM8958: 3188 snd_soc_add_controls(codec, wm8958_snd_controls, 3189 ARRAY_SIZE(wm8958_snd_controls)); 3190 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 3191 ARRAY_SIZE(wm8958_dapm_widgets)); 3192 if (wm8994->revision < 1) { 3193 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 3194 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 3195 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 3196 ARRAY_SIZE(wm8994_adc_revd_widgets)); 3197 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 3198 ARRAY_SIZE(wm8994_dac_revd_widgets)); 3199 } else { 3200 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 3201 ARRAY_SIZE(wm8994_lateclk_widgets)); 3202 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 3203 ARRAY_SIZE(wm8994_adc_widgets)); 3204 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 3205 ARRAY_SIZE(wm8994_dac_widgets)); 3206 } 3207 break; 3208 } 3209 3210 3211 wm_hubs_add_analogue_routes(codec, 0, 0); 3212 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 3213 3214 switch (control->type) { 3215 case WM8994: 3216 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 3217 ARRAY_SIZE(wm8994_intercon)); 3218 3219 if (wm8994->revision < 4) { 3220 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 3221 ARRAY_SIZE(wm8994_revd_intercon)); 3222 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 3223 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 3224 } else { 3225 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 3226 ARRAY_SIZE(wm8994_lateclk_intercon)); 3227 } 3228 break; 3229 case WM8958: 3230 if (wm8994->revision < 1) { 3231 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 3232 ARRAY_SIZE(wm8994_revd_intercon)); 3233 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 3234 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 3235 } else { 3236 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 3237 ARRAY_SIZE(wm8994_lateclk_intercon)); 3238 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 3239 ARRAY_SIZE(wm8958_intercon)); 3240 } 3241 3242 wm8958_dsp2_init(codec); 3243 break; 3244 } 3245 3246 return 0; 3247 3248 err_irq: 3249 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3250 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3251 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3252 if (wm8994->micdet_irq) 3253 free_irq(wm8994->micdet_irq, wm8994); 3254 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 3255 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i, 3256 &wm8994->fll_locked[i]); 3257 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE, 3258 &wm8994->hubs); 3259 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec); 3260 err: 3261 kfree(wm8994); 3262 return ret; 3263 } 3264 3265 static int wm8994_codec_remove(struct snd_soc_codec *codec) 3266 { 3267 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3268 struct wm8994 *control = codec->control_data; 3269 int i; 3270 3271 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3272 3273 pm_runtime_disable(codec->dev); 3274 3275 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 3276 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i, 3277 &wm8994->fll_locked[i]); 3278 3279 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE, 3280 &wm8994->hubs); 3281 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec); 3282 3283 switch (control->type) { 3284 case WM8994: 3285 if (wm8994->micdet_irq) 3286 free_irq(wm8994->micdet_irq, wm8994); 3287 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 3288 wm8994); 3289 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 3290 wm8994); 3291 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3292 wm8994); 3293 break; 3294 3295 case WM8958: 3296 if (wm8994->micdet_irq) 3297 free_irq(wm8994->micdet_irq, wm8994); 3298 break; 3299 } 3300 if (wm8994->mbc) 3301 release_firmware(wm8994->mbc); 3302 if (wm8994->mbc_vss) 3303 release_firmware(wm8994->mbc_vss); 3304 if (wm8994->enh_eq) 3305 release_firmware(wm8994->enh_eq); 3306 kfree(wm8994->retune_mobile_texts); 3307 kfree(wm8994->drc_texts); 3308 kfree(wm8994); 3309 3310 return 0; 3311 } 3312 3313 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 3314 .probe = wm8994_codec_probe, 3315 .remove = wm8994_codec_remove, 3316 .suspend = wm8994_suspend, 3317 .resume = wm8994_resume, 3318 .read = wm8994_read, 3319 .write = wm8994_write, 3320 .readable_register = wm8994_readable, 3321 .volatile_register = wm8994_volatile, 3322 .set_bias_level = wm8994_set_bias_level, 3323 3324 .reg_cache_size = WM8994_CACHE_SIZE, 3325 .reg_cache_default = wm8994_reg_defaults, 3326 .reg_word_size = 2, 3327 .compress_type = SND_SOC_RBTREE_COMPRESSION, 3328 }; 3329 3330 static int __devinit wm8994_probe(struct platform_device *pdev) 3331 { 3332 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 3333 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3334 } 3335 3336 static int __devexit wm8994_remove(struct platform_device *pdev) 3337 { 3338 snd_soc_unregister_codec(&pdev->dev); 3339 return 0; 3340 } 3341 3342 static struct platform_driver wm8994_codec_driver = { 3343 .driver = { 3344 .name = "wm8994-codec", 3345 .owner = THIS_MODULE, 3346 }, 3347 .probe = wm8994_probe, 3348 .remove = __devexit_p(wm8994_remove), 3349 }; 3350 3351 static __init int wm8994_init(void) 3352 { 3353 return platform_driver_register(&wm8994_codec_driver); 3354 } 3355 module_init(wm8994_init); 3356 3357 static __exit void wm8994_exit(void) 3358 { 3359 platform_driver_unregister(&wm8994_codec_driver); 3360 } 3361 module_exit(wm8994_exit); 3362 3363 3364 MODULE_DESCRIPTION("ASoC WM8994 driver"); 3365 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3366 MODULE_LICENSE("GPL"); 3367 MODULE_ALIAS("platform:wm8994-codec"); 3368