1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8994.c -- WM8994 ALSA SoC Audio driver 4 * 5 * Copyright 2009-12 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/gcd.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <trace/events/asoc.h> 29 30 #include <linux/mfd/wm8994/core.h> 31 #include <linux/mfd/wm8994/registers.h> 32 #include <linux/mfd/wm8994/pdata.h> 33 #include <linux/mfd/wm8994/gpio.h> 34 35 #include "wm8994.h" 36 #include "wm_hubs.h" 37 38 #define WM1811_JACKDET_MODE_NONE 0x0000 39 #define WM1811_JACKDET_MODE_JACK 0x0100 40 #define WM1811_JACKDET_MODE_MIC 0x0080 41 #define WM1811_JACKDET_MODE_AUDIO 0x0180 42 43 #define WM8994_NUM_DRC 3 44 #define WM8994_NUM_EQ 3 45 46 static struct { 47 unsigned int reg; 48 unsigned int mask; 49 } wm8994_vu_bits[] = { 50 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 51 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 52 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 53 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 54 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 55 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 56 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 57 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 58 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 59 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 60 61 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 62 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 63 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 64 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 65 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 66 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 67 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 68 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 69 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 70 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 71 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 72 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 73 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 74 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 75 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 76 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 77 }; 78 79 static int wm8994_drc_base[] = { 80 WM8994_AIF1_DRC1_1, 81 WM8994_AIF1_DRC2_1, 82 WM8994_AIF2_DRC_1, 83 }; 84 85 static int wm8994_retune_mobile_base[] = { 86 WM8994_AIF1_DAC1_EQ_GAINS_1, 87 WM8994_AIF1_DAC2_EQ_GAINS_1, 88 WM8994_AIF2_EQ_GAINS_1, 89 }; 90 91 static const struct wm8958_micd_rate micdet_rates[] = { 92 { 32768, true, 1, 4 }, 93 { 32768, false, 1, 1 }, 94 { 44100 * 256, true, 7, 10 }, 95 { 44100 * 256, false, 7, 10 }, 96 }; 97 98 static const struct wm8958_micd_rate jackdet_rates[] = { 99 { 32768, true, 0, 1 }, 100 { 32768, false, 0, 1 }, 101 { 44100 * 256, true, 10, 10 }, 102 { 44100 * 256, false, 7, 8 }, 103 }; 104 105 static void wm8958_micd_set_rate(struct snd_soc_component *component) 106 { 107 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 108 struct wm8994 *control = wm8994->wm8994; 109 int best, i, sysclk, val; 110 bool idle; 111 const struct wm8958_micd_rate *rates; 112 int num_rates; 113 114 idle = !wm8994->jack_mic; 115 116 sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1); 117 if (sysclk & WM8994_SYSCLK_SRC) 118 sysclk = wm8994->aifclk[1]; 119 else 120 sysclk = wm8994->aifclk[0]; 121 122 if (control->pdata.micd_rates) { 123 rates = control->pdata.micd_rates; 124 num_rates = control->pdata.num_micd_rates; 125 } else if (wm8994->jackdet) { 126 rates = jackdet_rates; 127 num_rates = ARRAY_SIZE(jackdet_rates); 128 } else { 129 rates = micdet_rates; 130 num_rates = ARRAY_SIZE(micdet_rates); 131 } 132 133 best = 0; 134 for (i = 0; i < num_rates; i++) { 135 if (rates[i].idle != idle) 136 continue; 137 if (abs(rates[i].sysclk - sysclk) < 138 abs(rates[best].sysclk - sysclk)) 139 best = i; 140 else if (rates[best].idle != idle) 141 best = i; 142 } 143 144 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 145 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 146 147 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n", 148 rates[best].start, rates[best].rate, sysclk, 149 idle ? "idle" : "active"); 150 151 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 152 WM8958_MICD_BIAS_STARTTIME_MASK | 153 WM8958_MICD_RATE_MASK, val); 154 } 155 156 static int configure_aif_clock(struct snd_soc_component *component, int aif) 157 { 158 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 159 int rate; 160 int reg1 = 0; 161 int offset; 162 163 if (aif) 164 offset = 4; 165 else 166 offset = 0; 167 168 switch (wm8994->sysclk[aif]) { 169 case WM8994_SYSCLK_MCLK1: 170 rate = wm8994->mclk_rate[0]; 171 break; 172 173 case WM8994_SYSCLK_MCLK2: 174 reg1 |= 0x8; 175 rate = wm8994->mclk_rate[1]; 176 break; 177 178 case WM8994_SYSCLK_FLL1: 179 reg1 |= 0x10; 180 rate = wm8994->fll[0].out; 181 break; 182 183 case WM8994_SYSCLK_FLL2: 184 reg1 |= 0x18; 185 rate = wm8994->fll[1].out; 186 break; 187 188 default: 189 return -EINVAL; 190 } 191 192 if (rate >= 13500000) { 193 rate /= 2; 194 reg1 |= WM8994_AIF1CLK_DIV; 195 196 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n", 197 aif + 1, rate); 198 } 199 200 wm8994->aifclk[aif] = rate; 201 202 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset, 203 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 204 reg1); 205 206 return 0; 207 } 208 209 static int configure_clock(struct snd_soc_component *component) 210 { 211 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 212 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 213 int change, new; 214 215 /* Bring up the AIF clocks first */ 216 configure_aif_clock(component, 0); 217 configure_aif_clock(component, 1); 218 219 /* Then switch CLK_SYS over to the higher of them; a change 220 * can only happen as a result of a clocking change which can 221 * only be made outside of DAPM so we can safely redo the 222 * clocking. 223 */ 224 225 /* If they're equal it doesn't matter which is used */ 226 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 227 wm8958_micd_set_rate(component); 228 return 0; 229 } 230 231 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 232 new = WM8994_SYSCLK_SRC; 233 else 234 new = 0; 235 236 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 237 WM8994_SYSCLK_SRC, new); 238 if (change) 239 snd_soc_dapm_sync(dapm); 240 241 wm8958_micd_set_rate(component); 242 243 return 0; 244 } 245 246 static int check_clk_sys(struct snd_soc_dapm_widget *source, 247 struct snd_soc_dapm_widget *sink) 248 { 249 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 250 int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); 251 const char *clk; 252 253 /* Check what we're currently using for CLK_SYS */ 254 if (reg & WM8994_SYSCLK_SRC) 255 clk = "AIF2CLK"; 256 else 257 clk = "AIF1CLK"; 258 259 return strcmp(source->name, clk) == 0; 260 } 261 262 static const char *sidetone_hpf_text[] = { 263 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 264 }; 265 266 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 267 WM8994_SIDETONE, 7, sidetone_hpf_text); 268 269 static const char *adc_hpf_text[] = { 270 "HiFi", "Voice 1", "Voice 2", "Voice 3" 271 }; 272 273 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf, 274 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text); 275 276 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf, 277 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text); 278 279 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf, 280 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text); 281 282 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 283 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 284 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 285 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 286 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 287 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 288 289 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 290 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ 291 snd_soc_get_volsw, wm8994_put_drc_sw) 292 293 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 294 struct snd_ctl_elem_value *ucontrol) 295 { 296 struct soc_mixer_control *mc = 297 (struct soc_mixer_control *)kcontrol->private_value; 298 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 299 int mask, ret; 300 301 /* Can't enable both ADC and DAC paths simultaneously */ 302 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 303 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 304 WM8994_AIF1ADC1R_DRC_ENA_MASK; 305 else 306 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 307 308 ret = snd_soc_component_read32(component, mc->reg); 309 if (ret < 0) 310 return ret; 311 if (ret & mask) 312 return -EINVAL; 313 314 return snd_soc_put_volsw(kcontrol, ucontrol); 315 } 316 317 static void wm8994_set_drc(struct snd_soc_component *component, int drc) 318 { 319 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 320 struct wm8994 *control = wm8994->wm8994; 321 struct wm8994_pdata *pdata = &control->pdata; 322 int base = wm8994_drc_base[drc]; 323 int cfg = wm8994->drc_cfg[drc]; 324 int save, i; 325 326 /* Save any enables; the configuration should clear them. */ 327 save = snd_soc_component_read32(component, base); 328 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 329 WM8994_AIF1ADC1R_DRC_ENA; 330 331 for (i = 0; i < WM8994_DRC_REGS; i++) 332 snd_soc_component_update_bits(component, base + i, 0xffff, 333 pdata->drc_cfgs[cfg].regs[i]); 334 335 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA | 336 WM8994_AIF1ADC1L_DRC_ENA | 337 WM8994_AIF1ADC1R_DRC_ENA, save); 338 } 339 340 /* Icky as hell but saves code duplication */ 341 static int wm8994_get_drc(const char *name) 342 { 343 if (strcmp(name, "AIF1DRC1 Mode") == 0) 344 return 0; 345 if (strcmp(name, "AIF1DRC2 Mode") == 0) 346 return 1; 347 if (strcmp(name, "AIF2DRC Mode") == 0) 348 return 2; 349 return -EINVAL; 350 } 351 352 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 353 struct snd_ctl_elem_value *ucontrol) 354 { 355 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 356 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 357 struct wm8994 *control = wm8994->wm8994; 358 struct wm8994_pdata *pdata = &control->pdata; 359 int drc = wm8994_get_drc(kcontrol->id.name); 360 int value = ucontrol->value.enumerated.item[0]; 361 362 if (drc < 0) 363 return drc; 364 365 if (value >= pdata->num_drc_cfgs) 366 return -EINVAL; 367 368 wm8994->drc_cfg[drc] = value; 369 370 wm8994_set_drc(component, drc); 371 372 return 0; 373 } 374 375 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 376 struct snd_ctl_elem_value *ucontrol) 377 { 378 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 379 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 380 int drc = wm8994_get_drc(kcontrol->id.name); 381 382 if (drc < 0) 383 return drc; 384 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 385 386 return 0; 387 } 388 389 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block) 390 { 391 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 392 struct wm8994 *control = wm8994->wm8994; 393 struct wm8994_pdata *pdata = &control->pdata; 394 int base = wm8994_retune_mobile_base[block]; 395 int iface, best, best_val, save, i, cfg; 396 397 if (!pdata || !wm8994->num_retune_mobile_texts) 398 return; 399 400 switch (block) { 401 case 0: 402 case 1: 403 iface = 0; 404 break; 405 case 2: 406 iface = 1; 407 break; 408 default: 409 return; 410 } 411 412 /* Find the version of the currently selected configuration 413 * with the nearest sample rate. */ 414 cfg = wm8994->retune_mobile_cfg[block]; 415 best = 0; 416 best_val = INT_MAX; 417 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 418 if (strcmp(pdata->retune_mobile_cfgs[i].name, 419 wm8994->retune_mobile_texts[cfg]) == 0 && 420 abs(pdata->retune_mobile_cfgs[i].rate 421 - wm8994->dac_rates[iface]) < best_val) { 422 best = i; 423 best_val = abs(pdata->retune_mobile_cfgs[i].rate 424 - wm8994->dac_rates[iface]); 425 } 426 } 427 428 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 429 block, 430 pdata->retune_mobile_cfgs[best].name, 431 pdata->retune_mobile_cfgs[best].rate, 432 wm8994->dac_rates[iface]); 433 434 /* The EQ will be disabled while reconfiguring it, remember the 435 * current configuration. 436 */ 437 save = snd_soc_component_read32(component, base); 438 save &= WM8994_AIF1DAC1_EQ_ENA; 439 440 for (i = 0; i < WM8994_EQ_REGS; i++) 441 snd_soc_component_update_bits(component, base + i, 0xffff, 442 pdata->retune_mobile_cfgs[best].regs[i]); 443 444 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save); 445 } 446 447 /* Icky as hell but saves code duplication */ 448 static int wm8994_get_retune_mobile_block(const char *name) 449 { 450 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 451 return 0; 452 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 453 return 1; 454 if (strcmp(name, "AIF2 EQ Mode") == 0) 455 return 2; 456 return -EINVAL; 457 } 458 459 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 460 struct snd_ctl_elem_value *ucontrol) 461 { 462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 463 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 464 struct wm8994 *control = wm8994->wm8994; 465 struct wm8994_pdata *pdata = &control->pdata; 466 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 467 int value = ucontrol->value.enumerated.item[0]; 468 469 if (block < 0) 470 return block; 471 472 if (value >= pdata->num_retune_mobile_cfgs) 473 return -EINVAL; 474 475 wm8994->retune_mobile_cfg[block] = value; 476 477 wm8994_set_retune_mobile(component, block); 478 479 return 0; 480 } 481 482 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 483 struct snd_ctl_elem_value *ucontrol) 484 { 485 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 486 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 487 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 488 489 if (block < 0) 490 return block; 491 492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 493 494 return 0; 495 } 496 497 static const char *aif_chan_src_text[] = { 498 "Left", "Right" 499 }; 500 501 static SOC_ENUM_SINGLE_DECL(aif1adcl_src, 502 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text); 503 504 static SOC_ENUM_SINGLE_DECL(aif1adcr_src, 505 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text); 506 507 static SOC_ENUM_SINGLE_DECL(aif2adcl_src, 508 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text); 509 510 static SOC_ENUM_SINGLE_DECL(aif2adcr_src, 511 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text); 512 513 static SOC_ENUM_SINGLE_DECL(aif1dacl_src, 514 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text); 515 516 static SOC_ENUM_SINGLE_DECL(aif1dacr_src, 517 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text); 518 519 static SOC_ENUM_SINGLE_DECL(aif2dacl_src, 520 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text); 521 522 static SOC_ENUM_SINGLE_DECL(aif2dacr_src, 523 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text); 524 525 static const char *osr_text[] = { 526 "Low Power", "High Performance", 527 }; 528 529 static SOC_ENUM_SINGLE_DECL(dac_osr, 530 WM8994_OVERSAMPLING, 0, osr_text); 531 532 static SOC_ENUM_SINGLE_DECL(adc_osr, 533 WM8994_OVERSAMPLING, 1, osr_text); 534 535 static const struct snd_kcontrol_new wm8994_common_snd_controls[] = { 536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 537 WM8994_AIF1_ADC1_RIGHT_VOLUME, 538 1, 119, 0, digital_tlv), 539 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 540 WM8994_AIF2_ADC_RIGHT_VOLUME, 541 1, 119, 0, digital_tlv), 542 543 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 544 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 545 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 546 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 547 548 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 549 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 550 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 551 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 552 553 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 554 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 555 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 556 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 557 558 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 559 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 560 561 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 562 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 563 564 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 565 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 566 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 567 568 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 569 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 570 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 571 572 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 573 5, 12, 0, st_tlv), 574 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 575 0, 12, 0, st_tlv), 576 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 577 5, 12, 0, st_tlv), 578 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 579 0, 12, 0, st_tlv), 580 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 581 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 582 583 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 584 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 585 586 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 587 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 588 589 SOC_ENUM("ADC OSR", adc_osr), 590 SOC_ENUM("DAC OSR", dac_osr), 591 592 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 593 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 594 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 595 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 596 597 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 598 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 599 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 600 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 601 602 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 603 6, 1, 1, wm_hubs_spkmix_tlv), 604 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 605 2, 1, 1, wm_hubs_spkmix_tlv), 606 607 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 608 6, 1, 1, wm_hubs_spkmix_tlv), 609 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 610 2, 1, 1, wm_hubs_spkmix_tlv), 611 612 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 613 10, 15, 0, wm8994_3d_tlv), 614 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 615 8, 1, 0), 616 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 617 10, 15, 0, wm8994_3d_tlv), 618 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 619 8, 1, 0), 620 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 621 10, 15, 0, wm8994_3d_tlv), 622 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 623 8, 1, 0), 624 }; 625 626 /* Controls not available on WM1811 */ 627 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 628 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 629 WM8994_AIF1_ADC2_RIGHT_VOLUME, 630 1, 119, 0, digital_tlv), 631 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 632 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 633 634 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 635 636 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 637 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 638 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 639 640 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 641 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 642 }; 643 644 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 646 eq_tlv), 647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 648 eq_tlv), 649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 650 eq_tlv), 651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 652 eq_tlv), 653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 654 eq_tlv), 655 656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 659 eq_tlv), 660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 661 eq_tlv), 662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 663 eq_tlv), 664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 665 eq_tlv), 666 667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 670 eq_tlv), 671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 672 eq_tlv), 673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 674 eq_tlv), 675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 676 eq_tlv), 677 }; 678 679 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 681 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 682 WM8994_AIF1ADC1R_DRC_ENA), 683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 684 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 685 WM8994_AIF1ADC2R_DRC_ENA), 686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 687 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 688 WM8994_AIF2ADCR_DRC_ENA), 689 }; 690 691 static const char *wm8958_ng_text[] = { 692 "30ms", "125ms", "250ms", "500ms", 693 }; 694 695 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold, 696 WM8958_AIF1_DAC1_NOISE_GATE, 697 WM8958_AIF1DAC1_NG_THR_SHIFT, 698 wm8958_ng_text); 699 700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold, 701 WM8958_AIF1_DAC2_NOISE_GATE, 702 WM8958_AIF1DAC2_NG_THR_SHIFT, 703 wm8958_ng_text); 704 705 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold, 706 WM8958_AIF2_DAC_NOISE_GATE, 707 WM8958_AIF2DAC_NG_THR_SHIFT, 708 wm8958_ng_text); 709 710 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 711 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 712 713 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 714 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 715 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 716 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 717 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 718 7, 1, ng_tlv), 719 720 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 721 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 722 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 723 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 724 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 725 7, 1, ng_tlv), 726 727 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 728 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 729 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 730 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 731 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 732 7, 1, ng_tlv), 733 }; 734 735 /* We run all mode setting through a function to enforce audio mode */ 736 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode) 737 { 738 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 739 740 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 741 return; 742 743 if (wm8994->active_refcount) 744 mode = WM1811_JACKDET_MODE_AUDIO; 745 746 if (mode == wm8994->jackdet_mode) 747 return; 748 749 wm8994->jackdet_mode = mode; 750 751 /* Always use audio mode to detect while the system is active */ 752 if (mode != WM1811_JACKDET_MODE_NONE) 753 mode = WM1811_JACKDET_MODE_AUDIO; 754 755 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 756 WM1811_JACKDET_MODE_MASK, mode); 757 } 758 759 static void active_reference(struct snd_soc_component *component) 760 { 761 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 762 763 mutex_lock(&wm8994->accdet_lock); 764 765 wm8994->active_refcount++; 766 767 dev_dbg(component->dev, "Active refcount incremented, now %d\n", 768 wm8994->active_refcount); 769 770 /* If we're using jack detection go into audio mode */ 771 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO); 772 773 mutex_unlock(&wm8994->accdet_lock); 774 } 775 776 static void active_dereference(struct snd_soc_component *component) 777 { 778 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 779 u16 mode; 780 781 mutex_lock(&wm8994->accdet_lock); 782 783 wm8994->active_refcount--; 784 785 dev_dbg(component->dev, "Active refcount decremented, now %d\n", 786 wm8994->active_refcount); 787 788 if (wm8994->active_refcount == 0) { 789 /* Go into appropriate detection only mode */ 790 if (wm8994->jack_mic || wm8994->mic_detecting) 791 mode = WM1811_JACKDET_MODE_MIC; 792 else 793 mode = WM1811_JACKDET_MODE_JACK; 794 795 wm1811_jackdet_set_mode(component, mode); 796 } 797 798 mutex_unlock(&wm8994->accdet_lock); 799 } 800 801 static int clk_sys_event(struct snd_soc_dapm_widget *w, 802 struct snd_kcontrol *kcontrol, int event) 803 { 804 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 805 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 806 807 switch (event) { 808 case SND_SOC_DAPM_PRE_PMU: 809 return configure_clock(component); 810 811 case SND_SOC_DAPM_POST_PMU: 812 /* 813 * JACKDET won't run until we start the clock and it 814 * only reports deltas, make sure we notify the state 815 * up the stack on startup. Use a *very* generous 816 * timeout for paranoia, there's no urgency and we 817 * don't want false reports. 818 */ 819 if (wm8994->jackdet && !wm8994->clk_has_run) { 820 queue_delayed_work(system_power_efficient_wq, 821 &wm8994->jackdet_bootstrap, 822 msecs_to_jiffies(1000)); 823 wm8994->clk_has_run = true; 824 } 825 break; 826 827 case SND_SOC_DAPM_POST_PMD: 828 configure_clock(component); 829 break; 830 } 831 832 return 0; 833 } 834 835 static void vmid_reference(struct snd_soc_component *component) 836 { 837 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 838 839 pm_runtime_get_sync(component->dev); 840 841 wm8994->vmid_refcount++; 842 843 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n", 844 wm8994->vmid_refcount); 845 846 if (wm8994->vmid_refcount == 1) { 847 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 848 WM8994_LINEOUT1_DISCH | 849 WM8994_LINEOUT2_DISCH, 0); 850 851 wm_hubs_vmid_ena(component); 852 853 switch (wm8994->vmid_mode) { 854 default: 855 WARN_ON(NULL == "Invalid VMID mode"); 856 /* fall through */ 857 case WM8994_VMID_NORMAL: 858 /* Startup bias, VMID ramp & buffer */ 859 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 860 WM8994_BIAS_SRC | 861 WM8994_VMID_DISCH | 862 WM8994_STARTUP_BIAS_ENA | 863 WM8994_VMID_BUF_ENA | 864 WM8994_VMID_RAMP_MASK, 865 WM8994_BIAS_SRC | 866 WM8994_STARTUP_BIAS_ENA | 867 WM8994_VMID_BUF_ENA | 868 (0x2 << WM8994_VMID_RAMP_SHIFT)); 869 870 /* Main bias enable, VMID=2x40k */ 871 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 872 WM8994_BIAS_ENA | 873 WM8994_VMID_SEL_MASK, 874 WM8994_BIAS_ENA | 0x2); 875 876 msleep(300); 877 878 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 879 WM8994_VMID_RAMP_MASK | 880 WM8994_BIAS_SRC, 881 0); 882 break; 883 884 case WM8994_VMID_FORCE: 885 /* Startup bias, slow VMID ramp & buffer */ 886 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 887 WM8994_BIAS_SRC | 888 WM8994_VMID_DISCH | 889 WM8994_STARTUP_BIAS_ENA | 890 WM8994_VMID_BUF_ENA | 891 WM8994_VMID_RAMP_MASK, 892 WM8994_BIAS_SRC | 893 WM8994_STARTUP_BIAS_ENA | 894 WM8994_VMID_BUF_ENA | 895 (0x2 << WM8994_VMID_RAMP_SHIFT)); 896 897 /* Main bias enable, VMID=2x40k */ 898 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 899 WM8994_BIAS_ENA | 900 WM8994_VMID_SEL_MASK, 901 WM8994_BIAS_ENA | 0x2); 902 903 msleep(400); 904 905 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 906 WM8994_VMID_RAMP_MASK | 907 WM8994_BIAS_SRC, 908 0); 909 break; 910 } 911 } 912 } 913 914 static void vmid_dereference(struct snd_soc_component *component) 915 { 916 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 917 918 wm8994->vmid_refcount--; 919 920 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n", 921 wm8994->vmid_refcount); 922 923 if (wm8994->vmid_refcount == 0) { 924 if (wm8994->hubs.lineout1_se) 925 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 926 WM8994_LINEOUT1N_ENA | 927 WM8994_LINEOUT1P_ENA, 928 WM8994_LINEOUT1N_ENA | 929 WM8994_LINEOUT1P_ENA); 930 931 if (wm8994->hubs.lineout2_se) 932 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 933 WM8994_LINEOUT2N_ENA | 934 WM8994_LINEOUT2P_ENA, 935 WM8994_LINEOUT2N_ENA | 936 WM8994_LINEOUT2P_ENA); 937 938 /* Start discharging VMID */ 939 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 940 WM8994_BIAS_SRC | 941 WM8994_VMID_DISCH, 942 WM8994_BIAS_SRC | 943 WM8994_VMID_DISCH); 944 945 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 946 WM8994_VMID_SEL_MASK, 0); 947 948 msleep(400); 949 950 /* Active discharge */ 951 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 952 WM8994_LINEOUT1_DISCH | 953 WM8994_LINEOUT2_DISCH, 954 WM8994_LINEOUT1_DISCH | 955 WM8994_LINEOUT2_DISCH); 956 957 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 958 WM8994_LINEOUT1N_ENA | 959 WM8994_LINEOUT1P_ENA | 960 WM8994_LINEOUT2N_ENA | 961 WM8994_LINEOUT2P_ENA, 0); 962 963 /* Switch off startup biases */ 964 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 965 WM8994_BIAS_SRC | 966 WM8994_STARTUP_BIAS_ENA | 967 WM8994_VMID_BUF_ENA | 968 WM8994_VMID_RAMP_MASK, 0); 969 970 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 971 WM8994_VMID_SEL_MASK, 0); 972 } 973 974 pm_runtime_put(component->dev); 975 } 976 977 static int vmid_event(struct snd_soc_dapm_widget *w, 978 struct snd_kcontrol *kcontrol, int event) 979 { 980 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 981 982 switch (event) { 983 case SND_SOC_DAPM_PRE_PMU: 984 vmid_reference(component); 985 break; 986 987 case SND_SOC_DAPM_POST_PMD: 988 vmid_dereference(component); 989 break; 990 } 991 992 return 0; 993 } 994 995 static bool wm8994_check_class_w_digital(struct snd_soc_component *component) 996 { 997 int source = 0; /* GCC flow analysis can't track enable */ 998 int reg, reg_r; 999 1000 /* We also need the same AIF source for L/R and only one path */ 1001 reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING); 1002 switch (reg) { 1003 case WM8994_AIF2DACL_TO_DAC1L: 1004 dev_vdbg(component->dev, "Class W source AIF2DAC\n"); 1005 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1006 break; 1007 case WM8994_AIF1DAC2L_TO_DAC1L: 1008 dev_vdbg(component->dev, "Class W source AIF1DAC2\n"); 1009 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1010 break; 1011 case WM8994_AIF1DAC1L_TO_DAC1L: 1012 dev_vdbg(component->dev, "Class W source AIF1DAC1\n"); 1013 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1014 break; 1015 default: 1016 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg); 1017 return false; 1018 } 1019 1020 reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1021 if (reg_r != reg) { 1022 dev_vdbg(component->dev, "Left and right DAC mixers different\n"); 1023 return false; 1024 } 1025 1026 /* Set the source up */ 1027 snd_soc_component_update_bits(component, WM8994_CLASS_W_1, 1028 WM8994_CP_DYN_SRC_SEL_MASK, source); 1029 1030 return true; 1031 } 1032 1033 static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable) 1034 { 1035 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1036 unsigned int offset, val, clk_idx; 1037 int ret; 1038 1039 if (aif) 1040 offset = 4; 1041 else 1042 offset = 0; 1043 1044 val = snd_soc_component_read32(component, WM8994_AIF1_CLOCKING_1 + offset); 1045 val &= WM8994_AIF1CLK_SRC_MASK; 1046 1047 switch (val) { 1048 case 0: 1049 clk_idx = WM8994_MCLK1; 1050 break; 1051 case 1: 1052 clk_idx = WM8994_MCLK2; 1053 break; 1054 default: 1055 return 0; 1056 } 1057 1058 if (enable) { 1059 ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk); 1060 if (ret < 0) { 1061 dev_err(component->dev, "Failed to enable MCLK%d\n", 1062 clk_idx); 1063 return ret; 1064 } 1065 } else { 1066 clk_disable_unprepare(wm8994->mclk[clk_idx].clk); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1073 struct snd_kcontrol *kcontrol, int event) 1074 { 1075 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1076 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1077 struct wm8994 *control = wm8994->wm8994; 1078 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1079 int ret, i; 1080 int dac; 1081 int adc; 1082 int val; 1083 1084 switch (control->type) { 1085 case WM8994: 1086 case WM8958: 1087 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 switch (event) { 1094 case SND_SOC_DAPM_PRE_PMU: 1095 ret = aif_mclk_set(component, 0, true); 1096 if (ret < 0) 1097 return ret; 1098 1099 /* Don't enable timeslot 2 if not in use */ 1100 if (wm8994->channels[0] <= 2) 1101 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1102 1103 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1); 1104 if ((val & WM8994_AIF1ADCL_SRC) && 1105 (val & WM8994_AIF1ADCR_SRC)) 1106 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1107 else if (!(val & WM8994_AIF1ADCL_SRC) && 1108 !(val & WM8994_AIF1ADCR_SRC)) 1109 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1110 else 1111 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1112 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1113 1114 val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2); 1115 if ((val & WM8994_AIF1DACL_SRC) && 1116 (val & WM8994_AIF1DACR_SRC)) 1117 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1118 else if (!(val & WM8994_AIF1DACL_SRC) && 1119 !(val & WM8994_AIF1DACR_SRC)) 1120 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1121 else 1122 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1123 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1124 1125 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1126 mask, adc); 1127 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1128 mask, dac); 1129 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1130 WM8994_AIF1DSPCLK_ENA | 1131 WM8994_SYSDSPCLK_ENA, 1132 WM8994_AIF1DSPCLK_ENA | 1133 WM8994_SYSDSPCLK_ENA); 1134 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask, 1135 WM8994_AIF1ADC1R_ENA | 1136 WM8994_AIF1ADC1L_ENA | 1137 WM8994_AIF1ADC2R_ENA | 1138 WM8994_AIF1ADC2L_ENA); 1139 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask, 1140 WM8994_AIF1DAC1R_ENA | 1141 WM8994_AIF1DAC1L_ENA | 1142 WM8994_AIF1DAC2R_ENA | 1143 WM8994_AIF1DAC2L_ENA); 1144 break; 1145 1146 case SND_SOC_DAPM_POST_PMU: 1147 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1148 snd_soc_component_write(component, wm8994_vu_bits[i].reg, 1149 snd_soc_component_read32(component, 1150 wm8994_vu_bits[i].reg)); 1151 break; 1152 1153 case SND_SOC_DAPM_PRE_PMD: 1154 case SND_SOC_DAPM_POST_PMD: 1155 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1156 mask, 0); 1157 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1158 mask, 0); 1159 1160 val = snd_soc_component_read32(component, WM8994_CLOCKING_1); 1161 if (val & WM8994_AIF2DSPCLK_ENA) 1162 val = WM8994_SYSDSPCLK_ENA; 1163 else 1164 val = 0; 1165 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1166 WM8994_SYSDSPCLK_ENA | 1167 WM8994_AIF1DSPCLK_ENA, val); 1168 break; 1169 } 1170 1171 switch (event) { 1172 case SND_SOC_DAPM_POST_PMD: 1173 aif_mclk_set(component, 0, false); 1174 break; 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1181 struct snd_kcontrol *kcontrol, int event) 1182 { 1183 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1184 int ret, i; 1185 int dac; 1186 int adc; 1187 int val; 1188 1189 switch (event) { 1190 case SND_SOC_DAPM_PRE_PMU: 1191 ret = aif_mclk_set(component, 1, true); 1192 if (ret < 0) 1193 return ret; 1194 1195 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1); 1196 if ((val & WM8994_AIF2ADCL_SRC) && 1197 (val & WM8994_AIF2ADCR_SRC)) 1198 adc = WM8994_AIF2ADCR_ENA; 1199 else if (!(val & WM8994_AIF2ADCL_SRC) && 1200 !(val & WM8994_AIF2ADCR_SRC)) 1201 adc = WM8994_AIF2ADCL_ENA; 1202 else 1203 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1204 1205 1206 val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2); 1207 if ((val & WM8994_AIF2DACL_SRC) && 1208 (val & WM8994_AIF2DACR_SRC)) 1209 dac = WM8994_AIF2DACR_ENA; 1210 else if (!(val & WM8994_AIF2DACL_SRC) && 1211 !(val & WM8994_AIF2DACR_SRC)) 1212 dac = WM8994_AIF2DACL_ENA; 1213 else 1214 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1215 1216 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1217 WM8994_AIF2ADCL_ENA | 1218 WM8994_AIF2ADCR_ENA, adc); 1219 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1220 WM8994_AIF2DACL_ENA | 1221 WM8994_AIF2DACR_ENA, dac); 1222 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1223 WM8994_AIF2DSPCLK_ENA | 1224 WM8994_SYSDSPCLK_ENA, 1225 WM8994_AIF2DSPCLK_ENA | 1226 WM8994_SYSDSPCLK_ENA); 1227 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1228 WM8994_AIF2ADCL_ENA | 1229 WM8994_AIF2ADCR_ENA, 1230 WM8994_AIF2ADCL_ENA | 1231 WM8994_AIF2ADCR_ENA); 1232 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1233 WM8994_AIF2DACL_ENA | 1234 WM8994_AIF2DACR_ENA, 1235 WM8994_AIF2DACL_ENA | 1236 WM8994_AIF2DACR_ENA); 1237 break; 1238 1239 case SND_SOC_DAPM_POST_PMU: 1240 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1241 snd_soc_component_write(component, wm8994_vu_bits[i].reg, 1242 snd_soc_component_read32(component, 1243 wm8994_vu_bits[i].reg)); 1244 break; 1245 1246 case SND_SOC_DAPM_PRE_PMD: 1247 case SND_SOC_DAPM_POST_PMD: 1248 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1249 WM8994_AIF2DACL_ENA | 1250 WM8994_AIF2DACR_ENA, 0); 1251 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1252 WM8994_AIF2ADCL_ENA | 1253 WM8994_AIF2ADCR_ENA, 0); 1254 1255 val = snd_soc_component_read32(component, WM8994_CLOCKING_1); 1256 if (val & WM8994_AIF1DSPCLK_ENA) 1257 val = WM8994_SYSDSPCLK_ENA; 1258 else 1259 val = 0; 1260 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1261 WM8994_SYSDSPCLK_ENA | 1262 WM8994_AIF2DSPCLK_ENA, val); 1263 break; 1264 } 1265 1266 switch (event) { 1267 case SND_SOC_DAPM_POST_PMD: 1268 aif_mclk_set(component, 1, false); 1269 break; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1276 struct snd_kcontrol *kcontrol, int event) 1277 { 1278 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1279 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1280 1281 switch (event) { 1282 case SND_SOC_DAPM_PRE_PMU: 1283 wm8994->aif1clk_enable = 1; 1284 break; 1285 case SND_SOC_DAPM_POST_PMD: 1286 wm8994->aif1clk_disable = 1; 1287 break; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1294 struct snd_kcontrol *kcontrol, int event) 1295 { 1296 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1297 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1298 1299 switch (event) { 1300 case SND_SOC_DAPM_PRE_PMU: 1301 wm8994->aif2clk_enable = 1; 1302 break; 1303 case SND_SOC_DAPM_POST_PMD: 1304 wm8994->aif2clk_disable = 1; 1305 break; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1312 struct snd_kcontrol *kcontrol, int event) 1313 { 1314 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1315 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1316 1317 switch (event) { 1318 case SND_SOC_DAPM_PRE_PMU: 1319 if (wm8994->aif1clk_enable) { 1320 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1321 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1322 WM8994_AIF1CLK_ENA_MASK, 1323 WM8994_AIF1CLK_ENA); 1324 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1325 wm8994->aif1clk_enable = 0; 1326 } 1327 if (wm8994->aif2clk_enable) { 1328 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1329 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1330 WM8994_AIF2CLK_ENA_MASK, 1331 WM8994_AIF2CLK_ENA); 1332 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1333 wm8994->aif2clk_enable = 0; 1334 } 1335 break; 1336 } 1337 1338 /* We may also have postponed startup of DSP, handle that. */ 1339 wm8958_aif_ev(w, kcontrol, event); 1340 1341 return 0; 1342 } 1343 1344 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1345 struct snd_kcontrol *kcontrol, int event) 1346 { 1347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1348 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1349 1350 switch (event) { 1351 case SND_SOC_DAPM_POST_PMD: 1352 if (wm8994->aif1clk_disable) { 1353 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1354 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1355 WM8994_AIF1CLK_ENA_MASK, 0); 1356 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1357 wm8994->aif1clk_disable = 0; 1358 } 1359 if (wm8994->aif2clk_disable) { 1360 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1361 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1362 WM8994_AIF2CLK_ENA_MASK, 0); 1363 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1364 wm8994->aif2clk_disable = 0; 1365 } 1366 break; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1373 struct snd_kcontrol *kcontrol, int event) 1374 { 1375 late_enable_ev(w, kcontrol, event); 1376 return 0; 1377 } 1378 1379 static int micbias_ev(struct snd_soc_dapm_widget *w, 1380 struct snd_kcontrol *kcontrol, int event) 1381 { 1382 late_enable_ev(w, kcontrol, event); 1383 return 0; 1384 } 1385 1386 static int dac_ev(struct snd_soc_dapm_widget *w, 1387 struct snd_kcontrol *kcontrol, int event) 1388 { 1389 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1390 unsigned int mask = 1 << w->shift; 1391 1392 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1393 mask, mask); 1394 return 0; 1395 } 1396 1397 static const char *adc_mux_text[] = { 1398 "ADC", 1399 "DMIC", 1400 }; 1401 1402 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 1403 1404 static const struct snd_kcontrol_new adcl_mux = 1405 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 1406 1407 static const struct snd_kcontrol_new adcr_mux = 1408 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 1409 1410 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1411 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1412 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1413 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1414 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1415 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1416 }; 1417 1418 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1419 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1420 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1421 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1422 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1423 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1424 }; 1425 1426 /* Debugging; dump chip status after DAPM transitions */ 1427 static int post_ev(struct snd_soc_dapm_widget *w, 1428 struct snd_kcontrol *kcontrol, int event) 1429 { 1430 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1431 dev_dbg(component->dev, "SRC status: %x\n", 1432 snd_soc_component_read32(component, 1433 WM8994_RATE_STATUS)); 1434 return 0; 1435 } 1436 1437 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1438 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1439 1, 1, 0), 1440 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1441 0, 1, 0), 1442 }; 1443 1444 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1445 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1446 1, 1, 0), 1447 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1448 0, 1, 0), 1449 }; 1450 1451 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1452 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1453 1, 1, 0), 1454 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1455 0, 1, 0), 1456 }; 1457 1458 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1459 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1460 1, 1, 0), 1461 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1462 0, 1, 0), 1463 }; 1464 1465 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1466 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1467 5, 1, 0), 1468 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1469 4, 1, 0), 1470 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1471 2, 1, 0), 1472 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1473 1, 1, 0), 1474 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1475 0, 1, 0), 1476 }; 1477 1478 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1479 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1480 5, 1, 0), 1481 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1482 4, 1, 0), 1483 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1484 2, 1, 0), 1485 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1486 1, 1, 0), 1487 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1488 0, 1, 0), 1489 }; 1490 1491 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1492 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 1493 snd_soc_dapm_get_volsw, wm8994_put_class_w) 1494 1495 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1496 struct snd_ctl_elem_value *ucontrol) 1497 { 1498 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 1499 int ret; 1500 1501 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1502 1503 wm_hubs_update_class_w(component); 1504 1505 return ret; 1506 } 1507 1508 static const struct snd_kcontrol_new dac1l_mix[] = { 1509 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1510 5, 1, 0), 1511 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1512 4, 1, 0), 1513 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1514 2, 1, 0), 1515 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1516 1, 1, 0), 1517 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1518 0, 1, 0), 1519 }; 1520 1521 static const struct snd_kcontrol_new dac1r_mix[] = { 1522 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1523 5, 1, 0), 1524 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1525 4, 1, 0), 1526 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1527 2, 1, 0), 1528 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1529 1, 1, 0), 1530 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1531 0, 1, 0), 1532 }; 1533 1534 static const char *sidetone_text[] = { 1535 "ADC/DMIC1", "DMIC2", 1536 }; 1537 1538 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, 1539 WM8994_SIDETONE, 0, sidetone_text); 1540 1541 static const struct snd_kcontrol_new sidetone1_mux = 1542 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1543 1544 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, 1545 WM8994_SIDETONE, 1, sidetone_text); 1546 1547 static const struct snd_kcontrol_new sidetone2_mux = 1548 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1549 1550 static const char *aif1dac_text[] = { 1551 "AIF1DACDAT", "AIF3DACDAT", 1552 }; 1553 1554 static const char *loopback_text[] = { 1555 "None", "ADCDAT", 1556 }; 1557 1558 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum, 1559 WM8994_AIF1_CONTROL_2, 1560 WM8994_AIF1_LOOPBACK_SHIFT, 1561 loopback_text); 1562 1563 static const struct snd_kcontrol_new aif1_loopback = 1564 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum); 1565 1566 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum, 1567 WM8994_AIF2_CONTROL_2, 1568 WM8994_AIF2_LOOPBACK_SHIFT, 1569 loopback_text); 1570 1571 static const struct snd_kcontrol_new aif2_loopback = 1572 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum); 1573 1574 static SOC_ENUM_SINGLE_DECL(aif1dac_enum, 1575 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text); 1576 1577 static const struct snd_kcontrol_new aif1dac_mux = 1578 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1579 1580 static const char *aif2dac_text[] = { 1581 "AIF2DACDAT", "AIF3DACDAT", 1582 }; 1583 1584 static SOC_ENUM_SINGLE_DECL(aif2dac_enum, 1585 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text); 1586 1587 static const struct snd_kcontrol_new aif2dac_mux = 1588 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1589 1590 static const char *aif2adc_text[] = { 1591 "AIF2ADCDAT", "AIF3DACDAT", 1592 }; 1593 1594 static SOC_ENUM_SINGLE_DECL(aif2adc_enum, 1595 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text); 1596 1597 static const struct snd_kcontrol_new aif2adc_mux = 1598 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1599 1600 static const char *aif3adc_text[] = { 1601 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1602 }; 1603 1604 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum, 1605 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1606 1607 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1608 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1609 1610 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum, 1611 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1612 1613 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1614 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1615 1616 static const char *mono_pcm_out_text[] = { 1617 "None", "AIF2ADCL", "AIF2ADCR", 1618 }; 1619 1620 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum, 1621 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text); 1622 1623 static const struct snd_kcontrol_new mono_pcm_out_mux = 1624 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1625 1626 static const char *aif2dac_src_text[] = { 1627 "AIF2", "AIF3", 1628 }; 1629 1630 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1631 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum, 1632 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text); 1633 1634 static const struct snd_kcontrol_new aif2dacl_src_mux = 1635 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1636 1637 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum, 1638 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text); 1639 1640 static const struct snd_kcontrol_new aif2dacr_src_mux = 1641 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1642 1643 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1644 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1646 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1647 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1648 1649 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1650 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1651 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1652 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1653 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1654 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1655 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1656 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1657 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1658 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1659 1660 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1661 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1662 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1663 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1664 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1665 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1666 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1667 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1668 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1669 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1670 1671 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1672 }; 1673 1674 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1675 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1676 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1677 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1678 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1679 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1680 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1681 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1682 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1683 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1684 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1685 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1686 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1687 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1688 }; 1689 1690 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1691 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1692 dac_ev, SND_SOC_DAPM_PRE_PMU), 1693 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1694 dac_ev, SND_SOC_DAPM_PRE_PMU), 1695 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1696 dac_ev, SND_SOC_DAPM_PRE_PMU), 1697 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1698 dac_ev, SND_SOC_DAPM_PRE_PMU), 1699 }; 1700 1701 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1702 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1703 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1704 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1705 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1706 }; 1707 1708 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1709 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1710 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1711 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1712 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1713 }; 1714 1715 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1716 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1717 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1718 }; 1719 1720 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1721 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1722 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1723 SND_SOC_DAPM_INPUT("Clock"), 1724 1725 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1726 SND_SOC_DAPM_PRE_PMU), 1727 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1728 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1729 1730 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1732 SND_SOC_DAPM_PRE_PMD), 1733 1734 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1735 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1736 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1737 1738 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1739 0, SND_SOC_NOPM, 9, 0), 1740 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1741 0, SND_SOC_NOPM, 8, 0), 1742 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1743 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1744 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1745 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1746 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1747 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1748 1749 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1750 0, SND_SOC_NOPM, 11, 0), 1751 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1752 0, SND_SOC_NOPM, 10, 0), 1753 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1754 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1755 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1756 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1757 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1758 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1759 1760 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1761 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1762 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1763 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1764 1765 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1766 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1767 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1768 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1769 1770 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1771 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1772 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1773 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1774 1775 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1776 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1777 1778 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1779 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1780 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1781 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1782 1783 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1784 SND_SOC_NOPM, 13, 0), 1785 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1786 SND_SOC_NOPM, 12, 0), 1787 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1788 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1789 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1790 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1791 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1792 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1793 1794 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1795 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1796 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1797 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1798 1799 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1800 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1801 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1802 1803 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1804 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1805 1806 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1807 1808 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1809 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1810 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1811 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1812 1813 /* Power is done with the muxes since the ADC power also controls the 1814 * downsampling chain, the chip will automatically manage the analogue 1815 * specific portions. 1816 */ 1817 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1818 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1819 1820 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback), 1821 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback), 1822 1823 SND_SOC_DAPM_POST("Debug log", post_ev), 1824 }; 1825 1826 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1827 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1828 }; 1829 1830 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1831 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1832 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1833 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1834 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1835 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1836 }; 1837 1838 static const struct snd_soc_dapm_route intercon[] = { 1839 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1840 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1841 1842 { "DSP1CLK", NULL, "CLK_SYS" }, 1843 { "DSP2CLK", NULL, "CLK_SYS" }, 1844 { "DSPINTCLK", NULL, "CLK_SYS" }, 1845 1846 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1847 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1848 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1849 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1850 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1851 1852 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1853 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1854 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1855 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1856 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1857 1858 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1859 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1860 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1861 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1862 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1863 1864 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1865 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1866 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1867 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1868 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1869 1870 { "AIF2ADCL", NULL, "AIF2CLK" }, 1871 { "AIF2ADCL", NULL, "DSP2CLK" }, 1872 { "AIF2ADCR", NULL, "AIF2CLK" }, 1873 { "AIF2ADCR", NULL, "DSP2CLK" }, 1874 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1875 1876 { "AIF2DACL", NULL, "AIF2CLK" }, 1877 { "AIF2DACL", NULL, "DSP2CLK" }, 1878 { "AIF2DACR", NULL, "AIF2CLK" }, 1879 { "AIF2DACR", NULL, "DSP2CLK" }, 1880 { "AIF2DACR", NULL, "DSPINTCLK" }, 1881 1882 { "DMIC1L", NULL, "DMIC1DAT" }, 1883 { "DMIC1L", NULL, "CLK_SYS" }, 1884 { "DMIC1R", NULL, "DMIC1DAT" }, 1885 { "DMIC1R", NULL, "CLK_SYS" }, 1886 { "DMIC2L", NULL, "DMIC2DAT" }, 1887 { "DMIC2L", NULL, "CLK_SYS" }, 1888 { "DMIC2R", NULL, "DMIC2DAT" }, 1889 { "DMIC2R", NULL, "CLK_SYS" }, 1890 1891 { "ADCL", NULL, "AIF1CLK" }, 1892 { "ADCL", NULL, "DSP1CLK" }, 1893 { "ADCL", NULL, "DSPINTCLK" }, 1894 1895 { "ADCR", NULL, "AIF1CLK" }, 1896 { "ADCR", NULL, "DSP1CLK" }, 1897 { "ADCR", NULL, "DSPINTCLK" }, 1898 1899 { "ADCL Mux", "ADC", "ADCL" }, 1900 { "ADCL Mux", "DMIC", "DMIC1L" }, 1901 { "ADCR Mux", "ADC", "ADCR" }, 1902 { "ADCR Mux", "DMIC", "DMIC1R" }, 1903 1904 { "DAC1L", NULL, "AIF1CLK" }, 1905 { "DAC1L", NULL, "DSP1CLK" }, 1906 { "DAC1L", NULL, "DSPINTCLK" }, 1907 1908 { "DAC1R", NULL, "AIF1CLK" }, 1909 { "DAC1R", NULL, "DSP1CLK" }, 1910 { "DAC1R", NULL, "DSPINTCLK" }, 1911 1912 { "DAC2L", NULL, "AIF2CLK" }, 1913 { "DAC2L", NULL, "DSP2CLK" }, 1914 { "DAC2L", NULL, "DSPINTCLK" }, 1915 1916 { "DAC2R", NULL, "AIF2DACR" }, 1917 { "DAC2R", NULL, "AIF2CLK" }, 1918 { "DAC2R", NULL, "DSP2CLK" }, 1919 { "DAC2R", NULL, "DSPINTCLK" }, 1920 1921 { "TOCLK", NULL, "CLK_SYS" }, 1922 1923 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1924 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1925 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1926 1927 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1928 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1929 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1930 1931 /* AIF1 outputs */ 1932 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1933 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1934 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1935 1936 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1937 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1938 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1939 1940 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1941 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1942 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1943 1944 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1945 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1946 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1947 1948 /* Pin level routing for AIF3 */ 1949 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1950 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1951 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1952 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1953 1954 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" }, 1955 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1956 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" }, 1957 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1958 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1959 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1960 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1961 1962 /* DAC1 inputs */ 1963 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1964 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1965 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1966 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1967 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1968 1969 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1970 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1971 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1972 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1973 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1974 1975 /* DAC2/AIF2 outputs */ 1976 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1977 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1978 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1979 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1980 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1981 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1982 1983 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1984 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1985 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1986 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1987 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1988 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1989 1990 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1991 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1992 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1993 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1994 1995 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1996 1997 /* AIF3 output */ 1998 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" }, 1999 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" }, 2000 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" }, 2001 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" }, 2002 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 2003 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 2004 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" }, 2005 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" }, 2006 2007 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" }, 2008 2009 /* Loopback */ 2010 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" }, 2011 { "AIF1 Loopback", "None", "AIF1DACDAT" }, 2012 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" }, 2013 { "AIF2 Loopback", "None", "AIF2DACDAT" }, 2014 2015 /* Sidetone */ 2016 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 2017 { "Left Sidetone", "DMIC2", "DMIC2L" }, 2018 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 2019 { "Right Sidetone", "DMIC2", "DMIC2R" }, 2020 2021 /* Output stages */ 2022 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 2023 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 2024 2025 { "SPKL", "DAC1 Switch", "DAC1L" }, 2026 { "SPKL", "DAC2 Switch", "DAC2L" }, 2027 2028 { "SPKR", "DAC1 Switch", "DAC1R" }, 2029 { "SPKR", "DAC2 Switch", "DAC2R" }, 2030 2031 { "Left Headphone Mux", "DAC", "DAC1L" }, 2032 { "Right Headphone Mux", "DAC", "DAC1R" }, 2033 }; 2034 2035 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 2036 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 2037 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 2038 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 2039 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 2040 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 2041 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 2042 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 2043 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 2044 }; 2045 2046 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 2047 { "DAC1L", NULL, "DAC1L Mixer" }, 2048 { "DAC1R", NULL, "DAC1R Mixer" }, 2049 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 2050 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 2051 }; 2052 2053 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 2054 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 2055 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 2056 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 2057 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 2058 { "MICBIAS1", NULL, "CLK_SYS" }, 2059 { "MICBIAS1", NULL, "MICBIAS Supply" }, 2060 { "MICBIAS2", NULL, "CLK_SYS" }, 2061 { "MICBIAS2", NULL, "MICBIAS Supply" }, 2062 }; 2063 2064 static const struct snd_soc_dapm_route wm8994_intercon[] = { 2065 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2066 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2067 { "MICBIAS1", NULL, "VMID" }, 2068 { "MICBIAS2", NULL, "VMID" }, 2069 }; 2070 2071 static const struct snd_soc_dapm_route wm8958_intercon[] = { 2072 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 2073 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 2074 2075 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 2076 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 2077 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 2078 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 2079 2080 { "AIF3DACDAT", NULL, "AIF3" }, 2081 { "AIF3ADCDAT", NULL, "AIF3" }, 2082 2083 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2084 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2085 2086 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2087 }; 2088 2089 /* The size in bits of the FLL divide multiplied by 10 2090 * to allow rounding later */ 2091 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2092 2093 struct fll_div { 2094 u16 outdiv; 2095 u16 n; 2096 u16 k; 2097 u16 lambda; 2098 u16 clk_ref_div; 2099 u16 fll_fratio; 2100 }; 2101 2102 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll, 2103 int freq_in, int freq_out) 2104 { 2105 u64 Kpart; 2106 unsigned int K, Ndiv, Nmod, gcd_fll; 2107 2108 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2109 2110 /* Scale the input frequency down to <= 13.5MHz */ 2111 fll->clk_ref_div = 0; 2112 while (freq_in > 13500000) { 2113 fll->clk_ref_div++; 2114 freq_in /= 2; 2115 2116 if (fll->clk_ref_div > 3) 2117 return -EINVAL; 2118 } 2119 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2120 2121 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2122 fll->outdiv = 3; 2123 while (freq_out * (fll->outdiv + 1) < 90000000) { 2124 fll->outdiv++; 2125 if (fll->outdiv > 63) 2126 return -EINVAL; 2127 } 2128 freq_out *= fll->outdiv + 1; 2129 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2130 2131 if (freq_in > 1000000) { 2132 fll->fll_fratio = 0; 2133 } else if (freq_in > 256000) { 2134 fll->fll_fratio = 1; 2135 freq_in *= 2; 2136 } else if (freq_in > 128000) { 2137 fll->fll_fratio = 2; 2138 freq_in *= 4; 2139 } else if (freq_in > 64000) { 2140 fll->fll_fratio = 3; 2141 freq_in *= 8; 2142 } else { 2143 fll->fll_fratio = 4; 2144 freq_in *= 16; 2145 } 2146 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2147 2148 /* Now, calculate N.K */ 2149 Ndiv = freq_out / freq_in; 2150 2151 fll->n = Ndiv; 2152 Nmod = freq_out % freq_in; 2153 pr_debug("Nmod=%d\n", Nmod); 2154 2155 switch (control->type) { 2156 case WM8994: 2157 /* Calculate fractional part - scale up so we can round. */ 2158 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2159 2160 do_div(Kpart, freq_in); 2161 2162 K = Kpart & 0xFFFFFFFF; 2163 2164 if ((K % 10) >= 5) 2165 K += 5; 2166 2167 /* Move down to proper range now rounding is done */ 2168 fll->k = K / 10; 2169 fll->lambda = 0; 2170 2171 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2172 break; 2173 2174 default: 2175 gcd_fll = gcd(freq_out, freq_in); 2176 2177 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; 2178 fll->lambda = freq_in / gcd_fll; 2179 2180 } 2181 2182 return 0; 2183 } 2184 2185 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, 2186 unsigned int freq_in, unsigned int freq_out) 2187 { 2188 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2189 struct wm8994 *control = wm8994->wm8994; 2190 int reg_offset, ret; 2191 struct fll_div fll; 2192 u16 reg, clk1, aif_reg, aif_src; 2193 unsigned long timeout; 2194 bool was_enabled; 2195 struct clk *mclk; 2196 2197 switch (id) { 2198 case WM8994_FLL1: 2199 reg_offset = 0; 2200 id = 0; 2201 aif_src = 0x10; 2202 break; 2203 case WM8994_FLL2: 2204 reg_offset = 0x20; 2205 id = 1; 2206 aif_src = 0x18; 2207 break; 2208 default: 2209 return -EINVAL; 2210 } 2211 2212 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset); 2213 was_enabled = reg & WM8994_FLL1_ENA; 2214 2215 switch (src) { 2216 case 0: 2217 /* Allow no source specification when stopping */ 2218 if (freq_out) 2219 return -EINVAL; 2220 src = wm8994->fll[id].src; 2221 break; 2222 case WM8994_FLL_SRC_MCLK1: 2223 case WM8994_FLL_SRC_MCLK2: 2224 case WM8994_FLL_SRC_LRCLK: 2225 case WM8994_FLL_SRC_BCLK: 2226 break; 2227 case WM8994_FLL_SRC_INTERNAL: 2228 freq_in = 12000000; 2229 freq_out = 12000000; 2230 break; 2231 default: 2232 return -EINVAL; 2233 } 2234 2235 /* Are we changing anything? */ 2236 if (wm8994->fll[id].src == src && 2237 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2238 return 0; 2239 2240 /* If we're stopping the FLL redo the old config - no 2241 * registers will actually be written but we avoid GCC flow 2242 * analysis bugs spewing warnings. 2243 */ 2244 if (freq_out) 2245 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out); 2246 else 2247 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in, 2248 wm8994->fll[id].out); 2249 if (ret < 0) 2250 return ret; 2251 2252 /* Make sure that we're not providing SYSCLK right now */ 2253 clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1); 2254 if (clk1 & WM8994_SYSCLK_SRC) 2255 aif_reg = WM8994_AIF2_CLOCKING_1; 2256 else 2257 aif_reg = WM8994_AIF1_CLOCKING_1; 2258 reg = snd_soc_component_read32(component, aif_reg); 2259 2260 if ((reg & WM8994_AIF1CLK_ENA) && 2261 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2262 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n", 2263 id + 1); 2264 return -EBUSY; 2265 } 2266 2267 /* We always need to disable the FLL while reconfiguring */ 2268 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2269 WM8994_FLL1_ENA, 0); 2270 2271 /* Disable MCLK if needed before we possibly change to new clock parent */ 2272 if (was_enabled) { 2273 reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_5 2274 + reg_offset); 2275 reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK) 2276 >> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1; 2277 2278 switch (reg) { 2279 case WM8994_FLL_SRC_MCLK1: 2280 mclk = wm8994->mclk[WM8994_MCLK1].clk; 2281 break; 2282 case WM8994_FLL_SRC_MCLK2: 2283 mclk = wm8994->mclk[WM8994_MCLK2].clk; 2284 break; 2285 default: 2286 mclk = NULL; 2287 } 2288 2289 clk_disable_unprepare(mclk); 2290 } 2291 2292 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2293 freq_in == freq_out && freq_out) { 2294 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1); 2295 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2296 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2297 goto out; 2298 } 2299 2300 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2301 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2302 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset, 2303 WM8994_FLL1_OUTDIV_MASK | 2304 WM8994_FLL1_FRATIO_MASK, reg); 2305 2306 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset, 2307 WM8994_FLL1_K_MASK, fll.k); 2308 2309 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset, 2310 WM8994_FLL1_N_MASK, 2311 fll.n << WM8994_FLL1_N_SHIFT); 2312 2313 if (fll.lambda) { 2314 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset, 2315 WM8958_FLL1_LAMBDA_MASK, 2316 fll.lambda); 2317 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2318 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA); 2319 } else { 2320 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2321 WM8958_FLL1_EFS_ENA, 0); 2322 } 2323 2324 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2325 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2326 WM8994_FLL1_REFCLK_DIV_MASK | 2327 WM8994_FLL1_REFCLK_SRC_MASK, 2328 ((src == WM8994_FLL_SRC_INTERNAL) 2329 << WM8994_FLL1_FRC_NCO_SHIFT) | 2330 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2331 (src - 1)); 2332 2333 /* Clear any pending completion from a previous failure */ 2334 try_wait_for_completion(&wm8994->fll_locked[id]); 2335 2336 switch (src) { 2337 case WM8994_FLL_SRC_MCLK1: 2338 mclk = wm8994->mclk[WM8994_MCLK1].clk; 2339 break; 2340 case WM8994_FLL_SRC_MCLK2: 2341 mclk = wm8994->mclk[WM8994_MCLK2].clk; 2342 break; 2343 default: 2344 mclk = NULL; 2345 } 2346 2347 /* Enable (with fractional mode if required) */ 2348 if (freq_out) { 2349 ret = clk_prepare_enable(mclk); 2350 if (ret < 0) { 2351 dev_err(component->dev, "Failed to enable MCLK for FLL%d\n", 2352 id + 1); 2353 return ret; 2354 } 2355 2356 /* Enable VMID if we need it */ 2357 if (!was_enabled) { 2358 2359 active_reference(component); 2360 2361 switch (control->type) { 2362 case WM8994: 2363 vmid_reference(component); 2364 break; 2365 case WM8958: 2366 if (control->revision < 1) 2367 vmid_reference(component); 2368 break; 2369 default: 2370 break; 2371 } 2372 } 2373 2374 reg = WM8994_FLL1_ENA; 2375 2376 if (fll.k) 2377 reg |= WM8994_FLL1_FRAC; 2378 if (src == WM8994_FLL_SRC_INTERNAL) 2379 reg |= WM8994_FLL1_OSC_ENA; 2380 2381 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2382 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2383 WM8994_FLL1_FRAC, reg); 2384 2385 if (wm8994->fll_locked_irq) { 2386 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2387 msecs_to_jiffies(10)); 2388 if (timeout == 0) 2389 dev_warn(component->dev, 2390 "Timed out waiting for FLL lock\n"); 2391 } else { 2392 msleep(5); 2393 } 2394 } else { 2395 if (was_enabled) { 2396 switch (control->type) { 2397 case WM8994: 2398 vmid_dereference(component); 2399 break; 2400 case WM8958: 2401 if (control->revision < 1) 2402 vmid_dereference(component); 2403 break; 2404 default: 2405 break; 2406 } 2407 2408 active_dereference(component); 2409 } 2410 } 2411 2412 out: 2413 wm8994->fll[id].in = freq_in; 2414 wm8994->fll[id].out = freq_out; 2415 wm8994->fll[id].src = src; 2416 2417 configure_clock(component); 2418 2419 /* 2420 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2421 * for detection. 2422 */ 2423 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2424 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2425 2426 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE) 2427 & WM8994_AIF1CLK_RATE_MASK; 2428 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE) 2429 & WM8994_AIF1CLK_RATE_MASK; 2430 2431 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2432 WM8994_AIF1CLK_RATE_MASK, 0x1); 2433 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2434 WM8994_AIF2CLK_RATE_MASK, 0x1); 2435 } else if (wm8994->aifdiv[0]) { 2436 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2437 WM8994_AIF1CLK_RATE_MASK, 2438 wm8994->aifdiv[0]); 2439 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2440 WM8994_AIF2CLK_RATE_MASK, 2441 wm8994->aifdiv[1]); 2442 2443 wm8994->aifdiv[0] = 0; 2444 wm8994->aifdiv[1] = 0; 2445 } 2446 2447 return 0; 2448 } 2449 2450 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2451 { 2452 struct completion *completion = data; 2453 2454 complete(completion); 2455 2456 return IRQ_HANDLED; 2457 } 2458 2459 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2460 2461 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2462 unsigned int freq_in, unsigned int freq_out) 2463 { 2464 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out); 2465 } 2466 2467 static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id, 2468 unsigned int *freq) 2469 { 2470 int ret; 2471 2472 if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id]) 2473 return 0; 2474 2475 ret = clk_set_rate(wm8994->mclk[id].clk, *freq); 2476 if (ret < 0) 2477 return ret; 2478 2479 *freq = clk_get_rate(wm8994->mclk[id].clk); 2480 2481 return 0; 2482 } 2483 2484 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2485 int clk_id, unsigned int freq, int dir) 2486 { 2487 struct snd_soc_component *component = dai->component; 2488 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2489 int ret, i; 2490 2491 switch (dai->id) { 2492 case 1: 2493 case 2: 2494 break; 2495 2496 default: 2497 /* AIF3 shares clocking with AIF1/2 */ 2498 return -EINVAL; 2499 } 2500 2501 switch (clk_id) { 2502 case WM8994_SYSCLK_MCLK1: 2503 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2504 2505 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq); 2506 if (ret < 0) 2507 return ret; 2508 2509 wm8994->mclk_rate[0] = freq; 2510 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2511 dai->id, freq); 2512 break; 2513 2514 case WM8994_SYSCLK_MCLK2: 2515 /* TODO: Set GPIO AF */ 2516 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2517 2518 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq); 2519 if (ret < 0) 2520 return ret; 2521 2522 wm8994->mclk_rate[1] = freq; 2523 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2524 dai->id, freq); 2525 break; 2526 2527 case WM8994_SYSCLK_FLL1: 2528 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2529 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2530 break; 2531 2532 case WM8994_SYSCLK_FLL2: 2533 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2534 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2535 break; 2536 2537 case WM8994_SYSCLK_OPCLK: 2538 /* Special case - a division (times 10) is given and 2539 * no effect on main clocking. 2540 */ 2541 if (freq) { 2542 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2543 if (opclk_divs[i] == freq) 2544 break; 2545 if (i == ARRAY_SIZE(opclk_divs)) 2546 return -EINVAL; 2547 snd_soc_component_update_bits(component, WM8994_CLOCKING_2, 2548 WM8994_OPCLK_DIV_MASK, i); 2549 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2550 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2551 } else { 2552 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2553 WM8994_OPCLK_ENA, 0); 2554 } 2555 break; 2556 2557 default: 2558 return -EINVAL; 2559 } 2560 2561 configure_clock(component); 2562 2563 /* 2564 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2565 * for detection. 2566 */ 2567 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2568 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2569 2570 wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE) 2571 & WM8994_AIF1CLK_RATE_MASK; 2572 wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE) 2573 & WM8994_AIF1CLK_RATE_MASK; 2574 2575 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2576 WM8994_AIF1CLK_RATE_MASK, 0x1); 2577 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2578 WM8994_AIF2CLK_RATE_MASK, 0x1); 2579 } else if (wm8994->aifdiv[0]) { 2580 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2581 WM8994_AIF1CLK_RATE_MASK, 2582 wm8994->aifdiv[0]); 2583 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2584 WM8994_AIF2CLK_RATE_MASK, 2585 wm8994->aifdiv[1]); 2586 2587 wm8994->aifdiv[0] = 0; 2588 wm8994->aifdiv[1] = 0; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static int wm8994_set_bias_level(struct snd_soc_component *component, 2595 enum snd_soc_bias_level level) 2596 { 2597 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2598 struct wm8994 *control = wm8994->wm8994; 2599 2600 wm_hubs_set_bias_level(component, level); 2601 2602 switch (level) { 2603 case SND_SOC_BIAS_ON: 2604 break; 2605 2606 case SND_SOC_BIAS_PREPARE: 2607 /* MICBIAS into regulating mode */ 2608 switch (control->type) { 2609 case WM8958: 2610 case WM1811: 2611 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2612 WM8958_MICB1_MODE, 0); 2613 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2614 WM8958_MICB2_MODE, 0); 2615 break; 2616 default: 2617 break; 2618 } 2619 2620 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 2621 active_reference(component); 2622 break; 2623 2624 case SND_SOC_BIAS_STANDBY: 2625 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2626 switch (control->type) { 2627 case WM8958: 2628 if (control->revision == 0) { 2629 /* Optimise performance for rev A */ 2630 snd_soc_component_update_bits(component, 2631 WM8958_CHARGE_PUMP_2, 2632 WM8958_CP_DISCH, 2633 WM8958_CP_DISCH); 2634 } 2635 break; 2636 2637 default: 2638 break; 2639 } 2640 2641 /* Discharge LINEOUT1 & 2 */ 2642 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 2643 WM8994_LINEOUT1_DISCH | 2644 WM8994_LINEOUT2_DISCH, 2645 WM8994_LINEOUT1_DISCH | 2646 WM8994_LINEOUT2_DISCH); 2647 } 2648 2649 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) 2650 active_dereference(component); 2651 2652 /* MICBIAS into bypass mode on newer devices */ 2653 switch (control->type) { 2654 case WM8958: 2655 case WM1811: 2656 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2657 WM8958_MICB1_MODE, 2658 WM8958_MICB1_MODE); 2659 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2660 WM8958_MICB2_MODE, 2661 WM8958_MICB2_MODE); 2662 break; 2663 default: 2664 break; 2665 } 2666 break; 2667 2668 case SND_SOC_BIAS_OFF: 2669 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 2670 wm8994->cur_fw = NULL; 2671 break; 2672 } 2673 2674 return 0; 2675 } 2676 2677 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode) 2678 { 2679 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2680 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2681 2682 switch (mode) { 2683 case WM8994_VMID_NORMAL: 2684 snd_soc_dapm_mutex_lock(dapm); 2685 2686 if (wm8994->hubs.lineout1_se) { 2687 snd_soc_dapm_disable_pin_unlocked(dapm, 2688 "LINEOUT1N Driver"); 2689 snd_soc_dapm_disable_pin_unlocked(dapm, 2690 "LINEOUT1P Driver"); 2691 } 2692 if (wm8994->hubs.lineout2_se) { 2693 snd_soc_dapm_disable_pin_unlocked(dapm, 2694 "LINEOUT2N Driver"); 2695 snd_soc_dapm_disable_pin_unlocked(dapm, 2696 "LINEOUT2P Driver"); 2697 } 2698 2699 /* Do the sync with the old mode to allow it to clean up */ 2700 snd_soc_dapm_sync_unlocked(dapm); 2701 wm8994->vmid_mode = mode; 2702 2703 snd_soc_dapm_mutex_unlock(dapm); 2704 break; 2705 2706 case WM8994_VMID_FORCE: 2707 snd_soc_dapm_mutex_lock(dapm); 2708 2709 if (wm8994->hubs.lineout1_se) { 2710 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2711 "LINEOUT1N Driver"); 2712 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2713 "LINEOUT1P Driver"); 2714 } 2715 if (wm8994->hubs.lineout2_se) { 2716 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2717 "LINEOUT2N Driver"); 2718 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2719 "LINEOUT2P Driver"); 2720 } 2721 2722 wm8994->vmid_mode = mode; 2723 snd_soc_dapm_sync_unlocked(dapm); 2724 2725 snd_soc_dapm_mutex_unlock(dapm); 2726 break; 2727 2728 default: 2729 return -EINVAL; 2730 } 2731 2732 return 0; 2733 } 2734 2735 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2736 { 2737 struct snd_soc_component *component = dai->component; 2738 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2739 struct wm8994 *control = wm8994->wm8994; 2740 int ms_reg; 2741 int aif1_reg; 2742 int dac_reg; 2743 int adc_reg; 2744 int ms = 0; 2745 int aif1 = 0; 2746 int lrclk = 0; 2747 2748 switch (dai->id) { 2749 case 1: 2750 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2751 aif1_reg = WM8994_AIF1_CONTROL_1; 2752 dac_reg = WM8994_AIF1DAC_LRCLK; 2753 adc_reg = WM8994_AIF1ADC_LRCLK; 2754 break; 2755 case 2: 2756 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2757 aif1_reg = WM8994_AIF2_CONTROL_1; 2758 dac_reg = WM8994_AIF1DAC_LRCLK; 2759 adc_reg = WM8994_AIF1ADC_LRCLK; 2760 break; 2761 default: 2762 return -EINVAL; 2763 } 2764 2765 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2766 case SND_SOC_DAIFMT_CBS_CFS: 2767 break; 2768 case SND_SOC_DAIFMT_CBM_CFM: 2769 ms = WM8994_AIF1_MSTR; 2770 break; 2771 default: 2772 return -EINVAL; 2773 } 2774 2775 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2776 case SND_SOC_DAIFMT_DSP_B: 2777 aif1 |= WM8994_AIF1_LRCLK_INV; 2778 lrclk |= WM8958_AIF1_LRCLK_INV; 2779 /* fall through */ 2780 case SND_SOC_DAIFMT_DSP_A: 2781 aif1 |= 0x18; 2782 break; 2783 case SND_SOC_DAIFMT_I2S: 2784 aif1 |= 0x10; 2785 break; 2786 case SND_SOC_DAIFMT_RIGHT_J: 2787 break; 2788 case SND_SOC_DAIFMT_LEFT_J: 2789 aif1 |= 0x8; 2790 break; 2791 default: 2792 return -EINVAL; 2793 } 2794 2795 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2796 case SND_SOC_DAIFMT_DSP_A: 2797 case SND_SOC_DAIFMT_DSP_B: 2798 /* frame inversion not valid for DSP modes */ 2799 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2800 case SND_SOC_DAIFMT_NB_NF: 2801 break; 2802 case SND_SOC_DAIFMT_IB_NF: 2803 aif1 |= WM8994_AIF1_BCLK_INV; 2804 break; 2805 default: 2806 return -EINVAL; 2807 } 2808 break; 2809 2810 case SND_SOC_DAIFMT_I2S: 2811 case SND_SOC_DAIFMT_RIGHT_J: 2812 case SND_SOC_DAIFMT_LEFT_J: 2813 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2814 case SND_SOC_DAIFMT_NB_NF: 2815 break; 2816 case SND_SOC_DAIFMT_IB_IF: 2817 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2818 lrclk |= WM8958_AIF1_LRCLK_INV; 2819 break; 2820 case SND_SOC_DAIFMT_IB_NF: 2821 aif1 |= WM8994_AIF1_BCLK_INV; 2822 break; 2823 case SND_SOC_DAIFMT_NB_IF: 2824 aif1 |= WM8994_AIF1_LRCLK_INV; 2825 lrclk |= WM8958_AIF1_LRCLK_INV; 2826 break; 2827 default: 2828 return -EINVAL; 2829 } 2830 break; 2831 default: 2832 return -EINVAL; 2833 } 2834 2835 /* The AIF2 format configuration needs to be mirrored to AIF3 2836 * on WM8958 if it's in use so just do it all the time. */ 2837 switch (control->type) { 2838 case WM1811: 2839 case WM8958: 2840 if (dai->id == 2) 2841 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1, 2842 WM8994_AIF1_LRCLK_INV | 2843 WM8958_AIF3_FMT_MASK, aif1); 2844 break; 2845 2846 default: 2847 break; 2848 } 2849 2850 snd_soc_component_update_bits(component, aif1_reg, 2851 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2852 WM8994_AIF1_FMT_MASK, 2853 aif1); 2854 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR, 2855 ms); 2856 snd_soc_component_update_bits(component, dac_reg, 2857 WM8958_AIF1_LRCLK_INV, lrclk); 2858 snd_soc_component_update_bits(component, adc_reg, 2859 WM8958_AIF1_LRCLK_INV, lrclk); 2860 2861 return 0; 2862 } 2863 2864 static struct { 2865 int val, rate; 2866 } srs[] = { 2867 { 0, 8000 }, 2868 { 1, 11025 }, 2869 { 2, 12000 }, 2870 { 3, 16000 }, 2871 { 4, 22050 }, 2872 { 5, 24000 }, 2873 { 6, 32000 }, 2874 { 7, 44100 }, 2875 { 8, 48000 }, 2876 { 9, 88200 }, 2877 { 10, 96000 }, 2878 }; 2879 2880 static int fs_ratios[] = { 2881 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 2882 }; 2883 2884 static int bclk_divs[] = { 2885 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2886 640, 880, 960, 1280, 1760, 1920 2887 }; 2888 2889 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2890 struct snd_pcm_hw_params *params, 2891 struct snd_soc_dai *dai) 2892 { 2893 struct snd_soc_component *component = dai->component; 2894 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2895 struct wm8994 *control = wm8994->wm8994; 2896 struct wm8994_pdata *pdata = &control->pdata; 2897 int aif1_reg; 2898 int aif2_reg; 2899 int bclk_reg; 2900 int lrclk_reg; 2901 int rate_reg; 2902 int aif1 = 0; 2903 int aif2 = 0; 2904 int bclk = 0; 2905 int lrclk = 0; 2906 int rate_val = 0; 2907 int id = dai->id - 1; 2908 2909 int i, cur_val, best_val, bclk_rate, best; 2910 2911 switch (dai->id) { 2912 case 1: 2913 aif1_reg = WM8994_AIF1_CONTROL_1; 2914 aif2_reg = WM8994_AIF1_CONTROL_2; 2915 bclk_reg = WM8994_AIF1_BCLK; 2916 rate_reg = WM8994_AIF1_RATE; 2917 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2918 wm8994->lrclk_shared[0]) { 2919 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2920 } else { 2921 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2922 dev_dbg(component->dev, "AIF1 using split LRCLK\n"); 2923 } 2924 break; 2925 case 2: 2926 aif1_reg = WM8994_AIF2_CONTROL_1; 2927 aif2_reg = WM8994_AIF2_CONTROL_2; 2928 bclk_reg = WM8994_AIF2_BCLK; 2929 rate_reg = WM8994_AIF2_RATE; 2930 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2931 wm8994->lrclk_shared[1]) { 2932 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2933 } else { 2934 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2935 dev_dbg(component->dev, "AIF2 using split LRCLK\n"); 2936 } 2937 break; 2938 default: 2939 return -EINVAL; 2940 } 2941 2942 bclk_rate = params_rate(params); 2943 switch (params_width(params)) { 2944 case 16: 2945 bclk_rate *= 16; 2946 break; 2947 case 20: 2948 bclk_rate *= 20; 2949 aif1 |= 0x20; 2950 break; 2951 case 24: 2952 bclk_rate *= 24; 2953 aif1 |= 0x40; 2954 break; 2955 case 32: 2956 bclk_rate *= 32; 2957 aif1 |= 0x60; 2958 break; 2959 default: 2960 return -EINVAL; 2961 } 2962 2963 wm8994->channels[id] = params_channels(params); 2964 if (pdata->max_channels_clocked[id] && 2965 wm8994->channels[id] > pdata->max_channels_clocked[id]) { 2966 dev_dbg(dai->dev, "Constraining channels to %d from %d\n", 2967 pdata->max_channels_clocked[id], wm8994->channels[id]); 2968 wm8994->channels[id] = pdata->max_channels_clocked[id]; 2969 } 2970 2971 switch (wm8994->channels[id]) { 2972 case 1: 2973 case 2: 2974 bclk_rate *= 2; 2975 break; 2976 default: 2977 bclk_rate *= 4; 2978 break; 2979 } 2980 2981 /* Try to find an appropriate sample rate; look for an exact match. */ 2982 for (i = 0; i < ARRAY_SIZE(srs); i++) 2983 if (srs[i].rate == params_rate(params)) 2984 break; 2985 if (i == ARRAY_SIZE(srs)) 2986 return -EINVAL; 2987 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2988 2989 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2990 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2991 dai->id, wm8994->aifclk[id], bclk_rate); 2992 2993 if (wm8994->channels[id] == 1 && 2994 (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18) 2995 aif2 |= WM8994_AIF1_MONO; 2996 2997 if (wm8994->aifclk[id] == 0) { 2998 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2999 return -EINVAL; 3000 } 3001 3002 /* AIFCLK/fs ratio; look for a close match in either direction */ 3003 best = 0; 3004 best_val = abs((fs_ratios[0] * params_rate(params)) 3005 - wm8994->aifclk[id]); 3006 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 3007 cur_val = abs((fs_ratios[i] * params_rate(params)) 3008 - wm8994->aifclk[id]); 3009 if (cur_val >= best_val) 3010 continue; 3011 best = i; 3012 best_val = cur_val; 3013 } 3014 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 3015 dai->id, fs_ratios[best]); 3016 rate_val |= best; 3017 3018 /* We may not get quite the right frequency if using 3019 * approximate clocks so look for the closest match that is 3020 * higher than the target (we need to ensure that there enough 3021 * BCLKs to clock out the samples). 3022 */ 3023 best = 0; 3024 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 3025 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 3026 if (cur_val < 0) /* BCLK table is sorted */ 3027 break; 3028 best = i; 3029 } 3030 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 3031 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 3032 bclk_divs[best], bclk_rate); 3033 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 3034 3035 lrclk = bclk_rate / params_rate(params); 3036 if (!lrclk) { 3037 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 3038 bclk_rate); 3039 return -EINVAL; 3040 } 3041 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 3042 lrclk, bclk_rate / lrclk); 3043 3044 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 3045 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2); 3046 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 3047 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 3048 lrclk); 3049 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK | 3050 WM8994_AIF1CLK_RATE_MASK, rate_val); 3051 3052 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3053 switch (dai->id) { 3054 case 1: 3055 wm8994->dac_rates[0] = params_rate(params); 3056 wm8994_set_retune_mobile(component, 0); 3057 wm8994_set_retune_mobile(component, 1); 3058 break; 3059 case 2: 3060 wm8994->dac_rates[1] = params_rate(params); 3061 wm8994_set_retune_mobile(component, 2); 3062 break; 3063 } 3064 } 3065 3066 return 0; 3067 } 3068 3069 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 3070 struct snd_pcm_hw_params *params, 3071 struct snd_soc_dai *dai) 3072 { 3073 struct snd_soc_component *component = dai->component; 3074 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3075 struct wm8994 *control = wm8994->wm8994; 3076 int aif1_reg; 3077 int aif1 = 0; 3078 3079 switch (dai->id) { 3080 case 3: 3081 switch (control->type) { 3082 case WM1811: 3083 case WM8958: 3084 aif1_reg = WM8958_AIF3_CONTROL_1; 3085 break; 3086 default: 3087 return 0; 3088 } 3089 break; 3090 default: 3091 return 0; 3092 } 3093 3094 switch (params_width(params)) { 3095 case 16: 3096 break; 3097 case 20: 3098 aif1 |= 0x20; 3099 break; 3100 case 24: 3101 aif1 |= 0x40; 3102 break; 3103 case 32: 3104 aif1 |= 0x60; 3105 break; 3106 default: 3107 return -EINVAL; 3108 } 3109 3110 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 3111 } 3112 3113 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 3114 { 3115 struct snd_soc_component *component = codec_dai->component; 3116 int mute_reg; 3117 int reg; 3118 3119 switch (codec_dai->id) { 3120 case 1: 3121 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 3122 break; 3123 case 2: 3124 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 3125 break; 3126 default: 3127 return -EINVAL; 3128 } 3129 3130 if (mute) 3131 reg = WM8994_AIF1DAC1_MUTE; 3132 else 3133 reg = 0; 3134 3135 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 3136 3137 return 0; 3138 } 3139 3140 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3141 { 3142 struct snd_soc_component *component = codec_dai->component; 3143 int reg, val, mask; 3144 3145 switch (codec_dai->id) { 3146 case 1: 3147 reg = WM8994_AIF1_MASTER_SLAVE; 3148 mask = WM8994_AIF1_TRI; 3149 break; 3150 case 2: 3151 reg = WM8994_AIF2_MASTER_SLAVE; 3152 mask = WM8994_AIF2_TRI; 3153 break; 3154 default: 3155 return -EINVAL; 3156 } 3157 3158 if (tristate) 3159 val = mask; 3160 else 3161 val = 0; 3162 3163 return snd_soc_component_update_bits(component, reg, mask, val); 3164 } 3165 3166 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 3167 { 3168 struct snd_soc_component *component = dai->component; 3169 3170 /* Disable the pulls on the AIF if we're using it to save power. */ 3171 snd_soc_component_update_bits(component, WM8994_GPIO_3, 3172 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3173 snd_soc_component_update_bits(component, WM8994_GPIO_4, 3174 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3175 snd_soc_component_update_bits(component, WM8994_GPIO_5, 3176 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3177 3178 return 0; 3179 } 3180 3181 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3182 3183 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3184 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3185 3186 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3187 .set_sysclk = wm8994_set_dai_sysclk, 3188 .set_fmt = wm8994_set_dai_fmt, 3189 .hw_params = wm8994_hw_params, 3190 .digital_mute = wm8994_aif_mute, 3191 .set_pll = wm8994_set_fll, 3192 .set_tristate = wm8994_set_tristate, 3193 }; 3194 3195 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3196 .set_sysclk = wm8994_set_dai_sysclk, 3197 .set_fmt = wm8994_set_dai_fmt, 3198 .hw_params = wm8994_hw_params, 3199 .digital_mute = wm8994_aif_mute, 3200 .set_pll = wm8994_set_fll, 3201 .set_tristate = wm8994_set_tristate, 3202 }; 3203 3204 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3205 .hw_params = wm8994_aif3_hw_params, 3206 }; 3207 3208 static struct snd_soc_dai_driver wm8994_dai[] = { 3209 { 3210 .name = "wm8994-aif1", 3211 .id = 1, 3212 .playback = { 3213 .stream_name = "AIF1 Playback", 3214 .channels_min = 1, 3215 .channels_max = 2, 3216 .rates = WM8994_RATES, 3217 .formats = WM8994_FORMATS, 3218 .sig_bits = 24, 3219 }, 3220 .capture = { 3221 .stream_name = "AIF1 Capture", 3222 .channels_min = 1, 3223 .channels_max = 2, 3224 .rates = WM8994_RATES, 3225 .formats = WM8994_FORMATS, 3226 .sig_bits = 24, 3227 }, 3228 .ops = &wm8994_aif1_dai_ops, 3229 }, 3230 { 3231 .name = "wm8994-aif2", 3232 .id = 2, 3233 .playback = { 3234 .stream_name = "AIF2 Playback", 3235 .channels_min = 1, 3236 .channels_max = 2, 3237 .rates = WM8994_RATES, 3238 .formats = WM8994_FORMATS, 3239 .sig_bits = 24, 3240 }, 3241 .capture = { 3242 .stream_name = "AIF2 Capture", 3243 .channels_min = 1, 3244 .channels_max = 2, 3245 .rates = WM8994_RATES, 3246 .formats = WM8994_FORMATS, 3247 .sig_bits = 24, 3248 }, 3249 .probe = wm8994_aif2_probe, 3250 .ops = &wm8994_aif2_dai_ops, 3251 }, 3252 { 3253 .name = "wm8994-aif3", 3254 .id = 3, 3255 .playback = { 3256 .stream_name = "AIF3 Playback", 3257 .channels_min = 1, 3258 .channels_max = 2, 3259 .rates = WM8994_RATES, 3260 .formats = WM8994_FORMATS, 3261 .sig_bits = 24, 3262 }, 3263 .capture = { 3264 .stream_name = "AIF3 Capture", 3265 .channels_min = 1, 3266 .channels_max = 2, 3267 .rates = WM8994_RATES, 3268 .formats = WM8994_FORMATS, 3269 .sig_bits = 24, 3270 }, 3271 .ops = &wm8994_aif3_dai_ops, 3272 } 3273 }; 3274 3275 #ifdef CONFIG_PM 3276 static int wm8994_component_suspend(struct snd_soc_component *component) 3277 { 3278 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3279 int i, ret; 3280 3281 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3282 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3283 sizeof(struct wm8994_fll_config)); 3284 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0); 3285 if (ret < 0) 3286 dev_warn(component->dev, "Failed to stop FLL%d: %d\n", 3287 i + 1, ret); 3288 } 3289 3290 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 3291 3292 return 0; 3293 } 3294 3295 static int wm8994_component_resume(struct snd_soc_component *component) 3296 { 3297 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3298 int i, ret; 3299 3300 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3301 if (!wm8994->fll_suspend[i].out) 3302 continue; 3303 3304 ret = _wm8994_set_fll(component, i + 1, 3305 wm8994->fll_suspend[i].src, 3306 wm8994->fll_suspend[i].in, 3307 wm8994->fll_suspend[i].out); 3308 if (ret < 0) 3309 dev_warn(component->dev, "Failed to restore FLL%d: %d\n", 3310 i + 1, ret); 3311 } 3312 3313 return 0; 3314 } 3315 #else 3316 #define wm8994_component_suspend NULL 3317 #define wm8994_component_resume NULL 3318 #endif 3319 3320 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3321 { 3322 struct snd_soc_component *component = wm8994->hubs.component; 3323 struct wm8994 *control = wm8994->wm8994; 3324 struct wm8994_pdata *pdata = &control->pdata; 3325 struct snd_kcontrol_new controls[] = { 3326 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3327 wm8994->retune_mobile_enum, 3328 wm8994_get_retune_mobile_enum, 3329 wm8994_put_retune_mobile_enum), 3330 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3331 wm8994->retune_mobile_enum, 3332 wm8994_get_retune_mobile_enum, 3333 wm8994_put_retune_mobile_enum), 3334 SOC_ENUM_EXT("AIF2 EQ Mode", 3335 wm8994->retune_mobile_enum, 3336 wm8994_get_retune_mobile_enum, 3337 wm8994_put_retune_mobile_enum), 3338 }; 3339 int ret, i, j; 3340 const char **t; 3341 3342 /* We need an array of texts for the enum API but the number 3343 * of texts is likely to be less than the number of 3344 * configurations due to the sample rate dependency of the 3345 * configurations. */ 3346 wm8994->num_retune_mobile_texts = 0; 3347 wm8994->retune_mobile_texts = NULL; 3348 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3349 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3350 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3351 wm8994->retune_mobile_texts[j]) == 0) 3352 break; 3353 } 3354 3355 if (j != wm8994->num_retune_mobile_texts) 3356 continue; 3357 3358 /* Expand the array... */ 3359 t = krealloc(wm8994->retune_mobile_texts, 3360 sizeof(char *) * 3361 (wm8994->num_retune_mobile_texts + 1), 3362 GFP_KERNEL); 3363 if (t == NULL) 3364 continue; 3365 3366 /* ...store the new entry... */ 3367 t[wm8994->num_retune_mobile_texts] = 3368 pdata->retune_mobile_cfgs[i].name; 3369 3370 /* ...and remember the new version. */ 3371 wm8994->num_retune_mobile_texts++; 3372 wm8994->retune_mobile_texts = t; 3373 } 3374 3375 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 3376 wm8994->num_retune_mobile_texts); 3377 3378 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts; 3379 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3380 3381 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3382 ARRAY_SIZE(controls)); 3383 if (ret != 0) 3384 dev_err(wm8994->hubs.component->dev, 3385 "Failed to add ReTune Mobile controls: %d\n", ret); 3386 } 3387 3388 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3389 { 3390 struct snd_soc_component *component = wm8994->hubs.component; 3391 struct wm8994 *control = wm8994->wm8994; 3392 struct wm8994_pdata *pdata = &control->pdata; 3393 int ret, i; 3394 3395 if (!pdata) 3396 return; 3397 3398 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff, 3399 pdata->lineout2_diff, 3400 pdata->lineout1fb, 3401 pdata->lineout2fb, 3402 pdata->jd_scthr, 3403 pdata->jd_thr, 3404 pdata->micb1_delay, 3405 pdata->micb2_delay, 3406 pdata->micbias1_lvl, 3407 pdata->micbias2_lvl); 3408 3409 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3410 3411 if (pdata->num_drc_cfgs) { 3412 struct snd_kcontrol_new controls[] = { 3413 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3414 wm8994_get_drc_enum, wm8994_put_drc_enum), 3415 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3416 wm8994_get_drc_enum, wm8994_put_drc_enum), 3417 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3418 wm8994_get_drc_enum, wm8994_put_drc_enum), 3419 }; 3420 3421 /* We need an array of texts for the enum API */ 3422 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev, 3423 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL); 3424 if (!wm8994->drc_texts) 3425 return; 3426 3427 for (i = 0; i < pdata->num_drc_cfgs; i++) 3428 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3429 3430 wm8994->drc_enum.items = pdata->num_drc_cfgs; 3431 wm8994->drc_enum.texts = wm8994->drc_texts; 3432 3433 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3434 ARRAY_SIZE(controls)); 3435 for (i = 0; i < WM8994_NUM_DRC; i++) 3436 wm8994_set_drc(component, i); 3437 } else { 3438 ret = snd_soc_add_component_controls(wm8994->hubs.component, 3439 wm8994_drc_controls, 3440 ARRAY_SIZE(wm8994_drc_controls)); 3441 } 3442 3443 if (ret != 0) 3444 dev_err(wm8994->hubs.component->dev, 3445 "Failed to add DRC mode controls: %d\n", ret); 3446 3447 3448 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 3449 pdata->num_retune_mobile_cfgs); 3450 3451 if (pdata->num_retune_mobile_cfgs) 3452 wm8994_handle_retune_mobile_pdata(wm8994); 3453 else 3454 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls, 3455 ARRAY_SIZE(wm8994_eq_controls)); 3456 3457 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3458 if (pdata->micbias[i]) { 3459 snd_soc_component_write(component, WM8958_MICBIAS1 + i, 3460 pdata->micbias[i] & 0xffff); 3461 } 3462 } 3463 } 3464 3465 /** 3466 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3467 * 3468 * @component: WM8994 component 3469 * @jack: jack to report detection events on 3470 * @micbias: microphone bias to detect on 3471 * 3472 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3473 * being used to bring out signals to the processor then only platform 3474 * data configuration is needed for WM8994 and processor GPIOs should 3475 * be configured using snd_soc_jack_add_gpios() instead. 3476 * 3477 * Configuration of detection levels is available via the micbias1_lvl 3478 * and micbias2_lvl platform data members. 3479 */ 3480 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3481 int micbias) 3482 { 3483 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3484 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3485 struct wm8994_micdet *micdet; 3486 struct wm8994 *control = wm8994->wm8994; 3487 int reg, ret; 3488 3489 if (control->type != WM8994) { 3490 dev_warn(component->dev, "Not a WM8994\n"); 3491 return -EINVAL; 3492 } 3493 3494 switch (micbias) { 3495 case 1: 3496 micdet = &wm8994->micdet[0]; 3497 if (jack) 3498 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3499 else 3500 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3501 break; 3502 case 2: 3503 micdet = &wm8994->micdet[1]; 3504 if (jack) 3505 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3506 else 3507 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3508 break; 3509 default: 3510 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias); 3511 return -EINVAL; 3512 } 3513 3514 if (ret != 0) 3515 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n", 3516 micbias, ret); 3517 3518 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n", 3519 micbias, jack); 3520 3521 /* Store the configuration */ 3522 micdet->jack = jack; 3523 micdet->detecting = true; 3524 3525 /* If either of the jacks is set up then enable detection */ 3526 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3527 reg = WM8994_MICD_ENA; 3528 else 3529 reg = 0; 3530 3531 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3532 3533 /* enable MICDET and MICSHRT deboune */ 3534 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE, 3535 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3536 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3537 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3538 3539 snd_soc_dapm_sync(dapm); 3540 3541 return 0; 3542 } 3543 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3544 3545 static void wm8994_mic_work(struct work_struct *work) 3546 { 3547 struct wm8994_priv *priv = container_of(work, 3548 struct wm8994_priv, 3549 mic_work.work); 3550 struct regmap *regmap = priv->wm8994->regmap; 3551 struct device *dev = priv->wm8994->dev; 3552 unsigned int reg; 3553 int ret; 3554 int report; 3555 3556 pm_runtime_get_sync(dev); 3557 3558 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3559 if (ret < 0) { 3560 dev_err(dev, "Failed to read microphone status: %d\n", 3561 ret); 3562 pm_runtime_put(dev); 3563 return; 3564 } 3565 3566 dev_dbg(dev, "Microphone status: %x\n", reg); 3567 3568 report = 0; 3569 if (reg & WM8994_MIC1_DET_STS) { 3570 if (priv->micdet[0].detecting) 3571 report = SND_JACK_HEADSET; 3572 } 3573 if (reg & WM8994_MIC1_SHRT_STS) { 3574 if (priv->micdet[0].detecting) 3575 report = SND_JACK_HEADPHONE; 3576 else 3577 report |= SND_JACK_BTN_0; 3578 } 3579 if (report) 3580 priv->micdet[0].detecting = false; 3581 else 3582 priv->micdet[0].detecting = true; 3583 3584 snd_soc_jack_report(priv->micdet[0].jack, report, 3585 SND_JACK_HEADSET | SND_JACK_BTN_0); 3586 3587 report = 0; 3588 if (reg & WM8994_MIC2_DET_STS) { 3589 if (priv->micdet[1].detecting) 3590 report = SND_JACK_HEADSET; 3591 } 3592 if (reg & WM8994_MIC2_SHRT_STS) { 3593 if (priv->micdet[1].detecting) 3594 report = SND_JACK_HEADPHONE; 3595 else 3596 report |= SND_JACK_BTN_0; 3597 } 3598 if (report) 3599 priv->micdet[1].detecting = false; 3600 else 3601 priv->micdet[1].detecting = true; 3602 3603 snd_soc_jack_report(priv->micdet[1].jack, report, 3604 SND_JACK_HEADSET | SND_JACK_BTN_0); 3605 3606 pm_runtime_put(dev); 3607 } 3608 3609 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3610 { 3611 struct wm8994_priv *priv = data; 3612 struct snd_soc_component *component = priv->hubs.component; 3613 3614 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3615 trace_snd_soc_jack_irq(dev_name(component->dev)); 3616 #endif 3617 3618 pm_wakeup_event(component->dev, 300); 3619 3620 queue_delayed_work(system_power_efficient_wq, 3621 &priv->mic_work, msecs_to_jiffies(250)); 3622 3623 return IRQ_HANDLED; 3624 } 3625 3626 /* Should be called with accdet_lock held */ 3627 static void wm1811_micd_stop(struct snd_soc_component *component) 3628 { 3629 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3630 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3631 3632 if (!wm8994->jackdet) 3633 return; 3634 3635 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3636 3637 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3638 3639 if (wm8994->wm8994->pdata.jd_ext_cap) 3640 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3641 } 3642 3643 static void wm8958_button_det(struct snd_soc_component *component, u16 status) 3644 { 3645 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3646 int report; 3647 3648 report = 0; 3649 if (status & 0x4) 3650 report |= SND_JACK_BTN_0; 3651 3652 if (status & 0x8) 3653 report |= SND_JACK_BTN_1; 3654 3655 if (status & 0x10) 3656 report |= SND_JACK_BTN_2; 3657 3658 if (status & 0x20) 3659 report |= SND_JACK_BTN_3; 3660 3661 if (status & 0x40) 3662 report |= SND_JACK_BTN_4; 3663 3664 if (status & 0x80) 3665 report |= SND_JACK_BTN_5; 3666 3667 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3668 wm8994->btn_mask); 3669 } 3670 3671 static void wm8958_open_circuit_work(struct work_struct *work) 3672 { 3673 struct wm8994_priv *wm8994 = container_of(work, 3674 struct wm8994_priv, 3675 open_circuit_work.work); 3676 struct device *dev = wm8994->wm8994->dev; 3677 3678 mutex_lock(&wm8994->accdet_lock); 3679 3680 wm1811_micd_stop(wm8994->hubs.component); 3681 3682 dev_dbg(dev, "Reporting open circuit\n"); 3683 3684 wm8994->jack_mic = false; 3685 wm8994->mic_detecting = true; 3686 3687 wm8958_micd_set_rate(wm8994->hubs.component); 3688 3689 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3690 wm8994->btn_mask | 3691 SND_JACK_HEADSET); 3692 3693 mutex_unlock(&wm8994->accdet_lock); 3694 } 3695 3696 static void wm8958_mic_id(void *data, u16 status) 3697 { 3698 struct snd_soc_component *component = data; 3699 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3700 3701 /* Either nothing present or just starting detection */ 3702 if (!(status & WM8958_MICD_STS)) { 3703 /* If nothing present then clear our statuses */ 3704 dev_dbg(component->dev, "Detected open circuit\n"); 3705 3706 queue_delayed_work(system_power_efficient_wq, 3707 &wm8994->open_circuit_work, 3708 msecs_to_jiffies(2500)); 3709 return; 3710 } 3711 3712 /* If the measurement is showing a high impedence we've got a 3713 * microphone. 3714 */ 3715 if (status & 0x600) { 3716 dev_dbg(component->dev, "Detected microphone\n"); 3717 3718 wm8994->mic_detecting = false; 3719 wm8994->jack_mic = true; 3720 3721 wm8958_micd_set_rate(component); 3722 3723 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3724 SND_JACK_HEADSET); 3725 } 3726 3727 3728 if (status & 0xfc) { 3729 dev_dbg(component->dev, "Detected headphone\n"); 3730 wm8994->mic_detecting = false; 3731 3732 wm8958_micd_set_rate(component); 3733 3734 /* If we have jackdet that will detect removal */ 3735 wm1811_micd_stop(component); 3736 3737 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3738 SND_JACK_HEADSET); 3739 } 3740 } 3741 3742 /* Deferred mic detection to allow for extra settling time */ 3743 static void wm1811_mic_work(struct work_struct *work) 3744 { 3745 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3746 mic_work.work); 3747 struct wm8994 *control = wm8994->wm8994; 3748 struct snd_soc_component *component = wm8994->hubs.component; 3749 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3750 3751 pm_runtime_get_sync(component->dev); 3752 3753 /* If required for an external cap force MICBIAS on */ 3754 if (control->pdata.jd_ext_cap) { 3755 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 3756 snd_soc_dapm_sync(dapm); 3757 } 3758 3759 mutex_lock(&wm8994->accdet_lock); 3760 3761 dev_dbg(component->dev, "Starting mic detection\n"); 3762 3763 /* Use a user-supplied callback if we have one */ 3764 if (wm8994->micd_cb) { 3765 wm8994->micd_cb(wm8994->micd_cb_data); 3766 } else { 3767 /* 3768 * Start off measument of microphone impedence to find out 3769 * what's actually there. 3770 */ 3771 wm8994->mic_detecting = true; 3772 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC); 3773 3774 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3775 WM8958_MICD_ENA, WM8958_MICD_ENA); 3776 } 3777 3778 mutex_unlock(&wm8994->accdet_lock); 3779 3780 pm_runtime_put(component->dev); 3781 } 3782 3783 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3784 { 3785 struct wm8994_priv *wm8994 = data; 3786 struct wm8994 *control = wm8994->wm8994; 3787 struct snd_soc_component *component = wm8994->hubs.component; 3788 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3789 int reg, delay; 3790 bool present; 3791 3792 pm_runtime_get_sync(component->dev); 3793 3794 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3795 3796 mutex_lock(&wm8994->accdet_lock); 3797 3798 reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL); 3799 if (reg < 0) { 3800 dev_err(component->dev, "Failed to read jack status: %d\n", reg); 3801 mutex_unlock(&wm8994->accdet_lock); 3802 pm_runtime_put(component->dev); 3803 return IRQ_NONE; 3804 } 3805 3806 dev_dbg(component->dev, "JACKDET %x\n", reg); 3807 3808 present = reg & WM1811_JACKDET_LVL; 3809 3810 if (present) { 3811 dev_dbg(component->dev, "Jack detected\n"); 3812 3813 wm8958_micd_set_rate(component); 3814 3815 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3816 WM8958_MICB2_DISCH, 0); 3817 3818 /* Disable debounce while inserted */ 3819 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3820 WM1811_JACKDET_DB, 0); 3821 3822 delay = control->pdata.micdet_delay; 3823 queue_delayed_work(system_power_efficient_wq, 3824 &wm8994->mic_work, 3825 msecs_to_jiffies(delay)); 3826 } else { 3827 dev_dbg(component->dev, "Jack not detected\n"); 3828 3829 cancel_delayed_work_sync(&wm8994->mic_work); 3830 3831 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3832 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3833 3834 /* Enable debounce while removed */ 3835 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3836 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3837 3838 wm8994->mic_detecting = false; 3839 wm8994->jack_mic = false; 3840 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3841 WM8958_MICD_ENA, 0); 3842 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3843 } 3844 3845 mutex_unlock(&wm8994->accdet_lock); 3846 3847 /* Turn off MICBIAS if it was on for an external cap */ 3848 if (control->pdata.jd_ext_cap && !present) 3849 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3850 3851 if (present) 3852 snd_soc_jack_report(wm8994->micdet[0].jack, 3853 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3854 else 3855 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3856 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3857 wm8994->btn_mask); 3858 3859 /* Since we only report deltas force an update, ensures we 3860 * avoid bootstrapping issues with the core. */ 3861 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3862 3863 pm_runtime_put(component->dev); 3864 return IRQ_HANDLED; 3865 } 3866 3867 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3868 { 3869 struct wm8994_priv *wm8994 = container_of(work, 3870 struct wm8994_priv, 3871 jackdet_bootstrap.work); 3872 wm1811_jackdet_irq(0, wm8994); 3873 } 3874 3875 /** 3876 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3877 * 3878 * @component: WM8958 component 3879 * @jack: jack to report detection events on 3880 * 3881 * Enable microphone detection functionality for the WM8958. By 3882 * default simple detection which supports the detection of up to 6 3883 * buttons plus video and microphone functionality is supported. 3884 * 3885 * The WM8958 has an advanced jack detection facility which is able to 3886 * support complex accessory detection, especially when used in 3887 * conjunction with external circuitry. In order to provide maximum 3888 * flexiblity a callback is provided which allows a completely custom 3889 * detection algorithm. 3890 */ 3891 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3892 wm1811_micdet_cb det_cb, void *det_cb_data, 3893 wm1811_mic_id_cb id_cb, void *id_cb_data) 3894 { 3895 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3896 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3897 struct wm8994 *control = wm8994->wm8994; 3898 u16 micd_lvl_sel; 3899 3900 switch (control->type) { 3901 case WM1811: 3902 case WM8958: 3903 break; 3904 default: 3905 return -EINVAL; 3906 } 3907 3908 if (jack) { 3909 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS"); 3910 snd_soc_dapm_sync(dapm); 3911 3912 wm8994->micdet[0].jack = jack; 3913 3914 if (det_cb) { 3915 wm8994->micd_cb = det_cb; 3916 wm8994->micd_cb_data = det_cb_data; 3917 } else { 3918 wm8994->mic_detecting = true; 3919 wm8994->jack_mic = false; 3920 } 3921 3922 if (id_cb) { 3923 wm8994->mic_id_cb = id_cb; 3924 wm8994->mic_id_cb_data = id_cb_data; 3925 } else { 3926 wm8994->mic_id_cb = wm8958_mic_id; 3927 wm8994->mic_id_cb_data = component; 3928 } 3929 3930 wm8958_micd_set_rate(component); 3931 3932 /* Detect microphones and short circuits by default */ 3933 if (control->pdata.micd_lvl_sel) 3934 micd_lvl_sel = control->pdata.micd_lvl_sel; 3935 else 3936 micd_lvl_sel = 0x41; 3937 3938 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3939 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3940 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3941 3942 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2, 3943 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3944 3945 WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY); 3946 3947 /* 3948 * If we can use jack detection start off with that, 3949 * otherwise jump straight to microphone detection. 3950 */ 3951 if (wm8994->jackdet) { 3952 /* Disable debounce for the initial detect */ 3953 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3954 WM1811_JACKDET_DB, 0); 3955 3956 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3957 WM8958_MICB2_DISCH, 3958 WM8958_MICB2_DISCH); 3959 snd_soc_component_update_bits(component, WM8994_LDO_1, 3960 WM8994_LDO1_DISCH, 0); 3961 wm1811_jackdet_set_mode(component, 3962 WM1811_JACKDET_MODE_JACK); 3963 } else { 3964 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3965 WM8958_MICD_ENA, WM8958_MICD_ENA); 3966 } 3967 3968 } else { 3969 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3970 WM8958_MICD_ENA, 0); 3971 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE); 3972 snd_soc_dapm_disable_pin(dapm, "CLK_SYS"); 3973 snd_soc_dapm_sync(dapm); 3974 } 3975 3976 return 0; 3977 } 3978 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3979 3980 static void wm8958_mic_work(struct work_struct *work) 3981 { 3982 struct wm8994_priv *wm8994 = container_of(work, 3983 struct wm8994_priv, 3984 mic_complete_work.work); 3985 struct snd_soc_component *component = wm8994->hubs.component; 3986 3987 pm_runtime_get_sync(component->dev); 3988 3989 mutex_lock(&wm8994->accdet_lock); 3990 3991 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status); 3992 3993 mutex_unlock(&wm8994->accdet_lock); 3994 3995 pm_runtime_put(component->dev); 3996 } 3997 3998 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3999 { 4000 struct wm8994_priv *wm8994 = data; 4001 struct snd_soc_component *component = wm8994->hubs.component; 4002 int reg, count, ret, id_delay; 4003 4004 /* 4005 * Jack detection may have detected a removal simulataneously 4006 * with an update of the MICDET status; if so it will have 4007 * stopped detection and we can ignore this interrupt. 4008 */ 4009 if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 4010 return IRQ_HANDLED; 4011 4012 cancel_delayed_work_sync(&wm8994->mic_complete_work); 4013 cancel_delayed_work_sync(&wm8994->open_circuit_work); 4014 4015 pm_runtime_get_sync(component->dev); 4016 4017 /* We may occasionally read a detection without an impedence 4018 * range being provided - if that happens loop again. 4019 */ 4020 count = 10; 4021 do { 4022 reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3); 4023 if (reg < 0) { 4024 dev_err(component->dev, 4025 "Failed to read mic detect status: %d\n", 4026 reg); 4027 pm_runtime_put(component->dev); 4028 return IRQ_NONE; 4029 } 4030 4031 if (!(reg & WM8958_MICD_VALID)) { 4032 dev_dbg(component->dev, "Mic detect data not valid\n"); 4033 goto out; 4034 } 4035 4036 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 4037 break; 4038 4039 msleep(1); 4040 } while (count--); 4041 4042 if (count == 0) 4043 dev_warn(component->dev, "No impedance range reported for jack\n"); 4044 4045 #ifndef CONFIG_SND_SOC_WM8994_MODULE 4046 trace_snd_soc_jack_irq(dev_name(component->dev)); 4047 #endif 4048 4049 /* Avoid a transient report when the accessory is being removed */ 4050 if (wm8994->jackdet) { 4051 ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL); 4052 if (ret < 0) { 4053 dev_err(component->dev, "Failed to read jack status: %d\n", 4054 ret); 4055 } else if (!(ret & WM1811_JACKDET_LVL)) { 4056 dev_dbg(component->dev, "Ignoring removed jack\n"); 4057 goto out; 4058 } 4059 } else if (!(reg & WM8958_MICD_STS)) { 4060 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 4061 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 4062 wm8994->btn_mask); 4063 wm8994->mic_detecting = true; 4064 goto out; 4065 } 4066 4067 wm8994->mic_status = reg; 4068 id_delay = wm8994->wm8994->pdata.mic_id_delay; 4069 4070 if (wm8994->mic_detecting) 4071 queue_delayed_work(system_power_efficient_wq, 4072 &wm8994->mic_complete_work, 4073 msecs_to_jiffies(id_delay)); 4074 else 4075 wm8958_button_det(component, reg); 4076 4077 out: 4078 pm_runtime_put(component->dev); 4079 return IRQ_HANDLED; 4080 } 4081 4082 static irqreturn_t wm8994_fifo_error(int irq, void *data) 4083 { 4084 struct snd_soc_component *component = data; 4085 4086 dev_err(component->dev, "FIFO error\n"); 4087 4088 return IRQ_HANDLED; 4089 } 4090 4091 static irqreturn_t wm8994_temp_warn(int irq, void *data) 4092 { 4093 struct snd_soc_component *component = data; 4094 4095 dev_err(component->dev, "Thermal warning\n"); 4096 4097 return IRQ_HANDLED; 4098 } 4099 4100 static irqreturn_t wm8994_temp_shut(int irq, void *data) 4101 { 4102 struct snd_soc_component *component = data; 4103 4104 dev_crit(component->dev, "Thermal shutdown\n"); 4105 4106 return IRQ_HANDLED; 4107 } 4108 4109 static int wm8994_component_probe(struct snd_soc_component *component) 4110 { 4111 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 4112 struct wm8994 *control = dev_get_drvdata(component->dev->parent); 4113 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 4114 unsigned int reg; 4115 int ret, i; 4116 4117 snd_soc_component_init_regmap(component, control->regmap); 4118 4119 wm8994->hubs.component = component; 4120 4121 mutex_init(&wm8994->accdet_lock); 4122 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 4123 wm1811_jackdet_bootstrap); 4124 INIT_DELAYED_WORK(&wm8994->open_circuit_work, 4125 wm8958_open_circuit_work); 4126 4127 switch (control->type) { 4128 case WM8994: 4129 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 4130 break; 4131 case WM1811: 4132 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 4133 break; 4134 default: 4135 break; 4136 } 4137 4138 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work); 4139 4140 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4141 init_completion(&wm8994->fll_locked[i]); 4142 4143 wm8994->micdet_irq = control->pdata.micdet_irq; 4144 4145 /* By default use idle_bias_off, will override for WM8994 */ 4146 dapm->idle_bias_off = 1; 4147 4148 /* Set revision-specific configuration */ 4149 switch (control->type) { 4150 case WM8994: 4151 /* Single ended line outputs should have VMID on. */ 4152 if (!control->pdata.lineout1_diff || 4153 !control->pdata.lineout2_diff) 4154 dapm->idle_bias_off = 0; 4155 4156 switch (control->revision) { 4157 case 2: 4158 case 3: 4159 wm8994->hubs.dcs_codes_l = -5; 4160 wm8994->hubs.dcs_codes_r = -5; 4161 wm8994->hubs.hp_startup_mode = 1; 4162 wm8994->hubs.dcs_readback_mode = 1; 4163 wm8994->hubs.series_startup = 1; 4164 break; 4165 default: 4166 wm8994->hubs.dcs_readback_mode = 2; 4167 break; 4168 } 4169 break; 4170 4171 case WM8958: 4172 wm8994->hubs.dcs_readback_mode = 1; 4173 wm8994->hubs.hp_startup_mode = 1; 4174 4175 switch (control->revision) { 4176 case 0: 4177 break; 4178 default: 4179 wm8994->fll_byp = true; 4180 break; 4181 } 4182 break; 4183 4184 case WM1811: 4185 wm8994->hubs.dcs_readback_mode = 2; 4186 wm8994->hubs.no_series_update = 1; 4187 wm8994->hubs.hp_startup_mode = 1; 4188 wm8994->hubs.no_cache_dac_hp_direct = true; 4189 wm8994->fll_byp = true; 4190 4191 wm8994->hubs.dcs_codes_l = -9; 4192 wm8994->hubs.dcs_codes_r = -7; 4193 4194 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1, 4195 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 4196 break; 4197 4198 default: 4199 break; 4200 } 4201 4202 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 4203 wm8994_fifo_error, "FIFO error", component); 4204 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 4205 wm8994_temp_warn, "Thermal warning", component); 4206 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 4207 wm8994_temp_shut, "Thermal shutdown", component); 4208 4209 switch (control->type) { 4210 case WM8994: 4211 if (wm8994->micdet_irq) 4212 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4213 wm8994_mic_irq, 4214 IRQF_TRIGGER_RISING | 4215 IRQF_ONESHOT, 4216 "Mic1 detect", 4217 wm8994); 4218 else 4219 ret = wm8994_request_irq(wm8994->wm8994, 4220 WM8994_IRQ_MIC1_DET, 4221 wm8994_mic_irq, "Mic 1 detect", 4222 wm8994); 4223 4224 if (ret != 0) 4225 dev_warn(component->dev, 4226 "Failed to request Mic1 detect IRQ: %d\n", 4227 ret); 4228 4229 4230 ret = wm8994_request_irq(wm8994->wm8994, 4231 WM8994_IRQ_MIC1_SHRT, 4232 wm8994_mic_irq, "Mic 1 short", 4233 wm8994); 4234 if (ret != 0) 4235 dev_warn(component->dev, 4236 "Failed to request Mic1 short IRQ: %d\n", 4237 ret); 4238 4239 ret = wm8994_request_irq(wm8994->wm8994, 4240 WM8994_IRQ_MIC2_DET, 4241 wm8994_mic_irq, "Mic 2 detect", 4242 wm8994); 4243 if (ret != 0) 4244 dev_warn(component->dev, 4245 "Failed to request Mic2 detect IRQ: %d\n", 4246 ret); 4247 4248 ret = wm8994_request_irq(wm8994->wm8994, 4249 WM8994_IRQ_MIC2_SHRT, 4250 wm8994_mic_irq, "Mic 2 short", 4251 wm8994); 4252 if (ret != 0) 4253 dev_warn(component->dev, 4254 "Failed to request Mic2 short IRQ: %d\n", 4255 ret); 4256 break; 4257 4258 case WM8958: 4259 case WM1811: 4260 if (wm8994->micdet_irq) { 4261 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4262 wm8958_mic_irq, 4263 IRQF_TRIGGER_RISING | 4264 IRQF_ONESHOT, 4265 "Mic detect", 4266 wm8994); 4267 if (ret != 0) 4268 dev_warn(component->dev, 4269 "Failed to request Mic detect IRQ: %d\n", 4270 ret); 4271 } else { 4272 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4273 wm8958_mic_irq, "Mic detect", 4274 wm8994); 4275 } 4276 } 4277 4278 switch (control->type) { 4279 case WM1811: 4280 if (control->cust_id > 1 || control->revision > 1) { 4281 ret = wm8994_request_irq(wm8994->wm8994, 4282 WM8994_IRQ_GPIO(6), 4283 wm1811_jackdet_irq, "JACKDET", 4284 wm8994); 4285 if (ret == 0) 4286 wm8994->jackdet = true; 4287 } 4288 break; 4289 default: 4290 break; 4291 } 4292 4293 wm8994->fll_locked_irq = true; 4294 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4295 ret = wm8994_request_irq(wm8994->wm8994, 4296 WM8994_IRQ_FLL1_LOCK + i, 4297 wm8994_fll_locked_irq, "FLL lock", 4298 &wm8994->fll_locked[i]); 4299 if (ret != 0) 4300 wm8994->fll_locked_irq = false; 4301 } 4302 4303 /* Make sure we can read from the GPIOs if they're inputs */ 4304 pm_runtime_get_sync(component->dev); 4305 4306 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4307 * configured on init - if a system wants to do this dynamically 4308 * at runtime we can deal with that then. 4309 */ 4310 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4311 if (ret < 0) { 4312 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret); 4313 goto err_irq; 4314 } 4315 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4316 wm8994->lrclk_shared[0] = 1; 4317 wm8994_dai[0].symmetric_rates = 1; 4318 } else { 4319 wm8994->lrclk_shared[0] = 0; 4320 } 4321 4322 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4323 if (ret < 0) { 4324 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret); 4325 goto err_irq; 4326 } 4327 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4328 wm8994->lrclk_shared[1] = 1; 4329 wm8994_dai[1].symmetric_rates = 1; 4330 } else { 4331 wm8994->lrclk_shared[1] = 0; 4332 } 4333 4334 pm_runtime_put(component->dev); 4335 4336 /* Latch volume update bits */ 4337 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4338 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg, 4339 wm8994_vu_bits[i].mask, 4340 wm8994_vu_bits[i].mask); 4341 4342 /* Set the low bit of the 3D stereo depth so TLV matches */ 4343 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2, 4344 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4345 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4346 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2, 4347 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4348 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4349 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2, 4350 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4351 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4352 4353 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4354 * use this; it only affects behaviour on idle TDM clock 4355 * cycles. */ 4356 switch (control->type) { 4357 case WM8994: 4358 case WM8958: 4359 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1, 4360 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4361 break; 4362 default: 4363 break; 4364 } 4365 4366 /* Put MICBIAS into bypass mode by default on newer devices */ 4367 switch (control->type) { 4368 case WM8958: 4369 case WM1811: 4370 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 4371 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4372 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 4373 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4374 break; 4375 default: 4376 break; 4377 } 4378 4379 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4380 wm_hubs_update_class_w(component); 4381 4382 wm8994_handle_pdata(wm8994); 4383 4384 wm_hubs_add_analogue_controls(component); 4385 snd_soc_add_component_controls(component, wm8994_common_snd_controls, 4386 ARRAY_SIZE(wm8994_common_snd_controls)); 4387 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4388 ARRAY_SIZE(wm8994_dapm_widgets)); 4389 4390 switch (control->type) { 4391 case WM8994: 4392 snd_soc_add_component_controls(component, wm8994_snd_controls, 4393 ARRAY_SIZE(wm8994_snd_controls)); 4394 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4395 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4396 if (control->revision < 4) { 4397 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4398 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4399 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4400 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4401 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4402 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4403 } else { 4404 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4405 ARRAY_SIZE(wm8994_lateclk_widgets)); 4406 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4407 ARRAY_SIZE(wm8994_adc_widgets)); 4408 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4409 ARRAY_SIZE(wm8994_dac_widgets)); 4410 } 4411 break; 4412 case WM8958: 4413 snd_soc_add_component_controls(component, wm8994_snd_controls, 4414 ARRAY_SIZE(wm8994_snd_controls)); 4415 snd_soc_add_component_controls(component, wm8958_snd_controls, 4416 ARRAY_SIZE(wm8958_snd_controls)); 4417 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4418 ARRAY_SIZE(wm8958_dapm_widgets)); 4419 if (control->revision < 1) { 4420 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4421 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4422 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4423 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4424 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4425 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4426 } else { 4427 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4428 ARRAY_SIZE(wm8994_lateclk_widgets)); 4429 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4430 ARRAY_SIZE(wm8994_adc_widgets)); 4431 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4432 ARRAY_SIZE(wm8994_dac_widgets)); 4433 } 4434 break; 4435 4436 case WM1811: 4437 snd_soc_add_component_controls(component, wm8958_snd_controls, 4438 ARRAY_SIZE(wm8958_snd_controls)); 4439 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4440 ARRAY_SIZE(wm8958_dapm_widgets)); 4441 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4442 ARRAY_SIZE(wm8994_lateclk_widgets)); 4443 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4444 ARRAY_SIZE(wm8994_adc_widgets)); 4445 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4446 ARRAY_SIZE(wm8994_dac_widgets)); 4447 break; 4448 } 4449 4450 wm_hubs_add_analogue_routes(component, 0, 0); 4451 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4452 wm_hubs_dcs_done, "DC servo done", 4453 &wm8994->hubs); 4454 if (ret == 0) 4455 wm8994->hubs.dcs_done_irq = true; 4456 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4457 4458 switch (control->type) { 4459 case WM8994: 4460 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4461 ARRAY_SIZE(wm8994_intercon)); 4462 4463 if (control->revision < 4) { 4464 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4465 ARRAY_SIZE(wm8994_revd_intercon)); 4466 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4467 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4468 } else { 4469 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4470 ARRAY_SIZE(wm8994_lateclk_intercon)); 4471 } 4472 break; 4473 case WM8958: 4474 if (control->revision < 1) { 4475 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4476 ARRAY_SIZE(wm8994_intercon)); 4477 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4478 ARRAY_SIZE(wm8994_revd_intercon)); 4479 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4480 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4481 } else { 4482 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4483 ARRAY_SIZE(wm8994_lateclk_intercon)); 4484 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4485 ARRAY_SIZE(wm8958_intercon)); 4486 } 4487 4488 wm8958_dsp2_init(component); 4489 break; 4490 case WM1811: 4491 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4492 ARRAY_SIZE(wm8994_lateclk_intercon)); 4493 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4494 ARRAY_SIZE(wm8958_intercon)); 4495 break; 4496 } 4497 4498 return 0; 4499 4500 err_irq: 4501 if (wm8994->jackdet) 4502 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4503 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4504 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4505 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4506 if (wm8994->micdet_irq) 4507 free_irq(wm8994->micdet_irq, wm8994); 4508 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4509 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4510 &wm8994->fll_locked[i]); 4511 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4512 &wm8994->hubs); 4513 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4514 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4515 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4516 4517 return ret; 4518 } 4519 4520 static void wm8994_component_remove(struct snd_soc_component *component) 4521 { 4522 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 4523 struct wm8994 *control = wm8994->wm8994; 4524 int i; 4525 4526 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4527 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4528 &wm8994->fll_locked[i]); 4529 4530 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4531 &wm8994->hubs); 4532 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4533 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4534 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4535 4536 if (wm8994->jackdet) 4537 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4538 4539 switch (control->type) { 4540 case WM8994: 4541 if (wm8994->micdet_irq) 4542 free_irq(wm8994->micdet_irq, wm8994); 4543 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4544 wm8994); 4545 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4546 wm8994); 4547 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4548 wm8994); 4549 break; 4550 4551 case WM1811: 4552 case WM8958: 4553 if (wm8994->micdet_irq) 4554 free_irq(wm8994->micdet_irq, wm8994); 4555 break; 4556 } 4557 release_firmware(wm8994->mbc); 4558 release_firmware(wm8994->mbc_vss); 4559 release_firmware(wm8994->enh_eq); 4560 kfree(wm8994->retune_mobile_texts); 4561 } 4562 4563 static const struct snd_soc_component_driver soc_component_dev_wm8994 = { 4564 .probe = wm8994_component_probe, 4565 .remove = wm8994_component_remove, 4566 .suspend = wm8994_component_suspend, 4567 .resume = wm8994_component_resume, 4568 .set_bias_level = wm8994_set_bias_level, 4569 .idle_bias_on = 1, 4570 .use_pmdown_time = 1, 4571 .endianness = 1, 4572 .non_legacy_dai_naming = 1, 4573 }; 4574 4575 static int wm8994_probe(struct platform_device *pdev) 4576 { 4577 struct wm8994_priv *wm8994; 4578 int ret; 4579 4580 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4581 GFP_KERNEL); 4582 if (wm8994 == NULL) 4583 return -ENOMEM; 4584 platform_set_drvdata(pdev, wm8994); 4585 4586 mutex_init(&wm8994->fw_lock); 4587 4588 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4589 4590 wm8994->mclk[WM8994_MCLK1].id = "MCLK1"; 4591 wm8994->mclk[WM8994_MCLK2].id = "MCLK2"; 4592 4593 ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk), 4594 wm8994->mclk); 4595 if (ret < 0) { 4596 dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret); 4597 return ret; 4598 } 4599 4600 pm_runtime_enable(&pdev->dev); 4601 pm_runtime_idle(&pdev->dev); 4602 4603 return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994, 4604 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4605 } 4606 4607 static int wm8994_remove(struct platform_device *pdev) 4608 { 4609 pm_runtime_disable(&pdev->dev); 4610 4611 return 0; 4612 } 4613 4614 #ifdef CONFIG_PM_SLEEP 4615 static int wm8994_suspend(struct device *dev) 4616 { 4617 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4618 4619 /* Drop down to power saving mode when system is suspended */ 4620 if (wm8994->jackdet && !wm8994->active_refcount) 4621 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4622 WM1811_JACKDET_MODE_MASK, 4623 wm8994->jackdet_mode); 4624 4625 return 0; 4626 } 4627 4628 static int wm8994_resume(struct device *dev) 4629 { 4630 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4631 4632 if (wm8994->jackdet && wm8994->jackdet_mode) 4633 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4634 WM1811_JACKDET_MODE_MASK, 4635 WM1811_JACKDET_MODE_AUDIO); 4636 4637 return 0; 4638 } 4639 #endif 4640 4641 static const struct dev_pm_ops wm8994_pm_ops = { 4642 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4643 }; 4644 4645 static struct platform_driver wm8994_codec_driver = { 4646 .driver = { 4647 .name = "wm8994-codec", 4648 .pm = &wm8994_pm_ops, 4649 }, 4650 .probe = wm8994_probe, 4651 .remove = wm8994_remove, 4652 }; 4653 4654 module_platform_driver(wm8994_codec_driver); 4655 4656 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4657 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4658 MODULE_LICENSE("GPL"); 4659 MODULE_ALIAS("platform:wm8994-codec"); 4660