1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 #include <trace/events/asoc.h> 33 34 #include <linux/mfd/wm8994/core.h> 35 #include <linux/mfd/wm8994/registers.h> 36 #include <linux/mfd/wm8994/pdata.h> 37 #include <linux/mfd/wm8994/gpio.h> 38 39 #include "wm8994.h" 40 #include "wm_hubs.h" 41 42 #define WM1811_JACKDET_MODE_NONE 0x0000 43 #define WM1811_JACKDET_MODE_JACK 0x0100 44 #define WM1811_JACKDET_MODE_MIC 0x0080 45 #define WM1811_JACKDET_MODE_AUDIO 0x0180 46 47 #define WM8994_NUM_DRC 3 48 #define WM8994_NUM_EQ 3 49 50 static struct { 51 unsigned int reg; 52 unsigned int mask; 53 } wm8994_vu_bits[] = { 54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 64 65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 81 }; 82 83 static int wm8994_drc_base[] = { 84 WM8994_AIF1_DRC1_1, 85 WM8994_AIF1_DRC2_1, 86 WM8994_AIF2_DRC_1, 87 }; 88 89 static int wm8994_retune_mobile_base[] = { 90 WM8994_AIF1_DAC1_EQ_GAINS_1, 91 WM8994_AIF1_DAC2_EQ_GAINS_1, 92 WM8994_AIF2_EQ_GAINS_1, 93 }; 94 95 static const struct wm8958_micd_rate micdet_rates[] = { 96 { 32768, true, 1, 4 }, 97 { 32768, false, 1, 1 }, 98 { 44100 * 256, true, 7, 10 }, 99 { 44100 * 256, false, 7, 10 }, 100 }; 101 102 static const struct wm8958_micd_rate jackdet_rates[] = { 103 { 32768, true, 0, 1 }, 104 { 32768, false, 0, 1 }, 105 { 44100 * 256, true, 10, 10 }, 106 { 44100 * 256, false, 7, 8 }, 107 }; 108 109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec) 110 { 111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 112 struct wm8994 *control = wm8994->wm8994; 113 int best, i, sysclk, val; 114 bool idle; 115 const struct wm8958_micd_rate *rates; 116 int num_rates; 117 118 idle = !wm8994->jack_mic; 119 120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1); 121 if (sysclk & WM8994_SYSCLK_SRC) 122 sysclk = wm8994->aifclk[1]; 123 else 124 sysclk = wm8994->aifclk[0]; 125 126 if (control->pdata.micd_rates) { 127 rates = control->pdata.micd_rates; 128 num_rates = control->pdata.num_micd_rates; 129 } else if (wm8994->jackdet) { 130 rates = jackdet_rates; 131 num_rates = ARRAY_SIZE(jackdet_rates); 132 } else { 133 rates = micdet_rates; 134 num_rates = ARRAY_SIZE(micdet_rates); 135 } 136 137 best = 0; 138 for (i = 0; i < num_rates; i++) { 139 if (rates[i].idle != idle) 140 continue; 141 if (abs(rates[i].sysclk - sysclk) < 142 abs(rates[best].sysclk - sysclk)) 143 best = i; 144 else if (rates[best].idle != idle) 145 best = i; 146 } 147 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 149 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 150 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n", 152 rates[best].start, rates[best].rate, sysclk, 153 idle ? "idle" : "active"); 154 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 156 WM8958_MICD_BIAS_STARTTIME_MASK | 157 WM8958_MICD_RATE_MASK, val); 158 } 159 160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 161 { 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 163 int rate; 164 int reg1 = 0; 165 int offset; 166 167 if (aif) 168 offset = 4; 169 else 170 offset = 0; 171 172 switch (wm8994->sysclk[aif]) { 173 case WM8994_SYSCLK_MCLK1: 174 rate = wm8994->mclk[0]; 175 break; 176 177 case WM8994_SYSCLK_MCLK2: 178 reg1 |= 0x8; 179 rate = wm8994->mclk[1]; 180 break; 181 182 case WM8994_SYSCLK_FLL1: 183 reg1 |= 0x10; 184 rate = wm8994->fll[0].out; 185 break; 186 187 case WM8994_SYSCLK_FLL2: 188 reg1 |= 0x18; 189 rate = wm8994->fll[1].out; 190 break; 191 192 default: 193 return -EINVAL; 194 } 195 196 if (rate >= 13500000) { 197 rate /= 2; 198 reg1 |= WM8994_AIF1CLK_DIV; 199 200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 201 aif + 1, rate); 202 } 203 204 wm8994->aifclk[aif] = rate; 205 206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 208 reg1); 209 210 return 0; 211 } 212 213 static int configure_clock(struct snd_soc_codec *codec) 214 { 215 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 216 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 217 int change, new; 218 219 /* Bring up the AIF clocks first */ 220 configure_aif_clock(codec, 0); 221 configure_aif_clock(codec, 1); 222 223 /* Then switch CLK_SYS over to the higher of them; a change 224 * can only happen as a result of a clocking change which can 225 * only be made outside of DAPM so we can safely redo the 226 * clocking. 227 */ 228 229 /* If they're equal it doesn't matter which is used */ 230 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 231 wm8958_micd_set_rate(codec); 232 return 0; 233 } 234 235 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 236 new = WM8994_SYSCLK_SRC; 237 else 238 new = 0; 239 240 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1, 241 WM8994_SYSCLK_SRC, new); 242 if (change) 243 snd_soc_dapm_sync(dapm); 244 245 wm8958_micd_set_rate(codec); 246 247 return 0; 248 } 249 250 static int check_clk_sys(struct snd_soc_dapm_widget *source, 251 struct snd_soc_dapm_widget *sink) 252 { 253 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 254 int reg = snd_soc_read(codec, WM8994_CLOCKING_1); 255 const char *clk; 256 257 /* Check what we're currently using for CLK_SYS */ 258 if (reg & WM8994_SYSCLK_SRC) 259 clk = "AIF2CLK"; 260 else 261 clk = "AIF1CLK"; 262 263 return strcmp(source->name, clk) == 0; 264 } 265 266 static const char *sidetone_hpf_text[] = { 267 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 268 }; 269 270 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 271 WM8994_SIDETONE, 7, sidetone_hpf_text); 272 273 static const char *adc_hpf_text[] = { 274 "HiFi", "Voice 1", "Voice 2", "Voice 3" 275 }; 276 277 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf, 278 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text); 279 280 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf, 281 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text); 282 283 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf, 284 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text); 285 286 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 287 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 288 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 289 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 290 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 291 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 292 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); 293 294 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 295 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ 296 snd_soc_get_volsw, wm8994_put_drc_sw) 297 298 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 299 struct snd_ctl_elem_value *ucontrol) 300 { 301 struct soc_mixer_control *mc = 302 (struct soc_mixer_control *)kcontrol->private_value; 303 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 304 int mask, ret; 305 306 /* Can't enable both ADC and DAC paths simultaneously */ 307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 309 WM8994_AIF1ADC1R_DRC_ENA_MASK; 310 else 311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 312 313 ret = snd_soc_read(codec, mc->reg); 314 if (ret < 0) 315 return ret; 316 if (ret & mask) 317 return -EINVAL; 318 319 return snd_soc_put_volsw(kcontrol, ucontrol); 320 } 321 322 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 323 { 324 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 325 struct wm8994 *control = wm8994->wm8994; 326 struct wm8994_pdata *pdata = &control->pdata; 327 int base = wm8994_drc_base[drc]; 328 int cfg = wm8994->drc_cfg[drc]; 329 int save, i; 330 331 /* Save any enables; the configuration should clear them. */ 332 save = snd_soc_read(codec, base); 333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 334 WM8994_AIF1ADC1R_DRC_ENA; 335 336 for (i = 0; i < WM8994_DRC_REGS; i++) 337 snd_soc_update_bits(codec, base + i, 0xffff, 338 pdata->drc_cfgs[cfg].regs[i]); 339 340 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 341 WM8994_AIF1ADC1L_DRC_ENA | 342 WM8994_AIF1ADC1R_DRC_ENA, save); 343 } 344 345 /* Icky as hell but saves code duplication */ 346 static int wm8994_get_drc(const char *name) 347 { 348 if (strcmp(name, "AIF1DRC1 Mode") == 0) 349 return 0; 350 if (strcmp(name, "AIF1DRC2 Mode") == 0) 351 return 1; 352 if (strcmp(name, "AIF2DRC Mode") == 0) 353 return 2; 354 return -EINVAL; 355 } 356 357 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 358 struct snd_ctl_elem_value *ucontrol) 359 { 360 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 362 struct wm8994 *control = wm8994->wm8994; 363 struct wm8994_pdata *pdata = &control->pdata; 364 int drc = wm8994_get_drc(kcontrol->id.name); 365 int value = ucontrol->value.integer.value[0]; 366 367 if (drc < 0) 368 return drc; 369 370 if (value >= pdata->num_drc_cfgs) 371 return -EINVAL; 372 373 wm8994->drc_cfg[drc] = value; 374 375 wm8994_set_drc(codec, drc); 376 377 return 0; 378 } 379 380 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 381 struct snd_ctl_elem_value *ucontrol) 382 { 383 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 385 int drc = wm8994_get_drc(kcontrol->id.name); 386 387 if (drc < 0) 388 return drc; 389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 390 391 return 0; 392 } 393 394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 395 { 396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 397 struct wm8994 *control = wm8994->wm8994; 398 struct wm8994_pdata *pdata = &control->pdata; 399 int base = wm8994_retune_mobile_base[block]; 400 int iface, best, best_val, save, i, cfg; 401 402 if (!pdata || !wm8994->num_retune_mobile_texts) 403 return; 404 405 switch (block) { 406 case 0: 407 case 1: 408 iface = 0; 409 break; 410 case 2: 411 iface = 1; 412 break; 413 default: 414 return; 415 } 416 417 /* Find the version of the currently selected configuration 418 * with the nearest sample rate. */ 419 cfg = wm8994->retune_mobile_cfg[block]; 420 best = 0; 421 best_val = INT_MAX; 422 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 423 if (strcmp(pdata->retune_mobile_cfgs[i].name, 424 wm8994->retune_mobile_texts[cfg]) == 0 && 425 abs(pdata->retune_mobile_cfgs[i].rate 426 - wm8994->dac_rates[iface]) < best_val) { 427 best = i; 428 best_val = abs(pdata->retune_mobile_cfgs[i].rate 429 - wm8994->dac_rates[iface]); 430 } 431 } 432 433 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 434 block, 435 pdata->retune_mobile_cfgs[best].name, 436 pdata->retune_mobile_cfgs[best].rate, 437 wm8994->dac_rates[iface]); 438 439 /* The EQ will be disabled while reconfiguring it, remember the 440 * current configuration. 441 */ 442 save = snd_soc_read(codec, base); 443 save &= WM8994_AIF1DAC1_EQ_ENA; 444 445 for (i = 0; i < WM8994_EQ_REGS; i++) 446 snd_soc_update_bits(codec, base + i, 0xffff, 447 pdata->retune_mobile_cfgs[best].regs[i]); 448 449 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 450 } 451 452 /* Icky as hell but saves code duplication */ 453 static int wm8994_get_retune_mobile_block(const char *name) 454 { 455 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 456 return 0; 457 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 458 return 1; 459 if (strcmp(name, "AIF2 EQ Mode") == 0) 460 return 2; 461 return -EINVAL; 462 } 463 464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 465 struct snd_ctl_elem_value *ucontrol) 466 { 467 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 469 struct wm8994 *control = wm8994->wm8994; 470 struct wm8994_pdata *pdata = &control->pdata; 471 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 472 int value = ucontrol->value.integer.value[0]; 473 474 if (block < 0) 475 return block; 476 477 if (value >= pdata->num_retune_mobile_cfgs) 478 return -EINVAL; 479 480 wm8994->retune_mobile_cfg[block] = value; 481 482 wm8994_set_retune_mobile(codec, block); 483 484 return 0; 485 } 486 487 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 488 struct snd_ctl_elem_value *ucontrol) 489 { 490 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 491 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 492 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 493 494 if (block < 0) 495 return block; 496 497 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 498 499 return 0; 500 } 501 502 static const char *aif_chan_src_text[] = { 503 "Left", "Right" 504 }; 505 506 static SOC_ENUM_SINGLE_DECL(aif1adcl_src, 507 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text); 508 509 static SOC_ENUM_SINGLE_DECL(aif1adcr_src, 510 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text); 511 512 static SOC_ENUM_SINGLE_DECL(aif2adcl_src, 513 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text); 514 515 static SOC_ENUM_SINGLE_DECL(aif2adcr_src, 516 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text); 517 518 static SOC_ENUM_SINGLE_DECL(aif1dacl_src, 519 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text); 520 521 static SOC_ENUM_SINGLE_DECL(aif1dacr_src, 522 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text); 523 524 static SOC_ENUM_SINGLE_DECL(aif2dacl_src, 525 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text); 526 527 static SOC_ENUM_SINGLE_DECL(aif2dacr_src, 528 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text); 529 530 static const char *osr_text[] = { 531 "Low Power", "High Performance", 532 }; 533 534 static SOC_ENUM_SINGLE_DECL(dac_osr, 535 WM8994_OVERSAMPLING, 0, osr_text); 536 537 static SOC_ENUM_SINGLE_DECL(adc_osr, 538 WM8994_OVERSAMPLING, 1, osr_text); 539 540 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 541 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 542 WM8994_AIF1_ADC1_RIGHT_VOLUME, 543 1, 119, 0, digital_tlv), 544 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 545 WM8994_AIF1_ADC2_RIGHT_VOLUME, 546 1, 119, 0, digital_tlv), 547 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 548 WM8994_AIF2_ADC_RIGHT_VOLUME, 549 1, 119, 0, digital_tlv), 550 551 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 552 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 553 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 554 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 555 556 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 557 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 558 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 559 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 560 561 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 562 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 563 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 564 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 565 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 566 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 567 568 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 569 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 570 571 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 572 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 573 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 574 575 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 576 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 577 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 578 579 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 580 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 581 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 582 583 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 584 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 585 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 586 587 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 588 5, 12, 0, st_tlv), 589 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 590 0, 12, 0, st_tlv), 591 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 592 5, 12, 0, st_tlv), 593 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 594 0, 12, 0, st_tlv), 595 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 596 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 597 598 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 599 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 600 601 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 602 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 603 604 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 605 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 606 607 SOC_ENUM("ADC OSR", adc_osr), 608 SOC_ENUM("DAC OSR", dac_osr), 609 610 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 611 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 612 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 613 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 614 615 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 616 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 617 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 618 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 619 620 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 621 6, 1, 1, wm_hubs_spkmix_tlv), 622 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 623 2, 1, 1, wm_hubs_spkmix_tlv), 624 625 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 626 6, 1, 1, wm_hubs_spkmix_tlv), 627 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 628 2, 1, 1, wm_hubs_spkmix_tlv), 629 630 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 631 10, 15, 0, wm8994_3d_tlv), 632 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 633 8, 1, 0), 634 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 635 10, 15, 0, wm8994_3d_tlv), 636 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 637 8, 1, 0), 638 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 639 10, 15, 0, wm8994_3d_tlv), 640 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 641 8, 1, 0), 642 }; 643 644 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 646 eq_tlv), 647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 648 eq_tlv), 649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 650 eq_tlv), 651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 652 eq_tlv), 653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 654 eq_tlv), 655 656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 659 eq_tlv), 660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 661 eq_tlv), 662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 663 eq_tlv), 664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 665 eq_tlv), 666 667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 670 eq_tlv), 671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 672 eq_tlv), 673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 674 eq_tlv), 675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 676 eq_tlv), 677 }; 678 679 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 681 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 682 WM8994_AIF1ADC1R_DRC_ENA), 683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 684 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 685 WM8994_AIF1ADC2R_DRC_ENA), 686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 687 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 688 WM8994_AIF2ADCR_DRC_ENA), 689 }; 690 691 static const char *wm8958_ng_text[] = { 692 "30ms", "125ms", "250ms", "500ms", 693 }; 694 695 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold, 696 WM8958_AIF1_DAC1_NOISE_GATE, 697 WM8958_AIF1DAC1_NG_THR_SHIFT, 698 wm8958_ng_text); 699 700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold, 701 WM8958_AIF1_DAC2_NOISE_GATE, 702 WM8958_AIF1DAC2_NG_THR_SHIFT, 703 wm8958_ng_text); 704 705 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold, 706 WM8958_AIF2_DAC_NOISE_GATE, 707 WM8958_AIF2DAC_NG_THR_SHIFT, 708 wm8958_ng_text); 709 710 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 711 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 712 713 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 714 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 715 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 716 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 717 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 718 7, 1, ng_tlv), 719 720 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 721 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 722 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 723 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 724 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 725 7, 1, ng_tlv), 726 727 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 728 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 729 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 730 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 731 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 732 7, 1, ng_tlv), 733 }; 734 735 static const struct snd_kcontrol_new wm1811_snd_controls[] = { 736 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, 737 mixin_boost_tlv), 738 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, 739 mixin_boost_tlv), 740 }; 741 742 /* We run all mode setting through a function to enforce audio mode */ 743 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode) 744 { 745 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 746 747 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 748 return; 749 750 if (wm8994->active_refcount) 751 mode = WM1811_JACKDET_MODE_AUDIO; 752 753 if (mode == wm8994->jackdet_mode) 754 return; 755 756 wm8994->jackdet_mode = mode; 757 758 /* Always use audio mode to detect while the system is active */ 759 if (mode != WM1811_JACKDET_MODE_NONE) 760 mode = WM1811_JACKDET_MODE_AUDIO; 761 762 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 763 WM1811_JACKDET_MODE_MASK, mode); 764 } 765 766 static void active_reference(struct snd_soc_codec *codec) 767 { 768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 769 770 mutex_lock(&wm8994->accdet_lock); 771 772 wm8994->active_refcount++; 773 774 dev_dbg(codec->dev, "Active refcount incremented, now %d\n", 775 wm8994->active_refcount); 776 777 /* If we're using jack detection go into audio mode */ 778 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO); 779 780 mutex_unlock(&wm8994->accdet_lock); 781 } 782 783 static void active_dereference(struct snd_soc_codec *codec) 784 { 785 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 786 u16 mode; 787 788 mutex_lock(&wm8994->accdet_lock); 789 790 wm8994->active_refcount--; 791 792 dev_dbg(codec->dev, "Active refcount decremented, now %d\n", 793 wm8994->active_refcount); 794 795 if (wm8994->active_refcount == 0) { 796 /* Go into appropriate detection only mode */ 797 if (wm8994->jack_mic || wm8994->mic_detecting) 798 mode = WM1811_JACKDET_MODE_MIC; 799 else 800 mode = WM1811_JACKDET_MODE_JACK; 801 802 wm1811_jackdet_set_mode(codec, mode); 803 } 804 805 mutex_unlock(&wm8994->accdet_lock); 806 } 807 808 static int clk_sys_event(struct snd_soc_dapm_widget *w, 809 struct snd_kcontrol *kcontrol, int event) 810 { 811 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 812 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 813 814 switch (event) { 815 case SND_SOC_DAPM_PRE_PMU: 816 return configure_clock(codec); 817 818 case SND_SOC_DAPM_POST_PMU: 819 /* 820 * JACKDET won't run until we start the clock and it 821 * only reports deltas, make sure we notify the state 822 * up the stack on startup. Use a *very* generous 823 * timeout for paranoia, there's no urgency and we 824 * don't want false reports. 825 */ 826 if (wm8994->jackdet && !wm8994->clk_has_run) { 827 queue_delayed_work(system_power_efficient_wq, 828 &wm8994->jackdet_bootstrap, 829 msecs_to_jiffies(1000)); 830 wm8994->clk_has_run = true; 831 } 832 break; 833 834 case SND_SOC_DAPM_POST_PMD: 835 configure_clock(codec); 836 break; 837 } 838 839 return 0; 840 } 841 842 static void vmid_reference(struct snd_soc_codec *codec) 843 { 844 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 845 846 pm_runtime_get_sync(codec->dev); 847 848 wm8994->vmid_refcount++; 849 850 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", 851 wm8994->vmid_refcount); 852 853 if (wm8994->vmid_refcount == 1) { 854 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 855 WM8994_LINEOUT1_DISCH | 856 WM8994_LINEOUT2_DISCH, 0); 857 858 wm_hubs_vmid_ena(codec); 859 860 switch (wm8994->vmid_mode) { 861 default: 862 WARN_ON(NULL == "Invalid VMID mode"); 863 case WM8994_VMID_NORMAL: 864 /* Startup bias, VMID ramp & buffer */ 865 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 866 WM8994_BIAS_SRC | 867 WM8994_VMID_DISCH | 868 WM8994_STARTUP_BIAS_ENA | 869 WM8994_VMID_BUF_ENA | 870 WM8994_VMID_RAMP_MASK, 871 WM8994_BIAS_SRC | 872 WM8994_STARTUP_BIAS_ENA | 873 WM8994_VMID_BUF_ENA | 874 (0x2 << WM8994_VMID_RAMP_SHIFT)); 875 876 /* Main bias enable, VMID=2x40k */ 877 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 878 WM8994_BIAS_ENA | 879 WM8994_VMID_SEL_MASK, 880 WM8994_BIAS_ENA | 0x2); 881 882 msleep(300); 883 884 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 885 WM8994_VMID_RAMP_MASK | 886 WM8994_BIAS_SRC, 887 0); 888 break; 889 890 case WM8994_VMID_FORCE: 891 /* Startup bias, slow VMID ramp & buffer */ 892 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 893 WM8994_BIAS_SRC | 894 WM8994_VMID_DISCH | 895 WM8994_STARTUP_BIAS_ENA | 896 WM8994_VMID_BUF_ENA | 897 WM8994_VMID_RAMP_MASK, 898 WM8994_BIAS_SRC | 899 WM8994_STARTUP_BIAS_ENA | 900 WM8994_VMID_BUF_ENA | 901 (0x2 << WM8994_VMID_RAMP_SHIFT)); 902 903 /* Main bias enable, VMID=2x40k */ 904 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 905 WM8994_BIAS_ENA | 906 WM8994_VMID_SEL_MASK, 907 WM8994_BIAS_ENA | 0x2); 908 909 msleep(400); 910 911 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 912 WM8994_VMID_RAMP_MASK | 913 WM8994_BIAS_SRC, 914 0); 915 break; 916 } 917 } 918 } 919 920 static void vmid_dereference(struct snd_soc_codec *codec) 921 { 922 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 923 924 wm8994->vmid_refcount--; 925 926 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", 927 wm8994->vmid_refcount); 928 929 if (wm8994->vmid_refcount == 0) { 930 if (wm8994->hubs.lineout1_se) 931 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 932 WM8994_LINEOUT1N_ENA | 933 WM8994_LINEOUT1P_ENA, 934 WM8994_LINEOUT1N_ENA | 935 WM8994_LINEOUT1P_ENA); 936 937 if (wm8994->hubs.lineout2_se) 938 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 939 WM8994_LINEOUT2N_ENA | 940 WM8994_LINEOUT2P_ENA, 941 WM8994_LINEOUT2N_ENA | 942 WM8994_LINEOUT2P_ENA); 943 944 /* Start discharging VMID */ 945 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 946 WM8994_BIAS_SRC | 947 WM8994_VMID_DISCH, 948 WM8994_BIAS_SRC | 949 WM8994_VMID_DISCH); 950 951 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 952 WM8994_VMID_SEL_MASK, 0); 953 954 msleep(400); 955 956 /* Active discharge */ 957 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 958 WM8994_LINEOUT1_DISCH | 959 WM8994_LINEOUT2_DISCH, 960 WM8994_LINEOUT1_DISCH | 961 WM8994_LINEOUT2_DISCH); 962 963 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 964 WM8994_LINEOUT1N_ENA | 965 WM8994_LINEOUT1P_ENA | 966 WM8994_LINEOUT2N_ENA | 967 WM8994_LINEOUT2P_ENA, 0); 968 969 /* Switch off startup biases */ 970 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 971 WM8994_BIAS_SRC | 972 WM8994_STARTUP_BIAS_ENA | 973 WM8994_VMID_BUF_ENA | 974 WM8994_VMID_RAMP_MASK, 0); 975 976 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 977 WM8994_VMID_SEL_MASK, 0); 978 } 979 980 pm_runtime_put(codec->dev); 981 } 982 983 static int vmid_event(struct snd_soc_dapm_widget *w, 984 struct snd_kcontrol *kcontrol, int event) 985 { 986 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 987 988 switch (event) { 989 case SND_SOC_DAPM_PRE_PMU: 990 vmid_reference(codec); 991 break; 992 993 case SND_SOC_DAPM_POST_PMD: 994 vmid_dereference(codec); 995 break; 996 } 997 998 return 0; 999 } 1000 1001 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec) 1002 { 1003 int source = 0; /* GCC flow analysis can't track enable */ 1004 int reg, reg_r; 1005 1006 /* We also need the same AIF source for L/R and only one path */ 1007 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 1008 switch (reg) { 1009 case WM8994_AIF2DACL_TO_DAC1L: 1010 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 1011 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1012 break; 1013 case WM8994_AIF1DAC2L_TO_DAC1L: 1014 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 1015 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1016 break; 1017 case WM8994_AIF1DAC1L_TO_DAC1L: 1018 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 1019 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1020 break; 1021 default: 1022 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 1023 return false; 1024 } 1025 1026 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1027 if (reg_r != reg) { 1028 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 1029 return false; 1030 } 1031 1032 /* Set the source up */ 1033 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1034 WM8994_CP_DYN_SRC_SEL_MASK, source); 1035 1036 return true; 1037 } 1038 1039 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1040 struct snd_kcontrol *kcontrol, int event) 1041 { 1042 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1043 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1044 struct wm8994 *control = wm8994->wm8994; 1045 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1046 int i; 1047 int dac; 1048 int adc; 1049 int val; 1050 1051 switch (control->type) { 1052 case WM8994: 1053 case WM8958: 1054 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1055 break; 1056 default: 1057 break; 1058 } 1059 1060 switch (event) { 1061 case SND_SOC_DAPM_PRE_PMU: 1062 /* Don't enable timeslot 2 if not in use */ 1063 if (wm8994->channels[0] <= 2) 1064 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1065 1066 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1); 1067 if ((val & WM8994_AIF1ADCL_SRC) && 1068 (val & WM8994_AIF1ADCR_SRC)) 1069 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1070 else if (!(val & WM8994_AIF1ADCL_SRC) && 1071 !(val & WM8994_AIF1ADCR_SRC)) 1072 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1073 else 1074 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1075 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1076 1077 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2); 1078 if ((val & WM8994_AIF1DACL_SRC) && 1079 (val & WM8994_AIF1DACR_SRC)) 1080 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1081 else if (!(val & WM8994_AIF1DACL_SRC) && 1082 !(val & WM8994_AIF1DACR_SRC)) 1083 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1084 else 1085 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1086 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1087 1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1089 mask, adc); 1090 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1091 mask, dac); 1092 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1093 WM8994_AIF1DSPCLK_ENA | 1094 WM8994_SYSDSPCLK_ENA, 1095 WM8994_AIF1DSPCLK_ENA | 1096 WM8994_SYSDSPCLK_ENA); 1097 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask, 1098 WM8994_AIF1ADC1R_ENA | 1099 WM8994_AIF1ADC1L_ENA | 1100 WM8994_AIF1ADC2R_ENA | 1101 WM8994_AIF1ADC2L_ENA); 1102 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask, 1103 WM8994_AIF1DAC1R_ENA | 1104 WM8994_AIF1DAC1L_ENA | 1105 WM8994_AIF1DAC2R_ENA | 1106 WM8994_AIF1DAC2L_ENA); 1107 break; 1108 1109 case SND_SOC_DAPM_POST_PMU: 1110 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1111 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1112 snd_soc_read(codec, 1113 wm8994_vu_bits[i].reg)); 1114 break; 1115 1116 case SND_SOC_DAPM_PRE_PMD: 1117 case SND_SOC_DAPM_POST_PMD: 1118 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1119 mask, 0); 1120 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1121 mask, 0); 1122 1123 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1124 if (val & WM8994_AIF2DSPCLK_ENA) 1125 val = WM8994_SYSDSPCLK_ENA; 1126 else 1127 val = 0; 1128 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1129 WM8994_SYSDSPCLK_ENA | 1130 WM8994_AIF1DSPCLK_ENA, val); 1131 break; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1138 struct snd_kcontrol *kcontrol, int event) 1139 { 1140 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1141 int i; 1142 int dac; 1143 int adc; 1144 int val; 1145 1146 switch (event) { 1147 case SND_SOC_DAPM_PRE_PMU: 1148 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1); 1149 if ((val & WM8994_AIF2ADCL_SRC) && 1150 (val & WM8994_AIF2ADCR_SRC)) 1151 adc = WM8994_AIF2ADCR_ENA; 1152 else if (!(val & WM8994_AIF2ADCL_SRC) && 1153 !(val & WM8994_AIF2ADCR_SRC)) 1154 adc = WM8994_AIF2ADCL_ENA; 1155 else 1156 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1157 1158 1159 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2); 1160 if ((val & WM8994_AIF2DACL_SRC) && 1161 (val & WM8994_AIF2DACR_SRC)) 1162 dac = WM8994_AIF2DACR_ENA; 1163 else if (!(val & WM8994_AIF2DACL_SRC) && 1164 !(val & WM8994_AIF2DACR_SRC)) 1165 dac = WM8994_AIF2DACL_ENA; 1166 else 1167 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1168 1169 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1170 WM8994_AIF2ADCL_ENA | 1171 WM8994_AIF2ADCR_ENA, adc); 1172 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1173 WM8994_AIF2DACL_ENA | 1174 WM8994_AIF2DACR_ENA, dac); 1175 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1176 WM8994_AIF2DSPCLK_ENA | 1177 WM8994_SYSDSPCLK_ENA, 1178 WM8994_AIF2DSPCLK_ENA | 1179 WM8994_SYSDSPCLK_ENA); 1180 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1181 WM8994_AIF2ADCL_ENA | 1182 WM8994_AIF2ADCR_ENA, 1183 WM8994_AIF2ADCL_ENA | 1184 WM8994_AIF2ADCR_ENA); 1185 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1186 WM8994_AIF2DACL_ENA | 1187 WM8994_AIF2DACR_ENA, 1188 WM8994_AIF2DACL_ENA | 1189 WM8994_AIF2DACR_ENA); 1190 break; 1191 1192 case SND_SOC_DAPM_POST_PMU: 1193 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1194 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1195 snd_soc_read(codec, 1196 wm8994_vu_bits[i].reg)); 1197 break; 1198 1199 case SND_SOC_DAPM_PRE_PMD: 1200 case SND_SOC_DAPM_POST_PMD: 1201 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1202 WM8994_AIF2DACL_ENA | 1203 WM8994_AIF2DACR_ENA, 0); 1204 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1205 WM8994_AIF2ADCL_ENA | 1206 WM8994_AIF2ADCR_ENA, 0); 1207 1208 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1209 if (val & WM8994_AIF1DSPCLK_ENA) 1210 val = WM8994_SYSDSPCLK_ENA; 1211 else 1212 val = 0; 1213 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1214 WM8994_SYSDSPCLK_ENA | 1215 WM8994_AIF2DSPCLK_ENA, val); 1216 break; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1223 struct snd_kcontrol *kcontrol, int event) 1224 { 1225 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1226 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1227 1228 switch (event) { 1229 case SND_SOC_DAPM_PRE_PMU: 1230 wm8994->aif1clk_enable = 1; 1231 break; 1232 case SND_SOC_DAPM_POST_PMD: 1233 wm8994->aif1clk_disable = 1; 1234 break; 1235 } 1236 1237 return 0; 1238 } 1239 1240 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1241 struct snd_kcontrol *kcontrol, int event) 1242 { 1243 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1244 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1245 1246 switch (event) { 1247 case SND_SOC_DAPM_PRE_PMU: 1248 wm8994->aif2clk_enable = 1; 1249 break; 1250 case SND_SOC_DAPM_POST_PMD: 1251 wm8994->aif2clk_disable = 1; 1252 break; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1259 struct snd_kcontrol *kcontrol, int event) 1260 { 1261 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1262 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1263 1264 switch (event) { 1265 case SND_SOC_DAPM_PRE_PMU: 1266 if (wm8994->aif1clk_enable) { 1267 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1268 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1269 WM8994_AIF1CLK_ENA_MASK, 1270 WM8994_AIF1CLK_ENA); 1271 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1272 wm8994->aif1clk_enable = 0; 1273 } 1274 if (wm8994->aif2clk_enable) { 1275 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1276 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1277 WM8994_AIF2CLK_ENA_MASK, 1278 WM8994_AIF2CLK_ENA); 1279 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1280 wm8994->aif2clk_enable = 0; 1281 } 1282 break; 1283 } 1284 1285 /* We may also have postponed startup of DSP, handle that. */ 1286 wm8958_aif_ev(w, kcontrol, event); 1287 1288 return 0; 1289 } 1290 1291 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1292 struct snd_kcontrol *kcontrol, int event) 1293 { 1294 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1295 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1296 1297 switch (event) { 1298 case SND_SOC_DAPM_POST_PMD: 1299 if (wm8994->aif1clk_disable) { 1300 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1301 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1302 WM8994_AIF1CLK_ENA_MASK, 0); 1303 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1304 wm8994->aif1clk_disable = 0; 1305 } 1306 if (wm8994->aif2clk_disable) { 1307 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1308 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1309 WM8994_AIF2CLK_ENA_MASK, 0); 1310 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1311 wm8994->aif2clk_disable = 0; 1312 } 1313 break; 1314 } 1315 1316 return 0; 1317 } 1318 1319 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1320 struct snd_kcontrol *kcontrol, int event) 1321 { 1322 late_enable_ev(w, kcontrol, event); 1323 return 0; 1324 } 1325 1326 static int micbias_ev(struct snd_soc_dapm_widget *w, 1327 struct snd_kcontrol *kcontrol, int event) 1328 { 1329 late_enable_ev(w, kcontrol, event); 1330 return 0; 1331 } 1332 1333 static int dac_ev(struct snd_soc_dapm_widget *w, 1334 struct snd_kcontrol *kcontrol, int event) 1335 { 1336 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1337 unsigned int mask = 1 << w->shift; 1338 1339 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1340 mask, mask); 1341 return 0; 1342 } 1343 1344 static const char *adc_mux_text[] = { 1345 "ADC", 1346 "DMIC", 1347 }; 1348 1349 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 1350 1351 static const struct snd_kcontrol_new adcl_mux = 1352 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 1353 1354 static const struct snd_kcontrol_new adcr_mux = 1355 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 1356 1357 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1358 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1359 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1360 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1361 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1362 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1363 }; 1364 1365 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1366 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1367 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1368 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1369 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1370 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1371 }; 1372 1373 /* Debugging; dump chip status after DAPM transitions */ 1374 static int post_ev(struct snd_soc_dapm_widget *w, 1375 struct snd_kcontrol *kcontrol, int event) 1376 { 1377 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1378 dev_dbg(codec->dev, "SRC status: %x\n", 1379 snd_soc_read(codec, 1380 WM8994_RATE_STATUS)); 1381 return 0; 1382 } 1383 1384 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1385 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1386 1, 1, 0), 1387 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1388 0, 1, 0), 1389 }; 1390 1391 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1392 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1393 1, 1, 0), 1394 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1395 0, 1, 0), 1396 }; 1397 1398 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1399 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1400 1, 1, 0), 1401 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1402 0, 1, 0), 1403 }; 1404 1405 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1406 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1407 1, 1, 0), 1408 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1409 0, 1, 0), 1410 }; 1411 1412 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1413 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1414 5, 1, 0), 1415 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1416 4, 1, 0), 1417 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1418 2, 1, 0), 1419 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1420 1, 1, 0), 1421 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1422 0, 1, 0), 1423 }; 1424 1425 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1426 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1427 5, 1, 0), 1428 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1429 4, 1, 0), 1430 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1431 2, 1, 0), 1432 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1433 1, 1, 0), 1434 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1435 0, 1, 0), 1436 }; 1437 1438 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1439 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 1440 snd_soc_dapm_get_volsw, wm8994_put_class_w) 1441 1442 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1443 struct snd_ctl_elem_value *ucontrol) 1444 { 1445 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 1446 int ret; 1447 1448 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1449 1450 wm_hubs_update_class_w(codec); 1451 1452 return ret; 1453 } 1454 1455 static const struct snd_kcontrol_new dac1l_mix[] = { 1456 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1457 5, 1, 0), 1458 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1459 4, 1, 0), 1460 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1461 2, 1, 0), 1462 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1463 1, 1, 0), 1464 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1465 0, 1, 0), 1466 }; 1467 1468 static const struct snd_kcontrol_new dac1r_mix[] = { 1469 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1470 5, 1, 0), 1471 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1472 4, 1, 0), 1473 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1474 2, 1, 0), 1475 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1476 1, 1, 0), 1477 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1478 0, 1, 0), 1479 }; 1480 1481 static const char *sidetone_text[] = { 1482 "ADC/DMIC1", "DMIC2", 1483 }; 1484 1485 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, 1486 WM8994_SIDETONE, 0, sidetone_text); 1487 1488 static const struct snd_kcontrol_new sidetone1_mux = 1489 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1490 1491 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, 1492 WM8994_SIDETONE, 1, sidetone_text); 1493 1494 static const struct snd_kcontrol_new sidetone2_mux = 1495 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1496 1497 static const char *aif1dac_text[] = { 1498 "AIF1DACDAT", "AIF3DACDAT", 1499 }; 1500 1501 static const char *loopback_text[] = { 1502 "None", "ADCDAT", 1503 }; 1504 1505 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum, 1506 WM8994_AIF1_CONTROL_2, 1507 WM8994_AIF1_LOOPBACK_SHIFT, 1508 loopback_text); 1509 1510 static const struct snd_kcontrol_new aif1_loopback = 1511 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum); 1512 1513 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum, 1514 WM8994_AIF2_CONTROL_2, 1515 WM8994_AIF2_LOOPBACK_SHIFT, 1516 loopback_text); 1517 1518 static const struct snd_kcontrol_new aif2_loopback = 1519 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum); 1520 1521 static SOC_ENUM_SINGLE_DECL(aif1dac_enum, 1522 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text); 1523 1524 static const struct snd_kcontrol_new aif1dac_mux = 1525 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1526 1527 static const char *aif2dac_text[] = { 1528 "AIF2DACDAT", "AIF3DACDAT", 1529 }; 1530 1531 static SOC_ENUM_SINGLE_DECL(aif2dac_enum, 1532 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text); 1533 1534 static const struct snd_kcontrol_new aif2dac_mux = 1535 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1536 1537 static const char *aif2adc_text[] = { 1538 "AIF2ADCDAT", "AIF3DACDAT", 1539 }; 1540 1541 static SOC_ENUM_SINGLE_DECL(aif2adc_enum, 1542 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text); 1543 1544 static const struct snd_kcontrol_new aif2adc_mux = 1545 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1546 1547 static const char *aif3adc_text[] = { 1548 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1549 }; 1550 1551 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum, 1552 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1553 1554 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1555 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1556 1557 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum, 1558 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1559 1560 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1561 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1562 1563 static const char *mono_pcm_out_text[] = { 1564 "None", "AIF2ADCL", "AIF2ADCR", 1565 }; 1566 1567 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum, 1568 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text); 1569 1570 static const struct snd_kcontrol_new mono_pcm_out_mux = 1571 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1572 1573 static const char *aif2dac_src_text[] = { 1574 "AIF2", "AIF3", 1575 }; 1576 1577 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1578 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum, 1579 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text); 1580 1581 static const struct snd_kcontrol_new aif2dacl_src_mux = 1582 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1583 1584 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum, 1585 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text); 1586 1587 static const struct snd_kcontrol_new aif2dacr_src_mux = 1588 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1589 1590 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1591 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1592 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1593 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1595 1596 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1597 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1598 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1599 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1600 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1601 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1602 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1603 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1604 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1605 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1606 1607 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1608 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1609 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1610 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1611 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1612 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1613 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1614 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1615 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1616 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1617 1618 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1619 }; 1620 1621 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1622 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1624 SND_SOC_DAPM_PRE_PMD), 1625 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1627 SND_SOC_DAPM_PRE_PMD), 1628 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1629 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1630 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1631 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1632 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1633 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1634 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1635 }; 1636 1637 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1638 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1639 dac_ev, SND_SOC_DAPM_PRE_PMU), 1640 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1641 dac_ev, SND_SOC_DAPM_PRE_PMU), 1642 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1643 dac_ev, SND_SOC_DAPM_PRE_PMU), 1644 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1645 dac_ev, SND_SOC_DAPM_PRE_PMU), 1646 }; 1647 1648 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1649 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1650 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1651 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1652 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1653 }; 1654 1655 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1656 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1657 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1658 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1659 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1660 }; 1661 1662 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1663 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1664 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1665 }; 1666 1667 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1668 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1669 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1670 SND_SOC_DAPM_INPUT("Clock"), 1671 1672 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1673 SND_SOC_DAPM_PRE_PMU), 1674 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1676 1677 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1679 SND_SOC_DAPM_PRE_PMD), 1680 1681 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1682 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1683 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1684 1685 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1686 0, SND_SOC_NOPM, 9, 0), 1687 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1688 0, SND_SOC_NOPM, 8, 0), 1689 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1690 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1691 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1692 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1693 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1694 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1695 1696 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1697 0, SND_SOC_NOPM, 11, 0), 1698 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1699 0, SND_SOC_NOPM, 10, 0), 1700 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1701 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1702 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1703 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1704 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1705 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1706 1707 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1708 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1709 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1710 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1711 1712 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1713 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1714 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1715 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1716 1717 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1718 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1719 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1720 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1721 1722 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1723 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1724 1725 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1726 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1727 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1728 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1729 1730 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1731 SND_SOC_NOPM, 13, 0), 1732 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1733 SND_SOC_NOPM, 12, 0), 1734 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1735 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1736 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1737 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1738 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1739 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1740 1741 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1742 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1743 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1744 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1745 1746 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1747 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1748 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1749 1750 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1751 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1752 1753 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1754 1755 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1756 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1757 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1758 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1759 1760 /* Power is done with the muxes since the ADC power also controls the 1761 * downsampling chain, the chip will automatically manage the analogue 1762 * specific portions. 1763 */ 1764 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1765 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1766 1767 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback), 1768 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback), 1769 1770 SND_SOC_DAPM_POST("Debug log", post_ev), 1771 }; 1772 1773 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1774 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1775 }; 1776 1777 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1778 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1779 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1780 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1781 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1782 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1783 }; 1784 1785 static const struct snd_soc_dapm_route intercon[] = { 1786 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1787 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1788 1789 { "DSP1CLK", NULL, "CLK_SYS" }, 1790 { "DSP2CLK", NULL, "CLK_SYS" }, 1791 { "DSPINTCLK", NULL, "CLK_SYS" }, 1792 1793 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1794 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1795 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1796 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1797 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1798 1799 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1800 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1801 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1802 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1803 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1804 1805 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1806 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1807 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1808 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1809 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1810 1811 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1812 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1813 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1814 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1815 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1816 1817 { "AIF2ADCL", NULL, "AIF2CLK" }, 1818 { "AIF2ADCL", NULL, "DSP2CLK" }, 1819 { "AIF2ADCR", NULL, "AIF2CLK" }, 1820 { "AIF2ADCR", NULL, "DSP2CLK" }, 1821 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1822 1823 { "AIF2DACL", NULL, "AIF2CLK" }, 1824 { "AIF2DACL", NULL, "DSP2CLK" }, 1825 { "AIF2DACR", NULL, "AIF2CLK" }, 1826 { "AIF2DACR", NULL, "DSP2CLK" }, 1827 { "AIF2DACR", NULL, "DSPINTCLK" }, 1828 1829 { "DMIC1L", NULL, "DMIC1DAT" }, 1830 { "DMIC1L", NULL, "CLK_SYS" }, 1831 { "DMIC1R", NULL, "DMIC1DAT" }, 1832 { "DMIC1R", NULL, "CLK_SYS" }, 1833 { "DMIC2L", NULL, "DMIC2DAT" }, 1834 { "DMIC2L", NULL, "CLK_SYS" }, 1835 { "DMIC2R", NULL, "DMIC2DAT" }, 1836 { "DMIC2R", NULL, "CLK_SYS" }, 1837 1838 { "ADCL", NULL, "AIF1CLK" }, 1839 { "ADCL", NULL, "DSP1CLK" }, 1840 { "ADCL", NULL, "DSPINTCLK" }, 1841 1842 { "ADCR", NULL, "AIF1CLK" }, 1843 { "ADCR", NULL, "DSP1CLK" }, 1844 { "ADCR", NULL, "DSPINTCLK" }, 1845 1846 { "ADCL Mux", "ADC", "ADCL" }, 1847 { "ADCL Mux", "DMIC", "DMIC1L" }, 1848 { "ADCR Mux", "ADC", "ADCR" }, 1849 { "ADCR Mux", "DMIC", "DMIC1R" }, 1850 1851 { "DAC1L", NULL, "AIF1CLK" }, 1852 { "DAC1L", NULL, "DSP1CLK" }, 1853 { "DAC1L", NULL, "DSPINTCLK" }, 1854 1855 { "DAC1R", NULL, "AIF1CLK" }, 1856 { "DAC1R", NULL, "DSP1CLK" }, 1857 { "DAC1R", NULL, "DSPINTCLK" }, 1858 1859 { "DAC2L", NULL, "AIF2CLK" }, 1860 { "DAC2L", NULL, "DSP2CLK" }, 1861 { "DAC2L", NULL, "DSPINTCLK" }, 1862 1863 { "DAC2R", NULL, "AIF2DACR" }, 1864 { "DAC2R", NULL, "AIF2CLK" }, 1865 { "DAC2R", NULL, "DSP2CLK" }, 1866 { "DAC2R", NULL, "DSPINTCLK" }, 1867 1868 { "TOCLK", NULL, "CLK_SYS" }, 1869 1870 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1871 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1872 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1873 1874 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1875 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1876 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1877 1878 /* AIF1 outputs */ 1879 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1880 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1881 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1882 1883 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1884 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1885 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1886 1887 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1888 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1889 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1890 1891 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1892 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1893 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1894 1895 /* Pin level routing for AIF3 */ 1896 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1897 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1898 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1899 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1900 1901 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" }, 1902 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1903 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" }, 1904 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1906 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1907 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1908 1909 /* DAC1 inputs */ 1910 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1911 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1912 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1913 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1914 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1915 1916 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1917 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1918 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1919 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1920 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1921 1922 /* DAC2/AIF2 outputs */ 1923 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1924 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1925 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1926 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1927 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1928 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1929 1930 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1931 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1932 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1933 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1934 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1935 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1936 1937 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1938 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1939 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1940 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1941 1942 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1943 1944 /* AIF3 output */ 1945 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" }, 1946 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" }, 1947 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" }, 1948 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" }, 1949 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1950 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1951 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" }, 1952 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" }, 1953 1954 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" }, 1955 1956 /* Loopback */ 1957 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" }, 1958 { "AIF1 Loopback", "None", "AIF1DACDAT" }, 1959 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" }, 1960 { "AIF2 Loopback", "None", "AIF2DACDAT" }, 1961 1962 /* Sidetone */ 1963 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1964 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1965 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1966 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1967 1968 /* Output stages */ 1969 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1970 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1971 1972 { "SPKL", "DAC1 Switch", "DAC1L" }, 1973 { "SPKL", "DAC2 Switch", "DAC2L" }, 1974 1975 { "SPKR", "DAC1 Switch", "DAC1R" }, 1976 { "SPKR", "DAC2 Switch", "DAC2R" }, 1977 1978 { "Left Headphone Mux", "DAC", "DAC1L" }, 1979 { "Right Headphone Mux", "DAC", "DAC1R" }, 1980 }; 1981 1982 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1983 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1984 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1985 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1986 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1987 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1988 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1989 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1990 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1991 }; 1992 1993 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1994 { "DAC1L", NULL, "DAC1L Mixer" }, 1995 { "DAC1R", NULL, "DAC1R Mixer" }, 1996 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1997 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1998 }; 1999 2000 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 2001 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 2002 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 2003 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 2004 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 2005 { "MICBIAS1", NULL, "CLK_SYS" }, 2006 { "MICBIAS1", NULL, "MICBIAS Supply" }, 2007 { "MICBIAS2", NULL, "CLK_SYS" }, 2008 { "MICBIAS2", NULL, "MICBIAS Supply" }, 2009 }; 2010 2011 static const struct snd_soc_dapm_route wm8994_intercon[] = { 2012 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2013 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2014 { "MICBIAS1", NULL, "VMID" }, 2015 { "MICBIAS2", NULL, "VMID" }, 2016 }; 2017 2018 static const struct snd_soc_dapm_route wm8958_intercon[] = { 2019 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 2020 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 2021 2022 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 2023 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 2024 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 2025 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 2026 2027 { "AIF3DACDAT", NULL, "AIF3" }, 2028 { "AIF3ADCDAT", NULL, "AIF3" }, 2029 2030 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2031 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2032 2033 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2034 }; 2035 2036 /* The size in bits of the FLL divide multiplied by 10 2037 * to allow rounding later */ 2038 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2039 2040 struct fll_div { 2041 u16 outdiv; 2042 u16 n; 2043 u16 k; 2044 u16 lambda; 2045 u16 clk_ref_div; 2046 u16 fll_fratio; 2047 }; 2048 2049 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll, 2050 int freq_in, int freq_out) 2051 { 2052 u64 Kpart; 2053 unsigned int K, Ndiv, Nmod, gcd_fll; 2054 2055 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2056 2057 /* Scale the input frequency down to <= 13.5MHz */ 2058 fll->clk_ref_div = 0; 2059 while (freq_in > 13500000) { 2060 fll->clk_ref_div++; 2061 freq_in /= 2; 2062 2063 if (fll->clk_ref_div > 3) 2064 return -EINVAL; 2065 } 2066 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2067 2068 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2069 fll->outdiv = 3; 2070 while (freq_out * (fll->outdiv + 1) < 90000000) { 2071 fll->outdiv++; 2072 if (fll->outdiv > 63) 2073 return -EINVAL; 2074 } 2075 freq_out *= fll->outdiv + 1; 2076 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2077 2078 if (freq_in > 1000000) { 2079 fll->fll_fratio = 0; 2080 } else if (freq_in > 256000) { 2081 fll->fll_fratio = 1; 2082 freq_in *= 2; 2083 } else if (freq_in > 128000) { 2084 fll->fll_fratio = 2; 2085 freq_in *= 4; 2086 } else if (freq_in > 64000) { 2087 fll->fll_fratio = 3; 2088 freq_in *= 8; 2089 } else { 2090 fll->fll_fratio = 4; 2091 freq_in *= 16; 2092 } 2093 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2094 2095 /* Now, calculate N.K */ 2096 Ndiv = freq_out / freq_in; 2097 2098 fll->n = Ndiv; 2099 Nmod = freq_out % freq_in; 2100 pr_debug("Nmod=%d\n", Nmod); 2101 2102 switch (control->type) { 2103 case WM8994: 2104 /* Calculate fractional part - scale up so we can round. */ 2105 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2106 2107 do_div(Kpart, freq_in); 2108 2109 K = Kpart & 0xFFFFFFFF; 2110 2111 if ((K % 10) >= 5) 2112 K += 5; 2113 2114 /* Move down to proper range now rounding is done */ 2115 fll->k = K / 10; 2116 fll->lambda = 0; 2117 2118 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2119 break; 2120 2121 default: 2122 gcd_fll = gcd(freq_out, freq_in); 2123 2124 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; 2125 fll->lambda = freq_in / gcd_fll; 2126 2127 } 2128 2129 return 0; 2130 } 2131 2132 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 2133 unsigned int freq_in, unsigned int freq_out) 2134 { 2135 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2136 struct wm8994 *control = wm8994->wm8994; 2137 int reg_offset, ret; 2138 struct fll_div fll; 2139 u16 reg, clk1, aif_reg, aif_src; 2140 unsigned long timeout; 2141 bool was_enabled; 2142 2143 switch (id) { 2144 case WM8994_FLL1: 2145 reg_offset = 0; 2146 id = 0; 2147 aif_src = 0x10; 2148 break; 2149 case WM8994_FLL2: 2150 reg_offset = 0x20; 2151 id = 1; 2152 aif_src = 0x18; 2153 break; 2154 default: 2155 return -EINVAL; 2156 } 2157 2158 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); 2159 was_enabled = reg & WM8994_FLL1_ENA; 2160 2161 switch (src) { 2162 case 0: 2163 /* Allow no source specification when stopping */ 2164 if (freq_out) 2165 return -EINVAL; 2166 src = wm8994->fll[id].src; 2167 break; 2168 case WM8994_FLL_SRC_MCLK1: 2169 case WM8994_FLL_SRC_MCLK2: 2170 case WM8994_FLL_SRC_LRCLK: 2171 case WM8994_FLL_SRC_BCLK: 2172 break; 2173 case WM8994_FLL_SRC_INTERNAL: 2174 freq_in = 12000000; 2175 freq_out = 12000000; 2176 break; 2177 default: 2178 return -EINVAL; 2179 } 2180 2181 /* Are we changing anything? */ 2182 if (wm8994->fll[id].src == src && 2183 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2184 return 0; 2185 2186 /* If we're stopping the FLL redo the old config - no 2187 * registers will actually be written but we avoid GCC flow 2188 * analysis bugs spewing warnings. 2189 */ 2190 if (freq_out) 2191 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out); 2192 else 2193 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in, 2194 wm8994->fll[id].out); 2195 if (ret < 0) 2196 return ret; 2197 2198 /* Make sure that we're not providing SYSCLK right now */ 2199 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1); 2200 if (clk1 & WM8994_SYSCLK_SRC) 2201 aif_reg = WM8994_AIF2_CLOCKING_1; 2202 else 2203 aif_reg = WM8994_AIF1_CLOCKING_1; 2204 reg = snd_soc_read(codec, aif_reg); 2205 2206 if ((reg & WM8994_AIF1CLK_ENA) && 2207 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2208 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n", 2209 id + 1); 2210 return -EBUSY; 2211 } 2212 2213 /* We always need to disable the FLL while reconfiguring */ 2214 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2215 WM8994_FLL1_ENA, 0); 2216 2217 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2218 freq_in == freq_out && freq_out) { 2219 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1); 2220 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2221 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2222 goto out; 2223 } 2224 2225 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2226 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2228 WM8994_FLL1_OUTDIV_MASK | 2229 WM8994_FLL1_FRATIO_MASK, reg); 2230 2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, 2232 WM8994_FLL1_K_MASK, fll.k); 2233 2234 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 2235 WM8994_FLL1_N_MASK, 2236 fll.n << WM8994_FLL1_N_SHIFT); 2237 2238 if (fll.lambda) { 2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset, 2240 WM8958_FLL1_LAMBDA_MASK, 2241 fll.lambda); 2242 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset, 2243 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA); 2244 } else { 2245 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset, 2246 WM8958_FLL1_EFS_ENA, 0); 2247 } 2248 2249 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2250 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2251 WM8994_FLL1_REFCLK_DIV_MASK | 2252 WM8994_FLL1_REFCLK_SRC_MASK, 2253 ((src == WM8994_FLL_SRC_INTERNAL) 2254 << WM8994_FLL1_FRC_NCO_SHIFT) | 2255 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2256 (src - 1)); 2257 2258 /* Clear any pending completion from a previous failure */ 2259 try_wait_for_completion(&wm8994->fll_locked[id]); 2260 2261 /* Enable (with fractional mode if required) */ 2262 if (freq_out) { 2263 /* Enable VMID if we need it */ 2264 if (!was_enabled) { 2265 active_reference(codec); 2266 2267 switch (control->type) { 2268 case WM8994: 2269 vmid_reference(codec); 2270 break; 2271 case WM8958: 2272 if (control->revision < 1) 2273 vmid_reference(codec); 2274 break; 2275 default: 2276 break; 2277 } 2278 } 2279 2280 reg = WM8994_FLL1_ENA; 2281 2282 if (fll.k) 2283 reg |= WM8994_FLL1_FRAC; 2284 if (src == WM8994_FLL_SRC_INTERNAL) 2285 reg |= WM8994_FLL1_OSC_ENA; 2286 2287 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2288 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2289 WM8994_FLL1_FRAC, reg); 2290 2291 if (wm8994->fll_locked_irq) { 2292 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2293 msecs_to_jiffies(10)); 2294 if (timeout == 0) 2295 dev_warn(codec->dev, 2296 "Timed out waiting for FLL lock\n"); 2297 } else { 2298 msleep(5); 2299 } 2300 } else { 2301 if (was_enabled) { 2302 switch (control->type) { 2303 case WM8994: 2304 vmid_dereference(codec); 2305 break; 2306 case WM8958: 2307 if (control->revision < 1) 2308 vmid_dereference(codec); 2309 break; 2310 default: 2311 break; 2312 } 2313 2314 active_dereference(codec); 2315 } 2316 } 2317 2318 out: 2319 wm8994->fll[id].in = freq_in; 2320 wm8994->fll[id].out = freq_out; 2321 wm8994->fll[id].src = src; 2322 2323 configure_clock(codec); 2324 2325 /* 2326 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2327 * for detection. 2328 */ 2329 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2330 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2331 2332 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) 2333 & WM8994_AIF1CLK_RATE_MASK; 2334 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) 2335 & WM8994_AIF1CLK_RATE_MASK; 2336 2337 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2338 WM8994_AIF1CLK_RATE_MASK, 0x1); 2339 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2340 WM8994_AIF2CLK_RATE_MASK, 0x1); 2341 } else if (wm8994->aifdiv[0]) { 2342 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2343 WM8994_AIF1CLK_RATE_MASK, 2344 wm8994->aifdiv[0]); 2345 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2346 WM8994_AIF2CLK_RATE_MASK, 2347 wm8994->aifdiv[1]); 2348 2349 wm8994->aifdiv[0] = 0; 2350 wm8994->aifdiv[1] = 0; 2351 } 2352 2353 return 0; 2354 } 2355 2356 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2357 { 2358 struct completion *completion = data; 2359 2360 complete(completion); 2361 2362 return IRQ_HANDLED; 2363 } 2364 2365 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2366 2367 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2368 unsigned int freq_in, unsigned int freq_out) 2369 { 2370 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 2371 } 2372 2373 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2374 int clk_id, unsigned int freq, int dir) 2375 { 2376 struct snd_soc_codec *codec = dai->codec; 2377 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2378 int i; 2379 2380 switch (dai->id) { 2381 case 1: 2382 case 2: 2383 break; 2384 2385 default: 2386 /* AIF3 shares clocking with AIF1/2 */ 2387 return -EINVAL; 2388 } 2389 2390 switch (clk_id) { 2391 case WM8994_SYSCLK_MCLK1: 2392 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2393 wm8994->mclk[0] = freq; 2394 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2395 dai->id, freq); 2396 break; 2397 2398 case WM8994_SYSCLK_MCLK2: 2399 /* TODO: Set GPIO AF */ 2400 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2401 wm8994->mclk[1] = freq; 2402 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2403 dai->id, freq); 2404 break; 2405 2406 case WM8994_SYSCLK_FLL1: 2407 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2408 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2409 break; 2410 2411 case WM8994_SYSCLK_FLL2: 2412 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2413 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2414 break; 2415 2416 case WM8994_SYSCLK_OPCLK: 2417 /* Special case - a division (times 10) is given and 2418 * no effect on main clocking. 2419 */ 2420 if (freq) { 2421 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2422 if (opclk_divs[i] == freq) 2423 break; 2424 if (i == ARRAY_SIZE(opclk_divs)) 2425 return -EINVAL; 2426 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 2427 WM8994_OPCLK_DIV_MASK, i); 2428 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2429 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2430 } else { 2431 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2432 WM8994_OPCLK_ENA, 0); 2433 } 2434 2435 default: 2436 return -EINVAL; 2437 } 2438 2439 configure_clock(codec); 2440 2441 /* 2442 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2443 * for detection. 2444 */ 2445 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2446 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2447 2448 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) 2449 & WM8994_AIF1CLK_RATE_MASK; 2450 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) 2451 & WM8994_AIF1CLK_RATE_MASK; 2452 2453 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2454 WM8994_AIF1CLK_RATE_MASK, 0x1); 2455 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2456 WM8994_AIF2CLK_RATE_MASK, 0x1); 2457 } else if (wm8994->aifdiv[0]) { 2458 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2459 WM8994_AIF1CLK_RATE_MASK, 2460 wm8994->aifdiv[0]); 2461 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2462 WM8994_AIF2CLK_RATE_MASK, 2463 wm8994->aifdiv[1]); 2464 2465 wm8994->aifdiv[0] = 0; 2466 wm8994->aifdiv[1] = 0; 2467 } 2468 2469 return 0; 2470 } 2471 2472 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2473 enum snd_soc_bias_level level) 2474 { 2475 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2476 struct wm8994 *control = wm8994->wm8994; 2477 2478 wm_hubs_set_bias_level(codec, level); 2479 2480 switch (level) { 2481 case SND_SOC_BIAS_ON: 2482 break; 2483 2484 case SND_SOC_BIAS_PREPARE: 2485 /* MICBIAS into regulating mode */ 2486 switch (control->type) { 2487 case WM8958: 2488 case WM1811: 2489 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2490 WM8958_MICB1_MODE, 0); 2491 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2492 WM8958_MICB2_MODE, 0); 2493 break; 2494 default: 2495 break; 2496 } 2497 2498 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) 2499 active_reference(codec); 2500 break; 2501 2502 case SND_SOC_BIAS_STANDBY: 2503 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 2504 switch (control->type) { 2505 case WM8958: 2506 if (control->revision == 0) { 2507 /* Optimise performance for rev A */ 2508 snd_soc_update_bits(codec, 2509 WM8958_CHARGE_PUMP_2, 2510 WM8958_CP_DISCH, 2511 WM8958_CP_DISCH); 2512 } 2513 break; 2514 2515 default: 2516 break; 2517 } 2518 2519 /* Discharge LINEOUT1 & 2 */ 2520 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2521 WM8994_LINEOUT1_DISCH | 2522 WM8994_LINEOUT2_DISCH, 2523 WM8994_LINEOUT1_DISCH | 2524 WM8994_LINEOUT2_DISCH); 2525 } 2526 2527 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) 2528 active_dereference(codec); 2529 2530 /* MICBIAS into bypass mode on newer devices */ 2531 switch (control->type) { 2532 case WM8958: 2533 case WM1811: 2534 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2535 WM8958_MICB1_MODE, 2536 WM8958_MICB1_MODE); 2537 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2538 WM8958_MICB2_MODE, 2539 WM8958_MICB2_MODE); 2540 break; 2541 default: 2542 break; 2543 } 2544 break; 2545 2546 case SND_SOC_BIAS_OFF: 2547 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) 2548 wm8994->cur_fw = NULL; 2549 break; 2550 } 2551 2552 return 0; 2553 } 2554 2555 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode) 2556 { 2557 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2558 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2559 2560 switch (mode) { 2561 case WM8994_VMID_NORMAL: 2562 snd_soc_dapm_mutex_lock(dapm); 2563 2564 if (wm8994->hubs.lineout1_se) { 2565 snd_soc_dapm_disable_pin_unlocked(dapm, 2566 "LINEOUT1N Driver"); 2567 snd_soc_dapm_disable_pin_unlocked(dapm, 2568 "LINEOUT1P Driver"); 2569 } 2570 if (wm8994->hubs.lineout2_se) { 2571 snd_soc_dapm_disable_pin_unlocked(dapm, 2572 "LINEOUT2N Driver"); 2573 snd_soc_dapm_disable_pin_unlocked(dapm, 2574 "LINEOUT2P Driver"); 2575 } 2576 2577 /* Do the sync with the old mode to allow it to clean up */ 2578 snd_soc_dapm_sync_unlocked(dapm); 2579 wm8994->vmid_mode = mode; 2580 2581 snd_soc_dapm_mutex_unlock(dapm); 2582 break; 2583 2584 case WM8994_VMID_FORCE: 2585 snd_soc_dapm_mutex_lock(dapm); 2586 2587 if (wm8994->hubs.lineout1_se) { 2588 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2589 "LINEOUT1N Driver"); 2590 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2591 "LINEOUT1P Driver"); 2592 } 2593 if (wm8994->hubs.lineout2_se) { 2594 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2595 "LINEOUT2N Driver"); 2596 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2597 "LINEOUT2P Driver"); 2598 } 2599 2600 wm8994->vmid_mode = mode; 2601 snd_soc_dapm_sync_unlocked(dapm); 2602 2603 snd_soc_dapm_mutex_unlock(dapm); 2604 break; 2605 2606 default: 2607 return -EINVAL; 2608 } 2609 2610 return 0; 2611 } 2612 2613 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2614 { 2615 struct snd_soc_codec *codec = dai->codec; 2616 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2617 struct wm8994 *control = wm8994->wm8994; 2618 int ms_reg; 2619 int aif1_reg; 2620 int dac_reg; 2621 int adc_reg; 2622 int ms = 0; 2623 int aif1 = 0; 2624 int lrclk = 0; 2625 2626 switch (dai->id) { 2627 case 1: 2628 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2629 aif1_reg = WM8994_AIF1_CONTROL_1; 2630 dac_reg = WM8994_AIF1DAC_LRCLK; 2631 adc_reg = WM8994_AIF1ADC_LRCLK; 2632 break; 2633 case 2: 2634 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2635 aif1_reg = WM8994_AIF2_CONTROL_1; 2636 dac_reg = WM8994_AIF1DAC_LRCLK; 2637 adc_reg = WM8994_AIF1ADC_LRCLK; 2638 break; 2639 default: 2640 return -EINVAL; 2641 } 2642 2643 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2644 case SND_SOC_DAIFMT_CBS_CFS: 2645 break; 2646 case SND_SOC_DAIFMT_CBM_CFM: 2647 ms = WM8994_AIF1_MSTR; 2648 break; 2649 default: 2650 return -EINVAL; 2651 } 2652 2653 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2654 case SND_SOC_DAIFMT_DSP_B: 2655 aif1 |= WM8994_AIF1_LRCLK_INV; 2656 lrclk |= WM8958_AIF1_LRCLK_INV; 2657 case SND_SOC_DAIFMT_DSP_A: 2658 aif1 |= 0x18; 2659 break; 2660 case SND_SOC_DAIFMT_I2S: 2661 aif1 |= 0x10; 2662 break; 2663 case SND_SOC_DAIFMT_RIGHT_J: 2664 break; 2665 case SND_SOC_DAIFMT_LEFT_J: 2666 aif1 |= 0x8; 2667 break; 2668 default: 2669 return -EINVAL; 2670 } 2671 2672 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2673 case SND_SOC_DAIFMT_DSP_A: 2674 case SND_SOC_DAIFMT_DSP_B: 2675 /* frame inversion not valid for DSP modes */ 2676 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2677 case SND_SOC_DAIFMT_NB_NF: 2678 break; 2679 case SND_SOC_DAIFMT_IB_NF: 2680 aif1 |= WM8994_AIF1_BCLK_INV; 2681 break; 2682 default: 2683 return -EINVAL; 2684 } 2685 break; 2686 2687 case SND_SOC_DAIFMT_I2S: 2688 case SND_SOC_DAIFMT_RIGHT_J: 2689 case SND_SOC_DAIFMT_LEFT_J: 2690 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2691 case SND_SOC_DAIFMT_NB_NF: 2692 break; 2693 case SND_SOC_DAIFMT_IB_IF: 2694 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2695 lrclk |= WM8958_AIF1_LRCLK_INV; 2696 break; 2697 case SND_SOC_DAIFMT_IB_NF: 2698 aif1 |= WM8994_AIF1_BCLK_INV; 2699 break; 2700 case SND_SOC_DAIFMT_NB_IF: 2701 aif1 |= WM8994_AIF1_LRCLK_INV; 2702 lrclk |= WM8958_AIF1_LRCLK_INV; 2703 break; 2704 default: 2705 return -EINVAL; 2706 } 2707 break; 2708 default: 2709 return -EINVAL; 2710 } 2711 2712 /* The AIF2 format configuration needs to be mirrored to AIF3 2713 * on WM8958 if it's in use so just do it all the time. */ 2714 switch (control->type) { 2715 case WM1811: 2716 case WM8958: 2717 if (dai->id == 2) 2718 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2719 WM8994_AIF1_LRCLK_INV | 2720 WM8958_AIF3_FMT_MASK, aif1); 2721 break; 2722 2723 default: 2724 break; 2725 } 2726 2727 snd_soc_update_bits(codec, aif1_reg, 2728 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2729 WM8994_AIF1_FMT_MASK, 2730 aif1); 2731 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2732 ms); 2733 snd_soc_update_bits(codec, dac_reg, 2734 WM8958_AIF1_LRCLK_INV, lrclk); 2735 snd_soc_update_bits(codec, adc_reg, 2736 WM8958_AIF1_LRCLK_INV, lrclk); 2737 2738 return 0; 2739 } 2740 2741 static struct { 2742 int val, rate; 2743 } srs[] = { 2744 { 0, 8000 }, 2745 { 1, 11025 }, 2746 { 2, 12000 }, 2747 { 3, 16000 }, 2748 { 4, 22050 }, 2749 { 5, 24000 }, 2750 { 6, 32000 }, 2751 { 7, 44100 }, 2752 { 8, 48000 }, 2753 { 9, 88200 }, 2754 { 10, 96000 }, 2755 }; 2756 2757 static int fs_ratios[] = { 2758 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 2759 }; 2760 2761 static int bclk_divs[] = { 2762 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2763 640, 880, 960, 1280, 1760, 1920 2764 }; 2765 2766 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2767 struct snd_pcm_hw_params *params, 2768 struct snd_soc_dai *dai) 2769 { 2770 struct snd_soc_codec *codec = dai->codec; 2771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2772 struct wm8994 *control = wm8994->wm8994; 2773 struct wm8994_pdata *pdata = &control->pdata; 2774 int aif1_reg; 2775 int aif2_reg; 2776 int bclk_reg; 2777 int lrclk_reg; 2778 int rate_reg; 2779 int aif1 = 0; 2780 int aif2 = 0; 2781 int bclk = 0; 2782 int lrclk = 0; 2783 int rate_val = 0; 2784 int id = dai->id - 1; 2785 2786 int i, cur_val, best_val, bclk_rate, best; 2787 2788 switch (dai->id) { 2789 case 1: 2790 aif1_reg = WM8994_AIF1_CONTROL_1; 2791 aif2_reg = WM8994_AIF1_CONTROL_2; 2792 bclk_reg = WM8994_AIF1_BCLK; 2793 rate_reg = WM8994_AIF1_RATE; 2794 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2795 wm8994->lrclk_shared[0]) { 2796 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2797 } else { 2798 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2799 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2800 } 2801 break; 2802 case 2: 2803 aif1_reg = WM8994_AIF2_CONTROL_1; 2804 aif2_reg = WM8994_AIF2_CONTROL_2; 2805 bclk_reg = WM8994_AIF2_BCLK; 2806 rate_reg = WM8994_AIF2_RATE; 2807 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2808 wm8994->lrclk_shared[1]) { 2809 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2810 } else { 2811 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2812 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2813 } 2814 break; 2815 default: 2816 return -EINVAL; 2817 } 2818 2819 bclk_rate = params_rate(params); 2820 switch (params_width(params)) { 2821 case 16: 2822 bclk_rate *= 16; 2823 break; 2824 case 20: 2825 bclk_rate *= 20; 2826 aif1 |= 0x20; 2827 break; 2828 case 24: 2829 bclk_rate *= 24; 2830 aif1 |= 0x40; 2831 break; 2832 case 32: 2833 bclk_rate *= 32; 2834 aif1 |= 0x60; 2835 break; 2836 default: 2837 return -EINVAL; 2838 } 2839 2840 wm8994->channels[id] = params_channels(params); 2841 if (pdata->max_channels_clocked[id] && 2842 wm8994->channels[id] > pdata->max_channels_clocked[id]) { 2843 dev_dbg(dai->dev, "Constraining channels to %d from %d\n", 2844 pdata->max_channels_clocked[id], wm8994->channels[id]); 2845 wm8994->channels[id] = pdata->max_channels_clocked[id]; 2846 } 2847 2848 switch (wm8994->channels[id]) { 2849 case 1: 2850 case 2: 2851 bclk_rate *= 2; 2852 break; 2853 default: 2854 bclk_rate *= 4; 2855 break; 2856 } 2857 2858 /* Try to find an appropriate sample rate; look for an exact match. */ 2859 for (i = 0; i < ARRAY_SIZE(srs); i++) 2860 if (srs[i].rate == params_rate(params)) 2861 break; 2862 if (i == ARRAY_SIZE(srs)) 2863 return -EINVAL; 2864 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2865 2866 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2867 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2868 dai->id, wm8994->aifclk[id], bclk_rate); 2869 2870 if (wm8994->channels[id] == 1 && 2871 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2872 aif2 |= WM8994_AIF1_MONO; 2873 2874 if (wm8994->aifclk[id] == 0) { 2875 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2876 return -EINVAL; 2877 } 2878 2879 /* AIFCLK/fs ratio; look for a close match in either direction */ 2880 best = 0; 2881 best_val = abs((fs_ratios[0] * params_rate(params)) 2882 - wm8994->aifclk[id]); 2883 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2884 cur_val = abs((fs_ratios[i] * params_rate(params)) 2885 - wm8994->aifclk[id]); 2886 if (cur_val >= best_val) 2887 continue; 2888 best = i; 2889 best_val = cur_val; 2890 } 2891 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2892 dai->id, fs_ratios[best]); 2893 rate_val |= best; 2894 2895 /* We may not get quite the right frequency if using 2896 * approximate clocks so look for the closest match that is 2897 * higher than the target (we need to ensure that there enough 2898 * BCLKs to clock out the samples). 2899 */ 2900 best = 0; 2901 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2902 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2903 if (cur_val < 0) /* BCLK table is sorted */ 2904 break; 2905 best = i; 2906 } 2907 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2908 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2909 bclk_divs[best], bclk_rate); 2910 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2911 2912 lrclk = bclk_rate / params_rate(params); 2913 if (!lrclk) { 2914 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 2915 bclk_rate); 2916 return -EINVAL; 2917 } 2918 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2919 lrclk, bclk_rate / lrclk); 2920 2921 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2922 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2923 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2924 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2925 lrclk); 2926 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2927 WM8994_AIF1CLK_RATE_MASK, rate_val); 2928 2929 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2930 switch (dai->id) { 2931 case 1: 2932 wm8994->dac_rates[0] = params_rate(params); 2933 wm8994_set_retune_mobile(codec, 0); 2934 wm8994_set_retune_mobile(codec, 1); 2935 break; 2936 case 2: 2937 wm8994->dac_rates[1] = params_rate(params); 2938 wm8994_set_retune_mobile(codec, 2); 2939 break; 2940 } 2941 } 2942 2943 return 0; 2944 } 2945 2946 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2947 struct snd_pcm_hw_params *params, 2948 struct snd_soc_dai *dai) 2949 { 2950 struct snd_soc_codec *codec = dai->codec; 2951 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2952 struct wm8994 *control = wm8994->wm8994; 2953 int aif1_reg; 2954 int aif1 = 0; 2955 2956 switch (dai->id) { 2957 case 3: 2958 switch (control->type) { 2959 case WM1811: 2960 case WM8958: 2961 aif1_reg = WM8958_AIF3_CONTROL_1; 2962 break; 2963 default: 2964 return 0; 2965 } 2966 break; 2967 default: 2968 return 0; 2969 } 2970 2971 switch (params_width(params)) { 2972 case 16: 2973 break; 2974 case 20: 2975 aif1 |= 0x20; 2976 break; 2977 case 24: 2978 aif1 |= 0x40; 2979 break; 2980 case 32: 2981 aif1 |= 0x60; 2982 break; 2983 default: 2984 return -EINVAL; 2985 } 2986 2987 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2988 } 2989 2990 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2991 { 2992 struct snd_soc_codec *codec = codec_dai->codec; 2993 int mute_reg; 2994 int reg; 2995 2996 switch (codec_dai->id) { 2997 case 1: 2998 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2999 break; 3000 case 2: 3001 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 3002 break; 3003 default: 3004 return -EINVAL; 3005 } 3006 3007 if (mute) 3008 reg = WM8994_AIF1DAC1_MUTE; 3009 else 3010 reg = 0; 3011 3012 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 3013 3014 return 0; 3015 } 3016 3017 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3018 { 3019 struct snd_soc_codec *codec = codec_dai->codec; 3020 int reg, val, mask; 3021 3022 switch (codec_dai->id) { 3023 case 1: 3024 reg = WM8994_AIF1_MASTER_SLAVE; 3025 mask = WM8994_AIF1_TRI; 3026 break; 3027 case 2: 3028 reg = WM8994_AIF2_MASTER_SLAVE; 3029 mask = WM8994_AIF2_TRI; 3030 break; 3031 default: 3032 return -EINVAL; 3033 } 3034 3035 if (tristate) 3036 val = mask; 3037 else 3038 val = 0; 3039 3040 return snd_soc_update_bits(codec, reg, mask, val); 3041 } 3042 3043 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 3044 { 3045 struct snd_soc_codec *codec = dai->codec; 3046 3047 /* Disable the pulls on the AIF if we're using it to save power. */ 3048 snd_soc_update_bits(codec, WM8994_GPIO_3, 3049 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3050 snd_soc_update_bits(codec, WM8994_GPIO_4, 3051 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3052 snd_soc_update_bits(codec, WM8994_GPIO_5, 3053 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3054 3055 return 0; 3056 } 3057 3058 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3059 3060 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3061 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3062 3063 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3064 .set_sysclk = wm8994_set_dai_sysclk, 3065 .set_fmt = wm8994_set_dai_fmt, 3066 .hw_params = wm8994_hw_params, 3067 .digital_mute = wm8994_aif_mute, 3068 .set_pll = wm8994_set_fll, 3069 .set_tristate = wm8994_set_tristate, 3070 }; 3071 3072 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3073 .set_sysclk = wm8994_set_dai_sysclk, 3074 .set_fmt = wm8994_set_dai_fmt, 3075 .hw_params = wm8994_hw_params, 3076 .digital_mute = wm8994_aif_mute, 3077 .set_pll = wm8994_set_fll, 3078 .set_tristate = wm8994_set_tristate, 3079 }; 3080 3081 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3082 .hw_params = wm8994_aif3_hw_params, 3083 }; 3084 3085 static struct snd_soc_dai_driver wm8994_dai[] = { 3086 { 3087 .name = "wm8994-aif1", 3088 .id = 1, 3089 .playback = { 3090 .stream_name = "AIF1 Playback", 3091 .channels_min = 1, 3092 .channels_max = 2, 3093 .rates = WM8994_RATES, 3094 .formats = WM8994_FORMATS, 3095 .sig_bits = 24, 3096 }, 3097 .capture = { 3098 .stream_name = "AIF1 Capture", 3099 .channels_min = 1, 3100 .channels_max = 2, 3101 .rates = WM8994_RATES, 3102 .formats = WM8994_FORMATS, 3103 .sig_bits = 24, 3104 }, 3105 .ops = &wm8994_aif1_dai_ops, 3106 }, 3107 { 3108 .name = "wm8994-aif2", 3109 .id = 2, 3110 .playback = { 3111 .stream_name = "AIF2 Playback", 3112 .channels_min = 1, 3113 .channels_max = 2, 3114 .rates = WM8994_RATES, 3115 .formats = WM8994_FORMATS, 3116 .sig_bits = 24, 3117 }, 3118 .capture = { 3119 .stream_name = "AIF2 Capture", 3120 .channels_min = 1, 3121 .channels_max = 2, 3122 .rates = WM8994_RATES, 3123 .formats = WM8994_FORMATS, 3124 .sig_bits = 24, 3125 }, 3126 .probe = wm8994_aif2_probe, 3127 .ops = &wm8994_aif2_dai_ops, 3128 }, 3129 { 3130 .name = "wm8994-aif3", 3131 .id = 3, 3132 .playback = { 3133 .stream_name = "AIF3 Playback", 3134 .channels_min = 1, 3135 .channels_max = 2, 3136 .rates = WM8994_RATES, 3137 .formats = WM8994_FORMATS, 3138 .sig_bits = 24, 3139 }, 3140 .capture = { 3141 .stream_name = "AIF3 Capture", 3142 .channels_min = 1, 3143 .channels_max = 2, 3144 .rates = WM8994_RATES, 3145 .formats = WM8994_FORMATS, 3146 .sig_bits = 24, 3147 }, 3148 .ops = &wm8994_aif3_dai_ops, 3149 } 3150 }; 3151 3152 #ifdef CONFIG_PM 3153 static int wm8994_codec_suspend(struct snd_soc_codec *codec) 3154 { 3155 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3156 int i, ret; 3157 3158 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3159 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3160 sizeof(struct wm8994_fll_config)); 3161 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 3162 if (ret < 0) 3163 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 3164 i + 1, ret); 3165 } 3166 3167 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 3168 3169 return 0; 3170 } 3171 3172 static int wm8994_codec_resume(struct snd_soc_codec *codec) 3173 { 3174 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3175 int i, ret; 3176 3177 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3178 if (!wm8994->fll_suspend[i].out) 3179 continue; 3180 3181 ret = _wm8994_set_fll(codec, i + 1, 3182 wm8994->fll_suspend[i].src, 3183 wm8994->fll_suspend[i].in, 3184 wm8994->fll_suspend[i].out); 3185 if (ret < 0) 3186 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 3187 i + 1, ret); 3188 } 3189 3190 return 0; 3191 } 3192 #else 3193 #define wm8994_codec_suspend NULL 3194 #define wm8994_codec_resume NULL 3195 #endif 3196 3197 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3198 { 3199 struct snd_soc_codec *codec = wm8994->hubs.codec; 3200 struct wm8994 *control = wm8994->wm8994; 3201 struct wm8994_pdata *pdata = &control->pdata; 3202 struct snd_kcontrol_new controls[] = { 3203 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3204 wm8994->retune_mobile_enum, 3205 wm8994_get_retune_mobile_enum, 3206 wm8994_put_retune_mobile_enum), 3207 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3208 wm8994->retune_mobile_enum, 3209 wm8994_get_retune_mobile_enum, 3210 wm8994_put_retune_mobile_enum), 3211 SOC_ENUM_EXT("AIF2 EQ Mode", 3212 wm8994->retune_mobile_enum, 3213 wm8994_get_retune_mobile_enum, 3214 wm8994_put_retune_mobile_enum), 3215 }; 3216 int ret, i, j; 3217 const char **t; 3218 3219 /* We need an array of texts for the enum API but the number 3220 * of texts is likely to be less than the number of 3221 * configurations due to the sample rate dependency of the 3222 * configurations. */ 3223 wm8994->num_retune_mobile_texts = 0; 3224 wm8994->retune_mobile_texts = NULL; 3225 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3226 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3227 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3228 wm8994->retune_mobile_texts[j]) == 0) 3229 break; 3230 } 3231 3232 if (j != wm8994->num_retune_mobile_texts) 3233 continue; 3234 3235 /* Expand the array... */ 3236 t = krealloc(wm8994->retune_mobile_texts, 3237 sizeof(char *) * 3238 (wm8994->num_retune_mobile_texts + 1), 3239 GFP_KERNEL); 3240 if (t == NULL) 3241 continue; 3242 3243 /* ...store the new entry... */ 3244 t[wm8994->num_retune_mobile_texts] = 3245 pdata->retune_mobile_cfgs[i].name; 3246 3247 /* ...and remember the new version. */ 3248 wm8994->num_retune_mobile_texts++; 3249 wm8994->retune_mobile_texts = t; 3250 } 3251 3252 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 3253 wm8994->num_retune_mobile_texts); 3254 3255 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts; 3256 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3257 3258 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3259 ARRAY_SIZE(controls)); 3260 if (ret != 0) 3261 dev_err(wm8994->hubs.codec->dev, 3262 "Failed to add ReTune Mobile controls: %d\n", ret); 3263 } 3264 3265 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3266 { 3267 struct snd_soc_codec *codec = wm8994->hubs.codec; 3268 struct wm8994 *control = wm8994->wm8994; 3269 struct wm8994_pdata *pdata = &control->pdata; 3270 int ret, i; 3271 3272 if (!pdata) 3273 return; 3274 3275 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 3276 pdata->lineout2_diff, 3277 pdata->lineout1fb, 3278 pdata->lineout2fb, 3279 pdata->jd_scthr, 3280 pdata->jd_thr, 3281 pdata->micb1_delay, 3282 pdata->micb2_delay, 3283 pdata->micbias1_lvl, 3284 pdata->micbias2_lvl); 3285 3286 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3287 3288 if (pdata->num_drc_cfgs) { 3289 struct snd_kcontrol_new controls[] = { 3290 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3291 wm8994_get_drc_enum, wm8994_put_drc_enum), 3292 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3293 wm8994_get_drc_enum, wm8994_put_drc_enum), 3294 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3295 wm8994_get_drc_enum, wm8994_put_drc_enum), 3296 }; 3297 3298 /* We need an array of texts for the enum API */ 3299 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev, 3300 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL); 3301 if (!wm8994->drc_texts) 3302 return; 3303 3304 for (i = 0; i < pdata->num_drc_cfgs; i++) 3305 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3306 3307 wm8994->drc_enum.items = pdata->num_drc_cfgs; 3308 wm8994->drc_enum.texts = wm8994->drc_texts; 3309 3310 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3311 ARRAY_SIZE(controls)); 3312 for (i = 0; i < WM8994_NUM_DRC; i++) 3313 wm8994_set_drc(codec, i); 3314 } else { 3315 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, 3316 wm8994_drc_controls, 3317 ARRAY_SIZE(wm8994_drc_controls)); 3318 } 3319 3320 if (ret != 0) 3321 dev_err(wm8994->hubs.codec->dev, 3322 "Failed to add DRC mode controls: %d\n", ret); 3323 3324 3325 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 3326 pdata->num_retune_mobile_cfgs); 3327 3328 if (pdata->num_retune_mobile_cfgs) 3329 wm8994_handle_retune_mobile_pdata(wm8994); 3330 else 3331 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls, 3332 ARRAY_SIZE(wm8994_eq_controls)); 3333 3334 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3335 if (pdata->micbias[i]) { 3336 snd_soc_write(codec, WM8958_MICBIAS1 + i, 3337 pdata->micbias[i] & 0xffff); 3338 } 3339 } 3340 } 3341 3342 /** 3343 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3344 * 3345 * @codec: WM8994 codec 3346 * @jack: jack to report detection events on 3347 * @micbias: microphone bias to detect on 3348 * 3349 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3350 * being used to bring out signals to the processor then only platform 3351 * data configuration is needed for WM8994 and processor GPIOs should 3352 * be configured using snd_soc_jack_add_gpios() instead. 3353 * 3354 * Configuration of detection levels is available via the micbias1_lvl 3355 * and micbias2_lvl platform data members. 3356 */ 3357 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3358 int micbias) 3359 { 3360 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3362 struct wm8994_micdet *micdet; 3363 struct wm8994 *control = wm8994->wm8994; 3364 int reg, ret; 3365 3366 if (control->type != WM8994) { 3367 dev_warn(codec->dev, "Not a WM8994\n"); 3368 return -EINVAL; 3369 } 3370 3371 switch (micbias) { 3372 case 1: 3373 micdet = &wm8994->micdet[0]; 3374 if (jack) 3375 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3376 else 3377 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3378 break; 3379 case 2: 3380 micdet = &wm8994->micdet[1]; 3381 if (jack) 3382 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3383 else 3384 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3385 break; 3386 default: 3387 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias); 3388 return -EINVAL; 3389 } 3390 3391 if (ret != 0) 3392 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n", 3393 micbias, ret); 3394 3395 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n", 3396 micbias, jack); 3397 3398 /* Store the configuration */ 3399 micdet->jack = jack; 3400 micdet->detecting = true; 3401 3402 /* If either of the jacks is set up then enable detection */ 3403 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3404 reg = WM8994_MICD_ENA; 3405 else 3406 reg = 0; 3407 3408 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3409 3410 /* enable MICDET and MICSHRT deboune */ 3411 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE, 3412 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3413 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3414 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3415 3416 snd_soc_dapm_sync(dapm); 3417 3418 return 0; 3419 } 3420 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3421 3422 static void wm8994_mic_work(struct work_struct *work) 3423 { 3424 struct wm8994_priv *priv = container_of(work, 3425 struct wm8994_priv, 3426 mic_work.work); 3427 struct regmap *regmap = priv->wm8994->regmap; 3428 struct device *dev = priv->wm8994->dev; 3429 unsigned int reg; 3430 int ret; 3431 int report; 3432 3433 pm_runtime_get_sync(dev); 3434 3435 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3436 if (ret < 0) { 3437 dev_err(dev, "Failed to read microphone status: %d\n", 3438 ret); 3439 pm_runtime_put(dev); 3440 return; 3441 } 3442 3443 dev_dbg(dev, "Microphone status: %x\n", reg); 3444 3445 report = 0; 3446 if (reg & WM8994_MIC1_DET_STS) { 3447 if (priv->micdet[0].detecting) 3448 report = SND_JACK_HEADSET; 3449 } 3450 if (reg & WM8994_MIC1_SHRT_STS) { 3451 if (priv->micdet[0].detecting) 3452 report = SND_JACK_HEADPHONE; 3453 else 3454 report |= SND_JACK_BTN_0; 3455 } 3456 if (report) 3457 priv->micdet[0].detecting = false; 3458 else 3459 priv->micdet[0].detecting = true; 3460 3461 snd_soc_jack_report(priv->micdet[0].jack, report, 3462 SND_JACK_HEADSET | SND_JACK_BTN_0); 3463 3464 report = 0; 3465 if (reg & WM8994_MIC2_DET_STS) { 3466 if (priv->micdet[1].detecting) 3467 report = SND_JACK_HEADSET; 3468 } 3469 if (reg & WM8994_MIC2_SHRT_STS) { 3470 if (priv->micdet[1].detecting) 3471 report = SND_JACK_HEADPHONE; 3472 else 3473 report |= SND_JACK_BTN_0; 3474 } 3475 if (report) 3476 priv->micdet[1].detecting = false; 3477 else 3478 priv->micdet[1].detecting = true; 3479 3480 snd_soc_jack_report(priv->micdet[1].jack, report, 3481 SND_JACK_HEADSET | SND_JACK_BTN_0); 3482 3483 pm_runtime_put(dev); 3484 } 3485 3486 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3487 { 3488 struct wm8994_priv *priv = data; 3489 struct snd_soc_codec *codec = priv->hubs.codec; 3490 3491 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3492 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3493 #endif 3494 3495 pm_wakeup_event(codec->dev, 300); 3496 3497 queue_delayed_work(system_power_efficient_wq, 3498 &priv->mic_work, msecs_to_jiffies(250)); 3499 3500 return IRQ_HANDLED; 3501 } 3502 3503 /* Should be called with accdet_lock held */ 3504 static void wm1811_micd_stop(struct snd_soc_codec *codec) 3505 { 3506 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3507 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3508 3509 if (!wm8994->jackdet) 3510 return; 3511 3512 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3513 3514 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3515 3516 if (wm8994->wm8994->pdata.jd_ext_cap) 3517 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3518 } 3519 3520 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status) 3521 { 3522 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3523 int report; 3524 3525 report = 0; 3526 if (status & 0x4) 3527 report |= SND_JACK_BTN_0; 3528 3529 if (status & 0x8) 3530 report |= SND_JACK_BTN_1; 3531 3532 if (status & 0x10) 3533 report |= SND_JACK_BTN_2; 3534 3535 if (status & 0x20) 3536 report |= SND_JACK_BTN_3; 3537 3538 if (status & 0x40) 3539 report |= SND_JACK_BTN_4; 3540 3541 if (status & 0x80) 3542 report |= SND_JACK_BTN_5; 3543 3544 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3545 wm8994->btn_mask); 3546 } 3547 3548 static void wm8958_open_circuit_work(struct work_struct *work) 3549 { 3550 struct wm8994_priv *wm8994 = container_of(work, 3551 struct wm8994_priv, 3552 open_circuit_work.work); 3553 struct device *dev = wm8994->wm8994->dev; 3554 3555 mutex_lock(&wm8994->accdet_lock); 3556 3557 wm1811_micd_stop(wm8994->hubs.codec); 3558 3559 dev_dbg(dev, "Reporting open circuit\n"); 3560 3561 wm8994->jack_mic = false; 3562 wm8994->mic_detecting = true; 3563 3564 wm8958_micd_set_rate(wm8994->hubs.codec); 3565 3566 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3567 wm8994->btn_mask | 3568 SND_JACK_HEADSET); 3569 3570 mutex_unlock(&wm8994->accdet_lock); 3571 } 3572 3573 static void wm8958_mic_id(void *data, u16 status) 3574 { 3575 struct snd_soc_codec *codec = data; 3576 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3577 3578 /* Either nothing present or just starting detection */ 3579 if (!(status & WM8958_MICD_STS)) { 3580 /* If nothing present then clear our statuses */ 3581 dev_dbg(codec->dev, "Detected open circuit\n"); 3582 3583 queue_delayed_work(system_power_efficient_wq, 3584 &wm8994->open_circuit_work, 3585 msecs_to_jiffies(2500)); 3586 return; 3587 } 3588 3589 /* If the measurement is showing a high impedence we've got a 3590 * microphone. 3591 */ 3592 if (status & 0x600) { 3593 dev_dbg(codec->dev, "Detected microphone\n"); 3594 3595 wm8994->mic_detecting = false; 3596 wm8994->jack_mic = true; 3597 3598 wm8958_micd_set_rate(codec); 3599 3600 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3601 SND_JACK_HEADSET); 3602 } 3603 3604 3605 if (status & 0xfc) { 3606 dev_dbg(codec->dev, "Detected headphone\n"); 3607 wm8994->mic_detecting = false; 3608 3609 wm8958_micd_set_rate(codec); 3610 3611 /* If we have jackdet that will detect removal */ 3612 wm1811_micd_stop(codec); 3613 3614 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3615 SND_JACK_HEADSET); 3616 } 3617 } 3618 3619 /* Deferred mic detection to allow for extra settling time */ 3620 static void wm1811_mic_work(struct work_struct *work) 3621 { 3622 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3623 mic_work.work); 3624 struct wm8994 *control = wm8994->wm8994; 3625 struct snd_soc_codec *codec = wm8994->hubs.codec; 3626 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3627 3628 pm_runtime_get_sync(codec->dev); 3629 3630 /* If required for an external cap force MICBIAS on */ 3631 if (control->pdata.jd_ext_cap) { 3632 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 3633 snd_soc_dapm_sync(dapm); 3634 } 3635 3636 mutex_lock(&wm8994->accdet_lock); 3637 3638 dev_dbg(codec->dev, "Starting mic detection\n"); 3639 3640 /* Use a user-supplied callback if we have one */ 3641 if (wm8994->micd_cb) { 3642 wm8994->micd_cb(wm8994->micd_cb_data); 3643 } else { 3644 /* 3645 * Start off measument of microphone impedence to find out 3646 * what's actually there. 3647 */ 3648 wm8994->mic_detecting = true; 3649 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC); 3650 3651 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3652 WM8958_MICD_ENA, WM8958_MICD_ENA); 3653 } 3654 3655 mutex_unlock(&wm8994->accdet_lock); 3656 3657 pm_runtime_put(codec->dev); 3658 } 3659 3660 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3661 { 3662 struct wm8994_priv *wm8994 = data; 3663 struct wm8994 *control = wm8994->wm8994; 3664 struct snd_soc_codec *codec = wm8994->hubs.codec; 3665 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3666 int reg, delay; 3667 bool present; 3668 3669 pm_runtime_get_sync(codec->dev); 3670 3671 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3672 3673 mutex_lock(&wm8994->accdet_lock); 3674 3675 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3676 if (reg < 0) { 3677 dev_err(codec->dev, "Failed to read jack status: %d\n", reg); 3678 mutex_unlock(&wm8994->accdet_lock); 3679 pm_runtime_put(codec->dev); 3680 return IRQ_NONE; 3681 } 3682 3683 dev_dbg(codec->dev, "JACKDET %x\n", reg); 3684 3685 present = reg & WM1811_JACKDET_LVL; 3686 3687 if (present) { 3688 dev_dbg(codec->dev, "Jack detected\n"); 3689 3690 wm8958_micd_set_rate(codec); 3691 3692 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3693 WM8958_MICB2_DISCH, 0); 3694 3695 /* Disable debounce while inserted */ 3696 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3697 WM1811_JACKDET_DB, 0); 3698 3699 delay = control->pdata.micdet_delay; 3700 queue_delayed_work(system_power_efficient_wq, 3701 &wm8994->mic_work, 3702 msecs_to_jiffies(delay)); 3703 } else { 3704 dev_dbg(codec->dev, "Jack not detected\n"); 3705 3706 cancel_delayed_work_sync(&wm8994->mic_work); 3707 3708 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3709 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3710 3711 /* Enable debounce while removed */ 3712 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3713 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3714 3715 wm8994->mic_detecting = false; 3716 wm8994->jack_mic = false; 3717 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3718 WM8958_MICD_ENA, 0); 3719 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3720 } 3721 3722 mutex_unlock(&wm8994->accdet_lock); 3723 3724 /* Turn off MICBIAS if it was on for an external cap */ 3725 if (control->pdata.jd_ext_cap && !present) 3726 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3727 3728 if (present) 3729 snd_soc_jack_report(wm8994->micdet[0].jack, 3730 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3731 else 3732 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3733 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3734 wm8994->btn_mask); 3735 3736 /* Since we only report deltas force an update, ensures we 3737 * avoid bootstrapping issues with the core. */ 3738 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3739 3740 pm_runtime_put(codec->dev); 3741 return IRQ_HANDLED; 3742 } 3743 3744 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3745 { 3746 struct wm8994_priv *wm8994 = container_of(work, 3747 struct wm8994_priv, 3748 jackdet_bootstrap.work); 3749 wm1811_jackdet_irq(0, wm8994); 3750 } 3751 3752 /** 3753 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3754 * 3755 * @codec: WM8958 codec 3756 * @jack: jack to report detection events on 3757 * 3758 * Enable microphone detection functionality for the WM8958. By 3759 * default simple detection which supports the detection of up to 6 3760 * buttons plus video and microphone functionality is supported. 3761 * 3762 * The WM8958 has an advanced jack detection facility which is able to 3763 * support complex accessory detection, especially when used in 3764 * conjunction with external circuitry. In order to provide maximum 3765 * flexiblity a callback is provided which allows a completely custom 3766 * detection algorithm. 3767 */ 3768 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3769 wm1811_micdet_cb det_cb, void *det_cb_data, 3770 wm1811_mic_id_cb id_cb, void *id_cb_data) 3771 { 3772 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3773 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3774 struct wm8994 *control = wm8994->wm8994; 3775 u16 micd_lvl_sel; 3776 3777 switch (control->type) { 3778 case WM1811: 3779 case WM8958: 3780 break; 3781 default: 3782 return -EINVAL; 3783 } 3784 3785 if (jack) { 3786 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS"); 3787 snd_soc_dapm_sync(dapm); 3788 3789 wm8994->micdet[0].jack = jack; 3790 3791 if (det_cb) { 3792 wm8994->micd_cb = det_cb; 3793 wm8994->micd_cb_data = det_cb_data; 3794 } else { 3795 wm8994->mic_detecting = true; 3796 wm8994->jack_mic = false; 3797 } 3798 3799 if (id_cb) { 3800 wm8994->mic_id_cb = id_cb; 3801 wm8994->mic_id_cb_data = id_cb_data; 3802 } else { 3803 wm8994->mic_id_cb = wm8958_mic_id; 3804 wm8994->mic_id_cb_data = codec; 3805 } 3806 3807 wm8958_micd_set_rate(codec); 3808 3809 /* Detect microphones and short circuits by default */ 3810 if (control->pdata.micd_lvl_sel) 3811 micd_lvl_sel = control->pdata.micd_lvl_sel; 3812 else 3813 micd_lvl_sel = 0x41; 3814 3815 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3816 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3817 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3818 3819 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2, 3820 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3821 3822 WARN_ON(snd_soc_codec_get_bias_level(codec) > SND_SOC_BIAS_STANDBY); 3823 3824 /* 3825 * If we can use jack detection start off with that, 3826 * otherwise jump straight to microphone detection. 3827 */ 3828 if (wm8994->jackdet) { 3829 /* Disable debounce for the initial detect */ 3830 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3831 WM1811_JACKDET_DB, 0); 3832 3833 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3834 WM8958_MICB2_DISCH, 3835 WM8958_MICB2_DISCH); 3836 snd_soc_update_bits(codec, WM8994_LDO_1, 3837 WM8994_LDO1_DISCH, 0); 3838 wm1811_jackdet_set_mode(codec, 3839 WM1811_JACKDET_MODE_JACK); 3840 } else { 3841 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3842 WM8958_MICD_ENA, WM8958_MICD_ENA); 3843 } 3844 3845 } else { 3846 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3847 WM8958_MICD_ENA, 0); 3848 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE); 3849 snd_soc_dapm_disable_pin(dapm, "CLK_SYS"); 3850 snd_soc_dapm_sync(dapm); 3851 } 3852 3853 return 0; 3854 } 3855 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3856 3857 static void wm8958_mic_work(struct work_struct *work) 3858 { 3859 struct wm8994_priv *wm8994 = container_of(work, 3860 struct wm8994_priv, 3861 mic_complete_work.work); 3862 struct snd_soc_codec *codec = wm8994->hubs.codec; 3863 3864 pm_runtime_get_sync(codec->dev); 3865 3866 mutex_lock(&wm8994->accdet_lock); 3867 3868 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status); 3869 3870 mutex_unlock(&wm8994->accdet_lock); 3871 3872 pm_runtime_put(codec->dev); 3873 } 3874 3875 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3876 { 3877 struct wm8994_priv *wm8994 = data; 3878 struct snd_soc_codec *codec = wm8994->hubs.codec; 3879 int reg, count, ret, id_delay; 3880 3881 /* 3882 * Jack detection may have detected a removal simulataneously 3883 * with an update of the MICDET status; if so it will have 3884 * stopped detection and we can ignore this interrupt. 3885 */ 3886 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 3887 return IRQ_HANDLED; 3888 3889 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3890 cancel_delayed_work_sync(&wm8994->open_circuit_work); 3891 3892 pm_runtime_get_sync(codec->dev); 3893 3894 /* We may occasionally read a detection without an impedence 3895 * range being provided - if that happens loop again. 3896 */ 3897 count = 10; 3898 do { 3899 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 3900 if (reg < 0) { 3901 dev_err(codec->dev, 3902 "Failed to read mic detect status: %d\n", 3903 reg); 3904 pm_runtime_put(codec->dev); 3905 return IRQ_NONE; 3906 } 3907 3908 if (!(reg & WM8958_MICD_VALID)) { 3909 dev_dbg(codec->dev, "Mic detect data not valid\n"); 3910 goto out; 3911 } 3912 3913 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 3914 break; 3915 3916 msleep(1); 3917 } while (count--); 3918 3919 if (count == 0) 3920 dev_warn(codec->dev, "No impedance range reported for jack\n"); 3921 3922 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3923 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3924 #endif 3925 3926 /* Avoid a transient report when the accessory is being removed */ 3927 if (wm8994->jackdet) { 3928 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3929 if (ret < 0) { 3930 dev_err(codec->dev, "Failed to read jack status: %d\n", 3931 ret); 3932 } else if (!(ret & WM1811_JACKDET_LVL)) { 3933 dev_dbg(codec->dev, "Ignoring removed jack\n"); 3934 goto out; 3935 } 3936 } else if (!(reg & WM8958_MICD_STS)) { 3937 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3938 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3939 wm8994->btn_mask); 3940 wm8994->mic_detecting = true; 3941 goto out; 3942 } 3943 3944 wm8994->mic_status = reg; 3945 id_delay = wm8994->wm8994->pdata.mic_id_delay; 3946 3947 if (wm8994->mic_detecting) 3948 queue_delayed_work(system_power_efficient_wq, 3949 &wm8994->mic_complete_work, 3950 msecs_to_jiffies(id_delay)); 3951 else 3952 wm8958_button_det(codec, reg); 3953 3954 out: 3955 pm_runtime_put(codec->dev); 3956 return IRQ_HANDLED; 3957 } 3958 3959 static irqreturn_t wm8994_fifo_error(int irq, void *data) 3960 { 3961 struct snd_soc_codec *codec = data; 3962 3963 dev_err(codec->dev, "FIFO error\n"); 3964 3965 return IRQ_HANDLED; 3966 } 3967 3968 static irqreturn_t wm8994_temp_warn(int irq, void *data) 3969 { 3970 struct snd_soc_codec *codec = data; 3971 3972 dev_err(codec->dev, "Thermal warning\n"); 3973 3974 return IRQ_HANDLED; 3975 } 3976 3977 static irqreturn_t wm8994_temp_shut(int irq, void *data) 3978 { 3979 struct snd_soc_codec *codec = data; 3980 3981 dev_crit(codec->dev, "Thermal shutdown\n"); 3982 3983 return IRQ_HANDLED; 3984 } 3985 3986 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3987 { 3988 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3989 struct wm8994 *control = dev_get_drvdata(codec->dev->parent); 3990 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3991 unsigned int reg; 3992 int ret, i; 3993 3994 wm8994->hubs.codec = codec; 3995 3996 mutex_init(&wm8994->accdet_lock); 3997 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 3998 wm1811_jackdet_bootstrap); 3999 INIT_DELAYED_WORK(&wm8994->open_circuit_work, 4000 wm8958_open_circuit_work); 4001 4002 switch (control->type) { 4003 case WM8994: 4004 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 4005 break; 4006 case WM1811: 4007 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 4008 break; 4009 default: 4010 break; 4011 } 4012 4013 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work); 4014 4015 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4016 init_completion(&wm8994->fll_locked[i]); 4017 4018 wm8994->micdet_irq = control->pdata.micdet_irq; 4019 4020 /* By default use idle_bias_off, will override for WM8994 */ 4021 dapm->idle_bias_off = 1; 4022 4023 /* Set revision-specific configuration */ 4024 switch (control->type) { 4025 case WM8994: 4026 /* Single ended line outputs should have VMID on. */ 4027 if (!control->pdata.lineout1_diff || 4028 !control->pdata.lineout2_diff) 4029 dapm->idle_bias_off = 0; 4030 4031 switch (control->revision) { 4032 case 2: 4033 case 3: 4034 wm8994->hubs.dcs_codes_l = -5; 4035 wm8994->hubs.dcs_codes_r = -5; 4036 wm8994->hubs.hp_startup_mode = 1; 4037 wm8994->hubs.dcs_readback_mode = 1; 4038 wm8994->hubs.series_startup = 1; 4039 break; 4040 default: 4041 wm8994->hubs.dcs_readback_mode = 2; 4042 break; 4043 } 4044 break; 4045 4046 case WM8958: 4047 wm8994->hubs.dcs_readback_mode = 1; 4048 wm8994->hubs.hp_startup_mode = 1; 4049 4050 switch (control->revision) { 4051 case 0: 4052 break; 4053 default: 4054 wm8994->fll_byp = true; 4055 break; 4056 } 4057 break; 4058 4059 case WM1811: 4060 wm8994->hubs.dcs_readback_mode = 2; 4061 wm8994->hubs.no_series_update = 1; 4062 wm8994->hubs.hp_startup_mode = 1; 4063 wm8994->hubs.no_cache_dac_hp_direct = true; 4064 wm8994->fll_byp = true; 4065 4066 wm8994->hubs.dcs_codes_l = -9; 4067 wm8994->hubs.dcs_codes_r = -7; 4068 4069 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1, 4070 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 4071 break; 4072 4073 default: 4074 break; 4075 } 4076 4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 4078 wm8994_fifo_error, "FIFO error", codec); 4079 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 4080 wm8994_temp_warn, "Thermal warning", codec); 4081 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 4082 wm8994_temp_shut, "Thermal shutdown", codec); 4083 4084 switch (control->type) { 4085 case WM8994: 4086 if (wm8994->micdet_irq) 4087 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4088 wm8994_mic_irq, 4089 IRQF_TRIGGER_RISING | 4090 IRQF_ONESHOT, 4091 "Mic1 detect", 4092 wm8994); 4093 else 4094 ret = wm8994_request_irq(wm8994->wm8994, 4095 WM8994_IRQ_MIC1_DET, 4096 wm8994_mic_irq, "Mic 1 detect", 4097 wm8994); 4098 4099 if (ret != 0) 4100 dev_warn(codec->dev, 4101 "Failed to request Mic1 detect IRQ: %d\n", 4102 ret); 4103 4104 4105 ret = wm8994_request_irq(wm8994->wm8994, 4106 WM8994_IRQ_MIC1_SHRT, 4107 wm8994_mic_irq, "Mic 1 short", 4108 wm8994); 4109 if (ret != 0) 4110 dev_warn(codec->dev, 4111 "Failed to request Mic1 short IRQ: %d\n", 4112 ret); 4113 4114 ret = wm8994_request_irq(wm8994->wm8994, 4115 WM8994_IRQ_MIC2_DET, 4116 wm8994_mic_irq, "Mic 2 detect", 4117 wm8994); 4118 if (ret != 0) 4119 dev_warn(codec->dev, 4120 "Failed to request Mic2 detect IRQ: %d\n", 4121 ret); 4122 4123 ret = wm8994_request_irq(wm8994->wm8994, 4124 WM8994_IRQ_MIC2_SHRT, 4125 wm8994_mic_irq, "Mic 2 short", 4126 wm8994); 4127 if (ret != 0) 4128 dev_warn(codec->dev, 4129 "Failed to request Mic2 short IRQ: %d\n", 4130 ret); 4131 break; 4132 4133 case WM8958: 4134 case WM1811: 4135 if (wm8994->micdet_irq) { 4136 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4137 wm8958_mic_irq, 4138 IRQF_TRIGGER_RISING | 4139 IRQF_ONESHOT, 4140 "Mic detect", 4141 wm8994); 4142 if (ret != 0) 4143 dev_warn(codec->dev, 4144 "Failed to request Mic detect IRQ: %d\n", 4145 ret); 4146 } else { 4147 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4148 wm8958_mic_irq, "Mic detect", 4149 wm8994); 4150 } 4151 } 4152 4153 switch (control->type) { 4154 case WM1811: 4155 if (control->cust_id > 1 || control->revision > 1) { 4156 ret = wm8994_request_irq(wm8994->wm8994, 4157 WM8994_IRQ_GPIO(6), 4158 wm1811_jackdet_irq, "JACKDET", 4159 wm8994); 4160 if (ret == 0) 4161 wm8994->jackdet = true; 4162 } 4163 break; 4164 default: 4165 break; 4166 } 4167 4168 wm8994->fll_locked_irq = true; 4169 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4170 ret = wm8994_request_irq(wm8994->wm8994, 4171 WM8994_IRQ_FLL1_LOCK + i, 4172 wm8994_fll_locked_irq, "FLL lock", 4173 &wm8994->fll_locked[i]); 4174 if (ret != 0) 4175 wm8994->fll_locked_irq = false; 4176 } 4177 4178 /* Make sure we can read from the GPIOs if they're inputs */ 4179 pm_runtime_get_sync(codec->dev); 4180 4181 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4182 * configured on init - if a system wants to do this dynamically 4183 * at runtime we can deal with that then. 4184 */ 4185 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4186 if (ret < 0) { 4187 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 4188 goto err_irq; 4189 } 4190 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4191 wm8994->lrclk_shared[0] = 1; 4192 wm8994_dai[0].symmetric_rates = 1; 4193 } else { 4194 wm8994->lrclk_shared[0] = 0; 4195 } 4196 4197 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4198 if (ret < 0) { 4199 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 4200 goto err_irq; 4201 } 4202 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4203 wm8994->lrclk_shared[1] = 1; 4204 wm8994_dai[1].symmetric_rates = 1; 4205 } else { 4206 wm8994->lrclk_shared[1] = 0; 4207 } 4208 4209 pm_runtime_put(codec->dev); 4210 4211 /* Latch volume update bits */ 4212 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4213 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg, 4214 wm8994_vu_bits[i].mask, 4215 wm8994_vu_bits[i].mask); 4216 4217 /* Set the low bit of the 3D stereo depth so TLV matches */ 4218 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 4219 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4220 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4221 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 4222 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4223 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4224 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 4225 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4226 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4227 4228 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4229 * use this; it only affects behaviour on idle TDM clock 4230 * cycles. */ 4231 switch (control->type) { 4232 case WM8994: 4233 case WM8958: 4234 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 4235 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4236 break; 4237 default: 4238 break; 4239 } 4240 4241 /* Put MICBIAS into bypass mode by default on newer devices */ 4242 switch (control->type) { 4243 case WM8958: 4244 case WM1811: 4245 snd_soc_update_bits(codec, WM8958_MICBIAS1, 4246 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4247 snd_soc_update_bits(codec, WM8958_MICBIAS2, 4248 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4249 break; 4250 default: 4251 break; 4252 } 4253 4254 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4255 wm_hubs_update_class_w(codec); 4256 4257 wm8994_handle_pdata(wm8994); 4258 4259 wm_hubs_add_analogue_controls(codec); 4260 snd_soc_add_codec_controls(codec, wm8994_snd_controls, 4261 ARRAY_SIZE(wm8994_snd_controls)); 4262 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4263 ARRAY_SIZE(wm8994_dapm_widgets)); 4264 4265 switch (control->type) { 4266 case WM8994: 4267 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4268 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4269 if (control->revision < 4) { 4270 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4271 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4272 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4273 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4274 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4275 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4276 } else { 4277 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4278 ARRAY_SIZE(wm8994_lateclk_widgets)); 4279 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4280 ARRAY_SIZE(wm8994_adc_widgets)); 4281 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4282 ARRAY_SIZE(wm8994_dac_widgets)); 4283 } 4284 break; 4285 case WM8958: 4286 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4287 ARRAY_SIZE(wm8958_snd_controls)); 4288 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4289 ARRAY_SIZE(wm8958_dapm_widgets)); 4290 if (control->revision < 1) { 4291 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4292 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4293 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4294 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4295 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4296 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4297 } else { 4298 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4299 ARRAY_SIZE(wm8994_lateclk_widgets)); 4300 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4301 ARRAY_SIZE(wm8994_adc_widgets)); 4302 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4303 ARRAY_SIZE(wm8994_dac_widgets)); 4304 } 4305 break; 4306 4307 case WM1811: 4308 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4309 ARRAY_SIZE(wm8958_snd_controls)); 4310 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4311 ARRAY_SIZE(wm8958_dapm_widgets)); 4312 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4313 ARRAY_SIZE(wm8994_lateclk_widgets)); 4314 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4315 ARRAY_SIZE(wm8994_adc_widgets)); 4316 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4317 ARRAY_SIZE(wm8994_dac_widgets)); 4318 break; 4319 } 4320 4321 wm_hubs_add_analogue_routes(codec, 0, 0); 4322 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4323 wm_hubs_dcs_done, "DC servo done", 4324 &wm8994->hubs); 4325 if (ret == 0) 4326 wm8994->hubs.dcs_done_irq = true; 4327 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4328 4329 switch (control->type) { 4330 case WM8994: 4331 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4332 ARRAY_SIZE(wm8994_intercon)); 4333 4334 if (control->revision < 4) { 4335 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4336 ARRAY_SIZE(wm8994_revd_intercon)); 4337 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4338 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4339 } else { 4340 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4341 ARRAY_SIZE(wm8994_lateclk_intercon)); 4342 } 4343 break; 4344 case WM8958: 4345 if (control->revision < 1) { 4346 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4347 ARRAY_SIZE(wm8994_intercon)); 4348 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4349 ARRAY_SIZE(wm8994_revd_intercon)); 4350 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4351 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4352 } else { 4353 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4354 ARRAY_SIZE(wm8994_lateclk_intercon)); 4355 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4356 ARRAY_SIZE(wm8958_intercon)); 4357 } 4358 4359 wm8958_dsp2_init(codec); 4360 break; 4361 case WM1811: 4362 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4363 ARRAY_SIZE(wm8994_lateclk_intercon)); 4364 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4365 ARRAY_SIZE(wm8958_intercon)); 4366 break; 4367 } 4368 4369 return 0; 4370 4371 err_irq: 4372 if (wm8994->jackdet) 4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4376 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4377 if (wm8994->micdet_irq) 4378 free_irq(wm8994->micdet_irq, wm8994); 4379 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4380 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4381 &wm8994->fll_locked[i]); 4382 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4383 &wm8994->hubs); 4384 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4385 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4386 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4387 4388 return ret; 4389 } 4390 4391 static int wm8994_codec_remove(struct snd_soc_codec *codec) 4392 { 4393 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 4394 struct wm8994 *control = wm8994->wm8994; 4395 int i; 4396 4397 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4399 &wm8994->fll_locked[i]); 4400 4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4402 &wm8994->hubs); 4403 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4406 4407 if (wm8994->jackdet) 4408 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4409 4410 switch (control->type) { 4411 case WM8994: 4412 if (wm8994->micdet_irq) 4413 free_irq(wm8994->micdet_irq, wm8994); 4414 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4415 wm8994); 4416 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4417 wm8994); 4418 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4419 wm8994); 4420 break; 4421 4422 case WM1811: 4423 case WM8958: 4424 if (wm8994->micdet_irq) 4425 free_irq(wm8994->micdet_irq, wm8994); 4426 break; 4427 } 4428 release_firmware(wm8994->mbc); 4429 release_firmware(wm8994->mbc_vss); 4430 release_firmware(wm8994->enh_eq); 4431 kfree(wm8994->retune_mobile_texts); 4432 return 0; 4433 } 4434 4435 static struct regmap *wm8994_get_regmap(struct device *dev) 4436 { 4437 struct wm8994 *control = dev_get_drvdata(dev->parent); 4438 4439 return control->regmap; 4440 } 4441 4442 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 4443 .probe = wm8994_codec_probe, 4444 .remove = wm8994_codec_remove, 4445 .suspend = wm8994_codec_suspend, 4446 .resume = wm8994_codec_resume, 4447 .get_regmap = wm8994_get_regmap, 4448 .set_bias_level = wm8994_set_bias_level, 4449 }; 4450 4451 static int wm8994_probe(struct platform_device *pdev) 4452 { 4453 struct wm8994_priv *wm8994; 4454 4455 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4456 GFP_KERNEL); 4457 if (wm8994 == NULL) 4458 return -ENOMEM; 4459 platform_set_drvdata(pdev, wm8994); 4460 4461 mutex_init(&wm8994->fw_lock); 4462 4463 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4464 4465 pm_runtime_enable(&pdev->dev); 4466 pm_runtime_idle(&pdev->dev); 4467 4468 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 4469 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4470 } 4471 4472 static int wm8994_remove(struct platform_device *pdev) 4473 { 4474 snd_soc_unregister_codec(&pdev->dev); 4475 pm_runtime_disable(&pdev->dev); 4476 4477 return 0; 4478 } 4479 4480 #ifdef CONFIG_PM_SLEEP 4481 static int wm8994_suspend(struct device *dev) 4482 { 4483 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4484 4485 /* Drop down to power saving mode when system is suspended */ 4486 if (wm8994->jackdet && !wm8994->active_refcount) 4487 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4488 WM1811_JACKDET_MODE_MASK, 4489 wm8994->jackdet_mode); 4490 4491 return 0; 4492 } 4493 4494 static int wm8994_resume(struct device *dev) 4495 { 4496 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4497 4498 if (wm8994->jackdet && wm8994->jackdet_mode) 4499 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4500 WM1811_JACKDET_MODE_MASK, 4501 WM1811_JACKDET_MODE_AUDIO); 4502 4503 return 0; 4504 } 4505 #endif 4506 4507 static const struct dev_pm_ops wm8994_pm_ops = { 4508 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4509 }; 4510 4511 static struct platform_driver wm8994_codec_driver = { 4512 .driver = { 4513 .name = "wm8994-codec", 4514 .pm = &wm8994_pm_ops, 4515 }, 4516 .probe = wm8994_probe, 4517 .remove = wm8994_remove, 4518 }; 4519 4520 module_platform_driver(wm8994_codec_driver); 4521 4522 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4523 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4524 MODULE_LICENSE("GPL"); 4525 MODULE_ALIAS("platform:wm8994-codec"); 4526