1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 #include <trace/events/asoc.h> 33 34 #include <linux/mfd/wm8994/core.h> 35 #include <linux/mfd/wm8994/registers.h> 36 #include <linux/mfd/wm8994/pdata.h> 37 #include <linux/mfd/wm8994/gpio.h> 38 39 #include "wm8994.h" 40 #include "wm_hubs.h" 41 42 #define WM1811_JACKDET_MODE_NONE 0x0000 43 #define WM1811_JACKDET_MODE_JACK 0x0100 44 #define WM1811_JACKDET_MODE_MIC 0x0080 45 #define WM1811_JACKDET_MODE_AUDIO 0x0180 46 47 #define WM8994_NUM_DRC 3 48 #define WM8994_NUM_EQ 3 49 50 static struct { 51 unsigned int reg; 52 unsigned int mask; 53 } wm8994_vu_bits[] = { 54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 64 65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 81 }; 82 83 static int wm8994_drc_base[] = { 84 WM8994_AIF1_DRC1_1, 85 WM8994_AIF1_DRC2_1, 86 WM8994_AIF2_DRC_1, 87 }; 88 89 static int wm8994_retune_mobile_base[] = { 90 WM8994_AIF1_DAC1_EQ_GAINS_1, 91 WM8994_AIF1_DAC2_EQ_GAINS_1, 92 WM8994_AIF2_EQ_GAINS_1, 93 }; 94 95 static const struct wm8958_micd_rate micdet_rates[] = { 96 { 32768, true, 1, 4 }, 97 { 32768, false, 1, 1 }, 98 { 44100 * 256, true, 7, 10 }, 99 { 44100 * 256, false, 7, 10 }, 100 }; 101 102 static const struct wm8958_micd_rate jackdet_rates[] = { 103 { 32768, true, 0, 1 }, 104 { 32768, false, 0, 1 }, 105 { 44100 * 256, true, 10, 10 }, 106 { 44100 * 256, false, 7, 8 }, 107 }; 108 109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec) 110 { 111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 112 struct wm8994 *control = wm8994->wm8994; 113 int best, i, sysclk, val; 114 bool idle; 115 const struct wm8958_micd_rate *rates; 116 int num_rates; 117 118 idle = !wm8994->jack_mic; 119 120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1); 121 if (sysclk & WM8994_SYSCLK_SRC) 122 sysclk = wm8994->aifclk[1]; 123 else 124 sysclk = wm8994->aifclk[0]; 125 126 if (control->pdata.micd_rates) { 127 rates = control->pdata.micd_rates; 128 num_rates = control->pdata.num_micd_rates; 129 } else if (wm8994->jackdet) { 130 rates = jackdet_rates; 131 num_rates = ARRAY_SIZE(jackdet_rates); 132 } else { 133 rates = micdet_rates; 134 num_rates = ARRAY_SIZE(micdet_rates); 135 } 136 137 best = 0; 138 for (i = 0; i < num_rates; i++) { 139 if (rates[i].idle != idle) 140 continue; 141 if (abs(rates[i].sysclk - sysclk) < 142 abs(rates[best].sysclk - sysclk)) 143 best = i; 144 else if (rates[best].idle != idle) 145 best = i; 146 } 147 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 149 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 150 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n", 152 rates[best].start, rates[best].rate, sysclk, 153 idle ? "idle" : "active"); 154 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 156 WM8958_MICD_BIAS_STARTTIME_MASK | 157 WM8958_MICD_RATE_MASK, val); 158 } 159 160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 161 { 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 163 int rate; 164 int reg1 = 0; 165 int offset; 166 167 if (aif) 168 offset = 4; 169 else 170 offset = 0; 171 172 switch (wm8994->sysclk[aif]) { 173 case WM8994_SYSCLK_MCLK1: 174 rate = wm8994->mclk[0]; 175 break; 176 177 case WM8994_SYSCLK_MCLK2: 178 reg1 |= 0x8; 179 rate = wm8994->mclk[1]; 180 break; 181 182 case WM8994_SYSCLK_FLL1: 183 reg1 |= 0x10; 184 rate = wm8994->fll[0].out; 185 break; 186 187 case WM8994_SYSCLK_FLL2: 188 reg1 |= 0x18; 189 rate = wm8994->fll[1].out; 190 break; 191 192 default: 193 return -EINVAL; 194 } 195 196 if (rate >= 13500000) { 197 rate /= 2; 198 reg1 |= WM8994_AIF1CLK_DIV; 199 200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 201 aif + 1, rate); 202 } 203 204 wm8994->aifclk[aif] = rate; 205 206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 208 reg1); 209 210 return 0; 211 } 212 213 static int configure_clock(struct snd_soc_codec *codec) 214 { 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 216 int change, new; 217 218 /* Bring up the AIF clocks first */ 219 configure_aif_clock(codec, 0); 220 configure_aif_clock(codec, 1); 221 222 /* Then switch CLK_SYS over to the higher of them; a change 223 * can only happen as a result of a clocking change which can 224 * only be made outside of DAPM so we can safely redo the 225 * clocking. 226 */ 227 228 /* If they're equal it doesn't matter which is used */ 229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 230 wm8958_micd_set_rate(codec); 231 return 0; 232 } 233 234 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 235 new = WM8994_SYSCLK_SRC; 236 else 237 new = 0; 238 239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1, 240 WM8994_SYSCLK_SRC, new); 241 if (change) 242 snd_soc_dapm_sync(&codec->dapm); 243 244 wm8958_micd_set_rate(codec); 245 246 return 0; 247 } 248 249 static int check_clk_sys(struct snd_soc_dapm_widget *source, 250 struct snd_soc_dapm_widget *sink) 251 { 252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 253 const char *clk; 254 255 /* Check what we're currently using for CLK_SYS */ 256 if (reg & WM8994_SYSCLK_SRC) 257 clk = "AIF2CLK"; 258 else 259 clk = "AIF1CLK"; 260 261 return strcmp(source->name, clk) == 0; 262 } 263 264 static const char *sidetone_hpf_text[] = { 265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 266 }; 267 268 static const struct soc_enum sidetone_hpf = 269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 270 271 static const char *adc_hpf_text[] = { 272 "HiFi", "Voice 1", "Voice 2", "Voice 3" 273 }; 274 275 static const struct soc_enum aif1adc1_hpf = 276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 277 278 static const struct soc_enum aif1adc2_hpf = 279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 280 281 static const struct soc_enum aif2adc_hpf = 282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 283 284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); 291 292 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ 294 snd_soc_get_volsw, wm8994_put_drc_sw) 295 296 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct soc_mixer_control *mc = 300 (struct soc_mixer_control *)kcontrol->private_value; 301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 302 int mask, ret; 303 304 /* Can't enable both ADC and DAC paths simultaneously */ 305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 307 WM8994_AIF1ADC1R_DRC_ENA_MASK; 308 else 309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 310 311 ret = snd_soc_read(codec, mc->reg); 312 if (ret < 0) 313 return ret; 314 if (ret & mask) 315 return -EINVAL; 316 317 return snd_soc_put_volsw(kcontrol, ucontrol); 318 } 319 320 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 321 { 322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 323 struct wm8994 *control = wm8994->wm8994; 324 struct wm8994_pdata *pdata = &control->pdata; 325 int base = wm8994_drc_base[drc]; 326 int cfg = wm8994->drc_cfg[drc]; 327 int save, i; 328 329 /* Save any enables; the configuration should clear them. */ 330 save = snd_soc_read(codec, base); 331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 332 WM8994_AIF1ADC1R_DRC_ENA; 333 334 for (i = 0; i < WM8994_DRC_REGS; i++) 335 snd_soc_update_bits(codec, base + i, 0xffff, 336 pdata->drc_cfgs[cfg].regs[i]); 337 338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 339 WM8994_AIF1ADC1L_DRC_ENA | 340 WM8994_AIF1ADC1R_DRC_ENA, save); 341 } 342 343 /* Icky as hell but saves code duplication */ 344 static int wm8994_get_drc(const char *name) 345 { 346 if (strcmp(name, "AIF1DRC1 Mode") == 0) 347 return 0; 348 if (strcmp(name, "AIF1DRC2 Mode") == 0) 349 return 1; 350 if (strcmp(name, "AIF2DRC Mode") == 0) 351 return 2; 352 return -EINVAL; 353 } 354 355 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 356 struct snd_ctl_elem_value *ucontrol) 357 { 358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 360 struct wm8994 *control = wm8994->wm8994; 361 struct wm8994_pdata *pdata = &control->pdata; 362 int drc = wm8994_get_drc(kcontrol->id.name); 363 int value = ucontrol->value.integer.value[0]; 364 365 if (drc < 0) 366 return drc; 367 368 if (value >= pdata->num_drc_cfgs) 369 return -EINVAL; 370 371 wm8994->drc_cfg[drc] = value; 372 373 wm8994_set_drc(codec, drc); 374 375 return 0; 376 } 377 378 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 379 struct snd_ctl_elem_value *ucontrol) 380 { 381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 383 int drc = wm8994_get_drc(kcontrol->id.name); 384 385 if (drc < 0) 386 return drc; 387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 388 389 return 0; 390 } 391 392 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 393 { 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 395 struct wm8994 *control = wm8994->wm8994; 396 struct wm8994_pdata *pdata = &control->pdata; 397 int base = wm8994_retune_mobile_base[block]; 398 int iface, best, best_val, save, i, cfg; 399 400 if (!pdata || !wm8994->num_retune_mobile_texts) 401 return; 402 403 switch (block) { 404 case 0: 405 case 1: 406 iface = 0; 407 break; 408 case 2: 409 iface = 1; 410 break; 411 default: 412 return; 413 } 414 415 /* Find the version of the currently selected configuration 416 * with the nearest sample rate. */ 417 cfg = wm8994->retune_mobile_cfg[block]; 418 best = 0; 419 best_val = INT_MAX; 420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 421 if (strcmp(pdata->retune_mobile_cfgs[i].name, 422 wm8994->retune_mobile_texts[cfg]) == 0 && 423 abs(pdata->retune_mobile_cfgs[i].rate 424 - wm8994->dac_rates[iface]) < best_val) { 425 best = i; 426 best_val = abs(pdata->retune_mobile_cfgs[i].rate 427 - wm8994->dac_rates[iface]); 428 } 429 } 430 431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 432 block, 433 pdata->retune_mobile_cfgs[best].name, 434 pdata->retune_mobile_cfgs[best].rate, 435 wm8994->dac_rates[iface]); 436 437 /* The EQ will be disabled while reconfiguring it, remember the 438 * current configuration. 439 */ 440 save = snd_soc_read(codec, base); 441 save &= WM8994_AIF1DAC1_EQ_ENA; 442 443 for (i = 0; i < WM8994_EQ_REGS; i++) 444 snd_soc_update_bits(codec, base + i, 0xffff, 445 pdata->retune_mobile_cfgs[best].regs[i]); 446 447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 448 } 449 450 /* Icky as hell but saves code duplication */ 451 static int wm8994_get_retune_mobile_block(const char *name) 452 { 453 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 454 return 0; 455 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 456 return 1; 457 if (strcmp(name, "AIF2 EQ Mode") == 0) 458 return 2; 459 return -EINVAL; 460 } 461 462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 463 struct snd_ctl_elem_value *ucontrol) 464 { 465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 467 struct wm8994 *control = wm8994->wm8994; 468 struct wm8994_pdata *pdata = &control->pdata; 469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 470 int value = ucontrol->value.integer.value[0]; 471 472 if (block < 0) 473 return block; 474 475 if (value >= pdata->num_retune_mobile_cfgs) 476 return -EINVAL; 477 478 wm8994->retune_mobile_cfg[block] = value; 479 480 wm8994_set_retune_mobile(codec, block); 481 482 return 0; 483 } 484 485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 486 struct snd_ctl_elem_value *ucontrol) 487 { 488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 491 492 if (block < 0) 493 return block; 494 495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 496 497 return 0; 498 } 499 500 static const char *aif_chan_src_text[] = { 501 "Left", "Right" 502 }; 503 504 static const struct soc_enum aif1adcl_src = 505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 506 507 static const struct soc_enum aif1adcr_src = 508 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 509 510 static const struct soc_enum aif2adcl_src = 511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 512 513 static const struct soc_enum aif2adcr_src = 514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 515 516 static const struct soc_enum aif1dacl_src = 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 518 519 static const struct soc_enum aif1dacr_src = 520 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 521 522 static const struct soc_enum aif2dacl_src = 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 524 525 static const struct soc_enum aif2dacr_src = 526 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 527 528 static const char *osr_text[] = { 529 "Low Power", "High Performance", 530 }; 531 532 static const struct soc_enum dac_osr = 533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 534 535 static const struct soc_enum adc_osr = 536 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 537 538 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 539 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 540 WM8994_AIF1_ADC1_RIGHT_VOLUME, 541 1, 119, 0, digital_tlv), 542 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 543 WM8994_AIF1_ADC2_RIGHT_VOLUME, 544 1, 119, 0, digital_tlv), 545 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 546 WM8994_AIF2_ADC_RIGHT_VOLUME, 547 1, 119, 0, digital_tlv), 548 549 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 550 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 551 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 552 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 553 554 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 555 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 556 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 557 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 558 559 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 561 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 563 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 565 566 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 567 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 568 569 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 570 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 571 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 572 573 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 574 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 575 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 576 577 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 578 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 579 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 580 581 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 582 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 583 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 584 585 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 586 5, 12, 0, st_tlv), 587 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 588 0, 12, 0, st_tlv), 589 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 590 5, 12, 0, st_tlv), 591 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 592 0, 12, 0, st_tlv), 593 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 594 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 595 596 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 597 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 598 599 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 600 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 601 602 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 603 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 604 605 SOC_ENUM("ADC OSR", adc_osr), 606 SOC_ENUM("DAC OSR", dac_osr), 607 608 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 610 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 612 613 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 615 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 617 618 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 619 6, 1, 1, wm_hubs_spkmix_tlv), 620 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 621 2, 1, 1, wm_hubs_spkmix_tlv), 622 623 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 624 6, 1, 1, wm_hubs_spkmix_tlv), 625 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 626 2, 1, 1, wm_hubs_spkmix_tlv), 627 628 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 629 10, 15, 0, wm8994_3d_tlv), 630 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 631 8, 1, 0), 632 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 633 10, 15, 0, wm8994_3d_tlv), 634 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 635 8, 1, 0), 636 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 637 10, 15, 0, wm8994_3d_tlv), 638 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 639 8, 1, 0), 640 }; 641 642 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 643 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 644 eq_tlv), 645 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 646 eq_tlv), 647 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 648 eq_tlv), 649 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 650 eq_tlv), 651 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 652 eq_tlv), 653 654 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 655 eq_tlv), 656 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 659 eq_tlv), 660 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 661 eq_tlv), 662 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 663 eq_tlv), 664 665 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 666 eq_tlv), 667 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 670 eq_tlv), 671 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 672 eq_tlv), 673 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 674 eq_tlv), 675 }; 676 677 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 678 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 680 WM8994_AIF1ADC1R_DRC_ENA), 681 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 683 WM8994_AIF1ADC2R_DRC_ENA), 684 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 686 WM8994_AIF2ADCR_DRC_ENA), 687 }; 688 689 static const char *wm8958_ng_text[] = { 690 "30ms", "125ms", "250ms", "500ms", 691 }; 692 693 static const struct soc_enum wm8958_aif1dac1_ng_hold = 694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE, 695 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text); 696 697 static const struct soc_enum wm8958_aif1dac2_ng_hold = 698 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE, 699 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text); 700 701 static const struct soc_enum wm8958_aif2dac_ng_hold = 702 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE, 703 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text); 704 705 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 706 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 707 708 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 709 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 710 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 711 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 712 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 713 7, 1, ng_tlv), 714 715 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 716 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 717 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 718 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 719 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 720 7, 1, ng_tlv), 721 722 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 723 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 724 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 725 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 726 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 727 7, 1, ng_tlv), 728 }; 729 730 static const struct snd_kcontrol_new wm1811_snd_controls[] = { 731 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, 732 mixin_boost_tlv), 733 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, 734 mixin_boost_tlv), 735 }; 736 737 /* We run all mode setting through a function to enforce audio mode */ 738 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode) 739 { 740 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 741 742 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 743 return; 744 745 if (wm8994->active_refcount) 746 mode = WM1811_JACKDET_MODE_AUDIO; 747 748 if (mode == wm8994->jackdet_mode) 749 return; 750 751 wm8994->jackdet_mode = mode; 752 753 /* Always use audio mode to detect while the system is active */ 754 if (mode != WM1811_JACKDET_MODE_NONE) 755 mode = WM1811_JACKDET_MODE_AUDIO; 756 757 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 758 WM1811_JACKDET_MODE_MASK, mode); 759 } 760 761 static void active_reference(struct snd_soc_codec *codec) 762 { 763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 764 765 mutex_lock(&wm8994->accdet_lock); 766 767 wm8994->active_refcount++; 768 769 dev_dbg(codec->dev, "Active refcount incremented, now %d\n", 770 wm8994->active_refcount); 771 772 /* If we're using jack detection go into audio mode */ 773 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO); 774 775 mutex_unlock(&wm8994->accdet_lock); 776 } 777 778 static void active_dereference(struct snd_soc_codec *codec) 779 { 780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 781 u16 mode; 782 783 mutex_lock(&wm8994->accdet_lock); 784 785 wm8994->active_refcount--; 786 787 dev_dbg(codec->dev, "Active refcount decremented, now %d\n", 788 wm8994->active_refcount); 789 790 if (wm8994->active_refcount == 0) { 791 /* Go into appropriate detection only mode */ 792 if (wm8994->jack_mic || wm8994->mic_detecting) 793 mode = WM1811_JACKDET_MODE_MIC; 794 else 795 mode = WM1811_JACKDET_MODE_JACK; 796 797 wm1811_jackdet_set_mode(codec, mode); 798 } 799 800 mutex_unlock(&wm8994->accdet_lock); 801 } 802 803 static int clk_sys_event(struct snd_soc_dapm_widget *w, 804 struct snd_kcontrol *kcontrol, int event) 805 { 806 struct snd_soc_codec *codec = w->codec; 807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 808 809 switch (event) { 810 case SND_SOC_DAPM_PRE_PMU: 811 return configure_clock(codec); 812 813 case SND_SOC_DAPM_POST_PMU: 814 /* 815 * JACKDET won't run until we start the clock and it 816 * only reports deltas, make sure we notify the state 817 * up the stack on startup. Use a *very* generous 818 * timeout for paranoia, there's no urgency and we 819 * don't want false reports. 820 */ 821 if (wm8994->jackdet && !wm8994->clk_has_run) { 822 schedule_delayed_work(&wm8994->jackdet_bootstrap, 823 msecs_to_jiffies(1000)); 824 wm8994->clk_has_run = true; 825 } 826 break; 827 828 case SND_SOC_DAPM_POST_PMD: 829 configure_clock(codec); 830 break; 831 } 832 833 return 0; 834 } 835 836 static void vmid_reference(struct snd_soc_codec *codec) 837 { 838 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 839 840 pm_runtime_get_sync(codec->dev); 841 842 wm8994->vmid_refcount++; 843 844 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", 845 wm8994->vmid_refcount); 846 847 if (wm8994->vmid_refcount == 1) { 848 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 849 WM8994_LINEOUT1_DISCH | 850 WM8994_LINEOUT2_DISCH, 0); 851 852 wm_hubs_vmid_ena(codec); 853 854 switch (wm8994->vmid_mode) { 855 default: 856 WARN_ON(NULL == "Invalid VMID mode"); 857 case WM8994_VMID_NORMAL: 858 /* Startup bias, VMID ramp & buffer */ 859 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 860 WM8994_BIAS_SRC | 861 WM8994_VMID_DISCH | 862 WM8994_STARTUP_BIAS_ENA | 863 WM8994_VMID_BUF_ENA | 864 WM8994_VMID_RAMP_MASK, 865 WM8994_BIAS_SRC | 866 WM8994_STARTUP_BIAS_ENA | 867 WM8994_VMID_BUF_ENA | 868 (0x2 << WM8994_VMID_RAMP_SHIFT)); 869 870 /* Main bias enable, VMID=2x40k */ 871 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 872 WM8994_BIAS_ENA | 873 WM8994_VMID_SEL_MASK, 874 WM8994_BIAS_ENA | 0x2); 875 876 msleep(300); 877 878 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 879 WM8994_VMID_RAMP_MASK | 880 WM8994_BIAS_SRC, 881 0); 882 break; 883 884 case WM8994_VMID_FORCE: 885 /* Startup bias, slow VMID ramp & buffer */ 886 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 887 WM8994_BIAS_SRC | 888 WM8994_VMID_DISCH | 889 WM8994_STARTUP_BIAS_ENA | 890 WM8994_VMID_BUF_ENA | 891 WM8994_VMID_RAMP_MASK, 892 WM8994_BIAS_SRC | 893 WM8994_STARTUP_BIAS_ENA | 894 WM8994_VMID_BUF_ENA | 895 (0x2 << WM8994_VMID_RAMP_SHIFT)); 896 897 /* Main bias enable, VMID=2x40k */ 898 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 899 WM8994_BIAS_ENA | 900 WM8994_VMID_SEL_MASK, 901 WM8994_BIAS_ENA | 0x2); 902 903 msleep(400); 904 905 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 906 WM8994_VMID_RAMP_MASK | 907 WM8994_BIAS_SRC, 908 0); 909 break; 910 } 911 } 912 } 913 914 static void vmid_dereference(struct snd_soc_codec *codec) 915 { 916 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 917 918 wm8994->vmid_refcount--; 919 920 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", 921 wm8994->vmid_refcount); 922 923 if (wm8994->vmid_refcount == 0) { 924 if (wm8994->hubs.lineout1_se) 925 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 926 WM8994_LINEOUT1N_ENA | 927 WM8994_LINEOUT1P_ENA, 928 WM8994_LINEOUT1N_ENA | 929 WM8994_LINEOUT1P_ENA); 930 931 if (wm8994->hubs.lineout2_se) 932 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 933 WM8994_LINEOUT2N_ENA | 934 WM8994_LINEOUT2P_ENA, 935 WM8994_LINEOUT2N_ENA | 936 WM8994_LINEOUT2P_ENA); 937 938 /* Start discharging VMID */ 939 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 940 WM8994_BIAS_SRC | 941 WM8994_VMID_DISCH, 942 WM8994_BIAS_SRC | 943 WM8994_VMID_DISCH); 944 945 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 946 WM8994_VMID_SEL_MASK, 0); 947 948 msleep(400); 949 950 /* Active discharge */ 951 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 952 WM8994_LINEOUT1_DISCH | 953 WM8994_LINEOUT2_DISCH, 954 WM8994_LINEOUT1_DISCH | 955 WM8994_LINEOUT2_DISCH); 956 957 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 958 WM8994_LINEOUT1N_ENA | 959 WM8994_LINEOUT1P_ENA | 960 WM8994_LINEOUT2N_ENA | 961 WM8994_LINEOUT2P_ENA, 0); 962 963 /* Switch off startup biases */ 964 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 965 WM8994_BIAS_SRC | 966 WM8994_STARTUP_BIAS_ENA | 967 WM8994_VMID_BUF_ENA | 968 WM8994_VMID_RAMP_MASK, 0); 969 970 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 971 WM8994_VMID_SEL_MASK, 0); 972 } 973 974 pm_runtime_put(codec->dev); 975 } 976 977 static int vmid_event(struct snd_soc_dapm_widget *w, 978 struct snd_kcontrol *kcontrol, int event) 979 { 980 struct snd_soc_codec *codec = w->codec; 981 982 switch (event) { 983 case SND_SOC_DAPM_PRE_PMU: 984 vmid_reference(codec); 985 break; 986 987 case SND_SOC_DAPM_POST_PMD: 988 vmid_dereference(codec); 989 break; 990 } 991 992 return 0; 993 } 994 995 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec) 996 { 997 int source = 0; /* GCC flow analysis can't track enable */ 998 int reg, reg_r; 999 1000 /* We also need the same AIF source for L/R and only one path */ 1001 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 1002 switch (reg) { 1003 case WM8994_AIF2DACL_TO_DAC1L: 1004 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 1005 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1006 break; 1007 case WM8994_AIF1DAC2L_TO_DAC1L: 1008 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 1009 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1010 break; 1011 case WM8994_AIF1DAC1L_TO_DAC1L: 1012 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 1013 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1014 break; 1015 default: 1016 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 1017 return false; 1018 } 1019 1020 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1021 if (reg_r != reg) { 1022 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 1023 return false; 1024 } 1025 1026 /* Set the source up */ 1027 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1028 WM8994_CP_DYN_SRC_SEL_MASK, source); 1029 1030 return true; 1031 } 1032 1033 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1034 struct snd_kcontrol *kcontrol, int event) 1035 { 1036 struct snd_soc_codec *codec = w->codec; 1037 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1038 struct wm8994 *control = wm8994->wm8994; 1039 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1040 int i; 1041 int dac; 1042 int adc; 1043 int val; 1044 1045 switch (control->type) { 1046 case WM8994: 1047 case WM8958: 1048 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 switch (event) { 1055 case SND_SOC_DAPM_PRE_PMU: 1056 /* Don't enable timeslot 2 if not in use */ 1057 if (wm8994->channels[0] <= 2) 1058 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1059 1060 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1); 1061 if ((val & WM8994_AIF1ADCL_SRC) && 1062 (val & WM8994_AIF1ADCR_SRC)) 1063 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1064 else if (!(val & WM8994_AIF1ADCL_SRC) && 1065 !(val & WM8994_AIF1ADCR_SRC)) 1066 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1067 else 1068 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1069 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1070 1071 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2); 1072 if ((val & WM8994_AIF1DACL_SRC) && 1073 (val & WM8994_AIF1DACR_SRC)) 1074 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1075 else if (!(val & WM8994_AIF1DACL_SRC) && 1076 !(val & WM8994_AIF1DACR_SRC)) 1077 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1078 else 1079 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1080 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1081 1082 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1083 mask, adc); 1084 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1085 mask, dac); 1086 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1087 WM8994_AIF1DSPCLK_ENA | 1088 WM8994_SYSDSPCLK_ENA, 1089 WM8994_AIF1DSPCLK_ENA | 1090 WM8994_SYSDSPCLK_ENA); 1091 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask, 1092 WM8994_AIF1ADC1R_ENA | 1093 WM8994_AIF1ADC1L_ENA | 1094 WM8994_AIF1ADC2R_ENA | 1095 WM8994_AIF1ADC2L_ENA); 1096 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask, 1097 WM8994_AIF1DAC1R_ENA | 1098 WM8994_AIF1DAC1L_ENA | 1099 WM8994_AIF1DAC2R_ENA | 1100 WM8994_AIF1DAC2L_ENA); 1101 break; 1102 1103 case SND_SOC_DAPM_POST_PMU: 1104 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1105 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1106 snd_soc_read(codec, 1107 wm8994_vu_bits[i].reg)); 1108 break; 1109 1110 case SND_SOC_DAPM_PRE_PMD: 1111 case SND_SOC_DAPM_POST_PMD: 1112 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1113 mask, 0); 1114 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1115 mask, 0); 1116 1117 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1118 if (val & WM8994_AIF2DSPCLK_ENA) 1119 val = WM8994_SYSDSPCLK_ENA; 1120 else 1121 val = 0; 1122 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1123 WM8994_SYSDSPCLK_ENA | 1124 WM8994_AIF1DSPCLK_ENA, val); 1125 break; 1126 } 1127 1128 return 0; 1129 } 1130 1131 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1132 struct snd_kcontrol *kcontrol, int event) 1133 { 1134 struct snd_soc_codec *codec = w->codec; 1135 int i; 1136 int dac; 1137 int adc; 1138 int val; 1139 1140 switch (event) { 1141 case SND_SOC_DAPM_PRE_PMU: 1142 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1); 1143 if ((val & WM8994_AIF2ADCL_SRC) && 1144 (val & WM8994_AIF2ADCR_SRC)) 1145 adc = WM8994_AIF2ADCR_ENA; 1146 else if (!(val & WM8994_AIF2ADCL_SRC) && 1147 !(val & WM8994_AIF2ADCR_SRC)) 1148 adc = WM8994_AIF2ADCL_ENA; 1149 else 1150 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1151 1152 1153 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2); 1154 if ((val & WM8994_AIF2DACL_SRC) && 1155 (val & WM8994_AIF2DACR_SRC)) 1156 dac = WM8994_AIF2DACR_ENA; 1157 else if (!(val & WM8994_AIF2DACL_SRC) && 1158 !(val & WM8994_AIF2DACR_SRC)) 1159 dac = WM8994_AIF2DACL_ENA; 1160 else 1161 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1162 1163 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1164 WM8994_AIF2ADCL_ENA | 1165 WM8994_AIF2ADCR_ENA, adc); 1166 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1167 WM8994_AIF2DACL_ENA | 1168 WM8994_AIF2DACR_ENA, dac); 1169 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1170 WM8994_AIF2DSPCLK_ENA | 1171 WM8994_SYSDSPCLK_ENA, 1172 WM8994_AIF2DSPCLK_ENA | 1173 WM8994_SYSDSPCLK_ENA); 1174 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1175 WM8994_AIF2ADCL_ENA | 1176 WM8994_AIF2ADCR_ENA, 1177 WM8994_AIF2ADCL_ENA | 1178 WM8994_AIF2ADCR_ENA); 1179 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1180 WM8994_AIF2DACL_ENA | 1181 WM8994_AIF2DACR_ENA, 1182 WM8994_AIF2DACL_ENA | 1183 WM8994_AIF2DACR_ENA); 1184 break; 1185 1186 case SND_SOC_DAPM_POST_PMU: 1187 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1188 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1189 snd_soc_read(codec, 1190 wm8994_vu_bits[i].reg)); 1191 break; 1192 1193 case SND_SOC_DAPM_PRE_PMD: 1194 case SND_SOC_DAPM_POST_PMD: 1195 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1196 WM8994_AIF2DACL_ENA | 1197 WM8994_AIF2DACR_ENA, 0); 1198 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1199 WM8994_AIF2ADCL_ENA | 1200 WM8994_AIF2ADCR_ENA, 0); 1201 1202 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1203 if (val & WM8994_AIF1DSPCLK_ENA) 1204 val = WM8994_SYSDSPCLK_ENA; 1205 else 1206 val = 0; 1207 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1208 WM8994_SYSDSPCLK_ENA | 1209 WM8994_AIF2DSPCLK_ENA, val); 1210 break; 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1217 struct snd_kcontrol *kcontrol, int event) 1218 { 1219 struct snd_soc_codec *codec = w->codec; 1220 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1221 1222 switch (event) { 1223 case SND_SOC_DAPM_PRE_PMU: 1224 wm8994->aif1clk_enable = 1; 1225 break; 1226 case SND_SOC_DAPM_POST_PMD: 1227 wm8994->aif1clk_disable = 1; 1228 break; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1235 struct snd_kcontrol *kcontrol, int event) 1236 { 1237 struct snd_soc_codec *codec = w->codec; 1238 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1239 1240 switch (event) { 1241 case SND_SOC_DAPM_PRE_PMU: 1242 wm8994->aif2clk_enable = 1; 1243 break; 1244 case SND_SOC_DAPM_POST_PMD: 1245 wm8994->aif2clk_disable = 1; 1246 break; 1247 } 1248 1249 return 0; 1250 } 1251 1252 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1253 struct snd_kcontrol *kcontrol, int event) 1254 { 1255 struct snd_soc_codec *codec = w->codec; 1256 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1257 1258 switch (event) { 1259 case SND_SOC_DAPM_PRE_PMU: 1260 if (wm8994->aif1clk_enable) { 1261 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1262 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1263 WM8994_AIF1CLK_ENA_MASK, 1264 WM8994_AIF1CLK_ENA); 1265 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1266 wm8994->aif1clk_enable = 0; 1267 } 1268 if (wm8994->aif2clk_enable) { 1269 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1270 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1271 WM8994_AIF2CLK_ENA_MASK, 1272 WM8994_AIF2CLK_ENA); 1273 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1274 wm8994->aif2clk_enable = 0; 1275 } 1276 break; 1277 } 1278 1279 /* We may also have postponed startup of DSP, handle that. */ 1280 wm8958_aif_ev(w, kcontrol, event); 1281 1282 return 0; 1283 } 1284 1285 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1286 struct snd_kcontrol *kcontrol, int event) 1287 { 1288 struct snd_soc_codec *codec = w->codec; 1289 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1290 1291 switch (event) { 1292 case SND_SOC_DAPM_POST_PMD: 1293 if (wm8994->aif1clk_disable) { 1294 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1295 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1296 WM8994_AIF1CLK_ENA_MASK, 0); 1297 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1298 wm8994->aif1clk_disable = 0; 1299 } 1300 if (wm8994->aif2clk_disable) { 1301 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1302 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1303 WM8994_AIF2CLK_ENA_MASK, 0); 1304 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1305 wm8994->aif2clk_disable = 0; 1306 } 1307 break; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1314 struct snd_kcontrol *kcontrol, int event) 1315 { 1316 late_enable_ev(w, kcontrol, event); 1317 return 0; 1318 } 1319 1320 static int micbias_ev(struct snd_soc_dapm_widget *w, 1321 struct snd_kcontrol *kcontrol, int event) 1322 { 1323 late_enable_ev(w, kcontrol, event); 1324 return 0; 1325 } 1326 1327 static int dac_ev(struct snd_soc_dapm_widget *w, 1328 struct snd_kcontrol *kcontrol, int event) 1329 { 1330 struct snd_soc_codec *codec = w->codec; 1331 unsigned int mask = 1 << w->shift; 1332 1333 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1334 mask, mask); 1335 return 0; 1336 } 1337 1338 static const char *adc_mux_text[] = { 1339 "ADC", 1340 "DMIC", 1341 }; 1342 1343 static const struct soc_enum adc_enum = 1344 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 1345 1346 static const struct snd_kcontrol_new adcl_mux = 1347 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1348 1349 static const struct snd_kcontrol_new adcr_mux = 1350 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1351 1352 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1353 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1354 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1355 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1356 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1357 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1358 }; 1359 1360 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1361 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1362 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1363 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1364 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1365 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1366 }; 1367 1368 /* Debugging; dump chip status after DAPM transitions */ 1369 static int post_ev(struct snd_soc_dapm_widget *w, 1370 struct snd_kcontrol *kcontrol, int event) 1371 { 1372 struct snd_soc_codec *codec = w->codec; 1373 dev_dbg(codec->dev, "SRC status: %x\n", 1374 snd_soc_read(codec, 1375 WM8994_RATE_STATUS)); 1376 return 0; 1377 } 1378 1379 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1380 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1381 1, 1, 0), 1382 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1383 0, 1, 0), 1384 }; 1385 1386 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1387 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1388 1, 1, 0), 1389 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1390 0, 1, 0), 1391 }; 1392 1393 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1394 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1395 1, 1, 0), 1396 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1397 0, 1, 0), 1398 }; 1399 1400 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1401 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1402 1, 1, 0), 1403 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1404 0, 1, 0), 1405 }; 1406 1407 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1408 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1409 5, 1, 0), 1410 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1411 4, 1, 0), 1412 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1413 2, 1, 0), 1414 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1415 1, 1, 0), 1416 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1417 0, 1, 0), 1418 }; 1419 1420 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1421 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1422 5, 1, 0), 1423 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1424 4, 1, 0), 1425 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1426 2, 1, 0), 1427 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1428 1, 1, 0), 1429 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1430 0, 1, 0), 1431 }; 1432 1433 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1434 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 1435 snd_soc_get_volsw, wm8994_put_class_w) 1436 1437 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1438 struct snd_ctl_elem_value *ucontrol) 1439 { 1440 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 1441 struct snd_soc_dapm_widget *w = wlist->widgets[0]; 1442 struct snd_soc_codec *codec = w->codec; 1443 int ret; 1444 1445 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1446 1447 wm_hubs_update_class_w(codec); 1448 1449 return ret; 1450 } 1451 1452 static const struct snd_kcontrol_new dac1l_mix[] = { 1453 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1454 5, 1, 0), 1455 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1456 4, 1, 0), 1457 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1458 2, 1, 0), 1459 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1460 1, 1, 0), 1461 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1462 0, 1, 0), 1463 }; 1464 1465 static const struct snd_kcontrol_new dac1r_mix[] = { 1466 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1467 5, 1, 0), 1468 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1469 4, 1, 0), 1470 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1471 2, 1, 0), 1472 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1473 1, 1, 0), 1474 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1475 0, 1, 0), 1476 }; 1477 1478 static const char *sidetone_text[] = { 1479 "ADC/DMIC1", "DMIC2", 1480 }; 1481 1482 static const struct soc_enum sidetone1_enum = 1483 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1484 1485 static const struct snd_kcontrol_new sidetone1_mux = 1486 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1487 1488 static const struct soc_enum sidetone2_enum = 1489 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1490 1491 static const struct snd_kcontrol_new sidetone2_mux = 1492 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1493 1494 static const char *aif1dac_text[] = { 1495 "AIF1DACDAT", "AIF3DACDAT", 1496 }; 1497 1498 static const char *loopback_text[] = { 1499 "None", "ADCDAT", 1500 }; 1501 1502 static const struct soc_enum aif1_loopback_enum = 1503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2, 1504 loopback_text); 1505 1506 static const struct snd_kcontrol_new aif1_loopback = 1507 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum); 1508 1509 static const struct soc_enum aif2_loopback_enum = 1510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2, 1511 loopback_text); 1512 1513 static const struct snd_kcontrol_new aif2_loopback = 1514 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum); 1515 1516 static const struct soc_enum aif1dac_enum = 1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1518 1519 static const struct snd_kcontrol_new aif1dac_mux = 1520 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1521 1522 static const char *aif2dac_text[] = { 1523 "AIF2DACDAT", "AIF3DACDAT", 1524 }; 1525 1526 static const struct soc_enum aif2dac_enum = 1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1528 1529 static const struct snd_kcontrol_new aif2dac_mux = 1530 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1531 1532 static const char *aif2adc_text[] = { 1533 "AIF2ADCDAT", "AIF3DACDAT", 1534 }; 1535 1536 static const struct soc_enum aif2adc_enum = 1537 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1538 1539 static const struct snd_kcontrol_new aif2adc_mux = 1540 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1541 1542 static const char *aif3adc_text[] = { 1543 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1544 }; 1545 1546 static const struct soc_enum wm8994_aif3adc_enum = 1547 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1548 1549 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1550 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1551 1552 static const struct soc_enum wm8958_aif3adc_enum = 1553 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1554 1555 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1556 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1557 1558 static const char *mono_pcm_out_text[] = { 1559 "None", "AIF2ADCL", "AIF2ADCR", 1560 }; 1561 1562 static const struct soc_enum mono_pcm_out_enum = 1563 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1564 1565 static const struct snd_kcontrol_new mono_pcm_out_mux = 1566 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1567 1568 static const char *aif2dac_src_text[] = { 1569 "AIF2", "AIF3", 1570 }; 1571 1572 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1573 static const struct soc_enum aif2dacl_src_enum = 1574 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1575 1576 static const struct snd_kcontrol_new aif2dacl_src_mux = 1577 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1578 1579 static const struct soc_enum aif2dacr_src_enum = 1580 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1581 1582 static const struct snd_kcontrol_new aif2dacr_src_mux = 1583 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1584 1585 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1586 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1587 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1588 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1590 1591 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1593 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1594 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1595 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1597 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1599 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1601 1602 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1603 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1605 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1606 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1607 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1608 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1609 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1610 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1612 1613 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1614 }; 1615 1616 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1617 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1618 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1619 SND_SOC_DAPM_PRE_PMD), 1620 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1622 SND_SOC_DAPM_PRE_PMD), 1623 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1624 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1625 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1626 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1627 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1628 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1629 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1630 }; 1631 1632 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1633 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1634 dac_ev, SND_SOC_DAPM_PRE_PMU), 1635 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1636 dac_ev, SND_SOC_DAPM_PRE_PMU), 1637 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1638 dac_ev, SND_SOC_DAPM_PRE_PMU), 1639 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1640 dac_ev, SND_SOC_DAPM_PRE_PMU), 1641 }; 1642 1643 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1644 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1645 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1646 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1647 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1648 }; 1649 1650 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1651 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1652 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1653 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1654 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1655 }; 1656 1657 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1658 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1659 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1660 }; 1661 1662 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1663 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1664 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1665 SND_SOC_DAPM_INPUT("Clock"), 1666 1667 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1668 SND_SOC_DAPM_PRE_PMU), 1669 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1670 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1671 1672 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1673 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1674 SND_SOC_DAPM_PRE_PMD), 1675 1676 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1677 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1678 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1679 1680 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1681 0, SND_SOC_NOPM, 9, 0), 1682 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1683 0, SND_SOC_NOPM, 8, 0), 1684 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1685 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1686 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1687 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1688 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1690 1691 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1692 0, SND_SOC_NOPM, 11, 0), 1693 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1694 0, SND_SOC_NOPM, 10, 0), 1695 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1696 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1697 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1698 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1699 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1701 1702 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1703 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1704 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1705 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1706 1707 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1708 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1709 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1710 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1711 1712 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1713 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1714 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1715 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1716 1717 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1718 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1719 1720 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1721 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1722 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1723 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1724 1725 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1726 SND_SOC_NOPM, 13, 0), 1727 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1728 SND_SOC_NOPM, 12, 0), 1729 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1730 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1731 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1732 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1733 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1734 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1735 1736 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1737 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1738 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1739 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1740 1741 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1742 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1743 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1744 1745 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1746 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1747 1748 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1749 1750 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1751 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1752 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1753 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1754 1755 /* Power is done with the muxes since the ADC power also controls the 1756 * downsampling chain, the chip will automatically manage the analogue 1757 * specific portions. 1758 */ 1759 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1760 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1761 1762 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback), 1763 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback), 1764 1765 SND_SOC_DAPM_POST("Debug log", post_ev), 1766 }; 1767 1768 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1769 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1770 }; 1771 1772 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1773 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1774 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1775 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1776 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1777 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1778 }; 1779 1780 static const struct snd_soc_dapm_route intercon[] = { 1781 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1782 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1783 1784 { "DSP1CLK", NULL, "CLK_SYS" }, 1785 { "DSP2CLK", NULL, "CLK_SYS" }, 1786 { "DSPINTCLK", NULL, "CLK_SYS" }, 1787 1788 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1789 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1790 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1791 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1792 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1793 1794 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1795 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1796 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1797 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1798 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1799 1800 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1801 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1802 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1803 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1804 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1805 1806 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1807 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1808 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1809 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1810 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1811 1812 { "AIF2ADCL", NULL, "AIF2CLK" }, 1813 { "AIF2ADCL", NULL, "DSP2CLK" }, 1814 { "AIF2ADCR", NULL, "AIF2CLK" }, 1815 { "AIF2ADCR", NULL, "DSP2CLK" }, 1816 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1817 1818 { "AIF2DACL", NULL, "AIF2CLK" }, 1819 { "AIF2DACL", NULL, "DSP2CLK" }, 1820 { "AIF2DACR", NULL, "AIF2CLK" }, 1821 { "AIF2DACR", NULL, "DSP2CLK" }, 1822 { "AIF2DACR", NULL, "DSPINTCLK" }, 1823 1824 { "DMIC1L", NULL, "DMIC1DAT" }, 1825 { "DMIC1L", NULL, "CLK_SYS" }, 1826 { "DMIC1R", NULL, "DMIC1DAT" }, 1827 { "DMIC1R", NULL, "CLK_SYS" }, 1828 { "DMIC2L", NULL, "DMIC2DAT" }, 1829 { "DMIC2L", NULL, "CLK_SYS" }, 1830 { "DMIC2R", NULL, "DMIC2DAT" }, 1831 { "DMIC2R", NULL, "CLK_SYS" }, 1832 1833 { "ADCL", NULL, "AIF1CLK" }, 1834 { "ADCL", NULL, "DSP1CLK" }, 1835 { "ADCL", NULL, "DSPINTCLK" }, 1836 1837 { "ADCR", NULL, "AIF1CLK" }, 1838 { "ADCR", NULL, "DSP1CLK" }, 1839 { "ADCR", NULL, "DSPINTCLK" }, 1840 1841 { "ADCL Mux", "ADC", "ADCL" }, 1842 { "ADCL Mux", "DMIC", "DMIC1L" }, 1843 { "ADCR Mux", "ADC", "ADCR" }, 1844 { "ADCR Mux", "DMIC", "DMIC1R" }, 1845 1846 { "DAC1L", NULL, "AIF1CLK" }, 1847 { "DAC1L", NULL, "DSP1CLK" }, 1848 { "DAC1L", NULL, "DSPINTCLK" }, 1849 1850 { "DAC1R", NULL, "AIF1CLK" }, 1851 { "DAC1R", NULL, "DSP1CLK" }, 1852 { "DAC1R", NULL, "DSPINTCLK" }, 1853 1854 { "DAC2L", NULL, "AIF2CLK" }, 1855 { "DAC2L", NULL, "DSP2CLK" }, 1856 { "DAC2L", NULL, "DSPINTCLK" }, 1857 1858 { "DAC2R", NULL, "AIF2DACR" }, 1859 { "DAC2R", NULL, "AIF2CLK" }, 1860 { "DAC2R", NULL, "DSP2CLK" }, 1861 { "DAC2R", NULL, "DSPINTCLK" }, 1862 1863 { "TOCLK", NULL, "CLK_SYS" }, 1864 1865 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1866 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1867 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1868 1869 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1870 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1871 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1872 1873 /* AIF1 outputs */ 1874 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1875 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1876 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1877 1878 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1879 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1880 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1881 1882 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1883 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1884 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1885 1886 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1887 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1888 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1889 1890 /* Pin level routing for AIF3 */ 1891 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1892 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1893 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1894 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1895 1896 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" }, 1897 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1898 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" }, 1899 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1900 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1901 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1902 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1903 1904 /* DAC1 inputs */ 1905 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1906 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1907 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1908 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1909 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1910 1911 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1912 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1913 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1914 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1915 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1916 1917 /* DAC2/AIF2 outputs */ 1918 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1919 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1920 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1921 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1922 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1923 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1924 1925 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1926 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1927 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1928 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1929 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1930 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1931 1932 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1933 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1934 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1935 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1936 1937 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1938 1939 /* AIF3 output */ 1940 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1941 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1942 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1943 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1944 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1945 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1946 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1947 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1948 1949 /* Loopback */ 1950 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" }, 1951 { "AIF1 Loopback", "None", "AIF1DACDAT" }, 1952 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" }, 1953 { "AIF2 Loopback", "None", "AIF2DACDAT" }, 1954 1955 /* Sidetone */ 1956 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1957 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1958 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1959 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1960 1961 /* Output stages */ 1962 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1963 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1964 1965 { "SPKL", "DAC1 Switch", "DAC1L" }, 1966 { "SPKL", "DAC2 Switch", "DAC2L" }, 1967 1968 { "SPKR", "DAC1 Switch", "DAC1R" }, 1969 { "SPKR", "DAC2 Switch", "DAC2R" }, 1970 1971 { "Left Headphone Mux", "DAC", "DAC1L" }, 1972 { "Right Headphone Mux", "DAC", "DAC1R" }, 1973 }; 1974 1975 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1976 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1977 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1978 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1979 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1980 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1981 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1982 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1983 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1984 }; 1985 1986 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1987 { "DAC1L", NULL, "DAC1L Mixer" }, 1988 { "DAC1R", NULL, "DAC1R Mixer" }, 1989 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1990 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1991 }; 1992 1993 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1994 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1995 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 1996 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 1997 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 1998 { "MICBIAS1", NULL, "CLK_SYS" }, 1999 { "MICBIAS1", NULL, "MICBIAS Supply" }, 2000 { "MICBIAS2", NULL, "CLK_SYS" }, 2001 { "MICBIAS2", NULL, "MICBIAS Supply" }, 2002 }; 2003 2004 static const struct snd_soc_dapm_route wm8994_intercon[] = { 2005 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2006 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2007 { "MICBIAS1", NULL, "VMID" }, 2008 { "MICBIAS2", NULL, "VMID" }, 2009 }; 2010 2011 static const struct snd_soc_dapm_route wm8958_intercon[] = { 2012 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 2013 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 2014 2015 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 2016 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 2017 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 2018 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 2019 2020 { "AIF3DACDAT", NULL, "AIF3" }, 2021 { "AIF3ADCDAT", NULL, "AIF3" }, 2022 2023 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2024 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2025 2026 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2027 }; 2028 2029 /* The size in bits of the FLL divide multiplied by 10 2030 * to allow rounding later */ 2031 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2032 2033 struct fll_div { 2034 u16 outdiv; 2035 u16 n; 2036 u16 k; 2037 u16 lambda; 2038 u16 clk_ref_div; 2039 u16 fll_fratio; 2040 }; 2041 2042 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll, 2043 int freq_in, int freq_out) 2044 { 2045 u64 Kpart; 2046 unsigned int K, Ndiv, Nmod, gcd_fll; 2047 2048 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2049 2050 /* Scale the input frequency down to <= 13.5MHz */ 2051 fll->clk_ref_div = 0; 2052 while (freq_in > 13500000) { 2053 fll->clk_ref_div++; 2054 freq_in /= 2; 2055 2056 if (fll->clk_ref_div > 3) 2057 return -EINVAL; 2058 } 2059 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2060 2061 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2062 fll->outdiv = 3; 2063 while (freq_out * (fll->outdiv + 1) < 90000000) { 2064 fll->outdiv++; 2065 if (fll->outdiv > 63) 2066 return -EINVAL; 2067 } 2068 freq_out *= fll->outdiv + 1; 2069 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2070 2071 if (freq_in > 1000000) { 2072 fll->fll_fratio = 0; 2073 } else if (freq_in > 256000) { 2074 fll->fll_fratio = 1; 2075 freq_in *= 2; 2076 } else if (freq_in > 128000) { 2077 fll->fll_fratio = 2; 2078 freq_in *= 4; 2079 } else if (freq_in > 64000) { 2080 fll->fll_fratio = 3; 2081 freq_in *= 8; 2082 } else { 2083 fll->fll_fratio = 4; 2084 freq_in *= 16; 2085 } 2086 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2087 2088 /* Now, calculate N.K */ 2089 Ndiv = freq_out / freq_in; 2090 2091 fll->n = Ndiv; 2092 Nmod = freq_out % freq_in; 2093 pr_debug("Nmod=%d\n", Nmod); 2094 2095 switch (control->type) { 2096 case WM8994: 2097 /* Calculate fractional part - scale up so we can round. */ 2098 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2099 2100 do_div(Kpart, freq_in); 2101 2102 K = Kpart & 0xFFFFFFFF; 2103 2104 if ((K % 10) >= 5) 2105 K += 5; 2106 2107 /* Move down to proper range now rounding is done */ 2108 fll->k = K / 10; 2109 fll->lambda = 0; 2110 2111 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2112 break; 2113 2114 default: 2115 gcd_fll = gcd(freq_out, freq_in); 2116 2117 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; 2118 fll->lambda = freq_in / gcd_fll; 2119 2120 } 2121 2122 return 0; 2123 } 2124 2125 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 2126 unsigned int freq_in, unsigned int freq_out) 2127 { 2128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2129 struct wm8994 *control = wm8994->wm8994; 2130 int reg_offset, ret; 2131 struct fll_div fll; 2132 u16 reg, clk1, aif_reg, aif_src; 2133 unsigned long timeout; 2134 bool was_enabled; 2135 2136 switch (id) { 2137 case WM8994_FLL1: 2138 reg_offset = 0; 2139 id = 0; 2140 aif_src = 0x10; 2141 break; 2142 case WM8994_FLL2: 2143 reg_offset = 0x20; 2144 id = 1; 2145 aif_src = 0x18; 2146 break; 2147 default: 2148 return -EINVAL; 2149 } 2150 2151 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); 2152 was_enabled = reg & WM8994_FLL1_ENA; 2153 2154 switch (src) { 2155 case 0: 2156 /* Allow no source specification when stopping */ 2157 if (freq_out) 2158 return -EINVAL; 2159 src = wm8994->fll[id].src; 2160 break; 2161 case WM8994_FLL_SRC_MCLK1: 2162 case WM8994_FLL_SRC_MCLK2: 2163 case WM8994_FLL_SRC_LRCLK: 2164 case WM8994_FLL_SRC_BCLK: 2165 break; 2166 case WM8994_FLL_SRC_INTERNAL: 2167 freq_in = 12000000; 2168 freq_out = 12000000; 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 /* Are we changing anything? */ 2175 if (wm8994->fll[id].src == src && 2176 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2177 return 0; 2178 2179 /* If we're stopping the FLL redo the old config - no 2180 * registers will actually be written but we avoid GCC flow 2181 * analysis bugs spewing warnings. 2182 */ 2183 if (freq_out) 2184 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out); 2185 else 2186 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in, 2187 wm8994->fll[id].out); 2188 if (ret < 0) 2189 return ret; 2190 2191 /* Make sure that we're not providing SYSCLK right now */ 2192 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1); 2193 if (clk1 & WM8994_SYSCLK_SRC) 2194 aif_reg = WM8994_AIF2_CLOCKING_1; 2195 else 2196 aif_reg = WM8994_AIF1_CLOCKING_1; 2197 reg = snd_soc_read(codec, aif_reg); 2198 2199 if ((reg & WM8994_AIF1CLK_ENA) && 2200 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2201 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n", 2202 id + 1); 2203 return -EBUSY; 2204 } 2205 2206 /* We always need to disable the FLL while reconfiguring */ 2207 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2208 WM8994_FLL1_ENA, 0); 2209 2210 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2211 freq_in == freq_out && freq_out) { 2212 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1); 2213 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2214 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2215 goto out; 2216 } 2217 2218 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2219 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2220 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2221 WM8994_FLL1_OUTDIV_MASK | 2222 WM8994_FLL1_FRATIO_MASK, reg); 2223 2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, 2225 WM8994_FLL1_K_MASK, fll.k); 2226 2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 2228 WM8994_FLL1_N_MASK, 2229 fll.n << WM8994_FLL1_N_SHIFT); 2230 2231 if (fll.lambda) { 2232 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset, 2233 WM8958_FLL1_LAMBDA_MASK, 2234 fll.lambda); 2235 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset, 2236 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA); 2237 } else { 2238 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset, 2239 WM8958_FLL1_EFS_ENA, 0); 2240 } 2241 2242 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2243 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2244 WM8994_FLL1_REFCLK_DIV_MASK | 2245 WM8994_FLL1_REFCLK_SRC_MASK, 2246 ((src == WM8994_FLL_SRC_INTERNAL) 2247 << WM8994_FLL1_FRC_NCO_SHIFT) | 2248 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2249 (src - 1)); 2250 2251 /* Clear any pending completion from a previous failure */ 2252 try_wait_for_completion(&wm8994->fll_locked[id]); 2253 2254 /* Enable (with fractional mode if required) */ 2255 if (freq_out) { 2256 /* Enable VMID if we need it */ 2257 if (!was_enabled) { 2258 active_reference(codec); 2259 2260 switch (control->type) { 2261 case WM8994: 2262 vmid_reference(codec); 2263 break; 2264 case WM8958: 2265 if (control->revision < 1) 2266 vmid_reference(codec); 2267 break; 2268 default: 2269 break; 2270 } 2271 } 2272 2273 reg = WM8994_FLL1_ENA; 2274 2275 if (fll.k) 2276 reg |= WM8994_FLL1_FRAC; 2277 if (src == WM8994_FLL_SRC_INTERNAL) 2278 reg |= WM8994_FLL1_OSC_ENA; 2279 2280 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2281 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2282 WM8994_FLL1_FRAC, reg); 2283 2284 if (wm8994->fll_locked_irq) { 2285 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2286 msecs_to_jiffies(10)); 2287 if (timeout == 0) 2288 dev_warn(codec->dev, 2289 "Timed out waiting for FLL lock\n"); 2290 } else { 2291 msleep(5); 2292 } 2293 } else { 2294 if (was_enabled) { 2295 switch (control->type) { 2296 case WM8994: 2297 vmid_dereference(codec); 2298 break; 2299 case WM8958: 2300 if (control->revision < 1) 2301 vmid_dereference(codec); 2302 break; 2303 default: 2304 break; 2305 } 2306 2307 active_dereference(codec); 2308 } 2309 } 2310 2311 out: 2312 wm8994->fll[id].in = freq_in; 2313 wm8994->fll[id].out = freq_out; 2314 wm8994->fll[id].src = src; 2315 2316 configure_clock(codec); 2317 2318 /* 2319 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2320 * for detection. 2321 */ 2322 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2323 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2324 2325 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) 2326 & WM8994_AIF1CLK_RATE_MASK; 2327 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) 2328 & WM8994_AIF1CLK_RATE_MASK; 2329 2330 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2331 WM8994_AIF1CLK_RATE_MASK, 0x1); 2332 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2333 WM8994_AIF2CLK_RATE_MASK, 0x1); 2334 } else if (wm8994->aifdiv[0]) { 2335 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2336 WM8994_AIF1CLK_RATE_MASK, 2337 wm8994->aifdiv[0]); 2338 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2339 WM8994_AIF2CLK_RATE_MASK, 2340 wm8994->aifdiv[1]); 2341 2342 wm8994->aifdiv[0] = 0; 2343 wm8994->aifdiv[1] = 0; 2344 } 2345 2346 return 0; 2347 } 2348 2349 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2350 { 2351 struct completion *completion = data; 2352 2353 complete(completion); 2354 2355 return IRQ_HANDLED; 2356 } 2357 2358 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2359 2360 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2361 unsigned int freq_in, unsigned int freq_out) 2362 { 2363 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 2364 } 2365 2366 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2367 int clk_id, unsigned int freq, int dir) 2368 { 2369 struct snd_soc_codec *codec = dai->codec; 2370 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2371 int i; 2372 2373 switch (dai->id) { 2374 case 1: 2375 case 2: 2376 break; 2377 2378 default: 2379 /* AIF3 shares clocking with AIF1/2 */ 2380 return -EINVAL; 2381 } 2382 2383 switch (clk_id) { 2384 case WM8994_SYSCLK_MCLK1: 2385 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2386 wm8994->mclk[0] = freq; 2387 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2388 dai->id, freq); 2389 break; 2390 2391 case WM8994_SYSCLK_MCLK2: 2392 /* TODO: Set GPIO AF */ 2393 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2394 wm8994->mclk[1] = freq; 2395 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2396 dai->id, freq); 2397 break; 2398 2399 case WM8994_SYSCLK_FLL1: 2400 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2401 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2402 break; 2403 2404 case WM8994_SYSCLK_FLL2: 2405 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2406 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2407 break; 2408 2409 case WM8994_SYSCLK_OPCLK: 2410 /* Special case - a division (times 10) is given and 2411 * no effect on main clocking. 2412 */ 2413 if (freq) { 2414 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2415 if (opclk_divs[i] == freq) 2416 break; 2417 if (i == ARRAY_SIZE(opclk_divs)) 2418 return -EINVAL; 2419 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 2420 WM8994_OPCLK_DIV_MASK, i); 2421 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2422 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2423 } else { 2424 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2425 WM8994_OPCLK_ENA, 0); 2426 } 2427 2428 default: 2429 return -EINVAL; 2430 } 2431 2432 configure_clock(codec); 2433 2434 /* 2435 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2436 * for detection. 2437 */ 2438 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2439 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2440 2441 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) 2442 & WM8994_AIF1CLK_RATE_MASK; 2443 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) 2444 & WM8994_AIF1CLK_RATE_MASK; 2445 2446 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2447 WM8994_AIF1CLK_RATE_MASK, 0x1); 2448 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2449 WM8994_AIF2CLK_RATE_MASK, 0x1); 2450 } else if (wm8994->aifdiv[0]) { 2451 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2452 WM8994_AIF1CLK_RATE_MASK, 2453 wm8994->aifdiv[0]); 2454 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2455 WM8994_AIF2CLK_RATE_MASK, 2456 wm8994->aifdiv[1]); 2457 2458 wm8994->aifdiv[0] = 0; 2459 wm8994->aifdiv[1] = 0; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2466 enum snd_soc_bias_level level) 2467 { 2468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2469 struct wm8994 *control = wm8994->wm8994; 2470 2471 wm_hubs_set_bias_level(codec, level); 2472 2473 switch (level) { 2474 case SND_SOC_BIAS_ON: 2475 break; 2476 2477 case SND_SOC_BIAS_PREPARE: 2478 /* MICBIAS into regulating mode */ 2479 switch (control->type) { 2480 case WM8958: 2481 case WM1811: 2482 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2483 WM8958_MICB1_MODE, 0); 2484 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2485 WM8958_MICB2_MODE, 0); 2486 break; 2487 default: 2488 break; 2489 } 2490 2491 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2492 active_reference(codec); 2493 break; 2494 2495 case SND_SOC_BIAS_STANDBY: 2496 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2497 switch (control->type) { 2498 case WM8958: 2499 if (control->revision == 0) { 2500 /* Optimise performance for rev A */ 2501 snd_soc_update_bits(codec, 2502 WM8958_CHARGE_PUMP_2, 2503 WM8958_CP_DISCH, 2504 WM8958_CP_DISCH); 2505 } 2506 break; 2507 2508 default: 2509 break; 2510 } 2511 2512 /* Discharge LINEOUT1 & 2 */ 2513 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2514 WM8994_LINEOUT1_DISCH | 2515 WM8994_LINEOUT2_DISCH, 2516 WM8994_LINEOUT1_DISCH | 2517 WM8994_LINEOUT2_DISCH); 2518 } 2519 2520 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) 2521 active_dereference(codec); 2522 2523 /* MICBIAS into bypass mode on newer devices */ 2524 switch (control->type) { 2525 case WM8958: 2526 case WM1811: 2527 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2528 WM8958_MICB1_MODE, 2529 WM8958_MICB1_MODE); 2530 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2531 WM8958_MICB2_MODE, 2532 WM8958_MICB2_MODE); 2533 break; 2534 default: 2535 break; 2536 } 2537 break; 2538 2539 case SND_SOC_BIAS_OFF: 2540 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2541 wm8994->cur_fw = NULL; 2542 break; 2543 } 2544 2545 codec->dapm.bias_level = level; 2546 2547 return 0; 2548 } 2549 2550 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode) 2551 { 2552 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2553 2554 switch (mode) { 2555 case WM8994_VMID_NORMAL: 2556 if (wm8994->hubs.lineout1_se) { 2557 snd_soc_dapm_disable_pin(&codec->dapm, 2558 "LINEOUT1N Driver"); 2559 snd_soc_dapm_disable_pin(&codec->dapm, 2560 "LINEOUT1P Driver"); 2561 } 2562 if (wm8994->hubs.lineout2_se) { 2563 snd_soc_dapm_disable_pin(&codec->dapm, 2564 "LINEOUT2N Driver"); 2565 snd_soc_dapm_disable_pin(&codec->dapm, 2566 "LINEOUT2P Driver"); 2567 } 2568 2569 /* Do the sync with the old mode to allow it to clean up */ 2570 snd_soc_dapm_sync(&codec->dapm); 2571 wm8994->vmid_mode = mode; 2572 break; 2573 2574 case WM8994_VMID_FORCE: 2575 if (wm8994->hubs.lineout1_se) { 2576 snd_soc_dapm_force_enable_pin(&codec->dapm, 2577 "LINEOUT1N Driver"); 2578 snd_soc_dapm_force_enable_pin(&codec->dapm, 2579 "LINEOUT1P Driver"); 2580 } 2581 if (wm8994->hubs.lineout2_se) { 2582 snd_soc_dapm_force_enable_pin(&codec->dapm, 2583 "LINEOUT2N Driver"); 2584 snd_soc_dapm_force_enable_pin(&codec->dapm, 2585 "LINEOUT2P Driver"); 2586 } 2587 2588 wm8994->vmid_mode = mode; 2589 snd_soc_dapm_sync(&codec->dapm); 2590 break; 2591 2592 default: 2593 return -EINVAL; 2594 } 2595 2596 return 0; 2597 } 2598 2599 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2600 { 2601 struct snd_soc_codec *codec = dai->codec; 2602 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2603 struct wm8994 *control = wm8994->wm8994; 2604 int ms_reg; 2605 int aif1_reg; 2606 int dac_reg; 2607 int adc_reg; 2608 int ms = 0; 2609 int aif1 = 0; 2610 int lrclk = 0; 2611 2612 switch (dai->id) { 2613 case 1: 2614 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2615 aif1_reg = WM8994_AIF1_CONTROL_1; 2616 dac_reg = WM8994_AIF1DAC_LRCLK; 2617 adc_reg = WM8994_AIF1ADC_LRCLK; 2618 break; 2619 case 2: 2620 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2621 aif1_reg = WM8994_AIF2_CONTROL_1; 2622 dac_reg = WM8994_AIF1DAC_LRCLK; 2623 adc_reg = WM8994_AIF1ADC_LRCLK; 2624 break; 2625 default: 2626 return -EINVAL; 2627 } 2628 2629 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2630 case SND_SOC_DAIFMT_CBS_CFS: 2631 break; 2632 case SND_SOC_DAIFMT_CBM_CFM: 2633 ms = WM8994_AIF1_MSTR; 2634 break; 2635 default: 2636 return -EINVAL; 2637 } 2638 2639 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2640 case SND_SOC_DAIFMT_DSP_B: 2641 aif1 |= WM8994_AIF1_LRCLK_INV; 2642 lrclk |= WM8958_AIF1_LRCLK_INV; 2643 case SND_SOC_DAIFMT_DSP_A: 2644 aif1 |= 0x18; 2645 break; 2646 case SND_SOC_DAIFMT_I2S: 2647 aif1 |= 0x10; 2648 break; 2649 case SND_SOC_DAIFMT_RIGHT_J: 2650 break; 2651 case SND_SOC_DAIFMT_LEFT_J: 2652 aif1 |= 0x8; 2653 break; 2654 default: 2655 return -EINVAL; 2656 } 2657 2658 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2659 case SND_SOC_DAIFMT_DSP_A: 2660 case SND_SOC_DAIFMT_DSP_B: 2661 /* frame inversion not valid for DSP modes */ 2662 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2663 case SND_SOC_DAIFMT_NB_NF: 2664 break; 2665 case SND_SOC_DAIFMT_IB_NF: 2666 aif1 |= WM8994_AIF1_BCLK_INV; 2667 break; 2668 default: 2669 return -EINVAL; 2670 } 2671 break; 2672 2673 case SND_SOC_DAIFMT_I2S: 2674 case SND_SOC_DAIFMT_RIGHT_J: 2675 case SND_SOC_DAIFMT_LEFT_J: 2676 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2677 case SND_SOC_DAIFMT_NB_NF: 2678 break; 2679 case SND_SOC_DAIFMT_IB_IF: 2680 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2681 lrclk |= WM8958_AIF1_LRCLK_INV; 2682 break; 2683 case SND_SOC_DAIFMT_IB_NF: 2684 aif1 |= WM8994_AIF1_BCLK_INV; 2685 break; 2686 case SND_SOC_DAIFMT_NB_IF: 2687 aif1 |= WM8994_AIF1_LRCLK_INV; 2688 lrclk |= WM8958_AIF1_LRCLK_INV; 2689 break; 2690 default: 2691 return -EINVAL; 2692 } 2693 break; 2694 default: 2695 return -EINVAL; 2696 } 2697 2698 /* The AIF2 format configuration needs to be mirrored to AIF3 2699 * on WM8958 if it's in use so just do it all the time. */ 2700 switch (control->type) { 2701 case WM1811: 2702 case WM8958: 2703 if (dai->id == 2) 2704 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2705 WM8994_AIF1_LRCLK_INV | 2706 WM8958_AIF3_FMT_MASK, aif1); 2707 break; 2708 2709 default: 2710 break; 2711 } 2712 2713 snd_soc_update_bits(codec, aif1_reg, 2714 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2715 WM8994_AIF1_FMT_MASK, 2716 aif1); 2717 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2718 ms); 2719 snd_soc_update_bits(codec, dac_reg, 2720 WM8958_AIF1_LRCLK_INV, lrclk); 2721 snd_soc_update_bits(codec, adc_reg, 2722 WM8958_AIF1_LRCLK_INV, lrclk); 2723 2724 return 0; 2725 } 2726 2727 static struct { 2728 int val, rate; 2729 } srs[] = { 2730 { 0, 8000 }, 2731 { 1, 11025 }, 2732 { 2, 12000 }, 2733 { 3, 16000 }, 2734 { 4, 22050 }, 2735 { 5, 24000 }, 2736 { 6, 32000 }, 2737 { 7, 44100 }, 2738 { 8, 48000 }, 2739 { 9, 88200 }, 2740 { 10, 96000 }, 2741 }; 2742 2743 static int fs_ratios[] = { 2744 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2745 }; 2746 2747 static int bclk_divs[] = { 2748 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2749 640, 880, 960, 1280, 1760, 1920 2750 }; 2751 2752 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2753 struct snd_pcm_hw_params *params, 2754 struct snd_soc_dai *dai) 2755 { 2756 struct snd_soc_codec *codec = dai->codec; 2757 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2758 struct wm8994 *control = wm8994->wm8994; 2759 struct wm8994_pdata *pdata = &control->pdata; 2760 int aif1_reg; 2761 int aif2_reg; 2762 int bclk_reg; 2763 int lrclk_reg; 2764 int rate_reg; 2765 int aif1 = 0; 2766 int aif2 = 0; 2767 int bclk = 0; 2768 int lrclk = 0; 2769 int rate_val = 0; 2770 int id = dai->id - 1; 2771 2772 int i, cur_val, best_val, bclk_rate, best; 2773 2774 switch (dai->id) { 2775 case 1: 2776 aif1_reg = WM8994_AIF1_CONTROL_1; 2777 aif2_reg = WM8994_AIF1_CONTROL_2; 2778 bclk_reg = WM8994_AIF1_BCLK; 2779 rate_reg = WM8994_AIF1_RATE; 2780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2781 wm8994->lrclk_shared[0]) { 2782 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2783 } else { 2784 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2785 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2786 } 2787 break; 2788 case 2: 2789 aif1_reg = WM8994_AIF2_CONTROL_1; 2790 aif2_reg = WM8994_AIF2_CONTROL_2; 2791 bclk_reg = WM8994_AIF2_BCLK; 2792 rate_reg = WM8994_AIF2_RATE; 2793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2794 wm8994->lrclk_shared[1]) { 2795 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2796 } else { 2797 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2798 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2799 } 2800 break; 2801 default: 2802 return -EINVAL; 2803 } 2804 2805 bclk_rate = params_rate(params); 2806 switch (params_format(params)) { 2807 case SNDRV_PCM_FORMAT_S16_LE: 2808 bclk_rate *= 16; 2809 break; 2810 case SNDRV_PCM_FORMAT_S20_3LE: 2811 bclk_rate *= 20; 2812 aif1 |= 0x20; 2813 break; 2814 case SNDRV_PCM_FORMAT_S24_LE: 2815 bclk_rate *= 24; 2816 aif1 |= 0x40; 2817 break; 2818 case SNDRV_PCM_FORMAT_S32_LE: 2819 bclk_rate *= 32; 2820 aif1 |= 0x60; 2821 break; 2822 default: 2823 return -EINVAL; 2824 } 2825 2826 wm8994->channels[id] = params_channels(params); 2827 if (pdata->max_channels_clocked[id] && 2828 wm8994->channels[id] > pdata->max_channels_clocked[id]) { 2829 dev_dbg(dai->dev, "Constraining channels to %d from %d\n", 2830 pdata->max_channels_clocked[id], wm8994->channels[id]); 2831 wm8994->channels[id] = pdata->max_channels_clocked[id]; 2832 } 2833 2834 switch (wm8994->channels[id]) { 2835 case 1: 2836 case 2: 2837 bclk_rate *= 2; 2838 break; 2839 default: 2840 bclk_rate *= 4; 2841 break; 2842 } 2843 2844 /* Try to find an appropriate sample rate; look for an exact match. */ 2845 for (i = 0; i < ARRAY_SIZE(srs); i++) 2846 if (srs[i].rate == params_rate(params)) 2847 break; 2848 if (i == ARRAY_SIZE(srs)) 2849 return -EINVAL; 2850 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2851 2852 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2853 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2854 dai->id, wm8994->aifclk[id], bclk_rate); 2855 2856 if (wm8994->channels[id] == 1 && 2857 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2858 aif2 |= WM8994_AIF1_MONO; 2859 2860 if (wm8994->aifclk[id] == 0) { 2861 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2862 return -EINVAL; 2863 } 2864 2865 /* AIFCLK/fs ratio; look for a close match in either direction */ 2866 best = 0; 2867 best_val = abs((fs_ratios[0] * params_rate(params)) 2868 - wm8994->aifclk[id]); 2869 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2870 cur_val = abs((fs_ratios[i] * params_rate(params)) 2871 - wm8994->aifclk[id]); 2872 if (cur_val >= best_val) 2873 continue; 2874 best = i; 2875 best_val = cur_val; 2876 } 2877 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2878 dai->id, fs_ratios[best]); 2879 rate_val |= best; 2880 2881 /* We may not get quite the right frequency if using 2882 * approximate clocks so look for the closest match that is 2883 * higher than the target (we need to ensure that there enough 2884 * BCLKs to clock out the samples). 2885 */ 2886 best = 0; 2887 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2888 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2889 if (cur_val < 0) /* BCLK table is sorted */ 2890 break; 2891 best = i; 2892 } 2893 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2894 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2895 bclk_divs[best], bclk_rate); 2896 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2897 2898 lrclk = bclk_rate / params_rate(params); 2899 if (!lrclk) { 2900 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 2901 bclk_rate); 2902 return -EINVAL; 2903 } 2904 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2905 lrclk, bclk_rate / lrclk); 2906 2907 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2908 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2909 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2910 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2911 lrclk); 2912 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2913 WM8994_AIF1CLK_RATE_MASK, rate_val); 2914 2915 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2916 switch (dai->id) { 2917 case 1: 2918 wm8994->dac_rates[0] = params_rate(params); 2919 wm8994_set_retune_mobile(codec, 0); 2920 wm8994_set_retune_mobile(codec, 1); 2921 break; 2922 case 2: 2923 wm8994->dac_rates[1] = params_rate(params); 2924 wm8994_set_retune_mobile(codec, 2); 2925 break; 2926 } 2927 } 2928 2929 return 0; 2930 } 2931 2932 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2933 struct snd_pcm_hw_params *params, 2934 struct snd_soc_dai *dai) 2935 { 2936 struct snd_soc_codec *codec = dai->codec; 2937 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2938 struct wm8994 *control = wm8994->wm8994; 2939 int aif1_reg; 2940 int aif1 = 0; 2941 2942 switch (dai->id) { 2943 case 3: 2944 switch (control->type) { 2945 case WM1811: 2946 case WM8958: 2947 aif1_reg = WM8958_AIF3_CONTROL_1; 2948 break; 2949 default: 2950 return 0; 2951 } 2952 break; 2953 default: 2954 return 0; 2955 } 2956 2957 switch (params_format(params)) { 2958 case SNDRV_PCM_FORMAT_S16_LE: 2959 break; 2960 case SNDRV_PCM_FORMAT_S20_3LE: 2961 aif1 |= 0x20; 2962 break; 2963 case SNDRV_PCM_FORMAT_S24_LE: 2964 aif1 |= 0x40; 2965 break; 2966 case SNDRV_PCM_FORMAT_S32_LE: 2967 aif1 |= 0x60; 2968 break; 2969 default: 2970 return -EINVAL; 2971 } 2972 2973 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2974 } 2975 2976 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2977 { 2978 struct snd_soc_codec *codec = codec_dai->codec; 2979 int mute_reg; 2980 int reg; 2981 2982 switch (codec_dai->id) { 2983 case 1: 2984 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2985 break; 2986 case 2: 2987 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2988 break; 2989 default: 2990 return -EINVAL; 2991 } 2992 2993 if (mute) 2994 reg = WM8994_AIF1DAC1_MUTE; 2995 else 2996 reg = 0; 2997 2998 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2999 3000 return 0; 3001 } 3002 3003 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3004 { 3005 struct snd_soc_codec *codec = codec_dai->codec; 3006 int reg, val, mask; 3007 3008 switch (codec_dai->id) { 3009 case 1: 3010 reg = WM8994_AIF1_MASTER_SLAVE; 3011 mask = WM8994_AIF1_TRI; 3012 break; 3013 case 2: 3014 reg = WM8994_AIF2_MASTER_SLAVE; 3015 mask = WM8994_AIF2_TRI; 3016 break; 3017 default: 3018 return -EINVAL; 3019 } 3020 3021 if (tristate) 3022 val = mask; 3023 else 3024 val = 0; 3025 3026 return snd_soc_update_bits(codec, reg, mask, val); 3027 } 3028 3029 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 3030 { 3031 struct snd_soc_codec *codec = dai->codec; 3032 3033 /* Disable the pulls on the AIF if we're using it to save power. */ 3034 snd_soc_update_bits(codec, WM8994_GPIO_3, 3035 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3036 snd_soc_update_bits(codec, WM8994_GPIO_4, 3037 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3038 snd_soc_update_bits(codec, WM8994_GPIO_5, 3039 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3040 3041 return 0; 3042 } 3043 3044 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3045 3046 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3047 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3048 3049 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3050 .set_sysclk = wm8994_set_dai_sysclk, 3051 .set_fmt = wm8994_set_dai_fmt, 3052 .hw_params = wm8994_hw_params, 3053 .digital_mute = wm8994_aif_mute, 3054 .set_pll = wm8994_set_fll, 3055 .set_tristate = wm8994_set_tristate, 3056 }; 3057 3058 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3059 .set_sysclk = wm8994_set_dai_sysclk, 3060 .set_fmt = wm8994_set_dai_fmt, 3061 .hw_params = wm8994_hw_params, 3062 .digital_mute = wm8994_aif_mute, 3063 .set_pll = wm8994_set_fll, 3064 .set_tristate = wm8994_set_tristate, 3065 }; 3066 3067 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3068 .hw_params = wm8994_aif3_hw_params, 3069 }; 3070 3071 static struct snd_soc_dai_driver wm8994_dai[] = { 3072 { 3073 .name = "wm8994-aif1", 3074 .id = 1, 3075 .playback = { 3076 .stream_name = "AIF1 Playback", 3077 .channels_min = 1, 3078 .channels_max = 2, 3079 .rates = WM8994_RATES, 3080 .formats = WM8994_FORMATS, 3081 .sig_bits = 24, 3082 }, 3083 .capture = { 3084 .stream_name = "AIF1 Capture", 3085 .channels_min = 1, 3086 .channels_max = 2, 3087 .rates = WM8994_RATES, 3088 .formats = WM8994_FORMATS, 3089 .sig_bits = 24, 3090 }, 3091 .ops = &wm8994_aif1_dai_ops, 3092 }, 3093 { 3094 .name = "wm8994-aif2", 3095 .id = 2, 3096 .playback = { 3097 .stream_name = "AIF2 Playback", 3098 .channels_min = 1, 3099 .channels_max = 2, 3100 .rates = WM8994_RATES, 3101 .formats = WM8994_FORMATS, 3102 .sig_bits = 24, 3103 }, 3104 .capture = { 3105 .stream_name = "AIF2 Capture", 3106 .channels_min = 1, 3107 .channels_max = 2, 3108 .rates = WM8994_RATES, 3109 .formats = WM8994_FORMATS, 3110 .sig_bits = 24, 3111 }, 3112 .probe = wm8994_aif2_probe, 3113 .ops = &wm8994_aif2_dai_ops, 3114 }, 3115 { 3116 .name = "wm8994-aif3", 3117 .id = 3, 3118 .playback = { 3119 .stream_name = "AIF3 Playback", 3120 .channels_min = 1, 3121 .channels_max = 2, 3122 .rates = WM8994_RATES, 3123 .formats = WM8994_FORMATS, 3124 .sig_bits = 24, 3125 }, 3126 .capture = { 3127 .stream_name = "AIF3 Capture", 3128 .channels_min = 1, 3129 .channels_max = 2, 3130 .rates = WM8994_RATES, 3131 .formats = WM8994_FORMATS, 3132 .sig_bits = 24, 3133 }, 3134 .ops = &wm8994_aif3_dai_ops, 3135 } 3136 }; 3137 3138 #ifdef CONFIG_PM 3139 static int wm8994_codec_suspend(struct snd_soc_codec *codec) 3140 { 3141 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3142 int i, ret; 3143 3144 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3145 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3146 sizeof(struct wm8994_fll_config)); 3147 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 3148 if (ret < 0) 3149 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 3150 i + 1, ret); 3151 } 3152 3153 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3154 3155 return 0; 3156 } 3157 3158 static int wm8994_codec_resume(struct snd_soc_codec *codec) 3159 { 3160 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3161 int i, ret; 3162 3163 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3164 if (!wm8994->fll_suspend[i].out) 3165 continue; 3166 3167 ret = _wm8994_set_fll(codec, i + 1, 3168 wm8994->fll_suspend[i].src, 3169 wm8994->fll_suspend[i].in, 3170 wm8994->fll_suspend[i].out); 3171 if (ret < 0) 3172 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 3173 i + 1, ret); 3174 } 3175 3176 return 0; 3177 } 3178 #else 3179 #define wm8994_codec_suspend NULL 3180 #define wm8994_codec_resume NULL 3181 #endif 3182 3183 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3184 { 3185 struct snd_soc_codec *codec = wm8994->hubs.codec; 3186 struct wm8994 *control = wm8994->wm8994; 3187 struct wm8994_pdata *pdata = &control->pdata; 3188 struct snd_kcontrol_new controls[] = { 3189 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3190 wm8994->retune_mobile_enum, 3191 wm8994_get_retune_mobile_enum, 3192 wm8994_put_retune_mobile_enum), 3193 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3194 wm8994->retune_mobile_enum, 3195 wm8994_get_retune_mobile_enum, 3196 wm8994_put_retune_mobile_enum), 3197 SOC_ENUM_EXT("AIF2 EQ Mode", 3198 wm8994->retune_mobile_enum, 3199 wm8994_get_retune_mobile_enum, 3200 wm8994_put_retune_mobile_enum), 3201 }; 3202 int ret, i, j; 3203 const char **t; 3204 3205 /* We need an array of texts for the enum API but the number 3206 * of texts is likely to be less than the number of 3207 * configurations due to the sample rate dependency of the 3208 * configurations. */ 3209 wm8994->num_retune_mobile_texts = 0; 3210 wm8994->retune_mobile_texts = NULL; 3211 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3212 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3213 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3214 wm8994->retune_mobile_texts[j]) == 0) 3215 break; 3216 } 3217 3218 if (j != wm8994->num_retune_mobile_texts) 3219 continue; 3220 3221 /* Expand the array... */ 3222 t = krealloc(wm8994->retune_mobile_texts, 3223 sizeof(char *) * 3224 (wm8994->num_retune_mobile_texts + 1), 3225 GFP_KERNEL); 3226 if (t == NULL) 3227 continue; 3228 3229 /* ...store the new entry... */ 3230 t[wm8994->num_retune_mobile_texts] = 3231 pdata->retune_mobile_cfgs[i].name; 3232 3233 /* ...and remember the new version. */ 3234 wm8994->num_retune_mobile_texts++; 3235 wm8994->retune_mobile_texts = t; 3236 } 3237 3238 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 3239 wm8994->num_retune_mobile_texts); 3240 3241 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 3242 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3243 3244 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3245 ARRAY_SIZE(controls)); 3246 if (ret != 0) 3247 dev_err(wm8994->hubs.codec->dev, 3248 "Failed to add ReTune Mobile controls: %d\n", ret); 3249 } 3250 3251 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3252 { 3253 struct snd_soc_codec *codec = wm8994->hubs.codec; 3254 struct wm8994 *control = wm8994->wm8994; 3255 struct wm8994_pdata *pdata = &control->pdata; 3256 int ret, i; 3257 3258 if (!pdata) 3259 return; 3260 3261 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 3262 pdata->lineout2_diff, 3263 pdata->lineout1fb, 3264 pdata->lineout2fb, 3265 pdata->jd_scthr, 3266 pdata->jd_thr, 3267 pdata->micb1_delay, 3268 pdata->micb2_delay, 3269 pdata->micbias1_lvl, 3270 pdata->micbias2_lvl); 3271 3272 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3273 3274 if (pdata->num_drc_cfgs) { 3275 struct snd_kcontrol_new controls[] = { 3276 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3277 wm8994_get_drc_enum, wm8994_put_drc_enum), 3278 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3279 wm8994_get_drc_enum, wm8994_put_drc_enum), 3280 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3281 wm8994_get_drc_enum, wm8994_put_drc_enum), 3282 }; 3283 3284 /* We need an array of texts for the enum API */ 3285 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev, 3286 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL); 3287 if (!wm8994->drc_texts) { 3288 dev_err(wm8994->hubs.codec->dev, 3289 "Failed to allocate %d DRC config texts\n", 3290 pdata->num_drc_cfgs); 3291 return; 3292 } 3293 3294 for (i = 0; i < pdata->num_drc_cfgs; i++) 3295 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3296 3297 wm8994->drc_enum.max = pdata->num_drc_cfgs; 3298 wm8994->drc_enum.texts = wm8994->drc_texts; 3299 3300 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3301 ARRAY_SIZE(controls)); 3302 for (i = 0; i < WM8994_NUM_DRC; i++) 3303 wm8994_set_drc(codec, i); 3304 } else { 3305 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, 3306 wm8994_drc_controls, 3307 ARRAY_SIZE(wm8994_drc_controls)); 3308 } 3309 3310 if (ret != 0) 3311 dev_err(wm8994->hubs.codec->dev, 3312 "Failed to add DRC mode controls: %d\n", ret); 3313 3314 3315 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 3316 pdata->num_retune_mobile_cfgs); 3317 3318 if (pdata->num_retune_mobile_cfgs) 3319 wm8994_handle_retune_mobile_pdata(wm8994); 3320 else 3321 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls, 3322 ARRAY_SIZE(wm8994_eq_controls)); 3323 3324 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3325 if (pdata->micbias[i]) { 3326 snd_soc_write(codec, WM8958_MICBIAS1 + i, 3327 pdata->micbias[i] & 0xffff); 3328 } 3329 } 3330 } 3331 3332 /** 3333 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3334 * 3335 * @codec: WM8994 codec 3336 * @jack: jack to report detection events on 3337 * @micbias: microphone bias to detect on 3338 * 3339 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3340 * being used to bring out signals to the processor then only platform 3341 * data configuration is needed for WM8994 and processor GPIOs should 3342 * be configured using snd_soc_jack_add_gpios() instead. 3343 * 3344 * Configuration of detection levels is available via the micbias1_lvl 3345 * and micbias2_lvl platform data members. 3346 */ 3347 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3348 int micbias) 3349 { 3350 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3351 struct wm8994_micdet *micdet; 3352 struct wm8994 *control = wm8994->wm8994; 3353 int reg, ret; 3354 3355 if (control->type != WM8994) { 3356 dev_warn(codec->dev, "Not a WM8994\n"); 3357 return -EINVAL; 3358 } 3359 3360 switch (micbias) { 3361 case 1: 3362 micdet = &wm8994->micdet[0]; 3363 if (jack) 3364 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3365 "MICBIAS1"); 3366 else 3367 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3368 "MICBIAS1"); 3369 break; 3370 case 2: 3371 micdet = &wm8994->micdet[1]; 3372 if (jack) 3373 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3374 "MICBIAS1"); 3375 else 3376 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3377 "MICBIAS1"); 3378 break; 3379 default: 3380 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias); 3381 return -EINVAL; 3382 } 3383 3384 if (ret != 0) 3385 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n", 3386 micbias, ret); 3387 3388 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n", 3389 micbias, jack); 3390 3391 /* Store the configuration */ 3392 micdet->jack = jack; 3393 micdet->detecting = true; 3394 3395 /* If either of the jacks is set up then enable detection */ 3396 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3397 reg = WM8994_MICD_ENA; 3398 else 3399 reg = 0; 3400 3401 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3402 3403 /* enable MICDET and MICSHRT deboune */ 3404 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE, 3405 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3406 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3407 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3408 3409 snd_soc_dapm_sync(&codec->dapm); 3410 3411 return 0; 3412 } 3413 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3414 3415 static void wm8994_mic_work(struct work_struct *work) 3416 { 3417 struct wm8994_priv *priv = container_of(work, 3418 struct wm8994_priv, 3419 mic_work.work); 3420 struct regmap *regmap = priv->wm8994->regmap; 3421 struct device *dev = priv->wm8994->dev; 3422 unsigned int reg; 3423 int ret; 3424 int report; 3425 3426 pm_runtime_get_sync(dev); 3427 3428 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3429 if (ret < 0) { 3430 dev_err(dev, "Failed to read microphone status: %d\n", 3431 ret); 3432 pm_runtime_put(dev); 3433 return; 3434 } 3435 3436 dev_dbg(dev, "Microphone status: %x\n", reg); 3437 3438 report = 0; 3439 if (reg & WM8994_MIC1_DET_STS) { 3440 if (priv->micdet[0].detecting) 3441 report = SND_JACK_HEADSET; 3442 } 3443 if (reg & WM8994_MIC1_SHRT_STS) { 3444 if (priv->micdet[0].detecting) 3445 report = SND_JACK_HEADPHONE; 3446 else 3447 report |= SND_JACK_BTN_0; 3448 } 3449 if (report) 3450 priv->micdet[0].detecting = false; 3451 else 3452 priv->micdet[0].detecting = true; 3453 3454 snd_soc_jack_report(priv->micdet[0].jack, report, 3455 SND_JACK_HEADSET | SND_JACK_BTN_0); 3456 3457 report = 0; 3458 if (reg & WM8994_MIC2_DET_STS) { 3459 if (priv->micdet[1].detecting) 3460 report = SND_JACK_HEADSET; 3461 } 3462 if (reg & WM8994_MIC2_SHRT_STS) { 3463 if (priv->micdet[1].detecting) 3464 report = SND_JACK_HEADPHONE; 3465 else 3466 report |= SND_JACK_BTN_0; 3467 } 3468 if (report) 3469 priv->micdet[1].detecting = false; 3470 else 3471 priv->micdet[1].detecting = true; 3472 3473 snd_soc_jack_report(priv->micdet[1].jack, report, 3474 SND_JACK_HEADSET | SND_JACK_BTN_0); 3475 3476 pm_runtime_put(dev); 3477 } 3478 3479 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3480 { 3481 struct wm8994_priv *priv = data; 3482 struct snd_soc_codec *codec = priv->hubs.codec; 3483 3484 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3485 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3486 #endif 3487 3488 pm_wakeup_event(codec->dev, 300); 3489 3490 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250)); 3491 3492 return IRQ_HANDLED; 3493 } 3494 3495 static void wm1811_micd_stop(struct snd_soc_codec *codec) 3496 { 3497 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3498 3499 if (!wm8994->jackdet) 3500 return; 3501 3502 mutex_lock(&wm8994->accdet_lock); 3503 3504 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3505 3506 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3507 3508 mutex_unlock(&wm8994->accdet_lock); 3509 3510 if (wm8994->wm8994->pdata.jd_ext_cap) 3511 snd_soc_dapm_disable_pin(&codec->dapm, 3512 "MICBIAS2"); 3513 } 3514 3515 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status) 3516 { 3517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3518 int report; 3519 3520 report = 0; 3521 if (status & 0x4) 3522 report |= SND_JACK_BTN_0; 3523 3524 if (status & 0x8) 3525 report |= SND_JACK_BTN_1; 3526 3527 if (status & 0x10) 3528 report |= SND_JACK_BTN_2; 3529 3530 if (status & 0x20) 3531 report |= SND_JACK_BTN_3; 3532 3533 if (status & 0x40) 3534 report |= SND_JACK_BTN_4; 3535 3536 if (status & 0x80) 3537 report |= SND_JACK_BTN_5; 3538 3539 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3540 wm8994->btn_mask); 3541 } 3542 3543 static void wm8958_open_circuit_work(struct work_struct *work) 3544 { 3545 struct wm8994_priv *wm8994 = container_of(work, 3546 struct wm8994_priv, 3547 open_circuit_work.work); 3548 struct device *dev = wm8994->wm8994->dev; 3549 3550 wm1811_micd_stop(wm8994->hubs.codec); 3551 3552 mutex_lock(&wm8994->accdet_lock); 3553 3554 dev_dbg(dev, "Reporting open circuit\n"); 3555 3556 wm8994->jack_mic = false; 3557 wm8994->mic_detecting = true; 3558 3559 wm8958_micd_set_rate(wm8994->hubs.codec); 3560 3561 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3562 wm8994->btn_mask | 3563 SND_JACK_HEADSET); 3564 3565 mutex_unlock(&wm8994->accdet_lock); 3566 } 3567 3568 static void wm8958_mic_id(void *data, u16 status) 3569 { 3570 struct snd_soc_codec *codec = data; 3571 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3572 3573 /* Either nothing present or just starting detection */ 3574 if (!(status & WM8958_MICD_STS)) { 3575 /* If nothing present then clear our statuses */ 3576 dev_dbg(codec->dev, "Detected open circuit\n"); 3577 3578 schedule_delayed_work(&wm8994->open_circuit_work, 3579 msecs_to_jiffies(2500)); 3580 return; 3581 } 3582 3583 /* If the measurement is showing a high impedence we've got a 3584 * microphone. 3585 */ 3586 if (status & 0x600) { 3587 dev_dbg(codec->dev, "Detected microphone\n"); 3588 3589 wm8994->mic_detecting = false; 3590 wm8994->jack_mic = true; 3591 3592 wm8958_micd_set_rate(codec); 3593 3594 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3595 SND_JACK_HEADSET); 3596 } 3597 3598 3599 if (status & 0xfc) { 3600 dev_dbg(codec->dev, "Detected headphone\n"); 3601 wm8994->mic_detecting = false; 3602 3603 wm8958_micd_set_rate(codec); 3604 3605 /* If we have jackdet that will detect removal */ 3606 wm1811_micd_stop(codec); 3607 3608 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3609 SND_JACK_HEADSET); 3610 } 3611 } 3612 3613 /* Deferred mic detection to allow for extra settling time */ 3614 static void wm1811_mic_work(struct work_struct *work) 3615 { 3616 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3617 mic_work.work); 3618 struct wm8994 *control = wm8994->wm8994; 3619 struct snd_soc_codec *codec = wm8994->hubs.codec; 3620 3621 pm_runtime_get_sync(codec->dev); 3622 3623 /* If required for an external cap force MICBIAS on */ 3624 if (control->pdata.jd_ext_cap) { 3625 snd_soc_dapm_force_enable_pin(&codec->dapm, 3626 "MICBIAS2"); 3627 snd_soc_dapm_sync(&codec->dapm); 3628 } 3629 3630 mutex_lock(&wm8994->accdet_lock); 3631 3632 dev_dbg(codec->dev, "Starting mic detection\n"); 3633 3634 /* Use a user-supplied callback if we have one */ 3635 if (wm8994->micd_cb) { 3636 wm8994->micd_cb(wm8994->micd_cb_data); 3637 } else { 3638 /* 3639 * Start off measument of microphone impedence to find out 3640 * what's actually there. 3641 */ 3642 wm8994->mic_detecting = true; 3643 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC); 3644 3645 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3646 WM8958_MICD_ENA, WM8958_MICD_ENA); 3647 } 3648 3649 mutex_unlock(&wm8994->accdet_lock); 3650 3651 pm_runtime_put(codec->dev); 3652 } 3653 3654 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3655 { 3656 struct wm8994_priv *wm8994 = data; 3657 struct wm8994 *control = wm8994->wm8994; 3658 struct snd_soc_codec *codec = wm8994->hubs.codec; 3659 int reg, delay; 3660 bool present; 3661 3662 pm_runtime_get_sync(codec->dev); 3663 3664 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3665 3666 mutex_lock(&wm8994->accdet_lock); 3667 3668 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3669 if (reg < 0) { 3670 dev_err(codec->dev, "Failed to read jack status: %d\n", reg); 3671 mutex_unlock(&wm8994->accdet_lock); 3672 pm_runtime_put(codec->dev); 3673 return IRQ_NONE; 3674 } 3675 3676 dev_dbg(codec->dev, "JACKDET %x\n", reg); 3677 3678 present = reg & WM1811_JACKDET_LVL; 3679 3680 if (present) { 3681 dev_dbg(codec->dev, "Jack detected\n"); 3682 3683 wm8958_micd_set_rate(codec); 3684 3685 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3686 WM8958_MICB2_DISCH, 0); 3687 3688 /* Disable debounce while inserted */ 3689 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3690 WM1811_JACKDET_DB, 0); 3691 3692 delay = control->pdata.micdet_delay; 3693 schedule_delayed_work(&wm8994->mic_work, 3694 msecs_to_jiffies(delay)); 3695 } else { 3696 dev_dbg(codec->dev, "Jack not detected\n"); 3697 3698 cancel_delayed_work_sync(&wm8994->mic_work); 3699 3700 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3701 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3702 3703 /* Enable debounce while removed */ 3704 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3705 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3706 3707 wm8994->mic_detecting = false; 3708 wm8994->jack_mic = false; 3709 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3710 WM8958_MICD_ENA, 0); 3711 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3712 } 3713 3714 mutex_unlock(&wm8994->accdet_lock); 3715 3716 /* Turn off MICBIAS if it was on for an external cap */ 3717 if (control->pdata.jd_ext_cap && !present) 3718 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2"); 3719 3720 if (present) 3721 snd_soc_jack_report(wm8994->micdet[0].jack, 3722 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3723 else 3724 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3725 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3726 wm8994->btn_mask); 3727 3728 /* Since we only report deltas force an update, ensures we 3729 * avoid bootstrapping issues with the core. */ 3730 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3731 3732 pm_runtime_put(codec->dev); 3733 return IRQ_HANDLED; 3734 } 3735 3736 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3737 { 3738 struct wm8994_priv *wm8994 = container_of(work, 3739 struct wm8994_priv, 3740 jackdet_bootstrap.work); 3741 wm1811_jackdet_irq(0, wm8994); 3742 } 3743 3744 /** 3745 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3746 * 3747 * @codec: WM8958 codec 3748 * @jack: jack to report detection events on 3749 * 3750 * Enable microphone detection functionality for the WM8958. By 3751 * default simple detection which supports the detection of up to 6 3752 * buttons plus video and microphone functionality is supported. 3753 * 3754 * The WM8958 has an advanced jack detection facility which is able to 3755 * support complex accessory detection, especially when used in 3756 * conjunction with external circuitry. In order to provide maximum 3757 * flexiblity a callback is provided which allows a completely custom 3758 * detection algorithm. 3759 */ 3760 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3761 wm1811_micdet_cb det_cb, void *det_cb_data, 3762 wm1811_mic_id_cb id_cb, void *id_cb_data) 3763 { 3764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3765 struct wm8994 *control = wm8994->wm8994; 3766 u16 micd_lvl_sel; 3767 3768 switch (control->type) { 3769 case WM1811: 3770 case WM8958: 3771 break; 3772 default: 3773 return -EINVAL; 3774 } 3775 3776 if (jack) { 3777 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS"); 3778 snd_soc_dapm_sync(&codec->dapm); 3779 3780 wm8994->micdet[0].jack = jack; 3781 3782 if (det_cb) { 3783 wm8994->micd_cb = det_cb; 3784 wm8994->micd_cb_data = det_cb_data; 3785 } else { 3786 wm8994->mic_detecting = true; 3787 wm8994->jack_mic = false; 3788 } 3789 3790 if (id_cb) { 3791 wm8994->mic_id_cb = id_cb; 3792 wm8994->mic_id_cb_data = id_cb_data; 3793 } else { 3794 wm8994->mic_id_cb = wm8958_mic_id; 3795 wm8994->mic_id_cb_data = codec; 3796 } 3797 3798 wm8958_micd_set_rate(codec); 3799 3800 /* Detect microphones and short circuits by default */ 3801 if (control->pdata.micd_lvl_sel) 3802 micd_lvl_sel = control->pdata.micd_lvl_sel; 3803 else 3804 micd_lvl_sel = 0x41; 3805 3806 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3807 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3808 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3809 3810 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2, 3811 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3812 3813 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY); 3814 3815 /* 3816 * If we can use jack detection start off with that, 3817 * otherwise jump straight to microphone detection. 3818 */ 3819 if (wm8994->jackdet) { 3820 /* Disable debounce for the initial detect */ 3821 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3822 WM1811_JACKDET_DB, 0); 3823 3824 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3825 WM8958_MICB2_DISCH, 3826 WM8958_MICB2_DISCH); 3827 snd_soc_update_bits(codec, WM8994_LDO_1, 3828 WM8994_LDO1_DISCH, 0); 3829 wm1811_jackdet_set_mode(codec, 3830 WM1811_JACKDET_MODE_JACK); 3831 } else { 3832 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3833 WM8958_MICD_ENA, WM8958_MICD_ENA); 3834 } 3835 3836 } else { 3837 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3838 WM8958_MICD_ENA, 0); 3839 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE); 3840 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS"); 3841 snd_soc_dapm_sync(&codec->dapm); 3842 } 3843 3844 return 0; 3845 } 3846 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3847 3848 static void wm8958_mic_work(struct work_struct *work) 3849 { 3850 struct wm8994_priv *wm8994 = container_of(work, 3851 struct wm8994_priv, 3852 mic_complete_work.work); 3853 struct snd_soc_codec *codec = wm8994->hubs.codec; 3854 3855 pm_runtime_get_sync(codec->dev); 3856 3857 mutex_lock(&wm8994->accdet_lock); 3858 3859 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status); 3860 3861 mutex_unlock(&wm8994->accdet_lock); 3862 3863 pm_runtime_put(codec->dev); 3864 } 3865 3866 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3867 { 3868 struct wm8994_priv *wm8994 = data; 3869 struct snd_soc_codec *codec = wm8994->hubs.codec; 3870 int reg, count, ret, id_delay; 3871 3872 /* 3873 * Jack detection may have detected a removal simulataneously 3874 * with an update of the MICDET status; if so it will have 3875 * stopped detection and we can ignore this interrupt. 3876 */ 3877 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 3878 return IRQ_HANDLED; 3879 3880 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3881 cancel_delayed_work_sync(&wm8994->open_circuit_work); 3882 3883 pm_runtime_get_sync(codec->dev); 3884 3885 /* We may occasionally read a detection without an impedence 3886 * range being provided - if that happens loop again. 3887 */ 3888 count = 10; 3889 do { 3890 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 3891 if (reg < 0) { 3892 dev_err(codec->dev, 3893 "Failed to read mic detect status: %d\n", 3894 reg); 3895 pm_runtime_put(codec->dev); 3896 return IRQ_NONE; 3897 } 3898 3899 if (!(reg & WM8958_MICD_VALID)) { 3900 dev_dbg(codec->dev, "Mic detect data not valid\n"); 3901 goto out; 3902 } 3903 3904 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 3905 break; 3906 3907 msleep(1); 3908 } while (count--); 3909 3910 if (count == 0) 3911 dev_warn(codec->dev, "No impedance range reported for jack\n"); 3912 3913 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3914 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3915 #endif 3916 3917 /* Avoid a transient report when the accessory is being removed */ 3918 if (wm8994->jackdet) { 3919 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3920 if (ret < 0) { 3921 dev_err(codec->dev, "Failed to read jack status: %d\n", 3922 ret); 3923 } else if (!(ret & WM1811_JACKDET_LVL)) { 3924 dev_dbg(codec->dev, "Ignoring removed jack\n"); 3925 goto out; 3926 } 3927 } else if (!(reg & WM8958_MICD_STS)) { 3928 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3929 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3930 wm8994->btn_mask); 3931 wm8994->mic_detecting = true; 3932 goto out; 3933 } 3934 3935 wm8994->mic_status = reg; 3936 id_delay = wm8994->wm8994->pdata.mic_id_delay; 3937 3938 if (wm8994->mic_detecting) 3939 schedule_delayed_work(&wm8994->mic_complete_work, 3940 msecs_to_jiffies(id_delay)); 3941 else 3942 wm8958_button_det(codec, reg); 3943 3944 out: 3945 pm_runtime_put(codec->dev); 3946 return IRQ_HANDLED; 3947 } 3948 3949 static irqreturn_t wm8994_fifo_error(int irq, void *data) 3950 { 3951 struct snd_soc_codec *codec = data; 3952 3953 dev_err(codec->dev, "FIFO error\n"); 3954 3955 return IRQ_HANDLED; 3956 } 3957 3958 static irqreturn_t wm8994_temp_warn(int irq, void *data) 3959 { 3960 struct snd_soc_codec *codec = data; 3961 3962 dev_err(codec->dev, "Thermal warning\n"); 3963 3964 return IRQ_HANDLED; 3965 } 3966 3967 static irqreturn_t wm8994_temp_shut(int irq, void *data) 3968 { 3969 struct snd_soc_codec *codec = data; 3970 3971 dev_crit(codec->dev, "Thermal shutdown\n"); 3972 3973 return IRQ_HANDLED; 3974 } 3975 3976 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3977 { 3978 struct wm8994 *control = dev_get_drvdata(codec->dev->parent); 3979 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3980 struct snd_soc_dapm_context *dapm = &codec->dapm; 3981 unsigned int reg; 3982 int ret, i; 3983 3984 wm8994->hubs.codec = codec; 3985 codec->control_data = control->regmap; 3986 3987 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 3988 3989 mutex_init(&wm8994->accdet_lock); 3990 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 3991 wm1811_jackdet_bootstrap); 3992 INIT_DELAYED_WORK(&wm8994->open_circuit_work, 3993 wm8958_open_circuit_work); 3994 3995 switch (control->type) { 3996 case WM8994: 3997 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 3998 break; 3999 case WM1811: 4000 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 4001 break; 4002 default: 4003 break; 4004 } 4005 4006 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work); 4007 4008 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4009 init_completion(&wm8994->fll_locked[i]); 4010 4011 wm8994->micdet_irq = control->pdata.micdet_irq; 4012 4013 pm_runtime_enable(codec->dev); 4014 pm_runtime_idle(codec->dev); 4015 4016 /* By default use idle_bias_off, will override for WM8994 */ 4017 codec->dapm.idle_bias_off = 1; 4018 4019 /* Set revision-specific configuration */ 4020 switch (control->type) { 4021 case WM8994: 4022 /* Single ended line outputs should have VMID on. */ 4023 if (!control->pdata.lineout1_diff || 4024 !control->pdata.lineout2_diff) 4025 codec->dapm.idle_bias_off = 0; 4026 4027 switch (control->revision) { 4028 case 2: 4029 case 3: 4030 wm8994->hubs.dcs_codes_l = -5; 4031 wm8994->hubs.dcs_codes_r = -5; 4032 wm8994->hubs.hp_startup_mode = 1; 4033 wm8994->hubs.dcs_readback_mode = 1; 4034 wm8994->hubs.series_startup = 1; 4035 break; 4036 default: 4037 wm8994->hubs.dcs_readback_mode = 2; 4038 break; 4039 } 4040 break; 4041 4042 case WM8958: 4043 wm8994->hubs.dcs_readback_mode = 1; 4044 wm8994->hubs.hp_startup_mode = 1; 4045 4046 switch (control->revision) { 4047 case 0: 4048 break; 4049 default: 4050 wm8994->fll_byp = true; 4051 break; 4052 } 4053 break; 4054 4055 case WM1811: 4056 wm8994->hubs.dcs_readback_mode = 2; 4057 wm8994->hubs.no_series_update = 1; 4058 wm8994->hubs.hp_startup_mode = 1; 4059 wm8994->hubs.no_cache_dac_hp_direct = true; 4060 wm8994->fll_byp = true; 4061 4062 wm8994->hubs.dcs_codes_l = -9; 4063 wm8994->hubs.dcs_codes_r = -7; 4064 4065 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1, 4066 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 4067 break; 4068 4069 default: 4070 break; 4071 } 4072 4073 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 4074 wm8994_fifo_error, "FIFO error", codec); 4075 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 4076 wm8994_temp_warn, "Thermal warning", codec); 4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 4078 wm8994_temp_shut, "Thermal shutdown", codec); 4079 4080 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4081 wm_hubs_dcs_done, "DC servo done", 4082 &wm8994->hubs); 4083 if (ret == 0) 4084 wm8994->hubs.dcs_done_irq = true; 4085 4086 switch (control->type) { 4087 case WM8994: 4088 if (wm8994->micdet_irq) { 4089 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4090 wm8994_mic_irq, 4091 IRQF_TRIGGER_RISING, 4092 "Mic1 detect", 4093 wm8994); 4094 if (ret != 0) 4095 dev_warn(codec->dev, 4096 "Failed to request Mic1 detect IRQ: %d\n", 4097 ret); 4098 } 4099 4100 ret = wm8994_request_irq(wm8994->wm8994, 4101 WM8994_IRQ_MIC1_SHRT, 4102 wm8994_mic_irq, "Mic 1 short", 4103 wm8994); 4104 if (ret != 0) 4105 dev_warn(codec->dev, 4106 "Failed to request Mic1 short IRQ: %d\n", 4107 ret); 4108 4109 ret = wm8994_request_irq(wm8994->wm8994, 4110 WM8994_IRQ_MIC2_DET, 4111 wm8994_mic_irq, "Mic 2 detect", 4112 wm8994); 4113 if (ret != 0) 4114 dev_warn(codec->dev, 4115 "Failed to request Mic2 detect IRQ: %d\n", 4116 ret); 4117 4118 ret = wm8994_request_irq(wm8994->wm8994, 4119 WM8994_IRQ_MIC2_SHRT, 4120 wm8994_mic_irq, "Mic 2 short", 4121 wm8994); 4122 if (ret != 0) 4123 dev_warn(codec->dev, 4124 "Failed to request Mic2 short IRQ: %d\n", 4125 ret); 4126 break; 4127 4128 case WM8958: 4129 case WM1811: 4130 if (wm8994->micdet_irq) { 4131 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4132 wm8958_mic_irq, 4133 IRQF_TRIGGER_RISING, 4134 "Mic detect", 4135 wm8994); 4136 if (ret != 0) 4137 dev_warn(codec->dev, 4138 "Failed to request Mic detect IRQ: %d\n", 4139 ret); 4140 } else { 4141 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4142 wm8958_mic_irq, "Mic detect", 4143 wm8994); 4144 } 4145 } 4146 4147 switch (control->type) { 4148 case WM1811: 4149 if (control->cust_id > 1 || control->revision > 1) { 4150 ret = wm8994_request_irq(wm8994->wm8994, 4151 WM8994_IRQ_GPIO(6), 4152 wm1811_jackdet_irq, "JACKDET", 4153 wm8994); 4154 if (ret == 0) 4155 wm8994->jackdet = true; 4156 } 4157 break; 4158 default: 4159 break; 4160 } 4161 4162 wm8994->fll_locked_irq = true; 4163 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4164 ret = wm8994_request_irq(wm8994->wm8994, 4165 WM8994_IRQ_FLL1_LOCK + i, 4166 wm8994_fll_locked_irq, "FLL lock", 4167 &wm8994->fll_locked[i]); 4168 if (ret != 0) 4169 wm8994->fll_locked_irq = false; 4170 } 4171 4172 /* Make sure we can read from the GPIOs if they're inputs */ 4173 pm_runtime_get_sync(codec->dev); 4174 4175 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4176 * configured on init - if a system wants to do this dynamically 4177 * at runtime we can deal with that then. 4178 */ 4179 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4180 if (ret < 0) { 4181 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 4182 goto err_irq; 4183 } 4184 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4185 wm8994->lrclk_shared[0] = 1; 4186 wm8994_dai[0].symmetric_rates = 1; 4187 } else { 4188 wm8994->lrclk_shared[0] = 0; 4189 } 4190 4191 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4192 if (ret < 0) { 4193 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 4194 goto err_irq; 4195 } 4196 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4197 wm8994->lrclk_shared[1] = 1; 4198 wm8994_dai[1].symmetric_rates = 1; 4199 } else { 4200 wm8994->lrclk_shared[1] = 0; 4201 } 4202 4203 pm_runtime_put(codec->dev); 4204 4205 /* Latch volume update bits */ 4206 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4207 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg, 4208 wm8994_vu_bits[i].mask, 4209 wm8994_vu_bits[i].mask); 4210 4211 /* Set the low bit of the 3D stereo depth so TLV matches */ 4212 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 4213 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4214 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4215 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 4216 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4217 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4218 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 4219 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4220 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4221 4222 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4223 * use this; it only affects behaviour on idle TDM clock 4224 * cycles. */ 4225 switch (control->type) { 4226 case WM8994: 4227 case WM8958: 4228 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 4229 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4230 break; 4231 default: 4232 break; 4233 } 4234 4235 /* Put MICBIAS into bypass mode by default on newer devices */ 4236 switch (control->type) { 4237 case WM8958: 4238 case WM1811: 4239 snd_soc_update_bits(codec, WM8958_MICBIAS1, 4240 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4241 snd_soc_update_bits(codec, WM8958_MICBIAS2, 4242 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4243 break; 4244 default: 4245 break; 4246 } 4247 4248 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4249 wm_hubs_update_class_w(codec); 4250 4251 wm8994_handle_pdata(wm8994); 4252 4253 wm_hubs_add_analogue_controls(codec); 4254 snd_soc_add_codec_controls(codec, wm8994_snd_controls, 4255 ARRAY_SIZE(wm8994_snd_controls)); 4256 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4257 ARRAY_SIZE(wm8994_dapm_widgets)); 4258 4259 switch (control->type) { 4260 case WM8994: 4261 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4262 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4263 if (control->revision < 4) { 4264 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4265 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4266 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4267 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4268 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4269 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4270 } else { 4271 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4272 ARRAY_SIZE(wm8994_lateclk_widgets)); 4273 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4274 ARRAY_SIZE(wm8994_adc_widgets)); 4275 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4276 ARRAY_SIZE(wm8994_dac_widgets)); 4277 } 4278 break; 4279 case WM8958: 4280 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4281 ARRAY_SIZE(wm8958_snd_controls)); 4282 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4283 ARRAY_SIZE(wm8958_dapm_widgets)); 4284 if (control->revision < 1) { 4285 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4286 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4287 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4288 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4289 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4290 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4291 } else { 4292 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4293 ARRAY_SIZE(wm8994_lateclk_widgets)); 4294 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4295 ARRAY_SIZE(wm8994_adc_widgets)); 4296 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4297 ARRAY_SIZE(wm8994_dac_widgets)); 4298 } 4299 break; 4300 4301 case WM1811: 4302 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4303 ARRAY_SIZE(wm8958_snd_controls)); 4304 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4305 ARRAY_SIZE(wm8958_dapm_widgets)); 4306 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4307 ARRAY_SIZE(wm8994_lateclk_widgets)); 4308 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4309 ARRAY_SIZE(wm8994_adc_widgets)); 4310 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4311 ARRAY_SIZE(wm8994_dac_widgets)); 4312 break; 4313 } 4314 4315 wm_hubs_add_analogue_routes(codec, 0, 0); 4316 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4317 4318 switch (control->type) { 4319 case WM8994: 4320 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4321 ARRAY_SIZE(wm8994_intercon)); 4322 4323 if (control->revision < 4) { 4324 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4325 ARRAY_SIZE(wm8994_revd_intercon)); 4326 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4327 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4328 } else { 4329 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4330 ARRAY_SIZE(wm8994_lateclk_intercon)); 4331 } 4332 break; 4333 case WM8958: 4334 if (control->revision < 1) { 4335 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4336 ARRAY_SIZE(wm8994_intercon)); 4337 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4338 ARRAY_SIZE(wm8994_revd_intercon)); 4339 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4340 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4341 } else { 4342 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4343 ARRAY_SIZE(wm8994_lateclk_intercon)); 4344 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4345 ARRAY_SIZE(wm8958_intercon)); 4346 } 4347 4348 wm8958_dsp2_init(codec); 4349 break; 4350 case WM1811: 4351 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4352 ARRAY_SIZE(wm8994_lateclk_intercon)); 4353 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4354 ARRAY_SIZE(wm8958_intercon)); 4355 break; 4356 } 4357 4358 return 0; 4359 4360 err_irq: 4361 if (wm8994->jackdet) 4362 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4363 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4364 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4365 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4366 if (wm8994->micdet_irq) 4367 free_irq(wm8994->micdet_irq, wm8994); 4368 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4369 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4370 &wm8994->fll_locked[i]); 4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4372 &wm8994->hubs); 4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4376 4377 return ret; 4378 } 4379 4380 static int wm8994_codec_remove(struct snd_soc_codec *codec) 4381 { 4382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 4383 struct wm8994 *control = wm8994->wm8994; 4384 int i; 4385 4386 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 4387 4388 pm_runtime_disable(codec->dev); 4389 4390 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4391 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4392 &wm8994->fll_locked[i]); 4393 4394 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4395 &wm8994->hubs); 4396 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4397 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4399 4400 if (wm8994->jackdet) 4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4402 4403 switch (control->type) { 4404 case WM8994: 4405 if (wm8994->micdet_irq) 4406 free_irq(wm8994->micdet_irq, wm8994); 4407 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4408 wm8994); 4409 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4410 wm8994); 4411 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4412 wm8994); 4413 break; 4414 4415 case WM1811: 4416 case WM8958: 4417 if (wm8994->micdet_irq) 4418 free_irq(wm8994->micdet_irq, wm8994); 4419 break; 4420 } 4421 release_firmware(wm8994->mbc); 4422 release_firmware(wm8994->mbc_vss); 4423 release_firmware(wm8994->enh_eq); 4424 kfree(wm8994->retune_mobile_texts); 4425 return 0; 4426 } 4427 4428 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 4429 .probe = wm8994_codec_probe, 4430 .remove = wm8994_codec_remove, 4431 .suspend = wm8994_codec_suspend, 4432 .resume = wm8994_codec_resume, 4433 .set_bias_level = wm8994_set_bias_level, 4434 }; 4435 4436 static int wm8994_probe(struct platform_device *pdev) 4437 { 4438 struct wm8994_priv *wm8994; 4439 4440 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4441 GFP_KERNEL); 4442 if (wm8994 == NULL) 4443 return -ENOMEM; 4444 platform_set_drvdata(pdev, wm8994); 4445 4446 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4447 4448 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 4449 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4450 } 4451 4452 static int wm8994_remove(struct platform_device *pdev) 4453 { 4454 snd_soc_unregister_codec(&pdev->dev); 4455 return 0; 4456 } 4457 4458 #ifdef CONFIG_PM_SLEEP 4459 static int wm8994_suspend(struct device *dev) 4460 { 4461 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4462 4463 /* Drop down to power saving mode when system is suspended */ 4464 if (wm8994->jackdet && !wm8994->active_refcount) 4465 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4466 WM1811_JACKDET_MODE_MASK, 4467 wm8994->jackdet_mode); 4468 4469 return 0; 4470 } 4471 4472 static int wm8994_resume(struct device *dev) 4473 { 4474 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4475 4476 if (wm8994->jackdet && wm8994->jackdet_mode) 4477 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4478 WM1811_JACKDET_MODE_MASK, 4479 WM1811_JACKDET_MODE_AUDIO); 4480 4481 return 0; 4482 } 4483 #endif 4484 4485 static const struct dev_pm_ops wm8994_pm_ops = { 4486 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4487 }; 4488 4489 static struct platform_driver wm8994_codec_driver = { 4490 .driver = { 4491 .name = "wm8994-codec", 4492 .owner = THIS_MODULE, 4493 .pm = &wm8994_pm_ops, 4494 }, 4495 .probe = wm8994_probe, 4496 .remove = wm8994_remove, 4497 }; 4498 4499 module_platform_driver(wm8994_codec_driver); 4500 4501 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4502 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4503 MODULE_LICENSE("GPL"); 4504 MODULE_ALIAS("platform:wm8994-codec"); 4505