1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <trace/events/asoc.h> 32 33 #include <linux/mfd/wm8994/core.h> 34 #include <linux/mfd/wm8994/registers.h> 35 #include <linux/mfd/wm8994/pdata.h> 36 #include <linux/mfd/wm8994/gpio.h> 37 38 #include "wm8994.h" 39 #include "wm_hubs.h" 40 41 struct fll_config { 42 int src; 43 int in; 44 int out; 45 }; 46 47 #define WM8994_NUM_DRC 3 48 #define WM8994_NUM_EQ 3 49 50 static int wm8994_drc_base[] = { 51 WM8994_AIF1_DRC1_1, 52 WM8994_AIF1_DRC2_1, 53 WM8994_AIF2_DRC_1, 54 }; 55 56 static int wm8994_retune_mobile_base[] = { 57 WM8994_AIF1_DAC1_EQ_GAINS_1, 58 WM8994_AIF1_DAC2_EQ_GAINS_1, 59 WM8994_AIF2_EQ_GAINS_1, 60 }; 61 62 struct wm8994_micdet { 63 struct snd_soc_jack *jack; 64 int det; 65 int shrt; 66 }; 67 68 /* codec private data */ 69 struct wm8994_priv { 70 struct wm_hubs_data hubs; 71 enum snd_soc_control_type control_type; 72 void *control_data; 73 struct snd_soc_codec *codec; 74 int sysclk[2]; 75 int sysclk_rate[2]; 76 int mclk[2]; 77 int aifclk[2]; 78 struct fll_config fll[2], fll_suspend[2]; 79 80 int dac_rates[2]; 81 int lrclk_shared[2]; 82 83 int mbc_ena[3]; 84 85 /* Platform dependant DRC configuration */ 86 const char **drc_texts; 87 int drc_cfg[WM8994_NUM_DRC]; 88 struct soc_enum drc_enum; 89 90 /* Platform dependant ReTune mobile configuration */ 91 int num_retune_mobile_texts; 92 const char **retune_mobile_texts; 93 int retune_mobile_cfg[WM8994_NUM_EQ]; 94 struct soc_enum retune_mobile_enum; 95 96 /* Platform dependant MBC configuration */ 97 int mbc_cfg; 98 const char **mbc_texts; 99 struct soc_enum mbc_enum; 100 101 struct wm8994_micdet micdet[2]; 102 103 wm8958_micdet_cb jack_cb; 104 void *jack_cb_data; 105 bool jack_is_mic; 106 bool jack_is_video; 107 108 int revision; 109 struct wm8994_pdata *pdata; 110 111 unsigned int aif1clk_enable:1; 112 unsigned int aif2clk_enable:1; 113 114 unsigned int aif1clk_disable:1; 115 unsigned int aif2clk_disable:1; 116 }; 117 118 static int wm8994_readable(unsigned int reg) 119 { 120 switch (reg) { 121 case WM8994_GPIO_1: 122 case WM8994_GPIO_2: 123 case WM8994_GPIO_3: 124 case WM8994_GPIO_4: 125 case WM8994_GPIO_5: 126 case WM8994_GPIO_6: 127 case WM8994_GPIO_7: 128 case WM8994_GPIO_8: 129 case WM8994_GPIO_9: 130 case WM8994_GPIO_10: 131 case WM8994_GPIO_11: 132 case WM8994_INTERRUPT_STATUS_1: 133 case WM8994_INTERRUPT_STATUS_2: 134 case WM8994_INTERRUPT_RAW_STATUS_2: 135 return 1; 136 default: 137 break; 138 } 139 140 if (reg >= WM8994_CACHE_SIZE) 141 return 0; 142 return wm8994_access_masks[reg].readable != 0; 143 } 144 145 static int wm8994_volatile(unsigned int reg) 146 { 147 if (reg >= WM8994_CACHE_SIZE) 148 return 1; 149 150 switch (reg) { 151 case WM8994_SOFTWARE_RESET: 152 case WM8994_CHIP_REVISION: 153 case WM8994_DC_SERVO_1: 154 case WM8994_DC_SERVO_READBACK: 155 case WM8994_RATE_STATUS: 156 case WM8994_LDO_1: 157 case WM8994_LDO_2: 158 case WM8958_DSP2_EXECCONTROL: 159 case WM8958_MIC_DETECT_3: 160 return 1; 161 default: 162 return 0; 163 } 164 } 165 166 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 167 unsigned int value) 168 { 169 int ret; 170 171 BUG_ON(reg > WM8994_MAX_REGISTER); 172 173 if (!wm8994_volatile(reg)) { 174 ret = snd_soc_cache_write(codec, reg, value); 175 if (ret != 0) 176 dev_err(codec->dev, "Cache write to %x failed: %d\n", 177 reg, ret); 178 } 179 180 return wm8994_reg_write(codec->control_data, reg, value); 181 } 182 183 static unsigned int wm8994_read(struct snd_soc_codec *codec, 184 unsigned int reg) 185 { 186 unsigned int val; 187 int ret; 188 189 BUG_ON(reg > WM8994_MAX_REGISTER); 190 191 if (!wm8994_volatile(reg) && wm8994_readable(reg) && 192 reg < codec->driver->reg_cache_size) { 193 ret = snd_soc_cache_read(codec, reg, &val); 194 if (ret >= 0) 195 return val; 196 else 197 dev_err(codec->dev, "Cache read from %x failed: %d\n", 198 reg, ret); 199 } 200 201 return wm8994_reg_read(codec->control_data, reg); 202 } 203 204 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 205 { 206 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 207 int rate; 208 int reg1 = 0; 209 int offset; 210 211 if (aif) 212 offset = 4; 213 else 214 offset = 0; 215 216 switch (wm8994->sysclk[aif]) { 217 case WM8994_SYSCLK_MCLK1: 218 rate = wm8994->mclk[0]; 219 break; 220 221 case WM8994_SYSCLK_MCLK2: 222 reg1 |= 0x8; 223 rate = wm8994->mclk[1]; 224 break; 225 226 case WM8994_SYSCLK_FLL1: 227 reg1 |= 0x10; 228 rate = wm8994->fll[0].out; 229 break; 230 231 case WM8994_SYSCLK_FLL2: 232 reg1 |= 0x18; 233 rate = wm8994->fll[1].out; 234 break; 235 236 default: 237 return -EINVAL; 238 } 239 240 if (rate >= 13500000) { 241 rate /= 2; 242 reg1 |= WM8994_AIF1CLK_DIV; 243 244 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 245 aif + 1, rate); 246 } 247 248 if (rate && rate < 3000000) 249 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n", 250 aif + 1, rate); 251 252 wm8994->aifclk[aif] = rate; 253 254 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 255 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 256 reg1); 257 258 return 0; 259 } 260 261 static int configure_clock(struct snd_soc_codec *codec) 262 { 263 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 264 int old, new; 265 266 /* Bring up the AIF clocks first */ 267 configure_aif_clock(codec, 0); 268 configure_aif_clock(codec, 1); 269 270 /* Then switch CLK_SYS over to the higher of them; a change 271 * can only happen as a result of a clocking change which can 272 * only be made outside of DAPM so we can safely redo the 273 * clocking. 274 */ 275 276 /* If they're equal it doesn't matter which is used */ 277 if (wm8994->aifclk[0] == wm8994->aifclk[1]) 278 return 0; 279 280 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 281 new = WM8994_SYSCLK_SRC; 282 else 283 new = 0; 284 285 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; 286 287 /* If there's no change then we're done. */ 288 if (old == new) 289 return 0; 290 291 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 292 293 snd_soc_dapm_sync(&codec->dapm); 294 295 return 0; 296 } 297 298 static int check_clk_sys(struct snd_soc_dapm_widget *source, 299 struct snd_soc_dapm_widget *sink) 300 { 301 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 302 const char *clk; 303 304 /* Check what we're currently using for CLK_SYS */ 305 if (reg & WM8994_SYSCLK_SRC) 306 clk = "AIF2CLK"; 307 else 308 clk = "AIF1CLK"; 309 310 return strcmp(source->name, clk) == 0; 311 } 312 313 static const char *sidetone_hpf_text[] = { 314 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 315 }; 316 317 static const struct soc_enum sidetone_hpf = 318 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 319 320 static const char *adc_hpf_text[] = { 321 "HiFi", "Voice 1", "Voice 2", "Voice 3" 322 }; 323 324 static const struct soc_enum aif1adc1_hpf = 325 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 326 327 static const struct soc_enum aif1adc2_hpf = 328 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 329 330 static const struct soc_enum aif2adc_hpf = 331 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 332 333 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 334 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 335 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 336 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 337 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 338 339 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 341 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 342 .put = wm8994_put_drc_sw, \ 343 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 344 345 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 346 struct snd_ctl_elem_value *ucontrol) 347 { 348 struct soc_mixer_control *mc = 349 (struct soc_mixer_control *)kcontrol->private_value; 350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 351 int mask, ret; 352 353 /* Can't enable both ADC and DAC paths simultaneously */ 354 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 355 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 356 WM8994_AIF1ADC1R_DRC_ENA_MASK; 357 else 358 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 359 360 ret = snd_soc_read(codec, mc->reg); 361 if (ret < 0) 362 return ret; 363 if (ret & mask) 364 return -EINVAL; 365 366 return snd_soc_put_volsw(kcontrol, ucontrol); 367 } 368 369 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 370 { 371 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 372 struct wm8994_pdata *pdata = wm8994->pdata; 373 int base = wm8994_drc_base[drc]; 374 int cfg = wm8994->drc_cfg[drc]; 375 int save, i; 376 377 /* Save any enables; the configuration should clear them. */ 378 save = snd_soc_read(codec, base); 379 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 380 WM8994_AIF1ADC1R_DRC_ENA; 381 382 for (i = 0; i < WM8994_DRC_REGS; i++) 383 snd_soc_update_bits(codec, base + i, 0xffff, 384 pdata->drc_cfgs[cfg].regs[i]); 385 386 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 387 WM8994_AIF1ADC1L_DRC_ENA | 388 WM8994_AIF1ADC1R_DRC_ENA, save); 389 } 390 391 /* Icky as hell but saves code duplication */ 392 static int wm8994_get_drc(const char *name) 393 { 394 if (strcmp(name, "AIF1DRC1 Mode") == 0) 395 return 0; 396 if (strcmp(name, "AIF1DRC2 Mode") == 0) 397 return 1; 398 if (strcmp(name, "AIF2DRC Mode") == 0) 399 return 2; 400 return -EINVAL; 401 } 402 403 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 404 struct snd_ctl_elem_value *ucontrol) 405 { 406 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 407 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 408 struct wm8994_pdata *pdata = wm8994->pdata; 409 int drc = wm8994_get_drc(kcontrol->id.name); 410 int value = ucontrol->value.integer.value[0]; 411 412 if (drc < 0) 413 return drc; 414 415 if (value >= pdata->num_drc_cfgs) 416 return -EINVAL; 417 418 wm8994->drc_cfg[drc] = value; 419 420 wm8994_set_drc(codec, drc); 421 422 return 0; 423 } 424 425 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 426 struct snd_ctl_elem_value *ucontrol) 427 { 428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 430 int drc = wm8994_get_drc(kcontrol->id.name); 431 432 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 433 434 return 0; 435 } 436 437 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 438 { 439 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 440 struct wm8994_pdata *pdata = wm8994->pdata; 441 int base = wm8994_retune_mobile_base[block]; 442 int iface, best, best_val, save, i, cfg; 443 444 if (!pdata || !wm8994->num_retune_mobile_texts) 445 return; 446 447 switch (block) { 448 case 0: 449 case 1: 450 iface = 0; 451 break; 452 case 2: 453 iface = 1; 454 break; 455 default: 456 return; 457 } 458 459 /* Find the version of the currently selected configuration 460 * with the nearest sample rate. */ 461 cfg = wm8994->retune_mobile_cfg[block]; 462 best = 0; 463 best_val = INT_MAX; 464 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 465 if (strcmp(pdata->retune_mobile_cfgs[i].name, 466 wm8994->retune_mobile_texts[cfg]) == 0 && 467 abs(pdata->retune_mobile_cfgs[i].rate 468 - wm8994->dac_rates[iface]) < best_val) { 469 best = i; 470 best_val = abs(pdata->retune_mobile_cfgs[i].rate 471 - wm8994->dac_rates[iface]); 472 } 473 } 474 475 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 476 block, 477 pdata->retune_mobile_cfgs[best].name, 478 pdata->retune_mobile_cfgs[best].rate, 479 wm8994->dac_rates[iface]); 480 481 /* The EQ will be disabled while reconfiguring it, remember the 482 * current configuration. 483 */ 484 save = snd_soc_read(codec, base); 485 save &= WM8994_AIF1DAC1_EQ_ENA; 486 487 for (i = 0; i < WM8994_EQ_REGS; i++) 488 snd_soc_update_bits(codec, base + i, 0xffff, 489 pdata->retune_mobile_cfgs[best].regs[i]); 490 491 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 492 } 493 494 /* Icky as hell but saves code duplication */ 495 static int wm8994_get_retune_mobile_block(const char *name) 496 { 497 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 498 return 0; 499 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 500 return 1; 501 if (strcmp(name, "AIF2 EQ Mode") == 0) 502 return 2; 503 return -EINVAL; 504 } 505 506 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 507 struct snd_ctl_elem_value *ucontrol) 508 { 509 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 511 struct wm8994_pdata *pdata = wm8994->pdata; 512 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 513 int value = ucontrol->value.integer.value[0]; 514 515 if (block < 0) 516 return block; 517 518 if (value >= pdata->num_retune_mobile_cfgs) 519 return -EINVAL; 520 521 wm8994->retune_mobile_cfg[block] = value; 522 523 wm8994_set_retune_mobile(codec, block); 524 525 return 0; 526 } 527 528 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 529 struct snd_ctl_elem_value *ucontrol) 530 { 531 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 532 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec); 533 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 534 535 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 536 537 return 0; 538 } 539 540 static const char *aif_chan_src_text[] = { 541 "Left", "Right" 542 }; 543 544 static const struct soc_enum aif1adcl_src = 545 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 546 547 static const struct soc_enum aif1adcr_src = 548 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 549 550 static const struct soc_enum aif2adcl_src = 551 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 552 553 static const struct soc_enum aif2adcr_src = 554 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 555 556 static const struct soc_enum aif1dacl_src = 557 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 558 559 static const struct soc_enum aif1dacr_src = 560 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 561 562 static const struct soc_enum aif2dacl_src = 563 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 564 565 static const struct soc_enum aif2dacr_src = 566 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 567 568 static const char *osr_text[] = { 569 "Low Power", "High Performance", 570 }; 571 572 static const struct soc_enum dac_osr = 573 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 574 575 static const struct soc_enum adc_osr = 576 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 577 578 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) 579 { 580 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 581 struct wm8994_pdata *pdata = wm8994->pdata; 582 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5); 583 int ena, reg, aif, i; 584 585 switch (mbc) { 586 case 0: 587 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); 588 aif = 0; 589 break; 590 case 1: 591 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 592 aif = 0; 593 break; 594 case 2: 595 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); 596 aif = 1; 597 break; 598 default: 599 BUG(); 600 return; 601 } 602 603 /* We can only enable the MBC if the AIF is enabled and we 604 * want it to be enabled. */ 605 ena = pwr_reg && wm8994->mbc_ena[mbc]; 606 607 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM); 608 609 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n", 610 mbc, start, pwr_reg, reg); 611 612 if (start && ena) { 613 /* If the DSP is already running then noop */ 614 if (reg & WM8958_DSP2_ENA) 615 return; 616 617 /* Switch the clock over to the appropriate AIF */ 618 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 619 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA, 620 aif << WM8958_DSP2CLK_SRC_SHIFT | 621 WM8958_DSP2CLK_ENA); 622 623 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, 624 WM8958_DSP2_ENA, WM8958_DSP2_ENA); 625 626 /* If we've got user supplied MBC settings use them */ 627 if (pdata && pdata->num_mbc_cfgs) { 628 struct wm8958_mbc_cfg *cfg 629 = &pdata->mbc_cfgs[wm8994->mbc_cfg]; 630 631 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++) 632 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1, 633 cfg->coeff_regs[i]); 634 635 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++) 636 snd_soc_write(codec, 637 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1, 638 cfg->cutoff_regs[i]); 639 } 640 641 /* Run the DSP */ 642 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL, 643 WM8958_DSP2_RUNR); 644 645 /* And we're off! */ 646 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, 647 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK, 648 mbc << WM8958_MBC_SEL_SHIFT | 649 WM8958_MBC_ENA); 650 } else { 651 /* If the DSP is already stopped then noop */ 652 if (!(reg & WM8958_DSP2_ENA)) 653 return; 654 655 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, 656 WM8958_MBC_ENA, 0); 657 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, 658 WM8958_DSP2_ENA, 0); 659 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 660 WM8958_DSP2CLK_ENA, 0); 661 } 662 } 663 664 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w, 665 struct snd_kcontrol *kcontrol, int event) 666 { 667 struct snd_soc_codec *codec = w->codec; 668 int mbc; 669 670 switch (w->shift) { 671 case 13: 672 case 12: 673 mbc = 2; 674 break; 675 case 11: 676 case 10: 677 mbc = 1; 678 break; 679 case 9: 680 case 8: 681 mbc = 0; 682 break; 683 default: 684 BUG(); 685 return -EINVAL; 686 } 687 688 switch (event) { 689 case SND_SOC_DAPM_POST_PMU: 690 wm8958_mbc_apply(codec, mbc, 1); 691 break; 692 case SND_SOC_DAPM_POST_PMD: 693 wm8958_mbc_apply(codec, mbc, 0); 694 break; 695 } 696 697 return 0; 698 } 699 700 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol, 701 struct snd_ctl_elem_value *ucontrol) 702 { 703 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 704 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 705 struct wm8994_pdata *pdata = wm8994->pdata; 706 int value = ucontrol->value.integer.value[0]; 707 int reg; 708 709 /* Don't allow on the fly reconfiguration */ 710 reg = snd_soc_read(codec, WM8994_CLOCKING_1); 711 if (reg < 0 || reg & WM8958_DSP2CLK_ENA) 712 return -EBUSY; 713 714 if (value >= pdata->num_mbc_cfgs) 715 return -EINVAL; 716 717 wm8994->mbc_cfg = value; 718 719 return 0; 720 } 721 722 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol, 723 struct snd_ctl_elem_value *ucontrol) 724 { 725 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 726 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 727 728 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg; 729 730 return 0; 731 } 732 733 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol, 734 struct snd_ctl_elem_info *uinfo) 735 { 736 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 737 uinfo->count = 1; 738 uinfo->value.integer.min = 0; 739 uinfo->value.integer.max = 1; 740 return 0; 741 } 742 743 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol, 744 struct snd_ctl_elem_value *ucontrol) 745 { 746 int mbc = kcontrol->private_value; 747 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 748 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 749 750 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc]; 751 752 return 0; 753 } 754 755 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol, 756 struct snd_ctl_elem_value *ucontrol) 757 { 758 int mbc = kcontrol->private_value; 759 int i; 760 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 761 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 762 763 if (ucontrol->value.integer.value[0] > 1) 764 return -EINVAL; 765 766 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) { 767 if (mbc != i && wm8994->mbc_ena[i]) { 768 dev_dbg(codec->dev, "MBC %d active already\n", mbc); 769 return -EBUSY; 770 } 771 } 772 773 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0]; 774 775 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]); 776 777 return 0; 778 } 779 780 #define WM8958_MBC_SWITCH(xname, xval) {\ 781 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 782 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 783 .info = wm8958_mbc_info, \ 784 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \ 785 .private_value = xval } 786 787 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 788 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 789 WM8994_AIF1_ADC1_RIGHT_VOLUME, 790 1, 119, 0, digital_tlv), 791 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 792 WM8994_AIF1_ADC2_RIGHT_VOLUME, 793 1, 119, 0, digital_tlv), 794 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 795 WM8994_AIF2_ADC_RIGHT_VOLUME, 796 1, 119, 0, digital_tlv), 797 798 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 799 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 800 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 801 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 802 803 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 804 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 805 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 806 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 807 808 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 809 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 810 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 811 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 812 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 813 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 814 815 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 816 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 817 818 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 819 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 820 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 821 822 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 823 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 824 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 825 826 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 827 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 828 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 829 830 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 831 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 832 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 833 834 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 835 5, 12, 0, st_tlv), 836 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 837 0, 12, 0, st_tlv), 838 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 839 5, 12, 0, st_tlv), 840 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 841 0, 12, 0, st_tlv), 842 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 843 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 844 845 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 846 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 847 848 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 849 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 850 851 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 852 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 853 854 SOC_ENUM("ADC OSR", adc_osr), 855 SOC_ENUM("DAC OSR", dac_osr), 856 857 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 858 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 859 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 860 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 861 862 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 863 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 864 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 865 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 866 867 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 868 6, 1, 1, wm_hubs_spkmix_tlv), 869 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 870 2, 1, 1, wm_hubs_spkmix_tlv), 871 872 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 873 6, 1, 1, wm_hubs_spkmix_tlv), 874 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 875 2, 1, 1, wm_hubs_spkmix_tlv), 876 877 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 878 10, 15, 0, wm8994_3d_tlv), 879 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 880 8, 1, 0), 881 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 882 10, 15, 0, wm8994_3d_tlv), 883 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 884 8, 1, 0), 885 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 886 10, 15, 0, wm8994_3d_tlv), 887 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 888 8, 1, 0), 889 }; 890 891 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 892 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 893 eq_tlv), 894 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 895 eq_tlv), 896 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 897 eq_tlv), 898 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 899 eq_tlv), 900 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 901 eq_tlv), 902 903 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 904 eq_tlv), 905 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 906 eq_tlv), 907 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 908 eq_tlv), 909 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 910 eq_tlv), 911 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 912 eq_tlv), 913 914 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 915 eq_tlv), 916 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 917 eq_tlv), 918 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 919 eq_tlv), 920 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 921 eq_tlv), 922 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 923 eq_tlv), 924 }; 925 926 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 927 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 928 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0), 929 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1), 930 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2), 931 }; 932 933 static int clk_sys_event(struct snd_soc_dapm_widget *w, 934 struct snd_kcontrol *kcontrol, int event) 935 { 936 struct snd_soc_codec *codec = w->codec; 937 938 switch (event) { 939 case SND_SOC_DAPM_PRE_PMU: 940 return configure_clock(codec); 941 942 case SND_SOC_DAPM_POST_PMD: 943 configure_clock(codec); 944 break; 945 } 946 947 return 0; 948 } 949 950 static void wm8994_update_class_w(struct snd_soc_codec *codec) 951 { 952 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 953 int enable = 1; 954 int source = 0; /* GCC flow analysis can't track enable */ 955 int reg, reg_r; 956 957 /* Only support direct DAC->headphone paths */ 958 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); 959 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { 960 dev_vdbg(codec->dev, "HPL connected to output mixer\n"); 961 enable = 0; 962 } 963 964 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); 965 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { 966 dev_vdbg(codec->dev, "HPR connected to output mixer\n"); 967 enable = 0; 968 } 969 970 /* We also need the same setting for L/R and only one path */ 971 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 972 switch (reg) { 973 case WM8994_AIF2DACL_TO_DAC1L: 974 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 975 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 976 break; 977 case WM8994_AIF1DAC2L_TO_DAC1L: 978 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 979 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 980 break; 981 case WM8994_AIF1DAC1L_TO_DAC1L: 982 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 983 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 984 break; 985 default: 986 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 987 enable = 0; 988 break; 989 } 990 991 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 992 if (reg_r != reg) { 993 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 994 enable = 0; 995 } 996 997 if (enable) { 998 dev_dbg(codec->dev, "Class W enabled\n"); 999 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1000 WM8994_CP_DYN_PWR | 1001 WM8994_CP_DYN_SRC_SEL_MASK, 1002 source | WM8994_CP_DYN_PWR); 1003 wm8994->hubs.class_w = true; 1004 1005 } else { 1006 dev_dbg(codec->dev, "Class W disabled\n"); 1007 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1008 WM8994_CP_DYN_PWR, 0); 1009 wm8994->hubs.class_w = false; 1010 } 1011 } 1012 1013 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1014 struct snd_kcontrol *kcontrol, int event) 1015 { 1016 struct snd_soc_codec *codec = w->codec; 1017 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1018 1019 switch (event) { 1020 case SND_SOC_DAPM_PRE_PMU: 1021 if (wm8994->aif1clk_enable) { 1022 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1023 WM8994_AIF1CLK_ENA_MASK, 1024 WM8994_AIF1CLK_ENA); 1025 wm8994->aif1clk_enable = 0; 1026 } 1027 if (wm8994->aif2clk_enable) { 1028 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1029 WM8994_AIF2CLK_ENA_MASK, 1030 WM8994_AIF2CLK_ENA); 1031 wm8994->aif2clk_enable = 0; 1032 } 1033 break; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1040 struct snd_kcontrol *kcontrol, int event) 1041 { 1042 struct snd_soc_codec *codec = w->codec; 1043 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1044 1045 switch (event) { 1046 case SND_SOC_DAPM_POST_PMD: 1047 if (wm8994->aif1clk_disable) { 1048 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1049 WM8994_AIF1CLK_ENA_MASK, 0); 1050 wm8994->aif1clk_disable = 0; 1051 } 1052 if (wm8994->aif2clk_disable) { 1053 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1054 WM8994_AIF2CLK_ENA_MASK, 0); 1055 wm8994->aif2clk_disable = 0; 1056 } 1057 break; 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1064 struct snd_kcontrol *kcontrol, int event) 1065 { 1066 struct snd_soc_codec *codec = w->codec; 1067 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1068 1069 switch (event) { 1070 case SND_SOC_DAPM_PRE_PMU: 1071 wm8994->aif1clk_enable = 1; 1072 break; 1073 case SND_SOC_DAPM_POST_PMD: 1074 wm8994->aif1clk_disable = 1; 1075 break; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1082 struct snd_kcontrol *kcontrol, int event) 1083 { 1084 struct snd_soc_codec *codec = w->codec; 1085 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1086 1087 switch (event) { 1088 case SND_SOC_DAPM_PRE_PMU: 1089 wm8994->aif2clk_enable = 1; 1090 break; 1091 case SND_SOC_DAPM_POST_PMD: 1092 wm8994->aif2clk_disable = 1; 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1100 struct snd_kcontrol *kcontrol, int event) 1101 { 1102 late_enable_ev(w, kcontrol, event); 1103 return 0; 1104 } 1105 1106 static int dac_ev(struct snd_soc_dapm_widget *w, 1107 struct snd_kcontrol *kcontrol, int event) 1108 { 1109 struct snd_soc_codec *codec = w->codec; 1110 unsigned int mask = 1 << w->shift; 1111 1112 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1113 mask, mask); 1114 return 0; 1115 } 1116 1117 static const char *hp_mux_text[] = { 1118 "Mixer", 1119 "DAC", 1120 }; 1121 1122 #define WM8994_HP_ENUM(xname, xenum) \ 1123 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1124 .info = snd_soc_info_enum_double, \ 1125 .get = snd_soc_dapm_get_enum_double, \ 1126 .put = wm8994_put_hp_enum, \ 1127 .private_value = (unsigned long)&xenum } 1128 1129 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, 1130 struct snd_ctl_elem_value *ucontrol) 1131 { 1132 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 1133 struct snd_soc_codec *codec = w->codec; 1134 int ret; 1135 1136 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1137 1138 wm8994_update_class_w(codec); 1139 1140 return ret; 1141 } 1142 1143 static const struct soc_enum hpl_enum = 1144 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); 1145 1146 static const struct snd_kcontrol_new hpl_mux = 1147 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); 1148 1149 static const struct soc_enum hpr_enum = 1150 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); 1151 1152 static const struct snd_kcontrol_new hpr_mux = 1153 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); 1154 1155 static const char *adc_mux_text[] = { 1156 "ADC", 1157 "DMIC", 1158 }; 1159 1160 static const struct soc_enum adc_enum = 1161 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 1162 1163 static const struct snd_kcontrol_new adcl_mux = 1164 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1165 1166 static const struct snd_kcontrol_new adcr_mux = 1167 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1168 1169 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1170 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1171 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1172 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1173 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1174 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1175 }; 1176 1177 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1178 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1179 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1180 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1181 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1182 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1183 }; 1184 1185 /* Debugging; dump chip status after DAPM transitions */ 1186 static int post_ev(struct snd_soc_dapm_widget *w, 1187 struct snd_kcontrol *kcontrol, int event) 1188 { 1189 struct snd_soc_codec *codec = w->codec; 1190 dev_dbg(codec->dev, "SRC status: %x\n", 1191 snd_soc_read(codec, 1192 WM8994_RATE_STATUS)); 1193 return 0; 1194 } 1195 1196 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1197 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1198 1, 1, 0), 1199 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1200 0, 1, 0), 1201 }; 1202 1203 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1204 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1205 1, 1, 0), 1206 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1207 0, 1, 0), 1208 }; 1209 1210 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1211 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1212 1, 1, 0), 1213 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1214 0, 1, 0), 1215 }; 1216 1217 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1218 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1219 1, 1, 0), 1220 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1221 0, 1, 0), 1222 }; 1223 1224 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1225 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1226 5, 1, 0), 1227 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1228 4, 1, 0), 1229 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1230 2, 1, 0), 1231 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1232 1, 1, 0), 1233 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1234 0, 1, 0), 1235 }; 1236 1237 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1238 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1239 5, 1, 0), 1240 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1241 4, 1, 0), 1242 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1243 2, 1, 0), 1244 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1245 1, 1, 0), 1246 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1247 0, 1, 0), 1248 }; 1249 1250 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1251 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1252 .info = snd_soc_info_volsw, \ 1253 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 1254 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 1255 1256 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1257 struct snd_ctl_elem_value *ucontrol) 1258 { 1259 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 1260 struct snd_soc_codec *codec = w->codec; 1261 int ret; 1262 1263 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1264 1265 wm8994_update_class_w(codec); 1266 1267 return ret; 1268 } 1269 1270 static const struct snd_kcontrol_new dac1l_mix[] = { 1271 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1272 5, 1, 0), 1273 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1274 4, 1, 0), 1275 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1276 2, 1, 0), 1277 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1278 1, 1, 0), 1279 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1280 0, 1, 0), 1281 }; 1282 1283 static const struct snd_kcontrol_new dac1r_mix[] = { 1284 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1285 5, 1, 0), 1286 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1287 4, 1, 0), 1288 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1289 2, 1, 0), 1290 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1291 1, 1, 0), 1292 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1293 0, 1, 0), 1294 }; 1295 1296 static const char *sidetone_text[] = { 1297 "ADC/DMIC1", "DMIC2", 1298 }; 1299 1300 static const struct soc_enum sidetone1_enum = 1301 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1302 1303 static const struct snd_kcontrol_new sidetone1_mux = 1304 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1305 1306 static const struct soc_enum sidetone2_enum = 1307 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1308 1309 static const struct snd_kcontrol_new sidetone2_mux = 1310 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1311 1312 static const char *aif1dac_text[] = { 1313 "AIF1DACDAT", "AIF3DACDAT", 1314 }; 1315 1316 static const struct soc_enum aif1dac_enum = 1317 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1318 1319 static const struct snd_kcontrol_new aif1dac_mux = 1320 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1321 1322 static const char *aif2dac_text[] = { 1323 "AIF2DACDAT", "AIF3DACDAT", 1324 }; 1325 1326 static const struct soc_enum aif2dac_enum = 1327 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1328 1329 static const struct snd_kcontrol_new aif2dac_mux = 1330 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1331 1332 static const char *aif2adc_text[] = { 1333 "AIF2ADCDAT", "AIF3DACDAT", 1334 }; 1335 1336 static const struct soc_enum aif2adc_enum = 1337 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1338 1339 static const struct snd_kcontrol_new aif2adc_mux = 1340 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1341 1342 static const char *aif3adc_text[] = { 1343 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1344 }; 1345 1346 static const struct soc_enum wm8994_aif3adc_enum = 1347 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1348 1349 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1350 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1351 1352 static const struct soc_enum wm8958_aif3adc_enum = 1353 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1354 1355 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1356 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1357 1358 static const char *mono_pcm_out_text[] = { 1359 "None", "AIF2ADCL", "AIF2ADCR", 1360 }; 1361 1362 static const struct soc_enum mono_pcm_out_enum = 1363 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1364 1365 static const struct snd_kcontrol_new mono_pcm_out_mux = 1366 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1367 1368 static const char *aif2dac_src_text[] = { 1369 "AIF2", "AIF3", 1370 }; 1371 1372 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1373 static const struct soc_enum aif2dacl_src_enum = 1374 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1375 1376 static const struct snd_kcontrol_new aif2dacl_src_mux = 1377 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1378 1379 static const struct soc_enum aif2dacr_src_enum = 1380 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1381 1382 static const struct snd_kcontrol_new aif2dacr_src_mux = 1383 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1384 1385 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1386 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev, 1387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1388 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev, 1389 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1390 1391 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1392 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1393 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1394 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1395 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1396 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1397 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1398 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1399 1400 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1401 }; 1402 1403 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1404 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 1405 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0) 1406 }; 1407 1408 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1409 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1410 dac_ev, SND_SOC_DAPM_PRE_PMU), 1411 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1412 dac_ev, SND_SOC_DAPM_PRE_PMU), 1413 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1414 dac_ev, SND_SOC_DAPM_PRE_PMU), 1415 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1416 dac_ev, SND_SOC_DAPM_PRE_PMU), 1417 }; 1418 1419 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1420 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1421 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1422 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1423 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1424 }; 1425 1426 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1427 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1428 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1429 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1430 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1431 }; 1432 1433 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1434 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1435 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1436 }; 1437 1438 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1439 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1440 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1441 SND_SOC_DAPM_INPUT("Clock"), 1442 1443 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1444 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1445 1446 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), 1447 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 1448 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 1449 1450 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1451 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1452 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1453 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1454 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1455 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, 1456 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1457 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1458 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, 1459 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1460 1461 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1462 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1463 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1464 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1465 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1466 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, 1467 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1468 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1469 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, 1470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1471 1472 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1473 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1474 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1475 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1476 1477 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1478 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1479 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1480 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1481 1482 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1483 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1484 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1485 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1486 1487 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1488 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1489 1490 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1491 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1492 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1493 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1494 1495 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1496 WM8994_POWER_MANAGEMENT_4, 13, 0), 1497 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1498 WM8994_POWER_MANAGEMENT_4, 12, 0), 1499 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1500 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev, 1501 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1502 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1503 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev, 1504 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1505 1506 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1507 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1508 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1509 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1510 1511 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1512 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1513 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1514 1515 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1516 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1517 1518 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1519 1520 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1521 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1522 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1523 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1524 1525 /* Power is done with the muxes since the ADC power also controls the 1526 * downsampling chain, the chip will automatically manage the analogue 1527 * specific portions. 1528 */ 1529 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1530 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1531 1532 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1533 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1534 1535 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1536 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1537 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1538 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1539 1540 SND_SOC_DAPM_POST("Debug log", post_ev), 1541 }; 1542 1543 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1544 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1545 }; 1546 1547 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1548 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1549 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1550 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1551 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1552 }; 1553 1554 static const struct snd_soc_dapm_route intercon[] = { 1555 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1556 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1557 1558 { "DSP1CLK", NULL, "CLK_SYS" }, 1559 { "DSP2CLK", NULL, "CLK_SYS" }, 1560 { "DSPINTCLK", NULL, "CLK_SYS" }, 1561 1562 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1563 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1564 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1565 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1566 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1567 1568 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1569 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1570 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1571 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1572 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1573 1574 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1575 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1576 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1577 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1578 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1579 1580 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1581 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1582 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1583 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1584 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1585 1586 { "AIF2ADCL", NULL, "AIF2CLK" }, 1587 { "AIF2ADCL", NULL, "DSP2CLK" }, 1588 { "AIF2ADCR", NULL, "AIF2CLK" }, 1589 { "AIF2ADCR", NULL, "DSP2CLK" }, 1590 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1591 1592 { "AIF2DACL", NULL, "AIF2CLK" }, 1593 { "AIF2DACL", NULL, "DSP2CLK" }, 1594 { "AIF2DACR", NULL, "AIF2CLK" }, 1595 { "AIF2DACR", NULL, "DSP2CLK" }, 1596 { "AIF2DACR", NULL, "DSPINTCLK" }, 1597 1598 { "DMIC1L", NULL, "DMIC1DAT" }, 1599 { "DMIC1L", NULL, "CLK_SYS" }, 1600 { "DMIC1R", NULL, "DMIC1DAT" }, 1601 { "DMIC1R", NULL, "CLK_SYS" }, 1602 { "DMIC2L", NULL, "DMIC2DAT" }, 1603 { "DMIC2L", NULL, "CLK_SYS" }, 1604 { "DMIC2R", NULL, "DMIC2DAT" }, 1605 { "DMIC2R", NULL, "CLK_SYS" }, 1606 1607 { "ADCL", NULL, "AIF1CLK" }, 1608 { "ADCL", NULL, "DSP1CLK" }, 1609 { "ADCL", NULL, "DSPINTCLK" }, 1610 1611 { "ADCR", NULL, "AIF1CLK" }, 1612 { "ADCR", NULL, "DSP1CLK" }, 1613 { "ADCR", NULL, "DSPINTCLK" }, 1614 1615 { "ADCL Mux", "ADC", "ADCL" }, 1616 { "ADCL Mux", "DMIC", "DMIC1L" }, 1617 { "ADCR Mux", "ADC", "ADCR" }, 1618 { "ADCR Mux", "DMIC", "DMIC1R" }, 1619 1620 { "DAC1L", NULL, "AIF1CLK" }, 1621 { "DAC1L", NULL, "DSP1CLK" }, 1622 { "DAC1L", NULL, "DSPINTCLK" }, 1623 1624 { "DAC1R", NULL, "AIF1CLK" }, 1625 { "DAC1R", NULL, "DSP1CLK" }, 1626 { "DAC1R", NULL, "DSPINTCLK" }, 1627 1628 { "DAC2L", NULL, "AIF2CLK" }, 1629 { "DAC2L", NULL, "DSP2CLK" }, 1630 { "DAC2L", NULL, "DSPINTCLK" }, 1631 1632 { "DAC2R", NULL, "AIF2DACR" }, 1633 { "DAC2R", NULL, "AIF2CLK" }, 1634 { "DAC2R", NULL, "DSP2CLK" }, 1635 { "DAC2R", NULL, "DSPINTCLK" }, 1636 1637 { "TOCLK", NULL, "CLK_SYS" }, 1638 1639 /* AIF1 outputs */ 1640 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1641 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1642 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1643 1644 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1645 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1646 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1647 1648 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1649 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1650 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1651 1652 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1653 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1654 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1655 1656 /* Pin level routing for AIF3 */ 1657 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1658 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1659 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1660 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1661 1662 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1663 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1664 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1665 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1666 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1667 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1668 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1669 1670 /* DAC1 inputs */ 1671 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1672 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1673 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1674 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1675 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1676 1677 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1678 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1679 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1680 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1681 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1682 1683 /* DAC2/AIF2 outputs */ 1684 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1685 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1686 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1687 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1688 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1689 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1690 1691 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1692 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1693 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1694 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1695 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1696 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1697 1698 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1699 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1700 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1701 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1702 1703 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1704 1705 /* AIF3 output */ 1706 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1707 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1708 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1709 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1710 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1711 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1712 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1713 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1714 1715 /* Sidetone */ 1716 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1717 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1718 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1719 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1720 1721 /* Output stages */ 1722 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1723 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1724 1725 { "SPKL", "DAC1 Switch", "DAC1L" }, 1726 { "SPKL", "DAC2 Switch", "DAC2L" }, 1727 1728 { "SPKR", "DAC1 Switch", "DAC1R" }, 1729 { "SPKR", "DAC2 Switch", "DAC2R" }, 1730 1731 { "Left Headphone Mux", "DAC", "DAC1L" }, 1732 { "Right Headphone Mux", "DAC", "DAC1R" }, 1733 }; 1734 1735 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1736 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1737 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1738 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1739 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1740 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1741 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1742 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1743 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1744 }; 1745 1746 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1747 { "DAC1L", NULL, "DAC1L Mixer" }, 1748 { "DAC1R", NULL, "DAC1R Mixer" }, 1749 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1750 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1751 }; 1752 1753 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1754 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1755 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 1756 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 1757 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 1758 }; 1759 1760 static const struct snd_soc_dapm_route wm8994_intercon[] = { 1761 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 1762 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 1763 }; 1764 1765 static const struct snd_soc_dapm_route wm8958_intercon[] = { 1766 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 1767 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 1768 1769 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 1770 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 1771 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1772 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1773 1774 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 1775 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 1776 1777 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 1778 }; 1779 1780 /* The size in bits of the FLL divide multiplied by 10 1781 * to allow rounding later */ 1782 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1783 1784 struct fll_div { 1785 u16 outdiv; 1786 u16 n; 1787 u16 k; 1788 u16 clk_ref_div; 1789 u16 fll_fratio; 1790 }; 1791 1792 static int wm8994_get_fll_config(struct fll_div *fll, 1793 int freq_in, int freq_out) 1794 { 1795 u64 Kpart; 1796 unsigned int K, Ndiv, Nmod; 1797 1798 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1799 1800 /* Scale the input frequency down to <= 13.5MHz */ 1801 fll->clk_ref_div = 0; 1802 while (freq_in > 13500000) { 1803 fll->clk_ref_div++; 1804 freq_in /= 2; 1805 1806 if (fll->clk_ref_div > 3) 1807 return -EINVAL; 1808 } 1809 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1810 1811 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1812 fll->outdiv = 3; 1813 while (freq_out * (fll->outdiv + 1) < 90000000) { 1814 fll->outdiv++; 1815 if (fll->outdiv > 63) 1816 return -EINVAL; 1817 } 1818 freq_out *= fll->outdiv + 1; 1819 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1820 1821 if (freq_in > 1000000) { 1822 fll->fll_fratio = 0; 1823 } else if (freq_in > 256000) { 1824 fll->fll_fratio = 1; 1825 freq_in *= 2; 1826 } else if (freq_in > 128000) { 1827 fll->fll_fratio = 2; 1828 freq_in *= 4; 1829 } else if (freq_in > 64000) { 1830 fll->fll_fratio = 3; 1831 freq_in *= 8; 1832 } else { 1833 fll->fll_fratio = 4; 1834 freq_in *= 16; 1835 } 1836 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1837 1838 /* Now, calculate N.K */ 1839 Ndiv = freq_out / freq_in; 1840 1841 fll->n = Ndiv; 1842 Nmod = freq_out % freq_in; 1843 pr_debug("Nmod=%d\n", Nmod); 1844 1845 /* Calculate fractional part - scale up so we can round. */ 1846 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1847 1848 do_div(Kpart, freq_in); 1849 1850 K = Kpart & 0xFFFFFFFF; 1851 1852 if ((K % 10) >= 5) 1853 K += 5; 1854 1855 /* Move down to proper range now rounding is done */ 1856 fll->k = K / 10; 1857 1858 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1859 1860 return 0; 1861 } 1862 1863 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 1864 unsigned int freq_in, unsigned int freq_out) 1865 { 1866 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1867 int reg_offset, ret; 1868 struct fll_div fll; 1869 u16 reg, aif1, aif2; 1870 1871 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) 1872 & WM8994_AIF1CLK_ENA; 1873 1874 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) 1875 & WM8994_AIF2CLK_ENA; 1876 1877 switch (id) { 1878 case WM8994_FLL1: 1879 reg_offset = 0; 1880 id = 0; 1881 break; 1882 case WM8994_FLL2: 1883 reg_offset = 0x20; 1884 id = 1; 1885 break; 1886 default: 1887 return -EINVAL; 1888 } 1889 1890 switch (src) { 1891 case 0: 1892 /* Allow no source specification when stopping */ 1893 if (freq_out) 1894 return -EINVAL; 1895 src = wm8994->fll[id].src; 1896 break; 1897 case WM8994_FLL_SRC_MCLK1: 1898 case WM8994_FLL_SRC_MCLK2: 1899 case WM8994_FLL_SRC_LRCLK: 1900 case WM8994_FLL_SRC_BCLK: 1901 break; 1902 default: 1903 return -EINVAL; 1904 } 1905 1906 /* Are we changing anything? */ 1907 if (wm8994->fll[id].src == src && 1908 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 1909 return 0; 1910 1911 /* If we're stopping the FLL redo the old config - no 1912 * registers will actually be written but we avoid GCC flow 1913 * analysis bugs spewing warnings. 1914 */ 1915 if (freq_out) 1916 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 1917 else 1918 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 1919 wm8994->fll[id].out); 1920 if (ret < 0) 1921 return ret; 1922 1923 /* Gate the AIF clocks while we reclock */ 1924 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1925 WM8994_AIF1CLK_ENA, 0); 1926 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1927 WM8994_AIF2CLK_ENA, 0); 1928 1929 /* We always need to disable the FLL while reconfiguring */ 1930 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1931 WM8994_FLL1_ENA, 0); 1932 1933 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 1934 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 1935 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 1936 WM8994_FLL1_OUTDIV_MASK | 1937 WM8994_FLL1_FRATIO_MASK, reg); 1938 1939 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); 1940 1941 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 1942 WM8994_FLL1_N_MASK, 1943 fll.n << WM8994_FLL1_N_SHIFT); 1944 1945 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 1946 WM8994_FLL1_REFCLK_DIV_MASK | 1947 WM8994_FLL1_REFCLK_SRC_MASK, 1948 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 1949 (src - 1)); 1950 1951 /* Enable (with fractional mode if required) */ 1952 if (freq_out) { 1953 if (fll.k) 1954 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; 1955 else 1956 reg = WM8994_FLL1_ENA; 1957 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1958 WM8994_FLL1_ENA | WM8994_FLL1_FRAC, 1959 reg); 1960 } 1961 1962 wm8994->fll[id].in = freq_in; 1963 wm8994->fll[id].out = freq_out; 1964 wm8994->fll[id].src = src; 1965 1966 /* Enable any gated AIF clocks */ 1967 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1968 WM8994_AIF1CLK_ENA, aif1); 1969 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1970 WM8994_AIF2CLK_ENA, aif2); 1971 1972 configure_clock(codec); 1973 1974 return 0; 1975 } 1976 1977 1978 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 1979 1980 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 1981 unsigned int freq_in, unsigned int freq_out) 1982 { 1983 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 1984 } 1985 1986 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 1987 int clk_id, unsigned int freq, int dir) 1988 { 1989 struct snd_soc_codec *codec = dai->codec; 1990 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1991 int i; 1992 1993 switch (dai->id) { 1994 case 1: 1995 case 2: 1996 break; 1997 1998 default: 1999 /* AIF3 shares clocking with AIF1/2 */ 2000 return -EINVAL; 2001 } 2002 2003 switch (clk_id) { 2004 case WM8994_SYSCLK_MCLK1: 2005 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2006 wm8994->mclk[0] = freq; 2007 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2008 dai->id, freq); 2009 break; 2010 2011 case WM8994_SYSCLK_MCLK2: 2012 /* TODO: Set GPIO AF */ 2013 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2014 wm8994->mclk[1] = freq; 2015 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2016 dai->id, freq); 2017 break; 2018 2019 case WM8994_SYSCLK_FLL1: 2020 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2021 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2022 break; 2023 2024 case WM8994_SYSCLK_FLL2: 2025 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2026 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2027 break; 2028 2029 case WM8994_SYSCLK_OPCLK: 2030 /* Special case - a division (times 10) is given and 2031 * no effect on main clocking. 2032 */ 2033 if (freq) { 2034 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2035 if (opclk_divs[i] == freq) 2036 break; 2037 if (i == ARRAY_SIZE(opclk_divs)) 2038 return -EINVAL; 2039 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 2040 WM8994_OPCLK_DIV_MASK, i); 2041 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2042 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2043 } else { 2044 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2045 WM8994_OPCLK_ENA, 0); 2046 } 2047 2048 default: 2049 return -EINVAL; 2050 } 2051 2052 configure_clock(codec); 2053 2054 return 0; 2055 } 2056 2057 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2058 enum snd_soc_bias_level level) 2059 { 2060 struct wm8994 *control = codec->control_data; 2061 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2062 2063 switch (level) { 2064 case SND_SOC_BIAS_ON: 2065 break; 2066 2067 case SND_SOC_BIAS_PREPARE: 2068 /* VMID=2x40k */ 2069 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2070 WM8994_VMID_SEL_MASK, 0x2); 2071 break; 2072 2073 case SND_SOC_BIAS_STANDBY: 2074 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2075 pm_runtime_get_sync(codec->dev); 2076 2077 switch (control->type) { 2078 case WM8994: 2079 if (wm8994->revision < 4) { 2080 /* Tweak DC servo and DSP 2081 * configuration for improved 2082 * performance. */ 2083 snd_soc_write(codec, 0x102, 0x3); 2084 snd_soc_write(codec, 0x56, 0x3); 2085 snd_soc_write(codec, 0x817, 0); 2086 snd_soc_write(codec, 0x102, 0); 2087 } 2088 break; 2089 2090 case WM8958: 2091 if (wm8994->revision == 0) { 2092 /* Optimise performance for rev A */ 2093 snd_soc_write(codec, 0x102, 0x3); 2094 snd_soc_write(codec, 0xcb, 0x81); 2095 snd_soc_write(codec, 0x817, 0); 2096 snd_soc_write(codec, 0x102, 0); 2097 2098 snd_soc_update_bits(codec, 2099 WM8958_CHARGE_PUMP_2, 2100 WM8958_CP_DISCH, 2101 WM8958_CP_DISCH); 2102 } 2103 break; 2104 } 2105 2106 /* Discharge LINEOUT1 & 2 */ 2107 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2108 WM8994_LINEOUT1_DISCH | 2109 WM8994_LINEOUT2_DISCH, 2110 WM8994_LINEOUT1_DISCH | 2111 WM8994_LINEOUT2_DISCH); 2112 2113 /* Startup bias, VMID ramp & buffer */ 2114 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 2115 WM8994_STARTUP_BIAS_ENA | 2116 WM8994_VMID_BUF_ENA | 2117 WM8994_VMID_RAMP_MASK, 2118 WM8994_STARTUP_BIAS_ENA | 2119 WM8994_VMID_BUF_ENA | 2120 (0x11 << WM8994_VMID_RAMP_SHIFT)); 2121 2122 /* Main bias enable, VMID=2x40k */ 2123 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2124 WM8994_BIAS_ENA | 2125 WM8994_VMID_SEL_MASK, 2126 WM8994_BIAS_ENA | 0x2); 2127 2128 msleep(20); 2129 } 2130 2131 /* VMID=2x500k */ 2132 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2133 WM8994_VMID_SEL_MASK, 0x4); 2134 2135 break; 2136 2137 case SND_SOC_BIAS_OFF: 2138 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 2139 /* Switch over to startup biases */ 2140 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 2141 WM8994_BIAS_SRC | 2142 WM8994_STARTUP_BIAS_ENA | 2143 WM8994_VMID_BUF_ENA | 2144 WM8994_VMID_RAMP_MASK, 2145 WM8994_BIAS_SRC | 2146 WM8994_STARTUP_BIAS_ENA | 2147 WM8994_VMID_BUF_ENA | 2148 (1 << WM8994_VMID_RAMP_SHIFT)); 2149 2150 /* Disable main biases */ 2151 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 2152 WM8994_BIAS_ENA | 2153 WM8994_VMID_SEL_MASK, 0); 2154 2155 /* Discharge line */ 2156 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2157 WM8994_LINEOUT1_DISCH | 2158 WM8994_LINEOUT2_DISCH, 2159 WM8994_LINEOUT1_DISCH | 2160 WM8994_LINEOUT2_DISCH); 2161 2162 msleep(5); 2163 2164 /* Switch off startup biases */ 2165 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 2166 WM8994_BIAS_SRC | 2167 WM8994_STARTUP_BIAS_ENA | 2168 WM8994_VMID_BUF_ENA | 2169 WM8994_VMID_RAMP_MASK, 0); 2170 2171 pm_runtime_put(codec->dev); 2172 } 2173 break; 2174 } 2175 codec->dapm.bias_level = level; 2176 return 0; 2177 } 2178 2179 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2180 { 2181 struct snd_soc_codec *codec = dai->codec; 2182 struct wm8994 *control = codec->control_data; 2183 int ms_reg; 2184 int aif1_reg; 2185 int ms = 0; 2186 int aif1 = 0; 2187 2188 switch (dai->id) { 2189 case 1: 2190 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2191 aif1_reg = WM8994_AIF1_CONTROL_1; 2192 break; 2193 case 2: 2194 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2195 aif1_reg = WM8994_AIF2_CONTROL_1; 2196 break; 2197 default: 2198 return -EINVAL; 2199 } 2200 2201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2202 case SND_SOC_DAIFMT_CBS_CFS: 2203 break; 2204 case SND_SOC_DAIFMT_CBM_CFM: 2205 ms = WM8994_AIF1_MSTR; 2206 break; 2207 default: 2208 return -EINVAL; 2209 } 2210 2211 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2212 case SND_SOC_DAIFMT_DSP_B: 2213 aif1 |= WM8994_AIF1_LRCLK_INV; 2214 case SND_SOC_DAIFMT_DSP_A: 2215 aif1 |= 0x18; 2216 break; 2217 case SND_SOC_DAIFMT_I2S: 2218 aif1 |= 0x10; 2219 break; 2220 case SND_SOC_DAIFMT_RIGHT_J: 2221 break; 2222 case SND_SOC_DAIFMT_LEFT_J: 2223 aif1 |= 0x8; 2224 break; 2225 default: 2226 return -EINVAL; 2227 } 2228 2229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2230 case SND_SOC_DAIFMT_DSP_A: 2231 case SND_SOC_DAIFMT_DSP_B: 2232 /* frame inversion not valid for DSP modes */ 2233 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2234 case SND_SOC_DAIFMT_NB_NF: 2235 break; 2236 case SND_SOC_DAIFMT_IB_NF: 2237 aif1 |= WM8994_AIF1_BCLK_INV; 2238 break; 2239 default: 2240 return -EINVAL; 2241 } 2242 break; 2243 2244 case SND_SOC_DAIFMT_I2S: 2245 case SND_SOC_DAIFMT_RIGHT_J: 2246 case SND_SOC_DAIFMT_LEFT_J: 2247 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2248 case SND_SOC_DAIFMT_NB_NF: 2249 break; 2250 case SND_SOC_DAIFMT_IB_IF: 2251 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2252 break; 2253 case SND_SOC_DAIFMT_IB_NF: 2254 aif1 |= WM8994_AIF1_BCLK_INV; 2255 break; 2256 case SND_SOC_DAIFMT_NB_IF: 2257 aif1 |= WM8994_AIF1_LRCLK_INV; 2258 break; 2259 default: 2260 return -EINVAL; 2261 } 2262 break; 2263 default: 2264 return -EINVAL; 2265 } 2266 2267 /* The AIF2 format configuration needs to be mirrored to AIF3 2268 * on WM8958 if it's in use so just do it all the time. */ 2269 if (control->type == WM8958 && dai->id == 2) 2270 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2271 WM8994_AIF1_LRCLK_INV | 2272 WM8958_AIF3_FMT_MASK, aif1); 2273 2274 snd_soc_update_bits(codec, aif1_reg, 2275 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2276 WM8994_AIF1_FMT_MASK, 2277 aif1); 2278 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2279 ms); 2280 2281 return 0; 2282 } 2283 2284 static struct { 2285 int val, rate; 2286 } srs[] = { 2287 { 0, 8000 }, 2288 { 1, 11025 }, 2289 { 2, 12000 }, 2290 { 3, 16000 }, 2291 { 4, 22050 }, 2292 { 5, 24000 }, 2293 { 6, 32000 }, 2294 { 7, 44100 }, 2295 { 8, 48000 }, 2296 { 9, 88200 }, 2297 { 10, 96000 }, 2298 }; 2299 2300 static int fs_ratios[] = { 2301 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2302 }; 2303 2304 static int bclk_divs[] = { 2305 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2306 640, 880, 960, 1280, 1760, 1920 2307 }; 2308 2309 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2310 struct snd_pcm_hw_params *params, 2311 struct snd_soc_dai *dai) 2312 { 2313 struct snd_soc_codec *codec = dai->codec; 2314 struct wm8994 *control = codec->control_data; 2315 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2316 int aif1_reg; 2317 int aif2_reg; 2318 int bclk_reg; 2319 int lrclk_reg; 2320 int rate_reg; 2321 int aif1 = 0; 2322 int aif2 = 0; 2323 int bclk = 0; 2324 int lrclk = 0; 2325 int rate_val = 0; 2326 int id = dai->id - 1; 2327 2328 int i, cur_val, best_val, bclk_rate, best; 2329 2330 switch (dai->id) { 2331 case 1: 2332 aif1_reg = WM8994_AIF1_CONTROL_1; 2333 aif2_reg = WM8994_AIF1_CONTROL_2; 2334 bclk_reg = WM8994_AIF1_BCLK; 2335 rate_reg = WM8994_AIF1_RATE; 2336 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2337 wm8994->lrclk_shared[0]) { 2338 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2339 } else { 2340 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2341 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2342 } 2343 break; 2344 case 2: 2345 aif1_reg = WM8994_AIF2_CONTROL_1; 2346 aif2_reg = WM8994_AIF2_CONTROL_2; 2347 bclk_reg = WM8994_AIF2_BCLK; 2348 rate_reg = WM8994_AIF2_RATE; 2349 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2350 wm8994->lrclk_shared[1]) { 2351 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2352 } else { 2353 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2354 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2355 } 2356 break; 2357 case 3: 2358 switch (control->type) { 2359 case WM8958: 2360 aif1_reg = WM8958_AIF3_CONTROL_1; 2361 break; 2362 default: 2363 return 0; 2364 } 2365 default: 2366 return -EINVAL; 2367 } 2368 2369 bclk_rate = params_rate(params) * 2; 2370 switch (params_format(params)) { 2371 case SNDRV_PCM_FORMAT_S16_LE: 2372 bclk_rate *= 16; 2373 break; 2374 case SNDRV_PCM_FORMAT_S20_3LE: 2375 bclk_rate *= 20; 2376 aif1 |= 0x20; 2377 break; 2378 case SNDRV_PCM_FORMAT_S24_LE: 2379 bclk_rate *= 24; 2380 aif1 |= 0x40; 2381 break; 2382 case SNDRV_PCM_FORMAT_S32_LE: 2383 bclk_rate *= 32; 2384 aif1 |= 0x60; 2385 break; 2386 default: 2387 return -EINVAL; 2388 } 2389 2390 /* Try to find an appropriate sample rate; look for an exact match. */ 2391 for (i = 0; i < ARRAY_SIZE(srs); i++) 2392 if (srs[i].rate == params_rate(params)) 2393 break; 2394 if (i == ARRAY_SIZE(srs)) 2395 return -EINVAL; 2396 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2397 2398 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2399 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2400 dai->id, wm8994->aifclk[id], bclk_rate); 2401 2402 if (params_channels(params) == 1 && 2403 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2404 aif2 |= WM8994_AIF1_MONO; 2405 2406 if (wm8994->aifclk[id] == 0) { 2407 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2408 return -EINVAL; 2409 } 2410 2411 /* AIFCLK/fs ratio; look for a close match in either direction */ 2412 best = 0; 2413 best_val = abs((fs_ratios[0] * params_rate(params)) 2414 - wm8994->aifclk[id]); 2415 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2416 cur_val = abs((fs_ratios[i] * params_rate(params)) 2417 - wm8994->aifclk[id]); 2418 if (cur_val >= best_val) 2419 continue; 2420 best = i; 2421 best_val = cur_val; 2422 } 2423 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2424 dai->id, fs_ratios[best]); 2425 rate_val |= best; 2426 2427 /* We may not get quite the right frequency if using 2428 * approximate clocks so look for the closest match that is 2429 * higher than the target (we need to ensure that there enough 2430 * BCLKs to clock out the samples). 2431 */ 2432 best = 0; 2433 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2434 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2435 if (cur_val < 0) /* BCLK table is sorted */ 2436 break; 2437 best = i; 2438 } 2439 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2440 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2441 bclk_divs[best], bclk_rate); 2442 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2443 2444 lrclk = bclk_rate / params_rate(params); 2445 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2446 lrclk, bclk_rate / lrclk); 2447 2448 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2449 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2450 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2451 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2452 lrclk); 2453 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2454 WM8994_AIF1CLK_RATE_MASK, rate_val); 2455 2456 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2457 switch (dai->id) { 2458 case 1: 2459 wm8994->dac_rates[0] = params_rate(params); 2460 wm8994_set_retune_mobile(codec, 0); 2461 wm8994_set_retune_mobile(codec, 1); 2462 break; 2463 case 2: 2464 wm8994->dac_rates[1] = params_rate(params); 2465 wm8994_set_retune_mobile(codec, 2); 2466 break; 2467 } 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2474 struct snd_pcm_hw_params *params, 2475 struct snd_soc_dai *dai) 2476 { 2477 struct snd_soc_codec *codec = dai->codec; 2478 struct wm8994 *control = codec->control_data; 2479 int aif1_reg; 2480 int aif1 = 0; 2481 2482 switch (dai->id) { 2483 case 3: 2484 switch (control->type) { 2485 case WM8958: 2486 aif1_reg = WM8958_AIF3_CONTROL_1; 2487 break; 2488 default: 2489 return 0; 2490 } 2491 default: 2492 return 0; 2493 } 2494 2495 switch (params_format(params)) { 2496 case SNDRV_PCM_FORMAT_S16_LE: 2497 break; 2498 case SNDRV_PCM_FORMAT_S20_3LE: 2499 aif1 |= 0x20; 2500 break; 2501 case SNDRV_PCM_FORMAT_S24_LE: 2502 aif1 |= 0x40; 2503 break; 2504 case SNDRV_PCM_FORMAT_S32_LE: 2505 aif1 |= 0x60; 2506 break; 2507 default: 2508 return -EINVAL; 2509 } 2510 2511 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2512 } 2513 2514 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2515 { 2516 struct snd_soc_codec *codec = codec_dai->codec; 2517 int mute_reg; 2518 int reg; 2519 2520 switch (codec_dai->id) { 2521 case 1: 2522 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2523 break; 2524 case 2: 2525 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2526 break; 2527 default: 2528 return -EINVAL; 2529 } 2530 2531 if (mute) 2532 reg = WM8994_AIF1DAC1_MUTE; 2533 else 2534 reg = 0; 2535 2536 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2537 2538 return 0; 2539 } 2540 2541 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 2542 { 2543 struct snd_soc_codec *codec = codec_dai->codec; 2544 int reg, val, mask; 2545 2546 switch (codec_dai->id) { 2547 case 1: 2548 reg = WM8994_AIF1_MASTER_SLAVE; 2549 mask = WM8994_AIF1_TRI; 2550 break; 2551 case 2: 2552 reg = WM8994_AIF2_MASTER_SLAVE; 2553 mask = WM8994_AIF2_TRI; 2554 break; 2555 case 3: 2556 reg = WM8994_POWER_MANAGEMENT_6; 2557 mask = WM8994_AIF3_TRI; 2558 break; 2559 default: 2560 return -EINVAL; 2561 } 2562 2563 if (tristate) 2564 val = mask; 2565 else 2566 val = 0; 2567 2568 return snd_soc_update_bits(codec, reg, mask, val); 2569 } 2570 2571 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2572 2573 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2574 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2575 2576 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2577 .set_sysclk = wm8994_set_dai_sysclk, 2578 .set_fmt = wm8994_set_dai_fmt, 2579 .hw_params = wm8994_hw_params, 2580 .digital_mute = wm8994_aif_mute, 2581 .set_pll = wm8994_set_fll, 2582 .set_tristate = wm8994_set_tristate, 2583 }; 2584 2585 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2586 .set_sysclk = wm8994_set_dai_sysclk, 2587 .set_fmt = wm8994_set_dai_fmt, 2588 .hw_params = wm8994_hw_params, 2589 .digital_mute = wm8994_aif_mute, 2590 .set_pll = wm8994_set_fll, 2591 .set_tristate = wm8994_set_tristate, 2592 }; 2593 2594 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2595 .hw_params = wm8994_aif3_hw_params, 2596 .set_tristate = wm8994_set_tristate, 2597 }; 2598 2599 static struct snd_soc_dai_driver wm8994_dai[] = { 2600 { 2601 .name = "wm8994-aif1", 2602 .id = 1, 2603 .playback = { 2604 .stream_name = "AIF1 Playback", 2605 .channels_min = 1, 2606 .channels_max = 2, 2607 .rates = WM8994_RATES, 2608 .formats = WM8994_FORMATS, 2609 }, 2610 .capture = { 2611 .stream_name = "AIF1 Capture", 2612 .channels_min = 1, 2613 .channels_max = 2, 2614 .rates = WM8994_RATES, 2615 .formats = WM8994_FORMATS, 2616 }, 2617 .ops = &wm8994_aif1_dai_ops, 2618 }, 2619 { 2620 .name = "wm8994-aif2", 2621 .id = 2, 2622 .playback = { 2623 .stream_name = "AIF2 Playback", 2624 .channels_min = 1, 2625 .channels_max = 2, 2626 .rates = WM8994_RATES, 2627 .formats = WM8994_FORMATS, 2628 }, 2629 .capture = { 2630 .stream_name = "AIF2 Capture", 2631 .channels_min = 1, 2632 .channels_max = 2, 2633 .rates = WM8994_RATES, 2634 .formats = WM8994_FORMATS, 2635 }, 2636 .ops = &wm8994_aif2_dai_ops, 2637 }, 2638 { 2639 .name = "wm8994-aif3", 2640 .id = 3, 2641 .playback = { 2642 .stream_name = "AIF3 Playback", 2643 .channels_min = 1, 2644 .channels_max = 2, 2645 .rates = WM8994_RATES, 2646 .formats = WM8994_FORMATS, 2647 }, 2648 .capture = { 2649 .stream_name = "AIF3 Capture", 2650 .channels_min = 1, 2651 .channels_max = 2, 2652 .rates = WM8994_RATES, 2653 .formats = WM8994_FORMATS, 2654 }, 2655 .ops = &wm8994_aif3_dai_ops, 2656 } 2657 }; 2658 2659 #ifdef CONFIG_PM 2660 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) 2661 { 2662 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2663 int i, ret; 2664 2665 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2666 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 2667 sizeof(struct fll_config)); 2668 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 2669 if (ret < 0) 2670 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 2671 i + 1, ret); 2672 } 2673 2674 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 2675 2676 return 0; 2677 } 2678 2679 static int wm8994_resume(struct snd_soc_codec *codec) 2680 { 2681 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2682 int i, ret; 2683 unsigned int val, mask; 2684 2685 if (wm8994->revision < 4) { 2686 /* force a HW read */ 2687 val = wm8994_reg_read(codec->control_data, 2688 WM8994_POWER_MANAGEMENT_5); 2689 2690 /* modify the cache only */ 2691 codec->cache_only = 1; 2692 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | 2693 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; 2694 val &= mask; 2695 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 2696 mask, val); 2697 codec->cache_only = 0; 2698 } 2699 2700 /* Restore the registers */ 2701 ret = snd_soc_cache_sync(codec); 2702 if (ret != 0) 2703 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 2704 2705 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2706 2707 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2708 if (!wm8994->fll_suspend[i].out) 2709 continue; 2710 2711 ret = _wm8994_set_fll(codec, i + 1, 2712 wm8994->fll_suspend[i].src, 2713 wm8994->fll_suspend[i].in, 2714 wm8994->fll_suspend[i].out); 2715 if (ret < 0) 2716 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 2717 i + 1, ret); 2718 } 2719 2720 return 0; 2721 } 2722 #else 2723 #define wm8994_suspend NULL 2724 #define wm8994_resume NULL 2725 #endif 2726 2727 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 2728 { 2729 struct snd_soc_codec *codec = wm8994->codec; 2730 struct wm8994_pdata *pdata = wm8994->pdata; 2731 struct snd_kcontrol_new controls[] = { 2732 SOC_ENUM_EXT("AIF1.1 EQ Mode", 2733 wm8994->retune_mobile_enum, 2734 wm8994_get_retune_mobile_enum, 2735 wm8994_put_retune_mobile_enum), 2736 SOC_ENUM_EXT("AIF1.2 EQ Mode", 2737 wm8994->retune_mobile_enum, 2738 wm8994_get_retune_mobile_enum, 2739 wm8994_put_retune_mobile_enum), 2740 SOC_ENUM_EXT("AIF2 EQ Mode", 2741 wm8994->retune_mobile_enum, 2742 wm8994_get_retune_mobile_enum, 2743 wm8994_put_retune_mobile_enum), 2744 }; 2745 int ret, i, j; 2746 const char **t; 2747 2748 /* We need an array of texts for the enum API but the number 2749 * of texts is likely to be less than the number of 2750 * configurations due to the sample rate dependency of the 2751 * configurations. */ 2752 wm8994->num_retune_mobile_texts = 0; 2753 wm8994->retune_mobile_texts = NULL; 2754 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2755 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 2756 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2757 wm8994->retune_mobile_texts[j]) == 0) 2758 break; 2759 } 2760 2761 if (j != wm8994->num_retune_mobile_texts) 2762 continue; 2763 2764 /* Expand the array... */ 2765 t = krealloc(wm8994->retune_mobile_texts, 2766 sizeof(char *) * 2767 (wm8994->num_retune_mobile_texts + 1), 2768 GFP_KERNEL); 2769 if (t == NULL) 2770 continue; 2771 2772 /* ...store the new entry... */ 2773 t[wm8994->num_retune_mobile_texts] = 2774 pdata->retune_mobile_cfgs[i].name; 2775 2776 /* ...and remember the new version. */ 2777 wm8994->num_retune_mobile_texts++; 2778 wm8994->retune_mobile_texts = t; 2779 } 2780 2781 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2782 wm8994->num_retune_mobile_texts); 2783 2784 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 2785 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 2786 2787 ret = snd_soc_add_controls(wm8994->codec, controls, 2788 ARRAY_SIZE(controls)); 2789 if (ret != 0) 2790 dev_err(wm8994->codec->dev, 2791 "Failed to add ReTune Mobile controls: %d\n", ret); 2792 } 2793 2794 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 2795 { 2796 struct snd_soc_codec *codec = wm8994->codec; 2797 struct wm8994_pdata *pdata = wm8994->pdata; 2798 int ret, i; 2799 2800 if (!pdata) 2801 return; 2802 2803 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 2804 pdata->lineout2_diff, 2805 pdata->lineout1fb, 2806 pdata->lineout2fb, 2807 pdata->jd_scthr, 2808 pdata->jd_thr, 2809 pdata->micbias1_lvl, 2810 pdata->micbias2_lvl); 2811 2812 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2813 2814 if (pdata->num_drc_cfgs) { 2815 struct snd_kcontrol_new controls[] = { 2816 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 2817 wm8994_get_drc_enum, wm8994_put_drc_enum), 2818 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 2819 wm8994_get_drc_enum, wm8994_put_drc_enum), 2820 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 2821 wm8994_get_drc_enum, wm8994_put_drc_enum), 2822 }; 2823 2824 /* We need an array of texts for the enum API */ 2825 wm8994->drc_texts = kmalloc(sizeof(char *) 2826 * pdata->num_drc_cfgs, GFP_KERNEL); 2827 if (!wm8994->drc_texts) { 2828 dev_err(wm8994->codec->dev, 2829 "Failed to allocate %d DRC config texts\n", 2830 pdata->num_drc_cfgs); 2831 return; 2832 } 2833 2834 for (i = 0; i < pdata->num_drc_cfgs; i++) 2835 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 2836 2837 wm8994->drc_enum.max = pdata->num_drc_cfgs; 2838 wm8994->drc_enum.texts = wm8994->drc_texts; 2839 2840 ret = snd_soc_add_controls(wm8994->codec, controls, 2841 ARRAY_SIZE(controls)); 2842 if (ret != 0) 2843 dev_err(wm8994->codec->dev, 2844 "Failed to add DRC mode controls: %d\n", ret); 2845 2846 for (i = 0; i < WM8994_NUM_DRC; i++) 2847 wm8994_set_drc(codec, i); 2848 } 2849 2850 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2851 pdata->num_retune_mobile_cfgs); 2852 2853 if (pdata->num_mbc_cfgs) { 2854 struct snd_kcontrol_new control[] = { 2855 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum, 2856 wm8958_get_mbc_enum, wm8958_put_mbc_enum), 2857 }; 2858 2859 /* We need an array of texts for the enum API */ 2860 wm8994->mbc_texts = kmalloc(sizeof(char *) 2861 * pdata->num_mbc_cfgs, GFP_KERNEL); 2862 if (!wm8994->mbc_texts) { 2863 dev_err(wm8994->codec->dev, 2864 "Failed to allocate %d MBC config texts\n", 2865 pdata->num_mbc_cfgs); 2866 return; 2867 } 2868 2869 for (i = 0; i < pdata->num_mbc_cfgs; i++) 2870 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name; 2871 2872 wm8994->mbc_enum.max = pdata->num_mbc_cfgs; 2873 wm8994->mbc_enum.texts = wm8994->mbc_texts; 2874 2875 ret = snd_soc_add_controls(wm8994->codec, control, 1); 2876 if (ret != 0) 2877 dev_err(wm8994->codec->dev, 2878 "Failed to add MBC mode controls: %d\n", ret); 2879 } 2880 2881 if (pdata->num_retune_mobile_cfgs) 2882 wm8994_handle_retune_mobile_pdata(wm8994); 2883 else 2884 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, 2885 ARRAY_SIZE(wm8994_eq_controls)); 2886 } 2887 2888 /** 2889 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 2890 * 2891 * @codec: WM8994 codec 2892 * @jack: jack to report detection events on 2893 * @micbias: microphone bias to detect on 2894 * @det: value to report for presence detection 2895 * @shrt: value to report for short detection 2896 * 2897 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 2898 * being used to bring out signals to the processor then only platform 2899 * data configuration is needed for WM8994 and processor GPIOs should 2900 * be configured using snd_soc_jack_add_gpios() instead. 2901 * 2902 * Configuration of detection levels is available via the micbias1_lvl 2903 * and micbias2_lvl platform data members. 2904 */ 2905 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2906 int micbias, int det, int shrt) 2907 { 2908 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2909 struct wm8994_micdet *micdet; 2910 struct wm8994 *control = codec->control_data; 2911 int reg; 2912 2913 if (control->type != WM8994) 2914 return -EINVAL; 2915 2916 switch (micbias) { 2917 case 1: 2918 micdet = &wm8994->micdet[0]; 2919 break; 2920 case 2: 2921 micdet = &wm8994->micdet[1]; 2922 break; 2923 default: 2924 return -EINVAL; 2925 } 2926 2927 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", 2928 micbias, det, shrt); 2929 2930 /* Store the configuration */ 2931 micdet->jack = jack; 2932 micdet->det = det; 2933 micdet->shrt = shrt; 2934 2935 /* If either of the jacks is set up then enable detection */ 2936 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 2937 reg = WM8994_MICD_ENA; 2938 else 2939 reg = 0; 2940 2941 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 2942 2943 return 0; 2944 } 2945 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 2946 2947 static irqreturn_t wm8994_mic_irq(int irq, void *data) 2948 { 2949 struct wm8994_priv *priv = data; 2950 struct snd_soc_codec *codec = priv->codec; 2951 int reg; 2952 int report; 2953 2954 #ifndef CONFIG_SND_SOC_WM8994_MODULE 2955 trace_snd_soc_jack_irq(dev_name(codec->dev)); 2956 #endif 2957 2958 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2959 if (reg < 0) { 2960 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2961 reg); 2962 return IRQ_HANDLED; 2963 } 2964 2965 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 2966 2967 report = 0; 2968 if (reg & WM8994_MIC1_DET_STS) 2969 report |= priv->micdet[0].det; 2970 if (reg & WM8994_MIC1_SHRT_STS) 2971 report |= priv->micdet[0].shrt; 2972 snd_soc_jack_report(priv->micdet[0].jack, report, 2973 priv->micdet[0].det | priv->micdet[0].shrt); 2974 2975 report = 0; 2976 if (reg & WM8994_MIC2_DET_STS) 2977 report |= priv->micdet[1].det; 2978 if (reg & WM8994_MIC2_SHRT_STS) 2979 report |= priv->micdet[1].shrt; 2980 snd_soc_jack_report(priv->micdet[1].jack, report, 2981 priv->micdet[1].det | priv->micdet[1].shrt); 2982 2983 return IRQ_HANDLED; 2984 } 2985 2986 /* Default microphone detection handler for WM8958 - the user can 2987 * override this if they wish. 2988 */ 2989 static void wm8958_default_micdet(u16 status, void *data) 2990 { 2991 struct snd_soc_codec *codec = data; 2992 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2993 int report = 0; 2994 2995 /* If nothing present then clear our statuses */ 2996 if (!(status & WM8958_MICD_STS)) { 2997 wm8994->jack_is_video = false; 2998 wm8994->jack_is_mic = false; 2999 goto done; 3000 } 3001 3002 /* Assume anything over 475 ohms is a microphone and remember 3003 * that we've seen one (since buttons override it) */ 3004 if (status & 0x600) 3005 wm8994->jack_is_mic = true; 3006 if (wm8994->jack_is_mic) 3007 report |= SND_JACK_MICROPHONE; 3008 3009 /* Video has an impedence of approximately 75 ohms; assume 3010 * this isn't used as a button and remember it since buttons 3011 * override it. */ 3012 if (status & 0x40) 3013 wm8994->jack_is_video = true; 3014 if (wm8994->jack_is_video) 3015 report |= SND_JACK_VIDEOOUT; 3016 3017 /* Everything else is buttons; just assign slots */ 3018 if (status & 0x4) 3019 report |= SND_JACK_BTN_0; 3020 if (status & 0x8) 3021 report |= SND_JACK_BTN_1; 3022 if (status & 0x10) 3023 report |= SND_JACK_BTN_2; 3024 if (status & 0x20) 3025 report |= SND_JACK_BTN_3; 3026 if (status & 0x80) 3027 report |= SND_JACK_BTN_4; 3028 if (status & 0x100) 3029 report |= SND_JACK_BTN_5; 3030 3031 done: 3032 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3033 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | 3034 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 | 3035 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT); 3036 } 3037 3038 /** 3039 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3040 * 3041 * @codec: WM8958 codec 3042 * @jack: jack to report detection events on 3043 * 3044 * Enable microphone detection functionality for the WM8958. By 3045 * default simple detection which supports the detection of up to 6 3046 * buttons plus video and microphone functionality is supported. 3047 * 3048 * The WM8958 has an advanced jack detection facility which is able to 3049 * support complex accessory detection, especially when used in 3050 * conjunction with external circuitry. In order to provide maximum 3051 * flexiblity a callback is provided which allows a completely custom 3052 * detection algorithm. 3053 */ 3054 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3055 wm8958_micdet_cb cb, void *cb_data) 3056 { 3057 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3058 struct wm8994 *control = codec->control_data; 3059 3060 if (control->type != WM8958) 3061 return -EINVAL; 3062 3063 if (jack) { 3064 if (!cb) { 3065 dev_dbg(codec->dev, "Using default micdet callback\n"); 3066 cb = wm8958_default_micdet; 3067 cb_data = codec; 3068 } 3069 3070 wm8994->micdet[0].jack = jack; 3071 wm8994->jack_cb = cb; 3072 wm8994->jack_cb_data = cb_data; 3073 3074 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3075 WM8958_MICD_ENA, WM8958_MICD_ENA); 3076 } else { 3077 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3078 WM8958_MICD_ENA, 0); 3079 } 3080 3081 return 0; 3082 } 3083 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3084 3085 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3086 { 3087 struct wm8994_priv *wm8994 = data; 3088 struct snd_soc_codec *codec = wm8994->codec; 3089 int reg; 3090 3091 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 3092 if (reg < 0) { 3093 dev_err(codec->dev, "Failed to read mic detect status: %d\n", 3094 reg); 3095 return IRQ_NONE; 3096 } 3097 3098 if (!(reg & WM8958_MICD_VALID)) { 3099 dev_dbg(codec->dev, "Mic detect data not valid\n"); 3100 goto out; 3101 } 3102 3103 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3104 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3105 #endif 3106 3107 if (wm8994->jack_cb) 3108 wm8994->jack_cb(reg, wm8994->jack_cb_data); 3109 else 3110 dev_warn(codec->dev, "Accessory detection with no callback\n"); 3111 3112 out: 3113 return IRQ_HANDLED; 3114 } 3115 3116 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3117 { 3118 struct wm8994 *control; 3119 struct wm8994_priv *wm8994; 3120 struct snd_soc_dapm_context *dapm = &codec->dapm; 3121 int ret, i; 3122 3123 codec->control_data = dev_get_drvdata(codec->dev->parent); 3124 control = codec->control_data; 3125 3126 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 3127 if (wm8994 == NULL) 3128 return -ENOMEM; 3129 snd_soc_codec_set_drvdata(codec, wm8994); 3130 3131 wm8994->pdata = dev_get_platdata(codec->dev->parent); 3132 wm8994->codec = codec; 3133 3134 pm_runtime_enable(codec->dev); 3135 pm_runtime_resume(codec->dev); 3136 3137 /* Read our current status back from the chip - we don't want to 3138 * reset as this may interfere with the GPIO or LDO operation. */ 3139 for (i = 0; i < WM8994_CACHE_SIZE; i++) { 3140 if (!wm8994_readable(i) || wm8994_volatile(i)) 3141 continue; 3142 3143 ret = wm8994_reg_read(codec->control_data, i); 3144 if (ret <= 0) 3145 continue; 3146 3147 ret = snd_soc_cache_write(codec, i, ret); 3148 if (ret != 0) { 3149 dev_err(codec->dev, 3150 "Failed to initialise cache for 0x%x: %d\n", 3151 i, ret); 3152 goto err; 3153 } 3154 } 3155 3156 /* Set revision-specific configuration */ 3157 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 3158 switch (control->type) { 3159 case WM8994: 3160 switch (wm8994->revision) { 3161 case 2: 3162 case 3: 3163 wm8994->hubs.dcs_codes = -5; 3164 wm8994->hubs.hp_startup_mode = 1; 3165 wm8994->hubs.dcs_readback_mode = 1; 3166 break; 3167 default: 3168 wm8994->hubs.dcs_readback_mode = 1; 3169 break; 3170 } 3171 3172 case WM8958: 3173 wm8994->hubs.dcs_readback_mode = 1; 3174 break; 3175 3176 default: 3177 break; 3178 } 3179 3180 switch (control->type) { 3181 case WM8994: 3182 ret = wm8994_request_irq(codec->control_data, 3183 WM8994_IRQ_MIC1_DET, 3184 wm8994_mic_irq, "Mic 1 detect", 3185 wm8994); 3186 if (ret != 0) 3187 dev_warn(codec->dev, 3188 "Failed to request Mic1 detect IRQ: %d\n", 3189 ret); 3190 3191 ret = wm8994_request_irq(codec->control_data, 3192 WM8994_IRQ_MIC1_SHRT, 3193 wm8994_mic_irq, "Mic 1 short", 3194 wm8994); 3195 if (ret != 0) 3196 dev_warn(codec->dev, 3197 "Failed to request Mic1 short IRQ: %d\n", 3198 ret); 3199 3200 ret = wm8994_request_irq(codec->control_data, 3201 WM8994_IRQ_MIC2_DET, 3202 wm8994_mic_irq, "Mic 2 detect", 3203 wm8994); 3204 if (ret != 0) 3205 dev_warn(codec->dev, 3206 "Failed to request Mic2 detect IRQ: %d\n", 3207 ret); 3208 3209 ret = wm8994_request_irq(codec->control_data, 3210 WM8994_IRQ_MIC2_SHRT, 3211 wm8994_mic_irq, "Mic 2 short", 3212 wm8994); 3213 if (ret != 0) 3214 dev_warn(codec->dev, 3215 "Failed to request Mic2 short IRQ: %d\n", 3216 ret); 3217 break; 3218 3219 case WM8958: 3220 ret = wm8994_request_irq(codec->control_data, 3221 WM8994_IRQ_MIC1_DET, 3222 wm8958_mic_irq, "Mic detect", 3223 wm8994); 3224 if (ret != 0) 3225 dev_warn(codec->dev, 3226 "Failed to request Mic detect IRQ: %d\n", 3227 ret); 3228 break; 3229 } 3230 3231 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3232 * configured on init - if a system wants to do this dynamically 3233 * at runtime we can deal with that then. 3234 */ 3235 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); 3236 if (ret < 0) { 3237 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 3238 goto err_irq; 3239 } 3240 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3241 wm8994->lrclk_shared[0] = 1; 3242 wm8994_dai[0].symmetric_rates = 1; 3243 } else { 3244 wm8994->lrclk_shared[0] = 0; 3245 } 3246 3247 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); 3248 if (ret < 0) { 3249 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 3250 goto err_irq; 3251 } 3252 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3253 wm8994->lrclk_shared[1] = 1; 3254 wm8994_dai[1].symmetric_rates = 1; 3255 } else { 3256 wm8994->lrclk_shared[1] = 0; 3257 } 3258 3259 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3260 3261 /* Latch volume updates (right only; we always do left then right). */ 3262 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, 3263 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3264 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, 3265 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3266 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, 3267 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3268 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, 3269 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3270 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, 3271 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3272 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, 3273 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3274 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, 3275 WM8994_DAC1_VU, WM8994_DAC1_VU); 3276 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, 3277 WM8994_DAC2_VU, WM8994_DAC2_VU); 3278 3279 /* Set the low bit of the 3D stereo depth so TLV matches */ 3280 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 3281 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 3282 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 3283 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 3284 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 3285 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 3286 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 3287 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 3288 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 3289 3290 /* Unconditionally enable AIF1 ADC TDM mode; it only affects 3291 * behaviour on idle TDM clock cycles. */ 3292 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 3293 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 3294 3295 wm8994_update_class_w(codec); 3296 3297 wm8994_handle_pdata(wm8994); 3298 3299 wm_hubs_add_analogue_controls(codec); 3300 snd_soc_add_controls(codec, wm8994_snd_controls, 3301 ARRAY_SIZE(wm8994_snd_controls)); 3302 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 3303 ARRAY_SIZE(wm8994_dapm_widgets)); 3304 3305 switch (control->type) { 3306 case WM8994: 3307 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 3308 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 3309 if (wm8994->revision < 4) { 3310 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 3311 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 3312 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 3313 ARRAY_SIZE(wm8994_adc_revd_widgets)); 3314 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 3315 ARRAY_SIZE(wm8994_dac_revd_widgets)); 3316 } else { 3317 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 3318 ARRAY_SIZE(wm8994_lateclk_widgets)); 3319 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 3320 ARRAY_SIZE(wm8994_adc_widgets)); 3321 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 3322 ARRAY_SIZE(wm8994_dac_widgets)); 3323 } 3324 break; 3325 case WM8958: 3326 snd_soc_add_controls(codec, wm8958_snd_controls, 3327 ARRAY_SIZE(wm8958_snd_controls)); 3328 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 3329 ARRAY_SIZE(wm8994_lateclk_widgets)); 3330 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 3331 ARRAY_SIZE(wm8994_adc_widgets)); 3332 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 3333 ARRAY_SIZE(wm8994_dac_widgets)); 3334 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 3335 ARRAY_SIZE(wm8958_dapm_widgets)); 3336 break; 3337 } 3338 3339 3340 wm_hubs_add_analogue_routes(codec, 0, 0); 3341 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 3342 3343 switch (control->type) { 3344 case WM8994: 3345 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 3346 ARRAY_SIZE(wm8994_intercon)); 3347 3348 if (wm8994->revision < 4) { 3349 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 3350 ARRAY_SIZE(wm8994_revd_intercon)); 3351 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 3352 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 3353 } else { 3354 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 3355 ARRAY_SIZE(wm8994_lateclk_intercon)); 3356 } 3357 break; 3358 case WM8958: 3359 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 3360 ARRAY_SIZE(wm8994_lateclk_intercon)); 3361 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 3362 ARRAY_SIZE(wm8958_intercon)); 3363 break; 3364 } 3365 3366 return 0; 3367 3368 err_irq: 3369 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3370 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3371 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3372 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3373 err: 3374 kfree(wm8994); 3375 return ret; 3376 } 3377 3378 static int wm8994_codec_remove(struct snd_soc_codec *codec) 3379 { 3380 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3381 struct wm8994 *control = codec->control_data; 3382 3383 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3384 3385 pm_runtime_disable(codec->dev); 3386 3387 switch (control->type) { 3388 case WM8994: 3389 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3390 wm8994); 3391 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 3392 wm8994); 3393 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 3394 wm8994); 3395 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3396 wm8994); 3397 break; 3398 3399 case WM8958: 3400 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3401 wm8994); 3402 break; 3403 } 3404 kfree(wm8994->retune_mobile_texts); 3405 kfree(wm8994->drc_texts); 3406 kfree(wm8994); 3407 3408 return 0; 3409 } 3410 3411 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 3412 .probe = wm8994_codec_probe, 3413 .remove = wm8994_codec_remove, 3414 .suspend = wm8994_suspend, 3415 .resume = wm8994_resume, 3416 .read = wm8994_read, 3417 .write = wm8994_write, 3418 .readable_register = wm8994_readable, 3419 .volatile_register = wm8994_volatile, 3420 .set_bias_level = wm8994_set_bias_level, 3421 3422 .reg_cache_size = WM8994_CACHE_SIZE, 3423 .reg_cache_default = wm8994_reg_defaults, 3424 .reg_word_size = 2, 3425 .compress_type = SND_SOC_RBTREE_COMPRESSION, 3426 }; 3427 3428 static int __devinit wm8994_probe(struct platform_device *pdev) 3429 { 3430 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 3431 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3432 } 3433 3434 static int __devexit wm8994_remove(struct platform_device *pdev) 3435 { 3436 snd_soc_unregister_codec(&pdev->dev); 3437 return 0; 3438 } 3439 3440 static struct platform_driver wm8994_codec_driver = { 3441 .driver = { 3442 .name = "wm8994-codec", 3443 .owner = THIS_MODULE, 3444 }, 3445 .probe = wm8994_probe, 3446 .remove = __devexit_p(wm8994_remove), 3447 }; 3448 3449 static __init int wm8994_init(void) 3450 { 3451 return platform_driver_register(&wm8994_codec_driver); 3452 } 3453 module_init(wm8994_init); 3454 3455 static __exit void wm8994_exit(void) 3456 { 3457 platform_driver_unregister(&wm8994_codec_driver); 3458 } 3459 module_exit(wm8994_exit); 3460 3461 3462 MODULE_DESCRIPTION("ASoC WM8994 driver"); 3463 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3464 MODULE_LICENSE("GPL"); 3465 MODULE_ALIAS("platform:wm8994-codec"); 3466