1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <trace/events/asoc.h> 32 33 #include <linux/mfd/wm8994/core.h> 34 #include <linux/mfd/wm8994/registers.h> 35 #include <linux/mfd/wm8994/pdata.h> 36 #include <linux/mfd/wm8994/gpio.h> 37 38 #include "wm8994.h" 39 #include "wm_hubs.h" 40 41 struct fll_config { 42 int src; 43 int in; 44 int out; 45 }; 46 47 #define WM8994_NUM_DRC 3 48 #define WM8994_NUM_EQ 3 49 50 static int wm8994_drc_base[] = { 51 WM8994_AIF1_DRC1_1, 52 WM8994_AIF1_DRC2_1, 53 WM8994_AIF2_DRC_1, 54 }; 55 56 static int wm8994_retune_mobile_base[] = { 57 WM8994_AIF1_DAC1_EQ_GAINS_1, 58 WM8994_AIF1_DAC2_EQ_GAINS_1, 59 WM8994_AIF2_EQ_GAINS_1, 60 }; 61 62 struct wm8994_micdet { 63 struct snd_soc_jack *jack; 64 int det; 65 int shrt; 66 }; 67 68 /* codec private data */ 69 struct wm8994_priv { 70 struct wm_hubs_data hubs; 71 enum snd_soc_control_type control_type; 72 void *control_data; 73 struct snd_soc_codec *codec; 74 int sysclk[2]; 75 int sysclk_rate[2]; 76 int mclk[2]; 77 int aifclk[2]; 78 struct fll_config fll[2], fll_suspend[2]; 79 80 int dac_rates[2]; 81 int lrclk_shared[2]; 82 83 int mbc_ena[3]; 84 85 /* Platform dependant DRC configuration */ 86 const char **drc_texts; 87 int drc_cfg[WM8994_NUM_DRC]; 88 struct soc_enum drc_enum; 89 90 /* Platform dependant ReTune mobile configuration */ 91 int num_retune_mobile_texts; 92 const char **retune_mobile_texts; 93 int retune_mobile_cfg[WM8994_NUM_EQ]; 94 struct soc_enum retune_mobile_enum; 95 96 /* Platform dependant MBC configuration */ 97 int mbc_cfg; 98 const char **mbc_texts; 99 struct soc_enum mbc_enum; 100 101 struct wm8994_micdet micdet[2]; 102 103 wm8958_micdet_cb jack_cb; 104 void *jack_cb_data; 105 bool jack_is_mic; 106 bool jack_is_video; 107 108 int revision; 109 struct wm8994_pdata *pdata; 110 }; 111 112 static int wm8994_readable(unsigned int reg) 113 { 114 switch (reg) { 115 case WM8994_GPIO_1: 116 case WM8994_GPIO_2: 117 case WM8994_GPIO_3: 118 case WM8994_GPIO_4: 119 case WM8994_GPIO_5: 120 case WM8994_GPIO_6: 121 case WM8994_GPIO_7: 122 case WM8994_GPIO_8: 123 case WM8994_GPIO_9: 124 case WM8994_GPIO_10: 125 case WM8994_GPIO_11: 126 case WM8994_INTERRUPT_STATUS_1: 127 case WM8994_INTERRUPT_STATUS_2: 128 case WM8994_INTERRUPT_RAW_STATUS_2: 129 return 1; 130 default: 131 break; 132 } 133 134 if (reg >= WM8994_CACHE_SIZE) 135 return 0; 136 return wm8994_access_masks[reg].readable != 0; 137 } 138 139 static int wm8994_volatile(unsigned int reg) 140 { 141 if (reg >= WM8994_CACHE_SIZE) 142 return 1; 143 144 switch (reg) { 145 case WM8994_SOFTWARE_RESET: 146 case WM8994_CHIP_REVISION: 147 case WM8994_DC_SERVO_1: 148 case WM8994_DC_SERVO_READBACK: 149 case WM8994_RATE_STATUS: 150 case WM8994_LDO_1: 151 case WM8994_LDO_2: 152 case WM8958_DSP2_EXECCONTROL: 153 case WM8958_MIC_DETECT_3: 154 return 1; 155 default: 156 return 0; 157 } 158 } 159 160 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 161 unsigned int value) 162 { 163 int ret; 164 165 BUG_ON(reg > WM8994_MAX_REGISTER); 166 167 if (!wm8994_volatile(reg)) { 168 ret = snd_soc_cache_write(codec, reg, value); 169 if (ret != 0) 170 dev_err(codec->dev, "Cache write to %x failed: %d\n", 171 reg, ret); 172 } 173 174 return wm8994_reg_write(codec->control_data, reg, value); 175 } 176 177 static unsigned int wm8994_read(struct snd_soc_codec *codec, 178 unsigned int reg) 179 { 180 unsigned int val; 181 int ret; 182 183 BUG_ON(reg > WM8994_MAX_REGISTER); 184 185 if (!wm8994_volatile(reg) && wm8994_readable(reg) && 186 reg < codec->driver->reg_cache_size) { 187 ret = snd_soc_cache_read(codec, reg, &val); 188 if (ret >= 0) 189 return val; 190 else 191 dev_err(codec->dev, "Cache read from %x failed: %d\n", 192 reg, ret); 193 } 194 195 return wm8994_reg_read(codec->control_data, reg); 196 } 197 198 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 199 { 200 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 201 int rate; 202 int reg1 = 0; 203 int offset; 204 205 if (aif) 206 offset = 4; 207 else 208 offset = 0; 209 210 switch (wm8994->sysclk[aif]) { 211 case WM8994_SYSCLK_MCLK1: 212 rate = wm8994->mclk[0]; 213 break; 214 215 case WM8994_SYSCLK_MCLK2: 216 reg1 |= 0x8; 217 rate = wm8994->mclk[1]; 218 break; 219 220 case WM8994_SYSCLK_FLL1: 221 reg1 |= 0x10; 222 rate = wm8994->fll[0].out; 223 break; 224 225 case WM8994_SYSCLK_FLL2: 226 reg1 |= 0x18; 227 rate = wm8994->fll[1].out; 228 break; 229 230 default: 231 return -EINVAL; 232 } 233 234 if (rate >= 13500000) { 235 rate /= 2; 236 reg1 |= WM8994_AIF1CLK_DIV; 237 238 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 239 aif + 1, rate); 240 } 241 242 if (rate && rate < 3000000) 243 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n", 244 aif + 1, rate); 245 246 wm8994->aifclk[aif] = rate; 247 248 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 249 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 250 reg1); 251 252 return 0; 253 } 254 255 static int configure_clock(struct snd_soc_codec *codec) 256 { 257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 258 int old, new; 259 260 /* Bring up the AIF clocks first */ 261 configure_aif_clock(codec, 0); 262 configure_aif_clock(codec, 1); 263 264 /* Then switch CLK_SYS over to the higher of them; a change 265 * can only happen as a result of a clocking change which can 266 * only be made outside of DAPM so we can safely redo the 267 * clocking. 268 */ 269 270 /* If they're equal it doesn't matter which is used */ 271 if (wm8994->aifclk[0] == wm8994->aifclk[1]) 272 return 0; 273 274 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 275 new = WM8994_SYSCLK_SRC; 276 else 277 new = 0; 278 279 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; 280 281 /* If there's no change then we're done. */ 282 if (old == new) 283 return 0; 284 285 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 286 287 snd_soc_dapm_sync(&codec->dapm); 288 289 return 0; 290 } 291 292 static int check_clk_sys(struct snd_soc_dapm_widget *source, 293 struct snd_soc_dapm_widget *sink) 294 { 295 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 296 const char *clk; 297 298 /* Check what we're currently using for CLK_SYS */ 299 if (reg & WM8994_SYSCLK_SRC) 300 clk = "AIF2CLK"; 301 else 302 clk = "AIF1CLK"; 303 304 return strcmp(source->name, clk) == 0; 305 } 306 307 static const char *sidetone_hpf_text[] = { 308 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 309 }; 310 311 static const struct soc_enum sidetone_hpf = 312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 313 314 static const char *adc_hpf_text[] = { 315 "HiFi", "Voice 1", "Voice 2", "Voice 3" 316 }; 317 318 static const struct soc_enum aif1adc1_hpf = 319 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 320 321 static const struct soc_enum aif1adc2_hpf = 322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 323 324 static const struct soc_enum aif2adc_hpf = 325 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 326 327 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 328 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 329 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 330 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 331 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 332 333 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 334 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 335 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 336 .put = wm8994_put_drc_sw, \ 337 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 338 339 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_value *ucontrol) 341 { 342 struct soc_mixer_control *mc = 343 (struct soc_mixer_control *)kcontrol->private_value; 344 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 345 int mask, ret; 346 347 /* Can't enable both ADC and DAC paths simultaneously */ 348 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 349 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 350 WM8994_AIF1ADC1R_DRC_ENA_MASK; 351 else 352 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 353 354 ret = snd_soc_read(codec, mc->reg); 355 if (ret < 0) 356 return ret; 357 if (ret & mask) 358 return -EINVAL; 359 360 return snd_soc_put_volsw(kcontrol, ucontrol); 361 } 362 363 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 364 { 365 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 366 struct wm8994_pdata *pdata = wm8994->pdata; 367 int base = wm8994_drc_base[drc]; 368 int cfg = wm8994->drc_cfg[drc]; 369 int save, i; 370 371 /* Save any enables; the configuration should clear them. */ 372 save = snd_soc_read(codec, base); 373 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 374 WM8994_AIF1ADC1R_DRC_ENA; 375 376 for (i = 0; i < WM8994_DRC_REGS; i++) 377 snd_soc_update_bits(codec, base + i, 0xffff, 378 pdata->drc_cfgs[cfg].regs[i]); 379 380 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 381 WM8994_AIF1ADC1L_DRC_ENA | 382 WM8994_AIF1ADC1R_DRC_ENA, save); 383 } 384 385 /* Icky as hell but saves code duplication */ 386 static int wm8994_get_drc(const char *name) 387 { 388 if (strcmp(name, "AIF1DRC1 Mode") == 0) 389 return 0; 390 if (strcmp(name, "AIF1DRC2 Mode") == 0) 391 return 1; 392 if (strcmp(name, "AIF2DRC Mode") == 0) 393 return 2; 394 return -EINVAL; 395 } 396 397 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 398 struct snd_ctl_elem_value *ucontrol) 399 { 400 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 401 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 402 struct wm8994_pdata *pdata = wm8994->pdata; 403 int drc = wm8994_get_drc(kcontrol->id.name); 404 int value = ucontrol->value.integer.value[0]; 405 406 if (drc < 0) 407 return drc; 408 409 if (value >= pdata->num_drc_cfgs) 410 return -EINVAL; 411 412 wm8994->drc_cfg[drc] = value; 413 414 wm8994_set_drc(codec, drc); 415 416 return 0; 417 } 418 419 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 420 struct snd_ctl_elem_value *ucontrol) 421 { 422 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 423 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 424 int drc = wm8994_get_drc(kcontrol->id.name); 425 426 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 427 428 return 0; 429 } 430 431 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 432 { 433 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 434 struct wm8994_pdata *pdata = wm8994->pdata; 435 int base = wm8994_retune_mobile_base[block]; 436 int iface, best, best_val, save, i, cfg; 437 438 if (!pdata || !wm8994->num_retune_mobile_texts) 439 return; 440 441 switch (block) { 442 case 0: 443 case 1: 444 iface = 0; 445 break; 446 case 2: 447 iface = 1; 448 break; 449 default: 450 return; 451 } 452 453 /* Find the version of the currently selected configuration 454 * with the nearest sample rate. */ 455 cfg = wm8994->retune_mobile_cfg[block]; 456 best = 0; 457 best_val = INT_MAX; 458 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 459 if (strcmp(pdata->retune_mobile_cfgs[i].name, 460 wm8994->retune_mobile_texts[cfg]) == 0 && 461 abs(pdata->retune_mobile_cfgs[i].rate 462 - wm8994->dac_rates[iface]) < best_val) { 463 best = i; 464 best_val = abs(pdata->retune_mobile_cfgs[i].rate 465 - wm8994->dac_rates[iface]); 466 } 467 } 468 469 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 470 block, 471 pdata->retune_mobile_cfgs[best].name, 472 pdata->retune_mobile_cfgs[best].rate, 473 wm8994->dac_rates[iface]); 474 475 /* The EQ will be disabled while reconfiguring it, remember the 476 * current configuration. 477 */ 478 save = snd_soc_read(codec, base); 479 save &= WM8994_AIF1DAC1_EQ_ENA; 480 481 for (i = 0; i < WM8994_EQ_REGS; i++) 482 snd_soc_update_bits(codec, base + i, 0xffff, 483 pdata->retune_mobile_cfgs[best].regs[i]); 484 485 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 486 } 487 488 /* Icky as hell but saves code duplication */ 489 static int wm8994_get_retune_mobile_block(const char *name) 490 { 491 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 492 return 0; 493 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 494 return 1; 495 if (strcmp(name, "AIF2 EQ Mode") == 0) 496 return 2; 497 return -EINVAL; 498 } 499 500 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 501 struct snd_ctl_elem_value *ucontrol) 502 { 503 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 505 struct wm8994_pdata *pdata = wm8994->pdata; 506 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 507 int value = ucontrol->value.integer.value[0]; 508 509 if (block < 0) 510 return block; 511 512 if (value >= pdata->num_retune_mobile_cfgs) 513 return -EINVAL; 514 515 wm8994->retune_mobile_cfg[block] = value; 516 517 wm8994_set_retune_mobile(codec, block); 518 519 return 0; 520 } 521 522 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 523 struct snd_ctl_elem_value *ucontrol) 524 { 525 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 526 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec); 527 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 528 529 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 530 531 return 0; 532 } 533 534 static const char *aif_chan_src_text[] = { 535 "Left", "Right" 536 }; 537 538 static const struct soc_enum aif1adcl_src = 539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 540 541 static const struct soc_enum aif1adcr_src = 542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 543 544 static const struct soc_enum aif2adcl_src = 545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 546 547 static const struct soc_enum aif2adcr_src = 548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 549 550 static const struct soc_enum aif1dacl_src = 551 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 552 553 static const struct soc_enum aif1dacr_src = 554 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 555 556 static const struct soc_enum aif2dacl_src = 557 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 558 559 static const struct soc_enum aif2dacr_src = 560 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 561 562 static const char *osr_text[] = { 563 "Low Power", "High Performance", 564 }; 565 566 static const struct soc_enum dac_osr = 567 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 568 569 static const struct soc_enum adc_osr = 570 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 571 572 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start) 573 { 574 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 575 struct wm8994_pdata *pdata = wm8994->pdata; 576 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5); 577 int ena, reg, aif, i; 578 579 switch (mbc) { 580 case 0: 581 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); 582 aif = 0; 583 break; 584 case 1: 585 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 586 aif = 0; 587 break; 588 case 2: 589 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); 590 aif = 1; 591 break; 592 default: 593 BUG(); 594 return; 595 } 596 597 /* We can only enable the MBC if the AIF is enabled and we 598 * want it to be enabled. */ 599 ena = pwr_reg && wm8994->mbc_ena[mbc]; 600 601 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM); 602 603 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n", 604 mbc, start, pwr_reg, reg); 605 606 if (start && ena) { 607 /* If the DSP is already running then noop */ 608 if (reg & WM8958_DSP2_ENA) 609 return; 610 611 /* Switch the clock over to the appropriate AIF */ 612 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 613 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA, 614 aif << WM8958_DSP2CLK_SRC_SHIFT | 615 WM8958_DSP2CLK_ENA); 616 617 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, 618 WM8958_DSP2_ENA, WM8958_DSP2_ENA); 619 620 /* If we've got user supplied MBC settings use them */ 621 if (pdata && pdata->num_mbc_cfgs) { 622 struct wm8958_mbc_cfg *cfg 623 = &pdata->mbc_cfgs[wm8994->mbc_cfg]; 624 625 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++) 626 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1, 627 cfg->coeff_regs[i]); 628 629 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++) 630 snd_soc_write(codec, 631 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1, 632 cfg->cutoff_regs[i]); 633 } 634 635 /* Run the DSP */ 636 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL, 637 WM8958_DSP2_RUNR); 638 639 /* And we're off! */ 640 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, 641 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK, 642 mbc << WM8958_MBC_SEL_SHIFT | 643 WM8958_MBC_ENA); 644 } else { 645 /* If the DSP is already stopped then noop */ 646 if (!(reg & WM8958_DSP2_ENA)) 647 return; 648 649 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG, 650 WM8958_MBC_ENA, 0); 651 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM, 652 WM8958_DSP2_ENA, 0); 653 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 654 WM8958_DSP2CLK_ENA, 0); 655 } 656 } 657 658 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w, 659 struct snd_kcontrol *kcontrol, int event) 660 { 661 struct snd_soc_codec *codec = w->codec; 662 int mbc; 663 664 switch (w->shift) { 665 case 13: 666 case 12: 667 mbc = 2; 668 break; 669 case 11: 670 case 10: 671 mbc = 1; 672 break; 673 case 9: 674 case 8: 675 mbc = 0; 676 break; 677 default: 678 BUG(); 679 return -EINVAL; 680 } 681 682 switch (event) { 683 case SND_SOC_DAPM_POST_PMU: 684 wm8958_mbc_apply(codec, mbc, 1); 685 break; 686 case SND_SOC_DAPM_POST_PMD: 687 wm8958_mbc_apply(codec, mbc, 0); 688 break; 689 } 690 691 return 0; 692 } 693 694 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol, 695 struct snd_ctl_elem_value *ucontrol) 696 { 697 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 698 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 699 struct wm8994_pdata *pdata = wm8994->pdata; 700 int value = ucontrol->value.integer.value[0]; 701 int reg; 702 703 /* Don't allow on the fly reconfiguration */ 704 reg = snd_soc_read(codec, WM8994_CLOCKING_1); 705 if (reg < 0 || reg & WM8958_DSP2CLK_ENA) 706 return -EBUSY; 707 708 if (value >= pdata->num_mbc_cfgs) 709 return -EINVAL; 710 711 wm8994->mbc_cfg = value; 712 713 return 0; 714 } 715 716 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol, 717 struct snd_ctl_elem_value *ucontrol) 718 { 719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 720 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 721 722 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg; 723 724 return 0; 725 } 726 727 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol, 728 struct snd_ctl_elem_info *uinfo) 729 { 730 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 731 uinfo->count = 1; 732 uinfo->value.integer.min = 0; 733 uinfo->value.integer.max = 1; 734 return 0; 735 } 736 737 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol, 738 struct snd_ctl_elem_value *ucontrol) 739 { 740 int mbc = kcontrol->private_value; 741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 742 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 743 744 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc]; 745 746 return 0; 747 } 748 749 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol, 750 struct snd_ctl_elem_value *ucontrol) 751 { 752 int mbc = kcontrol->private_value; 753 int i; 754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 756 757 if (ucontrol->value.integer.value[0] > 1) 758 return -EINVAL; 759 760 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) { 761 if (mbc != i && wm8994->mbc_ena[i]) { 762 dev_dbg(codec->dev, "MBC %d active already\n", mbc); 763 return -EBUSY; 764 } 765 } 766 767 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0]; 768 769 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]); 770 771 return 0; 772 } 773 774 #define WM8958_MBC_SWITCH(xname, xval) {\ 775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 776 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 777 .info = wm8958_mbc_info, \ 778 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \ 779 .private_value = xval } 780 781 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 782 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 783 WM8994_AIF1_ADC1_RIGHT_VOLUME, 784 1, 119, 0, digital_tlv), 785 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 786 WM8994_AIF1_ADC2_RIGHT_VOLUME, 787 1, 119, 0, digital_tlv), 788 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 789 WM8994_AIF2_ADC_RIGHT_VOLUME, 790 1, 119, 0, digital_tlv), 791 792 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 793 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 794 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 795 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 796 797 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 798 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 799 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 800 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 801 802 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 803 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 804 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 805 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 806 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 807 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 808 809 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 810 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 811 812 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 813 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 814 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 815 816 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 817 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 818 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 819 820 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 821 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 822 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 823 824 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 825 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 826 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 827 828 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 829 5, 12, 0, st_tlv), 830 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 831 0, 12, 0, st_tlv), 832 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 833 5, 12, 0, st_tlv), 834 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 835 0, 12, 0, st_tlv), 836 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 837 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 838 839 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 840 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 841 842 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 843 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 844 845 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 846 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 847 848 SOC_ENUM("ADC OSR", adc_osr), 849 SOC_ENUM("DAC OSR", dac_osr), 850 851 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 852 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 853 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 854 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 855 856 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 857 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 858 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 859 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 860 861 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 862 6, 1, 1, wm_hubs_spkmix_tlv), 863 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 864 2, 1, 1, wm_hubs_spkmix_tlv), 865 866 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 867 6, 1, 1, wm_hubs_spkmix_tlv), 868 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 869 2, 1, 1, wm_hubs_spkmix_tlv), 870 871 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 872 10, 15, 0, wm8994_3d_tlv), 873 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 874 8, 1, 0), 875 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 876 10, 15, 0, wm8994_3d_tlv), 877 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 878 8, 1, 0), 879 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 880 10, 15, 0, wm8994_3d_tlv), 881 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 882 8, 1, 0), 883 }; 884 885 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 886 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 887 eq_tlv), 888 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 889 eq_tlv), 890 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 891 eq_tlv), 892 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 893 eq_tlv), 894 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 895 eq_tlv), 896 897 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 898 eq_tlv), 899 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 900 eq_tlv), 901 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 902 eq_tlv), 903 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 904 eq_tlv), 905 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 906 eq_tlv), 907 908 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 909 eq_tlv), 910 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 911 eq_tlv), 912 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 913 eq_tlv), 914 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 915 eq_tlv), 916 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 917 eq_tlv), 918 }; 919 920 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 921 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 922 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0), 923 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1), 924 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2), 925 }; 926 927 static int clk_sys_event(struct snd_soc_dapm_widget *w, 928 struct snd_kcontrol *kcontrol, int event) 929 { 930 struct snd_soc_codec *codec = w->codec; 931 932 switch (event) { 933 case SND_SOC_DAPM_PRE_PMU: 934 return configure_clock(codec); 935 936 case SND_SOC_DAPM_POST_PMD: 937 configure_clock(codec); 938 break; 939 } 940 941 return 0; 942 } 943 944 static void wm8994_update_class_w(struct snd_soc_codec *codec) 945 { 946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 947 int enable = 1; 948 int source = 0; /* GCC flow analysis can't track enable */ 949 int reg, reg_r; 950 951 /* Only support direct DAC->headphone paths */ 952 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); 953 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { 954 dev_vdbg(codec->dev, "HPL connected to output mixer\n"); 955 enable = 0; 956 } 957 958 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); 959 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { 960 dev_vdbg(codec->dev, "HPR connected to output mixer\n"); 961 enable = 0; 962 } 963 964 /* We also need the same setting for L/R and only one path */ 965 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 966 switch (reg) { 967 case WM8994_AIF2DACL_TO_DAC1L: 968 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 969 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 970 break; 971 case WM8994_AIF1DAC2L_TO_DAC1L: 972 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 973 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 974 break; 975 case WM8994_AIF1DAC1L_TO_DAC1L: 976 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 977 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 978 break; 979 default: 980 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 981 enable = 0; 982 break; 983 } 984 985 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 986 if (reg_r != reg) { 987 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 988 enable = 0; 989 } 990 991 if (enable) { 992 dev_dbg(codec->dev, "Class W enabled\n"); 993 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 994 WM8994_CP_DYN_PWR | 995 WM8994_CP_DYN_SRC_SEL_MASK, 996 source | WM8994_CP_DYN_PWR); 997 wm8994->hubs.class_w = true; 998 999 } else { 1000 dev_dbg(codec->dev, "Class W disabled\n"); 1001 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1002 WM8994_CP_DYN_PWR, 0); 1003 wm8994->hubs.class_w = false; 1004 } 1005 } 1006 1007 static const char *hp_mux_text[] = { 1008 "Mixer", 1009 "DAC", 1010 }; 1011 1012 #define WM8994_HP_ENUM(xname, xenum) \ 1013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1014 .info = snd_soc_info_enum_double, \ 1015 .get = snd_soc_dapm_get_enum_double, \ 1016 .put = wm8994_put_hp_enum, \ 1017 .private_value = (unsigned long)&xenum } 1018 1019 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, 1020 struct snd_ctl_elem_value *ucontrol) 1021 { 1022 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 1023 struct snd_soc_codec *codec = w->codec; 1024 int ret; 1025 1026 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1027 1028 wm8994_update_class_w(codec); 1029 1030 return ret; 1031 } 1032 1033 static const struct soc_enum hpl_enum = 1034 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); 1035 1036 static const struct snd_kcontrol_new hpl_mux = 1037 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); 1038 1039 static const struct soc_enum hpr_enum = 1040 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); 1041 1042 static const struct snd_kcontrol_new hpr_mux = 1043 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); 1044 1045 static const char *adc_mux_text[] = { 1046 "ADC", 1047 "DMIC", 1048 }; 1049 1050 static const struct soc_enum adc_enum = 1051 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 1052 1053 static const struct snd_kcontrol_new adcl_mux = 1054 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1055 1056 static const struct snd_kcontrol_new adcr_mux = 1057 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1058 1059 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1060 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1061 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1062 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1063 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1064 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1065 }; 1066 1067 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1068 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1069 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1070 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1071 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1072 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1073 }; 1074 1075 /* Debugging; dump chip status after DAPM transitions */ 1076 static int post_ev(struct snd_soc_dapm_widget *w, 1077 struct snd_kcontrol *kcontrol, int event) 1078 { 1079 struct snd_soc_codec *codec = w->codec; 1080 dev_dbg(codec->dev, "SRC status: %x\n", 1081 snd_soc_read(codec, 1082 WM8994_RATE_STATUS)); 1083 return 0; 1084 } 1085 1086 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1087 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1088 1, 1, 0), 1089 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1090 0, 1, 0), 1091 }; 1092 1093 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1094 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1095 1, 1, 0), 1096 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1097 0, 1, 0), 1098 }; 1099 1100 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1101 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1102 1, 1, 0), 1103 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1104 0, 1, 0), 1105 }; 1106 1107 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1108 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1109 1, 1, 0), 1110 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1111 0, 1, 0), 1112 }; 1113 1114 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1115 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1116 5, 1, 0), 1117 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1118 4, 1, 0), 1119 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1120 2, 1, 0), 1121 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1122 1, 1, 0), 1123 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1124 0, 1, 0), 1125 }; 1126 1127 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1128 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1129 5, 1, 0), 1130 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1131 4, 1, 0), 1132 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1133 2, 1, 0), 1134 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1135 1, 1, 0), 1136 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1137 0, 1, 0), 1138 }; 1139 1140 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1141 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1142 .info = snd_soc_info_volsw, \ 1143 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 1144 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 1145 1146 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1147 struct snd_ctl_elem_value *ucontrol) 1148 { 1149 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 1150 struct snd_soc_codec *codec = w->codec; 1151 int ret; 1152 1153 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1154 1155 wm8994_update_class_w(codec); 1156 1157 return ret; 1158 } 1159 1160 static const struct snd_kcontrol_new dac1l_mix[] = { 1161 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1162 5, 1, 0), 1163 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1164 4, 1, 0), 1165 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1166 2, 1, 0), 1167 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1168 1, 1, 0), 1169 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1170 0, 1, 0), 1171 }; 1172 1173 static const struct snd_kcontrol_new dac1r_mix[] = { 1174 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1175 5, 1, 0), 1176 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1177 4, 1, 0), 1178 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1179 2, 1, 0), 1180 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1181 1, 1, 0), 1182 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1183 0, 1, 0), 1184 }; 1185 1186 static const char *sidetone_text[] = { 1187 "ADC/DMIC1", "DMIC2", 1188 }; 1189 1190 static const struct soc_enum sidetone1_enum = 1191 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1192 1193 static const struct snd_kcontrol_new sidetone1_mux = 1194 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1195 1196 static const struct soc_enum sidetone2_enum = 1197 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1198 1199 static const struct snd_kcontrol_new sidetone2_mux = 1200 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1201 1202 static const char *aif1dac_text[] = { 1203 "AIF1DACDAT", "AIF3DACDAT", 1204 }; 1205 1206 static const struct soc_enum aif1dac_enum = 1207 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1208 1209 static const struct snd_kcontrol_new aif1dac_mux = 1210 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1211 1212 static const char *aif2dac_text[] = { 1213 "AIF2DACDAT", "AIF3DACDAT", 1214 }; 1215 1216 static const struct soc_enum aif2dac_enum = 1217 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1218 1219 static const struct snd_kcontrol_new aif2dac_mux = 1220 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1221 1222 static const char *aif2adc_text[] = { 1223 "AIF2ADCDAT", "AIF3DACDAT", 1224 }; 1225 1226 static const struct soc_enum aif2adc_enum = 1227 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1228 1229 static const struct snd_kcontrol_new aif2adc_mux = 1230 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1231 1232 static const char *aif3adc_text[] = { 1233 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1234 }; 1235 1236 static const struct soc_enum wm8994_aif3adc_enum = 1237 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1238 1239 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1240 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1241 1242 static const struct soc_enum wm8958_aif3adc_enum = 1243 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1244 1245 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1246 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1247 1248 static const char *mono_pcm_out_text[] = { 1249 "None", "AIF2ADCL", "AIF2ADCR", 1250 }; 1251 1252 static const struct soc_enum mono_pcm_out_enum = 1253 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1254 1255 static const struct snd_kcontrol_new mono_pcm_out_mux = 1256 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1257 1258 static const char *aif2dac_src_text[] = { 1259 "AIF2", "AIF3", 1260 }; 1261 1262 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1263 static const struct soc_enum aif2dacl_src_enum = 1264 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1265 1266 static const struct snd_kcontrol_new aif2dacl_src_mux = 1267 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1268 1269 static const struct soc_enum aif2dacr_src_enum = 1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1271 1272 static const struct snd_kcontrol_new aif2dacr_src_mux = 1273 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1274 1275 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1276 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1277 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1278 SND_SOC_DAPM_INPUT("Clock"), 1279 1280 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1281 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1282 1283 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), 1284 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 1285 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 1286 1287 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 1288 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), 1289 1290 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 1291 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1292 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 1293 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1294 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1295 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev, 1296 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1297 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1298 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev, 1299 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1300 1301 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 1302 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1303 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 1304 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1305 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1306 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev, 1307 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1308 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1309 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev, 1310 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1311 1312 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1313 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1314 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1315 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1316 1317 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1318 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1319 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1320 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1321 1322 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1323 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1324 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1325 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1326 1327 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1328 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1329 1330 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1331 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1332 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1333 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1334 1335 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1336 WM8994_POWER_MANAGEMENT_4, 13, 0), 1337 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1338 WM8994_POWER_MANAGEMENT_4, 12, 0), 1339 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1340 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev, 1341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1342 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1343 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev, 1344 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1345 1346 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1347 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1348 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1349 1350 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1351 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1352 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1353 1354 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1355 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1356 1357 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1358 1359 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1360 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1361 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1362 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1363 1364 /* Power is done with the muxes since the ADC power also controls the 1365 * downsampling chain, the chip will automatically manage the analogue 1366 * specific portions. 1367 */ 1368 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1369 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1370 1371 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1372 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1373 1374 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1375 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1376 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1377 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1378 1379 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1380 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1381 1382 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1383 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1384 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1385 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1386 1387 SND_SOC_DAPM_POST("Debug log", post_ev), 1388 }; 1389 1390 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1391 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1392 }; 1393 1394 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1395 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1396 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1397 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1398 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1399 }; 1400 1401 static const struct snd_soc_dapm_route intercon[] = { 1402 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1403 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1404 1405 { "DSP1CLK", NULL, "CLK_SYS" }, 1406 { "DSP2CLK", NULL, "CLK_SYS" }, 1407 { "DSPINTCLK", NULL, "CLK_SYS" }, 1408 1409 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1410 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1411 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1412 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1413 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1414 1415 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1416 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1417 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1418 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1419 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1420 1421 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1422 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1423 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1424 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1425 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1426 1427 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1428 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1429 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1430 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1431 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1432 1433 { "AIF2ADCL", NULL, "AIF2CLK" }, 1434 { "AIF2ADCL", NULL, "DSP2CLK" }, 1435 { "AIF2ADCR", NULL, "AIF2CLK" }, 1436 { "AIF2ADCR", NULL, "DSP2CLK" }, 1437 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1438 1439 { "AIF2DACL", NULL, "AIF2CLK" }, 1440 { "AIF2DACL", NULL, "DSP2CLK" }, 1441 { "AIF2DACR", NULL, "AIF2CLK" }, 1442 { "AIF2DACR", NULL, "DSP2CLK" }, 1443 { "AIF2DACR", NULL, "DSPINTCLK" }, 1444 1445 { "DMIC1L", NULL, "DMIC1DAT" }, 1446 { "DMIC1L", NULL, "CLK_SYS" }, 1447 { "DMIC1R", NULL, "DMIC1DAT" }, 1448 { "DMIC1R", NULL, "CLK_SYS" }, 1449 { "DMIC2L", NULL, "DMIC2DAT" }, 1450 { "DMIC2L", NULL, "CLK_SYS" }, 1451 { "DMIC2R", NULL, "DMIC2DAT" }, 1452 { "DMIC2R", NULL, "CLK_SYS" }, 1453 1454 { "ADCL", NULL, "AIF1CLK" }, 1455 { "ADCL", NULL, "DSP1CLK" }, 1456 { "ADCL", NULL, "DSPINTCLK" }, 1457 1458 { "ADCR", NULL, "AIF1CLK" }, 1459 { "ADCR", NULL, "DSP1CLK" }, 1460 { "ADCR", NULL, "DSPINTCLK" }, 1461 1462 { "ADCL Mux", "ADC", "ADCL" }, 1463 { "ADCL Mux", "DMIC", "DMIC1L" }, 1464 { "ADCR Mux", "ADC", "ADCR" }, 1465 { "ADCR Mux", "DMIC", "DMIC1R" }, 1466 1467 { "DAC1L", NULL, "AIF1CLK" }, 1468 { "DAC1L", NULL, "DSP1CLK" }, 1469 { "DAC1L", NULL, "DSPINTCLK" }, 1470 1471 { "DAC1R", NULL, "AIF1CLK" }, 1472 { "DAC1R", NULL, "DSP1CLK" }, 1473 { "DAC1R", NULL, "DSPINTCLK" }, 1474 1475 { "DAC2L", NULL, "AIF2CLK" }, 1476 { "DAC2L", NULL, "DSP2CLK" }, 1477 { "DAC2L", NULL, "DSPINTCLK" }, 1478 1479 { "DAC2R", NULL, "AIF2DACR" }, 1480 { "DAC2R", NULL, "AIF2CLK" }, 1481 { "DAC2R", NULL, "DSP2CLK" }, 1482 { "DAC2R", NULL, "DSPINTCLK" }, 1483 1484 { "TOCLK", NULL, "CLK_SYS" }, 1485 1486 /* AIF1 outputs */ 1487 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1488 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1489 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1490 1491 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1492 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1493 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1494 1495 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1496 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1497 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1498 1499 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1500 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1501 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1502 1503 /* Pin level routing for AIF3 */ 1504 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1505 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1506 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1507 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1508 1509 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1510 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1511 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1512 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1513 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1514 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1515 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1516 1517 /* DAC1 inputs */ 1518 { "DAC1L", NULL, "DAC1L Mixer" }, 1519 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1520 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1521 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1522 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1523 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1524 1525 { "DAC1R", NULL, "DAC1R Mixer" }, 1526 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1527 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1528 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1529 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1530 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1531 1532 /* DAC2/AIF2 outputs */ 1533 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1534 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1535 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1536 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1537 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1538 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1539 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1540 1541 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1542 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1543 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1544 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1545 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1546 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1547 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1548 1549 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1550 1551 /* AIF3 output */ 1552 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1553 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1554 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1555 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1556 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1557 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1558 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1559 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1560 1561 /* Sidetone */ 1562 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1563 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1564 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1565 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1566 1567 /* Output stages */ 1568 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1569 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1570 1571 { "SPKL", "DAC1 Switch", "DAC1L" }, 1572 { "SPKL", "DAC2 Switch", "DAC2L" }, 1573 1574 { "SPKR", "DAC1 Switch", "DAC1R" }, 1575 { "SPKR", "DAC2 Switch", "DAC2R" }, 1576 1577 { "Left Headphone Mux", "DAC", "DAC1L" }, 1578 { "Right Headphone Mux", "DAC", "DAC1R" }, 1579 }; 1580 1581 static const struct snd_soc_dapm_route wm8994_intercon[] = { 1582 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 1583 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 1584 }; 1585 1586 static const struct snd_soc_dapm_route wm8958_intercon[] = { 1587 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 1588 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 1589 1590 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 1591 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 1592 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1593 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1594 1595 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 1596 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 1597 1598 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 1599 }; 1600 1601 /* The size in bits of the FLL divide multiplied by 10 1602 * to allow rounding later */ 1603 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1604 1605 struct fll_div { 1606 u16 outdiv; 1607 u16 n; 1608 u16 k; 1609 u16 clk_ref_div; 1610 u16 fll_fratio; 1611 }; 1612 1613 static int wm8994_get_fll_config(struct fll_div *fll, 1614 int freq_in, int freq_out) 1615 { 1616 u64 Kpart; 1617 unsigned int K, Ndiv, Nmod; 1618 1619 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1620 1621 /* Scale the input frequency down to <= 13.5MHz */ 1622 fll->clk_ref_div = 0; 1623 while (freq_in > 13500000) { 1624 fll->clk_ref_div++; 1625 freq_in /= 2; 1626 1627 if (fll->clk_ref_div > 3) 1628 return -EINVAL; 1629 } 1630 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1631 1632 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1633 fll->outdiv = 3; 1634 while (freq_out * (fll->outdiv + 1) < 90000000) { 1635 fll->outdiv++; 1636 if (fll->outdiv > 63) 1637 return -EINVAL; 1638 } 1639 freq_out *= fll->outdiv + 1; 1640 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1641 1642 if (freq_in > 1000000) { 1643 fll->fll_fratio = 0; 1644 } else if (freq_in > 256000) { 1645 fll->fll_fratio = 1; 1646 freq_in *= 2; 1647 } else if (freq_in > 128000) { 1648 fll->fll_fratio = 2; 1649 freq_in *= 4; 1650 } else if (freq_in > 64000) { 1651 fll->fll_fratio = 3; 1652 freq_in *= 8; 1653 } else { 1654 fll->fll_fratio = 4; 1655 freq_in *= 16; 1656 } 1657 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1658 1659 /* Now, calculate N.K */ 1660 Ndiv = freq_out / freq_in; 1661 1662 fll->n = Ndiv; 1663 Nmod = freq_out % freq_in; 1664 pr_debug("Nmod=%d\n", Nmod); 1665 1666 /* Calculate fractional part - scale up so we can round. */ 1667 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1668 1669 do_div(Kpart, freq_in); 1670 1671 K = Kpart & 0xFFFFFFFF; 1672 1673 if ((K % 10) >= 5) 1674 K += 5; 1675 1676 /* Move down to proper range now rounding is done */ 1677 fll->k = K / 10; 1678 1679 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1680 1681 return 0; 1682 } 1683 1684 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 1685 unsigned int freq_in, unsigned int freq_out) 1686 { 1687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1688 int reg_offset, ret; 1689 struct fll_div fll; 1690 u16 reg, aif1, aif2; 1691 1692 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) 1693 & WM8994_AIF1CLK_ENA; 1694 1695 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) 1696 & WM8994_AIF2CLK_ENA; 1697 1698 switch (id) { 1699 case WM8994_FLL1: 1700 reg_offset = 0; 1701 id = 0; 1702 break; 1703 case WM8994_FLL2: 1704 reg_offset = 0x20; 1705 id = 1; 1706 break; 1707 default: 1708 return -EINVAL; 1709 } 1710 1711 switch (src) { 1712 case 0: 1713 /* Allow no source specification when stopping */ 1714 if (freq_out) 1715 return -EINVAL; 1716 src = wm8994->fll[id].src; 1717 break; 1718 case WM8994_FLL_SRC_MCLK1: 1719 case WM8994_FLL_SRC_MCLK2: 1720 case WM8994_FLL_SRC_LRCLK: 1721 case WM8994_FLL_SRC_BCLK: 1722 break; 1723 default: 1724 return -EINVAL; 1725 } 1726 1727 /* Are we changing anything? */ 1728 if (wm8994->fll[id].src == src && 1729 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 1730 return 0; 1731 1732 /* If we're stopping the FLL redo the old config - no 1733 * registers will actually be written but we avoid GCC flow 1734 * analysis bugs spewing warnings. 1735 */ 1736 if (freq_out) 1737 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 1738 else 1739 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 1740 wm8994->fll[id].out); 1741 if (ret < 0) 1742 return ret; 1743 1744 /* Gate the AIF clocks while we reclock */ 1745 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1746 WM8994_AIF1CLK_ENA, 0); 1747 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1748 WM8994_AIF2CLK_ENA, 0); 1749 1750 /* We always need to disable the FLL while reconfiguring */ 1751 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1752 WM8994_FLL1_ENA, 0); 1753 1754 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 1755 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 1756 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 1757 WM8994_FLL1_OUTDIV_MASK | 1758 WM8994_FLL1_FRATIO_MASK, reg); 1759 1760 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); 1761 1762 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 1763 WM8994_FLL1_N_MASK, 1764 fll.n << WM8994_FLL1_N_SHIFT); 1765 1766 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 1767 WM8994_FLL1_REFCLK_DIV_MASK | 1768 WM8994_FLL1_REFCLK_SRC_MASK, 1769 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 1770 (src - 1)); 1771 1772 /* Enable (with fractional mode if required) */ 1773 if (freq_out) { 1774 if (fll.k) 1775 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; 1776 else 1777 reg = WM8994_FLL1_ENA; 1778 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 1779 WM8994_FLL1_ENA | WM8994_FLL1_FRAC, 1780 reg); 1781 } 1782 1783 wm8994->fll[id].in = freq_in; 1784 wm8994->fll[id].out = freq_out; 1785 wm8994->fll[id].src = src; 1786 1787 /* Enable any gated AIF clocks */ 1788 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1789 WM8994_AIF1CLK_ENA, aif1); 1790 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1791 WM8994_AIF2CLK_ENA, aif2); 1792 1793 configure_clock(codec); 1794 1795 return 0; 1796 } 1797 1798 1799 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 1800 1801 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 1802 unsigned int freq_in, unsigned int freq_out) 1803 { 1804 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 1805 } 1806 1807 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 1808 int clk_id, unsigned int freq, int dir) 1809 { 1810 struct snd_soc_codec *codec = dai->codec; 1811 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1812 int i; 1813 1814 switch (dai->id) { 1815 case 1: 1816 case 2: 1817 break; 1818 1819 default: 1820 /* AIF3 shares clocking with AIF1/2 */ 1821 return -EINVAL; 1822 } 1823 1824 switch (clk_id) { 1825 case WM8994_SYSCLK_MCLK1: 1826 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 1827 wm8994->mclk[0] = freq; 1828 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 1829 dai->id, freq); 1830 break; 1831 1832 case WM8994_SYSCLK_MCLK2: 1833 /* TODO: Set GPIO AF */ 1834 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 1835 wm8994->mclk[1] = freq; 1836 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 1837 dai->id, freq); 1838 break; 1839 1840 case WM8994_SYSCLK_FLL1: 1841 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 1842 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 1843 break; 1844 1845 case WM8994_SYSCLK_FLL2: 1846 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 1847 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 1848 break; 1849 1850 case WM8994_SYSCLK_OPCLK: 1851 /* Special case - a division (times 10) is given and 1852 * no effect on main clocking. 1853 */ 1854 if (freq) { 1855 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 1856 if (opclk_divs[i] == freq) 1857 break; 1858 if (i == ARRAY_SIZE(opclk_divs)) 1859 return -EINVAL; 1860 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 1861 WM8994_OPCLK_DIV_MASK, i); 1862 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 1863 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 1864 } else { 1865 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 1866 WM8994_OPCLK_ENA, 0); 1867 } 1868 1869 default: 1870 return -EINVAL; 1871 } 1872 1873 configure_clock(codec); 1874 1875 return 0; 1876 } 1877 1878 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 1879 enum snd_soc_bias_level level) 1880 { 1881 struct wm8994 *control = codec->control_data; 1882 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1883 1884 switch (level) { 1885 case SND_SOC_BIAS_ON: 1886 break; 1887 1888 case SND_SOC_BIAS_PREPARE: 1889 /* VMID=2x40k */ 1890 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1891 WM8994_VMID_SEL_MASK, 0x2); 1892 break; 1893 1894 case SND_SOC_BIAS_STANDBY: 1895 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1896 pm_runtime_get_sync(codec->dev); 1897 1898 switch (control->type) { 1899 case WM8994: 1900 if (wm8994->revision < 4) { 1901 /* Tweak DC servo and DSP 1902 * configuration for improved 1903 * performance. */ 1904 snd_soc_write(codec, 0x102, 0x3); 1905 snd_soc_write(codec, 0x56, 0x3); 1906 snd_soc_write(codec, 0x817, 0); 1907 snd_soc_write(codec, 0x102, 0); 1908 } 1909 break; 1910 1911 case WM8958: 1912 if (wm8994->revision == 0) { 1913 /* Optimise performance for rev A */ 1914 snd_soc_write(codec, 0x102, 0x3); 1915 snd_soc_write(codec, 0xcb, 0x81); 1916 snd_soc_write(codec, 0x817, 0); 1917 snd_soc_write(codec, 0x102, 0); 1918 1919 snd_soc_update_bits(codec, 1920 WM8958_CHARGE_PUMP_2, 1921 WM8958_CP_DISCH, 1922 WM8958_CP_DISCH); 1923 } 1924 break; 1925 } 1926 1927 /* Discharge LINEOUT1 & 2 */ 1928 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 1929 WM8994_LINEOUT1_DISCH | 1930 WM8994_LINEOUT2_DISCH, 1931 WM8994_LINEOUT1_DISCH | 1932 WM8994_LINEOUT2_DISCH); 1933 1934 /* Startup bias, VMID ramp & buffer */ 1935 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1936 WM8994_STARTUP_BIAS_ENA | 1937 WM8994_VMID_BUF_ENA | 1938 WM8994_VMID_RAMP_MASK, 1939 WM8994_STARTUP_BIAS_ENA | 1940 WM8994_VMID_BUF_ENA | 1941 (0x11 << WM8994_VMID_RAMP_SHIFT)); 1942 1943 /* Main bias enable, VMID=2x40k */ 1944 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1945 WM8994_BIAS_ENA | 1946 WM8994_VMID_SEL_MASK, 1947 WM8994_BIAS_ENA | 0x2); 1948 1949 msleep(20); 1950 } 1951 1952 /* VMID=2x500k */ 1953 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1954 WM8994_VMID_SEL_MASK, 0x4); 1955 1956 break; 1957 1958 case SND_SOC_BIAS_OFF: 1959 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 1960 /* Switch over to startup biases */ 1961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1962 WM8994_BIAS_SRC | 1963 WM8994_STARTUP_BIAS_ENA | 1964 WM8994_VMID_BUF_ENA | 1965 WM8994_VMID_RAMP_MASK, 1966 WM8994_BIAS_SRC | 1967 WM8994_STARTUP_BIAS_ENA | 1968 WM8994_VMID_BUF_ENA | 1969 (1 << WM8994_VMID_RAMP_SHIFT)); 1970 1971 /* Disable main biases */ 1972 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 1973 WM8994_BIAS_ENA | 1974 WM8994_VMID_SEL_MASK, 0); 1975 1976 /* Discharge line */ 1977 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 1978 WM8994_LINEOUT1_DISCH | 1979 WM8994_LINEOUT2_DISCH, 1980 WM8994_LINEOUT1_DISCH | 1981 WM8994_LINEOUT2_DISCH); 1982 1983 msleep(5); 1984 1985 /* Switch off startup biases */ 1986 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1987 WM8994_BIAS_SRC | 1988 WM8994_STARTUP_BIAS_ENA | 1989 WM8994_VMID_BUF_ENA | 1990 WM8994_VMID_RAMP_MASK, 0); 1991 1992 pm_runtime_put(codec->dev); 1993 } 1994 break; 1995 } 1996 codec->dapm.bias_level = level; 1997 return 0; 1998 } 1999 2000 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2001 { 2002 struct snd_soc_codec *codec = dai->codec; 2003 struct wm8994 *control = codec->control_data; 2004 int ms_reg; 2005 int aif1_reg; 2006 int ms = 0; 2007 int aif1 = 0; 2008 2009 switch (dai->id) { 2010 case 1: 2011 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2012 aif1_reg = WM8994_AIF1_CONTROL_1; 2013 break; 2014 case 2: 2015 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2016 aif1_reg = WM8994_AIF2_CONTROL_1; 2017 break; 2018 default: 2019 return -EINVAL; 2020 } 2021 2022 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2023 case SND_SOC_DAIFMT_CBS_CFS: 2024 break; 2025 case SND_SOC_DAIFMT_CBM_CFM: 2026 ms = WM8994_AIF1_MSTR; 2027 break; 2028 default: 2029 return -EINVAL; 2030 } 2031 2032 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2033 case SND_SOC_DAIFMT_DSP_B: 2034 aif1 |= WM8994_AIF1_LRCLK_INV; 2035 case SND_SOC_DAIFMT_DSP_A: 2036 aif1 |= 0x18; 2037 break; 2038 case SND_SOC_DAIFMT_I2S: 2039 aif1 |= 0x10; 2040 break; 2041 case SND_SOC_DAIFMT_RIGHT_J: 2042 break; 2043 case SND_SOC_DAIFMT_LEFT_J: 2044 aif1 |= 0x8; 2045 break; 2046 default: 2047 return -EINVAL; 2048 } 2049 2050 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2051 case SND_SOC_DAIFMT_DSP_A: 2052 case SND_SOC_DAIFMT_DSP_B: 2053 /* frame inversion not valid for DSP modes */ 2054 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2055 case SND_SOC_DAIFMT_NB_NF: 2056 break; 2057 case SND_SOC_DAIFMT_IB_NF: 2058 aif1 |= WM8994_AIF1_BCLK_INV; 2059 break; 2060 default: 2061 return -EINVAL; 2062 } 2063 break; 2064 2065 case SND_SOC_DAIFMT_I2S: 2066 case SND_SOC_DAIFMT_RIGHT_J: 2067 case SND_SOC_DAIFMT_LEFT_J: 2068 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2069 case SND_SOC_DAIFMT_NB_NF: 2070 break; 2071 case SND_SOC_DAIFMT_IB_IF: 2072 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2073 break; 2074 case SND_SOC_DAIFMT_IB_NF: 2075 aif1 |= WM8994_AIF1_BCLK_INV; 2076 break; 2077 case SND_SOC_DAIFMT_NB_IF: 2078 aif1 |= WM8994_AIF1_LRCLK_INV; 2079 break; 2080 default: 2081 return -EINVAL; 2082 } 2083 break; 2084 default: 2085 return -EINVAL; 2086 } 2087 2088 /* The AIF2 format configuration needs to be mirrored to AIF3 2089 * on WM8958 if it's in use so just do it all the time. */ 2090 if (control->type == WM8958 && dai->id == 2) 2091 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2092 WM8994_AIF1_LRCLK_INV | 2093 WM8958_AIF3_FMT_MASK, aif1); 2094 2095 snd_soc_update_bits(codec, aif1_reg, 2096 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2097 WM8994_AIF1_FMT_MASK, 2098 aif1); 2099 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2100 ms); 2101 2102 return 0; 2103 } 2104 2105 static struct { 2106 int val, rate; 2107 } srs[] = { 2108 { 0, 8000 }, 2109 { 1, 11025 }, 2110 { 2, 12000 }, 2111 { 3, 16000 }, 2112 { 4, 22050 }, 2113 { 5, 24000 }, 2114 { 6, 32000 }, 2115 { 7, 44100 }, 2116 { 8, 48000 }, 2117 { 9, 88200 }, 2118 { 10, 96000 }, 2119 }; 2120 2121 static int fs_ratios[] = { 2122 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2123 }; 2124 2125 static int bclk_divs[] = { 2126 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2127 640, 880, 960, 1280, 1760, 1920 2128 }; 2129 2130 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2131 struct snd_pcm_hw_params *params, 2132 struct snd_soc_dai *dai) 2133 { 2134 struct snd_soc_codec *codec = dai->codec; 2135 struct wm8994 *control = codec->control_data; 2136 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2137 int aif1_reg; 2138 int aif2_reg; 2139 int bclk_reg; 2140 int lrclk_reg; 2141 int rate_reg; 2142 int aif1 = 0; 2143 int aif2 = 0; 2144 int bclk = 0; 2145 int lrclk = 0; 2146 int rate_val = 0; 2147 int id = dai->id - 1; 2148 2149 int i, cur_val, best_val, bclk_rate, best; 2150 2151 switch (dai->id) { 2152 case 1: 2153 aif1_reg = WM8994_AIF1_CONTROL_1; 2154 aif2_reg = WM8994_AIF1_CONTROL_2; 2155 bclk_reg = WM8994_AIF1_BCLK; 2156 rate_reg = WM8994_AIF1_RATE; 2157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2158 wm8994->lrclk_shared[0]) { 2159 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2160 } else { 2161 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2162 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2163 } 2164 break; 2165 case 2: 2166 aif1_reg = WM8994_AIF2_CONTROL_1; 2167 aif2_reg = WM8994_AIF2_CONTROL_2; 2168 bclk_reg = WM8994_AIF2_BCLK; 2169 rate_reg = WM8994_AIF2_RATE; 2170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2171 wm8994->lrclk_shared[1]) { 2172 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2173 } else { 2174 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2175 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2176 } 2177 break; 2178 case 3: 2179 switch (control->type) { 2180 case WM8958: 2181 aif1_reg = WM8958_AIF3_CONTROL_1; 2182 break; 2183 default: 2184 return 0; 2185 } 2186 default: 2187 return -EINVAL; 2188 } 2189 2190 bclk_rate = params_rate(params) * 2; 2191 switch (params_format(params)) { 2192 case SNDRV_PCM_FORMAT_S16_LE: 2193 bclk_rate *= 16; 2194 break; 2195 case SNDRV_PCM_FORMAT_S20_3LE: 2196 bclk_rate *= 20; 2197 aif1 |= 0x20; 2198 break; 2199 case SNDRV_PCM_FORMAT_S24_LE: 2200 bclk_rate *= 24; 2201 aif1 |= 0x40; 2202 break; 2203 case SNDRV_PCM_FORMAT_S32_LE: 2204 bclk_rate *= 32; 2205 aif1 |= 0x60; 2206 break; 2207 default: 2208 return -EINVAL; 2209 } 2210 2211 /* Try to find an appropriate sample rate; look for an exact match. */ 2212 for (i = 0; i < ARRAY_SIZE(srs); i++) 2213 if (srs[i].rate == params_rate(params)) 2214 break; 2215 if (i == ARRAY_SIZE(srs)) 2216 return -EINVAL; 2217 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2218 2219 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2220 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2221 dai->id, wm8994->aifclk[id], bclk_rate); 2222 2223 if (params_channels(params) == 1 && 2224 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2225 aif2 |= WM8994_AIF1_MONO; 2226 2227 if (wm8994->aifclk[id] == 0) { 2228 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2229 return -EINVAL; 2230 } 2231 2232 /* AIFCLK/fs ratio; look for a close match in either direction */ 2233 best = 0; 2234 best_val = abs((fs_ratios[0] * params_rate(params)) 2235 - wm8994->aifclk[id]); 2236 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2237 cur_val = abs((fs_ratios[i] * params_rate(params)) 2238 - wm8994->aifclk[id]); 2239 if (cur_val >= best_val) 2240 continue; 2241 best = i; 2242 best_val = cur_val; 2243 } 2244 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2245 dai->id, fs_ratios[best]); 2246 rate_val |= best; 2247 2248 /* We may not get quite the right frequency if using 2249 * approximate clocks so look for the closest match that is 2250 * higher than the target (we need to ensure that there enough 2251 * BCLKs to clock out the samples). 2252 */ 2253 best = 0; 2254 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2255 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2256 if (cur_val < 0) /* BCLK table is sorted */ 2257 break; 2258 best = i; 2259 } 2260 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2261 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2262 bclk_divs[best], bclk_rate); 2263 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2264 2265 lrclk = bclk_rate / params_rate(params); 2266 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2267 lrclk, bclk_rate / lrclk); 2268 2269 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2270 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2271 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2272 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2273 lrclk); 2274 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2275 WM8994_AIF1CLK_RATE_MASK, rate_val); 2276 2277 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2278 switch (dai->id) { 2279 case 1: 2280 wm8994->dac_rates[0] = params_rate(params); 2281 wm8994_set_retune_mobile(codec, 0); 2282 wm8994_set_retune_mobile(codec, 1); 2283 break; 2284 case 2: 2285 wm8994->dac_rates[1] = params_rate(params); 2286 wm8994_set_retune_mobile(codec, 2); 2287 break; 2288 } 2289 } 2290 2291 return 0; 2292 } 2293 2294 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2295 struct snd_pcm_hw_params *params, 2296 struct snd_soc_dai *dai) 2297 { 2298 struct snd_soc_codec *codec = dai->codec; 2299 struct wm8994 *control = codec->control_data; 2300 int aif1_reg; 2301 int aif1 = 0; 2302 2303 switch (dai->id) { 2304 case 3: 2305 switch (control->type) { 2306 case WM8958: 2307 aif1_reg = WM8958_AIF3_CONTROL_1; 2308 break; 2309 default: 2310 return 0; 2311 } 2312 default: 2313 return 0; 2314 } 2315 2316 switch (params_format(params)) { 2317 case SNDRV_PCM_FORMAT_S16_LE: 2318 break; 2319 case SNDRV_PCM_FORMAT_S20_3LE: 2320 aif1 |= 0x20; 2321 break; 2322 case SNDRV_PCM_FORMAT_S24_LE: 2323 aif1 |= 0x40; 2324 break; 2325 case SNDRV_PCM_FORMAT_S32_LE: 2326 aif1 |= 0x60; 2327 break; 2328 default: 2329 return -EINVAL; 2330 } 2331 2332 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2333 } 2334 2335 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2336 { 2337 struct snd_soc_codec *codec = codec_dai->codec; 2338 int mute_reg; 2339 int reg; 2340 2341 switch (codec_dai->id) { 2342 case 1: 2343 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2344 break; 2345 case 2: 2346 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2347 break; 2348 default: 2349 return -EINVAL; 2350 } 2351 2352 if (mute) 2353 reg = WM8994_AIF1DAC1_MUTE; 2354 else 2355 reg = 0; 2356 2357 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2358 2359 return 0; 2360 } 2361 2362 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 2363 { 2364 struct snd_soc_codec *codec = codec_dai->codec; 2365 int reg, val, mask; 2366 2367 switch (codec_dai->id) { 2368 case 1: 2369 reg = WM8994_AIF1_MASTER_SLAVE; 2370 mask = WM8994_AIF1_TRI; 2371 break; 2372 case 2: 2373 reg = WM8994_AIF2_MASTER_SLAVE; 2374 mask = WM8994_AIF2_TRI; 2375 break; 2376 case 3: 2377 reg = WM8994_POWER_MANAGEMENT_6; 2378 mask = WM8994_AIF3_TRI; 2379 break; 2380 default: 2381 return -EINVAL; 2382 } 2383 2384 if (tristate) 2385 val = mask; 2386 else 2387 val = 0; 2388 2389 return snd_soc_update_bits(codec, reg, mask, reg); 2390 } 2391 2392 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2393 2394 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2395 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2396 2397 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2398 .set_sysclk = wm8994_set_dai_sysclk, 2399 .set_fmt = wm8994_set_dai_fmt, 2400 .hw_params = wm8994_hw_params, 2401 .digital_mute = wm8994_aif_mute, 2402 .set_pll = wm8994_set_fll, 2403 .set_tristate = wm8994_set_tristate, 2404 }; 2405 2406 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2407 .set_sysclk = wm8994_set_dai_sysclk, 2408 .set_fmt = wm8994_set_dai_fmt, 2409 .hw_params = wm8994_hw_params, 2410 .digital_mute = wm8994_aif_mute, 2411 .set_pll = wm8994_set_fll, 2412 .set_tristate = wm8994_set_tristate, 2413 }; 2414 2415 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2416 .hw_params = wm8994_aif3_hw_params, 2417 .set_tristate = wm8994_set_tristate, 2418 }; 2419 2420 static struct snd_soc_dai_driver wm8994_dai[] = { 2421 { 2422 .name = "wm8994-aif1", 2423 .id = 1, 2424 .playback = { 2425 .stream_name = "AIF1 Playback", 2426 .channels_min = 1, 2427 .channels_max = 2, 2428 .rates = WM8994_RATES, 2429 .formats = WM8994_FORMATS, 2430 }, 2431 .capture = { 2432 .stream_name = "AIF1 Capture", 2433 .channels_min = 1, 2434 .channels_max = 2, 2435 .rates = WM8994_RATES, 2436 .formats = WM8994_FORMATS, 2437 }, 2438 .ops = &wm8994_aif1_dai_ops, 2439 }, 2440 { 2441 .name = "wm8994-aif2", 2442 .id = 2, 2443 .playback = { 2444 .stream_name = "AIF2 Playback", 2445 .channels_min = 1, 2446 .channels_max = 2, 2447 .rates = WM8994_RATES, 2448 .formats = WM8994_FORMATS, 2449 }, 2450 .capture = { 2451 .stream_name = "AIF2 Capture", 2452 .channels_min = 1, 2453 .channels_max = 2, 2454 .rates = WM8994_RATES, 2455 .formats = WM8994_FORMATS, 2456 }, 2457 .ops = &wm8994_aif2_dai_ops, 2458 }, 2459 { 2460 .name = "wm8994-aif3", 2461 .id = 3, 2462 .playback = { 2463 .stream_name = "AIF3 Playback", 2464 .channels_min = 1, 2465 .channels_max = 2, 2466 .rates = WM8994_RATES, 2467 .formats = WM8994_FORMATS, 2468 }, 2469 .capture = { 2470 .stream_name = "AIF3 Capture", 2471 .channels_min = 1, 2472 .channels_max = 2, 2473 .rates = WM8994_RATES, 2474 .formats = WM8994_FORMATS, 2475 }, 2476 .ops = &wm8994_aif3_dai_ops, 2477 } 2478 }; 2479 2480 #ifdef CONFIG_PM 2481 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state) 2482 { 2483 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2484 int i, ret; 2485 2486 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2487 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 2488 sizeof(struct fll_config)); 2489 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 2490 if (ret < 0) 2491 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 2492 i + 1, ret); 2493 } 2494 2495 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 2496 2497 return 0; 2498 } 2499 2500 static int wm8994_resume(struct snd_soc_codec *codec) 2501 { 2502 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2503 int i, ret; 2504 2505 /* Restore the registers */ 2506 ret = snd_soc_cache_sync(codec); 2507 if (ret != 0) 2508 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 2509 2510 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2511 2512 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 2513 if (!wm8994->fll_suspend[i].out) 2514 continue; 2515 2516 ret = _wm8994_set_fll(codec, i + 1, 2517 wm8994->fll_suspend[i].src, 2518 wm8994->fll_suspend[i].in, 2519 wm8994->fll_suspend[i].out); 2520 if (ret < 0) 2521 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 2522 i + 1, ret); 2523 } 2524 2525 return 0; 2526 } 2527 #else 2528 #define wm8994_suspend NULL 2529 #define wm8994_resume NULL 2530 #endif 2531 2532 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 2533 { 2534 struct snd_soc_codec *codec = wm8994->codec; 2535 struct wm8994_pdata *pdata = wm8994->pdata; 2536 struct snd_kcontrol_new controls[] = { 2537 SOC_ENUM_EXT("AIF1.1 EQ Mode", 2538 wm8994->retune_mobile_enum, 2539 wm8994_get_retune_mobile_enum, 2540 wm8994_put_retune_mobile_enum), 2541 SOC_ENUM_EXT("AIF1.2 EQ Mode", 2542 wm8994->retune_mobile_enum, 2543 wm8994_get_retune_mobile_enum, 2544 wm8994_put_retune_mobile_enum), 2545 SOC_ENUM_EXT("AIF2 EQ Mode", 2546 wm8994->retune_mobile_enum, 2547 wm8994_get_retune_mobile_enum, 2548 wm8994_put_retune_mobile_enum), 2549 }; 2550 int ret, i, j; 2551 const char **t; 2552 2553 /* We need an array of texts for the enum API but the number 2554 * of texts is likely to be less than the number of 2555 * configurations due to the sample rate dependency of the 2556 * configurations. */ 2557 wm8994->num_retune_mobile_texts = 0; 2558 wm8994->retune_mobile_texts = NULL; 2559 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2560 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 2561 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2562 wm8994->retune_mobile_texts[j]) == 0) 2563 break; 2564 } 2565 2566 if (j != wm8994->num_retune_mobile_texts) 2567 continue; 2568 2569 /* Expand the array... */ 2570 t = krealloc(wm8994->retune_mobile_texts, 2571 sizeof(char *) * 2572 (wm8994->num_retune_mobile_texts + 1), 2573 GFP_KERNEL); 2574 if (t == NULL) 2575 continue; 2576 2577 /* ...store the new entry... */ 2578 t[wm8994->num_retune_mobile_texts] = 2579 pdata->retune_mobile_cfgs[i].name; 2580 2581 /* ...and remember the new version. */ 2582 wm8994->num_retune_mobile_texts++; 2583 wm8994->retune_mobile_texts = t; 2584 } 2585 2586 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2587 wm8994->num_retune_mobile_texts); 2588 2589 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 2590 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 2591 2592 ret = snd_soc_add_controls(wm8994->codec, controls, 2593 ARRAY_SIZE(controls)); 2594 if (ret != 0) 2595 dev_err(wm8994->codec->dev, 2596 "Failed to add ReTune Mobile controls: %d\n", ret); 2597 } 2598 2599 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 2600 { 2601 struct snd_soc_codec *codec = wm8994->codec; 2602 struct wm8994_pdata *pdata = wm8994->pdata; 2603 int ret, i; 2604 2605 if (!pdata) 2606 return; 2607 2608 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 2609 pdata->lineout2_diff, 2610 pdata->lineout1fb, 2611 pdata->lineout2fb, 2612 pdata->jd_scthr, 2613 pdata->jd_thr, 2614 pdata->micbias1_lvl, 2615 pdata->micbias2_lvl); 2616 2617 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2618 2619 if (pdata->num_drc_cfgs) { 2620 struct snd_kcontrol_new controls[] = { 2621 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 2622 wm8994_get_drc_enum, wm8994_put_drc_enum), 2623 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 2624 wm8994_get_drc_enum, wm8994_put_drc_enum), 2625 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 2626 wm8994_get_drc_enum, wm8994_put_drc_enum), 2627 }; 2628 2629 /* We need an array of texts for the enum API */ 2630 wm8994->drc_texts = kmalloc(sizeof(char *) 2631 * pdata->num_drc_cfgs, GFP_KERNEL); 2632 if (!wm8994->drc_texts) { 2633 dev_err(wm8994->codec->dev, 2634 "Failed to allocate %d DRC config texts\n", 2635 pdata->num_drc_cfgs); 2636 return; 2637 } 2638 2639 for (i = 0; i < pdata->num_drc_cfgs; i++) 2640 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 2641 2642 wm8994->drc_enum.max = pdata->num_drc_cfgs; 2643 wm8994->drc_enum.texts = wm8994->drc_texts; 2644 2645 ret = snd_soc_add_controls(wm8994->codec, controls, 2646 ARRAY_SIZE(controls)); 2647 if (ret != 0) 2648 dev_err(wm8994->codec->dev, 2649 "Failed to add DRC mode controls: %d\n", ret); 2650 2651 for (i = 0; i < WM8994_NUM_DRC; i++) 2652 wm8994_set_drc(codec, i); 2653 } 2654 2655 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2656 pdata->num_retune_mobile_cfgs); 2657 2658 if (pdata->num_mbc_cfgs) { 2659 struct snd_kcontrol_new control[] = { 2660 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum, 2661 wm8958_get_mbc_enum, wm8958_put_mbc_enum), 2662 }; 2663 2664 /* We need an array of texts for the enum API */ 2665 wm8994->mbc_texts = kmalloc(sizeof(char *) 2666 * pdata->num_mbc_cfgs, GFP_KERNEL); 2667 if (!wm8994->mbc_texts) { 2668 dev_err(wm8994->codec->dev, 2669 "Failed to allocate %d MBC config texts\n", 2670 pdata->num_mbc_cfgs); 2671 return; 2672 } 2673 2674 for (i = 0; i < pdata->num_mbc_cfgs; i++) 2675 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name; 2676 2677 wm8994->mbc_enum.max = pdata->num_mbc_cfgs; 2678 wm8994->mbc_enum.texts = wm8994->mbc_texts; 2679 2680 ret = snd_soc_add_controls(wm8994->codec, control, 1); 2681 if (ret != 0) 2682 dev_err(wm8994->codec->dev, 2683 "Failed to add MBC mode controls: %d\n", ret); 2684 } 2685 2686 if (pdata->num_retune_mobile_cfgs) 2687 wm8994_handle_retune_mobile_pdata(wm8994); 2688 else 2689 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls, 2690 ARRAY_SIZE(wm8994_eq_controls)); 2691 } 2692 2693 /** 2694 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 2695 * 2696 * @codec: WM8994 codec 2697 * @jack: jack to report detection events on 2698 * @micbias: microphone bias to detect on 2699 * @det: value to report for presence detection 2700 * @shrt: value to report for short detection 2701 * 2702 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 2703 * being used to bring out signals to the processor then only platform 2704 * data configuration is needed for WM8994 and processor GPIOs should 2705 * be configured using snd_soc_jack_add_gpios() instead. 2706 * 2707 * Configuration of detection levels is available via the micbias1_lvl 2708 * and micbias2_lvl platform data members. 2709 */ 2710 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2711 int micbias, int det, int shrt) 2712 { 2713 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2714 struct wm8994_micdet *micdet; 2715 struct wm8994 *control = codec->control_data; 2716 int reg; 2717 2718 if (control->type != WM8994) 2719 return -EINVAL; 2720 2721 switch (micbias) { 2722 case 1: 2723 micdet = &wm8994->micdet[0]; 2724 break; 2725 case 2: 2726 micdet = &wm8994->micdet[1]; 2727 break; 2728 default: 2729 return -EINVAL; 2730 } 2731 2732 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", 2733 micbias, det, shrt); 2734 2735 /* Store the configuration */ 2736 micdet->jack = jack; 2737 micdet->det = det; 2738 micdet->shrt = shrt; 2739 2740 /* If either of the jacks is set up then enable detection */ 2741 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 2742 reg = WM8994_MICD_ENA; 2743 else 2744 reg = 0; 2745 2746 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 2747 2748 return 0; 2749 } 2750 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 2751 2752 static irqreturn_t wm8994_mic_irq(int irq, void *data) 2753 { 2754 struct wm8994_priv *priv = data; 2755 struct snd_soc_codec *codec = priv->codec; 2756 int reg; 2757 int report; 2758 2759 #ifndef CONFIG_SND_SOC_WM8994_MODULE 2760 trace_snd_soc_jack_irq(dev_name(codec->dev)); 2761 #endif 2762 2763 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2764 if (reg < 0) { 2765 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2766 reg); 2767 return IRQ_HANDLED; 2768 } 2769 2770 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 2771 2772 report = 0; 2773 if (reg & WM8994_MIC1_DET_STS) 2774 report |= priv->micdet[0].det; 2775 if (reg & WM8994_MIC1_SHRT_STS) 2776 report |= priv->micdet[0].shrt; 2777 snd_soc_jack_report(priv->micdet[0].jack, report, 2778 priv->micdet[0].det | priv->micdet[0].shrt); 2779 2780 report = 0; 2781 if (reg & WM8994_MIC2_DET_STS) 2782 report |= priv->micdet[1].det; 2783 if (reg & WM8994_MIC2_SHRT_STS) 2784 report |= priv->micdet[1].shrt; 2785 snd_soc_jack_report(priv->micdet[1].jack, report, 2786 priv->micdet[1].det | priv->micdet[1].shrt); 2787 2788 return IRQ_HANDLED; 2789 } 2790 2791 /* Default microphone detection handler for WM8958 - the user can 2792 * override this if they wish. 2793 */ 2794 static void wm8958_default_micdet(u16 status, void *data) 2795 { 2796 struct snd_soc_codec *codec = data; 2797 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2798 int report = 0; 2799 2800 /* If nothing present then clear our statuses */ 2801 if (!(status & WM8958_MICD_STS)) { 2802 wm8994->jack_is_video = false; 2803 wm8994->jack_is_mic = false; 2804 goto done; 2805 } 2806 2807 /* Assume anything over 475 ohms is a microphone and remember 2808 * that we've seen one (since buttons override it) */ 2809 if (status & 0x600) 2810 wm8994->jack_is_mic = true; 2811 if (wm8994->jack_is_mic) 2812 report |= SND_JACK_MICROPHONE; 2813 2814 /* Video has an impedence of approximately 75 ohms; assume 2815 * this isn't used as a button and remember it since buttons 2816 * override it. */ 2817 if (status & 0x40) 2818 wm8994->jack_is_video = true; 2819 if (wm8994->jack_is_video) 2820 report |= SND_JACK_VIDEOOUT; 2821 2822 /* Everything else is buttons; just assign slots */ 2823 if (status & 0x4) 2824 report |= SND_JACK_BTN_0; 2825 if (status & 0x8) 2826 report |= SND_JACK_BTN_1; 2827 if (status & 0x10) 2828 report |= SND_JACK_BTN_2; 2829 if (status & 0x20) 2830 report |= SND_JACK_BTN_3; 2831 if (status & 0x80) 2832 report |= SND_JACK_BTN_4; 2833 if (status & 0x100) 2834 report |= SND_JACK_BTN_5; 2835 2836 done: 2837 snd_soc_jack_report(wm8994->micdet[0].jack, 2838 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | 2839 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 | 2840 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT, 2841 report); 2842 } 2843 2844 /** 2845 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 2846 * 2847 * @codec: WM8958 codec 2848 * @jack: jack to report detection events on 2849 * 2850 * Enable microphone detection functionality for the WM8958. By 2851 * default simple detection which supports the detection of up to 6 2852 * buttons plus video and microphone functionality is supported. 2853 * 2854 * The WM8958 has an advanced jack detection facility which is able to 2855 * support complex accessory detection, especially when used in 2856 * conjunction with external circuitry. In order to provide maximum 2857 * flexiblity a callback is provided which allows a completely custom 2858 * detection algorithm. 2859 */ 2860 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2861 wm8958_micdet_cb cb, void *cb_data) 2862 { 2863 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2864 struct wm8994 *control = codec->control_data; 2865 2866 if (control->type != WM8958) 2867 return -EINVAL; 2868 2869 if (jack) { 2870 if (!cb) { 2871 dev_dbg(codec->dev, "Using default micdet callback\n"); 2872 cb = wm8958_default_micdet; 2873 cb_data = codec; 2874 } 2875 2876 wm8994->micdet[0].jack = jack; 2877 wm8994->jack_cb = cb; 2878 wm8994->jack_cb_data = cb_data; 2879 2880 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2881 WM8958_MICD_ENA, WM8958_MICD_ENA); 2882 } else { 2883 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 2884 WM8958_MICD_ENA, 0); 2885 } 2886 2887 return 0; 2888 } 2889 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 2890 2891 static irqreturn_t wm8958_mic_irq(int irq, void *data) 2892 { 2893 struct wm8994_priv *wm8994 = data; 2894 struct snd_soc_codec *codec = wm8994->codec; 2895 int reg; 2896 2897 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 2898 if (reg < 0) { 2899 dev_err(codec->dev, "Failed to read mic detect status: %d\n", 2900 reg); 2901 return IRQ_NONE; 2902 } 2903 2904 if (!(reg & WM8958_MICD_VALID)) { 2905 dev_dbg(codec->dev, "Mic detect data not valid\n"); 2906 goto out; 2907 } 2908 2909 #ifndef CONFIG_SND_SOC_WM8994_MODULE 2910 trace_snd_soc_jack_irq(dev_name(codec->dev)); 2911 #endif 2912 2913 if (wm8994->jack_cb) 2914 wm8994->jack_cb(reg, wm8994->jack_cb_data); 2915 else 2916 dev_warn(codec->dev, "Accessory detection with no callback\n"); 2917 2918 out: 2919 return IRQ_HANDLED; 2920 } 2921 2922 static int wm8994_codec_probe(struct snd_soc_codec *codec) 2923 { 2924 struct wm8994 *control; 2925 struct wm8994_priv *wm8994; 2926 struct snd_soc_dapm_context *dapm = &codec->dapm; 2927 int ret, i; 2928 2929 codec->control_data = dev_get_drvdata(codec->dev->parent); 2930 control = codec->control_data; 2931 2932 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 2933 if (wm8994 == NULL) 2934 return -ENOMEM; 2935 snd_soc_codec_set_drvdata(codec, wm8994); 2936 2937 wm8994->pdata = dev_get_platdata(codec->dev->parent); 2938 wm8994->codec = codec; 2939 2940 pm_runtime_enable(codec->dev); 2941 pm_runtime_resume(codec->dev); 2942 2943 /* Read our current status back from the chip - we don't want to 2944 * reset as this may interfere with the GPIO or LDO operation. */ 2945 for (i = 0; i < WM8994_CACHE_SIZE; i++) { 2946 if (!wm8994_readable(i) || wm8994_volatile(i)) 2947 continue; 2948 2949 ret = wm8994_reg_read(codec->control_data, i); 2950 if (ret <= 0) 2951 continue; 2952 2953 ret = snd_soc_cache_write(codec, i, ret); 2954 if (ret != 0) { 2955 dev_err(codec->dev, 2956 "Failed to initialise cache for 0x%x: %d\n", 2957 i, ret); 2958 goto err; 2959 } 2960 } 2961 2962 /* Set revision-specific configuration */ 2963 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 2964 switch (control->type) { 2965 case WM8994: 2966 switch (wm8994->revision) { 2967 case 2: 2968 case 3: 2969 wm8994->hubs.dcs_codes = -5; 2970 wm8994->hubs.hp_startup_mode = 1; 2971 wm8994->hubs.dcs_readback_mode = 1; 2972 break; 2973 default: 2974 wm8994->hubs.dcs_readback_mode = 1; 2975 break; 2976 } 2977 2978 case WM8958: 2979 wm8994->hubs.dcs_readback_mode = 1; 2980 break; 2981 2982 default: 2983 break; 2984 } 2985 2986 switch (control->type) { 2987 case WM8994: 2988 ret = wm8994_request_irq(codec->control_data, 2989 WM8994_IRQ_MIC1_DET, 2990 wm8994_mic_irq, "Mic 1 detect", 2991 wm8994); 2992 if (ret != 0) 2993 dev_warn(codec->dev, 2994 "Failed to request Mic1 detect IRQ: %d\n", 2995 ret); 2996 2997 ret = wm8994_request_irq(codec->control_data, 2998 WM8994_IRQ_MIC1_SHRT, 2999 wm8994_mic_irq, "Mic 1 short", 3000 wm8994); 3001 if (ret != 0) 3002 dev_warn(codec->dev, 3003 "Failed to request Mic1 short IRQ: %d\n", 3004 ret); 3005 3006 ret = wm8994_request_irq(codec->control_data, 3007 WM8994_IRQ_MIC2_DET, 3008 wm8994_mic_irq, "Mic 2 detect", 3009 wm8994); 3010 if (ret != 0) 3011 dev_warn(codec->dev, 3012 "Failed to request Mic2 detect IRQ: %d\n", 3013 ret); 3014 3015 ret = wm8994_request_irq(codec->control_data, 3016 WM8994_IRQ_MIC2_SHRT, 3017 wm8994_mic_irq, "Mic 2 short", 3018 wm8994); 3019 if (ret != 0) 3020 dev_warn(codec->dev, 3021 "Failed to request Mic2 short IRQ: %d\n", 3022 ret); 3023 break; 3024 3025 case WM8958: 3026 ret = wm8994_request_irq(codec->control_data, 3027 WM8994_IRQ_MIC1_DET, 3028 wm8958_mic_irq, "Mic detect", 3029 wm8994); 3030 if (ret != 0) 3031 dev_warn(codec->dev, 3032 "Failed to request Mic detect IRQ: %d\n", 3033 ret); 3034 break; 3035 } 3036 3037 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3038 * configured on init - if a system wants to do this dynamically 3039 * at runtime we can deal with that then. 3040 */ 3041 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); 3042 if (ret < 0) { 3043 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 3044 goto err_irq; 3045 } 3046 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3047 wm8994->lrclk_shared[0] = 1; 3048 wm8994_dai[0].symmetric_rates = 1; 3049 } else { 3050 wm8994->lrclk_shared[0] = 0; 3051 } 3052 3053 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); 3054 if (ret < 0) { 3055 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 3056 goto err_irq; 3057 } 3058 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3059 wm8994->lrclk_shared[1] = 1; 3060 wm8994_dai[1].symmetric_rates = 1; 3061 } else { 3062 wm8994->lrclk_shared[1] = 0; 3063 } 3064 3065 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3066 3067 /* Latch volume updates (right only; we always do left then right). */ 3068 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, 3069 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3070 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, 3071 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3072 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, 3073 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3074 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, 3075 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3076 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, 3077 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3078 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, 3079 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3080 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, 3081 WM8994_DAC1_VU, WM8994_DAC1_VU); 3082 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, 3083 WM8994_DAC2_VU, WM8994_DAC2_VU); 3084 3085 /* Set the low bit of the 3D stereo depth so TLV matches */ 3086 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 3087 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 3088 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 3089 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 3090 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 3091 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 3092 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 3093 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 3094 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 3095 3096 /* Unconditionally enable AIF1 ADC TDM mode; it only affects 3097 * behaviour on idle TDM clock cycles. */ 3098 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 3099 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 3100 3101 wm8994_update_class_w(codec); 3102 3103 wm8994_handle_pdata(wm8994); 3104 3105 wm_hubs_add_analogue_controls(codec); 3106 snd_soc_add_controls(codec, wm8994_snd_controls, 3107 ARRAY_SIZE(wm8994_snd_controls)); 3108 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 3109 ARRAY_SIZE(wm8994_dapm_widgets)); 3110 3111 switch (control->type) { 3112 case WM8994: 3113 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 3114 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 3115 break; 3116 case WM8958: 3117 snd_soc_add_controls(codec, wm8958_snd_controls, 3118 ARRAY_SIZE(wm8958_snd_controls)); 3119 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 3120 ARRAY_SIZE(wm8958_dapm_widgets)); 3121 break; 3122 } 3123 3124 3125 wm_hubs_add_analogue_routes(codec, 0, 0); 3126 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 3127 3128 switch (control->type) { 3129 case WM8994: 3130 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 3131 ARRAY_SIZE(wm8994_intercon)); 3132 break; 3133 case WM8958: 3134 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 3135 ARRAY_SIZE(wm8958_intercon)); 3136 break; 3137 } 3138 3139 return 0; 3140 3141 err_irq: 3142 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3143 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3144 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3145 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3146 err: 3147 kfree(wm8994); 3148 return ret; 3149 } 3150 3151 static int wm8994_codec_remove(struct snd_soc_codec *codec) 3152 { 3153 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3154 struct wm8994 *control = codec->control_data; 3155 3156 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3157 3158 pm_runtime_disable(codec->dev); 3159 3160 switch (control->type) { 3161 case WM8994: 3162 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3163 wm8994); 3164 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 3165 wm8994); 3166 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 3167 wm8994); 3168 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3169 wm8994); 3170 break; 3171 3172 case WM8958: 3173 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3174 wm8994); 3175 break; 3176 } 3177 kfree(wm8994->retune_mobile_texts); 3178 kfree(wm8994->drc_texts); 3179 kfree(wm8994); 3180 3181 return 0; 3182 } 3183 3184 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 3185 .probe = wm8994_codec_probe, 3186 .remove = wm8994_codec_remove, 3187 .suspend = wm8994_suspend, 3188 .resume = wm8994_resume, 3189 .read = wm8994_read, 3190 .write = wm8994_write, 3191 .readable_register = wm8994_readable, 3192 .volatile_register = wm8994_volatile, 3193 .set_bias_level = wm8994_set_bias_level, 3194 3195 .reg_cache_size = WM8994_CACHE_SIZE, 3196 .reg_cache_default = wm8994_reg_defaults, 3197 .reg_word_size = 2, 3198 .compress_type = SND_SOC_RBTREE_COMPRESSION, 3199 }; 3200 3201 static int __devinit wm8994_probe(struct platform_device *pdev) 3202 { 3203 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 3204 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 3205 } 3206 3207 static int __devexit wm8994_remove(struct platform_device *pdev) 3208 { 3209 snd_soc_unregister_codec(&pdev->dev); 3210 return 0; 3211 } 3212 3213 static struct platform_driver wm8994_codec_driver = { 3214 .driver = { 3215 .name = "wm8994-codec", 3216 .owner = THIS_MODULE, 3217 }, 3218 .probe = wm8994_probe, 3219 .remove = __devexit_p(wm8994_remove), 3220 }; 3221 3222 static __init int wm8994_init(void) 3223 { 3224 return platform_driver_register(&wm8994_codec_driver); 3225 } 3226 module_init(wm8994_init); 3227 3228 static __exit void wm8994_exit(void) 3229 { 3230 platform_driver_unregister(&wm8994_codec_driver); 3231 } 3232 module_exit(wm8994_exit); 3233 3234 3235 MODULE_DESCRIPTION("ASoC WM8994 driver"); 3236 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3237 MODULE_LICENSE("GPL"); 3238 MODULE_ALIAS("platform:wm8994-codec"); 3239