1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <trace/events/asoc.h> 32 33 #include <linux/mfd/wm8994/core.h> 34 #include <linux/mfd/wm8994/registers.h> 35 #include <linux/mfd/wm8994/pdata.h> 36 #include <linux/mfd/wm8994/gpio.h> 37 38 #include "wm8994.h" 39 #include "wm_hubs.h" 40 41 #define WM1811_JACKDET_MODE_NONE 0x0000 42 #define WM1811_JACKDET_MODE_JACK 0x0100 43 #define WM1811_JACKDET_MODE_MIC 0x0080 44 #define WM1811_JACKDET_MODE_AUDIO 0x0180 45 46 #define WM8994_NUM_DRC 3 47 #define WM8994_NUM_EQ 3 48 49 static struct { 50 unsigned int reg; 51 unsigned int mask; 52 } wm8994_vu_bits[] = { 53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 63 64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 80 }; 81 82 static int wm8994_drc_base[] = { 83 WM8994_AIF1_DRC1_1, 84 WM8994_AIF1_DRC2_1, 85 WM8994_AIF2_DRC_1, 86 }; 87 88 static int wm8994_retune_mobile_base[] = { 89 WM8994_AIF1_DAC1_EQ_GAINS_1, 90 WM8994_AIF1_DAC2_EQ_GAINS_1, 91 WM8994_AIF2_EQ_GAINS_1, 92 }; 93 94 static const struct wm8958_micd_rate micdet_rates[] = { 95 { 32768, true, 1, 4 }, 96 { 32768, false, 1, 1 }, 97 { 44100 * 256, true, 7, 10 }, 98 { 44100 * 256, false, 7, 10 }, 99 }; 100 101 static const struct wm8958_micd_rate jackdet_rates[] = { 102 { 32768, true, 0, 1 }, 103 { 32768, false, 0, 1 }, 104 { 44100 * 256, true, 10, 10 }, 105 { 44100 * 256, false, 7, 8 }, 106 }; 107 108 static void wm8958_micd_set_rate(struct snd_soc_codec *codec) 109 { 110 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 111 struct wm8994 *control = wm8994->wm8994; 112 int best, i, sysclk, val; 113 bool idle; 114 const struct wm8958_micd_rate *rates; 115 int num_rates; 116 117 idle = !wm8994->jack_mic; 118 119 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1); 120 if (sysclk & WM8994_SYSCLK_SRC) 121 sysclk = wm8994->aifclk[1]; 122 else 123 sysclk = wm8994->aifclk[0]; 124 125 if (control->pdata.micd_rates) { 126 rates = control->pdata.micd_rates; 127 num_rates = control->pdata.num_micd_rates; 128 } else if (wm8994->jackdet) { 129 rates = jackdet_rates; 130 num_rates = ARRAY_SIZE(jackdet_rates); 131 } else { 132 rates = micdet_rates; 133 num_rates = ARRAY_SIZE(micdet_rates); 134 } 135 136 best = 0; 137 for (i = 0; i < num_rates; i++) { 138 if (rates[i].idle != idle) 139 continue; 140 if (abs(rates[i].sysclk - sysclk) < 141 abs(rates[best].sysclk - sysclk)) 142 best = i; 143 else if (rates[best].idle != idle) 144 best = i; 145 } 146 147 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 148 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 149 150 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n", 151 rates[best].start, rates[best].rate, sysclk, 152 idle ? "idle" : "active"); 153 154 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 155 WM8958_MICD_BIAS_STARTTIME_MASK | 156 WM8958_MICD_RATE_MASK, val); 157 } 158 159 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 160 { 161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 162 int rate; 163 int reg1 = 0; 164 int offset; 165 166 if (aif) 167 offset = 4; 168 else 169 offset = 0; 170 171 switch (wm8994->sysclk[aif]) { 172 case WM8994_SYSCLK_MCLK1: 173 rate = wm8994->mclk[0]; 174 break; 175 176 case WM8994_SYSCLK_MCLK2: 177 reg1 |= 0x8; 178 rate = wm8994->mclk[1]; 179 break; 180 181 case WM8994_SYSCLK_FLL1: 182 reg1 |= 0x10; 183 rate = wm8994->fll[0].out; 184 break; 185 186 case WM8994_SYSCLK_FLL2: 187 reg1 |= 0x18; 188 rate = wm8994->fll[1].out; 189 break; 190 191 default: 192 return -EINVAL; 193 } 194 195 if (rate >= 13500000) { 196 rate /= 2; 197 reg1 |= WM8994_AIF1CLK_DIV; 198 199 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 200 aif + 1, rate); 201 } 202 203 wm8994->aifclk[aif] = rate; 204 205 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 206 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 207 reg1); 208 209 return 0; 210 } 211 212 static int configure_clock(struct snd_soc_codec *codec) 213 { 214 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 215 int change, new; 216 217 /* Bring up the AIF clocks first */ 218 configure_aif_clock(codec, 0); 219 configure_aif_clock(codec, 1); 220 221 /* Then switch CLK_SYS over to the higher of them; a change 222 * can only happen as a result of a clocking change which can 223 * only be made outside of DAPM so we can safely redo the 224 * clocking. 225 */ 226 227 /* If they're equal it doesn't matter which is used */ 228 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 229 wm8958_micd_set_rate(codec); 230 return 0; 231 } 232 233 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 234 new = WM8994_SYSCLK_SRC; 235 else 236 new = 0; 237 238 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1, 239 WM8994_SYSCLK_SRC, new); 240 if (change) 241 snd_soc_dapm_sync(&codec->dapm); 242 243 wm8958_micd_set_rate(codec); 244 245 return 0; 246 } 247 248 static int check_clk_sys(struct snd_soc_dapm_widget *source, 249 struct snd_soc_dapm_widget *sink) 250 { 251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 252 const char *clk; 253 254 /* Check what we're currently using for CLK_SYS */ 255 if (reg & WM8994_SYSCLK_SRC) 256 clk = "AIF2CLK"; 257 else 258 clk = "AIF1CLK"; 259 260 return strcmp(source->name, clk) == 0; 261 } 262 263 static const char *sidetone_hpf_text[] = { 264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 265 }; 266 267 static const struct soc_enum sidetone_hpf = 268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 269 270 static const char *adc_hpf_text[] = { 271 "HiFi", "Voice 1", "Voice 2", "Voice 3" 272 }; 273 274 static const struct soc_enum aif1adc1_hpf = 275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 276 277 static const struct soc_enum aif1adc2_hpf = 278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 279 280 static const struct soc_enum aif2adc_hpf = 281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 282 283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 288 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 289 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); 290 291 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 292 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 294 .put = wm8994_put_drc_sw, \ 295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 296 297 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 298 struct snd_ctl_elem_value *ucontrol) 299 { 300 struct soc_mixer_control *mc = 301 (struct soc_mixer_control *)kcontrol->private_value; 302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 303 int mask, ret; 304 305 /* Can't enable both ADC and DAC paths simultaneously */ 306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 308 WM8994_AIF1ADC1R_DRC_ENA_MASK; 309 else 310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 311 312 ret = snd_soc_read(codec, mc->reg); 313 if (ret < 0) 314 return ret; 315 if (ret & mask) 316 return -EINVAL; 317 318 return snd_soc_put_volsw(kcontrol, ucontrol); 319 } 320 321 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 322 { 323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 324 struct wm8994 *control = wm8994->wm8994; 325 struct wm8994_pdata *pdata = &control->pdata; 326 int base = wm8994_drc_base[drc]; 327 int cfg = wm8994->drc_cfg[drc]; 328 int save, i; 329 330 /* Save any enables; the configuration should clear them. */ 331 save = snd_soc_read(codec, base); 332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 333 WM8994_AIF1ADC1R_DRC_ENA; 334 335 for (i = 0; i < WM8994_DRC_REGS; i++) 336 snd_soc_update_bits(codec, base + i, 0xffff, 337 pdata->drc_cfgs[cfg].regs[i]); 338 339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 340 WM8994_AIF1ADC1L_DRC_ENA | 341 WM8994_AIF1ADC1R_DRC_ENA, save); 342 } 343 344 /* Icky as hell but saves code duplication */ 345 static int wm8994_get_drc(const char *name) 346 { 347 if (strcmp(name, "AIF1DRC1 Mode") == 0) 348 return 0; 349 if (strcmp(name, "AIF1DRC2 Mode") == 0) 350 return 1; 351 if (strcmp(name, "AIF2DRC Mode") == 0) 352 return 2; 353 return -EINVAL; 354 } 355 356 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 357 struct snd_ctl_elem_value *ucontrol) 358 { 359 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 361 struct wm8994 *control = wm8994->wm8994; 362 struct wm8994_pdata *pdata = &control->pdata; 363 int drc = wm8994_get_drc(kcontrol->id.name); 364 int value = ucontrol->value.integer.value[0]; 365 366 if (drc < 0) 367 return drc; 368 369 if (value >= pdata->num_drc_cfgs) 370 return -EINVAL; 371 372 wm8994->drc_cfg[drc] = value; 373 374 wm8994_set_drc(codec, drc); 375 376 return 0; 377 } 378 379 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 380 struct snd_ctl_elem_value *ucontrol) 381 { 382 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 384 int drc = wm8994_get_drc(kcontrol->id.name); 385 386 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 387 388 return 0; 389 } 390 391 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 392 { 393 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 394 struct wm8994 *control = wm8994->wm8994; 395 struct wm8994_pdata *pdata = &control->pdata; 396 int base = wm8994_retune_mobile_base[block]; 397 int iface, best, best_val, save, i, cfg; 398 399 if (!pdata || !wm8994->num_retune_mobile_texts) 400 return; 401 402 switch (block) { 403 case 0: 404 case 1: 405 iface = 0; 406 break; 407 case 2: 408 iface = 1; 409 break; 410 default: 411 return; 412 } 413 414 /* Find the version of the currently selected configuration 415 * with the nearest sample rate. */ 416 cfg = wm8994->retune_mobile_cfg[block]; 417 best = 0; 418 best_val = INT_MAX; 419 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 420 if (strcmp(pdata->retune_mobile_cfgs[i].name, 421 wm8994->retune_mobile_texts[cfg]) == 0 && 422 abs(pdata->retune_mobile_cfgs[i].rate 423 - wm8994->dac_rates[iface]) < best_val) { 424 best = i; 425 best_val = abs(pdata->retune_mobile_cfgs[i].rate 426 - wm8994->dac_rates[iface]); 427 } 428 } 429 430 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 431 block, 432 pdata->retune_mobile_cfgs[best].name, 433 pdata->retune_mobile_cfgs[best].rate, 434 wm8994->dac_rates[iface]); 435 436 /* The EQ will be disabled while reconfiguring it, remember the 437 * current configuration. 438 */ 439 save = snd_soc_read(codec, base); 440 save &= WM8994_AIF1DAC1_EQ_ENA; 441 442 for (i = 0; i < WM8994_EQ_REGS; i++) 443 snd_soc_update_bits(codec, base + i, 0xffff, 444 pdata->retune_mobile_cfgs[best].regs[i]); 445 446 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 447 } 448 449 /* Icky as hell but saves code duplication */ 450 static int wm8994_get_retune_mobile_block(const char *name) 451 { 452 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 453 return 0; 454 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 455 return 1; 456 if (strcmp(name, "AIF2 EQ Mode") == 0) 457 return 2; 458 return -EINVAL; 459 } 460 461 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 462 struct snd_ctl_elem_value *ucontrol) 463 { 464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 466 struct wm8994 *control = wm8994->wm8994; 467 struct wm8994_pdata *pdata = &control->pdata; 468 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 469 int value = ucontrol->value.integer.value[0]; 470 471 if (block < 0) 472 return block; 473 474 if (value >= pdata->num_retune_mobile_cfgs) 475 return -EINVAL; 476 477 wm8994->retune_mobile_cfg[block] = value; 478 479 wm8994_set_retune_mobile(codec, block); 480 481 return 0; 482 } 483 484 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 485 struct snd_ctl_elem_value *ucontrol) 486 { 487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 488 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 489 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 490 491 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 492 493 return 0; 494 } 495 496 static const char *aif_chan_src_text[] = { 497 "Left", "Right" 498 }; 499 500 static const struct soc_enum aif1adcl_src = 501 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 502 503 static const struct soc_enum aif1adcr_src = 504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 505 506 static const struct soc_enum aif2adcl_src = 507 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 508 509 static const struct soc_enum aif2adcr_src = 510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 511 512 static const struct soc_enum aif1dacl_src = 513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 514 515 static const struct soc_enum aif1dacr_src = 516 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 517 518 static const struct soc_enum aif2dacl_src = 519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 520 521 static const struct soc_enum aif2dacr_src = 522 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 523 524 static const char *osr_text[] = { 525 "Low Power", "High Performance", 526 }; 527 528 static const struct soc_enum dac_osr = 529 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 530 531 static const struct soc_enum adc_osr = 532 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 533 534 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 535 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 536 WM8994_AIF1_ADC1_RIGHT_VOLUME, 537 1, 119, 0, digital_tlv), 538 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 539 WM8994_AIF1_ADC2_RIGHT_VOLUME, 540 1, 119, 0, digital_tlv), 541 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 542 WM8994_AIF2_ADC_RIGHT_VOLUME, 543 1, 119, 0, digital_tlv), 544 545 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 546 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 547 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 548 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 549 550 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 551 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 552 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 553 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 554 555 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 556 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 557 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 558 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 559 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 560 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 561 562 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 563 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 564 565 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 566 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 567 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 568 569 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 570 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 571 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 572 573 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 574 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 575 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 576 577 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 578 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 579 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 580 581 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 582 5, 12, 0, st_tlv), 583 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 584 0, 12, 0, st_tlv), 585 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 586 5, 12, 0, st_tlv), 587 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 588 0, 12, 0, st_tlv), 589 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 590 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 591 592 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 593 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 594 595 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 596 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 597 598 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 599 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 600 601 SOC_ENUM("ADC OSR", adc_osr), 602 SOC_ENUM("DAC OSR", dac_osr), 603 604 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 605 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 606 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 607 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 608 609 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 610 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 611 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 612 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 613 614 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 615 6, 1, 1, wm_hubs_spkmix_tlv), 616 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 617 2, 1, 1, wm_hubs_spkmix_tlv), 618 619 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 620 6, 1, 1, wm_hubs_spkmix_tlv), 621 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 622 2, 1, 1, wm_hubs_spkmix_tlv), 623 624 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 625 10, 15, 0, wm8994_3d_tlv), 626 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 627 8, 1, 0), 628 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 629 10, 15, 0, wm8994_3d_tlv), 630 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 631 8, 1, 0), 632 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 633 10, 15, 0, wm8994_3d_tlv), 634 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 635 8, 1, 0), 636 }; 637 638 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 639 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 640 eq_tlv), 641 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 642 eq_tlv), 643 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 644 eq_tlv), 645 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 646 eq_tlv), 647 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 648 eq_tlv), 649 650 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 651 eq_tlv), 652 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 653 eq_tlv), 654 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 655 eq_tlv), 656 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 659 eq_tlv), 660 661 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 662 eq_tlv), 663 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 664 eq_tlv), 665 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 666 eq_tlv), 667 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 670 eq_tlv), 671 }; 672 673 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 674 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 675 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 676 WM8994_AIF1ADC1R_DRC_ENA), 677 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 678 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 679 WM8994_AIF1ADC2R_DRC_ENA), 680 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 681 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 682 WM8994_AIF2ADCR_DRC_ENA), 683 }; 684 685 static const char *wm8958_ng_text[] = { 686 "30ms", "125ms", "250ms", "500ms", 687 }; 688 689 static const struct soc_enum wm8958_aif1dac1_ng_hold = 690 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE, 691 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text); 692 693 static const struct soc_enum wm8958_aif1dac2_ng_hold = 694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE, 695 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text); 696 697 static const struct soc_enum wm8958_aif2dac_ng_hold = 698 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE, 699 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text); 700 701 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 702 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 703 704 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 705 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 706 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 707 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 708 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 709 7, 1, ng_tlv), 710 711 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 712 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 713 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 714 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 715 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 716 7, 1, ng_tlv), 717 718 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 719 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 720 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 721 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 722 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 723 7, 1, ng_tlv), 724 }; 725 726 static const struct snd_kcontrol_new wm1811_snd_controls[] = { 727 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, 728 mixin_boost_tlv), 729 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, 730 mixin_boost_tlv), 731 }; 732 733 /* We run all mode setting through a function to enforce audio mode */ 734 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode) 735 { 736 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 737 738 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 739 return; 740 741 if (wm8994->active_refcount) 742 mode = WM1811_JACKDET_MODE_AUDIO; 743 744 if (mode == wm8994->jackdet_mode) 745 return; 746 747 wm8994->jackdet_mode = mode; 748 749 /* Always use audio mode to detect while the system is active */ 750 if (mode != WM1811_JACKDET_MODE_NONE) 751 mode = WM1811_JACKDET_MODE_AUDIO; 752 753 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 754 WM1811_JACKDET_MODE_MASK, mode); 755 } 756 757 static void active_reference(struct snd_soc_codec *codec) 758 { 759 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 760 761 mutex_lock(&wm8994->accdet_lock); 762 763 wm8994->active_refcount++; 764 765 dev_dbg(codec->dev, "Active refcount incremented, now %d\n", 766 wm8994->active_refcount); 767 768 /* If we're using jack detection go into audio mode */ 769 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO); 770 771 mutex_unlock(&wm8994->accdet_lock); 772 } 773 774 static void active_dereference(struct snd_soc_codec *codec) 775 { 776 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 777 u16 mode; 778 779 mutex_lock(&wm8994->accdet_lock); 780 781 wm8994->active_refcount--; 782 783 dev_dbg(codec->dev, "Active refcount decremented, now %d\n", 784 wm8994->active_refcount); 785 786 if (wm8994->active_refcount == 0) { 787 /* Go into appropriate detection only mode */ 788 if (wm8994->jack_mic || wm8994->mic_detecting) 789 mode = WM1811_JACKDET_MODE_MIC; 790 else 791 mode = WM1811_JACKDET_MODE_JACK; 792 793 wm1811_jackdet_set_mode(codec, mode); 794 } 795 796 mutex_unlock(&wm8994->accdet_lock); 797 } 798 799 static int clk_sys_event(struct snd_soc_dapm_widget *w, 800 struct snd_kcontrol *kcontrol, int event) 801 { 802 struct snd_soc_codec *codec = w->codec; 803 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 804 805 switch (event) { 806 case SND_SOC_DAPM_PRE_PMU: 807 return configure_clock(codec); 808 809 case SND_SOC_DAPM_POST_PMU: 810 /* 811 * JACKDET won't run until we start the clock and it 812 * only reports deltas, make sure we notify the state 813 * up the stack on startup. Use a *very* generous 814 * timeout for paranoia, there's no urgency and we 815 * don't want false reports. 816 */ 817 if (wm8994->jackdet && !wm8994->clk_has_run) { 818 schedule_delayed_work(&wm8994->jackdet_bootstrap, 819 msecs_to_jiffies(1000)); 820 wm8994->clk_has_run = true; 821 } 822 break; 823 824 case SND_SOC_DAPM_POST_PMD: 825 configure_clock(codec); 826 break; 827 } 828 829 return 0; 830 } 831 832 static void vmid_reference(struct snd_soc_codec *codec) 833 { 834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 835 836 pm_runtime_get_sync(codec->dev); 837 838 wm8994->vmid_refcount++; 839 840 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", 841 wm8994->vmid_refcount); 842 843 if (wm8994->vmid_refcount == 1) { 844 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 845 WM8994_LINEOUT1_DISCH | 846 WM8994_LINEOUT2_DISCH, 0); 847 848 wm_hubs_vmid_ena(codec); 849 850 switch (wm8994->vmid_mode) { 851 default: 852 WARN_ON(NULL == "Invalid VMID mode"); 853 case WM8994_VMID_NORMAL: 854 /* Startup bias, VMID ramp & buffer */ 855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 856 WM8994_BIAS_SRC | 857 WM8994_VMID_DISCH | 858 WM8994_STARTUP_BIAS_ENA | 859 WM8994_VMID_BUF_ENA | 860 WM8994_VMID_RAMP_MASK, 861 WM8994_BIAS_SRC | 862 WM8994_STARTUP_BIAS_ENA | 863 WM8994_VMID_BUF_ENA | 864 (0x2 << WM8994_VMID_RAMP_SHIFT)); 865 866 /* Main bias enable, VMID=2x40k */ 867 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 868 WM8994_BIAS_ENA | 869 WM8994_VMID_SEL_MASK, 870 WM8994_BIAS_ENA | 0x2); 871 872 msleep(300); 873 874 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 875 WM8994_VMID_RAMP_MASK | 876 WM8994_BIAS_SRC, 877 0); 878 break; 879 880 case WM8994_VMID_FORCE: 881 /* Startup bias, slow VMID ramp & buffer */ 882 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 883 WM8994_BIAS_SRC | 884 WM8994_VMID_DISCH | 885 WM8994_STARTUP_BIAS_ENA | 886 WM8994_VMID_BUF_ENA | 887 WM8994_VMID_RAMP_MASK, 888 WM8994_BIAS_SRC | 889 WM8994_STARTUP_BIAS_ENA | 890 WM8994_VMID_BUF_ENA | 891 (0x2 << WM8994_VMID_RAMP_SHIFT)); 892 893 /* Main bias enable, VMID=2x40k */ 894 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 895 WM8994_BIAS_ENA | 896 WM8994_VMID_SEL_MASK, 897 WM8994_BIAS_ENA | 0x2); 898 899 msleep(400); 900 901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 902 WM8994_VMID_RAMP_MASK | 903 WM8994_BIAS_SRC, 904 0); 905 break; 906 } 907 } 908 } 909 910 static void vmid_dereference(struct snd_soc_codec *codec) 911 { 912 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 913 914 wm8994->vmid_refcount--; 915 916 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", 917 wm8994->vmid_refcount); 918 919 if (wm8994->vmid_refcount == 0) { 920 if (wm8994->hubs.lineout1_se) 921 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 922 WM8994_LINEOUT1N_ENA | 923 WM8994_LINEOUT1P_ENA, 924 WM8994_LINEOUT1N_ENA | 925 WM8994_LINEOUT1P_ENA); 926 927 if (wm8994->hubs.lineout2_se) 928 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 929 WM8994_LINEOUT2N_ENA | 930 WM8994_LINEOUT2P_ENA, 931 WM8994_LINEOUT2N_ENA | 932 WM8994_LINEOUT2P_ENA); 933 934 /* Start discharging VMID */ 935 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 936 WM8994_BIAS_SRC | 937 WM8994_VMID_DISCH, 938 WM8994_BIAS_SRC | 939 WM8994_VMID_DISCH); 940 941 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 942 WM8994_VMID_SEL_MASK, 0); 943 944 msleep(400); 945 946 /* Active discharge */ 947 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 948 WM8994_LINEOUT1_DISCH | 949 WM8994_LINEOUT2_DISCH, 950 WM8994_LINEOUT1_DISCH | 951 WM8994_LINEOUT2_DISCH); 952 953 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 954 WM8994_LINEOUT1N_ENA | 955 WM8994_LINEOUT1P_ENA | 956 WM8994_LINEOUT2N_ENA | 957 WM8994_LINEOUT2P_ENA, 0); 958 959 /* Switch off startup biases */ 960 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 961 WM8994_BIAS_SRC | 962 WM8994_STARTUP_BIAS_ENA | 963 WM8994_VMID_BUF_ENA | 964 WM8994_VMID_RAMP_MASK, 0); 965 966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 967 WM8994_VMID_SEL_MASK, 0); 968 } 969 970 pm_runtime_put(codec->dev); 971 } 972 973 static int vmid_event(struct snd_soc_dapm_widget *w, 974 struct snd_kcontrol *kcontrol, int event) 975 { 976 struct snd_soc_codec *codec = w->codec; 977 978 switch (event) { 979 case SND_SOC_DAPM_PRE_PMU: 980 vmid_reference(codec); 981 break; 982 983 case SND_SOC_DAPM_POST_PMD: 984 vmid_dereference(codec); 985 break; 986 } 987 988 return 0; 989 } 990 991 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec) 992 { 993 int source = 0; /* GCC flow analysis can't track enable */ 994 int reg, reg_r; 995 996 /* We also need the same AIF source for L/R and only one path */ 997 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 998 switch (reg) { 999 case WM8994_AIF2DACL_TO_DAC1L: 1000 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 1001 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1002 break; 1003 case WM8994_AIF1DAC2L_TO_DAC1L: 1004 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 1005 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1006 break; 1007 case WM8994_AIF1DAC1L_TO_DAC1L: 1008 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 1009 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1010 break; 1011 default: 1012 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 1013 return false; 1014 } 1015 1016 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1017 if (reg_r != reg) { 1018 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 1019 return false; 1020 } 1021 1022 /* Set the source up */ 1023 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1024 WM8994_CP_DYN_SRC_SEL_MASK, source); 1025 1026 return true; 1027 } 1028 1029 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1030 struct snd_kcontrol *kcontrol, int event) 1031 { 1032 struct snd_soc_codec *codec = w->codec; 1033 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1034 struct wm8994 *control = codec->control_data; 1035 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1036 int i; 1037 int dac; 1038 int adc; 1039 int val; 1040 1041 switch (control->type) { 1042 case WM8994: 1043 case WM8958: 1044 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1045 break; 1046 default: 1047 break; 1048 } 1049 1050 switch (event) { 1051 case SND_SOC_DAPM_PRE_PMU: 1052 /* Don't enable timeslot 2 if not in use */ 1053 if (wm8994->channels[0] <= 2) 1054 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1055 1056 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1); 1057 if ((val & WM8994_AIF1ADCL_SRC) && 1058 (val & WM8994_AIF1ADCR_SRC)) 1059 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1060 else if (!(val & WM8994_AIF1ADCL_SRC) && 1061 !(val & WM8994_AIF1ADCR_SRC)) 1062 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1063 else 1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1065 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1066 1067 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2); 1068 if ((val & WM8994_AIF1DACL_SRC) && 1069 (val & WM8994_AIF1DACR_SRC)) 1070 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1071 else if (!(val & WM8994_AIF1DACL_SRC) && 1072 !(val & WM8994_AIF1DACR_SRC)) 1073 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1074 else 1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1076 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1077 1078 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1079 mask, adc); 1080 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1081 mask, dac); 1082 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1083 WM8994_AIF1DSPCLK_ENA | 1084 WM8994_SYSDSPCLK_ENA, 1085 WM8994_AIF1DSPCLK_ENA | 1086 WM8994_SYSDSPCLK_ENA); 1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask, 1088 WM8994_AIF1ADC1R_ENA | 1089 WM8994_AIF1ADC1L_ENA | 1090 WM8994_AIF1ADC2R_ENA | 1091 WM8994_AIF1ADC2L_ENA); 1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask, 1093 WM8994_AIF1DAC1R_ENA | 1094 WM8994_AIF1DAC1L_ENA | 1095 WM8994_AIF1DAC2R_ENA | 1096 WM8994_AIF1DAC2L_ENA); 1097 break; 1098 1099 case SND_SOC_DAPM_POST_PMU: 1100 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1101 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1102 snd_soc_read(codec, 1103 wm8994_vu_bits[i].reg)); 1104 break; 1105 1106 case SND_SOC_DAPM_PRE_PMD: 1107 case SND_SOC_DAPM_POST_PMD: 1108 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1109 mask, 0); 1110 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1111 mask, 0); 1112 1113 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1114 if (val & WM8994_AIF2DSPCLK_ENA) 1115 val = WM8994_SYSDSPCLK_ENA; 1116 else 1117 val = 0; 1118 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1119 WM8994_SYSDSPCLK_ENA | 1120 WM8994_AIF1DSPCLK_ENA, val); 1121 break; 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1128 struct snd_kcontrol *kcontrol, int event) 1129 { 1130 struct snd_soc_codec *codec = w->codec; 1131 int i; 1132 int dac; 1133 int adc; 1134 int val; 1135 1136 switch (event) { 1137 case SND_SOC_DAPM_PRE_PMU: 1138 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1); 1139 if ((val & WM8994_AIF2ADCL_SRC) && 1140 (val & WM8994_AIF2ADCR_SRC)) 1141 adc = WM8994_AIF2ADCR_ENA; 1142 else if (!(val & WM8994_AIF2ADCL_SRC) && 1143 !(val & WM8994_AIF2ADCR_SRC)) 1144 adc = WM8994_AIF2ADCL_ENA; 1145 else 1146 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1147 1148 1149 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2); 1150 if ((val & WM8994_AIF2DACL_SRC) && 1151 (val & WM8994_AIF2DACR_SRC)) 1152 dac = WM8994_AIF2DACR_ENA; 1153 else if (!(val & WM8994_AIF2DACL_SRC) && 1154 !(val & WM8994_AIF2DACR_SRC)) 1155 dac = WM8994_AIF2DACL_ENA; 1156 else 1157 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1158 1159 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1160 WM8994_AIF2ADCL_ENA | 1161 WM8994_AIF2ADCR_ENA, adc); 1162 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1163 WM8994_AIF2DACL_ENA | 1164 WM8994_AIF2DACR_ENA, dac); 1165 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1166 WM8994_AIF2DSPCLK_ENA | 1167 WM8994_SYSDSPCLK_ENA, 1168 WM8994_AIF2DSPCLK_ENA | 1169 WM8994_SYSDSPCLK_ENA); 1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1171 WM8994_AIF2ADCL_ENA | 1172 WM8994_AIF2ADCR_ENA, 1173 WM8994_AIF2ADCL_ENA | 1174 WM8994_AIF2ADCR_ENA); 1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1176 WM8994_AIF2DACL_ENA | 1177 WM8994_AIF2DACR_ENA, 1178 WM8994_AIF2DACL_ENA | 1179 WM8994_AIF2DACR_ENA); 1180 break; 1181 1182 case SND_SOC_DAPM_POST_PMU: 1183 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1184 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1185 snd_soc_read(codec, 1186 wm8994_vu_bits[i].reg)); 1187 break; 1188 1189 case SND_SOC_DAPM_PRE_PMD: 1190 case SND_SOC_DAPM_POST_PMD: 1191 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1192 WM8994_AIF2DACL_ENA | 1193 WM8994_AIF2DACR_ENA, 0); 1194 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1195 WM8994_AIF2ADCL_ENA | 1196 WM8994_AIF2ADCR_ENA, 0); 1197 1198 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1199 if (val & WM8994_AIF1DSPCLK_ENA) 1200 val = WM8994_SYSDSPCLK_ENA; 1201 else 1202 val = 0; 1203 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1204 WM8994_SYSDSPCLK_ENA | 1205 WM8994_AIF2DSPCLK_ENA, val); 1206 break; 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1213 struct snd_kcontrol *kcontrol, int event) 1214 { 1215 struct snd_soc_codec *codec = w->codec; 1216 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1217 1218 switch (event) { 1219 case SND_SOC_DAPM_PRE_PMU: 1220 wm8994->aif1clk_enable = 1; 1221 break; 1222 case SND_SOC_DAPM_POST_PMD: 1223 wm8994->aif1clk_disable = 1; 1224 break; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1231 struct snd_kcontrol *kcontrol, int event) 1232 { 1233 struct snd_soc_codec *codec = w->codec; 1234 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1235 1236 switch (event) { 1237 case SND_SOC_DAPM_PRE_PMU: 1238 wm8994->aif2clk_enable = 1; 1239 break; 1240 case SND_SOC_DAPM_POST_PMD: 1241 wm8994->aif2clk_disable = 1; 1242 break; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1249 struct snd_kcontrol *kcontrol, int event) 1250 { 1251 struct snd_soc_codec *codec = w->codec; 1252 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1253 1254 switch (event) { 1255 case SND_SOC_DAPM_PRE_PMU: 1256 if (wm8994->aif1clk_enable) { 1257 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1258 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1259 WM8994_AIF1CLK_ENA_MASK, 1260 WM8994_AIF1CLK_ENA); 1261 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1262 wm8994->aif1clk_enable = 0; 1263 } 1264 if (wm8994->aif2clk_enable) { 1265 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1266 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1267 WM8994_AIF2CLK_ENA_MASK, 1268 WM8994_AIF2CLK_ENA); 1269 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1270 wm8994->aif2clk_enable = 0; 1271 } 1272 break; 1273 } 1274 1275 /* We may also have postponed startup of DSP, handle that. */ 1276 wm8958_aif_ev(w, kcontrol, event); 1277 1278 return 0; 1279 } 1280 1281 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1282 struct snd_kcontrol *kcontrol, int event) 1283 { 1284 struct snd_soc_codec *codec = w->codec; 1285 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1286 1287 switch (event) { 1288 case SND_SOC_DAPM_POST_PMD: 1289 if (wm8994->aif1clk_disable) { 1290 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1291 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1292 WM8994_AIF1CLK_ENA_MASK, 0); 1293 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1294 wm8994->aif1clk_disable = 0; 1295 } 1296 if (wm8994->aif2clk_disable) { 1297 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1298 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1299 WM8994_AIF2CLK_ENA_MASK, 0); 1300 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1301 wm8994->aif2clk_disable = 0; 1302 } 1303 break; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1310 struct snd_kcontrol *kcontrol, int event) 1311 { 1312 late_enable_ev(w, kcontrol, event); 1313 return 0; 1314 } 1315 1316 static int micbias_ev(struct snd_soc_dapm_widget *w, 1317 struct snd_kcontrol *kcontrol, int event) 1318 { 1319 late_enable_ev(w, kcontrol, event); 1320 return 0; 1321 } 1322 1323 static int dac_ev(struct snd_soc_dapm_widget *w, 1324 struct snd_kcontrol *kcontrol, int event) 1325 { 1326 struct snd_soc_codec *codec = w->codec; 1327 unsigned int mask = 1 << w->shift; 1328 1329 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1330 mask, mask); 1331 return 0; 1332 } 1333 1334 static const char *adc_mux_text[] = { 1335 "ADC", 1336 "DMIC", 1337 }; 1338 1339 static const struct soc_enum adc_enum = 1340 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 1341 1342 static const struct snd_kcontrol_new adcl_mux = 1343 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1344 1345 static const struct snd_kcontrol_new adcr_mux = 1346 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1347 1348 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1349 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1350 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1351 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1352 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1353 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1354 }; 1355 1356 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1357 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1358 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1359 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1360 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1361 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1362 }; 1363 1364 /* Debugging; dump chip status after DAPM transitions */ 1365 static int post_ev(struct snd_soc_dapm_widget *w, 1366 struct snd_kcontrol *kcontrol, int event) 1367 { 1368 struct snd_soc_codec *codec = w->codec; 1369 dev_dbg(codec->dev, "SRC status: %x\n", 1370 snd_soc_read(codec, 1371 WM8994_RATE_STATUS)); 1372 return 0; 1373 } 1374 1375 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1376 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1377 1, 1, 0), 1378 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1379 0, 1, 0), 1380 }; 1381 1382 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1383 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1384 1, 1, 0), 1385 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1386 0, 1, 0), 1387 }; 1388 1389 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1390 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1391 1, 1, 0), 1392 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1393 0, 1, 0), 1394 }; 1395 1396 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1397 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1398 1, 1, 0), 1399 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1400 0, 1, 0), 1401 }; 1402 1403 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1404 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1405 5, 1, 0), 1406 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1407 4, 1, 0), 1408 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1409 2, 1, 0), 1410 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1411 1, 1, 0), 1412 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1413 0, 1, 0), 1414 }; 1415 1416 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1417 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1418 5, 1, 0), 1419 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1420 4, 1, 0), 1421 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1422 2, 1, 0), 1423 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1424 1, 1, 0), 1425 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1426 0, 1, 0), 1427 }; 1428 1429 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1430 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1431 .info = snd_soc_info_volsw, \ 1432 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 1433 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 1434 1435 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1436 struct snd_ctl_elem_value *ucontrol) 1437 { 1438 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 1439 struct snd_soc_dapm_widget *w = wlist->widgets[0]; 1440 struct snd_soc_codec *codec = w->codec; 1441 int ret; 1442 1443 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1444 1445 wm_hubs_update_class_w(codec); 1446 1447 return ret; 1448 } 1449 1450 static const struct snd_kcontrol_new dac1l_mix[] = { 1451 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1452 5, 1, 0), 1453 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1454 4, 1, 0), 1455 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1456 2, 1, 0), 1457 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1458 1, 1, 0), 1459 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1460 0, 1, 0), 1461 }; 1462 1463 static const struct snd_kcontrol_new dac1r_mix[] = { 1464 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1465 5, 1, 0), 1466 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1467 4, 1, 0), 1468 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1469 2, 1, 0), 1470 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1471 1, 1, 0), 1472 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1473 0, 1, 0), 1474 }; 1475 1476 static const char *sidetone_text[] = { 1477 "ADC/DMIC1", "DMIC2", 1478 }; 1479 1480 static const struct soc_enum sidetone1_enum = 1481 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1482 1483 static const struct snd_kcontrol_new sidetone1_mux = 1484 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1485 1486 static const struct soc_enum sidetone2_enum = 1487 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1488 1489 static const struct snd_kcontrol_new sidetone2_mux = 1490 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1491 1492 static const char *aif1dac_text[] = { 1493 "AIF1DACDAT", "AIF3DACDAT", 1494 }; 1495 1496 static const struct soc_enum aif1dac_enum = 1497 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1498 1499 static const struct snd_kcontrol_new aif1dac_mux = 1500 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1501 1502 static const char *aif2dac_text[] = { 1503 "AIF2DACDAT", "AIF3DACDAT", 1504 }; 1505 1506 static const struct soc_enum aif2dac_enum = 1507 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1508 1509 static const struct snd_kcontrol_new aif2dac_mux = 1510 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1511 1512 static const char *aif2adc_text[] = { 1513 "AIF2ADCDAT", "AIF3DACDAT", 1514 }; 1515 1516 static const struct soc_enum aif2adc_enum = 1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1518 1519 static const struct snd_kcontrol_new aif2adc_mux = 1520 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1521 1522 static const char *aif3adc_text[] = { 1523 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1524 }; 1525 1526 static const struct soc_enum wm8994_aif3adc_enum = 1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1528 1529 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1530 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1531 1532 static const struct soc_enum wm8958_aif3adc_enum = 1533 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1534 1535 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1536 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1537 1538 static const char *mono_pcm_out_text[] = { 1539 "None", "AIF2ADCL", "AIF2ADCR", 1540 }; 1541 1542 static const struct soc_enum mono_pcm_out_enum = 1543 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1544 1545 static const struct snd_kcontrol_new mono_pcm_out_mux = 1546 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1547 1548 static const char *aif2dac_src_text[] = { 1549 "AIF2", "AIF3", 1550 }; 1551 1552 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1553 static const struct soc_enum aif2dacl_src_enum = 1554 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1555 1556 static const struct snd_kcontrol_new aif2dacl_src_mux = 1557 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1558 1559 static const struct soc_enum aif2dacr_src_enum = 1560 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1561 1562 static const struct snd_kcontrol_new aif2dacr_src_mux = 1563 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1564 1565 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1566 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1568 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1570 1571 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1573 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1575 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1577 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1578 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1579 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1580 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1581 1582 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1583 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1584 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1585 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1586 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1587 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1588 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1589 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1590 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1591 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1592 1593 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1594 }; 1595 1596 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1597 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1599 SND_SOC_DAPM_PRE_PMD), 1600 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1602 SND_SOC_DAPM_PRE_PMD), 1603 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1604 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1605 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1606 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1607 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1608 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1609 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1610 }; 1611 1612 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1613 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1614 dac_ev, SND_SOC_DAPM_PRE_PMU), 1615 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1616 dac_ev, SND_SOC_DAPM_PRE_PMU), 1617 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1618 dac_ev, SND_SOC_DAPM_PRE_PMU), 1619 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1620 dac_ev, SND_SOC_DAPM_PRE_PMU), 1621 }; 1622 1623 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1624 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1625 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1626 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1627 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1628 }; 1629 1630 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1631 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1632 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1633 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1634 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1635 }; 1636 1637 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1638 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1639 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1640 }; 1641 1642 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1643 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1644 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1645 SND_SOC_DAPM_INPUT("Clock"), 1646 1647 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1648 SND_SOC_DAPM_PRE_PMU), 1649 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1650 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1651 1652 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1653 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1654 SND_SOC_DAPM_PRE_PMD), 1655 1656 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1657 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1658 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1659 1660 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1661 0, SND_SOC_NOPM, 9, 0), 1662 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1663 0, SND_SOC_NOPM, 8, 0), 1664 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1665 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1666 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1667 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1668 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1669 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1670 1671 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1672 0, SND_SOC_NOPM, 11, 0), 1673 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1674 0, SND_SOC_NOPM, 10, 0), 1675 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1676 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1677 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1678 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1679 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1680 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1681 1682 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1683 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1684 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1685 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1686 1687 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1688 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1689 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1690 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1691 1692 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1693 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1694 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1695 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1696 1697 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1698 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1699 1700 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1701 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1702 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1703 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1704 1705 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1706 SND_SOC_NOPM, 13, 0), 1707 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1708 SND_SOC_NOPM, 12, 0), 1709 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1710 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1711 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1712 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1713 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1714 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1715 1716 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1717 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1718 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1719 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1720 1721 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1722 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1723 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1724 1725 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1726 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1727 1728 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1729 1730 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1731 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1732 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1733 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1734 1735 /* Power is done with the muxes since the ADC power also controls the 1736 * downsampling chain, the chip will automatically manage the analogue 1737 * specific portions. 1738 */ 1739 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1740 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1741 1742 SND_SOC_DAPM_POST("Debug log", post_ev), 1743 }; 1744 1745 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1746 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1747 }; 1748 1749 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1750 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1751 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1752 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1753 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1754 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1755 }; 1756 1757 static const struct snd_soc_dapm_route intercon[] = { 1758 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1759 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1760 1761 { "DSP1CLK", NULL, "CLK_SYS" }, 1762 { "DSP2CLK", NULL, "CLK_SYS" }, 1763 { "DSPINTCLK", NULL, "CLK_SYS" }, 1764 1765 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1766 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1767 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1768 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1769 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1770 1771 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1772 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1773 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1774 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1775 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1776 1777 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1778 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1779 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1780 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1781 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1782 1783 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1784 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1785 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1786 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1787 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1788 1789 { "AIF2ADCL", NULL, "AIF2CLK" }, 1790 { "AIF2ADCL", NULL, "DSP2CLK" }, 1791 { "AIF2ADCR", NULL, "AIF2CLK" }, 1792 { "AIF2ADCR", NULL, "DSP2CLK" }, 1793 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1794 1795 { "AIF2DACL", NULL, "AIF2CLK" }, 1796 { "AIF2DACL", NULL, "DSP2CLK" }, 1797 { "AIF2DACR", NULL, "AIF2CLK" }, 1798 { "AIF2DACR", NULL, "DSP2CLK" }, 1799 { "AIF2DACR", NULL, "DSPINTCLK" }, 1800 1801 { "DMIC1L", NULL, "DMIC1DAT" }, 1802 { "DMIC1L", NULL, "CLK_SYS" }, 1803 { "DMIC1R", NULL, "DMIC1DAT" }, 1804 { "DMIC1R", NULL, "CLK_SYS" }, 1805 { "DMIC2L", NULL, "DMIC2DAT" }, 1806 { "DMIC2L", NULL, "CLK_SYS" }, 1807 { "DMIC2R", NULL, "DMIC2DAT" }, 1808 { "DMIC2R", NULL, "CLK_SYS" }, 1809 1810 { "ADCL", NULL, "AIF1CLK" }, 1811 { "ADCL", NULL, "DSP1CLK" }, 1812 { "ADCL", NULL, "DSPINTCLK" }, 1813 1814 { "ADCR", NULL, "AIF1CLK" }, 1815 { "ADCR", NULL, "DSP1CLK" }, 1816 { "ADCR", NULL, "DSPINTCLK" }, 1817 1818 { "ADCL Mux", "ADC", "ADCL" }, 1819 { "ADCL Mux", "DMIC", "DMIC1L" }, 1820 { "ADCR Mux", "ADC", "ADCR" }, 1821 { "ADCR Mux", "DMIC", "DMIC1R" }, 1822 1823 { "DAC1L", NULL, "AIF1CLK" }, 1824 { "DAC1L", NULL, "DSP1CLK" }, 1825 { "DAC1L", NULL, "DSPINTCLK" }, 1826 1827 { "DAC1R", NULL, "AIF1CLK" }, 1828 { "DAC1R", NULL, "DSP1CLK" }, 1829 { "DAC1R", NULL, "DSPINTCLK" }, 1830 1831 { "DAC2L", NULL, "AIF2CLK" }, 1832 { "DAC2L", NULL, "DSP2CLK" }, 1833 { "DAC2L", NULL, "DSPINTCLK" }, 1834 1835 { "DAC2R", NULL, "AIF2DACR" }, 1836 { "DAC2R", NULL, "AIF2CLK" }, 1837 { "DAC2R", NULL, "DSP2CLK" }, 1838 { "DAC2R", NULL, "DSPINTCLK" }, 1839 1840 { "TOCLK", NULL, "CLK_SYS" }, 1841 1842 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1843 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1844 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1845 1846 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1847 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1848 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1849 1850 /* AIF1 outputs */ 1851 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1852 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1853 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1854 1855 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1856 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1857 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1858 1859 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1860 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1861 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1862 1863 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1864 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1865 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1866 1867 /* Pin level routing for AIF3 */ 1868 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1869 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1870 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1871 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1872 1873 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1874 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1875 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1876 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1877 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1879 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1880 1881 /* DAC1 inputs */ 1882 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1883 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1884 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1885 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1886 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1887 1888 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1889 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1890 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1891 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1892 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1893 1894 /* DAC2/AIF2 outputs */ 1895 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1896 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1897 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1898 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1899 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1900 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1901 1902 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1903 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1904 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1905 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1906 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1907 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1908 1909 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1910 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1911 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1912 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1913 1914 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1915 1916 /* AIF3 output */ 1917 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1921 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1923 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1925 1926 /* Sidetone */ 1927 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1928 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1929 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1930 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1931 1932 /* Output stages */ 1933 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1934 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1935 1936 { "SPKL", "DAC1 Switch", "DAC1L" }, 1937 { "SPKL", "DAC2 Switch", "DAC2L" }, 1938 1939 { "SPKR", "DAC1 Switch", "DAC1R" }, 1940 { "SPKR", "DAC2 Switch", "DAC2R" }, 1941 1942 { "Left Headphone Mux", "DAC", "DAC1L" }, 1943 { "Right Headphone Mux", "DAC", "DAC1R" }, 1944 }; 1945 1946 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1947 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1948 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1949 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1950 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1951 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1952 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1953 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1954 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1955 }; 1956 1957 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1958 { "DAC1L", NULL, "DAC1L Mixer" }, 1959 { "DAC1R", NULL, "DAC1R Mixer" }, 1960 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1961 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1962 }; 1963 1964 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1965 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1966 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 1967 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 1968 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 1969 { "MICBIAS1", NULL, "CLK_SYS" }, 1970 { "MICBIAS1", NULL, "MICBIAS Supply" }, 1971 { "MICBIAS2", NULL, "CLK_SYS" }, 1972 { "MICBIAS2", NULL, "MICBIAS Supply" }, 1973 }; 1974 1975 static const struct snd_soc_dapm_route wm8994_intercon[] = { 1976 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 1977 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 1978 { "MICBIAS1", NULL, "VMID" }, 1979 { "MICBIAS2", NULL, "VMID" }, 1980 }; 1981 1982 static const struct snd_soc_dapm_route wm8958_intercon[] = { 1983 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 1984 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 1985 1986 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 1987 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 1988 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1989 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1990 1991 { "AIF3DACDAT", NULL, "AIF3" }, 1992 { "AIF3ADCDAT", NULL, "AIF3" }, 1993 1994 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 1995 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 1996 1997 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 1998 }; 1999 2000 /* The size in bits of the FLL divide multiplied by 10 2001 * to allow rounding later */ 2002 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2003 2004 struct fll_div { 2005 u16 outdiv; 2006 u16 n; 2007 u16 k; 2008 u16 clk_ref_div; 2009 u16 fll_fratio; 2010 }; 2011 2012 static int wm8994_get_fll_config(struct fll_div *fll, 2013 int freq_in, int freq_out) 2014 { 2015 u64 Kpart; 2016 unsigned int K, Ndiv, Nmod; 2017 2018 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2019 2020 /* Scale the input frequency down to <= 13.5MHz */ 2021 fll->clk_ref_div = 0; 2022 while (freq_in > 13500000) { 2023 fll->clk_ref_div++; 2024 freq_in /= 2; 2025 2026 if (fll->clk_ref_div > 3) 2027 return -EINVAL; 2028 } 2029 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2030 2031 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2032 fll->outdiv = 3; 2033 while (freq_out * (fll->outdiv + 1) < 90000000) { 2034 fll->outdiv++; 2035 if (fll->outdiv > 63) 2036 return -EINVAL; 2037 } 2038 freq_out *= fll->outdiv + 1; 2039 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2040 2041 if (freq_in > 1000000) { 2042 fll->fll_fratio = 0; 2043 } else if (freq_in > 256000) { 2044 fll->fll_fratio = 1; 2045 freq_in *= 2; 2046 } else if (freq_in > 128000) { 2047 fll->fll_fratio = 2; 2048 freq_in *= 4; 2049 } else if (freq_in > 64000) { 2050 fll->fll_fratio = 3; 2051 freq_in *= 8; 2052 } else { 2053 fll->fll_fratio = 4; 2054 freq_in *= 16; 2055 } 2056 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2057 2058 /* Now, calculate N.K */ 2059 Ndiv = freq_out / freq_in; 2060 2061 fll->n = Ndiv; 2062 Nmod = freq_out % freq_in; 2063 pr_debug("Nmod=%d\n", Nmod); 2064 2065 /* Calculate fractional part - scale up so we can round. */ 2066 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2067 2068 do_div(Kpart, freq_in); 2069 2070 K = Kpart & 0xFFFFFFFF; 2071 2072 if ((K % 10) >= 5) 2073 K += 5; 2074 2075 /* Move down to proper range now rounding is done */ 2076 fll->k = K / 10; 2077 2078 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2079 2080 return 0; 2081 } 2082 2083 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 2084 unsigned int freq_in, unsigned int freq_out) 2085 { 2086 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2087 struct wm8994 *control = wm8994->wm8994; 2088 int reg_offset, ret; 2089 struct fll_div fll; 2090 u16 reg, clk1, aif_reg, aif_src; 2091 unsigned long timeout; 2092 bool was_enabled; 2093 2094 switch (id) { 2095 case WM8994_FLL1: 2096 reg_offset = 0; 2097 id = 0; 2098 aif_src = 0x10; 2099 break; 2100 case WM8994_FLL2: 2101 reg_offset = 0x20; 2102 id = 1; 2103 aif_src = 0x18; 2104 break; 2105 default: 2106 return -EINVAL; 2107 } 2108 2109 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); 2110 was_enabled = reg & WM8994_FLL1_ENA; 2111 2112 switch (src) { 2113 case 0: 2114 /* Allow no source specification when stopping */ 2115 if (freq_out) 2116 return -EINVAL; 2117 src = wm8994->fll[id].src; 2118 break; 2119 case WM8994_FLL_SRC_MCLK1: 2120 case WM8994_FLL_SRC_MCLK2: 2121 case WM8994_FLL_SRC_LRCLK: 2122 case WM8994_FLL_SRC_BCLK: 2123 break; 2124 case WM8994_FLL_SRC_INTERNAL: 2125 freq_in = 12000000; 2126 freq_out = 12000000; 2127 break; 2128 default: 2129 return -EINVAL; 2130 } 2131 2132 /* Are we changing anything? */ 2133 if (wm8994->fll[id].src == src && 2134 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2135 return 0; 2136 2137 /* If we're stopping the FLL redo the old config - no 2138 * registers will actually be written but we avoid GCC flow 2139 * analysis bugs spewing warnings. 2140 */ 2141 if (freq_out) 2142 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 2143 else 2144 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 2145 wm8994->fll[id].out); 2146 if (ret < 0) 2147 return ret; 2148 2149 /* Make sure that we're not providing SYSCLK right now */ 2150 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1); 2151 if (clk1 & WM8994_SYSCLK_SRC) 2152 aif_reg = WM8994_AIF2_CLOCKING_1; 2153 else 2154 aif_reg = WM8994_AIF1_CLOCKING_1; 2155 reg = snd_soc_read(codec, aif_reg); 2156 2157 if ((reg & WM8994_AIF1CLK_ENA) && 2158 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2159 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n", 2160 id + 1); 2161 return -EBUSY; 2162 } 2163 2164 /* We always need to disable the FLL while reconfiguring */ 2165 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2166 WM8994_FLL1_ENA, 0); 2167 2168 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2169 freq_in == freq_out && freq_out) { 2170 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1); 2171 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2172 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2173 goto out; 2174 } 2175 2176 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2177 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2179 WM8994_FLL1_OUTDIV_MASK | 2180 WM8994_FLL1_FRATIO_MASK, reg); 2181 2182 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, 2183 WM8994_FLL1_K_MASK, fll.k); 2184 2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 2186 WM8994_FLL1_N_MASK, 2187 fll.n << WM8994_FLL1_N_SHIFT); 2188 2189 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2190 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2191 WM8994_FLL1_REFCLK_DIV_MASK | 2192 WM8994_FLL1_REFCLK_SRC_MASK, 2193 ((src == WM8994_FLL_SRC_INTERNAL) 2194 << WM8994_FLL1_FRC_NCO_SHIFT) | 2195 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2196 (src - 1)); 2197 2198 /* Clear any pending completion from a previous failure */ 2199 try_wait_for_completion(&wm8994->fll_locked[id]); 2200 2201 /* Enable (with fractional mode if required) */ 2202 if (freq_out) { 2203 /* Enable VMID if we need it */ 2204 if (!was_enabled) { 2205 active_reference(codec); 2206 2207 switch (control->type) { 2208 case WM8994: 2209 vmid_reference(codec); 2210 break; 2211 case WM8958: 2212 if (wm8994->revision < 1) 2213 vmid_reference(codec); 2214 break; 2215 default: 2216 break; 2217 } 2218 } 2219 2220 reg = WM8994_FLL1_ENA; 2221 2222 if (fll.k) 2223 reg |= WM8994_FLL1_FRAC; 2224 if (src == WM8994_FLL_SRC_INTERNAL) 2225 reg |= WM8994_FLL1_OSC_ENA; 2226 2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2228 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2229 WM8994_FLL1_FRAC, reg); 2230 2231 if (wm8994->fll_locked_irq) { 2232 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2233 msecs_to_jiffies(10)); 2234 if (timeout == 0) 2235 dev_warn(codec->dev, 2236 "Timed out waiting for FLL lock\n"); 2237 } else { 2238 msleep(5); 2239 } 2240 } else { 2241 if (was_enabled) { 2242 switch (control->type) { 2243 case WM8994: 2244 vmid_dereference(codec); 2245 break; 2246 case WM8958: 2247 if (wm8994->revision < 1) 2248 vmid_dereference(codec); 2249 break; 2250 default: 2251 break; 2252 } 2253 2254 active_dereference(codec); 2255 } 2256 } 2257 2258 out: 2259 wm8994->fll[id].in = freq_in; 2260 wm8994->fll[id].out = freq_out; 2261 wm8994->fll[id].src = src; 2262 2263 configure_clock(codec); 2264 2265 /* 2266 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2267 * for detection. 2268 */ 2269 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2270 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2271 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2272 WM8994_AIF1CLK_RATE_MASK, 0x1); 2273 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2274 WM8994_AIF2CLK_RATE_MASK, 0x1); 2275 } 2276 2277 return 0; 2278 } 2279 2280 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2281 { 2282 struct completion *completion = data; 2283 2284 complete(completion); 2285 2286 return IRQ_HANDLED; 2287 } 2288 2289 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2290 2291 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2292 unsigned int freq_in, unsigned int freq_out) 2293 { 2294 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 2295 } 2296 2297 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2298 int clk_id, unsigned int freq, int dir) 2299 { 2300 struct snd_soc_codec *codec = dai->codec; 2301 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2302 int i; 2303 2304 switch (dai->id) { 2305 case 1: 2306 case 2: 2307 break; 2308 2309 default: 2310 /* AIF3 shares clocking with AIF1/2 */ 2311 return -EINVAL; 2312 } 2313 2314 switch (clk_id) { 2315 case WM8994_SYSCLK_MCLK1: 2316 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2317 wm8994->mclk[0] = freq; 2318 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2319 dai->id, freq); 2320 break; 2321 2322 case WM8994_SYSCLK_MCLK2: 2323 /* TODO: Set GPIO AF */ 2324 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2325 wm8994->mclk[1] = freq; 2326 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2327 dai->id, freq); 2328 break; 2329 2330 case WM8994_SYSCLK_FLL1: 2331 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2332 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2333 break; 2334 2335 case WM8994_SYSCLK_FLL2: 2336 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2337 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2338 break; 2339 2340 case WM8994_SYSCLK_OPCLK: 2341 /* Special case - a division (times 10) is given and 2342 * no effect on main clocking. 2343 */ 2344 if (freq) { 2345 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2346 if (opclk_divs[i] == freq) 2347 break; 2348 if (i == ARRAY_SIZE(opclk_divs)) 2349 return -EINVAL; 2350 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 2351 WM8994_OPCLK_DIV_MASK, i); 2352 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2353 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2354 } else { 2355 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2356 WM8994_OPCLK_ENA, 0); 2357 } 2358 2359 default: 2360 return -EINVAL; 2361 } 2362 2363 configure_clock(codec); 2364 2365 /* 2366 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2367 * for detection. 2368 */ 2369 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2370 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2371 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2372 WM8994_AIF1CLK_RATE_MASK, 0x1); 2373 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2374 WM8994_AIF2CLK_RATE_MASK, 0x1); 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2381 enum snd_soc_bias_level level) 2382 { 2383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2384 struct wm8994 *control = wm8994->wm8994; 2385 2386 wm_hubs_set_bias_level(codec, level); 2387 2388 switch (level) { 2389 case SND_SOC_BIAS_ON: 2390 break; 2391 2392 case SND_SOC_BIAS_PREPARE: 2393 /* MICBIAS into regulating mode */ 2394 switch (control->type) { 2395 case WM8958: 2396 case WM1811: 2397 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2398 WM8958_MICB1_MODE, 0); 2399 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2400 WM8958_MICB2_MODE, 0); 2401 break; 2402 default: 2403 break; 2404 } 2405 2406 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2407 active_reference(codec); 2408 break; 2409 2410 case SND_SOC_BIAS_STANDBY: 2411 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2412 switch (control->type) { 2413 case WM8958: 2414 if (wm8994->revision == 0) { 2415 /* Optimise performance for rev A */ 2416 snd_soc_update_bits(codec, 2417 WM8958_CHARGE_PUMP_2, 2418 WM8958_CP_DISCH, 2419 WM8958_CP_DISCH); 2420 } 2421 break; 2422 2423 default: 2424 break; 2425 } 2426 2427 /* Discharge LINEOUT1 & 2 */ 2428 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2429 WM8994_LINEOUT1_DISCH | 2430 WM8994_LINEOUT2_DISCH, 2431 WM8994_LINEOUT1_DISCH | 2432 WM8994_LINEOUT2_DISCH); 2433 } 2434 2435 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) 2436 active_dereference(codec); 2437 2438 /* MICBIAS into bypass mode on newer devices */ 2439 switch (control->type) { 2440 case WM8958: 2441 case WM1811: 2442 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2443 WM8958_MICB1_MODE, 2444 WM8958_MICB1_MODE); 2445 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2446 WM8958_MICB2_MODE, 2447 WM8958_MICB2_MODE); 2448 break; 2449 default: 2450 break; 2451 } 2452 break; 2453 2454 case SND_SOC_BIAS_OFF: 2455 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2456 wm8994->cur_fw = NULL; 2457 break; 2458 } 2459 2460 codec->dapm.bias_level = level; 2461 2462 return 0; 2463 } 2464 2465 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode) 2466 { 2467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2468 2469 switch (mode) { 2470 case WM8994_VMID_NORMAL: 2471 if (wm8994->hubs.lineout1_se) { 2472 snd_soc_dapm_disable_pin(&codec->dapm, 2473 "LINEOUT1N Driver"); 2474 snd_soc_dapm_disable_pin(&codec->dapm, 2475 "LINEOUT1P Driver"); 2476 } 2477 if (wm8994->hubs.lineout2_se) { 2478 snd_soc_dapm_disable_pin(&codec->dapm, 2479 "LINEOUT2N Driver"); 2480 snd_soc_dapm_disable_pin(&codec->dapm, 2481 "LINEOUT2P Driver"); 2482 } 2483 2484 /* Do the sync with the old mode to allow it to clean up */ 2485 snd_soc_dapm_sync(&codec->dapm); 2486 wm8994->vmid_mode = mode; 2487 break; 2488 2489 case WM8994_VMID_FORCE: 2490 if (wm8994->hubs.lineout1_se) { 2491 snd_soc_dapm_force_enable_pin(&codec->dapm, 2492 "LINEOUT1N Driver"); 2493 snd_soc_dapm_force_enable_pin(&codec->dapm, 2494 "LINEOUT1P Driver"); 2495 } 2496 if (wm8994->hubs.lineout2_se) { 2497 snd_soc_dapm_force_enable_pin(&codec->dapm, 2498 "LINEOUT2N Driver"); 2499 snd_soc_dapm_force_enable_pin(&codec->dapm, 2500 "LINEOUT2P Driver"); 2501 } 2502 2503 wm8994->vmid_mode = mode; 2504 snd_soc_dapm_sync(&codec->dapm); 2505 break; 2506 2507 default: 2508 return -EINVAL; 2509 } 2510 2511 return 0; 2512 } 2513 2514 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2515 { 2516 struct snd_soc_codec *codec = dai->codec; 2517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2518 struct wm8994 *control = wm8994->wm8994; 2519 int ms_reg; 2520 int aif1_reg; 2521 int ms = 0; 2522 int aif1 = 0; 2523 2524 switch (dai->id) { 2525 case 1: 2526 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2527 aif1_reg = WM8994_AIF1_CONTROL_1; 2528 break; 2529 case 2: 2530 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2531 aif1_reg = WM8994_AIF2_CONTROL_1; 2532 break; 2533 default: 2534 return -EINVAL; 2535 } 2536 2537 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2538 case SND_SOC_DAIFMT_CBS_CFS: 2539 break; 2540 case SND_SOC_DAIFMT_CBM_CFM: 2541 ms = WM8994_AIF1_MSTR; 2542 break; 2543 default: 2544 return -EINVAL; 2545 } 2546 2547 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2548 case SND_SOC_DAIFMT_DSP_B: 2549 aif1 |= WM8994_AIF1_LRCLK_INV; 2550 case SND_SOC_DAIFMT_DSP_A: 2551 aif1 |= 0x18; 2552 break; 2553 case SND_SOC_DAIFMT_I2S: 2554 aif1 |= 0x10; 2555 break; 2556 case SND_SOC_DAIFMT_RIGHT_J: 2557 break; 2558 case SND_SOC_DAIFMT_LEFT_J: 2559 aif1 |= 0x8; 2560 break; 2561 default: 2562 return -EINVAL; 2563 } 2564 2565 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2566 case SND_SOC_DAIFMT_DSP_A: 2567 case SND_SOC_DAIFMT_DSP_B: 2568 /* frame inversion not valid for DSP modes */ 2569 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2570 case SND_SOC_DAIFMT_NB_NF: 2571 break; 2572 case SND_SOC_DAIFMT_IB_NF: 2573 aif1 |= WM8994_AIF1_BCLK_INV; 2574 break; 2575 default: 2576 return -EINVAL; 2577 } 2578 break; 2579 2580 case SND_SOC_DAIFMT_I2S: 2581 case SND_SOC_DAIFMT_RIGHT_J: 2582 case SND_SOC_DAIFMT_LEFT_J: 2583 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2584 case SND_SOC_DAIFMT_NB_NF: 2585 break; 2586 case SND_SOC_DAIFMT_IB_IF: 2587 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2588 break; 2589 case SND_SOC_DAIFMT_IB_NF: 2590 aif1 |= WM8994_AIF1_BCLK_INV; 2591 break; 2592 case SND_SOC_DAIFMT_NB_IF: 2593 aif1 |= WM8994_AIF1_LRCLK_INV; 2594 break; 2595 default: 2596 return -EINVAL; 2597 } 2598 break; 2599 default: 2600 return -EINVAL; 2601 } 2602 2603 /* The AIF2 format configuration needs to be mirrored to AIF3 2604 * on WM8958 if it's in use so just do it all the time. */ 2605 switch (control->type) { 2606 case WM1811: 2607 case WM8958: 2608 if (dai->id == 2) 2609 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2610 WM8994_AIF1_LRCLK_INV | 2611 WM8958_AIF3_FMT_MASK, aif1); 2612 break; 2613 2614 default: 2615 break; 2616 } 2617 2618 snd_soc_update_bits(codec, aif1_reg, 2619 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2620 WM8994_AIF1_FMT_MASK, 2621 aif1); 2622 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2623 ms); 2624 2625 return 0; 2626 } 2627 2628 static struct { 2629 int val, rate; 2630 } srs[] = { 2631 { 0, 8000 }, 2632 { 1, 11025 }, 2633 { 2, 12000 }, 2634 { 3, 16000 }, 2635 { 4, 22050 }, 2636 { 5, 24000 }, 2637 { 6, 32000 }, 2638 { 7, 44100 }, 2639 { 8, 48000 }, 2640 { 9, 88200 }, 2641 { 10, 96000 }, 2642 }; 2643 2644 static int fs_ratios[] = { 2645 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2646 }; 2647 2648 static int bclk_divs[] = { 2649 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2650 640, 880, 960, 1280, 1760, 1920 2651 }; 2652 2653 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2654 struct snd_pcm_hw_params *params, 2655 struct snd_soc_dai *dai) 2656 { 2657 struct snd_soc_codec *codec = dai->codec; 2658 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2659 int aif1_reg; 2660 int aif2_reg; 2661 int bclk_reg; 2662 int lrclk_reg; 2663 int rate_reg; 2664 int aif1 = 0; 2665 int aif2 = 0; 2666 int bclk = 0; 2667 int lrclk = 0; 2668 int rate_val = 0; 2669 int id = dai->id - 1; 2670 2671 int i, cur_val, best_val, bclk_rate, best; 2672 2673 switch (dai->id) { 2674 case 1: 2675 aif1_reg = WM8994_AIF1_CONTROL_1; 2676 aif2_reg = WM8994_AIF1_CONTROL_2; 2677 bclk_reg = WM8994_AIF1_BCLK; 2678 rate_reg = WM8994_AIF1_RATE; 2679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2680 wm8994->lrclk_shared[0]) { 2681 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2682 } else { 2683 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2684 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2685 } 2686 break; 2687 case 2: 2688 aif1_reg = WM8994_AIF2_CONTROL_1; 2689 aif2_reg = WM8994_AIF2_CONTROL_2; 2690 bclk_reg = WM8994_AIF2_BCLK; 2691 rate_reg = WM8994_AIF2_RATE; 2692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2693 wm8994->lrclk_shared[1]) { 2694 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2695 } else { 2696 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2697 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2698 } 2699 break; 2700 default: 2701 return -EINVAL; 2702 } 2703 2704 bclk_rate = params_rate(params); 2705 switch (params_format(params)) { 2706 case SNDRV_PCM_FORMAT_S16_LE: 2707 bclk_rate *= 16; 2708 break; 2709 case SNDRV_PCM_FORMAT_S20_3LE: 2710 bclk_rate *= 20; 2711 aif1 |= 0x20; 2712 break; 2713 case SNDRV_PCM_FORMAT_S24_LE: 2714 bclk_rate *= 24; 2715 aif1 |= 0x40; 2716 break; 2717 case SNDRV_PCM_FORMAT_S32_LE: 2718 bclk_rate *= 32; 2719 aif1 |= 0x60; 2720 break; 2721 default: 2722 return -EINVAL; 2723 } 2724 2725 wm8994->channels[id] = params_channels(params); 2726 switch (params_channels(params)) { 2727 case 1: 2728 case 2: 2729 bclk_rate *= 2; 2730 break; 2731 default: 2732 bclk_rate *= 4; 2733 break; 2734 } 2735 2736 /* Try to find an appropriate sample rate; look for an exact match. */ 2737 for (i = 0; i < ARRAY_SIZE(srs); i++) 2738 if (srs[i].rate == params_rate(params)) 2739 break; 2740 if (i == ARRAY_SIZE(srs)) 2741 return -EINVAL; 2742 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2743 2744 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2745 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2746 dai->id, wm8994->aifclk[id], bclk_rate); 2747 2748 if (params_channels(params) == 1 && 2749 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2750 aif2 |= WM8994_AIF1_MONO; 2751 2752 if (wm8994->aifclk[id] == 0) { 2753 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2754 return -EINVAL; 2755 } 2756 2757 /* AIFCLK/fs ratio; look for a close match in either direction */ 2758 best = 0; 2759 best_val = abs((fs_ratios[0] * params_rate(params)) 2760 - wm8994->aifclk[id]); 2761 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2762 cur_val = abs((fs_ratios[i] * params_rate(params)) 2763 - wm8994->aifclk[id]); 2764 if (cur_val >= best_val) 2765 continue; 2766 best = i; 2767 best_val = cur_val; 2768 } 2769 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2770 dai->id, fs_ratios[best]); 2771 rate_val |= best; 2772 2773 /* We may not get quite the right frequency if using 2774 * approximate clocks so look for the closest match that is 2775 * higher than the target (we need to ensure that there enough 2776 * BCLKs to clock out the samples). 2777 */ 2778 best = 0; 2779 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2780 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2781 if (cur_val < 0) /* BCLK table is sorted */ 2782 break; 2783 best = i; 2784 } 2785 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2786 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2787 bclk_divs[best], bclk_rate); 2788 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2789 2790 lrclk = bclk_rate / params_rate(params); 2791 if (!lrclk) { 2792 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 2793 bclk_rate); 2794 return -EINVAL; 2795 } 2796 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2797 lrclk, bclk_rate / lrclk); 2798 2799 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2800 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2801 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2802 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2803 lrclk); 2804 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2805 WM8994_AIF1CLK_RATE_MASK, rate_val); 2806 2807 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2808 switch (dai->id) { 2809 case 1: 2810 wm8994->dac_rates[0] = params_rate(params); 2811 wm8994_set_retune_mobile(codec, 0); 2812 wm8994_set_retune_mobile(codec, 1); 2813 break; 2814 case 2: 2815 wm8994->dac_rates[1] = params_rate(params); 2816 wm8994_set_retune_mobile(codec, 2); 2817 break; 2818 } 2819 } 2820 2821 return 0; 2822 } 2823 2824 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2825 struct snd_pcm_hw_params *params, 2826 struct snd_soc_dai *dai) 2827 { 2828 struct snd_soc_codec *codec = dai->codec; 2829 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2830 struct wm8994 *control = wm8994->wm8994; 2831 int aif1_reg; 2832 int aif1 = 0; 2833 2834 switch (dai->id) { 2835 case 3: 2836 switch (control->type) { 2837 case WM1811: 2838 case WM8958: 2839 aif1_reg = WM8958_AIF3_CONTROL_1; 2840 break; 2841 default: 2842 return 0; 2843 } 2844 default: 2845 return 0; 2846 } 2847 2848 switch (params_format(params)) { 2849 case SNDRV_PCM_FORMAT_S16_LE: 2850 break; 2851 case SNDRV_PCM_FORMAT_S20_3LE: 2852 aif1 |= 0x20; 2853 break; 2854 case SNDRV_PCM_FORMAT_S24_LE: 2855 aif1 |= 0x40; 2856 break; 2857 case SNDRV_PCM_FORMAT_S32_LE: 2858 aif1 |= 0x60; 2859 break; 2860 default: 2861 return -EINVAL; 2862 } 2863 2864 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2865 } 2866 2867 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2868 { 2869 struct snd_soc_codec *codec = codec_dai->codec; 2870 int mute_reg; 2871 int reg; 2872 2873 switch (codec_dai->id) { 2874 case 1: 2875 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2876 break; 2877 case 2: 2878 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2879 break; 2880 default: 2881 return -EINVAL; 2882 } 2883 2884 if (mute) 2885 reg = WM8994_AIF1DAC1_MUTE; 2886 else 2887 reg = 0; 2888 2889 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2890 2891 return 0; 2892 } 2893 2894 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 2895 { 2896 struct snd_soc_codec *codec = codec_dai->codec; 2897 int reg, val, mask; 2898 2899 switch (codec_dai->id) { 2900 case 1: 2901 reg = WM8994_AIF1_MASTER_SLAVE; 2902 mask = WM8994_AIF1_TRI; 2903 break; 2904 case 2: 2905 reg = WM8994_AIF2_MASTER_SLAVE; 2906 mask = WM8994_AIF2_TRI; 2907 break; 2908 default: 2909 return -EINVAL; 2910 } 2911 2912 if (tristate) 2913 val = mask; 2914 else 2915 val = 0; 2916 2917 return snd_soc_update_bits(codec, reg, mask, val); 2918 } 2919 2920 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 2921 { 2922 struct snd_soc_codec *codec = dai->codec; 2923 2924 /* Disable the pulls on the AIF if we're using it to save power. */ 2925 snd_soc_update_bits(codec, WM8994_GPIO_3, 2926 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2927 snd_soc_update_bits(codec, WM8994_GPIO_4, 2928 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2929 snd_soc_update_bits(codec, WM8994_GPIO_5, 2930 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2931 2932 return 0; 2933 } 2934 2935 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2936 2937 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2938 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2939 2940 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2941 .set_sysclk = wm8994_set_dai_sysclk, 2942 .set_fmt = wm8994_set_dai_fmt, 2943 .hw_params = wm8994_hw_params, 2944 .digital_mute = wm8994_aif_mute, 2945 .set_pll = wm8994_set_fll, 2946 .set_tristate = wm8994_set_tristate, 2947 }; 2948 2949 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2950 .set_sysclk = wm8994_set_dai_sysclk, 2951 .set_fmt = wm8994_set_dai_fmt, 2952 .hw_params = wm8994_hw_params, 2953 .digital_mute = wm8994_aif_mute, 2954 .set_pll = wm8994_set_fll, 2955 .set_tristate = wm8994_set_tristate, 2956 }; 2957 2958 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2959 .hw_params = wm8994_aif3_hw_params, 2960 }; 2961 2962 static struct snd_soc_dai_driver wm8994_dai[] = { 2963 { 2964 .name = "wm8994-aif1", 2965 .id = 1, 2966 .playback = { 2967 .stream_name = "AIF1 Playback", 2968 .channels_min = 1, 2969 .channels_max = 2, 2970 .rates = WM8994_RATES, 2971 .formats = WM8994_FORMATS, 2972 .sig_bits = 24, 2973 }, 2974 .capture = { 2975 .stream_name = "AIF1 Capture", 2976 .channels_min = 1, 2977 .channels_max = 2, 2978 .rates = WM8994_RATES, 2979 .formats = WM8994_FORMATS, 2980 .sig_bits = 24, 2981 }, 2982 .ops = &wm8994_aif1_dai_ops, 2983 }, 2984 { 2985 .name = "wm8994-aif2", 2986 .id = 2, 2987 .playback = { 2988 .stream_name = "AIF2 Playback", 2989 .channels_min = 1, 2990 .channels_max = 2, 2991 .rates = WM8994_RATES, 2992 .formats = WM8994_FORMATS, 2993 .sig_bits = 24, 2994 }, 2995 .capture = { 2996 .stream_name = "AIF2 Capture", 2997 .channels_min = 1, 2998 .channels_max = 2, 2999 .rates = WM8994_RATES, 3000 .formats = WM8994_FORMATS, 3001 .sig_bits = 24, 3002 }, 3003 .probe = wm8994_aif2_probe, 3004 .ops = &wm8994_aif2_dai_ops, 3005 }, 3006 { 3007 .name = "wm8994-aif3", 3008 .id = 3, 3009 .playback = { 3010 .stream_name = "AIF3 Playback", 3011 .channels_min = 1, 3012 .channels_max = 2, 3013 .rates = WM8994_RATES, 3014 .formats = WM8994_FORMATS, 3015 .sig_bits = 24, 3016 }, 3017 .capture = { 3018 .stream_name = "AIF3 Capture", 3019 .channels_min = 1, 3020 .channels_max = 2, 3021 .rates = WM8994_RATES, 3022 .formats = WM8994_FORMATS, 3023 .sig_bits = 24, 3024 }, 3025 .ops = &wm8994_aif3_dai_ops, 3026 } 3027 }; 3028 3029 #ifdef CONFIG_PM 3030 static int wm8994_codec_suspend(struct snd_soc_codec *codec) 3031 { 3032 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3033 int i, ret; 3034 3035 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3036 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3037 sizeof(struct wm8994_fll_config)); 3038 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 3039 if (ret < 0) 3040 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 3041 i + 1, ret); 3042 } 3043 3044 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3045 3046 return 0; 3047 } 3048 3049 static int wm8994_codec_resume(struct snd_soc_codec *codec) 3050 { 3051 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3052 struct wm8994 *control = wm8994->wm8994; 3053 int i, ret; 3054 unsigned int val, mask; 3055 3056 if (wm8994->revision < 4) { 3057 /* force a HW read */ 3058 ret = regmap_read(control->regmap, 3059 WM8994_POWER_MANAGEMENT_5, &val); 3060 3061 /* modify the cache only */ 3062 codec->cache_only = 1; 3063 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | 3064 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; 3065 val &= mask; 3066 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 3067 mask, val); 3068 codec->cache_only = 0; 3069 } 3070 3071 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3072 if (!wm8994->fll_suspend[i].out) 3073 continue; 3074 3075 ret = _wm8994_set_fll(codec, i + 1, 3076 wm8994->fll_suspend[i].src, 3077 wm8994->fll_suspend[i].in, 3078 wm8994->fll_suspend[i].out); 3079 if (ret < 0) 3080 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 3081 i + 1, ret); 3082 } 3083 3084 return 0; 3085 } 3086 #else 3087 #define wm8994_codec_suspend NULL 3088 #define wm8994_codec_resume NULL 3089 #endif 3090 3091 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3092 { 3093 struct snd_soc_codec *codec = wm8994->hubs.codec; 3094 struct wm8994 *control = wm8994->wm8994; 3095 struct wm8994_pdata *pdata = &control->pdata; 3096 struct snd_kcontrol_new controls[] = { 3097 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3098 wm8994->retune_mobile_enum, 3099 wm8994_get_retune_mobile_enum, 3100 wm8994_put_retune_mobile_enum), 3101 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3102 wm8994->retune_mobile_enum, 3103 wm8994_get_retune_mobile_enum, 3104 wm8994_put_retune_mobile_enum), 3105 SOC_ENUM_EXT("AIF2 EQ Mode", 3106 wm8994->retune_mobile_enum, 3107 wm8994_get_retune_mobile_enum, 3108 wm8994_put_retune_mobile_enum), 3109 }; 3110 int ret, i, j; 3111 const char **t; 3112 3113 /* We need an array of texts for the enum API but the number 3114 * of texts is likely to be less than the number of 3115 * configurations due to the sample rate dependency of the 3116 * configurations. */ 3117 wm8994->num_retune_mobile_texts = 0; 3118 wm8994->retune_mobile_texts = NULL; 3119 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3120 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3121 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3122 wm8994->retune_mobile_texts[j]) == 0) 3123 break; 3124 } 3125 3126 if (j != wm8994->num_retune_mobile_texts) 3127 continue; 3128 3129 /* Expand the array... */ 3130 t = krealloc(wm8994->retune_mobile_texts, 3131 sizeof(char *) * 3132 (wm8994->num_retune_mobile_texts + 1), 3133 GFP_KERNEL); 3134 if (t == NULL) 3135 continue; 3136 3137 /* ...store the new entry... */ 3138 t[wm8994->num_retune_mobile_texts] = 3139 pdata->retune_mobile_cfgs[i].name; 3140 3141 /* ...and remember the new version. */ 3142 wm8994->num_retune_mobile_texts++; 3143 wm8994->retune_mobile_texts = t; 3144 } 3145 3146 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 3147 wm8994->num_retune_mobile_texts); 3148 3149 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 3150 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3151 3152 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3153 ARRAY_SIZE(controls)); 3154 if (ret != 0) 3155 dev_err(wm8994->hubs.codec->dev, 3156 "Failed to add ReTune Mobile controls: %d\n", ret); 3157 } 3158 3159 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3160 { 3161 struct snd_soc_codec *codec = wm8994->hubs.codec; 3162 struct wm8994 *control = wm8994->wm8994; 3163 struct wm8994_pdata *pdata = &control->pdata; 3164 int ret, i; 3165 3166 if (!pdata) 3167 return; 3168 3169 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 3170 pdata->lineout2_diff, 3171 pdata->lineout1fb, 3172 pdata->lineout2fb, 3173 pdata->jd_scthr, 3174 pdata->jd_thr, 3175 pdata->micb1_delay, 3176 pdata->micb2_delay, 3177 pdata->micbias1_lvl, 3178 pdata->micbias2_lvl); 3179 3180 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3181 3182 if (pdata->num_drc_cfgs) { 3183 struct snd_kcontrol_new controls[] = { 3184 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3185 wm8994_get_drc_enum, wm8994_put_drc_enum), 3186 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3187 wm8994_get_drc_enum, wm8994_put_drc_enum), 3188 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3189 wm8994_get_drc_enum, wm8994_put_drc_enum), 3190 }; 3191 3192 /* We need an array of texts for the enum API */ 3193 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev, 3194 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL); 3195 if (!wm8994->drc_texts) { 3196 dev_err(wm8994->hubs.codec->dev, 3197 "Failed to allocate %d DRC config texts\n", 3198 pdata->num_drc_cfgs); 3199 return; 3200 } 3201 3202 for (i = 0; i < pdata->num_drc_cfgs; i++) 3203 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3204 3205 wm8994->drc_enum.max = pdata->num_drc_cfgs; 3206 wm8994->drc_enum.texts = wm8994->drc_texts; 3207 3208 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3209 ARRAY_SIZE(controls)); 3210 for (i = 0; i < WM8994_NUM_DRC; i++) 3211 wm8994_set_drc(codec, i); 3212 } else { 3213 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, 3214 wm8994_drc_controls, 3215 ARRAY_SIZE(wm8994_drc_controls)); 3216 } 3217 3218 if (ret != 0) 3219 dev_err(wm8994->hubs.codec->dev, 3220 "Failed to add DRC mode controls: %d\n", ret); 3221 3222 3223 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 3224 pdata->num_retune_mobile_cfgs); 3225 3226 if (pdata->num_retune_mobile_cfgs) 3227 wm8994_handle_retune_mobile_pdata(wm8994); 3228 else 3229 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls, 3230 ARRAY_SIZE(wm8994_eq_controls)); 3231 3232 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3233 if (pdata->micbias[i]) { 3234 snd_soc_write(codec, WM8958_MICBIAS1 + i, 3235 pdata->micbias[i] & 0xffff); 3236 } 3237 } 3238 } 3239 3240 /** 3241 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3242 * 3243 * @codec: WM8994 codec 3244 * @jack: jack to report detection events on 3245 * @micbias: microphone bias to detect on 3246 * 3247 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3248 * being used to bring out signals to the processor then only platform 3249 * data configuration is needed for WM8994 and processor GPIOs should 3250 * be configured using snd_soc_jack_add_gpios() instead. 3251 * 3252 * Configuration of detection levels is available via the micbias1_lvl 3253 * and micbias2_lvl platform data members. 3254 */ 3255 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3256 int micbias) 3257 { 3258 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3259 struct wm8994_micdet *micdet; 3260 struct wm8994 *control = wm8994->wm8994; 3261 int reg, ret; 3262 3263 if (control->type != WM8994) { 3264 dev_warn(codec->dev, "Not a WM8994\n"); 3265 return -EINVAL; 3266 } 3267 3268 switch (micbias) { 3269 case 1: 3270 micdet = &wm8994->micdet[0]; 3271 if (jack) 3272 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3273 "MICBIAS1"); 3274 else 3275 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3276 "MICBIAS1"); 3277 break; 3278 case 2: 3279 micdet = &wm8994->micdet[1]; 3280 if (jack) 3281 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3282 "MICBIAS1"); 3283 else 3284 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3285 "MICBIAS1"); 3286 break; 3287 default: 3288 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias); 3289 return -EINVAL; 3290 } 3291 3292 if (ret != 0) 3293 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n", 3294 micbias, ret); 3295 3296 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n", 3297 micbias, jack); 3298 3299 /* Store the configuration */ 3300 micdet->jack = jack; 3301 micdet->detecting = true; 3302 3303 /* If either of the jacks is set up then enable detection */ 3304 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3305 reg = WM8994_MICD_ENA; 3306 else 3307 reg = 0; 3308 3309 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3310 3311 /* enable MICDET and MICSHRT deboune */ 3312 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE, 3313 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3314 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3315 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3316 3317 snd_soc_dapm_sync(&codec->dapm); 3318 3319 return 0; 3320 } 3321 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3322 3323 static void wm8994_mic_work(struct work_struct *work) 3324 { 3325 struct wm8994_priv *priv = container_of(work, 3326 struct wm8994_priv, 3327 mic_work.work); 3328 struct regmap *regmap = priv->wm8994->regmap; 3329 struct device *dev = priv->wm8994->dev; 3330 unsigned int reg; 3331 int ret; 3332 int report; 3333 3334 pm_runtime_get_sync(dev); 3335 3336 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3337 if (ret < 0) { 3338 dev_err(dev, "Failed to read microphone status: %d\n", 3339 ret); 3340 pm_runtime_put(dev); 3341 return; 3342 } 3343 3344 dev_dbg(dev, "Microphone status: %x\n", reg); 3345 3346 report = 0; 3347 if (reg & WM8994_MIC1_DET_STS) { 3348 if (priv->micdet[0].detecting) 3349 report = SND_JACK_HEADSET; 3350 } 3351 if (reg & WM8994_MIC1_SHRT_STS) { 3352 if (priv->micdet[0].detecting) 3353 report = SND_JACK_HEADPHONE; 3354 else 3355 report |= SND_JACK_BTN_0; 3356 } 3357 if (report) 3358 priv->micdet[0].detecting = false; 3359 else 3360 priv->micdet[0].detecting = true; 3361 3362 snd_soc_jack_report(priv->micdet[0].jack, report, 3363 SND_JACK_HEADSET | SND_JACK_BTN_0); 3364 3365 report = 0; 3366 if (reg & WM8994_MIC2_DET_STS) { 3367 if (priv->micdet[1].detecting) 3368 report = SND_JACK_HEADSET; 3369 } 3370 if (reg & WM8994_MIC2_SHRT_STS) { 3371 if (priv->micdet[1].detecting) 3372 report = SND_JACK_HEADPHONE; 3373 else 3374 report |= SND_JACK_BTN_0; 3375 } 3376 if (report) 3377 priv->micdet[1].detecting = false; 3378 else 3379 priv->micdet[1].detecting = true; 3380 3381 snd_soc_jack_report(priv->micdet[1].jack, report, 3382 SND_JACK_HEADSET | SND_JACK_BTN_0); 3383 3384 pm_runtime_put(dev); 3385 } 3386 3387 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3388 { 3389 struct wm8994_priv *priv = data; 3390 struct snd_soc_codec *codec = priv->hubs.codec; 3391 3392 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3393 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3394 #endif 3395 3396 pm_wakeup_event(codec->dev, 300); 3397 3398 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250)); 3399 3400 return IRQ_HANDLED; 3401 } 3402 3403 static void wm1811_micd_stop(struct snd_soc_codec *codec) 3404 { 3405 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3406 3407 if (!wm8994->jackdet) 3408 return; 3409 3410 mutex_lock(&wm8994->accdet_lock); 3411 3412 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3413 3414 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3415 3416 mutex_unlock(&wm8994->accdet_lock); 3417 3418 if (wm8994->wm8994->pdata.jd_ext_cap) 3419 snd_soc_dapm_disable_pin(&codec->dapm, 3420 "MICBIAS2"); 3421 } 3422 3423 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status) 3424 { 3425 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3426 int report; 3427 3428 report = 0; 3429 if (status & 0x4) 3430 report |= SND_JACK_BTN_0; 3431 3432 if (status & 0x8) 3433 report |= SND_JACK_BTN_1; 3434 3435 if (status & 0x10) 3436 report |= SND_JACK_BTN_2; 3437 3438 if (status & 0x20) 3439 report |= SND_JACK_BTN_3; 3440 3441 if (status & 0x40) 3442 report |= SND_JACK_BTN_4; 3443 3444 if (status & 0x80) 3445 report |= SND_JACK_BTN_5; 3446 3447 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3448 wm8994->btn_mask); 3449 } 3450 3451 static void wm8958_mic_id(void *data, u16 status) 3452 { 3453 struct snd_soc_codec *codec = data; 3454 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3455 3456 /* Either nothing present or just starting detection */ 3457 if (!(status & WM8958_MICD_STS)) { 3458 /* If nothing present then clear our statuses */ 3459 dev_dbg(codec->dev, "Detected open circuit\n"); 3460 wm8994->jack_mic = false; 3461 wm8994->mic_detecting = true; 3462 3463 wm1811_micd_stop(codec); 3464 3465 wm8958_micd_set_rate(codec); 3466 3467 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3468 wm8994->btn_mask | 3469 SND_JACK_HEADSET); 3470 return; 3471 } 3472 3473 /* If the measurement is showing a high impedence we've got a 3474 * microphone. 3475 */ 3476 if (status & 0x600) { 3477 dev_dbg(codec->dev, "Detected microphone\n"); 3478 3479 wm8994->mic_detecting = false; 3480 wm8994->jack_mic = true; 3481 3482 wm8958_micd_set_rate(codec); 3483 3484 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3485 SND_JACK_HEADSET); 3486 } 3487 3488 3489 if (status & 0xfc) { 3490 dev_dbg(codec->dev, "Detected headphone\n"); 3491 wm8994->mic_detecting = false; 3492 3493 wm8958_micd_set_rate(codec); 3494 3495 /* If we have jackdet that will detect removal */ 3496 wm1811_micd_stop(codec); 3497 3498 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3499 SND_JACK_HEADSET); 3500 } 3501 } 3502 3503 /* Deferred mic detection to allow for extra settling time */ 3504 static void wm1811_mic_work(struct work_struct *work) 3505 { 3506 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3507 mic_work.work); 3508 struct wm8994 *control = wm8994->wm8994; 3509 struct snd_soc_codec *codec = wm8994->hubs.codec; 3510 3511 pm_runtime_get_sync(codec->dev); 3512 3513 /* If required for an external cap force MICBIAS on */ 3514 if (control->pdata.jd_ext_cap) { 3515 snd_soc_dapm_force_enable_pin(&codec->dapm, 3516 "MICBIAS2"); 3517 snd_soc_dapm_sync(&codec->dapm); 3518 } 3519 3520 mutex_lock(&wm8994->accdet_lock); 3521 3522 dev_dbg(codec->dev, "Starting mic detection\n"); 3523 3524 /* Use a user-supplied callback if we have one */ 3525 if (wm8994->micd_cb) { 3526 wm8994->micd_cb(wm8994->micd_cb_data); 3527 } else { 3528 /* 3529 * Start off measument of microphone impedence to find out 3530 * what's actually there. 3531 */ 3532 wm8994->mic_detecting = true; 3533 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC); 3534 3535 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3536 WM8958_MICD_ENA, WM8958_MICD_ENA); 3537 } 3538 3539 mutex_unlock(&wm8994->accdet_lock); 3540 3541 pm_runtime_put(codec->dev); 3542 } 3543 3544 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3545 { 3546 struct wm8994_priv *wm8994 = data; 3547 struct wm8994 *control = wm8994->wm8994; 3548 struct snd_soc_codec *codec = wm8994->hubs.codec; 3549 int reg, delay; 3550 bool present; 3551 3552 pm_runtime_get_sync(codec->dev); 3553 3554 mutex_lock(&wm8994->accdet_lock); 3555 3556 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3557 if (reg < 0) { 3558 dev_err(codec->dev, "Failed to read jack status: %d\n", reg); 3559 mutex_unlock(&wm8994->accdet_lock); 3560 pm_runtime_put(codec->dev); 3561 return IRQ_NONE; 3562 } 3563 3564 dev_dbg(codec->dev, "JACKDET %x\n", reg); 3565 3566 present = reg & WM1811_JACKDET_LVL; 3567 3568 if (present) { 3569 dev_dbg(codec->dev, "Jack detected\n"); 3570 3571 wm8958_micd_set_rate(codec); 3572 3573 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3574 WM8958_MICB2_DISCH, 0); 3575 3576 /* Disable debounce while inserted */ 3577 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3578 WM1811_JACKDET_DB, 0); 3579 3580 delay = control->pdata.micdet_delay; 3581 schedule_delayed_work(&wm8994->mic_work, 3582 msecs_to_jiffies(delay)); 3583 } else { 3584 dev_dbg(codec->dev, "Jack not detected\n"); 3585 3586 cancel_delayed_work_sync(&wm8994->mic_work); 3587 3588 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3589 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3590 3591 /* Enable debounce while removed */ 3592 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3593 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3594 3595 wm8994->mic_detecting = false; 3596 wm8994->jack_mic = false; 3597 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3598 WM8958_MICD_ENA, 0); 3599 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3600 } 3601 3602 mutex_unlock(&wm8994->accdet_lock); 3603 3604 /* Turn off MICBIAS if it was on for an external cap */ 3605 if (control->pdata.jd_ext_cap && !present) 3606 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2"); 3607 3608 if (present) 3609 snd_soc_jack_report(wm8994->micdet[0].jack, 3610 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3611 else 3612 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3613 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3614 wm8994->btn_mask); 3615 3616 /* Since we only report deltas force an update, ensures we 3617 * avoid bootstrapping issues with the core. */ 3618 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3619 3620 pm_runtime_put(codec->dev); 3621 return IRQ_HANDLED; 3622 } 3623 3624 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3625 { 3626 struct wm8994_priv *wm8994 = container_of(work, 3627 struct wm8994_priv, 3628 jackdet_bootstrap.work); 3629 wm1811_jackdet_irq(0, wm8994); 3630 } 3631 3632 /** 3633 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3634 * 3635 * @codec: WM8958 codec 3636 * @jack: jack to report detection events on 3637 * 3638 * Enable microphone detection functionality for the WM8958. By 3639 * default simple detection which supports the detection of up to 6 3640 * buttons plus video and microphone functionality is supported. 3641 * 3642 * The WM8958 has an advanced jack detection facility which is able to 3643 * support complex accessory detection, especially when used in 3644 * conjunction with external circuitry. In order to provide maximum 3645 * flexiblity a callback is provided which allows a completely custom 3646 * detection algorithm. 3647 */ 3648 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3649 wm1811_micdet_cb det_cb, void *det_cb_data, 3650 wm1811_mic_id_cb id_cb, void *id_cb_data) 3651 { 3652 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3653 struct wm8994 *control = wm8994->wm8994; 3654 u16 micd_lvl_sel; 3655 3656 switch (control->type) { 3657 case WM1811: 3658 case WM8958: 3659 break; 3660 default: 3661 return -EINVAL; 3662 } 3663 3664 if (jack) { 3665 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS"); 3666 snd_soc_dapm_sync(&codec->dapm); 3667 3668 wm8994->micdet[0].jack = jack; 3669 3670 if (det_cb) { 3671 wm8994->micd_cb = det_cb; 3672 wm8994->micd_cb_data = det_cb_data; 3673 } else { 3674 wm8994->mic_detecting = true; 3675 wm8994->jack_mic = false; 3676 } 3677 3678 if (id_cb) { 3679 wm8994->mic_id_cb = id_cb; 3680 wm8994->mic_id_cb_data = id_cb_data; 3681 } else { 3682 wm8994->mic_id_cb = wm8958_mic_id; 3683 wm8994->mic_id_cb_data = codec; 3684 } 3685 3686 wm8958_micd_set_rate(codec); 3687 3688 /* Detect microphones and short circuits by default */ 3689 if (control->pdata.micd_lvl_sel) 3690 micd_lvl_sel = control->pdata.micd_lvl_sel; 3691 else 3692 micd_lvl_sel = 0x41; 3693 3694 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3695 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3696 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3697 3698 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2, 3699 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3700 3701 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY); 3702 3703 /* 3704 * If we can use jack detection start off with that, 3705 * otherwise jump straight to microphone detection. 3706 */ 3707 if (wm8994->jackdet) { 3708 /* Disable debounce for the initial detect */ 3709 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3710 WM1811_JACKDET_DB, 0); 3711 3712 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3713 WM8958_MICB2_DISCH, 3714 WM8958_MICB2_DISCH); 3715 snd_soc_update_bits(codec, WM8994_LDO_1, 3716 WM8994_LDO1_DISCH, 0); 3717 wm1811_jackdet_set_mode(codec, 3718 WM1811_JACKDET_MODE_JACK); 3719 } else { 3720 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3721 WM8958_MICD_ENA, WM8958_MICD_ENA); 3722 } 3723 3724 } else { 3725 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3726 WM8958_MICD_ENA, 0); 3727 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE); 3728 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS"); 3729 snd_soc_dapm_sync(&codec->dapm); 3730 } 3731 3732 return 0; 3733 } 3734 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3735 3736 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3737 { 3738 struct wm8994_priv *wm8994 = data; 3739 struct snd_soc_codec *codec = wm8994->hubs.codec; 3740 int reg, count; 3741 3742 /* 3743 * Jack detection may have detected a removal simulataneously 3744 * with an update of the MICDET status; if so it will have 3745 * stopped detection and we can ignore this interrupt. 3746 */ 3747 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 3748 return IRQ_HANDLED; 3749 3750 pm_runtime_get_sync(codec->dev); 3751 3752 /* We may occasionally read a detection without an impedence 3753 * range being provided - if that happens loop again. 3754 */ 3755 count = 10; 3756 do { 3757 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 3758 if (reg < 0) { 3759 dev_err(codec->dev, 3760 "Failed to read mic detect status: %d\n", 3761 reg); 3762 pm_runtime_put(codec->dev); 3763 return IRQ_NONE; 3764 } 3765 3766 if (!(reg & WM8958_MICD_VALID)) { 3767 dev_dbg(codec->dev, "Mic detect data not valid\n"); 3768 goto out; 3769 } 3770 3771 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 3772 break; 3773 3774 msleep(1); 3775 } while (count--); 3776 3777 if (count == 0) 3778 dev_warn(codec->dev, "No impedance range reported for jack\n"); 3779 3780 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3781 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3782 #endif 3783 3784 /* Avoid a transient report when the accessory is being removed */ 3785 if (wm8994->jackdet) { 3786 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3787 if (reg < 0) { 3788 dev_err(codec->dev, "Failed to read jack status: %d\n", 3789 reg); 3790 } else if (!(reg & WM1811_JACKDET_LVL)) { 3791 dev_dbg(codec->dev, "Ignoring removed jack\n"); 3792 return IRQ_HANDLED; 3793 } 3794 } 3795 3796 if (wm8994->mic_detecting) 3797 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg); 3798 else 3799 wm8958_button_det(codec, reg); 3800 3801 out: 3802 pm_runtime_put(codec->dev); 3803 return IRQ_HANDLED; 3804 } 3805 3806 static irqreturn_t wm8994_fifo_error(int irq, void *data) 3807 { 3808 struct snd_soc_codec *codec = data; 3809 3810 dev_err(codec->dev, "FIFO error\n"); 3811 3812 return IRQ_HANDLED; 3813 } 3814 3815 static irqreturn_t wm8994_temp_warn(int irq, void *data) 3816 { 3817 struct snd_soc_codec *codec = data; 3818 3819 dev_err(codec->dev, "Thermal warning\n"); 3820 3821 return IRQ_HANDLED; 3822 } 3823 3824 static irqreturn_t wm8994_temp_shut(int irq, void *data) 3825 { 3826 struct snd_soc_codec *codec = data; 3827 3828 dev_crit(codec->dev, "Thermal shutdown\n"); 3829 3830 return IRQ_HANDLED; 3831 } 3832 3833 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3834 { 3835 struct wm8994 *control = dev_get_drvdata(codec->dev->parent); 3836 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3837 struct snd_soc_dapm_context *dapm = &codec->dapm; 3838 unsigned int reg; 3839 int ret, i; 3840 3841 wm8994->hubs.codec = codec; 3842 codec->control_data = control->regmap; 3843 3844 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 3845 3846 mutex_init(&wm8994->accdet_lock); 3847 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 3848 wm1811_jackdet_bootstrap); 3849 3850 switch (control->type) { 3851 case WM8994: 3852 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 3853 break; 3854 case WM1811: 3855 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 3856 break; 3857 default: 3858 break; 3859 } 3860 3861 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 3862 init_completion(&wm8994->fll_locked[i]); 3863 3864 wm8994->micdet_irq = control->pdata.micdet_irq; 3865 3866 pm_runtime_enable(codec->dev); 3867 pm_runtime_idle(codec->dev); 3868 3869 /* By default use idle_bias_off, will override for WM8994 */ 3870 codec->dapm.idle_bias_off = 1; 3871 3872 /* Set revision-specific configuration */ 3873 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 3874 switch (control->type) { 3875 case WM8994: 3876 /* Single ended line outputs should have VMID on. */ 3877 if (!control->pdata.lineout1_diff || 3878 !control->pdata.lineout2_diff) 3879 codec->dapm.idle_bias_off = 0; 3880 3881 switch (wm8994->revision) { 3882 case 2: 3883 case 3: 3884 wm8994->hubs.dcs_codes_l = -5; 3885 wm8994->hubs.dcs_codes_r = -5; 3886 wm8994->hubs.hp_startup_mode = 1; 3887 wm8994->hubs.dcs_readback_mode = 1; 3888 wm8994->hubs.series_startup = 1; 3889 break; 3890 default: 3891 wm8994->hubs.dcs_readback_mode = 2; 3892 break; 3893 } 3894 break; 3895 3896 case WM8958: 3897 wm8994->hubs.dcs_readback_mode = 1; 3898 wm8994->hubs.hp_startup_mode = 1; 3899 3900 switch (wm8994->revision) { 3901 case 0: 3902 break; 3903 default: 3904 wm8994->fll_byp = true; 3905 break; 3906 } 3907 break; 3908 3909 case WM1811: 3910 wm8994->hubs.dcs_readback_mode = 2; 3911 wm8994->hubs.no_series_update = 1; 3912 wm8994->hubs.hp_startup_mode = 1; 3913 wm8994->hubs.no_cache_dac_hp_direct = true; 3914 wm8994->fll_byp = true; 3915 3916 wm8994->hubs.dcs_codes_l = -9; 3917 wm8994->hubs.dcs_codes_r = -7; 3918 3919 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1, 3920 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 3921 break; 3922 3923 default: 3924 break; 3925 } 3926 3927 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 3928 wm8994_fifo_error, "FIFO error", codec); 3929 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 3930 wm8994_temp_warn, "Thermal warning", codec); 3931 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 3932 wm8994_temp_shut, "Thermal shutdown", codec); 3933 3934 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 3935 wm_hubs_dcs_done, "DC servo done", 3936 &wm8994->hubs); 3937 if (ret == 0) 3938 wm8994->hubs.dcs_done_irq = true; 3939 3940 switch (control->type) { 3941 case WM8994: 3942 if (wm8994->micdet_irq) { 3943 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3944 wm8994_mic_irq, 3945 IRQF_TRIGGER_RISING, 3946 "Mic1 detect", 3947 wm8994); 3948 if (ret != 0) 3949 dev_warn(codec->dev, 3950 "Failed to request Mic1 detect IRQ: %d\n", 3951 ret); 3952 } 3953 3954 ret = wm8994_request_irq(wm8994->wm8994, 3955 WM8994_IRQ_MIC1_SHRT, 3956 wm8994_mic_irq, "Mic 1 short", 3957 wm8994); 3958 if (ret != 0) 3959 dev_warn(codec->dev, 3960 "Failed to request Mic1 short IRQ: %d\n", 3961 ret); 3962 3963 ret = wm8994_request_irq(wm8994->wm8994, 3964 WM8994_IRQ_MIC2_DET, 3965 wm8994_mic_irq, "Mic 2 detect", 3966 wm8994); 3967 if (ret != 0) 3968 dev_warn(codec->dev, 3969 "Failed to request Mic2 detect IRQ: %d\n", 3970 ret); 3971 3972 ret = wm8994_request_irq(wm8994->wm8994, 3973 WM8994_IRQ_MIC2_SHRT, 3974 wm8994_mic_irq, "Mic 2 short", 3975 wm8994); 3976 if (ret != 0) 3977 dev_warn(codec->dev, 3978 "Failed to request Mic2 short IRQ: %d\n", 3979 ret); 3980 break; 3981 3982 case WM8958: 3983 case WM1811: 3984 if (wm8994->micdet_irq) { 3985 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3986 wm8958_mic_irq, 3987 IRQF_TRIGGER_RISING, 3988 "Mic detect", 3989 wm8994); 3990 if (ret != 0) 3991 dev_warn(codec->dev, 3992 "Failed to request Mic detect IRQ: %d\n", 3993 ret); 3994 } else { 3995 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 3996 wm8958_mic_irq, "Mic detect", 3997 wm8994); 3998 } 3999 } 4000 4001 switch (control->type) { 4002 case WM1811: 4003 if (control->cust_id > 1 || wm8994->revision > 1) { 4004 ret = wm8994_request_irq(wm8994->wm8994, 4005 WM8994_IRQ_GPIO(6), 4006 wm1811_jackdet_irq, "JACKDET", 4007 wm8994); 4008 if (ret == 0) 4009 wm8994->jackdet = true; 4010 } 4011 break; 4012 default: 4013 break; 4014 } 4015 4016 wm8994->fll_locked_irq = true; 4017 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4018 ret = wm8994_request_irq(wm8994->wm8994, 4019 WM8994_IRQ_FLL1_LOCK + i, 4020 wm8994_fll_locked_irq, "FLL lock", 4021 &wm8994->fll_locked[i]); 4022 if (ret != 0) 4023 wm8994->fll_locked_irq = false; 4024 } 4025 4026 /* Make sure we can read from the GPIOs if they're inputs */ 4027 pm_runtime_get_sync(codec->dev); 4028 4029 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4030 * configured on init - if a system wants to do this dynamically 4031 * at runtime we can deal with that then. 4032 */ 4033 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4034 if (ret < 0) { 4035 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 4036 goto err_irq; 4037 } 4038 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4039 wm8994->lrclk_shared[0] = 1; 4040 wm8994_dai[0].symmetric_rates = 1; 4041 } else { 4042 wm8994->lrclk_shared[0] = 0; 4043 } 4044 4045 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4046 if (ret < 0) { 4047 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 4048 goto err_irq; 4049 } 4050 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4051 wm8994->lrclk_shared[1] = 1; 4052 wm8994_dai[1].symmetric_rates = 1; 4053 } else { 4054 wm8994->lrclk_shared[1] = 0; 4055 } 4056 4057 pm_runtime_put(codec->dev); 4058 4059 /* Latch volume update bits */ 4060 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4061 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg, 4062 wm8994_vu_bits[i].mask, 4063 wm8994_vu_bits[i].mask); 4064 4065 /* Set the low bit of the 3D stereo depth so TLV matches */ 4066 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 4067 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4068 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4069 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 4070 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4071 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4072 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 4073 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4074 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4075 4076 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4077 * use this; it only affects behaviour on idle TDM clock 4078 * cycles. */ 4079 switch (control->type) { 4080 case WM8994: 4081 case WM8958: 4082 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 4083 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4084 break; 4085 default: 4086 break; 4087 } 4088 4089 /* Put MICBIAS into bypass mode by default on newer devices */ 4090 switch (control->type) { 4091 case WM8958: 4092 case WM1811: 4093 snd_soc_update_bits(codec, WM8958_MICBIAS1, 4094 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4095 snd_soc_update_bits(codec, WM8958_MICBIAS2, 4096 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4097 break; 4098 default: 4099 break; 4100 } 4101 4102 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4103 wm_hubs_update_class_w(codec); 4104 4105 wm8994_handle_pdata(wm8994); 4106 4107 wm_hubs_add_analogue_controls(codec); 4108 snd_soc_add_codec_controls(codec, wm8994_snd_controls, 4109 ARRAY_SIZE(wm8994_snd_controls)); 4110 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4111 ARRAY_SIZE(wm8994_dapm_widgets)); 4112 4113 switch (control->type) { 4114 case WM8994: 4115 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4116 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4117 if (wm8994->revision < 4) { 4118 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4119 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4120 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4121 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4122 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4123 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4124 } else { 4125 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4126 ARRAY_SIZE(wm8994_lateclk_widgets)); 4127 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4128 ARRAY_SIZE(wm8994_adc_widgets)); 4129 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4130 ARRAY_SIZE(wm8994_dac_widgets)); 4131 } 4132 break; 4133 case WM8958: 4134 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4135 ARRAY_SIZE(wm8958_snd_controls)); 4136 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4137 ARRAY_SIZE(wm8958_dapm_widgets)); 4138 if (wm8994->revision < 1) { 4139 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4140 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4141 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4142 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4143 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4144 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4145 } else { 4146 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4147 ARRAY_SIZE(wm8994_lateclk_widgets)); 4148 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4149 ARRAY_SIZE(wm8994_adc_widgets)); 4150 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4151 ARRAY_SIZE(wm8994_dac_widgets)); 4152 } 4153 break; 4154 4155 case WM1811: 4156 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4157 ARRAY_SIZE(wm8958_snd_controls)); 4158 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4159 ARRAY_SIZE(wm8958_dapm_widgets)); 4160 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4161 ARRAY_SIZE(wm8994_lateclk_widgets)); 4162 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4163 ARRAY_SIZE(wm8994_adc_widgets)); 4164 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4165 ARRAY_SIZE(wm8994_dac_widgets)); 4166 break; 4167 } 4168 4169 wm_hubs_add_analogue_routes(codec, 0, 0); 4170 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4171 4172 switch (control->type) { 4173 case WM8994: 4174 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4175 ARRAY_SIZE(wm8994_intercon)); 4176 4177 if (wm8994->revision < 4) { 4178 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4179 ARRAY_SIZE(wm8994_revd_intercon)); 4180 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4181 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4182 } else { 4183 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4184 ARRAY_SIZE(wm8994_lateclk_intercon)); 4185 } 4186 break; 4187 case WM8958: 4188 if (wm8994->revision < 1) { 4189 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4190 ARRAY_SIZE(wm8994_intercon)); 4191 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4192 ARRAY_SIZE(wm8994_revd_intercon)); 4193 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4194 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4195 } else { 4196 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4197 ARRAY_SIZE(wm8994_lateclk_intercon)); 4198 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4199 ARRAY_SIZE(wm8958_intercon)); 4200 } 4201 4202 wm8958_dsp2_init(codec); 4203 break; 4204 case WM1811: 4205 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4206 ARRAY_SIZE(wm8994_lateclk_intercon)); 4207 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4208 ARRAY_SIZE(wm8958_intercon)); 4209 break; 4210 } 4211 4212 return 0; 4213 4214 err_irq: 4215 if (wm8994->jackdet) 4216 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4217 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4218 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4219 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4220 if (wm8994->micdet_irq) 4221 free_irq(wm8994->micdet_irq, wm8994); 4222 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4223 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4224 &wm8994->fll_locked[i]); 4225 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4226 &wm8994->hubs); 4227 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4228 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4229 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4230 4231 return ret; 4232 } 4233 4234 static int wm8994_codec_remove(struct snd_soc_codec *codec) 4235 { 4236 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 4237 struct wm8994 *control = wm8994->wm8994; 4238 int i; 4239 4240 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 4241 4242 pm_runtime_disable(codec->dev); 4243 4244 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4245 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4246 &wm8994->fll_locked[i]); 4247 4248 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4249 &wm8994->hubs); 4250 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4251 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4252 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4253 4254 if (wm8994->jackdet) 4255 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4256 4257 switch (control->type) { 4258 case WM8994: 4259 if (wm8994->micdet_irq) 4260 free_irq(wm8994->micdet_irq, wm8994); 4261 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4262 wm8994); 4263 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4264 wm8994); 4265 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4266 wm8994); 4267 break; 4268 4269 case WM1811: 4270 case WM8958: 4271 if (wm8994->micdet_irq) 4272 free_irq(wm8994->micdet_irq, wm8994); 4273 break; 4274 } 4275 release_firmware(wm8994->mbc); 4276 release_firmware(wm8994->mbc_vss); 4277 release_firmware(wm8994->enh_eq); 4278 kfree(wm8994->retune_mobile_texts); 4279 return 0; 4280 } 4281 4282 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 4283 .probe = wm8994_codec_probe, 4284 .remove = wm8994_codec_remove, 4285 .suspend = wm8994_codec_suspend, 4286 .resume = wm8994_codec_resume, 4287 .set_bias_level = wm8994_set_bias_level, 4288 }; 4289 4290 static int wm8994_probe(struct platform_device *pdev) 4291 { 4292 struct wm8994_priv *wm8994; 4293 4294 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4295 GFP_KERNEL); 4296 if (wm8994 == NULL) 4297 return -ENOMEM; 4298 platform_set_drvdata(pdev, wm8994); 4299 4300 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4301 4302 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 4303 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4304 } 4305 4306 static int wm8994_remove(struct platform_device *pdev) 4307 { 4308 snd_soc_unregister_codec(&pdev->dev); 4309 return 0; 4310 } 4311 4312 #ifdef CONFIG_PM_SLEEP 4313 static int wm8994_suspend(struct device *dev) 4314 { 4315 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4316 4317 /* Drop down to power saving mode when system is suspended */ 4318 if (wm8994->jackdet && !wm8994->active_refcount) 4319 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4320 WM1811_JACKDET_MODE_MASK, 4321 wm8994->jackdet_mode); 4322 4323 return 0; 4324 } 4325 4326 static int wm8994_resume(struct device *dev) 4327 { 4328 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4329 4330 if (wm8994->jackdet && wm8994->jackdet_mode) 4331 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4332 WM1811_JACKDET_MODE_MASK, 4333 WM1811_JACKDET_MODE_AUDIO); 4334 4335 return 0; 4336 } 4337 #endif 4338 4339 static const struct dev_pm_ops wm8994_pm_ops = { 4340 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4341 }; 4342 4343 static struct platform_driver wm8994_codec_driver = { 4344 .driver = { 4345 .name = "wm8994-codec", 4346 .owner = THIS_MODULE, 4347 .pm = &wm8994_pm_ops, 4348 }, 4349 .probe = wm8994_probe, 4350 .remove = wm8994_remove, 4351 }; 4352 4353 module_platform_driver(wm8994_codec_driver); 4354 4355 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4356 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4357 MODULE_LICENSE("GPL"); 4358 MODULE_ALIAS("platform:wm8994-codec"); 4359