1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <sound/core.h> 25 #include <sound/jack.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <trace/events/asoc.h> 32 33 #include <linux/mfd/wm8994/core.h> 34 #include <linux/mfd/wm8994/registers.h> 35 #include <linux/mfd/wm8994/pdata.h> 36 #include <linux/mfd/wm8994/gpio.h> 37 38 #include "wm8994.h" 39 #include "wm_hubs.h" 40 41 #define WM1811_JACKDET_MODE_NONE 0x0000 42 #define WM1811_JACKDET_MODE_JACK 0x0100 43 #define WM1811_JACKDET_MODE_MIC 0x0080 44 #define WM1811_JACKDET_MODE_AUDIO 0x0180 45 46 #define WM8994_NUM_DRC 3 47 #define WM8994_NUM_EQ 3 48 49 static struct { 50 unsigned int reg; 51 unsigned int mask; 52 } wm8994_vu_bits[] = { 53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 63 64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 80 }; 81 82 static int wm8994_drc_base[] = { 83 WM8994_AIF1_DRC1_1, 84 WM8994_AIF1_DRC2_1, 85 WM8994_AIF2_DRC_1, 86 }; 87 88 static int wm8994_retune_mobile_base[] = { 89 WM8994_AIF1_DAC1_EQ_GAINS_1, 90 WM8994_AIF1_DAC2_EQ_GAINS_1, 91 WM8994_AIF2_EQ_GAINS_1, 92 }; 93 94 static void wm8958_default_micdet(u16 status, void *data); 95 96 static const struct wm8958_micd_rate micdet_rates[] = { 97 { 32768, true, 1, 4 }, 98 { 32768, false, 1, 1 }, 99 { 44100 * 256, true, 7, 10 }, 100 { 44100 * 256, false, 7, 10 }, 101 }; 102 103 static const struct wm8958_micd_rate jackdet_rates[] = { 104 { 32768, true, 0, 1 }, 105 { 32768, false, 0, 1 }, 106 { 44100 * 256, true, 10, 10 }, 107 { 44100 * 256, false, 7, 8 }, 108 }; 109 110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec) 111 { 112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 113 struct wm8994 *control = wm8994->wm8994; 114 int best, i, sysclk, val; 115 bool idle; 116 const struct wm8958_micd_rate *rates; 117 int num_rates; 118 119 if (wm8994->jack_cb != wm8958_default_micdet) 120 return; 121 122 idle = !wm8994->jack_mic; 123 124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1); 125 if (sysclk & WM8994_SYSCLK_SRC) 126 sysclk = wm8994->aifclk[1]; 127 else 128 sysclk = wm8994->aifclk[0]; 129 130 if (control->pdata.micd_rates) { 131 rates = control->pdata.micd_rates; 132 num_rates = control->pdata.num_micd_rates; 133 } else if (wm8994->jackdet) { 134 rates = jackdet_rates; 135 num_rates = ARRAY_SIZE(jackdet_rates); 136 } else { 137 rates = micdet_rates; 138 num_rates = ARRAY_SIZE(micdet_rates); 139 } 140 141 best = 0; 142 for (i = 0; i < num_rates; i++) { 143 if (rates[i].idle != idle) 144 continue; 145 if (abs(rates[i].sysclk - sysclk) < 146 abs(rates[best].sysclk - sysclk)) 147 best = i; 148 else if (rates[best].idle != idle) 149 best = i; 150 } 151 152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 153 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 154 155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n", 156 rates[best].start, rates[best].rate, sysclk, 157 idle ? "idle" : "active"); 158 159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 160 WM8958_MICD_BIAS_STARTTIME_MASK | 161 WM8958_MICD_RATE_MASK, val); 162 } 163 164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 165 { 166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 167 int rate; 168 int reg1 = 0; 169 int offset; 170 171 if (aif) 172 offset = 4; 173 else 174 offset = 0; 175 176 switch (wm8994->sysclk[aif]) { 177 case WM8994_SYSCLK_MCLK1: 178 rate = wm8994->mclk[0]; 179 break; 180 181 case WM8994_SYSCLK_MCLK2: 182 reg1 |= 0x8; 183 rate = wm8994->mclk[1]; 184 break; 185 186 case WM8994_SYSCLK_FLL1: 187 reg1 |= 0x10; 188 rate = wm8994->fll[0].out; 189 break; 190 191 case WM8994_SYSCLK_FLL2: 192 reg1 |= 0x18; 193 rate = wm8994->fll[1].out; 194 break; 195 196 default: 197 return -EINVAL; 198 } 199 200 if (rate >= 13500000) { 201 rate /= 2; 202 reg1 |= WM8994_AIF1CLK_DIV; 203 204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 205 aif + 1, rate); 206 } 207 208 wm8994->aifclk[aif] = rate; 209 210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 212 reg1); 213 214 return 0; 215 } 216 217 static int configure_clock(struct snd_soc_codec *codec) 218 { 219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 220 int change, new; 221 222 /* Bring up the AIF clocks first */ 223 configure_aif_clock(codec, 0); 224 configure_aif_clock(codec, 1); 225 226 /* Then switch CLK_SYS over to the higher of them; a change 227 * can only happen as a result of a clocking change which can 228 * only be made outside of DAPM so we can safely redo the 229 * clocking. 230 */ 231 232 /* If they're equal it doesn't matter which is used */ 233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 234 wm8958_micd_set_rate(codec); 235 return 0; 236 } 237 238 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 239 new = WM8994_SYSCLK_SRC; 240 else 241 new = 0; 242 243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1, 244 WM8994_SYSCLK_SRC, new); 245 if (change) 246 snd_soc_dapm_sync(&codec->dapm); 247 248 wm8958_micd_set_rate(codec); 249 250 return 0; 251 } 252 253 static int check_clk_sys(struct snd_soc_dapm_widget *source, 254 struct snd_soc_dapm_widget *sink) 255 { 256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 257 const char *clk; 258 259 /* Check what we're currently using for CLK_SYS */ 260 if (reg & WM8994_SYSCLK_SRC) 261 clk = "AIF2CLK"; 262 else 263 clk = "AIF1CLK"; 264 265 return strcmp(source->name, clk) == 0; 266 } 267 268 static const char *sidetone_hpf_text[] = { 269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 270 }; 271 272 static const struct soc_enum sidetone_hpf = 273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 274 275 static const char *adc_hpf_text[] = { 276 "HiFi", "Voice 1", "Voice 2", "Voice 3" 277 }; 278 279 static const struct soc_enum aif1adc1_hpf = 280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); 281 282 static const struct soc_enum aif1adc2_hpf = 283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); 284 285 static const struct soc_enum aif2adc_hpf = 286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); 287 288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); 295 296 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 299 .put = wm8994_put_drc_sw, \ 300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 301 302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 303 struct snd_ctl_elem_value *ucontrol) 304 { 305 struct soc_mixer_control *mc = 306 (struct soc_mixer_control *)kcontrol->private_value; 307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 308 int mask, ret; 309 310 /* Can't enable both ADC and DAC paths simultaneously */ 311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 313 WM8994_AIF1ADC1R_DRC_ENA_MASK; 314 else 315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 316 317 ret = snd_soc_read(codec, mc->reg); 318 if (ret < 0) 319 return ret; 320 if (ret & mask) 321 return -EINVAL; 322 323 return snd_soc_put_volsw(kcontrol, ucontrol); 324 } 325 326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 327 { 328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 329 struct wm8994 *control = wm8994->wm8994; 330 struct wm8994_pdata *pdata = &control->pdata; 331 int base = wm8994_drc_base[drc]; 332 int cfg = wm8994->drc_cfg[drc]; 333 int save, i; 334 335 /* Save any enables; the configuration should clear them. */ 336 save = snd_soc_read(codec, base); 337 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 338 WM8994_AIF1ADC1R_DRC_ENA; 339 340 for (i = 0; i < WM8994_DRC_REGS; i++) 341 snd_soc_update_bits(codec, base + i, 0xffff, 342 pdata->drc_cfgs[cfg].regs[i]); 343 344 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 345 WM8994_AIF1ADC1L_DRC_ENA | 346 WM8994_AIF1ADC1R_DRC_ENA, save); 347 } 348 349 /* Icky as hell but saves code duplication */ 350 static int wm8994_get_drc(const char *name) 351 { 352 if (strcmp(name, "AIF1DRC1 Mode") == 0) 353 return 0; 354 if (strcmp(name, "AIF1DRC2 Mode") == 0) 355 return 1; 356 if (strcmp(name, "AIF2DRC Mode") == 0) 357 return 2; 358 return -EINVAL; 359 } 360 361 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 362 struct snd_ctl_elem_value *ucontrol) 363 { 364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 365 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 366 struct wm8994 *control = wm8994->wm8994; 367 struct wm8994_pdata *pdata = &control->pdata; 368 int drc = wm8994_get_drc(kcontrol->id.name); 369 int value = ucontrol->value.integer.value[0]; 370 371 if (drc < 0) 372 return drc; 373 374 if (value >= pdata->num_drc_cfgs) 375 return -EINVAL; 376 377 wm8994->drc_cfg[drc] = value; 378 379 wm8994_set_drc(codec, drc); 380 381 return 0; 382 } 383 384 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 385 struct snd_ctl_elem_value *ucontrol) 386 { 387 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 388 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 389 int drc = wm8994_get_drc(kcontrol->id.name); 390 391 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 392 393 return 0; 394 } 395 396 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 397 { 398 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 399 struct wm8994 *control = wm8994->wm8994; 400 struct wm8994_pdata *pdata = &control->pdata; 401 int base = wm8994_retune_mobile_base[block]; 402 int iface, best, best_val, save, i, cfg; 403 404 if (!pdata || !wm8994->num_retune_mobile_texts) 405 return; 406 407 switch (block) { 408 case 0: 409 case 1: 410 iface = 0; 411 break; 412 case 2: 413 iface = 1; 414 break; 415 default: 416 return; 417 } 418 419 /* Find the version of the currently selected configuration 420 * with the nearest sample rate. */ 421 cfg = wm8994->retune_mobile_cfg[block]; 422 best = 0; 423 best_val = INT_MAX; 424 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 425 if (strcmp(pdata->retune_mobile_cfgs[i].name, 426 wm8994->retune_mobile_texts[cfg]) == 0 && 427 abs(pdata->retune_mobile_cfgs[i].rate 428 - wm8994->dac_rates[iface]) < best_val) { 429 best = i; 430 best_val = abs(pdata->retune_mobile_cfgs[i].rate 431 - wm8994->dac_rates[iface]); 432 } 433 } 434 435 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 436 block, 437 pdata->retune_mobile_cfgs[best].name, 438 pdata->retune_mobile_cfgs[best].rate, 439 wm8994->dac_rates[iface]); 440 441 /* The EQ will be disabled while reconfiguring it, remember the 442 * current configuration. 443 */ 444 save = snd_soc_read(codec, base); 445 save &= WM8994_AIF1DAC1_EQ_ENA; 446 447 for (i = 0; i < WM8994_EQ_REGS; i++) 448 snd_soc_update_bits(codec, base + i, 0xffff, 449 pdata->retune_mobile_cfgs[best].regs[i]); 450 451 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 452 } 453 454 /* Icky as hell but saves code duplication */ 455 static int wm8994_get_retune_mobile_block(const char *name) 456 { 457 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 458 return 0; 459 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 460 return 1; 461 if (strcmp(name, "AIF2 EQ Mode") == 0) 462 return 2; 463 return -EINVAL; 464 } 465 466 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_value *ucontrol) 468 { 469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 470 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 471 struct wm8994 *control = wm8994->wm8994; 472 struct wm8994_pdata *pdata = &control->pdata; 473 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 474 int value = ucontrol->value.integer.value[0]; 475 476 if (block < 0) 477 return block; 478 479 if (value >= pdata->num_retune_mobile_cfgs) 480 return -EINVAL; 481 482 wm8994->retune_mobile_cfg[block] = value; 483 484 wm8994_set_retune_mobile(codec, block); 485 486 return 0; 487 } 488 489 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 490 struct snd_ctl_elem_value *ucontrol) 491 { 492 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 493 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 494 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 495 496 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 497 498 return 0; 499 } 500 501 static const char *aif_chan_src_text[] = { 502 "Left", "Right" 503 }; 504 505 static const struct soc_enum aif1adcl_src = 506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); 507 508 static const struct soc_enum aif1adcr_src = 509 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); 510 511 static const struct soc_enum aif2adcl_src = 512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); 513 514 static const struct soc_enum aif2adcr_src = 515 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); 516 517 static const struct soc_enum aif1dacl_src = 518 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); 519 520 static const struct soc_enum aif1dacr_src = 521 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); 522 523 static const struct soc_enum aif2dacl_src = 524 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); 525 526 static const struct soc_enum aif2dacr_src = 527 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); 528 529 static const char *osr_text[] = { 530 "Low Power", "High Performance", 531 }; 532 533 static const struct soc_enum dac_osr = 534 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); 535 536 static const struct soc_enum adc_osr = 537 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); 538 539 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 540 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 541 WM8994_AIF1_ADC1_RIGHT_VOLUME, 542 1, 119, 0, digital_tlv), 543 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 544 WM8994_AIF1_ADC2_RIGHT_VOLUME, 545 1, 119, 0, digital_tlv), 546 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 547 WM8994_AIF2_ADC_RIGHT_VOLUME, 548 1, 119, 0, digital_tlv), 549 550 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 551 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 552 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 553 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 554 555 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 556 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 557 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 558 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 559 560 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 562 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 563 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 564 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 565 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 566 567 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 568 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 569 570 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 571 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 572 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 573 574 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 575 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 576 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 577 578 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 579 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 580 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 581 582 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 583 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 584 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 585 586 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 587 5, 12, 0, st_tlv), 588 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 589 0, 12, 0, st_tlv), 590 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 591 5, 12, 0, st_tlv), 592 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 593 0, 12, 0, st_tlv), 594 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 595 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 596 597 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 598 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 599 600 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 601 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 602 603 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 604 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 605 606 SOC_ENUM("ADC OSR", adc_osr), 607 SOC_ENUM("DAC OSR", dac_osr), 608 609 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 610 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 611 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 612 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 613 614 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 615 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 616 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 617 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 618 619 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 620 6, 1, 1, wm_hubs_spkmix_tlv), 621 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 622 2, 1, 1, wm_hubs_spkmix_tlv), 623 624 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 625 6, 1, 1, wm_hubs_spkmix_tlv), 626 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 627 2, 1, 1, wm_hubs_spkmix_tlv), 628 629 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 630 10, 15, 0, wm8994_3d_tlv), 631 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 632 8, 1, 0), 633 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 634 10, 15, 0, wm8994_3d_tlv), 635 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 636 8, 1, 0), 637 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 638 10, 15, 0, wm8994_3d_tlv), 639 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 640 8, 1, 0), 641 }; 642 643 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 644 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 645 eq_tlv), 646 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 647 eq_tlv), 648 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 649 eq_tlv), 650 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 651 eq_tlv), 652 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 653 eq_tlv), 654 655 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 656 eq_tlv), 657 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 658 eq_tlv), 659 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 660 eq_tlv), 661 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 662 eq_tlv), 663 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 664 eq_tlv), 665 666 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 667 eq_tlv), 668 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 669 eq_tlv), 670 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 671 eq_tlv), 672 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 673 eq_tlv), 674 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 675 eq_tlv), 676 }; 677 678 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 679 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 680 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 681 WM8994_AIF1ADC1R_DRC_ENA), 682 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 683 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 684 WM8994_AIF1ADC2R_DRC_ENA), 685 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 686 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 687 WM8994_AIF2ADCR_DRC_ENA), 688 }; 689 690 static const char *wm8958_ng_text[] = { 691 "30ms", "125ms", "250ms", "500ms", 692 }; 693 694 static const struct soc_enum wm8958_aif1dac1_ng_hold = 695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE, 696 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text); 697 698 static const struct soc_enum wm8958_aif1dac2_ng_hold = 699 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE, 700 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text); 701 702 static const struct soc_enum wm8958_aif2dac_ng_hold = 703 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE, 704 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text); 705 706 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 707 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 708 709 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 710 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 711 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 712 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 713 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 714 7, 1, ng_tlv), 715 716 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 717 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 718 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 719 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 720 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 721 7, 1, ng_tlv), 722 723 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 724 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 725 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 726 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 727 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 728 7, 1, ng_tlv), 729 }; 730 731 static const struct snd_kcontrol_new wm1811_snd_controls[] = { 732 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, 733 mixin_boost_tlv), 734 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, 735 mixin_boost_tlv), 736 }; 737 738 /* We run all mode setting through a function to enforce audio mode */ 739 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode) 740 { 741 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 742 743 if (!wm8994->jackdet || !wm8994->jack_cb) 744 return; 745 746 if (wm8994->active_refcount) 747 mode = WM1811_JACKDET_MODE_AUDIO; 748 749 if (mode == wm8994->jackdet_mode) 750 return; 751 752 wm8994->jackdet_mode = mode; 753 754 /* Always use audio mode to detect while the system is active */ 755 if (mode != WM1811_JACKDET_MODE_NONE) 756 mode = WM1811_JACKDET_MODE_AUDIO; 757 758 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 759 WM1811_JACKDET_MODE_MASK, mode); 760 } 761 762 static void active_reference(struct snd_soc_codec *codec) 763 { 764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 765 766 mutex_lock(&wm8994->accdet_lock); 767 768 wm8994->active_refcount++; 769 770 dev_dbg(codec->dev, "Active refcount incremented, now %d\n", 771 wm8994->active_refcount); 772 773 /* If we're using jack detection go into audio mode */ 774 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO); 775 776 mutex_unlock(&wm8994->accdet_lock); 777 } 778 779 static void active_dereference(struct snd_soc_codec *codec) 780 { 781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 782 u16 mode; 783 784 mutex_lock(&wm8994->accdet_lock); 785 786 wm8994->active_refcount--; 787 788 dev_dbg(codec->dev, "Active refcount decremented, now %d\n", 789 wm8994->active_refcount); 790 791 if (wm8994->active_refcount == 0) { 792 /* Go into appropriate detection only mode */ 793 if (wm8994->jack_mic || wm8994->mic_detecting) 794 mode = WM1811_JACKDET_MODE_MIC; 795 else 796 mode = WM1811_JACKDET_MODE_JACK; 797 798 wm1811_jackdet_set_mode(codec, mode); 799 } 800 801 mutex_unlock(&wm8994->accdet_lock); 802 } 803 804 static int clk_sys_event(struct snd_soc_dapm_widget *w, 805 struct snd_kcontrol *kcontrol, int event) 806 { 807 struct snd_soc_codec *codec = w->codec; 808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 809 810 switch (event) { 811 case SND_SOC_DAPM_PRE_PMU: 812 return configure_clock(codec); 813 814 case SND_SOC_DAPM_POST_PMU: 815 /* 816 * JACKDET won't run until we start the clock and it 817 * only reports deltas, make sure we notify the state 818 * up the stack on startup. Use a *very* generous 819 * timeout for paranoia, there's no urgency and we 820 * don't want false reports. 821 */ 822 if (wm8994->jackdet && !wm8994->clk_has_run) { 823 schedule_delayed_work(&wm8994->jackdet_bootstrap, 824 msecs_to_jiffies(1000)); 825 wm8994->clk_has_run = true; 826 } 827 break; 828 829 case SND_SOC_DAPM_POST_PMD: 830 configure_clock(codec); 831 break; 832 } 833 834 return 0; 835 } 836 837 static void vmid_reference(struct snd_soc_codec *codec) 838 { 839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 840 841 pm_runtime_get_sync(codec->dev); 842 843 wm8994->vmid_refcount++; 844 845 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", 846 wm8994->vmid_refcount); 847 848 if (wm8994->vmid_refcount == 1) { 849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 850 WM8994_LINEOUT1_DISCH | 851 WM8994_LINEOUT2_DISCH, 0); 852 853 wm_hubs_vmid_ena(codec); 854 855 switch (wm8994->vmid_mode) { 856 default: 857 WARN_ON(NULL == "Invalid VMID mode"); 858 case WM8994_VMID_NORMAL: 859 /* Startup bias, VMID ramp & buffer */ 860 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 861 WM8994_BIAS_SRC | 862 WM8994_VMID_DISCH | 863 WM8994_STARTUP_BIAS_ENA | 864 WM8994_VMID_BUF_ENA | 865 WM8994_VMID_RAMP_MASK, 866 WM8994_BIAS_SRC | 867 WM8994_STARTUP_BIAS_ENA | 868 WM8994_VMID_BUF_ENA | 869 (0x2 << WM8994_VMID_RAMP_SHIFT)); 870 871 /* Main bias enable, VMID=2x40k */ 872 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 873 WM8994_BIAS_ENA | 874 WM8994_VMID_SEL_MASK, 875 WM8994_BIAS_ENA | 0x2); 876 877 msleep(300); 878 879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 880 WM8994_VMID_RAMP_MASK | 881 WM8994_BIAS_SRC, 882 0); 883 break; 884 885 case WM8994_VMID_FORCE: 886 /* Startup bias, slow VMID ramp & buffer */ 887 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 888 WM8994_BIAS_SRC | 889 WM8994_VMID_DISCH | 890 WM8994_STARTUP_BIAS_ENA | 891 WM8994_VMID_BUF_ENA | 892 WM8994_VMID_RAMP_MASK, 893 WM8994_BIAS_SRC | 894 WM8994_STARTUP_BIAS_ENA | 895 WM8994_VMID_BUF_ENA | 896 (0x2 << WM8994_VMID_RAMP_SHIFT)); 897 898 /* Main bias enable, VMID=2x40k */ 899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 900 WM8994_BIAS_ENA | 901 WM8994_VMID_SEL_MASK, 902 WM8994_BIAS_ENA | 0x2); 903 904 msleep(400); 905 906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 907 WM8994_VMID_RAMP_MASK | 908 WM8994_BIAS_SRC, 909 0); 910 break; 911 } 912 } 913 } 914 915 static void vmid_dereference(struct snd_soc_codec *codec) 916 { 917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 918 919 wm8994->vmid_refcount--; 920 921 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", 922 wm8994->vmid_refcount); 923 924 if (wm8994->vmid_refcount == 0) { 925 if (wm8994->hubs.lineout1_se) 926 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 927 WM8994_LINEOUT1N_ENA | 928 WM8994_LINEOUT1P_ENA, 929 WM8994_LINEOUT1N_ENA | 930 WM8994_LINEOUT1P_ENA); 931 932 if (wm8994->hubs.lineout2_se) 933 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 934 WM8994_LINEOUT2N_ENA | 935 WM8994_LINEOUT2P_ENA, 936 WM8994_LINEOUT2N_ENA | 937 WM8994_LINEOUT2P_ENA); 938 939 /* Start discharging VMID */ 940 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 941 WM8994_BIAS_SRC | 942 WM8994_VMID_DISCH, 943 WM8994_BIAS_SRC | 944 WM8994_VMID_DISCH); 945 946 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 947 WM8994_VMID_SEL_MASK, 0); 948 949 msleep(400); 950 951 /* Active discharge */ 952 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 953 WM8994_LINEOUT1_DISCH | 954 WM8994_LINEOUT2_DISCH, 955 WM8994_LINEOUT1_DISCH | 956 WM8994_LINEOUT2_DISCH); 957 958 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, 959 WM8994_LINEOUT1N_ENA | 960 WM8994_LINEOUT1P_ENA | 961 WM8994_LINEOUT2N_ENA | 962 WM8994_LINEOUT2P_ENA, 0); 963 964 /* Switch off startup biases */ 965 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 966 WM8994_BIAS_SRC | 967 WM8994_STARTUP_BIAS_ENA | 968 WM8994_VMID_BUF_ENA | 969 WM8994_VMID_RAMP_MASK, 0); 970 971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 972 WM8994_VMID_SEL_MASK, 0); 973 } 974 975 pm_runtime_put(codec->dev); 976 } 977 978 static int vmid_event(struct snd_soc_dapm_widget *w, 979 struct snd_kcontrol *kcontrol, int event) 980 { 981 struct snd_soc_codec *codec = w->codec; 982 983 switch (event) { 984 case SND_SOC_DAPM_PRE_PMU: 985 vmid_reference(codec); 986 break; 987 988 case SND_SOC_DAPM_POST_PMD: 989 vmid_dereference(codec); 990 break; 991 } 992 993 return 0; 994 } 995 996 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec) 997 { 998 int source = 0; /* GCC flow analysis can't track enable */ 999 int reg, reg_r; 1000 1001 /* We also need the same AIF source for L/R and only one path */ 1002 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 1003 switch (reg) { 1004 case WM8994_AIF2DACL_TO_DAC1L: 1005 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 1006 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1007 break; 1008 case WM8994_AIF1DAC2L_TO_DAC1L: 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 1010 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1011 break; 1012 case WM8994_AIF1DAC1L_TO_DAC1L: 1013 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 1014 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1015 break; 1016 default: 1017 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 1018 return false; 1019 } 1020 1021 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1022 if (reg_r != reg) { 1023 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 1024 return false; 1025 } 1026 1027 /* Set the source up */ 1028 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1029 WM8994_CP_DYN_SRC_SEL_MASK, source); 1030 1031 return true; 1032 } 1033 1034 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1035 struct snd_kcontrol *kcontrol, int event) 1036 { 1037 struct snd_soc_codec *codec = w->codec; 1038 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1039 struct wm8994 *control = codec->control_data; 1040 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1041 int i; 1042 int dac; 1043 int adc; 1044 int val; 1045 1046 switch (control->type) { 1047 case WM8994: 1048 case WM8958: 1049 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 switch (event) { 1056 case SND_SOC_DAPM_PRE_PMU: 1057 /* Don't enable timeslot 2 if not in use */ 1058 if (wm8994->channels[0] <= 2) 1059 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1060 1061 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1); 1062 if ((val & WM8994_AIF1ADCL_SRC) && 1063 (val & WM8994_AIF1ADCR_SRC)) 1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1065 else if (!(val & WM8994_AIF1ADCL_SRC) && 1066 !(val & WM8994_AIF1ADCR_SRC)) 1067 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1068 else 1069 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1070 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1071 1072 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2); 1073 if ((val & WM8994_AIF1DACL_SRC) && 1074 (val & WM8994_AIF1DACR_SRC)) 1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1076 else if (!(val & WM8994_AIF1DACL_SRC) && 1077 !(val & WM8994_AIF1DACR_SRC)) 1078 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1079 else 1080 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1081 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1082 1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1084 mask, adc); 1085 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1086 mask, dac); 1087 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1088 WM8994_AIF1DSPCLK_ENA | 1089 WM8994_SYSDSPCLK_ENA, 1090 WM8994_AIF1DSPCLK_ENA | 1091 WM8994_SYSDSPCLK_ENA); 1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask, 1093 WM8994_AIF1ADC1R_ENA | 1094 WM8994_AIF1ADC1L_ENA | 1095 WM8994_AIF1ADC2R_ENA | 1096 WM8994_AIF1ADC2L_ENA); 1097 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask, 1098 WM8994_AIF1DAC1R_ENA | 1099 WM8994_AIF1DAC1L_ENA | 1100 WM8994_AIF1DAC2R_ENA | 1101 WM8994_AIF1DAC2L_ENA); 1102 break; 1103 1104 case SND_SOC_DAPM_POST_PMU: 1105 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1106 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1107 snd_soc_read(codec, 1108 wm8994_vu_bits[i].reg)); 1109 break; 1110 1111 case SND_SOC_DAPM_PRE_PMD: 1112 case SND_SOC_DAPM_POST_PMD: 1113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1114 mask, 0); 1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1116 mask, 0); 1117 1118 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1119 if (val & WM8994_AIF2DSPCLK_ENA) 1120 val = WM8994_SYSDSPCLK_ENA; 1121 else 1122 val = 0; 1123 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1124 WM8994_SYSDSPCLK_ENA | 1125 WM8994_AIF1DSPCLK_ENA, val); 1126 break; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1133 struct snd_kcontrol *kcontrol, int event) 1134 { 1135 struct snd_soc_codec *codec = w->codec; 1136 int i; 1137 int dac; 1138 int adc; 1139 int val; 1140 1141 switch (event) { 1142 case SND_SOC_DAPM_PRE_PMU: 1143 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1); 1144 if ((val & WM8994_AIF2ADCL_SRC) && 1145 (val & WM8994_AIF2ADCR_SRC)) 1146 adc = WM8994_AIF2ADCR_ENA; 1147 else if (!(val & WM8994_AIF2ADCL_SRC) && 1148 !(val & WM8994_AIF2ADCR_SRC)) 1149 adc = WM8994_AIF2ADCL_ENA; 1150 else 1151 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1152 1153 1154 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2); 1155 if ((val & WM8994_AIF2DACL_SRC) && 1156 (val & WM8994_AIF2DACR_SRC)) 1157 dac = WM8994_AIF2DACR_ENA; 1158 else if (!(val & WM8994_AIF2DACL_SRC) && 1159 !(val & WM8994_AIF2DACR_SRC)) 1160 dac = WM8994_AIF2DACL_ENA; 1161 else 1162 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1163 1164 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1165 WM8994_AIF2ADCL_ENA | 1166 WM8994_AIF2ADCR_ENA, adc); 1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1168 WM8994_AIF2DACL_ENA | 1169 WM8994_AIF2DACR_ENA, dac); 1170 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1171 WM8994_AIF2DSPCLK_ENA | 1172 WM8994_SYSDSPCLK_ENA, 1173 WM8994_AIF2DSPCLK_ENA | 1174 WM8994_SYSDSPCLK_ENA); 1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1176 WM8994_AIF2ADCL_ENA | 1177 WM8994_AIF2ADCR_ENA, 1178 WM8994_AIF2ADCL_ENA | 1179 WM8994_AIF2ADCR_ENA); 1180 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1181 WM8994_AIF2DACL_ENA | 1182 WM8994_AIF2DACR_ENA, 1183 WM8994_AIF2DACL_ENA | 1184 WM8994_AIF2DACR_ENA); 1185 break; 1186 1187 case SND_SOC_DAPM_POST_PMU: 1188 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1189 snd_soc_write(codec, wm8994_vu_bits[i].reg, 1190 snd_soc_read(codec, 1191 wm8994_vu_bits[i].reg)); 1192 break; 1193 1194 case SND_SOC_DAPM_PRE_PMD: 1195 case SND_SOC_DAPM_POST_PMD: 1196 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1197 WM8994_AIF2DACL_ENA | 1198 WM8994_AIF2DACR_ENA, 0); 1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, 1200 WM8994_AIF2ADCL_ENA | 1201 WM8994_AIF2ADCR_ENA, 0); 1202 1203 val = snd_soc_read(codec, WM8994_CLOCKING_1); 1204 if (val & WM8994_AIF1DSPCLK_ENA) 1205 val = WM8994_SYSDSPCLK_ENA; 1206 else 1207 val = 0; 1208 snd_soc_update_bits(codec, WM8994_CLOCKING_1, 1209 WM8994_SYSDSPCLK_ENA | 1210 WM8994_AIF2DSPCLK_ENA, val); 1211 break; 1212 } 1213 1214 return 0; 1215 } 1216 1217 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1218 struct snd_kcontrol *kcontrol, int event) 1219 { 1220 struct snd_soc_codec *codec = w->codec; 1221 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1222 1223 switch (event) { 1224 case SND_SOC_DAPM_PRE_PMU: 1225 wm8994->aif1clk_enable = 1; 1226 break; 1227 case SND_SOC_DAPM_POST_PMD: 1228 wm8994->aif1clk_disable = 1; 1229 break; 1230 } 1231 1232 return 0; 1233 } 1234 1235 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1236 struct snd_kcontrol *kcontrol, int event) 1237 { 1238 struct snd_soc_codec *codec = w->codec; 1239 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1240 1241 switch (event) { 1242 case SND_SOC_DAPM_PRE_PMU: 1243 wm8994->aif2clk_enable = 1; 1244 break; 1245 case SND_SOC_DAPM_POST_PMD: 1246 wm8994->aif2clk_disable = 1; 1247 break; 1248 } 1249 1250 return 0; 1251 } 1252 1253 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1254 struct snd_kcontrol *kcontrol, int event) 1255 { 1256 struct snd_soc_codec *codec = w->codec; 1257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1258 1259 switch (event) { 1260 case SND_SOC_DAPM_PRE_PMU: 1261 if (wm8994->aif1clk_enable) { 1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1263 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1264 WM8994_AIF1CLK_ENA_MASK, 1265 WM8994_AIF1CLK_ENA); 1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1267 wm8994->aif1clk_enable = 0; 1268 } 1269 if (wm8994->aif2clk_enable) { 1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1271 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1272 WM8994_AIF2CLK_ENA_MASK, 1273 WM8994_AIF2CLK_ENA); 1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1275 wm8994->aif2clk_enable = 0; 1276 } 1277 break; 1278 } 1279 1280 /* We may also have postponed startup of DSP, handle that. */ 1281 wm8958_aif_ev(w, kcontrol, event); 1282 1283 return 0; 1284 } 1285 1286 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1287 struct snd_kcontrol *kcontrol, int event) 1288 { 1289 struct snd_soc_codec *codec = w->codec; 1290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1291 1292 switch (event) { 1293 case SND_SOC_DAPM_POST_PMD: 1294 if (wm8994->aif1clk_disable) { 1295 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1296 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1297 WM8994_AIF1CLK_ENA_MASK, 0); 1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1299 wm8994->aif1clk_disable = 0; 1300 } 1301 if (wm8994->aif2clk_disable) { 1302 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1303 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1304 WM8994_AIF2CLK_ENA_MASK, 0); 1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1306 wm8994->aif2clk_disable = 0; 1307 } 1308 break; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1315 struct snd_kcontrol *kcontrol, int event) 1316 { 1317 late_enable_ev(w, kcontrol, event); 1318 return 0; 1319 } 1320 1321 static int micbias_ev(struct snd_soc_dapm_widget *w, 1322 struct snd_kcontrol *kcontrol, int event) 1323 { 1324 late_enable_ev(w, kcontrol, event); 1325 return 0; 1326 } 1327 1328 static int dac_ev(struct snd_soc_dapm_widget *w, 1329 struct snd_kcontrol *kcontrol, int event) 1330 { 1331 struct snd_soc_codec *codec = w->codec; 1332 unsigned int mask = 1 << w->shift; 1333 1334 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 1335 mask, mask); 1336 return 0; 1337 } 1338 1339 static const char *adc_mux_text[] = { 1340 "ADC", 1341 "DMIC", 1342 }; 1343 1344 static const struct soc_enum adc_enum = 1345 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 1346 1347 static const struct snd_kcontrol_new adcl_mux = 1348 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1349 1350 static const struct snd_kcontrol_new adcr_mux = 1351 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1352 1353 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1354 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1355 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1356 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1357 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1358 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1359 }; 1360 1361 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1362 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1363 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1364 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1365 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1366 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1367 }; 1368 1369 /* Debugging; dump chip status after DAPM transitions */ 1370 static int post_ev(struct snd_soc_dapm_widget *w, 1371 struct snd_kcontrol *kcontrol, int event) 1372 { 1373 struct snd_soc_codec *codec = w->codec; 1374 dev_dbg(codec->dev, "SRC status: %x\n", 1375 snd_soc_read(codec, 1376 WM8994_RATE_STATUS)); 1377 return 0; 1378 } 1379 1380 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1381 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1382 1, 1, 0), 1383 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1384 0, 1, 0), 1385 }; 1386 1387 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1388 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1389 1, 1, 0), 1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1391 0, 1, 0), 1392 }; 1393 1394 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1395 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1396 1, 1, 0), 1397 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1398 0, 1, 0), 1399 }; 1400 1401 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1402 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1403 1, 1, 0), 1404 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1405 0, 1, 0), 1406 }; 1407 1408 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1409 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1410 5, 1, 0), 1411 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1412 4, 1, 0), 1413 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1414 2, 1, 0), 1415 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1416 1, 1, 0), 1417 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1418 0, 1, 0), 1419 }; 1420 1421 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1422 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1423 5, 1, 0), 1424 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1425 4, 1, 0), 1426 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1427 2, 1, 0), 1428 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1429 1, 1, 0), 1430 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1431 0, 1, 0), 1432 }; 1433 1434 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1435 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1436 .info = snd_soc_info_volsw, \ 1437 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 1438 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 1439 1440 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1441 struct snd_ctl_elem_value *ucontrol) 1442 { 1443 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 1444 struct snd_soc_dapm_widget *w = wlist->widgets[0]; 1445 struct snd_soc_codec *codec = w->codec; 1446 int ret; 1447 1448 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1449 1450 wm_hubs_update_class_w(codec); 1451 1452 return ret; 1453 } 1454 1455 static const struct snd_kcontrol_new dac1l_mix[] = { 1456 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1457 5, 1, 0), 1458 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1459 4, 1, 0), 1460 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1461 2, 1, 0), 1462 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1463 1, 1, 0), 1464 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1465 0, 1, 0), 1466 }; 1467 1468 static const struct snd_kcontrol_new dac1r_mix[] = { 1469 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1470 5, 1, 0), 1471 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1472 4, 1, 0), 1473 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1474 2, 1, 0), 1475 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1476 1, 1, 0), 1477 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1478 0, 1, 0), 1479 }; 1480 1481 static const char *sidetone_text[] = { 1482 "ADC/DMIC1", "DMIC2", 1483 }; 1484 1485 static const struct soc_enum sidetone1_enum = 1486 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 1487 1488 static const struct snd_kcontrol_new sidetone1_mux = 1489 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1490 1491 static const struct soc_enum sidetone2_enum = 1492 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 1493 1494 static const struct snd_kcontrol_new sidetone2_mux = 1495 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1496 1497 static const char *aif1dac_text[] = { 1498 "AIF1DACDAT", "AIF3DACDAT", 1499 }; 1500 1501 static const struct soc_enum aif1dac_enum = 1502 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 1503 1504 static const struct snd_kcontrol_new aif1dac_mux = 1505 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1506 1507 static const char *aif2dac_text[] = { 1508 "AIF2DACDAT", "AIF3DACDAT", 1509 }; 1510 1511 static const struct soc_enum aif2dac_enum = 1512 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 1513 1514 static const struct snd_kcontrol_new aif2dac_mux = 1515 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1516 1517 static const char *aif2adc_text[] = { 1518 "AIF2ADCDAT", "AIF3DACDAT", 1519 }; 1520 1521 static const struct soc_enum aif2adc_enum = 1522 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 1523 1524 static const struct snd_kcontrol_new aif2adc_mux = 1525 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1526 1527 static const char *aif3adc_text[] = { 1528 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1529 }; 1530 1531 static const struct soc_enum wm8994_aif3adc_enum = 1532 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1533 1534 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1535 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1536 1537 static const struct soc_enum wm8958_aif3adc_enum = 1538 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); 1539 1540 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1541 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1542 1543 static const char *mono_pcm_out_text[] = { 1544 "None", "AIF2ADCL", "AIF2ADCR", 1545 }; 1546 1547 static const struct soc_enum mono_pcm_out_enum = 1548 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); 1549 1550 static const struct snd_kcontrol_new mono_pcm_out_mux = 1551 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1552 1553 static const char *aif2dac_src_text[] = { 1554 "AIF2", "AIF3", 1555 }; 1556 1557 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1558 static const struct soc_enum aif2dacl_src_enum = 1559 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); 1560 1561 static const struct snd_kcontrol_new aif2dacl_src_mux = 1562 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1563 1564 static const struct soc_enum aif2dacr_src_enum = 1565 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); 1566 1567 static const struct snd_kcontrol_new aif2dacr_src_mux = 1568 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1569 1570 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1571 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1572 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1573 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1574 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1575 1576 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1577 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1578 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1580 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1581 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1582 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1583 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1584 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1586 1587 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1588 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1589 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1590 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1591 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1593 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1594 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1595 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1597 1598 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1599 }; 1600 1601 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1602 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1603 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1604 SND_SOC_DAPM_PRE_PMD), 1605 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1606 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1607 SND_SOC_DAPM_PRE_PMD), 1608 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1609 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1610 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1611 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1612 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1613 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1614 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1615 }; 1616 1617 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1618 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1619 dac_ev, SND_SOC_DAPM_PRE_PMU), 1620 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1621 dac_ev, SND_SOC_DAPM_PRE_PMU), 1622 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1623 dac_ev, SND_SOC_DAPM_PRE_PMU), 1624 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1625 dac_ev, SND_SOC_DAPM_PRE_PMU), 1626 }; 1627 1628 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1629 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1630 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1631 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1632 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1633 }; 1634 1635 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1636 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1637 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1638 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1639 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1640 }; 1641 1642 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1643 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1644 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1645 }; 1646 1647 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1648 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1649 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1650 SND_SOC_DAPM_INPUT("Clock"), 1651 1652 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1653 SND_SOC_DAPM_PRE_PMU), 1654 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1655 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1656 1657 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1658 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1659 SND_SOC_DAPM_PRE_PMD), 1660 1661 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1662 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1663 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1664 1665 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1666 0, SND_SOC_NOPM, 9, 0), 1667 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1668 0, SND_SOC_NOPM, 8, 0), 1669 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1670 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1672 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1673 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1674 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1675 1676 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1677 0, SND_SOC_NOPM, 11, 0), 1678 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1679 0, SND_SOC_NOPM, 10, 0), 1680 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1681 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1682 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1683 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1684 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1685 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1686 1687 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1688 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1689 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1690 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1691 1692 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1693 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1694 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1695 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1696 1697 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1698 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1699 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1700 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1701 1702 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1703 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1704 1705 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1706 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1707 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1708 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1709 1710 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1711 SND_SOC_NOPM, 13, 0), 1712 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1713 SND_SOC_NOPM, 12, 0), 1714 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1715 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1716 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1717 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1718 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1719 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1720 1721 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1722 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1723 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1724 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1725 1726 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1727 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1728 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1729 1730 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1731 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1732 1733 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1734 1735 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1736 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1737 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1738 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1739 1740 /* Power is done with the muxes since the ADC power also controls the 1741 * downsampling chain, the chip will automatically manage the analogue 1742 * specific portions. 1743 */ 1744 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1745 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1746 1747 SND_SOC_DAPM_POST("Debug log", post_ev), 1748 }; 1749 1750 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1751 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1752 }; 1753 1754 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1755 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1756 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1757 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1758 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1759 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1760 }; 1761 1762 static const struct snd_soc_dapm_route intercon[] = { 1763 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1764 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1765 1766 { "DSP1CLK", NULL, "CLK_SYS" }, 1767 { "DSP2CLK", NULL, "CLK_SYS" }, 1768 { "DSPINTCLK", NULL, "CLK_SYS" }, 1769 1770 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1771 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1772 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1773 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1774 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1775 1776 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1777 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1778 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1779 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1780 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1781 1782 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1783 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1784 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1785 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1786 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1787 1788 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1789 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1790 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1791 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1792 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1793 1794 { "AIF2ADCL", NULL, "AIF2CLK" }, 1795 { "AIF2ADCL", NULL, "DSP2CLK" }, 1796 { "AIF2ADCR", NULL, "AIF2CLK" }, 1797 { "AIF2ADCR", NULL, "DSP2CLK" }, 1798 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1799 1800 { "AIF2DACL", NULL, "AIF2CLK" }, 1801 { "AIF2DACL", NULL, "DSP2CLK" }, 1802 { "AIF2DACR", NULL, "AIF2CLK" }, 1803 { "AIF2DACR", NULL, "DSP2CLK" }, 1804 { "AIF2DACR", NULL, "DSPINTCLK" }, 1805 1806 { "DMIC1L", NULL, "DMIC1DAT" }, 1807 { "DMIC1L", NULL, "CLK_SYS" }, 1808 { "DMIC1R", NULL, "DMIC1DAT" }, 1809 { "DMIC1R", NULL, "CLK_SYS" }, 1810 { "DMIC2L", NULL, "DMIC2DAT" }, 1811 { "DMIC2L", NULL, "CLK_SYS" }, 1812 { "DMIC2R", NULL, "DMIC2DAT" }, 1813 { "DMIC2R", NULL, "CLK_SYS" }, 1814 1815 { "ADCL", NULL, "AIF1CLK" }, 1816 { "ADCL", NULL, "DSP1CLK" }, 1817 { "ADCL", NULL, "DSPINTCLK" }, 1818 1819 { "ADCR", NULL, "AIF1CLK" }, 1820 { "ADCR", NULL, "DSP1CLK" }, 1821 { "ADCR", NULL, "DSPINTCLK" }, 1822 1823 { "ADCL Mux", "ADC", "ADCL" }, 1824 { "ADCL Mux", "DMIC", "DMIC1L" }, 1825 { "ADCR Mux", "ADC", "ADCR" }, 1826 { "ADCR Mux", "DMIC", "DMIC1R" }, 1827 1828 { "DAC1L", NULL, "AIF1CLK" }, 1829 { "DAC1L", NULL, "DSP1CLK" }, 1830 { "DAC1L", NULL, "DSPINTCLK" }, 1831 1832 { "DAC1R", NULL, "AIF1CLK" }, 1833 { "DAC1R", NULL, "DSP1CLK" }, 1834 { "DAC1R", NULL, "DSPINTCLK" }, 1835 1836 { "DAC2L", NULL, "AIF2CLK" }, 1837 { "DAC2L", NULL, "DSP2CLK" }, 1838 { "DAC2L", NULL, "DSPINTCLK" }, 1839 1840 { "DAC2R", NULL, "AIF2DACR" }, 1841 { "DAC2R", NULL, "AIF2CLK" }, 1842 { "DAC2R", NULL, "DSP2CLK" }, 1843 { "DAC2R", NULL, "DSPINTCLK" }, 1844 1845 { "TOCLK", NULL, "CLK_SYS" }, 1846 1847 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1848 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1849 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1850 1851 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1852 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1853 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1854 1855 /* AIF1 outputs */ 1856 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1857 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1858 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1859 1860 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1861 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1862 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1863 1864 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1865 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1866 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1867 1868 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1869 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1870 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1871 1872 /* Pin level routing for AIF3 */ 1873 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1874 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1875 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1876 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1877 1878 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1879 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1880 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1881 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1882 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1883 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1884 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1885 1886 /* DAC1 inputs */ 1887 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1888 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1889 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1890 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1891 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1892 1893 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1894 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1895 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1896 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1897 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1898 1899 /* DAC2/AIF2 outputs */ 1900 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1901 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1902 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1903 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1904 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1905 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1906 1907 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 1908 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1909 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1910 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1911 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1912 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1913 1914 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 1915 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 1916 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 1917 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 1918 1919 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 1920 1921 /* AIF3 output */ 1922 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 1923 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 1924 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 1925 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 1926 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 1927 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 1928 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 1929 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 1930 1931 /* Sidetone */ 1932 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 1933 { "Left Sidetone", "DMIC2", "DMIC2L" }, 1934 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 1935 { "Right Sidetone", "DMIC2", "DMIC2R" }, 1936 1937 /* Output stages */ 1938 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 1939 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 1940 1941 { "SPKL", "DAC1 Switch", "DAC1L" }, 1942 { "SPKL", "DAC2 Switch", "DAC2L" }, 1943 1944 { "SPKR", "DAC1 Switch", "DAC1R" }, 1945 { "SPKR", "DAC2 Switch", "DAC2R" }, 1946 1947 { "Left Headphone Mux", "DAC", "DAC1L" }, 1948 { "Right Headphone Mux", "DAC", "DAC1R" }, 1949 }; 1950 1951 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 1952 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 1953 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 1954 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 1955 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 1956 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 1957 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 1958 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 1959 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 1960 }; 1961 1962 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 1963 { "DAC1L", NULL, "DAC1L Mixer" }, 1964 { "DAC1R", NULL, "DAC1R Mixer" }, 1965 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1966 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1967 }; 1968 1969 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 1970 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 1971 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 1972 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 1973 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 1974 { "MICBIAS1", NULL, "CLK_SYS" }, 1975 { "MICBIAS1", NULL, "MICBIAS Supply" }, 1976 { "MICBIAS2", NULL, "CLK_SYS" }, 1977 { "MICBIAS2", NULL, "MICBIAS Supply" }, 1978 }; 1979 1980 static const struct snd_soc_dapm_route wm8994_intercon[] = { 1981 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 1982 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 1983 { "MICBIAS1", NULL, "VMID" }, 1984 { "MICBIAS2", NULL, "VMID" }, 1985 }; 1986 1987 static const struct snd_soc_dapm_route wm8958_intercon[] = { 1988 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 1989 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 1990 1991 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 1992 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 1993 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1994 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1995 1996 { "AIF3DACDAT", NULL, "AIF3" }, 1997 { "AIF3ADCDAT", NULL, "AIF3" }, 1998 1999 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2000 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2001 2002 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2003 }; 2004 2005 /* The size in bits of the FLL divide multiplied by 10 2006 * to allow rounding later */ 2007 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2008 2009 struct fll_div { 2010 u16 outdiv; 2011 u16 n; 2012 u16 k; 2013 u16 clk_ref_div; 2014 u16 fll_fratio; 2015 }; 2016 2017 static int wm8994_get_fll_config(struct fll_div *fll, 2018 int freq_in, int freq_out) 2019 { 2020 u64 Kpart; 2021 unsigned int K, Ndiv, Nmod; 2022 2023 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2024 2025 /* Scale the input frequency down to <= 13.5MHz */ 2026 fll->clk_ref_div = 0; 2027 while (freq_in > 13500000) { 2028 fll->clk_ref_div++; 2029 freq_in /= 2; 2030 2031 if (fll->clk_ref_div > 3) 2032 return -EINVAL; 2033 } 2034 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2035 2036 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2037 fll->outdiv = 3; 2038 while (freq_out * (fll->outdiv + 1) < 90000000) { 2039 fll->outdiv++; 2040 if (fll->outdiv > 63) 2041 return -EINVAL; 2042 } 2043 freq_out *= fll->outdiv + 1; 2044 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2045 2046 if (freq_in > 1000000) { 2047 fll->fll_fratio = 0; 2048 } else if (freq_in > 256000) { 2049 fll->fll_fratio = 1; 2050 freq_in *= 2; 2051 } else if (freq_in > 128000) { 2052 fll->fll_fratio = 2; 2053 freq_in *= 4; 2054 } else if (freq_in > 64000) { 2055 fll->fll_fratio = 3; 2056 freq_in *= 8; 2057 } else { 2058 fll->fll_fratio = 4; 2059 freq_in *= 16; 2060 } 2061 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2062 2063 /* Now, calculate N.K */ 2064 Ndiv = freq_out / freq_in; 2065 2066 fll->n = Ndiv; 2067 Nmod = freq_out % freq_in; 2068 pr_debug("Nmod=%d\n", Nmod); 2069 2070 /* Calculate fractional part - scale up so we can round. */ 2071 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2072 2073 do_div(Kpart, freq_in); 2074 2075 K = Kpart & 0xFFFFFFFF; 2076 2077 if ((K % 10) >= 5) 2078 K += 5; 2079 2080 /* Move down to proper range now rounding is done */ 2081 fll->k = K / 10; 2082 2083 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2084 2085 return 0; 2086 } 2087 2088 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, 2089 unsigned int freq_in, unsigned int freq_out) 2090 { 2091 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2092 struct wm8994 *control = wm8994->wm8994; 2093 int reg_offset, ret; 2094 struct fll_div fll; 2095 u16 reg, clk1, aif_reg, aif_src; 2096 unsigned long timeout; 2097 bool was_enabled; 2098 2099 switch (id) { 2100 case WM8994_FLL1: 2101 reg_offset = 0; 2102 id = 0; 2103 aif_src = 0x10; 2104 break; 2105 case WM8994_FLL2: 2106 reg_offset = 0x20; 2107 id = 1; 2108 aif_src = 0x18; 2109 break; 2110 default: 2111 return -EINVAL; 2112 } 2113 2114 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); 2115 was_enabled = reg & WM8994_FLL1_ENA; 2116 2117 switch (src) { 2118 case 0: 2119 /* Allow no source specification when stopping */ 2120 if (freq_out) 2121 return -EINVAL; 2122 src = wm8994->fll[id].src; 2123 break; 2124 case WM8994_FLL_SRC_MCLK1: 2125 case WM8994_FLL_SRC_MCLK2: 2126 case WM8994_FLL_SRC_LRCLK: 2127 case WM8994_FLL_SRC_BCLK: 2128 break; 2129 case WM8994_FLL_SRC_INTERNAL: 2130 freq_in = 12000000; 2131 freq_out = 12000000; 2132 break; 2133 default: 2134 return -EINVAL; 2135 } 2136 2137 /* Are we changing anything? */ 2138 if (wm8994->fll[id].src == src && 2139 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2140 return 0; 2141 2142 /* If we're stopping the FLL redo the old config - no 2143 * registers will actually be written but we avoid GCC flow 2144 * analysis bugs spewing warnings. 2145 */ 2146 if (freq_out) 2147 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 2148 else 2149 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 2150 wm8994->fll[id].out); 2151 if (ret < 0) 2152 return ret; 2153 2154 /* Make sure that we're not providing SYSCLK right now */ 2155 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1); 2156 if (clk1 & WM8994_SYSCLK_SRC) 2157 aif_reg = WM8994_AIF2_CLOCKING_1; 2158 else 2159 aif_reg = WM8994_AIF1_CLOCKING_1; 2160 reg = snd_soc_read(codec, aif_reg); 2161 2162 if ((reg & WM8994_AIF1CLK_ENA) && 2163 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2164 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n", 2165 id + 1); 2166 return -EBUSY; 2167 } 2168 2169 /* We always need to disable the FLL while reconfiguring */ 2170 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2171 WM8994_FLL1_ENA, 0); 2172 2173 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2174 freq_in == freq_out && freq_out) { 2175 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1); 2176 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2177 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2178 goto out; 2179 } 2180 2181 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2182 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2183 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2184 WM8994_FLL1_OUTDIV_MASK | 2185 WM8994_FLL1_FRATIO_MASK, reg); 2186 2187 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, 2188 WM8994_FLL1_K_MASK, fll.k); 2189 2190 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 2191 WM8994_FLL1_N_MASK, 2192 fll.n << WM8994_FLL1_N_SHIFT); 2193 2194 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2195 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2196 WM8994_FLL1_REFCLK_DIV_MASK | 2197 WM8994_FLL1_REFCLK_SRC_MASK, 2198 ((src == WM8994_FLL_SRC_INTERNAL) 2199 << WM8994_FLL1_FRC_NCO_SHIFT) | 2200 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2201 (src - 1)); 2202 2203 /* Clear any pending completion from a previous failure */ 2204 try_wait_for_completion(&wm8994->fll_locked[id]); 2205 2206 /* Enable (with fractional mode if required) */ 2207 if (freq_out) { 2208 /* Enable VMID if we need it */ 2209 if (!was_enabled) { 2210 active_reference(codec); 2211 2212 switch (control->type) { 2213 case WM8994: 2214 vmid_reference(codec); 2215 break; 2216 case WM8958: 2217 if (wm8994->revision < 1) 2218 vmid_reference(codec); 2219 break; 2220 default: 2221 break; 2222 } 2223 } 2224 2225 reg = WM8994_FLL1_ENA; 2226 2227 if (fll.k) 2228 reg |= WM8994_FLL1_FRAC; 2229 if (src == WM8994_FLL_SRC_INTERNAL) 2230 reg |= WM8994_FLL1_OSC_ENA; 2231 2232 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2233 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2234 WM8994_FLL1_FRAC, reg); 2235 2236 if (wm8994->fll_locked_irq) { 2237 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], 2238 msecs_to_jiffies(10)); 2239 if (timeout == 0) 2240 dev_warn(codec->dev, 2241 "Timed out waiting for FLL lock\n"); 2242 } else { 2243 msleep(5); 2244 } 2245 } else { 2246 if (was_enabled) { 2247 switch (control->type) { 2248 case WM8994: 2249 vmid_dereference(codec); 2250 break; 2251 case WM8958: 2252 if (wm8994->revision < 1) 2253 vmid_dereference(codec); 2254 break; 2255 default: 2256 break; 2257 } 2258 2259 active_dereference(codec); 2260 } 2261 } 2262 2263 out: 2264 wm8994->fll[id].in = freq_in; 2265 wm8994->fll[id].out = freq_out; 2266 wm8994->fll[id].src = src; 2267 2268 configure_clock(codec); 2269 2270 /* 2271 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2272 * for detection. 2273 */ 2274 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2275 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2276 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2277 WM8994_AIF1CLK_RATE_MASK, 0x1); 2278 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2279 WM8994_AIF2CLK_RATE_MASK, 0x1); 2280 } 2281 2282 return 0; 2283 } 2284 2285 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2286 { 2287 struct completion *completion = data; 2288 2289 complete(completion); 2290 2291 return IRQ_HANDLED; 2292 } 2293 2294 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2295 2296 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2297 unsigned int freq_in, unsigned int freq_out) 2298 { 2299 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); 2300 } 2301 2302 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2303 int clk_id, unsigned int freq, int dir) 2304 { 2305 struct snd_soc_codec *codec = dai->codec; 2306 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2307 int i; 2308 2309 switch (dai->id) { 2310 case 1: 2311 case 2: 2312 break; 2313 2314 default: 2315 /* AIF3 shares clocking with AIF1/2 */ 2316 return -EINVAL; 2317 } 2318 2319 switch (clk_id) { 2320 case WM8994_SYSCLK_MCLK1: 2321 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2322 wm8994->mclk[0] = freq; 2323 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2324 dai->id, freq); 2325 break; 2326 2327 case WM8994_SYSCLK_MCLK2: 2328 /* TODO: Set GPIO AF */ 2329 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2330 wm8994->mclk[1] = freq; 2331 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2332 dai->id, freq); 2333 break; 2334 2335 case WM8994_SYSCLK_FLL1: 2336 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2337 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2338 break; 2339 2340 case WM8994_SYSCLK_FLL2: 2341 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2342 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2343 break; 2344 2345 case WM8994_SYSCLK_OPCLK: 2346 /* Special case - a division (times 10) is given and 2347 * no effect on main clocking. 2348 */ 2349 if (freq) { 2350 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2351 if (opclk_divs[i] == freq) 2352 break; 2353 if (i == ARRAY_SIZE(opclk_divs)) 2354 return -EINVAL; 2355 snd_soc_update_bits(codec, WM8994_CLOCKING_2, 2356 WM8994_OPCLK_DIV_MASK, i); 2357 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2358 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2359 } else { 2360 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, 2361 WM8994_OPCLK_ENA, 0); 2362 } 2363 2364 default: 2365 return -EINVAL; 2366 } 2367 2368 configure_clock(codec); 2369 2370 /* 2371 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2372 * for detection. 2373 */ 2374 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2375 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); 2376 snd_soc_update_bits(codec, WM8994_AIF1_RATE, 2377 WM8994_AIF1CLK_RATE_MASK, 0x1); 2378 snd_soc_update_bits(codec, WM8994_AIF2_RATE, 2379 WM8994_AIF2CLK_RATE_MASK, 0x1); 2380 } 2381 2382 return 0; 2383 } 2384 2385 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 2386 enum snd_soc_bias_level level) 2387 { 2388 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2389 struct wm8994 *control = wm8994->wm8994; 2390 2391 wm_hubs_set_bias_level(codec, level); 2392 2393 switch (level) { 2394 case SND_SOC_BIAS_ON: 2395 break; 2396 2397 case SND_SOC_BIAS_PREPARE: 2398 /* MICBIAS into regulating mode */ 2399 switch (control->type) { 2400 case WM8958: 2401 case WM1811: 2402 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2403 WM8958_MICB1_MODE, 0); 2404 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2405 WM8958_MICB2_MODE, 0); 2406 break; 2407 default: 2408 break; 2409 } 2410 2411 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2412 active_reference(codec); 2413 break; 2414 2415 case SND_SOC_BIAS_STANDBY: 2416 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2417 switch (control->type) { 2418 case WM8958: 2419 if (wm8994->revision == 0) { 2420 /* Optimise performance for rev A */ 2421 snd_soc_update_bits(codec, 2422 WM8958_CHARGE_PUMP_2, 2423 WM8958_CP_DISCH, 2424 WM8958_CP_DISCH); 2425 } 2426 break; 2427 2428 default: 2429 break; 2430 } 2431 2432 /* Discharge LINEOUT1 & 2 */ 2433 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 2434 WM8994_LINEOUT1_DISCH | 2435 WM8994_LINEOUT2_DISCH, 2436 WM8994_LINEOUT1_DISCH | 2437 WM8994_LINEOUT2_DISCH); 2438 } 2439 2440 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) 2441 active_dereference(codec); 2442 2443 /* MICBIAS into bypass mode on newer devices */ 2444 switch (control->type) { 2445 case WM8958: 2446 case WM1811: 2447 snd_soc_update_bits(codec, WM8958_MICBIAS1, 2448 WM8958_MICB1_MODE, 2449 WM8958_MICB1_MODE); 2450 snd_soc_update_bits(codec, WM8958_MICBIAS2, 2451 WM8958_MICB2_MODE, 2452 WM8958_MICB2_MODE); 2453 break; 2454 default: 2455 break; 2456 } 2457 break; 2458 2459 case SND_SOC_BIAS_OFF: 2460 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 2461 wm8994->cur_fw = NULL; 2462 break; 2463 } 2464 2465 codec->dapm.bias_level = level; 2466 2467 return 0; 2468 } 2469 2470 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode) 2471 { 2472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2473 2474 switch (mode) { 2475 case WM8994_VMID_NORMAL: 2476 if (wm8994->hubs.lineout1_se) { 2477 snd_soc_dapm_disable_pin(&codec->dapm, 2478 "LINEOUT1N Driver"); 2479 snd_soc_dapm_disable_pin(&codec->dapm, 2480 "LINEOUT1P Driver"); 2481 } 2482 if (wm8994->hubs.lineout2_se) { 2483 snd_soc_dapm_disable_pin(&codec->dapm, 2484 "LINEOUT2N Driver"); 2485 snd_soc_dapm_disable_pin(&codec->dapm, 2486 "LINEOUT2P Driver"); 2487 } 2488 2489 /* Do the sync with the old mode to allow it to clean up */ 2490 snd_soc_dapm_sync(&codec->dapm); 2491 wm8994->vmid_mode = mode; 2492 break; 2493 2494 case WM8994_VMID_FORCE: 2495 if (wm8994->hubs.lineout1_se) { 2496 snd_soc_dapm_force_enable_pin(&codec->dapm, 2497 "LINEOUT1N Driver"); 2498 snd_soc_dapm_force_enable_pin(&codec->dapm, 2499 "LINEOUT1P Driver"); 2500 } 2501 if (wm8994->hubs.lineout2_se) { 2502 snd_soc_dapm_force_enable_pin(&codec->dapm, 2503 "LINEOUT2N Driver"); 2504 snd_soc_dapm_force_enable_pin(&codec->dapm, 2505 "LINEOUT2P Driver"); 2506 } 2507 2508 wm8994->vmid_mode = mode; 2509 snd_soc_dapm_sync(&codec->dapm); 2510 break; 2511 2512 default: 2513 return -EINVAL; 2514 } 2515 2516 return 0; 2517 } 2518 2519 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2520 { 2521 struct snd_soc_codec *codec = dai->codec; 2522 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2523 struct wm8994 *control = wm8994->wm8994; 2524 int ms_reg; 2525 int aif1_reg; 2526 int ms = 0; 2527 int aif1 = 0; 2528 2529 switch (dai->id) { 2530 case 1: 2531 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2532 aif1_reg = WM8994_AIF1_CONTROL_1; 2533 break; 2534 case 2: 2535 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2536 aif1_reg = WM8994_AIF2_CONTROL_1; 2537 break; 2538 default: 2539 return -EINVAL; 2540 } 2541 2542 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2543 case SND_SOC_DAIFMT_CBS_CFS: 2544 break; 2545 case SND_SOC_DAIFMT_CBM_CFM: 2546 ms = WM8994_AIF1_MSTR; 2547 break; 2548 default: 2549 return -EINVAL; 2550 } 2551 2552 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2553 case SND_SOC_DAIFMT_DSP_B: 2554 aif1 |= WM8994_AIF1_LRCLK_INV; 2555 case SND_SOC_DAIFMT_DSP_A: 2556 aif1 |= 0x18; 2557 break; 2558 case SND_SOC_DAIFMT_I2S: 2559 aif1 |= 0x10; 2560 break; 2561 case SND_SOC_DAIFMT_RIGHT_J: 2562 break; 2563 case SND_SOC_DAIFMT_LEFT_J: 2564 aif1 |= 0x8; 2565 break; 2566 default: 2567 return -EINVAL; 2568 } 2569 2570 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2571 case SND_SOC_DAIFMT_DSP_A: 2572 case SND_SOC_DAIFMT_DSP_B: 2573 /* frame inversion not valid for DSP modes */ 2574 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2575 case SND_SOC_DAIFMT_NB_NF: 2576 break; 2577 case SND_SOC_DAIFMT_IB_NF: 2578 aif1 |= WM8994_AIF1_BCLK_INV; 2579 break; 2580 default: 2581 return -EINVAL; 2582 } 2583 break; 2584 2585 case SND_SOC_DAIFMT_I2S: 2586 case SND_SOC_DAIFMT_RIGHT_J: 2587 case SND_SOC_DAIFMT_LEFT_J: 2588 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2589 case SND_SOC_DAIFMT_NB_NF: 2590 break; 2591 case SND_SOC_DAIFMT_IB_IF: 2592 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2593 break; 2594 case SND_SOC_DAIFMT_IB_NF: 2595 aif1 |= WM8994_AIF1_BCLK_INV; 2596 break; 2597 case SND_SOC_DAIFMT_NB_IF: 2598 aif1 |= WM8994_AIF1_LRCLK_INV; 2599 break; 2600 default: 2601 return -EINVAL; 2602 } 2603 break; 2604 default: 2605 return -EINVAL; 2606 } 2607 2608 /* The AIF2 format configuration needs to be mirrored to AIF3 2609 * on WM8958 if it's in use so just do it all the time. */ 2610 switch (control->type) { 2611 case WM1811: 2612 case WM8958: 2613 if (dai->id == 2) 2614 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, 2615 WM8994_AIF1_LRCLK_INV | 2616 WM8958_AIF3_FMT_MASK, aif1); 2617 break; 2618 2619 default: 2620 break; 2621 } 2622 2623 snd_soc_update_bits(codec, aif1_reg, 2624 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2625 WM8994_AIF1_FMT_MASK, 2626 aif1); 2627 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 2628 ms); 2629 2630 return 0; 2631 } 2632 2633 static struct { 2634 int val, rate; 2635 } srs[] = { 2636 { 0, 8000 }, 2637 { 1, 11025 }, 2638 { 2, 12000 }, 2639 { 3, 16000 }, 2640 { 4, 22050 }, 2641 { 5, 24000 }, 2642 { 6, 32000 }, 2643 { 7, 44100 }, 2644 { 8, 48000 }, 2645 { 9, 88200 }, 2646 { 10, 96000 }, 2647 }; 2648 2649 static int fs_ratios[] = { 2650 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 2651 }; 2652 2653 static int bclk_divs[] = { 2654 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2655 640, 880, 960, 1280, 1760, 1920 2656 }; 2657 2658 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2659 struct snd_pcm_hw_params *params, 2660 struct snd_soc_dai *dai) 2661 { 2662 struct snd_soc_codec *codec = dai->codec; 2663 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2664 int aif1_reg; 2665 int aif2_reg; 2666 int bclk_reg; 2667 int lrclk_reg; 2668 int rate_reg; 2669 int aif1 = 0; 2670 int aif2 = 0; 2671 int bclk = 0; 2672 int lrclk = 0; 2673 int rate_val = 0; 2674 int id = dai->id - 1; 2675 2676 int i, cur_val, best_val, bclk_rate, best; 2677 2678 switch (dai->id) { 2679 case 1: 2680 aif1_reg = WM8994_AIF1_CONTROL_1; 2681 aif2_reg = WM8994_AIF1_CONTROL_2; 2682 bclk_reg = WM8994_AIF1_BCLK; 2683 rate_reg = WM8994_AIF1_RATE; 2684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2685 wm8994->lrclk_shared[0]) { 2686 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2687 } else { 2688 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2689 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 2690 } 2691 break; 2692 case 2: 2693 aif1_reg = WM8994_AIF2_CONTROL_1; 2694 aif2_reg = WM8994_AIF2_CONTROL_2; 2695 bclk_reg = WM8994_AIF2_BCLK; 2696 rate_reg = WM8994_AIF2_RATE; 2697 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2698 wm8994->lrclk_shared[1]) { 2699 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2700 } else { 2701 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2702 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2703 } 2704 break; 2705 default: 2706 return -EINVAL; 2707 } 2708 2709 bclk_rate = params_rate(params); 2710 switch (params_format(params)) { 2711 case SNDRV_PCM_FORMAT_S16_LE: 2712 bclk_rate *= 16; 2713 break; 2714 case SNDRV_PCM_FORMAT_S20_3LE: 2715 bclk_rate *= 20; 2716 aif1 |= 0x20; 2717 break; 2718 case SNDRV_PCM_FORMAT_S24_LE: 2719 bclk_rate *= 24; 2720 aif1 |= 0x40; 2721 break; 2722 case SNDRV_PCM_FORMAT_S32_LE: 2723 bclk_rate *= 32; 2724 aif1 |= 0x60; 2725 break; 2726 default: 2727 return -EINVAL; 2728 } 2729 2730 wm8994->channels[id] = params_channels(params); 2731 switch (params_channels(params)) { 2732 case 1: 2733 case 2: 2734 bclk_rate *= 2; 2735 break; 2736 default: 2737 bclk_rate *= 4; 2738 break; 2739 } 2740 2741 /* Try to find an appropriate sample rate; look for an exact match. */ 2742 for (i = 0; i < ARRAY_SIZE(srs); i++) 2743 if (srs[i].rate == params_rate(params)) 2744 break; 2745 if (i == ARRAY_SIZE(srs)) 2746 return -EINVAL; 2747 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 2748 2749 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 2750 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2751 dai->id, wm8994->aifclk[id], bclk_rate); 2752 2753 if (params_channels(params) == 1 && 2754 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) 2755 aif2 |= WM8994_AIF1_MONO; 2756 2757 if (wm8994->aifclk[id] == 0) { 2758 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2759 return -EINVAL; 2760 } 2761 2762 /* AIFCLK/fs ratio; look for a close match in either direction */ 2763 best = 0; 2764 best_val = abs((fs_ratios[0] * params_rate(params)) 2765 - wm8994->aifclk[id]); 2766 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 2767 cur_val = abs((fs_ratios[i] * params_rate(params)) 2768 - wm8994->aifclk[id]); 2769 if (cur_val >= best_val) 2770 continue; 2771 best = i; 2772 best_val = cur_val; 2773 } 2774 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 2775 dai->id, fs_ratios[best]); 2776 rate_val |= best; 2777 2778 /* We may not get quite the right frequency if using 2779 * approximate clocks so look for the closest match that is 2780 * higher than the target (we need to ensure that there enough 2781 * BCLKs to clock out the samples). 2782 */ 2783 best = 0; 2784 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2785 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 2786 if (cur_val < 0) /* BCLK table is sorted */ 2787 break; 2788 best = i; 2789 } 2790 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 2791 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 2792 bclk_divs[best], bclk_rate); 2793 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 2794 2795 lrclk = bclk_rate / params_rate(params); 2796 if (!lrclk) { 2797 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 2798 bclk_rate); 2799 return -EINVAL; 2800 } 2801 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 2802 lrclk, bclk_rate / lrclk); 2803 2804 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2805 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); 2806 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2807 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2808 lrclk); 2809 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 2810 WM8994_AIF1CLK_RATE_MASK, rate_val); 2811 2812 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2813 switch (dai->id) { 2814 case 1: 2815 wm8994->dac_rates[0] = params_rate(params); 2816 wm8994_set_retune_mobile(codec, 0); 2817 wm8994_set_retune_mobile(codec, 1); 2818 break; 2819 case 2: 2820 wm8994->dac_rates[1] = params_rate(params); 2821 wm8994_set_retune_mobile(codec, 2); 2822 break; 2823 } 2824 } 2825 2826 return 0; 2827 } 2828 2829 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 2830 struct snd_pcm_hw_params *params, 2831 struct snd_soc_dai *dai) 2832 { 2833 struct snd_soc_codec *codec = dai->codec; 2834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2835 struct wm8994 *control = wm8994->wm8994; 2836 int aif1_reg; 2837 int aif1 = 0; 2838 2839 switch (dai->id) { 2840 case 3: 2841 switch (control->type) { 2842 case WM1811: 2843 case WM8958: 2844 aif1_reg = WM8958_AIF3_CONTROL_1; 2845 break; 2846 default: 2847 return 0; 2848 } 2849 default: 2850 return 0; 2851 } 2852 2853 switch (params_format(params)) { 2854 case SNDRV_PCM_FORMAT_S16_LE: 2855 break; 2856 case SNDRV_PCM_FORMAT_S20_3LE: 2857 aif1 |= 0x20; 2858 break; 2859 case SNDRV_PCM_FORMAT_S24_LE: 2860 aif1 |= 0x40; 2861 break; 2862 case SNDRV_PCM_FORMAT_S32_LE: 2863 aif1 |= 0x60; 2864 break; 2865 default: 2866 return -EINVAL; 2867 } 2868 2869 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2870 } 2871 2872 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2873 { 2874 struct snd_soc_codec *codec = codec_dai->codec; 2875 int mute_reg; 2876 int reg; 2877 2878 switch (codec_dai->id) { 2879 case 1: 2880 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 2881 break; 2882 case 2: 2883 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 2884 break; 2885 default: 2886 return -EINVAL; 2887 } 2888 2889 if (mute) 2890 reg = WM8994_AIF1DAC1_MUTE; 2891 else 2892 reg = 0; 2893 2894 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 2895 2896 return 0; 2897 } 2898 2899 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 2900 { 2901 struct snd_soc_codec *codec = codec_dai->codec; 2902 int reg, val, mask; 2903 2904 switch (codec_dai->id) { 2905 case 1: 2906 reg = WM8994_AIF1_MASTER_SLAVE; 2907 mask = WM8994_AIF1_TRI; 2908 break; 2909 case 2: 2910 reg = WM8994_AIF2_MASTER_SLAVE; 2911 mask = WM8994_AIF2_TRI; 2912 break; 2913 default: 2914 return -EINVAL; 2915 } 2916 2917 if (tristate) 2918 val = mask; 2919 else 2920 val = 0; 2921 2922 return snd_soc_update_bits(codec, reg, mask, val); 2923 } 2924 2925 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 2926 { 2927 struct snd_soc_codec *codec = dai->codec; 2928 2929 /* Disable the pulls on the AIF if we're using it to save power. */ 2930 snd_soc_update_bits(codec, WM8994_GPIO_3, 2931 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2932 snd_soc_update_bits(codec, WM8994_GPIO_4, 2933 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2934 snd_soc_update_bits(codec, WM8994_GPIO_5, 2935 WM8994_GPN_PU | WM8994_GPN_PD, 0); 2936 2937 return 0; 2938 } 2939 2940 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 2941 2942 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2943 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2944 2945 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 2946 .set_sysclk = wm8994_set_dai_sysclk, 2947 .set_fmt = wm8994_set_dai_fmt, 2948 .hw_params = wm8994_hw_params, 2949 .digital_mute = wm8994_aif_mute, 2950 .set_pll = wm8994_set_fll, 2951 .set_tristate = wm8994_set_tristate, 2952 }; 2953 2954 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 2955 .set_sysclk = wm8994_set_dai_sysclk, 2956 .set_fmt = wm8994_set_dai_fmt, 2957 .hw_params = wm8994_hw_params, 2958 .digital_mute = wm8994_aif_mute, 2959 .set_pll = wm8994_set_fll, 2960 .set_tristate = wm8994_set_tristate, 2961 }; 2962 2963 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2964 .hw_params = wm8994_aif3_hw_params, 2965 }; 2966 2967 static struct snd_soc_dai_driver wm8994_dai[] = { 2968 { 2969 .name = "wm8994-aif1", 2970 .id = 1, 2971 .playback = { 2972 .stream_name = "AIF1 Playback", 2973 .channels_min = 1, 2974 .channels_max = 2, 2975 .rates = WM8994_RATES, 2976 .formats = WM8994_FORMATS, 2977 .sig_bits = 24, 2978 }, 2979 .capture = { 2980 .stream_name = "AIF1 Capture", 2981 .channels_min = 1, 2982 .channels_max = 2, 2983 .rates = WM8994_RATES, 2984 .formats = WM8994_FORMATS, 2985 .sig_bits = 24, 2986 }, 2987 .ops = &wm8994_aif1_dai_ops, 2988 }, 2989 { 2990 .name = "wm8994-aif2", 2991 .id = 2, 2992 .playback = { 2993 .stream_name = "AIF2 Playback", 2994 .channels_min = 1, 2995 .channels_max = 2, 2996 .rates = WM8994_RATES, 2997 .formats = WM8994_FORMATS, 2998 .sig_bits = 24, 2999 }, 3000 .capture = { 3001 .stream_name = "AIF2 Capture", 3002 .channels_min = 1, 3003 .channels_max = 2, 3004 .rates = WM8994_RATES, 3005 .formats = WM8994_FORMATS, 3006 .sig_bits = 24, 3007 }, 3008 .probe = wm8994_aif2_probe, 3009 .ops = &wm8994_aif2_dai_ops, 3010 }, 3011 { 3012 .name = "wm8994-aif3", 3013 .id = 3, 3014 .playback = { 3015 .stream_name = "AIF3 Playback", 3016 .channels_min = 1, 3017 .channels_max = 2, 3018 .rates = WM8994_RATES, 3019 .formats = WM8994_FORMATS, 3020 .sig_bits = 24, 3021 }, 3022 .capture = { 3023 .stream_name = "AIF3 Capture", 3024 .channels_min = 1, 3025 .channels_max = 2, 3026 .rates = WM8994_RATES, 3027 .formats = WM8994_FORMATS, 3028 .sig_bits = 24, 3029 }, 3030 .ops = &wm8994_aif3_dai_ops, 3031 } 3032 }; 3033 3034 #ifdef CONFIG_PM 3035 static int wm8994_codec_suspend(struct snd_soc_codec *codec) 3036 { 3037 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3038 int i, ret; 3039 3040 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3041 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3042 sizeof(struct wm8994_fll_config)); 3043 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); 3044 if (ret < 0) 3045 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 3046 i + 1, ret); 3047 } 3048 3049 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3050 3051 return 0; 3052 } 3053 3054 static int wm8994_codec_resume(struct snd_soc_codec *codec) 3055 { 3056 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3057 struct wm8994 *control = wm8994->wm8994; 3058 int i, ret; 3059 unsigned int val, mask; 3060 3061 if (wm8994->revision < 4) { 3062 /* force a HW read */ 3063 ret = regmap_read(control->regmap, 3064 WM8994_POWER_MANAGEMENT_5, &val); 3065 3066 /* modify the cache only */ 3067 codec->cache_only = 1; 3068 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | 3069 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; 3070 val &= mask; 3071 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, 3072 mask, val); 3073 codec->cache_only = 0; 3074 } 3075 3076 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3077 if (!wm8994->fll_suspend[i].out) 3078 continue; 3079 3080 ret = _wm8994_set_fll(codec, i + 1, 3081 wm8994->fll_suspend[i].src, 3082 wm8994->fll_suspend[i].in, 3083 wm8994->fll_suspend[i].out); 3084 if (ret < 0) 3085 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 3086 i + 1, ret); 3087 } 3088 3089 return 0; 3090 } 3091 #else 3092 #define wm8994_codec_suspend NULL 3093 #define wm8994_codec_resume NULL 3094 #endif 3095 3096 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3097 { 3098 struct snd_soc_codec *codec = wm8994->hubs.codec; 3099 struct wm8994 *control = wm8994->wm8994; 3100 struct wm8994_pdata *pdata = &control->pdata; 3101 struct snd_kcontrol_new controls[] = { 3102 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3103 wm8994->retune_mobile_enum, 3104 wm8994_get_retune_mobile_enum, 3105 wm8994_put_retune_mobile_enum), 3106 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3107 wm8994->retune_mobile_enum, 3108 wm8994_get_retune_mobile_enum, 3109 wm8994_put_retune_mobile_enum), 3110 SOC_ENUM_EXT("AIF2 EQ Mode", 3111 wm8994->retune_mobile_enum, 3112 wm8994_get_retune_mobile_enum, 3113 wm8994_put_retune_mobile_enum), 3114 }; 3115 int ret, i, j; 3116 const char **t; 3117 3118 /* We need an array of texts for the enum API but the number 3119 * of texts is likely to be less than the number of 3120 * configurations due to the sample rate dependency of the 3121 * configurations. */ 3122 wm8994->num_retune_mobile_texts = 0; 3123 wm8994->retune_mobile_texts = NULL; 3124 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3125 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3126 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3127 wm8994->retune_mobile_texts[j]) == 0) 3128 break; 3129 } 3130 3131 if (j != wm8994->num_retune_mobile_texts) 3132 continue; 3133 3134 /* Expand the array... */ 3135 t = krealloc(wm8994->retune_mobile_texts, 3136 sizeof(char *) * 3137 (wm8994->num_retune_mobile_texts + 1), 3138 GFP_KERNEL); 3139 if (t == NULL) 3140 continue; 3141 3142 /* ...store the new entry... */ 3143 t[wm8994->num_retune_mobile_texts] = 3144 pdata->retune_mobile_cfgs[i].name; 3145 3146 /* ...and remember the new version. */ 3147 wm8994->num_retune_mobile_texts++; 3148 wm8994->retune_mobile_texts = t; 3149 } 3150 3151 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 3152 wm8994->num_retune_mobile_texts); 3153 3154 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 3155 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3156 3157 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3158 ARRAY_SIZE(controls)); 3159 if (ret != 0) 3160 dev_err(wm8994->hubs.codec->dev, 3161 "Failed to add ReTune Mobile controls: %d\n", ret); 3162 } 3163 3164 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3165 { 3166 struct snd_soc_codec *codec = wm8994->hubs.codec; 3167 struct wm8994 *control = wm8994->wm8994; 3168 struct wm8994_pdata *pdata = &control->pdata; 3169 int ret, i; 3170 3171 if (!pdata) 3172 return; 3173 3174 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 3175 pdata->lineout2_diff, 3176 pdata->lineout1fb, 3177 pdata->lineout2fb, 3178 pdata->jd_scthr, 3179 pdata->jd_thr, 3180 pdata->micb1_delay, 3181 pdata->micb2_delay, 3182 pdata->micbias1_lvl, 3183 pdata->micbias2_lvl); 3184 3185 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3186 3187 if (pdata->num_drc_cfgs) { 3188 struct snd_kcontrol_new controls[] = { 3189 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3190 wm8994_get_drc_enum, wm8994_put_drc_enum), 3191 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3192 wm8994_get_drc_enum, wm8994_put_drc_enum), 3193 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3194 wm8994_get_drc_enum, wm8994_put_drc_enum), 3195 }; 3196 3197 /* We need an array of texts for the enum API */ 3198 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev, 3199 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL); 3200 if (!wm8994->drc_texts) { 3201 dev_err(wm8994->hubs.codec->dev, 3202 "Failed to allocate %d DRC config texts\n", 3203 pdata->num_drc_cfgs); 3204 return; 3205 } 3206 3207 for (i = 0; i < pdata->num_drc_cfgs; i++) 3208 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3209 3210 wm8994->drc_enum.max = pdata->num_drc_cfgs; 3211 wm8994->drc_enum.texts = wm8994->drc_texts; 3212 3213 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, 3214 ARRAY_SIZE(controls)); 3215 for (i = 0; i < WM8994_NUM_DRC; i++) 3216 wm8994_set_drc(codec, i); 3217 } else { 3218 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, 3219 wm8994_drc_controls, 3220 ARRAY_SIZE(wm8994_drc_controls)); 3221 } 3222 3223 if (ret != 0) 3224 dev_err(wm8994->hubs.codec->dev, 3225 "Failed to add DRC mode controls: %d\n", ret); 3226 3227 3228 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 3229 pdata->num_retune_mobile_cfgs); 3230 3231 if (pdata->num_retune_mobile_cfgs) 3232 wm8994_handle_retune_mobile_pdata(wm8994); 3233 else 3234 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls, 3235 ARRAY_SIZE(wm8994_eq_controls)); 3236 3237 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3238 if (pdata->micbias[i]) { 3239 snd_soc_write(codec, WM8958_MICBIAS1 + i, 3240 pdata->micbias[i] & 0xffff); 3241 } 3242 } 3243 } 3244 3245 /** 3246 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3247 * 3248 * @codec: WM8994 codec 3249 * @jack: jack to report detection events on 3250 * @micbias: microphone bias to detect on 3251 * 3252 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3253 * being used to bring out signals to the processor then only platform 3254 * data configuration is needed for WM8994 and processor GPIOs should 3255 * be configured using snd_soc_jack_add_gpios() instead. 3256 * 3257 * Configuration of detection levels is available via the micbias1_lvl 3258 * and micbias2_lvl platform data members. 3259 */ 3260 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3261 int micbias) 3262 { 3263 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3264 struct wm8994_micdet *micdet; 3265 struct wm8994 *control = wm8994->wm8994; 3266 int reg, ret; 3267 3268 if (control->type != WM8994) { 3269 dev_warn(codec->dev, "Not a WM8994\n"); 3270 return -EINVAL; 3271 } 3272 3273 switch (micbias) { 3274 case 1: 3275 micdet = &wm8994->micdet[0]; 3276 if (jack) 3277 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3278 "MICBIAS1"); 3279 else 3280 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3281 "MICBIAS1"); 3282 break; 3283 case 2: 3284 micdet = &wm8994->micdet[1]; 3285 if (jack) 3286 ret = snd_soc_dapm_force_enable_pin(&codec->dapm, 3287 "MICBIAS1"); 3288 else 3289 ret = snd_soc_dapm_disable_pin(&codec->dapm, 3290 "MICBIAS1"); 3291 break; 3292 default: 3293 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias); 3294 return -EINVAL; 3295 } 3296 3297 if (ret != 0) 3298 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n", 3299 micbias, ret); 3300 3301 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n", 3302 micbias, jack); 3303 3304 /* Store the configuration */ 3305 micdet->jack = jack; 3306 micdet->detecting = true; 3307 3308 /* If either of the jacks is set up then enable detection */ 3309 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3310 reg = WM8994_MICD_ENA; 3311 else 3312 reg = 0; 3313 3314 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3315 3316 /* enable MICDET and MICSHRT deboune */ 3317 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE, 3318 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3319 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3320 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3321 3322 snd_soc_dapm_sync(&codec->dapm); 3323 3324 return 0; 3325 } 3326 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3327 3328 static void wm8994_mic_work(struct work_struct *work) 3329 { 3330 struct wm8994_priv *priv = container_of(work, 3331 struct wm8994_priv, 3332 mic_work.work); 3333 struct regmap *regmap = priv->wm8994->regmap; 3334 struct device *dev = priv->wm8994->dev; 3335 unsigned int reg; 3336 int ret; 3337 int report; 3338 3339 pm_runtime_get_sync(dev); 3340 3341 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3342 if (ret < 0) { 3343 dev_err(dev, "Failed to read microphone status: %d\n", 3344 ret); 3345 pm_runtime_put(dev); 3346 return; 3347 } 3348 3349 dev_dbg(dev, "Microphone status: %x\n", reg); 3350 3351 report = 0; 3352 if (reg & WM8994_MIC1_DET_STS) { 3353 if (priv->micdet[0].detecting) 3354 report = SND_JACK_HEADSET; 3355 } 3356 if (reg & WM8994_MIC1_SHRT_STS) { 3357 if (priv->micdet[0].detecting) 3358 report = SND_JACK_HEADPHONE; 3359 else 3360 report |= SND_JACK_BTN_0; 3361 } 3362 if (report) 3363 priv->micdet[0].detecting = false; 3364 else 3365 priv->micdet[0].detecting = true; 3366 3367 snd_soc_jack_report(priv->micdet[0].jack, report, 3368 SND_JACK_HEADSET | SND_JACK_BTN_0); 3369 3370 report = 0; 3371 if (reg & WM8994_MIC2_DET_STS) { 3372 if (priv->micdet[1].detecting) 3373 report = SND_JACK_HEADSET; 3374 } 3375 if (reg & WM8994_MIC2_SHRT_STS) { 3376 if (priv->micdet[1].detecting) 3377 report = SND_JACK_HEADPHONE; 3378 else 3379 report |= SND_JACK_BTN_0; 3380 } 3381 if (report) 3382 priv->micdet[1].detecting = false; 3383 else 3384 priv->micdet[1].detecting = true; 3385 3386 snd_soc_jack_report(priv->micdet[1].jack, report, 3387 SND_JACK_HEADSET | SND_JACK_BTN_0); 3388 3389 pm_runtime_put(dev); 3390 } 3391 3392 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3393 { 3394 struct wm8994_priv *priv = data; 3395 struct snd_soc_codec *codec = priv->hubs.codec; 3396 3397 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3398 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3399 #endif 3400 3401 pm_wakeup_event(codec->dev, 300); 3402 3403 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250)); 3404 3405 return IRQ_HANDLED; 3406 } 3407 3408 /* Default microphone detection handler for WM8958 - the user can 3409 * override this if they wish. 3410 */ 3411 static void wm8958_default_micdet(u16 status, void *data) 3412 { 3413 struct snd_soc_codec *codec = data; 3414 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3415 int report; 3416 3417 dev_dbg(codec->dev, "MICDET %x\n", status); 3418 3419 /* Either nothing present or just starting detection */ 3420 if (!(status & WM8958_MICD_STS)) { 3421 if (!wm8994->jackdet) { 3422 /* If nothing present then clear our statuses */ 3423 dev_dbg(codec->dev, "Detected open circuit\n"); 3424 wm8994->jack_mic = false; 3425 wm8994->mic_detecting = true; 3426 3427 wm8958_micd_set_rate(codec); 3428 3429 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3430 wm8994->btn_mask | 3431 SND_JACK_HEADSET); 3432 } 3433 return; 3434 } 3435 3436 /* If the measurement is showing a high impedence we've got a 3437 * microphone. 3438 */ 3439 if (wm8994->mic_detecting && (status & 0x600)) { 3440 dev_dbg(codec->dev, "Detected microphone\n"); 3441 3442 wm8994->mic_detecting = false; 3443 wm8994->jack_mic = true; 3444 3445 wm8958_micd_set_rate(codec); 3446 3447 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3448 SND_JACK_HEADSET); 3449 } 3450 3451 3452 if (wm8994->mic_detecting && status & 0xfc) { 3453 dev_dbg(codec->dev, "Detected headphone\n"); 3454 wm8994->mic_detecting = false; 3455 3456 wm8958_micd_set_rate(codec); 3457 3458 /* If we have jackdet that will detect removal */ 3459 if (wm8994->jackdet) { 3460 mutex_lock(&wm8994->accdet_lock); 3461 3462 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3463 WM8958_MICD_ENA, 0); 3464 3465 wm1811_jackdet_set_mode(codec, 3466 WM1811_JACKDET_MODE_JACK); 3467 3468 mutex_unlock(&wm8994->accdet_lock); 3469 3470 if (wm8994->wm8994->pdata.jd_ext_cap) 3471 snd_soc_dapm_disable_pin(&codec->dapm, 3472 "MICBIAS2"); 3473 } 3474 3475 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3476 SND_JACK_HEADSET); 3477 } 3478 3479 /* Report short circuit as a button */ 3480 if (wm8994->jack_mic) { 3481 report = 0; 3482 if (status & 0x4) 3483 report |= SND_JACK_BTN_0; 3484 3485 if (status & 0x8) 3486 report |= SND_JACK_BTN_1; 3487 3488 if (status & 0x10) 3489 report |= SND_JACK_BTN_2; 3490 3491 if (status & 0x20) 3492 report |= SND_JACK_BTN_3; 3493 3494 if (status & 0x40) 3495 report |= SND_JACK_BTN_4; 3496 3497 if (status & 0x80) 3498 report |= SND_JACK_BTN_5; 3499 3500 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3501 wm8994->btn_mask); 3502 } 3503 } 3504 3505 /* Deferred mic detection to allow for extra settling time */ 3506 static void wm1811_mic_work(struct work_struct *work) 3507 { 3508 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3509 mic_work.work); 3510 struct wm8994 *control = wm8994->wm8994; 3511 struct snd_soc_codec *codec = wm8994->hubs.codec; 3512 3513 pm_runtime_get_sync(codec->dev); 3514 3515 /* If required for an external cap force MICBIAS on */ 3516 if (control->pdata.jd_ext_cap) { 3517 snd_soc_dapm_force_enable_pin(&codec->dapm, 3518 "MICBIAS2"); 3519 snd_soc_dapm_sync(&codec->dapm); 3520 } 3521 3522 mutex_lock(&wm8994->accdet_lock); 3523 3524 dev_dbg(codec->dev, "Starting mic detection\n"); 3525 3526 /* 3527 * Start off measument of microphone impedence to find out 3528 * what's actually there. 3529 */ 3530 wm8994->mic_detecting = true; 3531 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC); 3532 3533 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3534 WM8958_MICD_ENA, WM8958_MICD_ENA); 3535 3536 mutex_unlock(&wm8994->accdet_lock); 3537 3538 pm_runtime_put(codec->dev); 3539 } 3540 3541 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3542 { 3543 struct wm8994_priv *wm8994 = data; 3544 struct wm8994 *control = wm8994->wm8994; 3545 struct snd_soc_codec *codec = wm8994->hubs.codec; 3546 int reg, delay; 3547 bool present; 3548 3549 pm_runtime_get_sync(codec->dev); 3550 3551 mutex_lock(&wm8994->accdet_lock); 3552 3553 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); 3554 if (reg < 0) { 3555 dev_err(codec->dev, "Failed to read jack status: %d\n", reg); 3556 mutex_unlock(&wm8994->accdet_lock); 3557 pm_runtime_put(codec->dev); 3558 return IRQ_NONE; 3559 } 3560 3561 dev_dbg(codec->dev, "JACKDET %x\n", reg); 3562 3563 present = reg & WM1811_JACKDET_LVL; 3564 3565 if (present) { 3566 dev_dbg(codec->dev, "Jack detected\n"); 3567 3568 wm8958_micd_set_rate(codec); 3569 3570 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3571 WM8958_MICB2_DISCH, 0); 3572 3573 /* Disable debounce while inserted */ 3574 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3575 WM1811_JACKDET_DB, 0); 3576 3577 delay = control->pdata.micdet_delay; 3578 schedule_delayed_work(&wm8994->mic_work, 3579 msecs_to_jiffies(delay)); 3580 } else { 3581 dev_dbg(codec->dev, "Jack not detected\n"); 3582 3583 cancel_delayed_work_sync(&wm8994->mic_work); 3584 3585 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3586 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3587 3588 /* Enable debounce while removed */ 3589 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3590 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3591 3592 wm8994->mic_detecting = false; 3593 wm8994->jack_mic = false; 3594 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3595 WM8958_MICD_ENA, 0); 3596 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); 3597 } 3598 3599 mutex_unlock(&wm8994->accdet_lock); 3600 3601 /* Turn off MICBIAS if it was on for an external cap */ 3602 if (control->pdata.jd_ext_cap && !present) 3603 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2"); 3604 3605 if (present) 3606 snd_soc_jack_report(wm8994->micdet[0].jack, 3607 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3608 else 3609 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3610 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3611 wm8994->btn_mask); 3612 3613 /* Since we only report deltas force an update, ensures we 3614 * avoid bootstrapping issues with the core. */ 3615 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3616 3617 pm_runtime_put(codec->dev); 3618 return IRQ_HANDLED; 3619 } 3620 3621 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3622 { 3623 struct wm8994_priv *wm8994 = container_of(work, 3624 struct wm8994_priv, 3625 jackdet_bootstrap.work); 3626 wm1811_jackdet_irq(0, wm8994); 3627 } 3628 3629 /** 3630 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3631 * 3632 * @codec: WM8958 codec 3633 * @jack: jack to report detection events on 3634 * 3635 * Enable microphone detection functionality for the WM8958. By 3636 * default simple detection which supports the detection of up to 6 3637 * buttons plus video and microphone functionality is supported. 3638 * 3639 * The WM8958 has an advanced jack detection facility which is able to 3640 * support complex accessory detection, especially when used in 3641 * conjunction with external circuitry. In order to provide maximum 3642 * flexiblity a callback is provided which allows a completely custom 3643 * detection algorithm. 3644 */ 3645 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3646 wm8958_micdet_cb cb, void *cb_data) 3647 { 3648 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3649 struct wm8994 *control = wm8994->wm8994; 3650 u16 micd_lvl_sel; 3651 3652 switch (control->type) { 3653 case WM1811: 3654 case WM8958: 3655 break; 3656 default: 3657 return -EINVAL; 3658 } 3659 3660 if (jack) { 3661 if (!cb) { 3662 dev_dbg(codec->dev, "Using default micdet callback\n"); 3663 cb = wm8958_default_micdet; 3664 cb_data = codec; 3665 } 3666 3667 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS"); 3668 snd_soc_dapm_sync(&codec->dapm); 3669 3670 wm8994->micdet[0].jack = jack; 3671 wm8994->jack_cb = cb; 3672 wm8994->jack_cb_data = cb_data; 3673 3674 wm8994->mic_detecting = true; 3675 wm8994->jack_mic = false; 3676 3677 wm8958_micd_set_rate(codec); 3678 3679 /* Detect microphones and short circuits by default */ 3680 if (control->pdata.micd_lvl_sel) 3681 micd_lvl_sel = control->pdata.micd_lvl_sel; 3682 else 3683 micd_lvl_sel = 0x41; 3684 3685 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3686 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3687 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3688 3689 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2, 3690 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3691 3692 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY); 3693 3694 /* 3695 * If we can use jack detection start off with that, 3696 * otherwise jump straight to microphone detection. 3697 */ 3698 if (wm8994->jackdet) { 3699 /* Disable debounce for the initial detect */ 3700 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, 3701 WM1811_JACKDET_DB, 0); 3702 3703 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3704 WM8958_MICB2_DISCH, 3705 WM8958_MICB2_DISCH); 3706 snd_soc_update_bits(codec, WM8994_LDO_1, 3707 WM8994_LDO1_DISCH, 0); 3708 wm1811_jackdet_set_mode(codec, 3709 WM1811_JACKDET_MODE_JACK); 3710 } else { 3711 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3712 WM8958_MICD_ENA, WM8958_MICD_ENA); 3713 } 3714 3715 } else { 3716 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 3717 WM8958_MICD_ENA, 0); 3718 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE); 3719 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS"); 3720 snd_soc_dapm_sync(&codec->dapm); 3721 } 3722 3723 return 0; 3724 } 3725 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 3726 3727 static irqreturn_t wm8958_mic_irq(int irq, void *data) 3728 { 3729 struct wm8994_priv *wm8994 = data; 3730 struct snd_soc_codec *codec = wm8994->hubs.codec; 3731 int reg, count; 3732 3733 /* 3734 * Jack detection may have detected a removal simulataneously 3735 * with an update of the MICDET status; if so it will have 3736 * stopped detection and we can ignore this interrupt. 3737 */ 3738 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 3739 return IRQ_HANDLED; 3740 3741 pm_runtime_get_sync(codec->dev); 3742 3743 /* We may occasionally read a detection without an impedence 3744 * range being provided - if that happens loop again. 3745 */ 3746 count = 10; 3747 do { 3748 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); 3749 if (reg < 0) { 3750 dev_err(codec->dev, 3751 "Failed to read mic detect status: %d\n", 3752 reg); 3753 pm_runtime_put(codec->dev); 3754 return IRQ_NONE; 3755 } 3756 3757 if (!(reg & WM8958_MICD_VALID)) { 3758 dev_dbg(codec->dev, "Mic detect data not valid\n"); 3759 goto out; 3760 } 3761 3762 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 3763 break; 3764 3765 msleep(1); 3766 } while (count--); 3767 3768 if (count == 0) 3769 dev_warn(codec->dev, "No impedance range reported for jack\n"); 3770 3771 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3772 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3773 #endif 3774 3775 if (wm8994->jack_cb) 3776 wm8994->jack_cb(reg, wm8994->jack_cb_data); 3777 else 3778 dev_warn(codec->dev, "Accessory detection with no callback\n"); 3779 3780 out: 3781 pm_runtime_put(codec->dev); 3782 return IRQ_HANDLED; 3783 } 3784 3785 static irqreturn_t wm8994_fifo_error(int irq, void *data) 3786 { 3787 struct snd_soc_codec *codec = data; 3788 3789 dev_err(codec->dev, "FIFO error\n"); 3790 3791 return IRQ_HANDLED; 3792 } 3793 3794 static irqreturn_t wm8994_temp_warn(int irq, void *data) 3795 { 3796 struct snd_soc_codec *codec = data; 3797 3798 dev_err(codec->dev, "Thermal warning\n"); 3799 3800 return IRQ_HANDLED; 3801 } 3802 3803 static irqreturn_t wm8994_temp_shut(int irq, void *data) 3804 { 3805 struct snd_soc_codec *codec = data; 3806 3807 dev_crit(codec->dev, "Thermal shutdown\n"); 3808 3809 return IRQ_HANDLED; 3810 } 3811 3812 static int wm8994_codec_probe(struct snd_soc_codec *codec) 3813 { 3814 struct wm8994 *control = dev_get_drvdata(codec->dev->parent); 3815 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3816 struct snd_soc_dapm_context *dapm = &codec->dapm; 3817 unsigned int reg; 3818 int ret, i; 3819 3820 wm8994->hubs.codec = codec; 3821 codec->control_data = control->regmap; 3822 3823 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 3824 3825 mutex_init(&wm8994->accdet_lock); 3826 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 3827 wm1811_jackdet_bootstrap); 3828 3829 switch (control->type) { 3830 case WM8994: 3831 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 3832 break; 3833 case WM1811: 3834 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 3835 break; 3836 default: 3837 break; 3838 } 3839 3840 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 3841 init_completion(&wm8994->fll_locked[i]); 3842 3843 wm8994->micdet_irq = control->pdata.micdet_irq; 3844 3845 pm_runtime_enable(codec->dev); 3846 pm_runtime_idle(codec->dev); 3847 3848 /* By default use idle_bias_off, will override for WM8994 */ 3849 codec->dapm.idle_bias_off = 1; 3850 3851 /* Set revision-specific configuration */ 3852 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 3853 switch (control->type) { 3854 case WM8994: 3855 /* Single ended line outputs should have VMID on. */ 3856 if (!control->pdata.lineout1_diff || 3857 !control->pdata.lineout2_diff) 3858 codec->dapm.idle_bias_off = 0; 3859 3860 switch (wm8994->revision) { 3861 case 2: 3862 case 3: 3863 wm8994->hubs.dcs_codes_l = -5; 3864 wm8994->hubs.dcs_codes_r = -5; 3865 wm8994->hubs.hp_startup_mode = 1; 3866 wm8994->hubs.dcs_readback_mode = 1; 3867 wm8994->hubs.series_startup = 1; 3868 break; 3869 default: 3870 wm8994->hubs.dcs_readback_mode = 2; 3871 break; 3872 } 3873 break; 3874 3875 case WM8958: 3876 wm8994->hubs.dcs_readback_mode = 1; 3877 wm8994->hubs.hp_startup_mode = 1; 3878 3879 switch (wm8994->revision) { 3880 case 0: 3881 break; 3882 default: 3883 wm8994->fll_byp = true; 3884 break; 3885 } 3886 break; 3887 3888 case WM1811: 3889 wm8994->hubs.dcs_readback_mode = 2; 3890 wm8994->hubs.no_series_update = 1; 3891 wm8994->hubs.hp_startup_mode = 1; 3892 wm8994->hubs.no_cache_dac_hp_direct = true; 3893 wm8994->fll_byp = true; 3894 3895 wm8994->hubs.dcs_codes_l = -9; 3896 wm8994->hubs.dcs_codes_r = -7; 3897 3898 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1, 3899 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 3900 break; 3901 3902 default: 3903 break; 3904 } 3905 3906 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 3907 wm8994_fifo_error, "FIFO error", codec); 3908 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 3909 wm8994_temp_warn, "Thermal warning", codec); 3910 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 3911 wm8994_temp_shut, "Thermal shutdown", codec); 3912 3913 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 3914 wm_hubs_dcs_done, "DC servo done", 3915 &wm8994->hubs); 3916 if (ret == 0) 3917 wm8994->hubs.dcs_done_irq = true; 3918 3919 switch (control->type) { 3920 case WM8994: 3921 if (wm8994->micdet_irq) { 3922 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3923 wm8994_mic_irq, 3924 IRQF_TRIGGER_RISING, 3925 "Mic1 detect", 3926 wm8994); 3927 if (ret != 0) 3928 dev_warn(codec->dev, 3929 "Failed to request Mic1 detect IRQ: %d\n", 3930 ret); 3931 } 3932 3933 ret = wm8994_request_irq(wm8994->wm8994, 3934 WM8994_IRQ_MIC1_SHRT, 3935 wm8994_mic_irq, "Mic 1 short", 3936 wm8994); 3937 if (ret != 0) 3938 dev_warn(codec->dev, 3939 "Failed to request Mic1 short IRQ: %d\n", 3940 ret); 3941 3942 ret = wm8994_request_irq(wm8994->wm8994, 3943 WM8994_IRQ_MIC2_DET, 3944 wm8994_mic_irq, "Mic 2 detect", 3945 wm8994); 3946 if (ret != 0) 3947 dev_warn(codec->dev, 3948 "Failed to request Mic2 detect IRQ: %d\n", 3949 ret); 3950 3951 ret = wm8994_request_irq(wm8994->wm8994, 3952 WM8994_IRQ_MIC2_SHRT, 3953 wm8994_mic_irq, "Mic 2 short", 3954 wm8994); 3955 if (ret != 0) 3956 dev_warn(codec->dev, 3957 "Failed to request Mic2 short IRQ: %d\n", 3958 ret); 3959 break; 3960 3961 case WM8958: 3962 case WM1811: 3963 if (wm8994->micdet_irq) { 3964 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 3965 wm8958_mic_irq, 3966 IRQF_TRIGGER_RISING, 3967 "Mic detect", 3968 wm8994); 3969 if (ret != 0) 3970 dev_warn(codec->dev, 3971 "Failed to request Mic detect IRQ: %d\n", 3972 ret); 3973 } else { 3974 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 3975 wm8958_mic_irq, "Mic detect", 3976 wm8994); 3977 } 3978 } 3979 3980 switch (control->type) { 3981 case WM1811: 3982 if (control->cust_id > 1 || wm8994->revision > 1) { 3983 ret = wm8994_request_irq(wm8994->wm8994, 3984 WM8994_IRQ_GPIO(6), 3985 wm1811_jackdet_irq, "JACKDET", 3986 wm8994); 3987 if (ret == 0) 3988 wm8994->jackdet = true; 3989 } 3990 break; 3991 default: 3992 break; 3993 } 3994 3995 wm8994->fll_locked_irq = true; 3996 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 3997 ret = wm8994_request_irq(wm8994->wm8994, 3998 WM8994_IRQ_FLL1_LOCK + i, 3999 wm8994_fll_locked_irq, "FLL lock", 4000 &wm8994->fll_locked[i]); 4001 if (ret != 0) 4002 wm8994->fll_locked_irq = false; 4003 } 4004 4005 /* Make sure we can read from the GPIOs if they're inputs */ 4006 pm_runtime_get_sync(codec->dev); 4007 4008 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4009 * configured on init - if a system wants to do this dynamically 4010 * at runtime we can deal with that then. 4011 */ 4012 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4013 if (ret < 0) { 4014 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 4015 goto err_irq; 4016 } 4017 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4018 wm8994->lrclk_shared[0] = 1; 4019 wm8994_dai[0].symmetric_rates = 1; 4020 } else { 4021 wm8994->lrclk_shared[0] = 0; 4022 } 4023 4024 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4025 if (ret < 0) { 4026 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 4027 goto err_irq; 4028 } 4029 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4030 wm8994->lrclk_shared[1] = 1; 4031 wm8994_dai[1].symmetric_rates = 1; 4032 } else { 4033 wm8994->lrclk_shared[1] = 0; 4034 } 4035 4036 pm_runtime_put(codec->dev); 4037 4038 /* Latch volume update bits */ 4039 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4040 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg, 4041 wm8994_vu_bits[i].mask, 4042 wm8994_vu_bits[i].mask); 4043 4044 /* Set the low bit of the 3D stereo depth so TLV matches */ 4045 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 4046 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4047 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4048 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 4049 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4050 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4051 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 4052 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4053 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4054 4055 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4056 * use this; it only affects behaviour on idle TDM clock 4057 * cycles. */ 4058 switch (control->type) { 4059 case WM8994: 4060 case WM8958: 4061 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, 4062 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4063 break; 4064 default: 4065 break; 4066 } 4067 4068 /* Put MICBIAS into bypass mode by default on newer devices */ 4069 switch (control->type) { 4070 case WM8958: 4071 case WM1811: 4072 snd_soc_update_bits(codec, WM8958_MICBIAS1, 4073 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4074 snd_soc_update_bits(codec, WM8958_MICBIAS2, 4075 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4076 break; 4077 default: 4078 break; 4079 } 4080 4081 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4082 wm_hubs_update_class_w(codec); 4083 4084 wm8994_handle_pdata(wm8994); 4085 4086 wm_hubs_add_analogue_controls(codec); 4087 snd_soc_add_codec_controls(codec, wm8994_snd_controls, 4088 ARRAY_SIZE(wm8994_snd_controls)); 4089 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4090 ARRAY_SIZE(wm8994_dapm_widgets)); 4091 4092 switch (control->type) { 4093 case WM8994: 4094 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4095 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4096 if (wm8994->revision < 4) { 4097 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4098 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4099 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4100 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4101 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4102 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4103 } else { 4104 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4105 ARRAY_SIZE(wm8994_lateclk_widgets)); 4106 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4107 ARRAY_SIZE(wm8994_adc_widgets)); 4108 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4109 ARRAY_SIZE(wm8994_dac_widgets)); 4110 } 4111 break; 4112 case WM8958: 4113 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4114 ARRAY_SIZE(wm8958_snd_controls)); 4115 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4116 ARRAY_SIZE(wm8958_dapm_widgets)); 4117 if (wm8994->revision < 1) { 4118 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4119 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4120 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4121 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4122 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4123 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4124 } else { 4125 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4126 ARRAY_SIZE(wm8994_lateclk_widgets)); 4127 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4128 ARRAY_SIZE(wm8994_adc_widgets)); 4129 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4130 ARRAY_SIZE(wm8994_dac_widgets)); 4131 } 4132 break; 4133 4134 case WM1811: 4135 snd_soc_add_codec_controls(codec, wm8958_snd_controls, 4136 ARRAY_SIZE(wm8958_snd_controls)); 4137 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4138 ARRAY_SIZE(wm8958_dapm_widgets)); 4139 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4140 ARRAY_SIZE(wm8994_lateclk_widgets)); 4141 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4142 ARRAY_SIZE(wm8994_adc_widgets)); 4143 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4144 ARRAY_SIZE(wm8994_dac_widgets)); 4145 break; 4146 } 4147 4148 wm_hubs_add_analogue_routes(codec, 0, 0); 4149 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4150 4151 switch (control->type) { 4152 case WM8994: 4153 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4154 ARRAY_SIZE(wm8994_intercon)); 4155 4156 if (wm8994->revision < 4) { 4157 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4158 ARRAY_SIZE(wm8994_revd_intercon)); 4159 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4160 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4161 } else { 4162 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4163 ARRAY_SIZE(wm8994_lateclk_intercon)); 4164 } 4165 break; 4166 case WM8958: 4167 if (wm8994->revision < 1) { 4168 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4169 ARRAY_SIZE(wm8994_intercon)); 4170 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4171 ARRAY_SIZE(wm8994_revd_intercon)); 4172 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4173 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4174 } else { 4175 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4176 ARRAY_SIZE(wm8994_lateclk_intercon)); 4177 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4178 ARRAY_SIZE(wm8958_intercon)); 4179 } 4180 4181 wm8958_dsp2_init(codec); 4182 break; 4183 case WM1811: 4184 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4185 ARRAY_SIZE(wm8994_lateclk_intercon)); 4186 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4187 ARRAY_SIZE(wm8958_intercon)); 4188 break; 4189 } 4190 4191 return 0; 4192 4193 err_irq: 4194 if (wm8994->jackdet) 4195 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4196 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4197 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4198 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4199 if (wm8994->micdet_irq) 4200 free_irq(wm8994->micdet_irq, wm8994); 4201 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4202 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4203 &wm8994->fll_locked[i]); 4204 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4205 &wm8994->hubs); 4206 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4207 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4208 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4209 4210 return ret; 4211 } 4212 4213 static int wm8994_codec_remove(struct snd_soc_codec *codec) 4214 { 4215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 4216 struct wm8994 *control = wm8994->wm8994; 4217 int i; 4218 4219 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 4220 4221 pm_runtime_disable(codec->dev); 4222 4223 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4224 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4225 &wm8994->fll_locked[i]); 4226 4227 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4228 &wm8994->hubs); 4229 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); 4230 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); 4231 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); 4232 4233 if (wm8994->jackdet) 4234 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4235 4236 switch (control->type) { 4237 case WM8994: 4238 if (wm8994->micdet_irq) 4239 free_irq(wm8994->micdet_irq, wm8994); 4240 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4241 wm8994); 4242 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4243 wm8994); 4244 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4245 wm8994); 4246 break; 4247 4248 case WM1811: 4249 case WM8958: 4250 if (wm8994->micdet_irq) 4251 free_irq(wm8994->micdet_irq, wm8994); 4252 break; 4253 } 4254 release_firmware(wm8994->mbc); 4255 release_firmware(wm8994->mbc_vss); 4256 release_firmware(wm8994->enh_eq); 4257 kfree(wm8994->retune_mobile_texts); 4258 return 0; 4259 } 4260 4261 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 4262 .probe = wm8994_codec_probe, 4263 .remove = wm8994_codec_remove, 4264 .suspend = wm8994_codec_suspend, 4265 .resume = wm8994_codec_resume, 4266 .set_bias_level = wm8994_set_bias_level, 4267 }; 4268 4269 static int __devinit wm8994_probe(struct platform_device *pdev) 4270 { 4271 struct wm8994_priv *wm8994; 4272 4273 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4274 GFP_KERNEL); 4275 if (wm8994 == NULL) 4276 return -ENOMEM; 4277 platform_set_drvdata(pdev, wm8994); 4278 4279 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4280 4281 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, 4282 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4283 } 4284 4285 static int __devexit wm8994_remove(struct platform_device *pdev) 4286 { 4287 snd_soc_unregister_codec(&pdev->dev); 4288 return 0; 4289 } 4290 4291 #ifdef CONFIG_PM_SLEEP 4292 static int wm8994_suspend(struct device *dev) 4293 { 4294 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4295 4296 /* Drop down to power saving mode when system is suspended */ 4297 if (wm8994->jackdet && !wm8994->active_refcount) 4298 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4299 WM1811_JACKDET_MODE_MASK, 4300 wm8994->jackdet_mode); 4301 4302 return 0; 4303 } 4304 4305 static int wm8994_resume(struct device *dev) 4306 { 4307 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4308 4309 if (wm8994->jackdet && wm8994->jack_cb) 4310 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4311 WM1811_JACKDET_MODE_MASK, 4312 WM1811_JACKDET_MODE_AUDIO); 4313 4314 return 0; 4315 } 4316 #endif 4317 4318 static const struct dev_pm_ops wm8994_pm_ops = { 4319 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4320 }; 4321 4322 static struct platform_driver wm8994_codec_driver = { 4323 .driver = { 4324 .name = "wm8994-codec", 4325 .owner = THIS_MODULE, 4326 .pm = &wm8994_pm_ops, 4327 }, 4328 .probe = wm8994_probe, 4329 .remove = __devexit_p(wm8994_remove), 4330 }; 4331 4332 module_platform_driver(wm8994_codec_driver); 4333 4334 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4335 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4336 MODULE_LICENSE("GPL"); 4337 MODULE_ALIAS("platform:wm8994-codec"); 4338