1 /* 2 * wm8993.c -- WM8993 ALSA SoC audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/spi/spi.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/tlv.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/initval.h> 27 #include <sound/wm8993.h> 28 29 #include "wm8993.h" 30 #include "wm_hubs.h" 31 32 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = { 33 0x8993, /* R0 - Software Reset */ 34 0x0000, /* R1 - Power Management (1) */ 35 0x6000, /* R2 - Power Management (2) */ 36 0x0000, /* R3 - Power Management (3) */ 37 0x4050, /* R4 - Audio Interface (1) */ 38 0x4000, /* R5 - Audio Interface (2) */ 39 0x01C8, /* R6 - Clocking 1 */ 40 0x0000, /* R7 - Clocking 2 */ 41 0x0000, /* R8 - Audio Interface (3) */ 42 0x0040, /* R9 - Audio Interface (4) */ 43 0x0004, /* R10 - DAC CTRL */ 44 0x00C0, /* R11 - Left DAC Digital Volume */ 45 0x00C0, /* R12 - Right DAC Digital Volume */ 46 0x0000, /* R13 - Digital Side Tone */ 47 0x0300, /* R14 - ADC CTRL */ 48 0x00C0, /* R15 - Left ADC Digital Volume */ 49 0x00C0, /* R16 - Right ADC Digital Volume */ 50 0x0000, /* R17 */ 51 0x0000, /* R18 - GPIO CTRL 1 */ 52 0x0010, /* R19 - GPIO1 */ 53 0x0000, /* R20 - IRQ_DEBOUNCE */ 54 0x0000, /* R21 */ 55 0x8000, /* R22 - GPIOCTRL 2 */ 56 0x0800, /* R23 - GPIO_POL */ 57 0x008B, /* R24 - Left Line Input 1&2 Volume */ 58 0x008B, /* R25 - Left Line Input 3&4 Volume */ 59 0x008B, /* R26 - Right Line Input 1&2 Volume */ 60 0x008B, /* R27 - Right Line Input 3&4 Volume */ 61 0x006D, /* R28 - Left Output Volume */ 62 0x006D, /* R29 - Right Output Volume */ 63 0x0066, /* R30 - Line Outputs Volume */ 64 0x0020, /* R31 - HPOUT2 Volume */ 65 0x0079, /* R32 - Left OPGA Volume */ 66 0x0079, /* R33 - Right OPGA Volume */ 67 0x0003, /* R34 - SPKMIXL Attenuation */ 68 0x0003, /* R35 - SPKMIXR Attenuation */ 69 0x0011, /* R36 - SPKOUT Mixers */ 70 0x0100, /* R37 - SPKOUT Boost */ 71 0x0079, /* R38 - Speaker Volume Left */ 72 0x0079, /* R39 - Speaker Volume Right */ 73 0x0000, /* R40 - Input Mixer2 */ 74 0x0000, /* R41 - Input Mixer3 */ 75 0x0000, /* R42 - Input Mixer4 */ 76 0x0000, /* R43 - Input Mixer5 */ 77 0x0000, /* R44 - Input Mixer6 */ 78 0x0000, /* R45 - Output Mixer1 */ 79 0x0000, /* R46 - Output Mixer2 */ 80 0x0000, /* R47 - Output Mixer3 */ 81 0x0000, /* R48 - Output Mixer4 */ 82 0x0000, /* R49 - Output Mixer5 */ 83 0x0000, /* R50 - Output Mixer6 */ 84 0x0000, /* R51 - HPOUT2 Mixer */ 85 0x0000, /* R52 - Line Mixer1 */ 86 0x0000, /* R53 - Line Mixer2 */ 87 0x0000, /* R54 - Speaker Mixer */ 88 0x0000, /* R55 - Additional Control */ 89 0x0000, /* R56 - AntiPOP1 */ 90 0x0000, /* R57 - AntiPOP2 */ 91 0x0000, /* R58 - MICBIAS */ 92 0x0000, /* R59 */ 93 0x0000, /* R60 - FLL Control 1 */ 94 0x0000, /* R61 - FLL Control 2 */ 95 0x0000, /* R62 - FLL Control 3 */ 96 0x2EE0, /* R63 - FLL Control 4 */ 97 0x0002, /* R64 - FLL Control 5 */ 98 0x2287, /* R65 - Clocking 3 */ 99 0x025F, /* R66 - Clocking 4 */ 100 0x0000, /* R67 - MW Slave Control */ 101 0x0000, /* R68 */ 102 0x0002, /* R69 - Bus Control 1 */ 103 0x0000, /* R70 - Write Sequencer 0 */ 104 0x0000, /* R71 - Write Sequencer 1 */ 105 0x0000, /* R72 - Write Sequencer 2 */ 106 0x0000, /* R73 - Write Sequencer 3 */ 107 0x0000, /* R74 - Write Sequencer 4 */ 108 0x0000, /* R75 - Write Sequencer 5 */ 109 0x1F25, /* R76 - Charge Pump 1 */ 110 0x0000, /* R77 */ 111 0x0000, /* R78 */ 112 0x0000, /* R79 */ 113 0x0000, /* R80 */ 114 0x0000, /* R81 - Class W 0 */ 115 0x0000, /* R82 */ 116 0x0000, /* R83 */ 117 0x0000, /* R84 - DC Servo 0 */ 118 0x054A, /* R85 - DC Servo 1 */ 119 0x0000, /* R86 */ 120 0x0000, /* R87 - DC Servo 3 */ 121 0x0000, /* R88 - DC Servo Readback 0 */ 122 0x0000, /* R89 - DC Servo Readback 1 */ 123 0x0000, /* R90 - DC Servo Readback 2 */ 124 0x0000, /* R91 */ 125 0x0000, /* R92 */ 126 0x0000, /* R93 */ 127 0x0000, /* R94 */ 128 0x0000, /* R95 */ 129 0x0100, /* R96 - Analogue HP 0 */ 130 0x0000, /* R97 */ 131 0x0000, /* R98 - EQ1 */ 132 0x000C, /* R99 - EQ2 */ 133 0x000C, /* R100 - EQ3 */ 134 0x000C, /* R101 - EQ4 */ 135 0x000C, /* R102 - EQ5 */ 136 0x000C, /* R103 - EQ6 */ 137 0x0FCA, /* R104 - EQ7 */ 138 0x0400, /* R105 - EQ8 */ 139 0x00D8, /* R106 - EQ9 */ 140 0x1EB5, /* R107 - EQ10 */ 141 0xF145, /* R108 - EQ11 */ 142 0x0B75, /* R109 - EQ12 */ 143 0x01C5, /* R110 - EQ13 */ 144 0x1C58, /* R111 - EQ14 */ 145 0xF373, /* R112 - EQ15 */ 146 0x0A54, /* R113 - EQ16 */ 147 0x0558, /* R114 - EQ17 */ 148 0x168E, /* R115 - EQ18 */ 149 0xF829, /* R116 - EQ19 */ 150 0x07AD, /* R117 - EQ20 */ 151 0x1103, /* R118 - EQ21 */ 152 0x0564, /* R119 - EQ22 */ 153 0x0559, /* R120 - EQ23 */ 154 0x4000, /* R121 - EQ24 */ 155 0x0000, /* R122 - Digital Pulls */ 156 0x0F08, /* R123 - DRC Control 1 */ 157 0x0000, /* R124 - DRC Control 2 */ 158 0x0080, /* R125 - DRC Control 3 */ 159 0x0000, /* R126 - DRC Control 4 */ 160 }; 161 162 static struct { 163 int ratio; 164 int clk_sys_rate; 165 } clk_sys_rates[] = { 166 { 64, 0 }, 167 { 128, 1 }, 168 { 192, 2 }, 169 { 256, 3 }, 170 { 384, 4 }, 171 { 512, 5 }, 172 { 768, 6 }, 173 { 1024, 7 }, 174 { 1408, 8 }, 175 { 1536, 9 }, 176 }; 177 178 static struct { 179 int rate; 180 int sample_rate; 181 } sample_rates[] = { 182 { 8000, 0 }, 183 { 11025, 1 }, 184 { 12000, 1 }, 185 { 16000, 2 }, 186 { 22050, 3 }, 187 { 24000, 3 }, 188 { 32000, 4 }, 189 { 44100, 5 }, 190 { 48000, 5 }, 191 }; 192 193 static struct { 194 int div; /* *10 due to .5s */ 195 int bclk_div; 196 } bclk_divs[] = { 197 { 10, 0 }, 198 { 15, 1 }, 199 { 20, 2 }, 200 { 30, 3 }, 201 { 40, 4 }, 202 { 55, 5 }, 203 { 60, 6 }, 204 { 80, 7 }, 205 { 110, 8 }, 206 { 120, 9 }, 207 { 160, 10 }, 208 { 220, 11 }, 209 { 240, 12 }, 210 { 320, 13 }, 211 { 440, 14 }, 212 { 480, 15 }, 213 }; 214 215 struct wm8993_priv { 216 u16 reg_cache[WM8993_REGISTER_COUNT]; 217 struct wm8993_platform_data pdata; 218 struct snd_soc_codec codec; 219 int master; 220 int sysclk_source; 221 int tdm_slots; 222 int tdm_width; 223 unsigned int mclk_rate; 224 unsigned int sysclk_rate; 225 unsigned int fs; 226 unsigned int bclk; 227 int class_w_users; 228 unsigned int fll_fref; 229 unsigned int fll_fout; 230 }; 231 232 static unsigned int wm8993_read_hw(struct snd_soc_codec *codec, u8 reg) 233 { 234 struct i2c_msg xfer[2]; 235 u16 data; 236 int ret; 237 struct i2c_client *i2c = codec->control_data; 238 239 /* Write register */ 240 xfer[0].addr = i2c->addr; 241 xfer[0].flags = 0; 242 xfer[0].len = 1; 243 xfer[0].buf = ® 244 245 /* Read data */ 246 xfer[1].addr = i2c->addr; 247 xfer[1].flags = I2C_M_RD; 248 xfer[1].len = 2; 249 xfer[1].buf = (u8 *)&data; 250 251 ret = i2c_transfer(i2c->adapter, xfer, 2); 252 if (ret != 2) { 253 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret); 254 return 0; 255 } 256 257 return (data >> 8) | ((data & 0xff) << 8); 258 } 259 260 static int wm8993_volatile(unsigned int reg) 261 { 262 switch (reg) { 263 case WM8993_SOFTWARE_RESET: 264 case WM8993_DC_SERVO_0: 265 case WM8993_DC_SERVO_READBACK_0: 266 case WM8993_DC_SERVO_READBACK_1: 267 case WM8993_DC_SERVO_READBACK_2: 268 return 1; 269 default: 270 return 0; 271 } 272 } 273 274 static unsigned int wm8993_read(struct snd_soc_codec *codec, 275 unsigned int reg) 276 { 277 u16 *reg_cache = codec->reg_cache; 278 279 BUG_ON(reg > WM8993_MAX_REGISTER); 280 281 if (wm8993_volatile(reg)) 282 return wm8993_read_hw(codec, reg); 283 else 284 return reg_cache[reg]; 285 } 286 287 static int wm8993_write(struct snd_soc_codec *codec, unsigned int reg, 288 unsigned int value) 289 { 290 u16 *reg_cache = codec->reg_cache; 291 u8 data[3]; 292 int ret; 293 294 BUG_ON(reg > WM8993_MAX_REGISTER); 295 296 /* data is 297 * D15..D9 WM8993 register offset 298 * D8...D0 register data 299 */ 300 data[0] = reg; 301 data[1] = value >> 8; 302 data[2] = value & 0x00ff; 303 304 if (!wm8993_volatile(reg)) 305 reg_cache[reg] = value; 306 307 ret = codec->hw_write(codec->control_data, data, 3); 308 309 if (ret == 3) 310 return 0; 311 if (ret < 0) 312 return ret; 313 return -EIO; 314 } 315 316 struct _fll_div { 317 u16 fll_fratio; 318 u16 fll_outdiv; 319 u16 fll_clk_ref_div; 320 u16 n; 321 u16 k; 322 }; 323 324 /* The size in bits of the FLL divide multiplied by 10 325 * to allow rounding later */ 326 #define FIXED_FLL_SIZE ((1 << 16) * 10) 327 328 static struct { 329 unsigned int min; 330 unsigned int max; 331 u16 fll_fratio; 332 int ratio; 333 } fll_fratios[] = { 334 { 0, 64000, 4, 16 }, 335 { 64000, 128000, 3, 8 }, 336 { 128000, 256000, 2, 4 }, 337 { 256000, 1000000, 1, 2 }, 338 { 1000000, 13500000, 0, 1 }, 339 }; 340 341 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 342 unsigned int Fout) 343 { 344 u64 Kpart; 345 unsigned int K, Ndiv, Nmod, target; 346 unsigned int div; 347 int i; 348 349 /* Fref must be <=13.5MHz */ 350 div = 1; 351 fll_div->fll_clk_ref_div = 0; 352 while ((Fref / div) > 13500000) { 353 div *= 2; 354 fll_div->fll_clk_ref_div++; 355 356 if (div > 8) { 357 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 358 Fref); 359 return -EINVAL; 360 } 361 } 362 363 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 364 365 /* Apply the division for our remaining calculations */ 366 Fref /= div; 367 368 /* Fvco should be 90-100MHz; don't check the upper bound */ 369 div = 0; 370 target = Fout * 2; 371 while (target < 90000000) { 372 div++; 373 target *= 2; 374 if (div > 7) { 375 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 376 Fout); 377 return -EINVAL; 378 } 379 } 380 fll_div->fll_outdiv = div; 381 382 pr_debug("Fvco=%dHz\n", target); 383 384 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 385 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 386 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 387 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 388 target /= fll_fratios[i].ratio; 389 break; 390 } 391 } 392 if (i == ARRAY_SIZE(fll_fratios)) { 393 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 394 return -EINVAL; 395 } 396 397 /* Now, calculate N.K */ 398 Ndiv = target / Fref; 399 400 fll_div->n = Ndiv; 401 Nmod = target % Fref; 402 pr_debug("Nmod=%d\n", Nmod); 403 404 /* Calculate fractional part - scale up so we can round. */ 405 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 406 407 do_div(Kpart, Fref); 408 409 K = Kpart & 0xFFFFFFFF; 410 411 if ((K % 10) >= 5) 412 K += 5; 413 414 /* Move down to proper range now rounding is done */ 415 fll_div->k = K / 10; 416 417 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 418 fll_div->n, fll_div->k, 419 fll_div->fll_fratio, fll_div->fll_outdiv, 420 fll_div->fll_clk_ref_div); 421 422 return 0; 423 } 424 425 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 426 unsigned int Fref, unsigned int Fout) 427 { 428 struct snd_soc_codec *codec = dai->codec; 429 struct wm8993_priv *wm8993 = codec->private_data; 430 u16 reg1, reg4, reg5; 431 struct _fll_div fll_div; 432 int ret; 433 434 /* Any change? */ 435 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout) 436 return 0; 437 438 /* Disable the FLL */ 439 if (Fout == 0) { 440 dev_dbg(codec->dev, "FLL disabled\n"); 441 wm8993->fll_fref = 0; 442 wm8993->fll_fout = 0; 443 444 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1); 445 reg1 &= ~WM8993_FLL_ENA; 446 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1); 447 448 return 0; 449 } 450 451 ret = fll_factors(&fll_div, Fref, Fout); 452 if (ret != 0) 453 return ret; 454 455 reg5 = wm8993_read(codec, WM8993_FLL_CONTROL_5); 456 reg5 &= ~WM8993_FLL_CLK_SRC_MASK; 457 458 switch (fll_id) { 459 case WM8993_FLL_MCLK: 460 break; 461 462 case WM8993_FLL_LRCLK: 463 reg5 |= 1; 464 break; 465 466 case WM8993_FLL_BCLK: 467 reg5 |= 2; 468 break; 469 470 default: 471 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 472 return -EINVAL; 473 } 474 475 /* Any FLL configuration change requires that the FLL be 476 * disabled first. */ 477 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1); 478 reg1 &= ~WM8993_FLL_ENA; 479 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1); 480 481 /* Apply the configuration */ 482 if (fll_div.k) 483 reg1 |= WM8993_FLL_FRAC_MASK; 484 else 485 reg1 &= ~WM8993_FLL_FRAC_MASK; 486 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1); 487 488 wm8993_write(codec, WM8993_FLL_CONTROL_2, 489 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) | 490 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT)); 491 wm8993_write(codec, WM8993_FLL_CONTROL_3, fll_div.k); 492 493 reg4 = wm8993_read(codec, WM8993_FLL_CONTROL_4); 494 reg4 &= ~WM8993_FLL_N_MASK; 495 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT; 496 wm8993_write(codec, WM8993_FLL_CONTROL_4, reg4); 497 498 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; 499 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; 500 wm8993_write(codec, WM8993_FLL_CONTROL_5, reg5); 501 502 /* Enable the FLL */ 503 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); 504 505 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 506 507 wm8993->fll_fref = Fref; 508 wm8993->fll_fout = Fout; 509 510 return 0; 511 } 512 513 static int configure_clock(struct snd_soc_codec *codec) 514 { 515 struct wm8993_priv *wm8993 = codec->private_data; 516 unsigned int reg; 517 518 /* This should be done on init() for bypass paths */ 519 switch (wm8993->sysclk_source) { 520 case WM8993_SYSCLK_MCLK: 521 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); 522 523 reg = wm8993_read(codec, WM8993_CLOCKING_2); 524 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); 525 if (wm8993->mclk_rate > 13500000) { 526 reg |= WM8993_MCLK_DIV; 527 wm8993->sysclk_rate = wm8993->mclk_rate / 2; 528 } else { 529 reg &= ~WM8993_MCLK_DIV; 530 wm8993->sysclk_rate = wm8993->mclk_rate; 531 } 532 wm8993_write(codec, WM8993_CLOCKING_2, reg); 533 break; 534 535 case WM8993_SYSCLK_FLL: 536 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 537 wm8993->fll_fout); 538 539 reg = wm8993_read(codec, WM8993_CLOCKING_2); 540 reg |= WM8993_SYSCLK_SRC; 541 if (wm8993->fll_fout > 13500000) { 542 reg |= WM8993_MCLK_DIV; 543 wm8993->sysclk_rate = wm8993->fll_fout / 2; 544 } else { 545 reg &= ~WM8993_MCLK_DIV; 546 wm8993->sysclk_rate = wm8993->fll_fout; 547 } 548 wm8993_write(codec, WM8993_CLOCKING_2, reg); 549 break; 550 551 default: 552 dev_err(codec->dev, "System clock not configured\n"); 553 return -EINVAL; 554 } 555 556 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate); 557 558 return 0; 559 } 560 561 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 562 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0); 563 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0); 564 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); 565 static const unsigned int drc_max_tlv[] = { 566 TLV_DB_RANGE_HEAD(4), 567 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0), 568 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), 569 }; 570 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); 571 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0); 572 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 573 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 574 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 575 576 static const char *dac_deemph_text[] = { 577 "None", 578 "32kHz", 579 "44.1kHz", 580 "48kHz", 581 }; 582 583 static const struct soc_enum dac_deemph = 584 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text); 585 586 static const char *adc_hpf_text[] = { 587 "Hi-Fi", 588 "Voice 1", 589 "Voice 2", 590 "Voice 3", 591 }; 592 593 static const struct soc_enum adc_hpf = 594 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text); 595 596 static const char *drc_path_text[] = { 597 "ADC", 598 "DAC" 599 }; 600 601 static const struct soc_enum drc_path = 602 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text); 603 604 static const char *drc_r0_text[] = { 605 "1", 606 "1/2", 607 "1/4", 608 "1/8", 609 "1/16", 610 "0", 611 }; 612 613 static const struct soc_enum drc_r0 = 614 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text); 615 616 static const char *drc_r1_text[] = { 617 "1", 618 "1/2", 619 "1/4", 620 "1/8", 621 "0", 622 }; 623 624 static const struct soc_enum drc_r1 = 625 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text); 626 627 static const char *drc_attack_text[] = { 628 "Reserved", 629 "181us", 630 "363us", 631 "726us", 632 "1.45ms", 633 "2.9ms", 634 "5.8ms", 635 "11.6ms", 636 "23.2ms", 637 "46.4ms", 638 "92.8ms", 639 "185.6ms", 640 }; 641 642 static const struct soc_enum drc_attack = 643 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text); 644 645 static const char *drc_decay_text[] = { 646 "186ms", 647 "372ms", 648 "743ms", 649 "1.49s", 650 "2.97ms", 651 "5.94ms", 652 "11.89ms", 653 "23.78ms", 654 "47.56ms", 655 }; 656 657 static const struct soc_enum drc_decay = 658 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text); 659 660 static const char *drc_ff_text[] = { 661 "5 samples", 662 "9 samples", 663 }; 664 665 static const struct soc_enum drc_ff = 666 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text); 667 668 static const char *drc_qr_rate_text[] = { 669 "0.725ms", 670 "1.45ms", 671 "5.8ms", 672 }; 673 674 static const struct soc_enum drc_qr_rate = 675 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text); 676 677 static const char *drc_smooth_text[] = { 678 "Low", 679 "Medium", 680 "High", 681 }; 682 683 static const struct soc_enum drc_smooth = 684 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text); 685 686 static const struct snd_kcontrol_new wm8993_snd_controls[] = { 687 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE, 688 5, 9, 12, 0, sidetone_tlv), 689 690 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0), 691 SOC_ENUM("DRC Path", drc_path), 692 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2, 693 2, 60, 1, drc_comp_threash), 694 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3, 695 11, 30, 1, drc_comp_amp), 696 SOC_ENUM("DRC R0", drc_r0), 697 SOC_ENUM("DRC R1", drc_r1), 698 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1, 699 drc_min_tlv), 700 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0, 701 drc_max_tlv), 702 SOC_ENUM("DRC Attack Rate", drc_attack), 703 SOC_ENUM("DRC Decay Rate", drc_decay), 704 SOC_ENUM("DRC FF Delay", drc_ff), 705 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0), 706 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0), 707 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0, 708 drc_qr_tlv), 709 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate), 710 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0), 711 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0), 712 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth), 713 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0, 714 drc_startup_tlv), 715 716 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0), 717 718 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME, 719 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 720 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0), 721 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 722 723 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME, 724 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 725 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0, 726 dac_boost_tlv), 727 SOC_ENUM("DAC Deemphasis", dac_deemph), 728 729 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION, 730 2, 1, 1, wm_hubs_spkmix_tlv), 731 732 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION, 733 2, 1, 1, wm_hubs_spkmix_tlv), 734 }; 735 736 static const struct snd_kcontrol_new wm8993_eq_controls[] = { 737 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv), 738 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv), 739 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv), 740 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv), 741 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv), 742 }; 743 744 static int clk_sys_event(struct snd_soc_dapm_widget *w, 745 struct snd_kcontrol *kcontrol, int event) 746 { 747 struct snd_soc_codec *codec = w->codec; 748 749 switch (event) { 750 case SND_SOC_DAPM_PRE_PMU: 751 return configure_clock(codec); 752 753 case SND_SOC_DAPM_POST_PMD: 754 break; 755 } 756 757 return 0; 758 } 759 760 /* 761 * When used with DAC outputs only the WM8993 charge pump supports 762 * operation in class W mode, providing very low power consumption 763 * when used with digital sources. Enable and disable this mode 764 * automatically depending on the mixer configuration. 765 * 766 * Currently the only supported paths are the direct DAC->headphone 767 * paths (which provide minimum power consumption anyway). 768 */ 769 static int class_w_put(struct snd_kcontrol *kcontrol, 770 struct snd_ctl_elem_value *ucontrol) 771 { 772 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 773 struct snd_soc_codec *codec = widget->codec; 774 struct wm8993_priv *wm8993 = codec->private_data; 775 int ret; 776 777 /* Turn it off if we're using the main output mixer */ 778 if (ucontrol->value.integer.value[0] == 0) { 779 if (wm8993->class_w_users == 0) { 780 dev_dbg(codec->dev, "Disabling Class W\n"); 781 snd_soc_update_bits(codec, WM8993_CLASS_W_0, 782 WM8993_CP_DYN_FREQ | 783 WM8993_CP_DYN_V, 784 0); 785 } 786 wm8993->class_w_users++; 787 } 788 789 /* Implement the change */ 790 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 791 792 /* Enable it if we're using the direct DAC path */ 793 if (ucontrol->value.integer.value[0] == 1) { 794 if (wm8993->class_w_users == 1) { 795 dev_dbg(codec->dev, "Enabling Class W\n"); 796 snd_soc_update_bits(codec, WM8993_CLASS_W_0, 797 WM8993_CP_DYN_FREQ | 798 WM8993_CP_DYN_V, 799 WM8993_CP_DYN_FREQ | 800 WM8993_CP_DYN_V); 801 } 802 wm8993->class_w_users--; 803 } 804 805 dev_dbg(codec->dev, "Indirect DAC use count now %d\n", 806 wm8993->class_w_users); 807 808 return ret; 809 } 810 811 #define SOC_DAPM_ENUM_W(xname, xenum) \ 812 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 813 .info = snd_soc_info_enum_double, \ 814 .get = snd_soc_dapm_get_enum_double, \ 815 .put = class_w_put, \ 816 .private_value = (unsigned long)&xenum } 817 818 static const char *hp_mux_text[] = { 819 "Mixer", 820 "DAC", 821 }; 822 823 static const struct soc_enum hpl_enum = 824 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text); 825 826 static const struct snd_kcontrol_new hpl_mux = 827 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum); 828 829 static const struct soc_enum hpr_enum = 830 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text); 831 832 static const struct snd_kcontrol_new hpr_mux = 833 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum); 834 835 static const struct snd_kcontrol_new left_speaker_mixer[] = { 836 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), 837 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), 838 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0), 839 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 840 }; 841 842 static const struct snd_kcontrol_new right_speaker_mixer[] = { 843 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 844 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0), 845 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0), 846 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0), 847 }; 848 849 static const char *aif_text[] = { 850 "Left", "Right" 851 }; 852 853 static const struct soc_enum aifoutl_enum = 854 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text); 855 856 static const struct snd_kcontrol_new aifoutl_mux = 857 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 858 859 static const struct soc_enum aifoutr_enum = 860 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text); 861 862 static const struct snd_kcontrol_new aifoutr_mux = 863 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 864 865 static const struct soc_enum aifinl_enum = 866 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text); 867 868 static const struct snd_kcontrol_new aifinl_mux = 869 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 870 871 static const struct soc_enum aifinr_enum = 872 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text); 873 874 static const struct snd_kcontrol_new aifinr_mux = 875 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 876 877 static const char *sidetone_text[] = { 878 "None", "Left", "Right" 879 }; 880 881 static const struct soc_enum sidetonel_enum = 882 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text); 883 884 static const struct snd_kcontrol_new sidetonel_mux = 885 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum); 886 887 static const struct soc_enum sidetoner_enum = 888 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text); 889 890 static const struct snd_kcontrol_new sidetoner_mux = 891 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum); 892 893 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = { 894 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event, 895 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 896 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0), 897 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0), 898 899 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0), 900 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0), 901 902 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 903 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 904 905 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 906 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 907 908 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 909 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 910 911 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 912 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 913 914 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux), 915 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux), 916 917 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), 918 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), 919 920 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 921 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 922 923 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, 924 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 925 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0, 926 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 927 928 }; 929 930 static const struct snd_soc_dapm_route routes[] = { 931 { "ADCL", NULL, "CLK_SYS" }, 932 { "ADCL", NULL, "CLK_DSP" }, 933 { "ADCR", NULL, "CLK_SYS" }, 934 { "ADCR", NULL, "CLK_DSP" }, 935 936 { "AIFOUTL Mux", "Left", "ADCL" }, 937 { "AIFOUTL Mux", "Right", "ADCR" }, 938 { "AIFOUTR Mux", "Left", "ADCL" }, 939 { "AIFOUTR Mux", "Right", "ADCR" }, 940 941 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 942 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 943 944 { "DACL Mux", "Left", "AIFINL" }, 945 { "DACL Mux", "Right", "AIFINR" }, 946 { "DACR Mux", "Left", "AIFINL" }, 947 { "DACR Mux", "Right", "AIFINR" }, 948 949 { "DACL Sidetone", "Left", "ADCL" }, 950 { "DACL Sidetone", "Right", "ADCR" }, 951 { "DACR Sidetone", "Left", "ADCL" }, 952 { "DACR Sidetone", "Right", "ADCR" }, 953 954 { "DACL", NULL, "CLK_SYS" }, 955 { "DACL", NULL, "CLK_DSP" }, 956 { "DACL", NULL, "DACL Mux" }, 957 { "DACL", NULL, "DACL Sidetone" }, 958 { "DACR", NULL, "CLK_SYS" }, 959 { "DACR", NULL, "CLK_DSP" }, 960 { "DACR", NULL, "DACR Mux" }, 961 { "DACR", NULL, "DACR Sidetone" }, 962 963 { "Left Output Mixer", "DAC Switch", "DACL" }, 964 965 { "Right Output Mixer", "DAC Switch", "DACR" }, 966 967 { "Left Output PGA", NULL, "CLK_SYS" }, 968 969 { "Right Output PGA", NULL, "CLK_SYS" }, 970 971 { "SPKL", "DAC Switch", "DACL" }, 972 { "SPKL", NULL, "CLK_SYS" }, 973 974 { "SPKR", "DAC Switch", "DACR" }, 975 { "SPKR", NULL, "CLK_SYS" }, 976 977 { "Left Headphone Mux", "DAC", "DACL" }, 978 { "Right Headphone Mux", "DAC", "DACR" }, 979 }; 980 981 static int wm8993_set_bias_level(struct snd_soc_codec *codec, 982 enum snd_soc_bias_level level) 983 { 984 struct wm8993_priv *wm8993 = codec->private_data; 985 986 switch (level) { 987 case SND_SOC_BIAS_ON: 988 case SND_SOC_BIAS_PREPARE: 989 /* VMID=2*40k */ 990 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 991 WM8993_VMID_SEL_MASK, 0x2); 992 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 993 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); 994 break; 995 996 case SND_SOC_BIAS_STANDBY: 997 if (codec->bias_level == SND_SOC_BIAS_OFF) { 998 /* Bring up VMID with fast soft start */ 999 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1000 WM8993_STARTUP_BIAS_ENA | 1001 WM8993_VMID_BUF_ENA | 1002 WM8993_VMID_RAMP_MASK | 1003 WM8993_BIAS_SRC, 1004 WM8993_STARTUP_BIAS_ENA | 1005 WM8993_VMID_BUF_ENA | 1006 WM8993_VMID_RAMP_MASK | 1007 WM8993_BIAS_SRC); 1008 1009 /* If either line output is single ended we 1010 * need the VMID buffer */ 1011 if (!wm8993->pdata.lineout1_diff || 1012 !wm8993->pdata.lineout2_diff) 1013 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1014 WM8993_LINEOUT_VMID_BUF_ENA, 1015 WM8993_LINEOUT_VMID_BUF_ENA); 1016 1017 /* VMID=2*40k */ 1018 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1019 WM8993_VMID_SEL_MASK | 1020 WM8993_BIAS_ENA, 1021 WM8993_BIAS_ENA | 0x2); 1022 msleep(32); 1023 1024 /* Switch to normal bias */ 1025 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1026 WM8993_BIAS_SRC | 1027 WM8993_STARTUP_BIAS_ENA, 0); 1028 } 1029 1030 /* VMID=2*240k */ 1031 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1032 WM8993_VMID_SEL_MASK, 0x4); 1033 1034 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 1035 WM8993_TSHUT_ENA, 0); 1036 break; 1037 1038 case SND_SOC_BIAS_OFF: 1039 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1040 WM8993_LINEOUT_VMID_BUF_ENA, 0); 1041 1042 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1043 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 1044 0); 1045 break; 1046 } 1047 1048 codec->bias_level = level; 1049 1050 return 0; 1051 } 1052 1053 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai, 1054 int clk_id, unsigned int freq, int dir) 1055 { 1056 struct snd_soc_codec *codec = codec_dai->codec; 1057 struct wm8993_priv *wm8993 = codec->private_data; 1058 1059 switch (clk_id) { 1060 case WM8993_SYSCLK_MCLK: 1061 wm8993->mclk_rate = freq; 1062 case WM8993_SYSCLK_FLL: 1063 wm8993->sysclk_source = clk_id; 1064 break; 1065 1066 default: 1067 return -EINVAL; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai, 1074 unsigned int fmt) 1075 { 1076 struct snd_soc_codec *codec = dai->codec; 1077 struct wm8993_priv *wm8993 = codec->private_data; 1078 unsigned int aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1); 1079 unsigned int aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4); 1080 1081 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV | 1082 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK); 1083 aif4 &= ~WM8993_LRCLK_DIR; 1084 1085 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1086 case SND_SOC_DAIFMT_CBS_CFS: 1087 wm8993->master = 0; 1088 break; 1089 case SND_SOC_DAIFMT_CBS_CFM: 1090 aif4 |= WM8993_LRCLK_DIR; 1091 wm8993->master = 1; 1092 break; 1093 case SND_SOC_DAIFMT_CBM_CFS: 1094 aif1 |= WM8993_BCLK_DIR; 1095 wm8993->master = 1; 1096 break; 1097 case SND_SOC_DAIFMT_CBM_CFM: 1098 aif1 |= WM8993_BCLK_DIR; 1099 aif4 |= WM8993_LRCLK_DIR; 1100 wm8993->master = 1; 1101 break; 1102 default: 1103 return -EINVAL; 1104 } 1105 1106 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1107 case SND_SOC_DAIFMT_DSP_B: 1108 aif1 |= WM8993_AIF_LRCLK_INV; 1109 case SND_SOC_DAIFMT_DSP_A: 1110 aif1 |= 0x18; 1111 break; 1112 case SND_SOC_DAIFMT_I2S: 1113 aif1 |= 0x10; 1114 break; 1115 case SND_SOC_DAIFMT_RIGHT_J: 1116 break; 1117 case SND_SOC_DAIFMT_LEFT_J: 1118 aif1 |= 0x8; 1119 break; 1120 default: 1121 return -EINVAL; 1122 } 1123 1124 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1125 case SND_SOC_DAIFMT_DSP_A: 1126 case SND_SOC_DAIFMT_DSP_B: 1127 /* frame inversion not valid for DSP modes */ 1128 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1129 case SND_SOC_DAIFMT_NB_NF: 1130 break; 1131 case SND_SOC_DAIFMT_IB_NF: 1132 aif1 |= WM8993_AIF_BCLK_INV; 1133 break; 1134 default: 1135 return -EINVAL; 1136 } 1137 break; 1138 1139 case SND_SOC_DAIFMT_I2S: 1140 case SND_SOC_DAIFMT_RIGHT_J: 1141 case SND_SOC_DAIFMT_LEFT_J: 1142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1143 case SND_SOC_DAIFMT_NB_NF: 1144 break; 1145 case SND_SOC_DAIFMT_IB_IF: 1146 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV; 1147 break; 1148 case SND_SOC_DAIFMT_IB_NF: 1149 aif1 |= WM8993_AIF_BCLK_INV; 1150 break; 1151 case SND_SOC_DAIFMT_NB_IF: 1152 aif1 |= WM8993_AIF_LRCLK_INV; 1153 break; 1154 default: 1155 return -EINVAL; 1156 } 1157 break; 1158 default: 1159 return -EINVAL; 1160 } 1161 1162 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1163 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1164 1165 return 0; 1166 } 1167 1168 static int wm8993_hw_params(struct snd_pcm_substream *substream, 1169 struct snd_pcm_hw_params *params, 1170 struct snd_soc_dai *dai) 1171 { 1172 struct snd_soc_codec *codec = dai->codec; 1173 struct wm8993_priv *wm8993 = codec->private_data; 1174 int ret, i, best, best_val, cur_val; 1175 unsigned int clocking1, clocking3, aif1, aif4; 1176 1177 clocking1 = wm8993_read(codec, WM8993_CLOCKING_1); 1178 clocking1 &= ~WM8993_BCLK_DIV_MASK; 1179 1180 clocking3 = wm8993_read(codec, WM8993_CLOCKING_3); 1181 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK); 1182 1183 aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1); 1184 aif1 &= ~WM8993_AIF_WL_MASK; 1185 1186 aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4); 1187 aif4 &= ~WM8993_LRCLK_RATE_MASK; 1188 1189 /* What BCLK do we need? */ 1190 wm8993->fs = params_rate(params); 1191 wm8993->bclk = 2 * wm8993->fs; 1192 if (wm8993->tdm_slots) { 1193 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1194 wm8993->tdm_slots, wm8993->tdm_width); 1195 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots; 1196 } else { 1197 switch (params_format(params)) { 1198 case SNDRV_PCM_FORMAT_S16_LE: 1199 wm8993->bclk *= 16; 1200 break; 1201 case SNDRV_PCM_FORMAT_S20_3LE: 1202 wm8993->bclk *= 20; 1203 aif1 |= 0x8; 1204 break; 1205 case SNDRV_PCM_FORMAT_S24_LE: 1206 wm8993->bclk *= 24; 1207 aif1 |= 0x10; 1208 break; 1209 case SNDRV_PCM_FORMAT_S32_LE: 1210 wm8993->bclk *= 32; 1211 aif1 |= 0x18; 1212 break; 1213 default: 1214 return -EINVAL; 1215 } 1216 } 1217 1218 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); 1219 1220 ret = configure_clock(codec); 1221 if (ret != 0) 1222 return ret; 1223 1224 /* Select nearest CLK_SYS_RATE */ 1225 best = 0; 1226 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio) 1227 - wm8993->fs); 1228 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1229 cur_val = abs((wm8993->sysclk_rate / 1230 clk_sys_rates[i].ratio) - wm8993->fs);; 1231 if (cur_val < best_val) { 1232 best = i; 1233 best_val = cur_val; 1234 } 1235 } 1236 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1237 clk_sys_rates[best].ratio); 1238 clocking3 |= (clk_sys_rates[best].clk_sys_rate 1239 << WM8993_CLK_SYS_RATE_SHIFT); 1240 1241 /* SAMPLE_RATE */ 1242 best = 0; 1243 best_val = abs(wm8993->fs - sample_rates[0].rate); 1244 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1245 /* Closest match */ 1246 cur_val = abs(wm8993->fs - sample_rates[i].rate); 1247 if (cur_val < best_val) { 1248 best = i; 1249 best_val = cur_val; 1250 } 1251 } 1252 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1253 sample_rates[best].rate); 1254 clocking3 |= (sample_rates[best].sample_rate 1255 << WM8993_SAMPLE_RATE_SHIFT); 1256 1257 /* BCLK_DIV */ 1258 best = 0; 1259 best_val = INT_MAX; 1260 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1261 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div) 1262 - wm8993->bclk; 1263 if (cur_val < 0) /* Table is sorted */ 1264 break; 1265 if (cur_val < best_val) { 1266 best = i; 1267 best_val = cur_val; 1268 } 1269 } 1270 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div; 1271 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1272 bclk_divs[best].div, wm8993->bclk); 1273 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT; 1274 1275 /* LRCLK is a simple fraction of BCLK */ 1276 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs); 1277 aif4 |= wm8993->bclk / wm8993->fs; 1278 1279 wm8993_write(codec, WM8993_CLOCKING_1, clocking1); 1280 wm8993_write(codec, WM8993_CLOCKING_3, clocking3); 1281 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1282 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1283 1284 /* ReTune Mobile? */ 1285 if (wm8993->pdata.num_retune_configs) { 1286 u16 eq1 = wm8993_read(codec, WM8993_EQ1); 1287 struct wm8993_retune_mobile_setting *s; 1288 1289 best = 0; 1290 best_val = abs(wm8993->pdata.retune_configs[0].rate 1291 - wm8993->fs); 1292 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) { 1293 cur_val = abs(wm8993->pdata.retune_configs[i].rate 1294 - wm8993->fs); 1295 if (cur_val < best_val) { 1296 best_val = cur_val; 1297 best = i; 1298 } 1299 } 1300 s = &wm8993->pdata.retune_configs[best]; 1301 1302 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", 1303 s->name, s->rate); 1304 1305 /* Disable EQ while we reconfigure */ 1306 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0); 1307 1308 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1309 wm8993_write(codec, WM8993_EQ1 + i, s->config[i]); 1310 1311 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1); 1312 } 1313 1314 return 0; 1315 } 1316 1317 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1318 { 1319 struct snd_soc_codec *codec = codec_dai->codec; 1320 unsigned int reg; 1321 1322 reg = wm8993_read(codec, WM8993_DAC_CTRL); 1323 1324 if (mute) 1325 reg |= WM8993_DAC_MUTE; 1326 else 1327 reg &= ~WM8993_DAC_MUTE; 1328 1329 wm8993_write(codec, WM8993_DAC_CTRL, reg); 1330 1331 return 0; 1332 } 1333 1334 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1335 unsigned int rx_mask, int slots, int slot_width) 1336 { 1337 struct snd_soc_codec *codec = dai->codec; 1338 struct wm8993_priv *wm8993 = codec->private_data; 1339 int aif1 = 0; 1340 int aif2 = 0; 1341 1342 /* Don't need to validate anything if we're turning off TDM */ 1343 if (slots == 0) { 1344 wm8993->tdm_slots = 0; 1345 goto out; 1346 } 1347 1348 /* Note that we allow configurations we can't handle ourselves - 1349 * for example, we can generate clocks for slots 2 and up even if 1350 * we can't use those slots ourselves. 1351 */ 1352 aif1 |= WM8993_AIFADC_TDM; 1353 aif2 |= WM8993_AIFDAC_TDM; 1354 1355 switch (rx_mask) { 1356 case 3: 1357 break; 1358 case 0xc: 1359 aif1 |= WM8993_AIFADC_TDM_CHAN; 1360 break; 1361 default: 1362 return -EINVAL; 1363 } 1364 1365 1366 switch (tx_mask) { 1367 case 3: 1368 break; 1369 case 0xc: 1370 aif2 |= WM8993_AIFDAC_TDM_CHAN; 1371 break; 1372 default: 1373 return -EINVAL; 1374 } 1375 1376 out: 1377 wm8993->tdm_width = slot_width; 1378 wm8993->tdm_slots = slots / 2; 1379 1380 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1, 1381 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1); 1382 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2, 1383 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2); 1384 1385 return 0; 1386 } 1387 1388 static struct snd_soc_dai_ops wm8993_ops = { 1389 .set_sysclk = wm8993_set_sysclk, 1390 .set_fmt = wm8993_set_dai_fmt, 1391 .hw_params = wm8993_hw_params, 1392 .digital_mute = wm8993_digital_mute, 1393 .set_pll = wm8993_set_fll, 1394 .set_tdm_slot = wm8993_set_tdm_slot, 1395 }; 1396 1397 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000 1398 1399 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1400 SNDRV_PCM_FMTBIT_S20_3LE |\ 1401 SNDRV_PCM_FMTBIT_S24_LE |\ 1402 SNDRV_PCM_FMTBIT_S32_LE) 1403 1404 struct snd_soc_dai wm8993_dai = { 1405 .name = "WM8993", 1406 .playback = { 1407 .stream_name = "Playback", 1408 .channels_min = 1, 1409 .channels_max = 2, 1410 .rates = WM8993_RATES, 1411 .formats = WM8993_FORMATS, 1412 }, 1413 .capture = { 1414 .stream_name = "Capture", 1415 .channels_min = 1, 1416 .channels_max = 2, 1417 .rates = WM8993_RATES, 1418 .formats = WM8993_FORMATS, 1419 }, 1420 .ops = &wm8993_ops, 1421 .symmetric_rates = 1, 1422 }; 1423 EXPORT_SYMBOL_GPL(wm8993_dai); 1424 1425 static struct snd_soc_codec *wm8993_codec; 1426 1427 static int wm8993_probe(struct platform_device *pdev) 1428 { 1429 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1430 struct snd_soc_codec *codec; 1431 struct wm8993_priv *wm8993; 1432 int ret = 0; 1433 1434 if (!wm8993_codec) { 1435 dev_err(&pdev->dev, "I2C device not yet probed\n"); 1436 goto err; 1437 } 1438 1439 socdev->card->codec = wm8993_codec; 1440 codec = wm8993_codec; 1441 wm8993 = codec->private_data; 1442 1443 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1444 if (ret < 0) { 1445 dev_err(codec->dev, "failed to create pcms\n"); 1446 goto err; 1447 } 1448 1449 snd_soc_add_controls(codec, wm8993_snd_controls, 1450 ARRAY_SIZE(wm8993_snd_controls)); 1451 if (wm8993->pdata.num_retune_configs != 0) { 1452 dev_dbg(codec->dev, "Using ReTune Mobile\n"); 1453 } else { 1454 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n"); 1455 snd_soc_add_controls(codec, wm8993_eq_controls, 1456 ARRAY_SIZE(wm8993_eq_controls)); 1457 } 1458 1459 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets, 1460 ARRAY_SIZE(wm8993_dapm_widgets)); 1461 wm_hubs_add_analogue_controls(codec); 1462 1463 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes)); 1464 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, 1465 wm8993->pdata.lineout2_diff); 1466 1467 return ret; 1468 1469 err: 1470 return ret; 1471 } 1472 1473 static int wm8993_remove(struct platform_device *pdev) 1474 { 1475 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1476 1477 snd_soc_free_pcms(socdev); 1478 snd_soc_dapm_free(socdev); 1479 1480 return 0; 1481 } 1482 1483 struct snd_soc_codec_device soc_codec_dev_wm8993 = { 1484 .probe = wm8993_probe, 1485 .remove = wm8993_remove, 1486 }; 1487 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993); 1488 1489 static int wm8993_i2c_probe(struct i2c_client *i2c, 1490 const struct i2c_device_id *id) 1491 { 1492 struct wm8993_priv *wm8993; 1493 struct snd_soc_codec *codec; 1494 unsigned int val; 1495 int ret; 1496 1497 if (wm8993_codec) { 1498 dev_err(&i2c->dev, "A WM8993 is already registered\n"); 1499 return -EINVAL; 1500 } 1501 1502 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL); 1503 if (wm8993 == NULL) 1504 return -ENOMEM; 1505 1506 codec = &wm8993->codec; 1507 if (i2c->dev.platform_data) 1508 memcpy(&wm8993->pdata, i2c->dev.platform_data, 1509 sizeof(wm8993->pdata)); 1510 1511 mutex_init(&codec->mutex); 1512 INIT_LIST_HEAD(&codec->dapm_widgets); 1513 INIT_LIST_HEAD(&codec->dapm_paths); 1514 1515 codec->name = "WM8993"; 1516 codec->read = wm8993_read; 1517 codec->write = wm8993_write; 1518 codec->hw_write = (hw_write_t)i2c_master_send; 1519 codec->reg_cache = wm8993->reg_cache; 1520 codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache); 1521 codec->bias_level = SND_SOC_BIAS_OFF; 1522 codec->set_bias_level = wm8993_set_bias_level; 1523 codec->dai = &wm8993_dai; 1524 codec->num_dai = 1; 1525 codec->private_data = wm8993; 1526 1527 memcpy(wm8993->reg_cache, wm8993_reg_defaults, 1528 sizeof(wm8993->reg_cache)); 1529 1530 i2c_set_clientdata(i2c, wm8993); 1531 codec->control_data = i2c; 1532 wm8993_codec = codec; 1533 1534 codec->dev = &i2c->dev; 1535 1536 val = wm8993_read_hw(codec, WM8993_SOFTWARE_RESET); 1537 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) { 1538 dev_err(codec->dev, "Invalid ID register value %x\n", val); 1539 ret = -EINVAL; 1540 goto err; 1541 } 1542 1543 ret = wm8993_write(codec, WM8993_SOFTWARE_RESET, 0xffff); 1544 if (ret != 0) 1545 goto err; 1546 1547 /* By default we're using the output mixers */ 1548 wm8993->class_w_users = 2; 1549 1550 /* Latch volume update bits and default ZC on */ 1551 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1552 WM8993_DAC_VU, WM8993_DAC_VU); 1553 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1554 WM8993_ADC_VU, WM8993_ADC_VU); 1555 1556 /* Manualy manage the HPOUT sequencing for independent stereo 1557 * control. */ 1558 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0, 1559 WM8993_HPOUT1_AUTO_PU, 0); 1560 1561 /* Use automatic clock configuration */ 1562 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0); 1563 1564 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff, 1565 wm8993->pdata.lineout2_diff, 1566 wm8993->pdata.lineout1fb, 1567 wm8993->pdata.lineout2fb, 1568 wm8993->pdata.jd_scthr, 1569 wm8993->pdata.jd_thr, 1570 wm8993->pdata.micbias1_lvl, 1571 wm8993->pdata.micbias2_lvl); 1572 1573 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1574 if (ret != 0) 1575 goto err; 1576 1577 wm8993_dai.dev = codec->dev; 1578 1579 ret = snd_soc_register_dai(&wm8993_dai); 1580 if (ret != 0) 1581 goto err_bias; 1582 1583 ret = snd_soc_register_codec(codec); 1584 1585 return 0; 1586 1587 err_bias: 1588 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); 1589 err: 1590 wm8993_codec = NULL; 1591 kfree(wm8993); 1592 return ret; 1593 } 1594 1595 static int wm8993_i2c_remove(struct i2c_client *client) 1596 { 1597 struct wm8993_priv *wm8993 = i2c_get_clientdata(client); 1598 1599 snd_soc_unregister_codec(&wm8993->codec); 1600 snd_soc_unregister_dai(&wm8993_dai); 1601 1602 wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF); 1603 kfree(wm8993); 1604 1605 return 0; 1606 } 1607 1608 static const struct i2c_device_id wm8993_i2c_id[] = { 1609 { "wm8993", 0 }, 1610 { } 1611 }; 1612 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id); 1613 1614 static struct i2c_driver wm8993_i2c_driver = { 1615 .driver = { 1616 .name = "WM8993", 1617 .owner = THIS_MODULE, 1618 }, 1619 .probe = wm8993_i2c_probe, 1620 .remove = wm8993_i2c_remove, 1621 .id_table = wm8993_i2c_id, 1622 }; 1623 1624 1625 static int __init wm8993_modinit(void) 1626 { 1627 int ret; 1628 1629 ret = i2c_add_driver(&wm8993_i2c_driver); 1630 if (ret != 0) 1631 pr_err("WM8993: Unable to register I2C driver: %d\n", ret); 1632 1633 return ret; 1634 } 1635 module_init(wm8993_modinit); 1636 1637 static void __exit wm8993_exit(void) 1638 { 1639 i2c_del_driver(&wm8993_i2c_driver); 1640 } 1641 module_exit(wm8993_exit); 1642 1643 1644 MODULE_DESCRIPTION("ASoC WM8993 driver"); 1645 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1646 MODULE_LICENSE("GPL"); 1647