1 /* 2 * wm8993.c -- WM8993 ALSA SoC audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/tlv.h> 27 #include <sound/soc.h> 28 #include <sound/initval.h> 29 #include <sound/wm8993.h> 30 31 #include "wm8993.h" 32 #include "wm_hubs.h" 33 34 #define WM8993_NUM_SUPPLIES 6 35 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = { 36 "DCVDD", 37 "DBVDD", 38 "AVDD1", 39 "AVDD2", 40 "CPVDD", 41 "SPKVDD", 42 }; 43 44 static const struct reg_default wm8993_reg_defaults[] = { 45 { 1, 0x0000 }, /* R1 - Power Management (1) */ 46 { 2, 0x6000 }, /* R2 - Power Management (2) */ 47 { 3, 0x0000 }, /* R3 - Power Management (3) */ 48 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 49 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 50 { 6, 0x01C8 }, /* R6 - Clocking 1 */ 51 { 7, 0x0000 }, /* R7 - Clocking 2 */ 52 { 8, 0x0000 }, /* R8 - Audio Interface (3) */ 53 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 54 { 10, 0x0004 }, /* R10 - DAC CTRL */ 55 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 56 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 57 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 58 { 14, 0x0300 }, /* R14 - ADC CTRL */ 59 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 60 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 61 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 62 { 19, 0x0010 }, /* R19 - GPIO1 */ 63 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */ 64 { 21, 0x0000 }, /* R21 - Inputs Clamp */ 65 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 66 { 23, 0x0800 }, /* R23 - GPIO_POL */ 67 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 68 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 69 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 70 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 71 { 28, 0x006D }, /* R28 - Left Output Volume */ 72 { 29, 0x006D }, /* R29 - Right Output Volume */ 73 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 74 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */ 75 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 76 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 77 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */ 78 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */ 79 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */ 80 { 37, 0x0100 }, /* R37 - SPKOUT Boost */ 81 { 38, 0x0079 }, /* R38 - Speaker Volume Left */ 82 { 39, 0x0079 }, /* R39 - Speaker Volume Right */ 83 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 84 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 85 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 86 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 87 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 88 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 89 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 90 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 91 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 92 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 93 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 94 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */ 95 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 96 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 97 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 98 { 55, 0x0000 }, /* R55 - Additional Control */ 99 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 100 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 101 { 58, 0x0000 }, /* R58 - MICBIAS */ 102 { 60, 0x0000 }, /* R60 - FLL Control 1 */ 103 { 61, 0x0000 }, /* R61 - FLL Control 2 */ 104 { 62, 0x0000 }, /* R62 - FLL Control 3 */ 105 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */ 106 { 64, 0x0002 }, /* R64 - FLL Control 5 */ 107 { 65, 0x2287 }, /* R65 - Clocking 3 */ 108 { 66, 0x025F }, /* R66 - Clocking 4 */ 109 { 67, 0x0000 }, /* R67 - MW Slave Control */ 110 { 69, 0x0002 }, /* R69 - Bus Control 1 */ 111 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */ 112 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */ 113 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */ 114 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */ 115 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */ 116 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */ 117 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */ 118 { 81, 0x0000 }, /* R81 - Class W 0 */ 119 { 85, 0x054A }, /* R85 - DC Servo 1 */ 120 { 87, 0x0000 }, /* R87 - DC Servo 3 */ 121 { 96, 0x0100 }, /* R96 - Analogue HP 0 */ 122 { 98, 0x0000 }, /* R98 - EQ1 */ 123 { 99, 0x000C }, /* R99 - EQ2 */ 124 { 100, 0x000C }, /* R100 - EQ3 */ 125 { 101, 0x000C }, /* R101 - EQ4 */ 126 { 102, 0x000C }, /* R102 - EQ5 */ 127 { 103, 0x000C }, /* R103 - EQ6 */ 128 { 104, 0x0FCA }, /* R104 - EQ7 */ 129 { 105, 0x0400 }, /* R105 - EQ8 */ 130 { 106, 0x00D8 }, /* R106 - EQ9 */ 131 { 107, 0x1EB5 }, /* R107 - EQ10 */ 132 { 108, 0xF145 }, /* R108 - EQ11 */ 133 { 109, 0x0B75 }, /* R109 - EQ12 */ 134 { 110, 0x01C5 }, /* R110 - EQ13 */ 135 { 111, 0x1C58 }, /* R111 - EQ14 */ 136 { 112, 0xF373 }, /* R112 - EQ15 */ 137 { 113, 0x0A54 }, /* R113 - EQ16 */ 138 { 114, 0x0558 }, /* R114 - EQ17 */ 139 { 115, 0x168E }, /* R115 - EQ18 */ 140 { 116, 0xF829 }, /* R116 - EQ19 */ 141 { 117, 0x07AD }, /* R117 - EQ20 */ 142 { 118, 0x1103 }, /* R118 - EQ21 */ 143 { 119, 0x0564 }, /* R119 - EQ22 */ 144 { 120, 0x0559 }, /* R120 - EQ23 */ 145 { 121, 0x4000 }, /* R121 - EQ24 */ 146 { 122, 0x0000 }, /* R122 - Digital Pulls */ 147 { 123, 0x0F08 }, /* R123 - DRC Control 1 */ 148 { 124, 0x0000 }, /* R124 - DRC Control 2 */ 149 { 125, 0x0080 }, /* R125 - DRC Control 3 */ 150 { 126, 0x0000 }, /* R126 - DRC Control 4 */ 151 }; 152 153 static struct { 154 int ratio; 155 int clk_sys_rate; 156 } clk_sys_rates[] = { 157 { 64, 0 }, 158 { 128, 1 }, 159 { 192, 2 }, 160 { 256, 3 }, 161 { 384, 4 }, 162 { 512, 5 }, 163 { 768, 6 }, 164 { 1024, 7 }, 165 { 1408, 8 }, 166 { 1536, 9 }, 167 }; 168 169 static struct { 170 int rate; 171 int sample_rate; 172 } sample_rates[] = { 173 { 8000, 0 }, 174 { 11025, 1 }, 175 { 12000, 1 }, 176 { 16000, 2 }, 177 { 22050, 3 }, 178 { 24000, 3 }, 179 { 32000, 4 }, 180 { 44100, 5 }, 181 { 48000, 5 }, 182 }; 183 184 static struct { 185 int div; /* *10 due to .5s */ 186 int bclk_div; 187 } bclk_divs[] = { 188 { 10, 0 }, 189 { 15, 1 }, 190 { 20, 2 }, 191 { 30, 3 }, 192 { 40, 4 }, 193 { 55, 5 }, 194 { 60, 6 }, 195 { 80, 7 }, 196 { 110, 8 }, 197 { 120, 9 }, 198 { 160, 10 }, 199 { 220, 11 }, 200 { 240, 12 }, 201 { 320, 13 }, 202 { 440, 14 }, 203 { 480, 15 }, 204 }; 205 206 struct wm8993_priv { 207 struct wm_hubs_data hubs_data; 208 struct device *dev; 209 struct regmap *regmap; 210 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; 211 struct wm8993_platform_data pdata; 212 struct completion fll_lock; 213 int master; 214 int sysclk_source; 215 int tdm_slots; 216 int tdm_width; 217 unsigned int mclk_rate; 218 unsigned int sysclk_rate; 219 unsigned int fs; 220 unsigned int bclk; 221 unsigned int fll_fref; 222 unsigned int fll_fout; 223 int fll_src; 224 }; 225 226 static bool wm8993_volatile(struct device *dev, unsigned int reg) 227 { 228 switch (reg) { 229 case WM8993_SOFTWARE_RESET: 230 case WM8993_GPIO_CTRL_1: 231 case WM8993_DC_SERVO_0: 232 case WM8993_DC_SERVO_READBACK_0: 233 case WM8993_DC_SERVO_READBACK_1: 234 case WM8993_DC_SERVO_READBACK_2: 235 return true; 236 default: 237 return false; 238 } 239 } 240 241 static bool wm8993_readable(struct device *dev, unsigned int reg) 242 { 243 switch (reg) { 244 case WM8993_SOFTWARE_RESET: 245 case WM8993_POWER_MANAGEMENT_1: 246 case WM8993_POWER_MANAGEMENT_2: 247 case WM8993_POWER_MANAGEMENT_3: 248 case WM8993_AUDIO_INTERFACE_1: 249 case WM8993_AUDIO_INTERFACE_2: 250 case WM8993_CLOCKING_1: 251 case WM8993_CLOCKING_2: 252 case WM8993_AUDIO_INTERFACE_3: 253 case WM8993_AUDIO_INTERFACE_4: 254 case WM8993_DAC_CTRL: 255 case WM8993_LEFT_DAC_DIGITAL_VOLUME: 256 case WM8993_RIGHT_DAC_DIGITAL_VOLUME: 257 case WM8993_DIGITAL_SIDE_TONE: 258 case WM8993_ADC_CTRL: 259 case WM8993_LEFT_ADC_DIGITAL_VOLUME: 260 case WM8993_RIGHT_ADC_DIGITAL_VOLUME: 261 case WM8993_GPIO_CTRL_1: 262 case WM8993_GPIO1: 263 case WM8993_IRQ_DEBOUNCE: 264 case WM8993_GPIOCTRL_2: 265 case WM8993_GPIO_POL: 266 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME: 267 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME: 268 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME: 269 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME: 270 case WM8993_LEFT_OUTPUT_VOLUME: 271 case WM8993_RIGHT_OUTPUT_VOLUME: 272 case WM8993_LINE_OUTPUTS_VOLUME: 273 case WM8993_HPOUT2_VOLUME: 274 case WM8993_LEFT_OPGA_VOLUME: 275 case WM8993_RIGHT_OPGA_VOLUME: 276 case WM8993_SPKMIXL_ATTENUATION: 277 case WM8993_SPKMIXR_ATTENUATION: 278 case WM8993_SPKOUT_MIXERS: 279 case WM8993_SPKOUT_BOOST: 280 case WM8993_SPEAKER_VOLUME_LEFT: 281 case WM8993_SPEAKER_VOLUME_RIGHT: 282 case WM8993_INPUT_MIXER2: 283 case WM8993_INPUT_MIXER3: 284 case WM8993_INPUT_MIXER4: 285 case WM8993_INPUT_MIXER5: 286 case WM8993_INPUT_MIXER6: 287 case WM8993_OUTPUT_MIXER1: 288 case WM8993_OUTPUT_MIXER2: 289 case WM8993_OUTPUT_MIXER3: 290 case WM8993_OUTPUT_MIXER4: 291 case WM8993_OUTPUT_MIXER5: 292 case WM8993_OUTPUT_MIXER6: 293 case WM8993_HPOUT2_MIXER: 294 case WM8993_LINE_MIXER1: 295 case WM8993_LINE_MIXER2: 296 case WM8993_SPEAKER_MIXER: 297 case WM8993_ADDITIONAL_CONTROL: 298 case WM8993_ANTIPOP1: 299 case WM8993_ANTIPOP2: 300 case WM8993_MICBIAS: 301 case WM8993_FLL_CONTROL_1: 302 case WM8993_FLL_CONTROL_2: 303 case WM8993_FLL_CONTROL_3: 304 case WM8993_FLL_CONTROL_4: 305 case WM8993_FLL_CONTROL_5: 306 case WM8993_CLOCKING_3: 307 case WM8993_CLOCKING_4: 308 case WM8993_MW_SLAVE_CONTROL: 309 case WM8993_BUS_CONTROL_1: 310 case WM8993_WRITE_SEQUENCER_0: 311 case WM8993_WRITE_SEQUENCER_1: 312 case WM8993_WRITE_SEQUENCER_2: 313 case WM8993_WRITE_SEQUENCER_3: 314 case WM8993_WRITE_SEQUENCER_4: 315 case WM8993_WRITE_SEQUENCER_5: 316 case WM8993_CHARGE_PUMP_1: 317 case WM8993_CLASS_W_0: 318 case WM8993_DC_SERVO_0: 319 case WM8993_DC_SERVO_1: 320 case WM8993_DC_SERVO_3: 321 case WM8993_DC_SERVO_READBACK_0: 322 case WM8993_DC_SERVO_READBACK_1: 323 case WM8993_DC_SERVO_READBACK_2: 324 case WM8993_ANALOGUE_HP_0: 325 case WM8993_EQ1: 326 case WM8993_EQ2: 327 case WM8993_EQ3: 328 case WM8993_EQ4: 329 case WM8993_EQ5: 330 case WM8993_EQ6: 331 case WM8993_EQ7: 332 case WM8993_EQ8: 333 case WM8993_EQ9: 334 case WM8993_EQ10: 335 case WM8993_EQ11: 336 case WM8993_EQ12: 337 case WM8993_EQ13: 338 case WM8993_EQ14: 339 case WM8993_EQ15: 340 case WM8993_EQ16: 341 case WM8993_EQ17: 342 case WM8993_EQ18: 343 case WM8993_EQ19: 344 case WM8993_EQ20: 345 case WM8993_EQ21: 346 case WM8993_EQ22: 347 case WM8993_EQ23: 348 case WM8993_EQ24: 349 case WM8993_DIGITAL_PULLS: 350 case WM8993_DRC_CONTROL_1: 351 case WM8993_DRC_CONTROL_2: 352 case WM8993_DRC_CONTROL_3: 353 case WM8993_DRC_CONTROL_4: 354 return true; 355 default: 356 return false; 357 } 358 } 359 360 struct _fll_div { 361 u16 fll_fratio; 362 u16 fll_outdiv; 363 u16 fll_clk_ref_div; 364 u16 n; 365 u16 k; 366 }; 367 368 /* The size in bits of the FLL divide multiplied by 10 369 * to allow rounding later */ 370 #define FIXED_FLL_SIZE ((1 << 16) * 10) 371 372 static struct { 373 unsigned int min; 374 unsigned int max; 375 u16 fll_fratio; 376 int ratio; 377 } fll_fratios[] = { 378 { 0, 64000, 4, 16 }, 379 { 64000, 128000, 3, 8 }, 380 { 128000, 256000, 2, 4 }, 381 { 256000, 1000000, 1, 2 }, 382 { 1000000, 13500000, 0, 1 }, 383 }; 384 385 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 386 unsigned int Fout) 387 { 388 u64 Kpart; 389 unsigned int K, Ndiv, Nmod, target; 390 unsigned int div; 391 int i; 392 393 /* Fref must be <=13.5MHz */ 394 div = 1; 395 fll_div->fll_clk_ref_div = 0; 396 while ((Fref / div) > 13500000) { 397 div *= 2; 398 fll_div->fll_clk_ref_div++; 399 400 if (div > 8) { 401 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 402 Fref); 403 return -EINVAL; 404 } 405 } 406 407 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 408 409 /* Apply the division for our remaining calculations */ 410 Fref /= div; 411 412 /* Fvco should be 90-100MHz; don't check the upper bound */ 413 div = 0; 414 target = Fout * 2; 415 while (target < 90000000) { 416 div++; 417 target *= 2; 418 if (div > 7) { 419 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 420 Fout); 421 return -EINVAL; 422 } 423 } 424 fll_div->fll_outdiv = div; 425 426 pr_debug("Fvco=%dHz\n", target); 427 428 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 429 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 430 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 431 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 432 target /= fll_fratios[i].ratio; 433 break; 434 } 435 } 436 if (i == ARRAY_SIZE(fll_fratios)) { 437 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 438 return -EINVAL; 439 } 440 441 /* Now, calculate N.K */ 442 Ndiv = target / Fref; 443 444 fll_div->n = Ndiv; 445 Nmod = target % Fref; 446 pr_debug("Nmod=%d\n", Nmod); 447 448 /* Calculate fractional part - scale up so we can round. */ 449 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 450 451 do_div(Kpart, Fref); 452 453 K = Kpart & 0xFFFFFFFF; 454 455 if ((K % 10) >= 5) 456 K += 5; 457 458 /* Move down to proper range now rounding is done */ 459 fll_div->k = K / 10; 460 461 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 462 fll_div->n, fll_div->k, 463 fll_div->fll_fratio, fll_div->fll_outdiv, 464 fll_div->fll_clk_ref_div); 465 466 return 0; 467 } 468 469 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 470 unsigned int Fref, unsigned int Fout) 471 { 472 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 473 struct i2c_client *i2c = to_i2c_client(codec->dev); 474 u16 reg1, reg4, reg5; 475 struct _fll_div fll_div; 476 unsigned int timeout; 477 int ret; 478 479 /* Any change? */ 480 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout) 481 return 0; 482 483 /* Disable the FLL */ 484 if (Fout == 0) { 485 dev_dbg(codec->dev, "FLL disabled\n"); 486 wm8993->fll_fref = 0; 487 wm8993->fll_fout = 0; 488 489 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 490 reg1 &= ~WM8993_FLL_ENA; 491 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 492 493 return 0; 494 } 495 496 ret = fll_factors(&fll_div, Fref, Fout); 497 if (ret != 0) 498 return ret; 499 500 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5); 501 reg5 &= ~WM8993_FLL_CLK_SRC_MASK; 502 503 switch (fll_id) { 504 case WM8993_FLL_MCLK: 505 break; 506 507 case WM8993_FLL_LRCLK: 508 reg5 |= 1; 509 break; 510 511 case WM8993_FLL_BCLK: 512 reg5 |= 2; 513 break; 514 515 default: 516 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 517 return -EINVAL; 518 } 519 520 /* Any FLL configuration change requires that the FLL be 521 * disabled first. */ 522 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 523 reg1 &= ~WM8993_FLL_ENA; 524 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 525 526 /* Apply the configuration */ 527 if (fll_div.k) 528 reg1 |= WM8993_FLL_FRAC_MASK; 529 else 530 reg1 &= ~WM8993_FLL_FRAC_MASK; 531 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 532 533 snd_soc_write(codec, WM8993_FLL_CONTROL_2, 534 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) | 535 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT)); 536 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k); 537 538 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4); 539 reg4 &= ~WM8993_FLL_N_MASK; 540 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT; 541 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4); 542 543 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; 544 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; 545 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5); 546 547 /* If we've got an interrupt wired up make sure we get it */ 548 if (i2c->irq) 549 timeout = msecs_to_jiffies(20); 550 else if (Fref < 1000000) 551 timeout = msecs_to_jiffies(3); 552 else 553 timeout = msecs_to_jiffies(1); 554 555 try_wait_for_completion(&wm8993->fll_lock); 556 557 /* Enable the FLL */ 558 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); 559 560 timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout); 561 if (i2c->irq && !timeout) 562 dev_warn(codec->dev, "Timed out waiting for FLL\n"); 563 564 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 565 566 wm8993->fll_fref = Fref; 567 wm8993->fll_fout = Fout; 568 wm8993->fll_src = source; 569 570 return 0; 571 } 572 573 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 574 unsigned int Fref, unsigned int Fout) 575 { 576 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout); 577 } 578 579 static int configure_clock(struct snd_soc_codec *codec) 580 { 581 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 582 unsigned int reg; 583 584 /* This should be done on init() for bypass paths */ 585 switch (wm8993->sysclk_source) { 586 case WM8993_SYSCLK_MCLK: 587 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); 588 589 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 590 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); 591 if (wm8993->mclk_rate > 13500000) { 592 reg |= WM8993_MCLK_DIV; 593 wm8993->sysclk_rate = wm8993->mclk_rate / 2; 594 } else { 595 reg &= ~WM8993_MCLK_DIV; 596 wm8993->sysclk_rate = wm8993->mclk_rate; 597 } 598 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 599 break; 600 601 case WM8993_SYSCLK_FLL: 602 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 603 wm8993->fll_fout); 604 605 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 606 reg |= WM8993_SYSCLK_SRC; 607 if (wm8993->fll_fout > 13500000) { 608 reg |= WM8993_MCLK_DIV; 609 wm8993->sysclk_rate = wm8993->fll_fout / 2; 610 } else { 611 reg &= ~WM8993_MCLK_DIV; 612 wm8993->sysclk_rate = wm8993->fll_fout; 613 } 614 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 615 break; 616 617 default: 618 dev_err(codec->dev, "System clock not configured\n"); 619 return -EINVAL; 620 } 621 622 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate); 623 624 return 0; 625 } 626 627 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 628 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0); 629 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0); 630 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); 631 static const DECLARE_TLV_DB_RANGE(drc_max_tlv, 632 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0), 633 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0) 634 ); 635 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); 636 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0); 637 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 638 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 639 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 640 641 static const char *dac_deemph_text[] = { 642 "None", 643 "32kHz", 644 "44.1kHz", 645 "48kHz", 646 }; 647 648 static SOC_ENUM_SINGLE_DECL(dac_deemph, 649 WM8993_DAC_CTRL, 4, dac_deemph_text); 650 651 static const char *adc_hpf_text[] = { 652 "Hi-Fi", 653 "Voice 1", 654 "Voice 2", 655 "Voice 3", 656 }; 657 658 static SOC_ENUM_SINGLE_DECL(adc_hpf, 659 WM8993_ADC_CTRL, 5, adc_hpf_text); 660 661 static const char *drc_path_text[] = { 662 "ADC", 663 "DAC" 664 }; 665 666 static SOC_ENUM_SINGLE_DECL(drc_path, 667 WM8993_DRC_CONTROL_1, 14, drc_path_text); 668 669 static const char *drc_r0_text[] = { 670 "1", 671 "1/2", 672 "1/4", 673 "1/8", 674 "1/16", 675 "0", 676 }; 677 678 static SOC_ENUM_SINGLE_DECL(drc_r0, 679 WM8993_DRC_CONTROL_3, 8, drc_r0_text); 680 681 static const char *drc_r1_text[] = { 682 "1", 683 "1/2", 684 "1/4", 685 "1/8", 686 "0", 687 }; 688 689 static SOC_ENUM_SINGLE_DECL(drc_r1, 690 WM8993_DRC_CONTROL_4, 13, drc_r1_text); 691 692 static const char *drc_attack_text[] = { 693 "Reserved", 694 "181us", 695 "363us", 696 "726us", 697 "1.45ms", 698 "2.9ms", 699 "5.8ms", 700 "11.6ms", 701 "23.2ms", 702 "46.4ms", 703 "92.8ms", 704 "185.6ms", 705 }; 706 707 static SOC_ENUM_SINGLE_DECL(drc_attack, 708 WM8993_DRC_CONTROL_2, 12, drc_attack_text); 709 710 static const char *drc_decay_text[] = { 711 "186ms", 712 "372ms", 713 "743ms", 714 "1.49s", 715 "2.97ms", 716 "5.94ms", 717 "11.89ms", 718 "23.78ms", 719 "47.56ms", 720 }; 721 722 static SOC_ENUM_SINGLE_DECL(drc_decay, 723 WM8993_DRC_CONTROL_2, 8, drc_decay_text); 724 725 static const char *drc_ff_text[] = { 726 "5 samples", 727 "9 samples", 728 }; 729 730 static SOC_ENUM_SINGLE_DECL(drc_ff, 731 WM8993_DRC_CONTROL_3, 7, drc_ff_text); 732 733 static const char *drc_qr_rate_text[] = { 734 "0.725ms", 735 "1.45ms", 736 "5.8ms", 737 }; 738 739 static SOC_ENUM_SINGLE_DECL(drc_qr_rate, 740 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text); 741 742 static const char *drc_smooth_text[] = { 743 "Low", 744 "Medium", 745 "High", 746 }; 747 748 static SOC_ENUM_SINGLE_DECL(drc_smooth, 749 WM8993_DRC_CONTROL_1, 4, drc_smooth_text); 750 751 static const struct snd_kcontrol_new wm8993_snd_controls[] = { 752 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE, 753 5, 9, 12, 0, sidetone_tlv), 754 755 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0), 756 SOC_ENUM("DRC Path", drc_path), 757 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2, 758 2, 60, 1, drc_comp_threash), 759 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3, 760 11, 30, 1, drc_comp_amp), 761 SOC_ENUM("DRC R0", drc_r0), 762 SOC_ENUM("DRC R1", drc_r1), 763 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1, 764 drc_min_tlv), 765 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0, 766 drc_max_tlv), 767 SOC_ENUM("DRC Attack Rate", drc_attack), 768 SOC_ENUM("DRC Decay Rate", drc_decay), 769 SOC_ENUM("DRC FF Delay", drc_ff), 770 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0), 771 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0), 772 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0, 773 drc_qr_tlv), 774 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate), 775 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0), 776 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0), 777 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth), 778 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0, 779 drc_startup_tlv), 780 781 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0), 782 783 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME, 784 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 785 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0), 786 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 787 788 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME, 789 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 790 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0, 791 dac_boost_tlv), 792 SOC_ENUM("DAC Deemphasis", dac_deemph), 793 794 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION, 795 2, 1, 1, wm_hubs_spkmix_tlv), 796 797 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION, 798 2, 1, 1, wm_hubs_spkmix_tlv), 799 }; 800 801 static const struct snd_kcontrol_new wm8993_eq_controls[] = { 802 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv), 803 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv), 804 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv), 805 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv), 806 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv), 807 }; 808 809 static int clk_sys_event(struct snd_soc_dapm_widget *w, 810 struct snd_kcontrol *kcontrol, int event) 811 { 812 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 813 814 switch (event) { 815 case SND_SOC_DAPM_PRE_PMU: 816 return configure_clock(codec); 817 818 case SND_SOC_DAPM_POST_PMD: 819 break; 820 } 821 822 return 0; 823 } 824 825 static const struct snd_kcontrol_new left_speaker_mixer[] = { 826 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), 827 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), 828 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0), 829 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 830 }; 831 832 static const struct snd_kcontrol_new right_speaker_mixer[] = { 833 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 834 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0), 835 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0), 836 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0), 837 }; 838 839 static const char *aif_text[] = { 840 "Left", "Right" 841 }; 842 843 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, 844 WM8993_AUDIO_INTERFACE_1, 15, aif_text); 845 846 static const struct snd_kcontrol_new aifoutl_mux = 847 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 848 849 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, 850 WM8993_AUDIO_INTERFACE_1, 14, aif_text); 851 852 static const struct snd_kcontrol_new aifoutr_mux = 853 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 854 855 static SOC_ENUM_SINGLE_DECL(aifinl_enum, 856 WM8993_AUDIO_INTERFACE_2, 15, aif_text); 857 858 static const struct snd_kcontrol_new aifinl_mux = 859 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 860 861 static SOC_ENUM_SINGLE_DECL(aifinr_enum, 862 WM8993_AUDIO_INTERFACE_2, 14, aif_text); 863 864 static const struct snd_kcontrol_new aifinr_mux = 865 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 866 867 static const char *sidetone_text[] = { 868 "None", "Left", "Right" 869 }; 870 871 static SOC_ENUM_SINGLE_DECL(sidetonel_enum, 872 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text); 873 874 static const struct snd_kcontrol_new sidetonel_mux = 875 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum); 876 877 static SOC_ENUM_SINGLE_DECL(sidetoner_enum, 878 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text); 879 880 static const struct snd_kcontrol_new sidetoner_mux = 881 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum); 882 883 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = { 884 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event, 885 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 886 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0), 887 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0), 888 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0), 889 890 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0), 891 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0), 892 893 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 894 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 895 896 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 897 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 898 899 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 900 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 901 902 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 903 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 904 905 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux), 906 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux), 907 908 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), 909 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), 910 911 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 912 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 913 914 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, 915 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 916 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0, 917 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 918 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 919 }; 920 921 static const struct snd_soc_dapm_route routes[] = { 922 { "MICBIAS1", NULL, "VMID" }, 923 { "MICBIAS2", NULL, "VMID" }, 924 925 { "ADCL", NULL, "CLK_SYS" }, 926 { "ADCL", NULL, "CLK_DSP" }, 927 { "ADCR", NULL, "CLK_SYS" }, 928 { "ADCR", NULL, "CLK_DSP" }, 929 930 { "AIFOUTL Mux", "Left", "ADCL" }, 931 { "AIFOUTL Mux", "Right", "ADCR" }, 932 { "AIFOUTR Mux", "Left", "ADCL" }, 933 { "AIFOUTR Mux", "Right", "ADCR" }, 934 935 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 936 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 937 938 { "DACL Mux", "Left", "AIFINL" }, 939 { "DACL Mux", "Right", "AIFINR" }, 940 { "DACR Mux", "Left", "AIFINL" }, 941 { "DACR Mux", "Right", "AIFINR" }, 942 943 { "DACL Sidetone", "Left", "ADCL" }, 944 { "DACL Sidetone", "Right", "ADCR" }, 945 { "DACR Sidetone", "Left", "ADCL" }, 946 { "DACR Sidetone", "Right", "ADCR" }, 947 948 { "DACL", NULL, "CLK_SYS" }, 949 { "DACL", NULL, "CLK_DSP" }, 950 { "DACL", NULL, "DACL Mux" }, 951 { "DACL", NULL, "DACL Sidetone" }, 952 { "DACR", NULL, "CLK_SYS" }, 953 { "DACR", NULL, "CLK_DSP" }, 954 { "DACR", NULL, "DACR Mux" }, 955 { "DACR", NULL, "DACR Sidetone" }, 956 957 { "Left Output Mixer", "DAC Switch", "DACL" }, 958 959 { "Right Output Mixer", "DAC Switch", "DACR" }, 960 961 { "Left Output PGA", NULL, "CLK_SYS" }, 962 963 { "Right Output PGA", NULL, "CLK_SYS" }, 964 965 { "SPKL", "DAC Switch", "DACL" }, 966 { "SPKL", NULL, "CLK_SYS" }, 967 968 { "SPKR", "DAC Switch", "DACR" }, 969 { "SPKR", NULL, "CLK_SYS" }, 970 971 { "Left Headphone Mux", "DAC", "DACL" }, 972 { "Right Headphone Mux", "DAC", "DACR" }, 973 }; 974 975 static int wm8993_set_bias_level(struct snd_soc_codec *codec, 976 enum snd_soc_bias_level level) 977 { 978 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 979 int ret; 980 981 wm_hubs_set_bias_level(codec, level); 982 983 switch (level) { 984 case SND_SOC_BIAS_ON: 985 case SND_SOC_BIAS_PREPARE: 986 /* VMID=2*40k */ 987 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 988 WM8993_VMID_SEL_MASK, 0x2); 989 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 990 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); 991 break; 992 993 case SND_SOC_BIAS_STANDBY: 994 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 995 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 996 wm8993->supplies); 997 if (ret != 0) 998 return ret; 999 1000 regcache_cache_only(wm8993->regmap, false); 1001 regcache_sync(wm8993->regmap); 1002 1003 wm_hubs_vmid_ena(codec); 1004 1005 /* Bring up VMID with fast soft start */ 1006 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1007 WM8993_STARTUP_BIAS_ENA | 1008 WM8993_VMID_BUF_ENA | 1009 WM8993_VMID_RAMP_MASK | 1010 WM8993_BIAS_SRC, 1011 WM8993_STARTUP_BIAS_ENA | 1012 WM8993_VMID_BUF_ENA | 1013 WM8993_VMID_RAMP_MASK | 1014 WM8993_BIAS_SRC); 1015 1016 /* If either line output is single ended we 1017 * need the VMID buffer */ 1018 if (!wm8993->pdata.lineout1_diff || 1019 !wm8993->pdata.lineout2_diff) 1020 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1021 WM8993_LINEOUT_VMID_BUF_ENA, 1022 WM8993_LINEOUT_VMID_BUF_ENA); 1023 1024 /* VMID=2*40k */ 1025 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1026 WM8993_VMID_SEL_MASK | 1027 WM8993_BIAS_ENA, 1028 WM8993_BIAS_ENA | 0x2); 1029 msleep(32); 1030 1031 /* Switch to normal bias */ 1032 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1033 WM8993_BIAS_SRC | 1034 WM8993_STARTUP_BIAS_ENA, 0); 1035 } 1036 1037 /* VMID=2*240k */ 1038 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1039 WM8993_VMID_SEL_MASK, 0x4); 1040 1041 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 1042 WM8993_TSHUT_ENA, 0); 1043 break; 1044 1045 case SND_SOC_BIAS_OFF: 1046 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1047 WM8993_LINEOUT_VMID_BUF_ENA, 0); 1048 1049 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1050 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 1051 0); 1052 1053 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1054 WM8993_STARTUP_BIAS_ENA | 1055 WM8993_VMID_BUF_ENA | 1056 WM8993_VMID_RAMP_MASK | 1057 WM8993_BIAS_SRC, 0); 1058 1059 regcache_cache_only(wm8993->regmap, true); 1060 regcache_mark_dirty(wm8993->regmap); 1061 1062 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), 1063 wm8993->supplies); 1064 break; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai, 1071 int clk_id, unsigned int freq, int dir) 1072 { 1073 struct snd_soc_codec *codec = codec_dai->codec; 1074 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1075 1076 switch (clk_id) { 1077 case WM8993_SYSCLK_MCLK: 1078 wm8993->mclk_rate = freq; 1079 /* fall through */ 1080 case WM8993_SYSCLK_FLL: 1081 wm8993->sysclk_source = clk_id; 1082 break; 1083 1084 default: 1085 return -EINVAL; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai, 1092 unsigned int fmt) 1093 { 1094 struct snd_soc_codec *codec = dai->codec; 1095 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1096 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1097 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1098 1099 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV | 1100 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK); 1101 aif4 &= ~WM8993_LRCLK_DIR; 1102 1103 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1104 case SND_SOC_DAIFMT_CBS_CFS: 1105 wm8993->master = 0; 1106 break; 1107 case SND_SOC_DAIFMT_CBS_CFM: 1108 aif4 |= WM8993_LRCLK_DIR; 1109 wm8993->master = 1; 1110 break; 1111 case SND_SOC_DAIFMT_CBM_CFS: 1112 aif1 |= WM8993_BCLK_DIR; 1113 wm8993->master = 1; 1114 break; 1115 case SND_SOC_DAIFMT_CBM_CFM: 1116 aif1 |= WM8993_BCLK_DIR; 1117 aif4 |= WM8993_LRCLK_DIR; 1118 wm8993->master = 1; 1119 break; 1120 default: 1121 return -EINVAL; 1122 } 1123 1124 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1125 case SND_SOC_DAIFMT_DSP_B: 1126 aif1 |= WM8993_AIF_LRCLK_INV; 1127 /* fall through */ 1128 case SND_SOC_DAIFMT_DSP_A: 1129 aif1 |= 0x18; 1130 break; 1131 case SND_SOC_DAIFMT_I2S: 1132 aif1 |= 0x10; 1133 break; 1134 case SND_SOC_DAIFMT_RIGHT_J: 1135 break; 1136 case SND_SOC_DAIFMT_LEFT_J: 1137 aif1 |= 0x8; 1138 break; 1139 default: 1140 return -EINVAL; 1141 } 1142 1143 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1144 case SND_SOC_DAIFMT_DSP_A: 1145 case SND_SOC_DAIFMT_DSP_B: 1146 /* frame inversion not valid for DSP modes */ 1147 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1148 case SND_SOC_DAIFMT_NB_NF: 1149 break; 1150 case SND_SOC_DAIFMT_IB_NF: 1151 aif1 |= WM8993_AIF_BCLK_INV; 1152 break; 1153 default: 1154 return -EINVAL; 1155 } 1156 break; 1157 1158 case SND_SOC_DAIFMT_I2S: 1159 case SND_SOC_DAIFMT_RIGHT_J: 1160 case SND_SOC_DAIFMT_LEFT_J: 1161 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1162 case SND_SOC_DAIFMT_NB_NF: 1163 break; 1164 case SND_SOC_DAIFMT_IB_IF: 1165 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV; 1166 break; 1167 case SND_SOC_DAIFMT_IB_NF: 1168 aif1 |= WM8993_AIF_BCLK_INV; 1169 break; 1170 case SND_SOC_DAIFMT_NB_IF: 1171 aif1 |= WM8993_AIF_LRCLK_INV; 1172 break; 1173 default: 1174 return -EINVAL; 1175 } 1176 break; 1177 default: 1178 return -EINVAL; 1179 } 1180 1181 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1182 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1183 1184 return 0; 1185 } 1186 1187 static int wm8993_hw_params(struct snd_pcm_substream *substream, 1188 struct snd_pcm_hw_params *params, 1189 struct snd_soc_dai *dai) 1190 { 1191 struct snd_soc_codec *codec = dai->codec; 1192 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1193 int ret, i, best, best_val, cur_val; 1194 unsigned int clocking1, clocking3, aif1, aif4; 1195 1196 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1); 1197 clocking1 &= ~WM8993_BCLK_DIV_MASK; 1198 1199 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3); 1200 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK); 1201 1202 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1203 aif1 &= ~WM8993_AIF_WL_MASK; 1204 1205 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1206 aif4 &= ~WM8993_LRCLK_RATE_MASK; 1207 1208 /* What BCLK do we need? */ 1209 wm8993->fs = params_rate(params); 1210 wm8993->bclk = 2 * wm8993->fs; 1211 if (wm8993->tdm_slots) { 1212 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1213 wm8993->tdm_slots, wm8993->tdm_width); 1214 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots; 1215 } else { 1216 switch (params_width(params)) { 1217 case 16: 1218 wm8993->bclk *= 16; 1219 break; 1220 case 20: 1221 wm8993->bclk *= 20; 1222 aif1 |= 0x8; 1223 break; 1224 case 24: 1225 wm8993->bclk *= 24; 1226 aif1 |= 0x10; 1227 break; 1228 case 32: 1229 wm8993->bclk *= 32; 1230 aif1 |= 0x18; 1231 break; 1232 default: 1233 return -EINVAL; 1234 } 1235 } 1236 1237 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); 1238 1239 ret = configure_clock(codec); 1240 if (ret != 0) 1241 return ret; 1242 1243 /* Select nearest CLK_SYS_RATE */ 1244 best = 0; 1245 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio) 1246 - wm8993->fs); 1247 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1248 cur_val = abs((wm8993->sysclk_rate / 1249 clk_sys_rates[i].ratio) - wm8993->fs); 1250 if (cur_val < best_val) { 1251 best = i; 1252 best_val = cur_val; 1253 } 1254 } 1255 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1256 clk_sys_rates[best].ratio); 1257 clocking3 |= (clk_sys_rates[best].clk_sys_rate 1258 << WM8993_CLK_SYS_RATE_SHIFT); 1259 1260 /* SAMPLE_RATE */ 1261 best = 0; 1262 best_val = abs(wm8993->fs - sample_rates[0].rate); 1263 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1264 /* Closest match */ 1265 cur_val = abs(wm8993->fs - sample_rates[i].rate); 1266 if (cur_val < best_val) { 1267 best = i; 1268 best_val = cur_val; 1269 } 1270 } 1271 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1272 sample_rates[best].rate); 1273 clocking3 |= (sample_rates[best].sample_rate 1274 << WM8993_SAMPLE_RATE_SHIFT); 1275 1276 /* BCLK_DIV */ 1277 best = 0; 1278 best_val = INT_MAX; 1279 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1280 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div) 1281 - wm8993->bclk; 1282 if (cur_val < 0) /* Table is sorted */ 1283 break; 1284 if (cur_val < best_val) { 1285 best = i; 1286 best_val = cur_val; 1287 } 1288 } 1289 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div; 1290 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1291 bclk_divs[best].div, wm8993->bclk); 1292 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT; 1293 1294 /* LRCLK is a simple fraction of BCLK */ 1295 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs); 1296 aif4 |= wm8993->bclk / wm8993->fs; 1297 1298 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1); 1299 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3); 1300 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1301 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1302 1303 /* ReTune Mobile? */ 1304 if (wm8993->pdata.num_retune_configs) { 1305 u16 eq1 = snd_soc_read(codec, WM8993_EQ1); 1306 struct wm8993_retune_mobile_setting *s; 1307 1308 best = 0; 1309 best_val = abs(wm8993->pdata.retune_configs[0].rate 1310 - wm8993->fs); 1311 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) { 1312 cur_val = abs(wm8993->pdata.retune_configs[i].rate 1313 - wm8993->fs); 1314 if (cur_val < best_val) { 1315 best_val = cur_val; 1316 best = i; 1317 } 1318 } 1319 s = &wm8993->pdata.retune_configs[best]; 1320 1321 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", 1322 s->name, s->rate); 1323 1324 /* Disable EQ while we reconfigure */ 1325 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0); 1326 1327 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1328 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]); 1329 1330 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1337 { 1338 struct snd_soc_codec *codec = codec_dai->codec; 1339 unsigned int reg; 1340 1341 reg = snd_soc_read(codec, WM8993_DAC_CTRL); 1342 1343 if (mute) 1344 reg |= WM8993_DAC_MUTE; 1345 else 1346 reg &= ~WM8993_DAC_MUTE; 1347 1348 snd_soc_write(codec, WM8993_DAC_CTRL, reg); 1349 1350 return 0; 1351 } 1352 1353 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1354 unsigned int rx_mask, int slots, int slot_width) 1355 { 1356 struct snd_soc_codec *codec = dai->codec; 1357 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1358 int aif1 = 0; 1359 int aif2 = 0; 1360 1361 /* Don't need to validate anything if we're turning off TDM */ 1362 if (slots == 0) { 1363 wm8993->tdm_slots = 0; 1364 goto out; 1365 } 1366 1367 /* Note that we allow configurations we can't handle ourselves - 1368 * for example, we can generate clocks for slots 2 and up even if 1369 * we can't use those slots ourselves. 1370 */ 1371 aif1 |= WM8993_AIFADC_TDM; 1372 aif2 |= WM8993_AIFDAC_TDM; 1373 1374 switch (rx_mask) { 1375 case 3: 1376 break; 1377 case 0xc: 1378 aif1 |= WM8993_AIFADC_TDM_CHAN; 1379 break; 1380 default: 1381 return -EINVAL; 1382 } 1383 1384 1385 switch (tx_mask) { 1386 case 3: 1387 break; 1388 case 0xc: 1389 aif2 |= WM8993_AIFDAC_TDM_CHAN; 1390 break; 1391 default: 1392 return -EINVAL; 1393 } 1394 1395 out: 1396 wm8993->tdm_width = slot_width; 1397 wm8993->tdm_slots = slots / 2; 1398 1399 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1, 1400 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1); 1401 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2, 1402 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2); 1403 1404 return 0; 1405 } 1406 1407 static irqreturn_t wm8993_irq(int irq, void *data) 1408 { 1409 struct wm8993_priv *wm8993 = data; 1410 int mask, val, ret; 1411 1412 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val); 1413 if (ret != 0) { 1414 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n", 1415 ret); 1416 return IRQ_NONE; 1417 } 1418 1419 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask); 1420 if (ret != 0) { 1421 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n", 1422 ret); 1423 return IRQ_NONE; 1424 } 1425 1426 /* The IRQ pin status is visible in the register too */ 1427 val &= ~(mask | WM8993_IRQ); 1428 if (!val) 1429 return IRQ_NONE; 1430 1431 if (val & WM8993_TEMPOK_EINT) 1432 dev_crit(wm8993->dev, "Thermal warning\n"); 1433 1434 if (val & WM8993_FLL_LOCK_EINT) { 1435 dev_dbg(wm8993->dev, "FLL locked\n"); 1436 complete(&wm8993->fll_lock); 1437 } 1438 1439 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val); 1440 if (ret != 0) 1441 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret); 1442 1443 return IRQ_HANDLED; 1444 } 1445 1446 static const struct snd_soc_dai_ops wm8993_ops = { 1447 .set_sysclk = wm8993_set_sysclk, 1448 .set_fmt = wm8993_set_dai_fmt, 1449 .hw_params = wm8993_hw_params, 1450 .digital_mute = wm8993_digital_mute, 1451 .set_pll = wm8993_set_fll, 1452 .set_tdm_slot = wm8993_set_tdm_slot, 1453 }; 1454 1455 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000 1456 1457 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1458 SNDRV_PCM_FMTBIT_S20_3LE |\ 1459 SNDRV_PCM_FMTBIT_S24_LE |\ 1460 SNDRV_PCM_FMTBIT_S32_LE) 1461 1462 static struct snd_soc_dai_driver wm8993_dai = { 1463 .name = "wm8993-hifi", 1464 .playback = { 1465 .stream_name = "Playback", 1466 .channels_min = 1, 1467 .channels_max = 2, 1468 .rates = WM8993_RATES, 1469 .formats = WM8993_FORMATS, 1470 .sig_bits = 24, 1471 }, 1472 .capture = { 1473 .stream_name = "Capture", 1474 .channels_min = 1, 1475 .channels_max = 2, 1476 .rates = WM8993_RATES, 1477 .formats = WM8993_FORMATS, 1478 .sig_bits = 24, 1479 }, 1480 .ops = &wm8993_ops, 1481 .symmetric_rates = 1, 1482 }; 1483 1484 static int wm8993_probe(struct snd_soc_codec *codec) 1485 { 1486 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1487 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1488 1489 wm8993->hubs_data.hp_startup_mode = 1; 1490 wm8993->hubs_data.dcs_codes_l = -2; 1491 wm8993->hubs_data.dcs_codes_r = -2; 1492 wm8993->hubs_data.series_startup = 1; 1493 1494 /* Latch volume update bits and default ZC on */ 1495 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1496 WM8993_DAC_VU, WM8993_DAC_VU); 1497 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1498 WM8993_ADC_VU, WM8993_ADC_VU); 1499 1500 /* Manualy manage the HPOUT sequencing for independent stereo 1501 * control. */ 1502 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0, 1503 WM8993_HPOUT1_AUTO_PU, 0); 1504 1505 /* Use automatic clock configuration */ 1506 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0); 1507 1508 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff, 1509 wm8993->pdata.lineout2_diff, 1510 wm8993->pdata.lineout1fb, 1511 wm8993->pdata.lineout2fb, 1512 wm8993->pdata.jd_scthr, 1513 wm8993->pdata.jd_thr, 1514 wm8993->pdata.micbias1_delay, 1515 wm8993->pdata.micbias2_delay, 1516 wm8993->pdata.micbias1_lvl, 1517 wm8993->pdata.micbias2_lvl); 1518 1519 snd_soc_add_codec_controls(codec, wm8993_snd_controls, 1520 ARRAY_SIZE(wm8993_snd_controls)); 1521 if (wm8993->pdata.num_retune_configs != 0) { 1522 dev_dbg(codec->dev, "Using ReTune Mobile\n"); 1523 } else { 1524 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n"); 1525 snd_soc_add_codec_controls(codec, wm8993_eq_controls, 1526 ARRAY_SIZE(wm8993_eq_controls)); 1527 } 1528 1529 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets, 1530 ARRAY_SIZE(wm8993_dapm_widgets)); 1531 wm_hubs_add_analogue_controls(codec); 1532 1533 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 1534 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, 1535 wm8993->pdata.lineout2_diff); 1536 1537 /* If the line outputs are differential then we aren't presenting 1538 * VMID as an output and can disable it. 1539 */ 1540 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff) 1541 dapm->idle_bias_off = 1; 1542 1543 return 0; 1544 1545 } 1546 1547 #ifdef CONFIG_PM 1548 static int wm8993_suspend(struct snd_soc_codec *codec) 1549 { 1550 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1551 int fll_fout = wm8993->fll_fout; 1552 int fll_fref = wm8993->fll_fref; 1553 int ret; 1554 1555 /* Stop the FLL in an orderly fashion */ 1556 ret = _wm8993_set_fll(codec, 0, 0, 0, 0); 1557 if (ret != 0) { 1558 dev_err(codec->dev, "Failed to stop FLL\n"); 1559 return ret; 1560 } 1561 1562 wm8993->fll_fout = fll_fout; 1563 wm8993->fll_fref = fll_fref; 1564 1565 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1566 1567 return 0; 1568 } 1569 1570 static int wm8993_resume(struct snd_soc_codec *codec) 1571 { 1572 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1573 int ret; 1574 1575 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY); 1576 1577 /* Restart the FLL? */ 1578 if (wm8993->fll_fout) { 1579 int fll_fout = wm8993->fll_fout; 1580 int fll_fref = wm8993->fll_fref; 1581 1582 wm8993->fll_fref = 0; 1583 wm8993->fll_fout = 0; 1584 1585 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src, 1586 fll_fref, fll_fout); 1587 if (ret != 0) 1588 dev_err(codec->dev, "Failed to restart FLL\n"); 1589 } 1590 1591 return 0; 1592 } 1593 #else 1594 #define wm8993_suspend NULL 1595 #define wm8993_resume NULL 1596 #endif 1597 1598 /* Tune DC servo configuration */ 1599 static const struct reg_sequence wm8993_regmap_patch[] = { 1600 { 0x44, 3 }, 1601 { 0x56, 3 }, 1602 { 0x44, 0 }, 1603 }; 1604 1605 static const struct regmap_config wm8993_regmap = { 1606 .reg_bits = 8, 1607 .val_bits = 16, 1608 1609 .max_register = WM8993_MAX_REGISTER, 1610 .volatile_reg = wm8993_volatile, 1611 .readable_reg = wm8993_readable, 1612 1613 .cache_type = REGCACHE_RBTREE, 1614 .reg_defaults = wm8993_reg_defaults, 1615 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults), 1616 }; 1617 1618 static const struct snd_soc_codec_driver soc_codec_dev_wm8993 = { 1619 .probe = wm8993_probe, 1620 .suspend = wm8993_suspend, 1621 .resume = wm8993_resume, 1622 .set_bias_level = wm8993_set_bias_level, 1623 }; 1624 1625 static int wm8993_i2c_probe(struct i2c_client *i2c, 1626 const struct i2c_device_id *id) 1627 { 1628 struct wm8993_priv *wm8993; 1629 unsigned int reg; 1630 int ret, i; 1631 1632 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv), 1633 GFP_KERNEL); 1634 if (wm8993 == NULL) 1635 return -ENOMEM; 1636 1637 wm8993->dev = &i2c->dev; 1638 init_completion(&wm8993->fll_lock); 1639 1640 wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap); 1641 if (IS_ERR(wm8993->regmap)) { 1642 ret = PTR_ERR(wm8993->regmap); 1643 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 1644 return ret; 1645 } 1646 1647 i2c_set_clientdata(i2c, wm8993); 1648 1649 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++) 1650 wm8993->supplies[i].supply = wm8993_supply_names[i]; 1651 1652 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies), 1653 wm8993->supplies); 1654 if (ret != 0) { 1655 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1656 return ret; 1657 } 1658 1659 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 1660 wm8993->supplies); 1661 if (ret != 0) { 1662 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 1663 return ret; 1664 } 1665 1666 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®); 1667 if (ret != 0) { 1668 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 1669 goto err_enable; 1670 } 1671 1672 if (reg != 0x8993) { 1673 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg); 1674 ret = -EINVAL; 1675 goto err_enable; 1676 } 1677 1678 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff); 1679 if (ret != 0) 1680 goto err_enable; 1681 1682 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch, 1683 ARRAY_SIZE(wm8993_regmap_patch)); 1684 if (ret != 0) 1685 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n", 1686 ret); 1687 1688 if (i2c->irq) { 1689 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */ 1690 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1, 1691 WM8993_GPIO1_PD | 1692 WM8993_GPIO1_SEL_MASK, 7); 1693 if (ret != 0) 1694 goto err_enable; 1695 1696 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq, 1697 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1698 "wm8993", wm8993); 1699 if (ret != 0) 1700 goto err_enable; 1701 1702 } 1703 1704 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1705 1706 regcache_cache_only(wm8993->regmap, true); 1707 1708 ret = snd_soc_register_codec(&i2c->dev, 1709 &soc_codec_dev_wm8993, &wm8993_dai, 1); 1710 if (ret != 0) { 1711 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 1712 goto err_irq; 1713 } 1714 1715 return 0; 1716 1717 err_irq: 1718 if (i2c->irq) 1719 free_irq(i2c->irq, wm8993); 1720 err_enable: 1721 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1722 return ret; 1723 } 1724 1725 static int wm8993_i2c_remove(struct i2c_client *i2c) 1726 { 1727 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c); 1728 1729 snd_soc_unregister_codec(&i2c->dev); 1730 if (i2c->irq) 1731 free_irq(i2c->irq, wm8993); 1732 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1733 1734 return 0; 1735 } 1736 1737 static const struct i2c_device_id wm8993_i2c_id[] = { 1738 { "wm8993", 0 }, 1739 { } 1740 }; 1741 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id); 1742 1743 static struct i2c_driver wm8993_i2c_driver = { 1744 .driver = { 1745 .name = "wm8993", 1746 }, 1747 .probe = wm8993_i2c_probe, 1748 .remove = wm8993_i2c_remove, 1749 .id_table = wm8993_i2c_id, 1750 }; 1751 1752 module_i2c_driver(wm8993_i2c_driver); 1753 1754 MODULE_DESCRIPTION("ASoC WM8993 driver"); 1755 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1756 MODULE_LICENSE("GPL"); 1757