1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * wm8991.c -- WM8991 ALSA Soc Audio driver 4 * 5 * Copyright 2007-2010 Wolfson Microelectronics PLC. 6 * Author: Graeme Gregory 7 * Graeme.Gregory@wolfsonmicro.com 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <asm/div64.h> 27 28 #include "wm8991.h" 29 30 struct wm8991_priv { 31 struct regmap *regmap; 32 unsigned int pcmclk; 33 }; 34 35 static const struct reg_default wm8991_reg_defaults[] = { 36 { 1, 0x0000 }, /* R1 - Power Management (1) */ 37 { 2, 0x6000 }, /* R2 - Power Management (2) */ 38 { 3, 0x0000 }, /* R3 - Power Management (3) */ 39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 41 { 6, 0x01C8 }, /* R6 - Clocking (1) */ 42 { 7, 0x0000 }, /* R7 - Clocking (2) */ 43 { 8, 0x0040 }, /* R8 - Audio Interface (3) */ 44 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 45 { 10, 0x0004 }, /* R10 - DAC CTRL */ 46 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 47 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 48 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 49 { 14, 0x0100 }, /* R14 - ADC CTRL */ 50 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 51 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 52 53 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 54 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */ 55 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */ 56 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */ 57 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 58 { 23, 0x0800 }, /* R23 - GPIO_POL */ 59 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 60 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 61 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 62 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 63 { 28, 0x0000 }, /* R28 - Left Output Volume */ 64 { 29, 0x0000 }, /* R29 - Right Output Volume */ 65 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 66 { 31, 0x0022 }, /* R31 - Out3/4 Volume */ 67 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 68 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 69 { 34, 0x0003 }, /* R34 - Speaker Volume */ 70 { 35, 0x0003 }, /* R35 - ClassD1 */ 71 72 { 37, 0x0100 }, /* R37 - ClassD3 */ 73 74 { 39, 0x0000 }, /* R39 - Input Mixer1 */ 75 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 76 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 77 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 78 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 79 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 80 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 81 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 82 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 83 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 84 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 85 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 86 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */ 87 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 88 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 89 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 90 { 55, 0x0000 }, /* R55 - Additional Control */ 91 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 92 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 93 { 58, 0x0000 }, /* R58 - MICBIAS */ 94 95 { 60, 0x0008 }, /* R60 - PLL1 */ 96 { 61, 0x0031 }, /* R61 - PLL2 */ 97 { 62, 0x0026 }, /* R62 - PLL3 */ 98 }; 99 100 static bool wm8991_volatile(struct device *dev, unsigned int reg) 101 { 102 switch (reg) { 103 case WM8991_RESET: 104 return true; 105 default: 106 return false; 107 } 108 } 109 110 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_pga_tlv, -1650, 150, 0); 111 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(out_mix_tlv, -2100, 300, 0); 112 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_pga_tlv, 113 0x00, 0x2f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(SNDRV_CTL_TLVD_DB_GAIN_MUTE, 0, 1), 114 0x30, 0x7f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-7300, 100, 0), 115 ); 116 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_dac_tlv, 117 0x00, 0xbf, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1), 118 0xc0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0), 119 ); 120 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(in_adc_tlv, 121 0x00, 0xef, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1), 122 0xf0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(17625, 0, 0), 123 ); 124 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_sidetone_tlv, 125 0x00, 0x0c, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-3600, 300, 0), 126 0x0d, 0x0f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0), 127 ); 128 129 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 130 struct snd_ctl_elem_value *ucontrol) 131 { 132 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 133 int reg = kcontrol->private_value & 0xff; 134 int ret; 135 u16 val; 136 137 ret = snd_soc_put_volsw(kcontrol, ucontrol); 138 if (ret < 0) 139 return ret; 140 141 /* now hit the volume update bits (always bit 8) */ 142 val = snd_soc_component_read(component, reg); 143 return snd_soc_component_write(component, reg, val | 0x0100); 144 } 145 146 static const char *wm8991_digital_sidetone[] = 147 {"None", "Left ADC", "Right ADC", "Reserved"}; 148 149 static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum, 150 WM8991_DIGITAL_SIDE_TONE, 151 WM8991_ADC_TO_DACL_SHIFT, 152 wm8991_digital_sidetone); 153 154 static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum, 155 WM8991_DIGITAL_SIDE_TONE, 156 WM8991_ADC_TO_DACR_SHIFT, 157 wm8991_digital_sidetone); 158 159 static const char *wm8991_adcmode[] = 160 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 161 162 static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum, 163 WM8991_ADC_CTRL, 164 WM8991_ADC_HPF_CUT_SHIFT, 165 wm8991_adcmode); 166 167 static const struct snd_kcontrol_new wm8991_snd_controls[] = { 168 /* INMIXL */ 169 SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0), 170 SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0), 171 /* INMIXR */ 172 SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0), 173 SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0), 174 175 /* LOMIX */ 176 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3, 177 WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv), 178 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 179 WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv), 180 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 181 WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv), 182 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5, 183 WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv), 184 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 185 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 186 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 187 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 188 189 /* ROMIX */ 190 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4, 191 WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv), 192 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 193 WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv), 194 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 195 WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv), 196 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6, 197 WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv), 198 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 199 WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv), 200 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 201 WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv), 202 203 /* LOUT */ 204 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME, 205 WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv), 206 SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0), 207 208 /* ROUT */ 209 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME, 210 WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv), 211 SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0), 212 213 /* LOPGA */ 214 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME, 215 WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv), 216 SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME, 217 WM8991_LOPGAZC_BIT, 1, 0), 218 219 /* ROPGA */ 220 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME, 221 WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv), 222 SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME, 223 WM8991_ROPGAZC_BIT, 1, 0), 224 225 SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 226 WM8991_LONMUTE_BIT, 1, 0), 227 SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 228 WM8991_LOPMUTE_BIT, 1, 0), 229 SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 230 WM8991_LOATTN_BIT, 1, 0), 231 SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 232 WM8991_RONMUTE_BIT, 1, 0), 233 SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 234 WM8991_ROPMUTE_BIT, 1, 0), 235 SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 236 WM8991_ROATTN_BIT, 1, 0), 237 238 SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME, 239 WM8991_OUT3MUTE_BIT, 1, 0), 240 SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME, 241 WM8991_OUT3ATTN_BIT, 1, 0), 242 243 SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME, 244 WM8991_OUT4MUTE_BIT, 1, 0), 245 SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME, 246 WM8991_OUT4ATTN_BIT, 1, 0), 247 248 SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1, 249 WM8991_CDMODE_BIT, 1, 0), 250 251 SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME, 252 WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0), 253 SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3, 254 WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0), 255 SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3, 256 WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0), 257 258 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 259 WM8991_LEFT_DAC_DIGITAL_VOLUME, 260 WM8991_DACL_VOL_SHIFT, 261 WM8991_DACL_VOL_MASK, 262 0, 263 out_dac_tlv), 264 265 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 266 WM8991_RIGHT_DAC_DIGITAL_VOLUME, 267 WM8991_DACR_VOL_SHIFT, 268 WM8991_DACR_VOL_MASK, 269 0, 270 out_dac_tlv), 271 272 SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum), 273 SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum), 274 275 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 276 WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0, 277 out_sidetone_tlv), 278 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 279 WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0, 280 out_sidetone_tlv), 281 282 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL, 283 WM8991_ADC_HPF_ENA_BIT, 1, 0), 284 285 SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum), 286 287 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 288 WM8991_LEFT_ADC_DIGITAL_VOLUME, 289 WM8991_ADCL_VOL_SHIFT, 290 WM8991_ADCL_VOL_MASK, 291 0, 292 in_adc_tlv), 293 294 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 295 WM8991_RIGHT_ADC_DIGITAL_VOLUME, 296 WM8991_ADCR_VOL_SHIFT, 297 WM8991_ADCR_VOL_MASK, 298 0, 299 in_adc_tlv), 300 301 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 302 WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 303 WM8991_LIN12VOL_SHIFT, 304 WM8991_LIN12VOL_MASK, 305 0, 306 in_pga_tlv), 307 308 SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 309 WM8991_LI12ZC_BIT, 1, 0), 310 311 SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 312 WM8991_LI12MUTE_BIT, 1, 0), 313 314 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 315 WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 316 WM8991_LIN34VOL_SHIFT, 317 WM8991_LIN34VOL_MASK, 318 0, 319 in_pga_tlv), 320 321 SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 322 WM8991_LI34ZC_BIT, 1, 0), 323 324 SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 325 WM8991_LI34MUTE_BIT, 1, 0), 326 327 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 328 WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 329 WM8991_RIN12VOL_SHIFT, 330 WM8991_RIN12VOL_MASK, 331 0, 332 in_pga_tlv), 333 334 SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 335 WM8991_RI12ZC_BIT, 1, 0), 336 337 SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 338 WM8991_RI12MUTE_BIT, 1, 0), 339 340 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 341 WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 342 WM8991_RIN34VOL_SHIFT, 343 WM8991_RIN34VOL_MASK, 344 0, 345 in_pga_tlv), 346 347 SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 348 WM8991_RI34ZC_BIT, 1, 0), 349 350 SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 351 WM8991_RI34MUTE_BIT, 1, 0), 352 }; 353 354 /* 355 * _DAPM_ Controls 356 */ 357 static int outmixer_event(struct snd_soc_dapm_widget *w, 358 struct snd_kcontrol *kcontrol, int event) 359 { 360 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 361 u32 reg_shift = kcontrol->private_value & 0xfff; 362 int ret = 0; 363 u16 reg; 364 365 switch (reg_shift) { 366 case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8): 367 reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER1); 368 if (reg & WM8991_LDLO) { 369 printk(KERN_WARNING 370 "Cannot set as Output Mixer 1 LDLO Set\n"); 371 ret = -1; 372 } 373 break; 374 375 case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8): 376 reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER2); 377 if (reg & WM8991_RDRO) { 378 printk(KERN_WARNING 379 "Cannot set as Output Mixer 2 RDRO Set\n"); 380 ret = -1; 381 } 382 break; 383 384 case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8): 385 reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER); 386 if (reg & WM8991_LDSPK) { 387 printk(KERN_WARNING 388 "Cannot set as Speaker Mixer LDSPK Set\n"); 389 ret = -1; 390 } 391 break; 392 393 case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8): 394 reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER); 395 if (reg & WM8991_RDSPK) { 396 printk(KERN_WARNING 397 "Cannot set as Speaker Mixer RDSPK Set\n"); 398 ret = -1; 399 } 400 break; 401 } 402 403 return ret; 404 } 405 406 /* INMIX dB values */ 407 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_mix_tlv, -1200, 300, 1); 408 409 /* Left In PGA Connections */ 410 static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = { 411 SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0), 412 SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0), 413 }; 414 415 static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = { 416 SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0), 417 SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0), 418 }; 419 420 /* Right In PGA Connections */ 421 static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = { 422 SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0), 423 SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0), 424 }; 425 426 static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = { 427 SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0), 428 SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0), 429 }; 430 431 /* INMIXL */ 432 static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = { 433 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3, 434 WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv), 435 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT, 436 7, 0, in_mix_tlv), 437 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 438 1, 0), 439 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 440 1, 0), 441 }; 442 443 /* INMIXR */ 444 static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = { 445 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4, 446 WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv), 447 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT, 448 7, 0, in_mix_tlv), 449 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 450 1, 0), 451 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 452 1, 0), 453 }; 454 455 /* AINLMUX */ 456 static const char *wm8991_ainlmux[] = 457 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 458 459 static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum, 460 WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT, 461 wm8991_ainlmux); 462 463 static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls = 464 SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum); 465 466 /* DIFFINL */ 467 468 /* AINRMUX */ 469 static const char *wm8991_ainrmux[] = 470 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 471 472 static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum, 473 WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT, 474 wm8991_ainrmux); 475 476 static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls = 477 SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum); 478 479 /* LOMIX */ 480 static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = { 481 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 482 WM8991_LRBLO_BIT, 1, 0), 483 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 484 WM8991_LLBLO_BIT, 1, 0), 485 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 486 WM8991_LRI3LO_BIT, 1, 0), 487 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 488 WM8991_LLI3LO_BIT, 1, 0), 489 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 490 WM8991_LR12LO_BIT, 1, 0), 491 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 492 WM8991_LL12LO_BIT, 1, 0), 493 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1, 494 WM8991_LDLO_BIT, 1, 0), 495 }; 496 497 /* ROMIX */ 498 static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = { 499 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 500 WM8991_RLBRO_BIT, 1, 0), 501 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 502 WM8991_RRBRO_BIT, 1, 0), 503 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 504 WM8991_RLI3RO_BIT, 1, 0), 505 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 506 WM8991_RRI3RO_BIT, 1, 0), 507 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 508 WM8991_RL12RO_BIT, 1, 0), 509 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 510 WM8991_RR12RO_BIT, 1, 0), 511 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2, 512 WM8991_RDRO_BIT, 1, 0), 513 }; 514 515 /* LONMIX */ 516 static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = { 517 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 518 WM8991_LLOPGALON_BIT, 1, 0), 519 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1, 520 WM8991_LROPGALON_BIT, 1, 0), 521 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1, 522 WM8991_LOPLON_BIT, 1, 0), 523 }; 524 525 /* LOPMIX */ 526 static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = { 527 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1, 528 WM8991_LR12LOP_BIT, 1, 0), 529 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1, 530 WM8991_LL12LOP_BIT, 1, 0), 531 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 532 WM8991_LLOPGALOP_BIT, 1, 0), 533 }; 534 535 /* RONMIX */ 536 static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = { 537 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 538 WM8991_RROPGARON_BIT, 1, 0), 539 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2, 540 WM8991_RLOPGARON_BIT, 1, 0), 541 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2, 542 WM8991_ROPRON_BIT, 1, 0), 543 }; 544 545 /* ROPMIX */ 546 static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = { 547 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2, 548 WM8991_RL12ROP_BIT, 1, 0), 549 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2, 550 WM8991_RR12ROP_BIT, 1, 0), 551 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 552 WM8991_RROPGAROP_BIT, 1, 0), 553 }; 554 555 /* OUT3MIX */ 556 static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = { 557 SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER, 558 WM8991_LI4O3_BIT, 1, 0), 559 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER, 560 WM8991_LPGAO3_BIT, 1, 0), 561 }; 562 563 /* OUT4MIX */ 564 static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = { 565 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER, 566 WM8991_RPGAO4_BIT, 1, 0), 567 SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER, 568 WM8991_RI4O4_BIT, 1, 0), 569 }; 570 571 /* SPKMIX */ 572 static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = { 573 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 574 WM8991_LI2SPK_BIT, 1, 0), 575 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER, 576 WM8991_LB2SPK_BIT, 1, 0), 577 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER, 578 WM8991_LOPGASPK_BIT, 1, 0), 579 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER, 580 WM8991_LDSPK_BIT, 1, 0), 581 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER, 582 WM8991_RDSPK_BIT, 1, 0), 583 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER, 584 WM8991_ROPGASPK_BIT, 1, 0), 585 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER, 586 WM8991_RL12ROP_BIT, 1, 0), 587 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 588 WM8991_RI2SPK_BIT, 1, 0), 589 }; 590 591 static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = { 592 /* Input Side */ 593 /* Input Lines */ 594 SND_SOC_DAPM_INPUT("LIN1"), 595 SND_SOC_DAPM_INPUT("LIN2"), 596 SND_SOC_DAPM_INPUT("LIN3"), 597 SND_SOC_DAPM_INPUT("LIN4RXN"), 598 SND_SOC_DAPM_INPUT("RIN3"), 599 SND_SOC_DAPM_INPUT("RIN4RXP"), 600 SND_SOC_DAPM_INPUT("RIN1"), 601 SND_SOC_DAPM_INPUT("RIN2"), 602 SND_SOC_DAPM_INPUT("Internal ADC Source"), 603 604 SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2, 605 WM8991_AINL_ENA_BIT, 0, NULL, 0), 606 SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2, 607 WM8991_AINR_ENA_BIT, 0, NULL, 0), 608 609 /* DACs */ 610 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2, 611 WM8991_ADCL_ENA_BIT, 0), 612 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2, 613 WM8991_ADCR_ENA_BIT, 0), 614 615 /* Input PGAs */ 616 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT, 617 0, &wm8991_dapm_lin12_pga_controls[0], 618 ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)), 619 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT, 620 0, &wm8991_dapm_lin34_pga_controls[0], 621 ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)), 622 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT, 623 0, &wm8991_dapm_rin12_pga_controls[0], 624 ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)), 625 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT, 626 0, &wm8991_dapm_rin34_pga_controls[0], 627 ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)), 628 629 /* INMIXL */ 630 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, 631 &wm8991_dapm_inmixl_controls[0], 632 ARRAY_SIZE(wm8991_dapm_inmixl_controls)), 633 634 /* AINLMUX */ 635 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, 636 &wm8991_dapm_ainlmux_controls), 637 638 /* INMIXR */ 639 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, 640 &wm8991_dapm_inmixr_controls[0], 641 ARRAY_SIZE(wm8991_dapm_inmixr_controls)), 642 643 /* AINRMUX */ 644 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, 645 &wm8991_dapm_ainrmux_controls), 646 647 /* Output Side */ 648 /* DACs */ 649 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3, 650 WM8991_DACL_ENA_BIT, 0), 651 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3, 652 WM8991_DACR_ENA_BIT, 0), 653 654 /* LOMIX */ 655 SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT, 656 0, &wm8991_dapm_lomix_controls[0], 657 ARRAY_SIZE(wm8991_dapm_lomix_controls), 658 outmixer_event, SND_SOC_DAPM_PRE_REG), 659 660 /* LONMIX */ 661 SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0, 662 &wm8991_dapm_lonmix_controls[0], 663 ARRAY_SIZE(wm8991_dapm_lonmix_controls)), 664 665 /* LOPMIX */ 666 SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0, 667 &wm8991_dapm_lopmix_controls[0], 668 ARRAY_SIZE(wm8991_dapm_lopmix_controls)), 669 670 /* OUT3MIX */ 671 SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0, 672 &wm8991_dapm_out3mix_controls[0], 673 ARRAY_SIZE(wm8991_dapm_out3mix_controls)), 674 675 /* SPKMIX */ 676 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0, 677 &wm8991_dapm_spkmix_controls[0], 678 ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event, 679 SND_SOC_DAPM_PRE_REG), 680 681 /* OUT4MIX */ 682 SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0, 683 &wm8991_dapm_out4mix_controls[0], 684 ARRAY_SIZE(wm8991_dapm_out4mix_controls)), 685 686 /* ROPMIX */ 687 SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0, 688 &wm8991_dapm_ropmix_controls[0], 689 ARRAY_SIZE(wm8991_dapm_ropmix_controls)), 690 691 /* RONMIX */ 692 SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0, 693 &wm8991_dapm_ronmix_controls[0], 694 ARRAY_SIZE(wm8991_dapm_ronmix_controls)), 695 696 /* ROMIX */ 697 SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT, 698 0, &wm8991_dapm_romix_controls[0], 699 ARRAY_SIZE(wm8991_dapm_romix_controls), 700 outmixer_event, SND_SOC_DAPM_PRE_REG), 701 702 /* LOUT PGA */ 703 SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0, 704 NULL, 0), 705 706 /* ROUT PGA */ 707 SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0, 708 NULL, 0), 709 710 /* LOPGA */ 711 SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0, 712 NULL, 0), 713 714 /* ROPGA */ 715 SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0, 716 NULL, 0), 717 718 /* MICBIAS */ 719 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1, 720 WM8991_MICBIAS_ENA_BIT, 0, NULL, 0), 721 722 SND_SOC_DAPM_OUTPUT("LON"), 723 SND_SOC_DAPM_OUTPUT("LOP"), 724 SND_SOC_DAPM_OUTPUT("OUT3"), 725 SND_SOC_DAPM_OUTPUT("LOUT"), 726 SND_SOC_DAPM_OUTPUT("SPKN"), 727 SND_SOC_DAPM_OUTPUT("SPKP"), 728 SND_SOC_DAPM_OUTPUT("ROUT"), 729 SND_SOC_DAPM_OUTPUT("OUT4"), 730 SND_SOC_DAPM_OUTPUT("ROP"), 731 SND_SOC_DAPM_OUTPUT("RON"), 732 SND_SOC_DAPM_OUTPUT("OUT"), 733 734 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 735 }; 736 737 static const struct snd_soc_dapm_route wm8991_dapm_routes[] = { 738 /* Make DACs turn on when playing even if not mixed into any outputs */ 739 {"Internal DAC Sink", NULL, "Left DAC"}, 740 {"Internal DAC Sink", NULL, "Right DAC"}, 741 742 /* Make ADCs turn on when recording even if not mixed from any inputs */ 743 {"Left ADC", NULL, "Internal ADC Source"}, 744 {"Right ADC", NULL, "Internal ADC Source"}, 745 746 /* Input Side */ 747 {"INMIXL", NULL, "INL"}, 748 {"AINLMUX", NULL, "INL"}, 749 {"INMIXR", NULL, "INR"}, 750 {"AINRMUX", NULL, "INR"}, 751 /* LIN12 PGA */ 752 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 753 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 754 /* LIN34 PGA */ 755 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 756 {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"}, 757 /* INMIXL */ 758 {"INMIXL", "Record Left Volume", "LOMIX"}, 759 {"INMIXL", "LIN2 Volume", "LIN2"}, 760 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 761 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 762 /* AINLMUX */ 763 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 764 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 765 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 766 {"AINLMUX", "RXVOICE Mix", "LIN4RXN"}, 767 {"AINLMUX", "RXVOICE Mix", "RIN4RXP"}, 768 /* ADC */ 769 {"Left ADC", NULL, "AINLMUX"}, 770 771 /* RIN12 PGA */ 772 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 773 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 774 /* RIN34 PGA */ 775 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 776 {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"}, 777 /* INMIXL */ 778 {"INMIXR", "Record Right Volume", "ROMIX"}, 779 {"INMIXR", "RIN2 Volume", "RIN2"}, 780 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 781 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 782 /* AINRMUX */ 783 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 784 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 785 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 786 {"AINRMUX", "RXVOICE Mix", "LIN4RXN"}, 787 {"AINRMUX", "RXVOICE Mix", "RIN4RXP"}, 788 /* ADC */ 789 {"Right ADC", NULL, "AINRMUX"}, 790 791 /* LOMIX */ 792 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 793 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 794 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 795 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 796 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 797 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 798 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 799 800 /* ROMIX */ 801 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 802 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 803 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 804 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 805 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 806 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 807 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 808 809 /* SPKMIX */ 810 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 811 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 812 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 813 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 814 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 815 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 816 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 817 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, 818 819 /* LONMIX */ 820 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 821 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 822 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 823 824 /* LOPMIX */ 825 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 826 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 827 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 828 829 /* OUT3MIX */ 830 {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"}, 831 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 832 833 /* OUT4MIX */ 834 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 835 {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"}, 836 837 /* RONMIX */ 838 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 839 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 840 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 841 842 /* ROPMIX */ 843 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 844 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 845 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 846 847 /* Out Mixer PGAs */ 848 {"LOPGA", NULL, "LOMIX"}, 849 {"ROPGA", NULL, "ROMIX"}, 850 851 {"LOUT PGA", NULL, "LOMIX"}, 852 {"ROUT PGA", NULL, "ROMIX"}, 853 854 /* Output Pins */ 855 {"LON", NULL, "LONMIX"}, 856 {"LOP", NULL, "LOPMIX"}, 857 {"OUT", NULL, "OUT3MIX"}, 858 {"LOUT", NULL, "LOUT PGA"}, 859 {"SPKN", NULL, "SPKMIX"}, 860 {"ROUT", NULL, "ROUT PGA"}, 861 {"OUT4", NULL, "OUT4MIX"}, 862 {"ROP", NULL, "ROPMIX"}, 863 {"RON", NULL, "RONMIX"}, 864 }; 865 866 /* PLL divisors */ 867 struct _pll_div { 868 u32 div2; 869 u32 n; 870 u32 k; 871 }; 872 873 /* The size in bits of the pll divide multiplied by 10 874 * to allow rounding later */ 875 #define FIXED_PLL_SIZE ((1 << 16) * 10) 876 877 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 878 unsigned int source) 879 { 880 u64 Kpart; 881 unsigned int K, Ndiv, Nmod; 882 883 884 Ndiv = target / source; 885 if (Ndiv < 6) { 886 source >>= 1; 887 pll_div->div2 = 1; 888 Ndiv = target / source; 889 } else 890 pll_div->div2 = 0; 891 892 if ((Ndiv < 6) || (Ndiv > 12)) 893 printk(KERN_WARNING 894 "WM8991 N value outwith recommended range! N = %d\n", Ndiv); 895 896 pll_div->n = Ndiv; 897 Nmod = target % source; 898 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 899 900 do_div(Kpart, source); 901 902 K = Kpart & 0xFFFFFFFF; 903 904 /* Check if we need to round */ 905 if ((K % 10) >= 5) 906 K += 5; 907 908 /* Move down to proper range now rounding is done */ 909 K /= 10; 910 911 pll_div->k = K; 912 } 913 914 static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai, 915 int pll_id, int src, unsigned int freq_in, unsigned int freq_out) 916 { 917 u16 reg; 918 struct snd_soc_component *component = codec_dai->component; 919 struct _pll_div pll_div; 920 921 if (freq_in && freq_out) { 922 pll_factors(&pll_div, freq_out * 4, freq_in); 923 924 /* Turn on PLL */ 925 reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2); 926 reg |= WM8991_PLL_ENA; 927 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); 928 929 /* sysclk comes from PLL */ 930 reg = snd_soc_component_read(component, WM8991_CLOCKING_2); 931 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); 932 933 /* set up N , fractional mode and pre-divisor if necessary */ 934 snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM | 935 (pll_div.div2 ? WM8991_PRESCALE : 0)); 936 snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8)); 937 snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); 938 } else { 939 /* Turn on PLL */ 940 reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2); 941 reg &= ~WM8991_PLL_ENA; 942 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); 943 } 944 return 0; 945 } 946 947 /* 948 * Set's ADC and Voice DAC format. 949 */ 950 static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai, 951 unsigned int fmt) 952 { 953 struct snd_soc_component *component = codec_dai->component; 954 u16 audio1, audio3; 955 956 audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1); 957 audio3 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_3); 958 959 /* set master/slave audio interface */ 960 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 961 case SND_SOC_DAIFMT_CBS_CFS: 962 audio3 &= ~WM8991_AIF_MSTR1; 963 break; 964 case SND_SOC_DAIFMT_CBM_CFM: 965 audio3 |= WM8991_AIF_MSTR1; 966 break; 967 default: 968 return -EINVAL; 969 } 970 971 audio1 &= ~WM8991_AIF_FMT_MASK; 972 973 /* interface format */ 974 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 975 case SND_SOC_DAIFMT_I2S: 976 audio1 |= WM8991_AIF_TMF_I2S; 977 audio1 &= ~WM8991_AIF_LRCLK_INV; 978 break; 979 case SND_SOC_DAIFMT_RIGHT_J: 980 audio1 |= WM8991_AIF_TMF_RIGHTJ; 981 audio1 &= ~WM8991_AIF_LRCLK_INV; 982 break; 983 case SND_SOC_DAIFMT_LEFT_J: 984 audio1 |= WM8991_AIF_TMF_LEFTJ; 985 audio1 &= ~WM8991_AIF_LRCLK_INV; 986 break; 987 case SND_SOC_DAIFMT_DSP_A: 988 audio1 |= WM8991_AIF_TMF_DSP; 989 audio1 &= ~WM8991_AIF_LRCLK_INV; 990 break; 991 case SND_SOC_DAIFMT_DSP_B: 992 audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV; 993 break; 994 default: 995 return -EINVAL; 996 } 997 998 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1); 999 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_3, audio3); 1000 return 0; 1001 } 1002 1003 static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1004 int div_id, int div) 1005 { 1006 struct snd_soc_component *component = codec_dai->component; 1007 u16 reg; 1008 1009 switch (div_id) { 1010 case WM8991_MCLK_DIV: 1011 reg = snd_soc_component_read(component, WM8991_CLOCKING_2) & 1012 ~WM8991_MCLK_DIV_MASK; 1013 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1014 break; 1015 case WM8991_DACCLK_DIV: 1016 reg = snd_soc_component_read(component, WM8991_CLOCKING_2) & 1017 ~WM8991_DAC_CLKDIV_MASK; 1018 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1019 break; 1020 case WM8991_ADCCLK_DIV: 1021 reg = snd_soc_component_read(component, WM8991_CLOCKING_2) & 1022 ~WM8991_ADC_CLKDIV_MASK; 1023 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1024 break; 1025 case WM8991_BCLK_DIV: 1026 reg = snd_soc_component_read(component, WM8991_CLOCKING_1) & 1027 ~WM8991_BCLK_DIV_MASK; 1028 snd_soc_component_write(component, WM8991_CLOCKING_1, reg | div); 1029 break; 1030 default: 1031 return -EINVAL; 1032 } 1033 1034 return 0; 1035 } 1036 1037 /* 1038 * Set PCM DAI bit size and sample rate. 1039 */ 1040 static int wm8991_hw_params(struct snd_pcm_substream *substream, 1041 struct snd_pcm_hw_params *params, 1042 struct snd_soc_dai *dai) 1043 { 1044 struct snd_soc_component *component = dai->component; 1045 u16 audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1); 1046 1047 audio1 &= ~WM8991_AIF_WL_MASK; 1048 /* bit size */ 1049 switch (params_width(params)) { 1050 case 16: 1051 break; 1052 case 20: 1053 audio1 |= WM8991_AIF_WL_20BITS; 1054 break; 1055 case 24: 1056 audio1 |= WM8991_AIF_WL_24BITS; 1057 break; 1058 case 32: 1059 audio1 |= WM8991_AIF_WL_32BITS; 1060 break; 1061 } 1062 1063 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1); 1064 return 0; 1065 } 1066 1067 static int wm8991_mute(struct snd_soc_dai *dai, int mute, int direction) 1068 { 1069 struct snd_soc_component *component = dai->component; 1070 u16 val; 1071 1072 val = snd_soc_component_read(component, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE; 1073 if (mute) 1074 snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1075 else 1076 snd_soc_component_write(component, WM8991_DAC_CTRL, val); 1077 return 0; 1078 } 1079 1080 static int wm8991_set_bias_level(struct snd_soc_component *component, 1081 enum snd_soc_bias_level level) 1082 { 1083 struct wm8991_priv *wm8991 = snd_soc_component_get_drvdata(component); 1084 u16 val; 1085 1086 switch (level) { 1087 case SND_SOC_BIAS_ON: 1088 break; 1089 1090 case SND_SOC_BIAS_PREPARE: 1091 /* VMID=2*50k */ 1092 val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) & 1093 ~WM8991_VMID_MODE_MASK; 1094 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x2); 1095 break; 1096 1097 case SND_SOC_BIAS_STANDBY: 1098 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1099 regcache_sync(wm8991->regmap); 1100 /* Enable all output discharge bits */ 1101 snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1102 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1103 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1104 WM8991_DIS_ROUT); 1105 1106 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1107 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1108 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1109 WM8991_VMIDTOG); 1110 1111 /* Delay to allow output caps to discharge */ 1112 msleep(300); 1113 1114 /* Disable VMIDTOG */ 1115 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1116 WM8991_BUFDCOPEN | WM8991_POBCTRL); 1117 1118 /* disable all output discharge bits */ 1119 snd_soc_component_write(component, WM8991_ANTIPOP1, 0); 1120 1121 /* Enable outputs */ 1122 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1b00); 1123 1124 msleep(50); 1125 1126 /* Enable VMID at 2x50k */ 1127 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f02); 1128 1129 msleep(100); 1130 1131 /* Enable VREF */ 1132 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1133 1134 msleep(600); 1135 1136 /* Enable BUFIOEN */ 1137 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1138 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1139 WM8991_BUFIOEN); 1140 1141 /* Disable outputs */ 1142 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x3); 1143 1144 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1145 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_BUFIOEN); 1146 } 1147 1148 /* VMID=2*250k */ 1149 val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) & 1150 ~WM8991_VMID_MODE_MASK; 1151 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x4); 1152 break; 1153 1154 case SND_SOC_BIAS_OFF: 1155 /* Enable POBCTRL and SOFT_ST */ 1156 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1157 WM8991_POBCTRL | WM8991_BUFIOEN); 1158 1159 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1160 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1161 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1162 WM8991_BUFIOEN); 1163 1164 /* mute DAC */ 1165 val = snd_soc_component_read(component, WM8991_DAC_CTRL); 1166 snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1167 1168 /* Enable any disabled outputs */ 1169 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1170 1171 /* Disable VMID */ 1172 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f01); 1173 1174 msleep(300); 1175 1176 /* Enable all output discharge bits */ 1177 snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1178 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1179 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1180 WM8991_DIS_ROUT); 1181 1182 /* Disable VREF */ 1183 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x0); 1184 1185 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1186 snd_soc_component_write(component, WM8991_ANTIPOP2, 0x0); 1187 regcache_mark_dirty(wm8991->regmap); 1188 break; 1189 } 1190 1191 return 0; 1192 } 1193 1194 #define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1195 SNDRV_PCM_FMTBIT_S24_LE) 1196 1197 static const struct snd_soc_dai_ops wm8991_ops = { 1198 .hw_params = wm8991_hw_params, 1199 .mute_stream = wm8991_mute, 1200 .set_fmt = wm8991_set_dai_fmt, 1201 .set_clkdiv = wm8991_set_dai_clkdiv, 1202 .set_pll = wm8991_set_dai_pll, 1203 .no_capture_mute = 1, 1204 }; 1205 1206 /* 1207 * The WM8991 supports 2 different and mutually exclusive DAI 1208 * configurations. 1209 * 1210 * 1. ADC/DAC on Primary Interface 1211 * 2. ADC on Primary Interface/DAC on secondary 1212 */ 1213 static struct snd_soc_dai_driver wm8991_dai = { 1214 /* ADC/DAC on primary */ 1215 .name = "wm8991", 1216 .id = 1, 1217 .playback = { 1218 .stream_name = "Playback", 1219 .channels_min = 1, 1220 .channels_max = 2, 1221 .rates = SNDRV_PCM_RATE_8000_96000, 1222 .formats = WM8991_FORMATS 1223 }, 1224 .capture = { 1225 .stream_name = "Capture", 1226 .channels_min = 1, 1227 .channels_max = 2, 1228 .rates = SNDRV_PCM_RATE_8000_96000, 1229 .formats = WM8991_FORMATS 1230 }, 1231 .ops = &wm8991_ops 1232 }; 1233 1234 static const struct snd_soc_component_driver soc_component_dev_wm8991 = { 1235 .set_bias_level = wm8991_set_bias_level, 1236 .controls = wm8991_snd_controls, 1237 .num_controls = ARRAY_SIZE(wm8991_snd_controls), 1238 .dapm_widgets = wm8991_dapm_widgets, 1239 .num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets), 1240 .dapm_routes = wm8991_dapm_routes, 1241 .num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes), 1242 .suspend_bias_off = 1, 1243 .idle_bias_on = 1, 1244 .use_pmdown_time = 1, 1245 .endianness = 1, 1246 }; 1247 1248 static const struct regmap_config wm8991_regmap = { 1249 .reg_bits = 8, 1250 .val_bits = 16, 1251 1252 .max_register = WM8991_PLL3, 1253 .volatile_reg = wm8991_volatile, 1254 .reg_defaults = wm8991_reg_defaults, 1255 .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults), 1256 .cache_type = REGCACHE_RBTREE, 1257 }; 1258 1259 static int wm8991_i2c_probe(struct i2c_client *i2c) 1260 { 1261 struct wm8991_priv *wm8991; 1262 unsigned int val; 1263 int ret; 1264 1265 wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL); 1266 if (!wm8991) 1267 return -ENOMEM; 1268 1269 wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap); 1270 if (IS_ERR(wm8991->regmap)) 1271 return PTR_ERR(wm8991->regmap); 1272 1273 i2c_set_clientdata(i2c, wm8991); 1274 1275 ret = regmap_read(wm8991->regmap, WM8991_RESET, &val); 1276 if (ret != 0) { 1277 dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret); 1278 return ret; 1279 } 1280 if (val != 0x8991) { 1281 dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val); 1282 return -EINVAL; 1283 } 1284 1285 ret = regmap_write(wm8991->regmap, WM8991_RESET, 0); 1286 if (ret < 0) { 1287 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 1288 return ret; 1289 } 1290 1291 regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4, 1292 WM8991_ALRCGPIO1, WM8991_ALRCGPIO1); 1293 1294 regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2, 1295 WM8991_GPIO1_SEL_MASK, 1); 1296 1297 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1, 1298 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK, 1299 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK); 1300 1301 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2, 1302 WM8991_OPCLK_ENA, WM8991_OPCLK_ENA); 1303 1304 regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0); 1305 regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME, 1306 0x50 | (1<<8)); 1307 regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME, 1308 0x50 | (1<<8)); 1309 1310 ret = devm_snd_soc_register_component(&i2c->dev, 1311 &soc_component_dev_wm8991, &wm8991_dai, 1); 1312 1313 return ret; 1314 } 1315 1316 static const struct i2c_device_id wm8991_i2c_id[] = { 1317 { "wm8991", 0 }, 1318 { } 1319 }; 1320 MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id); 1321 1322 static struct i2c_driver wm8991_i2c_driver = { 1323 .driver = { 1324 .name = "wm8991", 1325 }, 1326 .probe = wm8991_i2c_probe, 1327 .id_table = wm8991_i2c_id, 1328 }; 1329 1330 module_i2c_driver(wm8991_i2c_driver); 1331 1332 MODULE_DESCRIPTION("ASoC WM8991 driver"); 1333 MODULE_AUTHOR("Graeme Gregory"); 1334 MODULE_LICENSE("GPL"); 1335