1 /* 2 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/initval.h> 26 #include <sound/tlv.h> 27 #include <asm/div64.h> 28 29 #include "wm8990.h" 30 31 /* codec private data */ 32 struct wm8990_priv { 33 enum snd_soc_control_type control_type; 34 unsigned int sysclk; 35 unsigned int pcmclk; 36 }; 37 38 static int wm8990_volatile_register(struct snd_soc_codec *codec, 39 unsigned int reg) 40 { 41 switch (reg) { 42 case WM8990_RESET: 43 return 1; 44 default: 45 return 0; 46 } 47 } 48 49 static const u16 wm8990_reg[] = { 50 0x8990, /* R0 - Reset */ 51 0x0000, /* R1 - Power Management (1) */ 52 0x6000, /* R2 - Power Management (2) */ 53 0x0000, /* R3 - Power Management (3) */ 54 0x4050, /* R4 - Audio Interface (1) */ 55 0x4000, /* R5 - Audio Interface (2) */ 56 0x01C8, /* R6 - Clocking (1) */ 57 0x0000, /* R7 - Clocking (2) */ 58 0x0040, /* R8 - Audio Interface (3) */ 59 0x0040, /* R9 - Audio Interface (4) */ 60 0x0004, /* R10 - DAC CTRL */ 61 0x00C0, /* R11 - Left DAC Digital Volume */ 62 0x00C0, /* R12 - Right DAC Digital Volume */ 63 0x0000, /* R13 - Digital Side Tone */ 64 0x0100, /* R14 - ADC CTRL */ 65 0x00C0, /* R15 - Left ADC Digital Volume */ 66 0x00C0, /* R16 - Right ADC Digital Volume */ 67 0x0000, /* R17 */ 68 0x0000, /* R18 - GPIO CTRL 1 */ 69 0x1000, /* R19 - GPIO1 & GPIO2 */ 70 0x1010, /* R20 - GPIO3 & GPIO4 */ 71 0x1010, /* R21 - GPIO5 & GPIO6 */ 72 0x8000, /* R22 - GPIOCTRL 2 */ 73 0x0800, /* R23 - GPIO_POL */ 74 0x008B, /* R24 - Left Line Input 1&2 Volume */ 75 0x008B, /* R25 - Left Line Input 3&4 Volume */ 76 0x008B, /* R26 - Right Line Input 1&2 Volume */ 77 0x008B, /* R27 - Right Line Input 3&4 Volume */ 78 0x0000, /* R28 - Left Output Volume */ 79 0x0000, /* R29 - Right Output Volume */ 80 0x0066, /* R30 - Line Outputs Volume */ 81 0x0022, /* R31 - Out3/4 Volume */ 82 0x0079, /* R32 - Left OPGA Volume */ 83 0x0079, /* R33 - Right OPGA Volume */ 84 0x0003, /* R34 - Speaker Volume */ 85 0x0003, /* R35 - ClassD1 */ 86 0x0000, /* R36 */ 87 0x0100, /* R37 - ClassD3 */ 88 0x0079, /* R38 - ClassD4 */ 89 0x0000, /* R39 - Input Mixer1 */ 90 0x0000, /* R40 - Input Mixer2 */ 91 0x0000, /* R41 - Input Mixer3 */ 92 0x0000, /* R42 - Input Mixer4 */ 93 0x0000, /* R43 - Input Mixer5 */ 94 0x0000, /* R44 - Input Mixer6 */ 95 0x0000, /* R45 - Output Mixer1 */ 96 0x0000, /* R46 - Output Mixer2 */ 97 0x0000, /* R47 - Output Mixer3 */ 98 0x0000, /* R48 - Output Mixer4 */ 99 0x0000, /* R49 - Output Mixer5 */ 100 0x0000, /* R50 - Output Mixer6 */ 101 0x0180, /* R51 - Out3/4 Mixer */ 102 0x0000, /* R52 - Line Mixer1 */ 103 0x0000, /* R53 - Line Mixer2 */ 104 0x0000, /* R54 - Speaker Mixer */ 105 0x0000, /* R55 - Additional Control */ 106 0x0000, /* R56 - AntiPOP1 */ 107 0x0000, /* R57 - AntiPOP2 */ 108 0x0000, /* R58 - MICBIAS */ 109 0x0000, /* R59 */ 110 0x0008, /* R60 - PLL1 */ 111 0x0031, /* R61 - PLL2 */ 112 0x0026, /* R62 - PLL3 */ 113 0x0000, /* R63 - Driver internal */ 114 }; 115 116 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0) 117 118 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 119 120 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 121 122 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0); 123 124 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 125 126 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 127 128 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 129 130 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 131 132 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 133 134 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 135 struct snd_ctl_elem_value *ucontrol) 136 { 137 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 138 struct soc_mixer_control *mc = 139 (struct soc_mixer_control *)kcontrol->private_value; 140 int reg = mc->reg; 141 int ret; 142 u16 val; 143 144 ret = snd_soc_put_volsw(kcontrol, ucontrol); 145 if (ret < 0) 146 return ret; 147 148 /* now hit the volume update bits (always bit 8) */ 149 val = snd_soc_read(codec, reg); 150 return snd_soc_write(codec, reg, val | 0x0100); 151 } 152 153 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 154 tlv_array) {\ 155 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 156 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 157 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 158 .tlv.p = (tlv_array), \ 159 .info = snd_soc_info_volsw, \ 160 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 161 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 162 163 164 static const char *wm8990_digital_sidetone[] = 165 {"None", "Left ADC", "Right ADC", "Reserved"}; 166 167 static const struct soc_enum wm8990_left_digital_sidetone_enum = 168 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 169 WM8990_ADC_TO_DACL_SHIFT, 170 WM8990_ADC_TO_DACL_MASK, 171 wm8990_digital_sidetone); 172 173 static const struct soc_enum wm8990_right_digital_sidetone_enum = 174 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 175 WM8990_ADC_TO_DACR_SHIFT, 176 WM8990_ADC_TO_DACR_MASK, 177 wm8990_digital_sidetone); 178 179 static const char *wm8990_adcmode[] = 180 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 181 182 static const struct soc_enum wm8990_right_adcmode_enum = 183 SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 184 WM8990_ADC_HPF_CUT_SHIFT, 185 WM8990_ADC_HPF_CUT_MASK, 186 wm8990_adcmode); 187 188 static const struct snd_kcontrol_new wm8990_snd_controls[] = { 189 /* INMIXL */ 190 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 191 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 192 /* INMIXR */ 193 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 194 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 195 196 /* LOMIX */ 197 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 198 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 199 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 200 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 201 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 202 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 203 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 204 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 205 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 206 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 207 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 208 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 209 210 /* ROMIX */ 211 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 212 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 213 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 214 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 215 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 216 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 217 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 218 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 219 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 220 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 221 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 222 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 223 224 /* LOUT */ 225 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 226 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 227 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 228 229 /* ROUT */ 230 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 231 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 232 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 233 234 /* LOPGA */ 235 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 236 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 237 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 238 WM8990_LOPGAZC_BIT, 1, 0), 239 240 /* ROPGA */ 241 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 242 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 243 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 244 WM8990_ROPGAZC_BIT, 1, 0), 245 246 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 247 WM8990_LONMUTE_BIT, 1, 0), 248 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 249 WM8990_LOPMUTE_BIT, 1, 0), 250 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 251 WM8990_LOATTN_BIT, 1, 0), 252 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 253 WM8990_RONMUTE_BIT, 1, 0), 254 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 255 WM8990_ROPMUTE_BIT, 1, 0), 256 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 257 WM8990_ROATTN_BIT, 1, 0), 258 259 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 260 WM8990_OUT3MUTE_BIT, 1, 0), 261 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 262 WM8990_OUT3ATTN_BIT, 1, 0), 263 264 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 265 WM8990_OUT4MUTE_BIT, 1, 0), 266 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 267 WM8990_OUT4ATTN_BIT, 1, 0), 268 269 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 270 WM8990_CDMODE_BIT, 1, 0), 271 272 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 273 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 274 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 275 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 276 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 277 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 278 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 279 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 280 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 281 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 282 283 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 284 WM8990_LEFT_DAC_DIGITAL_VOLUME, 285 WM8990_DACL_VOL_SHIFT, 286 WM8990_DACL_VOL_MASK, 287 0, 288 out_dac_tlv), 289 290 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 291 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 292 WM8990_DACR_VOL_SHIFT, 293 WM8990_DACR_VOL_MASK, 294 0, 295 out_dac_tlv), 296 297 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 298 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 299 300 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 301 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 302 out_sidetone_tlv), 303 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 304 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 305 out_sidetone_tlv), 306 307 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 308 WM8990_ADC_HPF_ENA_BIT, 1, 0), 309 310 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 311 312 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 313 WM8990_LEFT_ADC_DIGITAL_VOLUME, 314 WM8990_ADCL_VOL_SHIFT, 315 WM8990_ADCL_VOL_MASK, 316 0, 317 in_adc_tlv), 318 319 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 320 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 321 WM8990_ADCR_VOL_SHIFT, 322 WM8990_ADCR_VOL_MASK, 323 0, 324 in_adc_tlv), 325 326 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 327 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 328 WM8990_LIN12VOL_SHIFT, 329 WM8990_LIN12VOL_MASK, 330 0, 331 in_pga_tlv), 332 333 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 334 WM8990_LI12ZC_BIT, 1, 0), 335 336 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 337 WM8990_LI12MUTE_BIT, 1, 0), 338 339 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 340 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 341 WM8990_LIN34VOL_SHIFT, 342 WM8990_LIN34VOL_MASK, 343 0, 344 in_pga_tlv), 345 346 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 347 WM8990_LI34ZC_BIT, 1, 0), 348 349 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 350 WM8990_LI34MUTE_BIT, 1, 0), 351 352 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 353 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 354 WM8990_RIN12VOL_SHIFT, 355 WM8990_RIN12VOL_MASK, 356 0, 357 in_pga_tlv), 358 359 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 360 WM8990_RI12ZC_BIT, 1, 0), 361 362 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 363 WM8990_RI12MUTE_BIT, 1, 0), 364 365 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 366 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 367 WM8990_RIN34VOL_SHIFT, 368 WM8990_RIN34VOL_MASK, 369 0, 370 in_pga_tlv), 371 372 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 373 WM8990_RI34ZC_BIT, 1, 0), 374 375 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 376 WM8990_RI34MUTE_BIT, 1, 0), 377 378 }; 379 380 /* 381 * _DAPM_ Controls 382 */ 383 384 static int inmixer_event(struct snd_soc_dapm_widget *w, 385 struct snd_kcontrol *kcontrol, int event) 386 { 387 u16 reg, fakepower; 388 389 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2); 390 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS); 391 392 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 393 (1 << WM8990_AINLMUX_PWR_BIT))) { 394 reg |= WM8990_AINL_ENA; 395 } else { 396 reg &= ~WM8990_AINL_ENA; 397 } 398 399 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 400 (1 << WM8990_AINRMUX_PWR_BIT))) { 401 reg |= WM8990_AINR_ENA; 402 } else { 403 reg &= ~WM8990_AINR_ENA; 404 } 405 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 406 407 return 0; 408 } 409 410 static int outmixer_event(struct snd_soc_dapm_widget *w, 411 struct snd_kcontrol *kcontrol, int event) 412 { 413 u32 reg_shift = kcontrol->private_value & 0xfff; 414 int ret = 0; 415 u16 reg; 416 417 switch (reg_shift) { 418 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 419 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1); 420 if (reg & WM8990_LDLO) { 421 printk(KERN_WARNING 422 "Cannot set as Output Mixer 1 LDLO Set\n"); 423 ret = -1; 424 } 425 break; 426 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 427 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2); 428 if (reg & WM8990_RDRO) { 429 printk(KERN_WARNING 430 "Cannot set as Output Mixer 2 RDRO Set\n"); 431 ret = -1; 432 } 433 break; 434 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 435 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 436 if (reg & WM8990_LDSPK) { 437 printk(KERN_WARNING 438 "Cannot set as Speaker Mixer LDSPK Set\n"); 439 ret = -1; 440 } 441 break; 442 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 443 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 444 if (reg & WM8990_RDSPK) { 445 printk(KERN_WARNING 446 "Cannot set as Speaker Mixer RDSPK Set\n"); 447 ret = -1; 448 } 449 break; 450 } 451 452 return ret; 453 } 454 455 /* INMIX dB values */ 456 static const unsigned int in_mix_tlv[] = { 457 TLV_DB_RANGE_HEAD(1), 458 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 459 }; 460 461 /* Left In PGA Connections */ 462 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 463 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 464 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 465 }; 466 467 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 468 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 469 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 470 }; 471 472 /* Right In PGA Connections */ 473 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 474 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 475 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 476 }; 477 478 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 479 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 480 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 481 }; 482 483 /* INMIXL */ 484 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 485 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 486 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 487 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 488 7, 0, in_mix_tlv), 489 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 490 1, 0), 491 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 492 1, 0), 493 }; 494 495 /* INMIXR */ 496 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 497 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 498 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 499 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 500 7, 0, in_mix_tlv), 501 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 502 1, 0), 503 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 504 1, 0), 505 }; 506 507 /* AINLMUX */ 508 static const char *wm8990_ainlmux[] = 509 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 510 511 static const struct soc_enum wm8990_ainlmux_enum = 512 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 513 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 514 515 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 516 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 517 518 /* DIFFINL */ 519 520 /* AINRMUX */ 521 static const char *wm8990_ainrmux[] = 522 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 523 524 static const struct soc_enum wm8990_ainrmux_enum = 525 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 526 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 527 528 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 529 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 530 531 /* RXVOICE */ 532 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 533 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 534 WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 535 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 536 WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 537 }; 538 539 /* LOMIX */ 540 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 541 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 542 WM8990_LRBLO_BIT, 1, 0), 543 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 544 WM8990_LLBLO_BIT, 1, 0), 545 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 546 WM8990_LRI3LO_BIT, 1, 0), 547 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 548 WM8990_LLI3LO_BIT, 1, 0), 549 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 550 WM8990_LR12LO_BIT, 1, 0), 551 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 552 WM8990_LL12LO_BIT, 1, 0), 553 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 554 WM8990_LDLO_BIT, 1, 0), 555 }; 556 557 /* ROMIX */ 558 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 559 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 560 WM8990_RLBRO_BIT, 1, 0), 561 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 562 WM8990_RRBRO_BIT, 1, 0), 563 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 564 WM8990_RLI3RO_BIT, 1, 0), 565 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 566 WM8990_RRI3RO_BIT, 1, 0), 567 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 568 WM8990_RL12RO_BIT, 1, 0), 569 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 570 WM8990_RR12RO_BIT, 1, 0), 571 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 572 WM8990_RDRO_BIT, 1, 0), 573 }; 574 575 /* LONMIX */ 576 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 577 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 578 WM8990_LLOPGALON_BIT, 1, 0), 579 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 580 WM8990_LROPGALON_BIT, 1, 0), 581 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 582 WM8990_LOPLON_BIT, 1, 0), 583 }; 584 585 /* LOPMIX */ 586 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 587 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 588 WM8990_LR12LOP_BIT, 1, 0), 589 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 590 WM8990_LL12LOP_BIT, 1, 0), 591 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 592 WM8990_LLOPGALOP_BIT, 1, 0), 593 }; 594 595 /* RONMIX */ 596 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 597 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 598 WM8990_RROPGARON_BIT, 1, 0), 599 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 600 WM8990_RLOPGARON_BIT, 1, 0), 601 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 602 WM8990_ROPRON_BIT, 1, 0), 603 }; 604 605 /* ROPMIX */ 606 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 607 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 608 WM8990_RL12ROP_BIT, 1, 0), 609 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 610 WM8990_RR12ROP_BIT, 1, 0), 611 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 612 WM8990_RROPGAROP_BIT, 1, 0), 613 }; 614 615 /* OUT3MIX */ 616 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 617 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 618 WM8990_LI4O3_BIT, 1, 0), 619 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 620 WM8990_LPGAO3_BIT, 1, 0), 621 }; 622 623 /* OUT4MIX */ 624 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 625 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 626 WM8990_RPGAO4_BIT, 1, 0), 627 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 628 WM8990_RI4O4_BIT, 1, 0), 629 }; 630 631 /* SPKMIX */ 632 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 633 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 634 WM8990_LI2SPK_BIT, 1, 0), 635 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 636 WM8990_LB2SPK_BIT, 1, 0), 637 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 638 WM8990_LOPGASPK_BIT, 1, 0), 639 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 640 WM8990_LDSPK_BIT, 1, 0), 641 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 642 WM8990_RDSPK_BIT, 1, 0), 643 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 644 WM8990_ROPGASPK_BIT, 1, 0), 645 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 646 WM8990_RL12ROP_BIT, 1, 0), 647 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 648 WM8990_RI2SPK_BIT, 1, 0), 649 }; 650 651 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 652 /* Input Side */ 653 /* Input Lines */ 654 SND_SOC_DAPM_INPUT("LIN1"), 655 SND_SOC_DAPM_INPUT("LIN2"), 656 SND_SOC_DAPM_INPUT("LIN3"), 657 SND_SOC_DAPM_INPUT("LIN4/RXN"), 658 SND_SOC_DAPM_INPUT("RIN3"), 659 SND_SOC_DAPM_INPUT("RIN4/RXP"), 660 SND_SOC_DAPM_INPUT("RIN1"), 661 SND_SOC_DAPM_INPUT("RIN2"), 662 SND_SOC_DAPM_INPUT("Internal ADC Source"), 663 664 /* DACs */ 665 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 666 WM8990_ADCL_ENA_BIT, 0), 667 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 668 WM8990_ADCR_ENA_BIT, 0), 669 670 /* Input PGAs */ 671 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 672 0, &wm8990_dapm_lin12_pga_controls[0], 673 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 674 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 675 0, &wm8990_dapm_lin34_pga_controls[0], 676 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 677 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 678 0, &wm8990_dapm_rin12_pga_controls[0], 679 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 680 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 681 0, &wm8990_dapm_rin34_pga_controls[0], 682 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 683 684 /* INMIXL */ 685 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 686 &wm8990_dapm_inmixl_controls[0], 687 ARRAY_SIZE(wm8990_dapm_inmixl_controls), 688 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 689 690 /* AINLMUX */ 691 SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 692 &wm8990_dapm_ainlmux_controls, inmixer_event, 693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 694 695 /* INMIXR */ 696 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 697 &wm8990_dapm_inmixr_controls[0], 698 ARRAY_SIZE(wm8990_dapm_inmixr_controls), 699 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 700 701 /* AINRMUX */ 702 SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 703 &wm8990_dapm_ainrmux_controls, inmixer_event, 704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 705 706 /* Output Side */ 707 /* DACs */ 708 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 709 WM8990_DACL_ENA_BIT, 0), 710 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 711 WM8990_DACR_ENA_BIT, 0), 712 713 /* LOMIX */ 714 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 715 0, &wm8990_dapm_lomix_controls[0], 716 ARRAY_SIZE(wm8990_dapm_lomix_controls), 717 outmixer_event, SND_SOC_DAPM_PRE_REG), 718 719 /* LONMIX */ 720 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 721 &wm8990_dapm_lonmix_controls[0], 722 ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 723 724 /* LOPMIX */ 725 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 726 &wm8990_dapm_lopmix_controls[0], 727 ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 728 729 /* OUT3MIX */ 730 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 731 &wm8990_dapm_out3mix_controls[0], 732 ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 733 734 /* SPKMIX */ 735 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 736 &wm8990_dapm_spkmix_controls[0], 737 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 738 SND_SOC_DAPM_PRE_REG), 739 740 /* OUT4MIX */ 741 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 742 &wm8990_dapm_out4mix_controls[0], 743 ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 744 745 /* ROPMIX */ 746 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 747 &wm8990_dapm_ropmix_controls[0], 748 ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 749 750 /* RONMIX */ 751 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 752 &wm8990_dapm_ronmix_controls[0], 753 ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 754 755 /* ROMIX */ 756 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 757 0, &wm8990_dapm_romix_controls[0], 758 ARRAY_SIZE(wm8990_dapm_romix_controls), 759 outmixer_event, SND_SOC_DAPM_PRE_REG), 760 761 /* LOUT PGA */ 762 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 763 NULL, 0), 764 765 /* ROUT PGA */ 766 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 767 NULL, 0), 768 769 /* LOPGA */ 770 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 771 NULL, 0), 772 773 /* ROPGA */ 774 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 775 NULL, 0), 776 777 /* MICBIAS */ 778 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1, 779 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0), 780 781 SND_SOC_DAPM_OUTPUT("LON"), 782 SND_SOC_DAPM_OUTPUT("LOP"), 783 SND_SOC_DAPM_OUTPUT("OUT3"), 784 SND_SOC_DAPM_OUTPUT("LOUT"), 785 SND_SOC_DAPM_OUTPUT("SPKN"), 786 SND_SOC_DAPM_OUTPUT("SPKP"), 787 SND_SOC_DAPM_OUTPUT("ROUT"), 788 SND_SOC_DAPM_OUTPUT("OUT4"), 789 SND_SOC_DAPM_OUTPUT("ROP"), 790 SND_SOC_DAPM_OUTPUT("RON"), 791 792 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 793 }; 794 795 static const struct snd_soc_dapm_route audio_map[] = { 796 /* Make DACs turn on when playing even if not mixed into any outputs */ 797 {"Internal DAC Sink", NULL, "Left DAC"}, 798 {"Internal DAC Sink", NULL, "Right DAC"}, 799 800 /* Make ADCs turn on when recording even if not mixed from any inputs */ 801 {"Left ADC", NULL, "Internal ADC Source"}, 802 {"Right ADC", NULL, "Internal ADC Source"}, 803 804 /* Input Side */ 805 /* LIN12 PGA */ 806 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 807 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 808 /* LIN34 PGA */ 809 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 810 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 811 /* INMIXL */ 812 {"INMIXL", "Record Left Volume", "LOMIX"}, 813 {"INMIXL", "LIN2 Volume", "LIN2"}, 814 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 815 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 816 /* AINLMUX */ 817 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 818 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 819 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 820 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 821 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 822 /* ADC */ 823 {"Left ADC", NULL, "AINLMUX"}, 824 825 /* RIN12 PGA */ 826 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 827 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 828 /* RIN34 PGA */ 829 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 830 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 831 /* INMIXL */ 832 {"INMIXR", "Record Right Volume", "ROMIX"}, 833 {"INMIXR", "RIN2 Volume", "RIN2"}, 834 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 835 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 836 /* AINRMUX */ 837 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 838 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 839 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 840 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 841 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 842 /* ADC */ 843 {"Right ADC", NULL, "AINRMUX"}, 844 845 /* LOMIX */ 846 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 847 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 848 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 849 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 850 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 851 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 852 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 853 854 /* ROMIX */ 855 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 856 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 857 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 858 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 859 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 860 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 861 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 862 863 /* SPKMIX */ 864 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 865 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 866 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 867 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 868 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 869 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 870 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 871 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 872 873 /* LONMIX */ 874 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 875 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 876 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 877 878 /* LOPMIX */ 879 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 880 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 881 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 882 883 /* OUT3MIX */ 884 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 885 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 886 887 /* OUT4MIX */ 888 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 889 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 890 891 /* RONMIX */ 892 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 893 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 894 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 895 896 /* ROPMIX */ 897 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 898 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 899 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 900 901 /* Out Mixer PGAs */ 902 {"LOPGA", NULL, "LOMIX"}, 903 {"ROPGA", NULL, "ROMIX"}, 904 905 {"LOUT PGA", NULL, "LOMIX"}, 906 {"ROUT PGA", NULL, "ROMIX"}, 907 908 /* Output Pins */ 909 {"LON", NULL, "LONMIX"}, 910 {"LOP", NULL, "LOPMIX"}, 911 {"OUT3", NULL, "OUT3MIX"}, 912 {"LOUT", NULL, "LOUT PGA"}, 913 {"SPKN", NULL, "SPKMIX"}, 914 {"ROUT", NULL, "ROUT PGA"}, 915 {"OUT4", NULL, "OUT4MIX"}, 916 {"ROP", NULL, "ROPMIX"}, 917 {"RON", NULL, "RONMIX"}, 918 }; 919 920 static int wm8990_add_widgets(struct snd_soc_codec *codec) 921 { 922 struct snd_soc_dapm_context *dapm = &codec->dapm; 923 924 snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets, 925 ARRAY_SIZE(wm8990_dapm_widgets)); 926 /* set up the WM8990 audio map */ 927 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 928 929 return 0; 930 } 931 932 /* PLL divisors */ 933 struct _pll_div { 934 u32 div2; 935 u32 n; 936 u32 k; 937 }; 938 939 /* The size in bits of the pll divide multiplied by 10 940 * to allow rounding later */ 941 #define FIXED_PLL_SIZE ((1 << 16) * 10) 942 943 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 944 unsigned int source) 945 { 946 u64 Kpart; 947 unsigned int K, Ndiv, Nmod; 948 949 950 Ndiv = target / source; 951 if (Ndiv < 6) { 952 source >>= 1; 953 pll_div->div2 = 1; 954 Ndiv = target / source; 955 } else 956 pll_div->div2 = 0; 957 958 if ((Ndiv < 6) || (Ndiv > 12)) 959 printk(KERN_WARNING 960 "WM8990 N value outwith recommended range! N = %u\n", Ndiv); 961 962 pll_div->n = Ndiv; 963 Nmod = target % source; 964 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 965 966 do_div(Kpart, source); 967 968 K = Kpart & 0xFFFFFFFF; 969 970 /* Check if we need to round */ 971 if ((K % 10) >= 5) 972 K += 5; 973 974 /* Move down to proper range now rounding is done */ 975 K /= 10; 976 977 pll_div->k = K; 978 } 979 980 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 981 int source, unsigned int freq_in, unsigned int freq_out) 982 { 983 struct snd_soc_codec *codec = codec_dai->codec; 984 struct _pll_div pll_div; 985 986 if (freq_in && freq_out) { 987 pll_factors(&pll_div, freq_out * 4, freq_in); 988 989 /* Turn on PLL */ 990 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 991 WM8990_PLL_ENA, WM8990_PLL_ENA); 992 993 /* sysclk comes from PLL */ 994 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 995 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC); 996 997 /* set up N , fractional mode and pre-divisor if necessary */ 998 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 999 (pll_div.div2?WM8990_PRESCALE:0)); 1000 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 1001 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 1002 } else { 1003 /* Turn off PLL */ 1004 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 1005 WM8990_PLL_ENA, 0); 1006 } 1007 return 0; 1008 } 1009 1010 /* 1011 * Clock after PLL and dividers 1012 */ 1013 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1014 int clk_id, unsigned int freq, int dir) 1015 { 1016 struct snd_soc_codec *codec = codec_dai->codec; 1017 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1018 1019 wm8990->sysclk = freq; 1020 return 0; 1021 } 1022 1023 /* 1024 * Set's ADC and Voice DAC format. 1025 */ 1026 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1027 unsigned int fmt) 1028 { 1029 struct snd_soc_codec *codec = codec_dai->codec; 1030 u16 audio1, audio3; 1031 1032 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1033 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3); 1034 1035 /* set master/slave audio interface */ 1036 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1037 case SND_SOC_DAIFMT_CBS_CFS: 1038 audio3 &= ~WM8990_AIF_MSTR1; 1039 break; 1040 case SND_SOC_DAIFMT_CBM_CFM: 1041 audio3 |= WM8990_AIF_MSTR1; 1042 break; 1043 default: 1044 return -EINVAL; 1045 } 1046 1047 audio1 &= ~WM8990_AIF_FMT_MASK; 1048 1049 /* interface format */ 1050 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1051 case SND_SOC_DAIFMT_I2S: 1052 audio1 |= WM8990_AIF_TMF_I2S; 1053 audio1 &= ~WM8990_AIF_LRCLK_INV; 1054 break; 1055 case SND_SOC_DAIFMT_RIGHT_J: 1056 audio1 |= WM8990_AIF_TMF_RIGHTJ; 1057 audio1 &= ~WM8990_AIF_LRCLK_INV; 1058 break; 1059 case SND_SOC_DAIFMT_LEFT_J: 1060 audio1 |= WM8990_AIF_TMF_LEFTJ; 1061 audio1 &= ~WM8990_AIF_LRCLK_INV; 1062 break; 1063 case SND_SOC_DAIFMT_DSP_A: 1064 audio1 |= WM8990_AIF_TMF_DSP; 1065 audio1 &= ~WM8990_AIF_LRCLK_INV; 1066 break; 1067 case SND_SOC_DAIFMT_DSP_B: 1068 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1069 break; 1070 default: 1071 return -EINVAL; 1072 } 1073 1074 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1075 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1076 return 0; 1077 } 1078 1079 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1080 int div_id, int div) 1081 { 1082 struct snd_soc_codec *codec = codec_dai->codec; 1083 1084 switch (div_id) { 1085 case WM8990_MCLK_DIV: 1086 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1087 WM8990_MCLK_DIV_MASK, div); 1088 break; 1089 case WM8990_DACCLK_DIV: 1090 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1091 WM8990_DAC_CLKDIV_MASK, div); 1092 break; 1093 case WM8990_ADCCLK_DIV: 1094 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1095 WM8990_ADC_CLKDIV_MASK, div); 1096 break; 1097 case WM8990_BCLK_DIV: 1098 snd_soc_update_bits(codec, WM8990_CLOCKING_1, 1099 WM8990_BCLK_DIV_MASK, div); 1100 break; 1101 default: 1102 return -EINVAL; 1103 } 1104 1105 return 0; 1106 } 1107 1108 /* 1109 * Set PCM DAI bit size and sample rate. 1110 */ 1111 static int wm8990_hw_params(struct snd_pcm_substream *substream, 1112 struct snd_pcm_hw_params *params, 1113 struct snd_soc_dai *dai) 1114 { 1115 struct snd_soc_codec *codec = dai->codec; 1116 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1117 1118 audio1 &= ~WM8990_AIF_WL_MASK; 1119 /* bit size */ 1120 switch (params_format(params)) { 1121 case SNDRV_PCM_FORMAT_S16_LE: 1122 break; 1123 case SNDRV_PCM_FORMAT_S20_3LE: 1124 audio1 |= WM8990_AIF_WL_20BITS; 1125 break; 1126 case SNDRV_PCM_FORMAT_S24_LE: 1127 audio1 |= WM8990_AIF_WL_24BITS; 1128 break; 1129 case SNDRV_PCM_FORMAT_S32_LE: 1130 audio1 |= WM8990_AIF_WL_32BITS; 1131 break; 1132 } 1133 1134 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1135 return 0; 1136 } 1137 1138 static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1139 { 1140 struct snd_soc_codec *codec = dai->codec; 1141 u16 val; 1142 1143 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1144 1145 if (mute) 1146 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1147 else 1148 snd_soc_write(codec, WM8990_DAC_CTRL, val); 1149 1150 return 0; 1151 } 1152 1153 static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1154 enum snd_soc_bias_level level) 1155 { 1156 int ret; 1157 1158 switch (level) { 1159 case SND_SOC_BIAS_ON: 1160 break; 1161 1162 case SND_SOC_BIAS_PREPARE: 1163 /* VMID=2*50k */ 1164 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1, 1165 WM8990_VMID_MODE_MASK, 0x2); 1166 break; 1167 1168 case SND_SOC_BIAS_STANDBY: 1169 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1170 ret = snd_soc_cache_sync(codec); 1171 if (ret < 0) { 1172 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1173 return ret; 1174 } 1175 1176 /* Enable all output discharge bits */ 1177 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1178 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1179 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1180 WM8990_DIS_ROUT); 1181 1182 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1183 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1184 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1185 WM8990_VMIDTOG); 1186 1187 /* Delay to allow output caps to discharge */ 1188 msleep(300); 1189 1190 /* Disable VMIDTOG */ 1191 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1192 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1193 1194 /* disable all output discharge bits */ 1195 snd_soc_write(codec, WM8990_ANTIPOP1, 0); 1196 1197 /* Enable outputs */ 1198 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1199 1200 msleep(50); 1201 1202 /* Enable VMID at 2x50k */ 1203 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1204 1205 msleep(100); 1206 1207 /* Enable VREF */ 1208 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1209 1210 msleep(600); 1211 1212 /* Enable BUFIOEN */ 1213 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1214 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1215 WM8990_BUFIOEN); 1216 1217 /* Disable outputs */ 1218 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1219 1220 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1221 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1222 1223 /* Enable workaround for ADC clocking issue. */ 1224 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1225 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003); 1226 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1227 } 1228 1229 /* VMID=2*250k */ 1230 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1, 1231 WM8990_VMID_MODE_MASK, 0x4); 1232 break; 1233 1234 case SND_SOC_BIAS_OFF: 1235 /* Enable POBCTRL and SOFT_ST */ 1236 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1237 WM8990_POBCTRL | WM8990_BUFIOEN); 1238 1239 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1240 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1241 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1242 WM8990_BUFIOEN); 1243 1244 /* mute DAC */ 1245 snd_soc_update_bits(codec, WM8990_DAC_CTRL, 1246 WM8990_DAC_MUTE, WM8990_DAC_MUTE); 1247 1248 /* Enable any disabled outputs */ 1249 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1250 1251 /* Disable VMID */ 1252 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1253 1254 msleep(300); 1255 1256 /* Enable all output discharge bits */ 1257 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1258 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1259 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1260 WM8990_DIS_ROUT); 1261 1262 /* Disable VREF */ 1263 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1264 1265 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1266 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1267 break; 1268 } 1269 1270 codec->dapm.bias_level = level; 1271 return 0; 1272 } 1273 1274 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1275 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1276 SNDRV_PCM_RATE_48000) 1277 1278 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1279 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1280 1281 /* 1282 * The WM8990 supports 2 different and mutually exclusive DAI 1283 * configurations. 1284 * 1285 * 1. ADC/DAC on Primary Interface 1286 * 2. ADC on Primary Interface/DAC on secondary 1287 */ 1288 static const struct snd_soc_dai_ops wm8990_dai_ops = { 1289 .hw_params = wm8990_hw_params, 1290 .digital_mute = wm8990_mute, 1291 .set_fmt = wm8990_set_dai_fmt, 1292 .set_clkdiv = wm8990_set_dai_clkdiv, 1293 .set_pll = wm8990_set_dai_pll, 1294 .set_sysclk = wm8990_set_dai_sysclk, 1295 }; 1296 1297 static struct snd_soc_dai_driver wm8990_dai = { 1298 /* ADC/DAC on primary */ 1299 .name = "wm8990-hifi", 1300 .playback = { 1301 .stream_name = "Playback", 1302 .channels_min = 1, 1303 .channels_max = 2, 1304 .rates = WM8990_RATES, 1305 .formats = WM8990_FORMATS,}, 1306 .capture = { 1307 .stream_name = "Capture", 1308 .channels_min = 1, 1309 .channels_max = 2, 1310 .rates = WM8990_RATES, 1311 .formats = WM8990_FORMATS,}, 1312 .ops = &wm8990_dai_ops, 1313 }; 1314 1315 static int wm8990_suspend(struct snd_soc_codec *codec) 1316 { 1317 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1318 return 0; 1319 } 1320 1321 static int wm8990_resume(struct snd_soc_codec *codec) 1322 { 1323 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1324 return 0; 1325 } 1326 1327 /* 1328 * initialise the WM8990 driver 1329 * register the mixer and dsp interfaces with the kernel 1330 */ 1331 static int wm8990_probe(struct snd_soc_codec *codec) 1332 { 1333 int ret; 1334 1335 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1336 if (ret < 0) { 1337 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret); 1338 return ret; 1339 } 1340 1341 wm8990_reset(codec); 1342 1343 /* charge output caps */ 1344 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1345 1346 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4, 1347 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1); 1348 1349 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2, 1350 WM8990_GPIO1_SEL_MASK, 1); 1351 1352 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 1353 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA); 1354 1355 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1356 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1357 1358 snd_soc_add_codec_controls(codec, wm8990_snd_controls, 1359 ARRAY_SIZE(wm8990_snd_controls)); 1360 wm8990_add_widgets(codec); 1361 1362 return 0; 1363 } 1364 1365 /* power down chip */ 1366 static int wm8990_remove(struct snd_soc_codec *codec) 1367 { 1368 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1369 return 0; 1370 } 1371 1372 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = { 1373 .probe = wm8990_probe, 1374 .remove = wm8990_remove, 1375 .suspend = wm8990_suspend, 1376 .resume = wm8990_resume, 1377 .set_bias_level = wm8990_set_bias_level, 1378 .reg_cache_size = ARRAY_SIZE(wm8990_reg), 1379 .reg_word_size = sizeof(u16), 1380 .reg_cache_default = wm8990_reg, 1381 .volatile_register = wm8990_volatile_register, 1382 }; 1383 1384 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1385 static int wm8990_i2c_probe(struct i2c_client *i2c, 1386 const struct i2c_device_id *id) 1387 { 1388 struct wm8990_priv *wm8990; 1389 int ret; 1390 1391 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv), 1392 GFP_KERNEL); 1393 if (wm8990 == NULL) 1394 return -ENOMEM; 1395 1396 i2c_set_clientdata(i2c, wm8990); 1397 1398 ret = snd_soc_register_codec(&i2c->dev, 1399 &soc_codec_dev_wm8990, &wm8990_dai, 1); 1400 1401 return ret; 1402 } 1403 1404 static int wm8990_i2c_remove(struct i2c_client *client) 1405 { 1406 snd_soc_unregister_codec(&client->dev); 1407 1408 return 0; 1409 } 1410 1411 static const struct i2c_device_id wm8990_i2c_id[] = { 1412 { "wm8990", 0 }, 1413 { } 1414 }; 1415 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1416 1417 static struct i2c_driver wm8990_i2c_driver = { 1418 .driver = { 1419 .name = "wm8990", 1420 .owner = THIS_MODULE, 1421 }, 1422 .probe = wm8990_i2c_probe, 1423 .remove = wm8990_i2c_remove, 1424 .id_table = wm8990_i2c_id, 1425 }; 1426 #endif 1427 1428 static int __init wm8990_modinit(void) 1429 { 1430 int ret = 0; 1431 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1432 ret = i2c_add_driver(&wm8990_i2c_driver); 1433 if (ret != 0) { 1434 printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n", 1435 ret); 1436 } 1437 #endif 1438 return ret; 1439 } 1440 module_init(wm8990_modinit); 1441 1442 static void __exit wm8990_exit(void) 1443 { 1444 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1445 i2c_del_driver(&wm8990_i2c_driver); 1446 #endif 1447 } 1448 module_exit(wm8990_exit); 1449 1450 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1451 MODULE_AUTHOR("Liam Girdwood"); 1452 MODULE_LICENSE("GPL"); 1453