1 /* 2 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <asm/div64.h> 29 30 #include "wm8990.h" 31 32 /* codec private data */ 33 struct wm8990_priv { 34 struct regmap *regmap; 35 unsigned int sysclk; 36 unsigned int pcmclk; 37 }; 38 39 static bool wm8990_volatile_register(struct device *dev, unsigned int reg) 40 { 41 switch (reg) { 42 case WM8990_RESET: 43 return 1; 44 default: 45 return 0; 46 } 47 } 48 49 static const struct reg_default wm8990_reg_defaults[] = { 50 { 1, 0x0000 }, /* R1 - Power Management (1) */ 51 { 2, 0x6000 }, /* R2 - Power Management (2) */ 52 { 3, 0x0000 }, /* R3 - Power Management (3) */ 53 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 54 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 55 { 6, 0x01C8 }, /* R6 - Clocking (1) */ 56 { 7, 0x0000 }, /* R7 - Clocking (2) */ 57 { 8, 0x0040 }, /* R8 - Audio Interface (3) */ 58 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 59 { 10, 0x0004 }, /* R10 - DAC CTRL */ 60 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 61 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 62 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 63 { 14, 0x0100 }, /* R14 - ADC CTRL */ 64 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 65 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 66 67 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 68 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */ 69 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */ 70 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */ 71 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 72 { 23, 0x0800 }, /* R23 - GPIO_POL */ 73 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 74 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 75 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 76 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 77 { 28, 0x0000 }, /* R28 - Left Output Volume */ 78 { 29, 0x0000 }, /* R29 - Right Output Volume */ 79 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 80 { 31, 0x0022 }, /* R31 - Out3/4 Volume */ 81 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 82 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 83 { 34, 0x0003 }, /* R34 - Speaker Volume */ 84 { 35, 0x0003 }, /* R35 - ClassD1 */ 85 86 { 37, 0x0100 }, /* R37 - ClassD3 */ 87 { 38, 0x0079 }, /* R38 - ClassD4 */ 88 { 39, 0x0000 }, /* R39 - Input Mixer1 */ 89 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 90 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 91 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 92 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 93 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 94 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 95 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 96 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 97 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 98 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 99 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 100 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */ 101 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 102 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 103 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 104 { 55, 0x0000 }, /* R55 - Additional Control */ 105 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 106 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 107 { 58, 0x0000 }, /* R58 - MICBIAS */ 108 109 { 60, 0x0008 }, /* R60 - PLL1 */ 110 { 61, 0x0031 }, /* R61 - PLL2 */ 111 { 62, 0x0026 }, /* R62 - PLL3 */ 112 }; 113 114 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0) 115 116 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 117 118 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 119 120 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0); 121 122 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 123 124 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 125 126 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 127 128 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 129 130 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 131 132 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 133 struct snd_ctl_elem_value *ucontrol) 134 { 135 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 136 struct soc_mixer_control *mc = 137 (struct soc_mixer_control *)kcontrol->private_value; 138 int reg = mc->reg; 139 int ret; 140 u16 val; 141 142 ret = snd_soc_put_volsw(kcontrol, ucontrol); 143 if (ret < 0) 144 return ret; 145 146 /* now hit the volume update bits (always bit 8) */ 147 val = snd_soc_read(codec, reg); 148 return snd_soc_write(codec, reg, val | 0x0100); 149 } 150 151 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 152 tlv_array) \ 153 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ 154 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array) 155 156 157 static const char *wm8990_digital_sidetone[] = 158 {"None", "Left ADC", "Right ADC", "Reserved"}; 159 160 static const struct soc_enum wm8990_left_digital_sidetone_enum = 161 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 162 WM8990_ADC_TO_DACL_SHIFT, 163 WM8990_ADC_TO_DACL_MASK, 164 wm8990_digital_sidetone); 165 166 static const struct soc_enum wm8990_right_digital_sidetone_enum = 167 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 168 WM8990_ADC_TO_DACR_SHIFT, 169 WM8990_ADC_TO_DACR_MASK, 170 wm8990_digital_sidetone); 171 172 static const char *wm8990_adcmode[] = 173 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 174 175 static const struct soc_enum wm8990_right_adcmode_enum = 176 SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 177 WM8990_ADC_HPF_CUT_SHIFT, 178 WM8990_ADC_HPF_CUT_MASK, 179 wm8990_adcmode); 180 181 static const struct snd_kcontrol_new wm8990_snd_controls[] = { 182 /* INMIXL */ 183 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 184 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 185 /* INMIXR */ 186 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 187 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 188 189 /* LOMIX */ 190 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 191 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 192 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 193 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 194 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 195 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 196 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 197 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 198 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 199 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 200 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 201 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 202 203 /* ROMIX */ 204 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 205 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 206 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 207 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 208 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 209 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 210 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 211 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 212 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 213 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 214 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 215 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 216 217 /* LOUT */ 218 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 219 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 220 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 221 222 /* ROUT */ 223 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 224 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 225 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 226 227 /* LOPGA */ 228 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 229 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 230 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 231 WM8990_LOPGAZC_BIT, 1, 0), 232 233 /* ROPGA */ 234 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 235 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 236 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 237 WM8990_ROPGAZC_BIT, 1, 0), 238 239 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 240 WM8990_LONMUTE_BIT, 1, 0), 241 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 242 WM8990_LOPMUTE_BIT, 1, 0), 243 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 244 WM8990_LOATTN_BIT, 1, 0), 245 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 246 WM8990_RONMUTE_BIT, 1, 0), 247 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 248 WM8990_ROPMUTE_BIT, 1, 0), 249 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 250 WM8990_ROATTN_BIT, 1, 0), 251 252 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 253 WM8990_OUT3MUTE_BIT, 1, 0), 254 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 255 WM8990_OUT3ATTN_BIT, 1, 0), 256 257 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 258 WM8990_OUT4MUTE_BIT, 1, 0), 259 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 260 WM8990_OUT4ATTN_BIT, 1, 0), 261 262 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 263 WM8990_CDMODE_BIT, 1, 0), 264 265 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 266 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 267 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 268 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 269 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 270 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 271 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 272 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 273 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 274 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 275 276 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 277 WM8990_LEFT_DAC_DIGITAL_VOLUME, 278 WM8990_DACL_VOL_SHIFT, 279 WM8990_DACL_VOL_MASK, 280 0, 281 out_dac_tlv), 282 283 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 284 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 285 WM8990_DACR_VOL_SHIFT, 286 WM8990_DACR_VOL_MASK, 287 0, 288 out_dac_tlv), 289 290 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 291 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 292 293 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 294 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 295 out_sidetone_tlv), 296 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 297 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 298 out_sidetone_tlv), 299 300 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 301 WM8990_ADC_HPF_ENA_BIT, 1, 0), 302 303 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 304 305 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 306 WM8990_LEFT_ADC_DIGITAL_VOLUME, 307 WM8990_ADCL_VOL_SHIFT, 308 WM8990_ADCL_VOL_MASK, 309 0, 310 in_adc_tlv), 311 312 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 313 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 314 WM8990_ADCR_VOL_SHIFT, 315 WM8990_ADCR_VOL_MASK, 316 0, 317 in_adc_tlv), 318 319 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 320 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 321 WM8990_LIN12VOL_SHIFT, 322 WM8990_LIN12VOL_MASK, 323 0, 324 in_pga_tlv), 325 326 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 327 WM8990_LI12ZC_BIT, 1, 0), 328 329 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 330 WM8990_LI12MUTE_BIT, 1, 0), 331 332 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 333 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 334 WM8990_LIN34VOL_SHIFT, 335 WM8990_LIN34VOL_MASK, 336 0, 337 in_pga_tlv), 338 339 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 340 WM8990_LI34ZC_BIT, 1, 0), 341 342 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 343 WM8990_LI34MUTE_BIT, 1, 0), 344 345 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 346 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 347 WM8990_RIN12VOL_SHIFT, 348 WM8990_RIN12VOL_MASK, 349 0, 350 in_pga_tlv), 351 352 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 353 WM8990_RI12ZC_BIT, 1, 0), 354 355 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 356 WM8990_RI12MUTE_BIT, 1, 0), 357 358 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 359 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 360 WM8990_RIN34VOL_SHIFT, 361 WM8990_RIN34VOL_MASK, 362 0, 363 in_pga_tlv), 364 365 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 366 WM8990_RI34ZC_BIT, 1, 0), 367 368 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 369 WM8990_RI34MUTE_BIT, 1, 0), 370 371 }; 372 373 /* 374 * _DAPM_ Controls 375 */ 376 377 static int outmixer_event(struct snd_soc_dapm_widget *w, 378 struct snd_kcontrol *kcontrol, int event) 379 { 380 u32 reg_shift = kcontrol->private_value & 0xfff; 381 int ret = 0; 382 u16 reg; 383 384 switch (reg_shift) { 385 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 386 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1); 387 if (reg & WM8990_LDLO) { 388 printk(KERN_WARNING 389 "Cannot set as Output Mixer 1 LDLO Set\n"); 390 ret = -1; 391 } 392 break; 393 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 394 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2); 395 if (reg & WM8990_RDRO) { 396 printk(KERN_WARNING 397 "Cannot set as Output Mixer 2 RDRO Set\n"); 398 ret = -1; 399 } 400 break; 401 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 402 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 403 if (reg & WM8990_LDSPK) { 404 printk(KERN_WARNING 405 "Cannot set as Speaker Mixer LDSPK Set\n"); 406 ret = -1; 407 } 408 break; 409 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 410 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 411 if (reg & WM8990_RDSPK) { 412 printk(KERN_WARNING 413 "Cannot set as Speaker Mixer RDSPK Set\n"); 414 ret = -1; 415 } 416 break; 417 } 418 419 return ret; 420 } 421 422 /* INMIX dB values */ 423 static const unsigned int in_mix_tlv[] = { 424 TLV_DB_RANGE_HEAD(1), 425 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 426 }; 427 428 /* Left In PGA Connections */ 429 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 430 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 431 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 432 }; 433 434 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 435 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 436 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 437 }; 438 439 /* Right In PGA Connections */ 440 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 441 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 442 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 443 }; 444 445 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 446 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 447 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 448 }; 449 450 /* INMIXL */ 451 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 452 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 453 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 454 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 455 7, 0, in_mix_tlv), 456 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 457 1, 0), 458 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 459 1, 0), 460 }; 461 462 /* INMIXR */ 463 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 464 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 465 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 466 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 467 7, 0, in_mix_tlv), 468 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 469 1, 0), 470 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 471 1, 0), 472 }; 473 474 /* AINLMUX */ 475 static const char *wm8990_ainlmux[] = 476 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 477 478 static const struct soc_enum wm8990_ainlmux_enum = 479 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 480 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 481 482 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 483 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 484 485 /* DIFFINL */ 486 487 /* AINRMUX */ 488 static const char *wm8990_ainrmux[] = 489 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 490 491 static const struct soc_enum wm8990_ainrmux_enum = 492 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 493 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 494 495 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 496 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 497 498 /* RXVOICE */ 499 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 500 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 501 WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 502 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 503 WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 504 }; 505 506 /* LOMIX */ 507 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 508 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 509 WM8990_LRBLO_BIT, 1, 0), 510 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 511 WM8990_LLBLO_BIT, 1, 0), 512 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 513 WM8990_LRI3LO_BIT, 1, 0), 514 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 515 WM8990_LLI3LO_BIT, 1, 0), 516 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 517 WM8990_LR12LO_BIT, 1, 0), 518 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 519 WM8990_LL12LO_BIT, 1, 0), 520 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 521 WM8990_LDLO_BIT, 1, 0), 522 }; 523 524 /* ROMIX */ 525 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 526 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 527 WM8990_RLBRO_BIT, 1, 0), 528 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 529 WM8990_RRBRO_BIT, 1, 0), 530 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 531 WM8990_RLI3RO_BIT, 1, 0), 532 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 533 WM8990_RRI3RO_BIT, 1, 0), 534 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 535 WM8990_RL12RO_BIT, 1, 0), 536 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 537 WM8990_RR12RO_BIT, 1, 0), 538 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 539 WM8990_RDRO_BIT, 1, 0), 540 }; 541 542 /* LONMIX */ 543 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 544 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 545 WM8990_LLOPGALON_BIT, 1, 0), 546 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 547 WM8990_LROPGALON_BIT, 1, 0), 548 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 549 WM8990_LOPLON_BIT, 1, 0), 550 }; 551 552 /* LOPMIX */ 553 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 554 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 555 WM8990_LR12LOP_BIT, 1, 0), 556 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 557 WM8990_LL12LOP_BIT, 1, 0), 558 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 559 WM8990_LLOPGALOP_BIT, 1, 0), 560 }; 561 562 /* RONMIX */ 563 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 564 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 565 WM8990_RROPGARON_BIT, 1, 0), 566 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 567 WM8990_RLOPGARON_BIT, 1, 0), 568 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 569 WM8990_ROPRON_BIT, 1, 0), 570 }; 571 572 /* ROPMIX */ 573 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 574 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 575 WM8990_RL12ROP_BIT, 1, 0), 576 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 577 WM8990_RR12ROP_BIT, 1, 0), 578 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 579 WM8990_RROPGAROP_BIT, 1, 0), 580 }; 581 582 /* OUT3MIX */ 583 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 584 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 585 WM8990_LI4O3_BIT, 1, 0), 586 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 587 WM8990_LPGAO3_BIT, 1, 0), 588 }; 589 590 /* OUT4MIX */ 591 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 592 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 593 WM8990_RPGAO4_BIT, 1, 0), 594 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 595 WM8990_RI4O4_BIT, 1, 0), 596 }; 597 598 /* SPKMIX */ 599 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 600 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 601 WM8990_LI2SPK_BIT, 1, 0), 602 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 603 WM8990_LB2SPK_BIT, 1, 0), 604 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 605 WM8990_LOPGASPK_BIT, 1, 0), 606 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 607 WM8990_LDSPK_BIT, 1, 0), 608 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 609 WM8990_RDSPK_BIT, 1, 0), 610 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 611 WM8990_ROPGASPK_BIT, 1, 0), 612 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 613 WM8990_RL12ROP_BIT, 1, 0), 614 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 615 WM8990_RI2SPK_BIT, 1, 0), 616 }; 617 618 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 619 /* Input Side */ 620 /* Input Lines */ 621 SND_SOC_DAPM_INPUT("LIN1"), 622 SND_SOC_DAPM_INPUT("LIN2"), 623 SND_SOC_DAPM_INPUT("LIN3"), 624 SND_SOC_DAPM_INPUT("LIN4/RXN"), 625 SND_SOC_DAPM_INPUT("RIN3"), 626 SND_SOC_DAPM_INPUT("RIN4/RXP"), 627 SND_SOC_DAPM_INPUT("RIN1"), 628 SND_SOC_DAPM_INPUT("RIN2"), 629 SND_SOC_DAPM_INPUT("Internal ADC Source"), 630 631 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0, 632 NULL, 0), 633 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0, 634 NULL, 0), 635 636 /* DACs */ 637 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 638 WM8990_ADCL_ENA_BIT, 0), 639 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 640 WM8990_ADCR_ENA_BIT, 0), 641 642 /* Input PGAs */ 643 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 644 0, &wm8990_dapm_lin12_pga_controls[0], 645 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 646 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 647 0, &wm8990_dapm_lin34_pga_controls[0], 648 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 649 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 650 0, &wm8990_dapm_rin12_pga_controls[0], 651 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 652 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 653 0, &wm8990_dapm_rin34_pga_controls[0], 654 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 655 656 /* INMIXL */ 657 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, 658 &wm8990_dapm_inmixl_controls[0], 659 ARRAY_SIZE(wm8990_dapm_inmixl_controls)), 660 661 /* AINLMUX */ 662 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls), 663 664 /* INMIXR */ 665 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, 666 &wm8990_dapm_inmixr_controls[0], 667 ARRAY_SIZE(wm8990_dapm_inmixr_controls)), 668 669 /* AINRMUX */ 670 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls), 671 672 /* Output Side */ 673 /* DACs */ 674 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 675 WM8990_DACL_ENA_BIT, 0), 676 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 677 WM8990_DACR_ENA_BIT, 0), 678 679 /* LOMIX */ 680 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 681 0, &wm8990_dapm_lomix_controls[0], 682 ARRAY_SIZE(wm8990_dapm_lomix_controls), 683 outmixer_event, SND_SOC_DAPM_PRE_REG), 684 685 /* LONMIX */ 686 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 687 &wm8990_dapm_lonmix_controls[0], 688 ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 689 690 /* LOPMIX */ 691 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 692 &wm8990_dapm_lopmix_controls[0], 693 ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 694 695 /* OUT3MIX */ 696 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 697 &wm8990_dapm_out3mix_controls[0], 698 ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 699 700 /* SPKMIX */ 701 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 702 &wm8990_dapm_spkmix_controls[0], 703 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 704 SND_SOC_DAPM_PRE_REG), 705 706 /* OUT4MIX */ 707 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 708 &wm8990_dapm_out4mix_controls[0], 709 ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 710 711 /* ROPMIX */ 712 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 713 &wm8990_dapm_ropmix_controls[0], 714 ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 715 716 /* RONMIX */ 717 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 718 &wm8990_dapm_ronmix_controls[0], 719 ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 720 721 /* ROMIX */ 722 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 723 0, &wm8990_dapm_romix_controls[0], 724 ARRAY_SIZE(wm8990_dapm_romix_controls), 725 outmixer_event, SND_SOC_DAPM_PRE_REG), 726 727 /* LOUT PGA */ 728 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 729 NULL, 0), 730 731 /* ROUT PGA */ 732 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 733 NULL, 0), 734 735 /* LOPGA */ 736 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 737 NULL, 0), 738 739 /* ROPGA */ 740 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 741 NULL, 0), 742 743 /* MICBIAS */ 744 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1, 745 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0), 746 747 SND_SOC_DAPM_OUTPUT("LON"), 748 SND_SOC_DAPM_OUTPUT("LOP"), 749 SND_SOC_DAPM_OUTPUT("OUT3"), 750 SND_SOC_DAPM_OUTPUT("LOUT"), 751 SND_SOC_DAPM_OUTPUT("SPKN"), 752 SND_SOC_DAPM_OUTPUT("SPKP"), 753 SND_SOC_DAPM_OUTPUT("ROUT"), 754 SND_SOC_DAPM_OUTPUT("OUT4"), 755 SND_SOC_DAPM_OUTPUT("ROP"), 756 SND_SOC_DAPM_OUTPUT("RON"), 757 758 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 759 }; 760 761 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = { 762 /* Make DACs turn on when playing even if not mixed into any outputs */ 763 {"Internal DAC Sink", NULL, "Left DAC"}, 764 {"Internal DAC Sink", NULL, "Right DAC"}, 765 766 /* Make ADCs turn on when recording even if not mixed from any inputs */ 767 {"Left ADC", NULL, "Internal ADC Source"}, 768 {"Right ADC", NULL, "Internal ADC Source"}, 769 770 {"AINLMUX", NULL, "INL"}, 771 {"INMIXL", NULL, "INL"}, 772 {"AINRMUX", NULL, "INR"}, 773 {"INMIXR", NULL, "INR"}, 774 775 /* Input Side */ 776 /* LIN12 PGA */ 777 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 778 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 779 /* LIN34 PGA */ 780 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 781 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 782 /* INMIXL */ 783 {"INMIXL", "Record Left Volume", "LOMIX"}, 784 {"INMIXL", "LIN2 Volume", "LIN2"}, 785 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 786 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 787 /* AINLMUX */ 788 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 789 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 790 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 791 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 792 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 793 /* ADC */ 794 {"Left ADC", NULL, "AINLMUX"}, 795 796 /* RIN12 PGA */ 797 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 798 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 799 /* RIN34 PGA */ 800 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 801 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 802 /* INMIXL */ 803 {"INMIXR", "Record Right Volume", "ROMIX"}, 804 {"INMIXR", "RIN2 Volume", "RIN2"}, 805 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 806 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 807 /* AINRMUX */ 808 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 809 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 810 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 811 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 812 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 813 /* ADC */ 814 {"Right ADC", NULL, "AINRMUX"}, 815 816 /* LOMIX */ 817 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 818 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 819 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 820 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 821 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 822 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 823 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 824 825 /* ROMIX */ 826 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 827 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 828 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 829 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 830 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 831 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 832 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 833 834 /* SPKMIX */ 835 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 836 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 837 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 838 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 839 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 840 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 841 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 842 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 843 844 /* LONMIX */ 845 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 846 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 847 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 848 849 /* LOPMIX */ 850 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 851 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 852 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 853 854 /* OUT3MIX */ 855 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 856 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 857 858 /* OUT4MIX */ 859 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 860 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 861 862 /* RONMIX */ 863 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 864 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 865 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 866 867 /* ROPMIX */ 868 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 869 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 870 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 871 872 /* Out Mixer PGAs */ 873 {"LOPGA", NULL, "LOMIX"}, 874 {"ROPGA", NULL, "ROMIX"}, 875 876 {"LOUT PGA", NULL, "LOMIX"}, 877 {"ROUT PGA", NULL, "ROMIX"}, 878 879 /* Output Pins */ 880 {"LON", NULL, "LONMIX"}, 881 {"LOP", NULL, "LOPMIX"}, 882 {"OUT3", NULL, "OUT3MIX"}, 883 {"LOUT", NULL, "LOUT PGA"}, 884 {"SPKN", NULL, "SPKMIX"}, 885 {"ROUT", NULL, "ROUT PGA"}, 886 {"OUT4", NULL, "OUT4MIX"}, 887 {"ROP", NULL, "ROPMIX"}, 888 {"RON", NULL, "RONMIX"}, 889 }; 890 891 /* PLL divisors */ 892 struct _pll_div { 893 u32 div2; 894 u32 n; 895 u32 k; 896 }; 897 898 /* The size in bits of the pll divide multiplied by 10 899 * to allow rounding later */ 900 #define FIXED_PLL_SIZE ((1 << 16) * 10) 901 902 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 903 unsigned int source) 904 { 905 u64 Kpart; 906 unsigned int K, Ndiv, Nmod; 907 908 909 Ndiv = target / source; 910 if (Ndiv < 6) { 911 source >>= 1; 912 pll_div->div2 = 1; 913 Ndiv = target / source; 914 } else 915 pll_div->div2 = 0; 916 917 if ((Ndiv < 6) || (Ndiv > 12)) 918 printk(KERN_WARNING 919 "WM8990 N value outwith recommended range! N = %u\n", Ndiv); 920 921 pll_div->n = Ndiv; 922 Nmod = target % source; 923 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 924 925 do_div(Kpart, source); 926 927 K = Kpart & 0xFFFFFFFF; 928 929 /* Check if we need to round */ 930 if ((K % 10) >= 5) 931 K += 5; 932 933 /* Move down to proper range now rounding is done */ 934 K /= 10; 935 936 pll_div->k = K; 937 } 938 939 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 940 int source, unsigned int freq_in, unsigned int freq_out) 941 { 942 struct snd_soc_codec *codec = codec_dai->codec; 943 struct _pll_div pll_div; 944 945 if (freq_in && freq_out) { 946 pll_factors(&pll_div, freq_out * 4, freq_in); 947 948 /* Turn on PLL */ 949 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 950 WM8990_PLL_ENA, WM8990_PLL_ENA); 951 952 /* sysclk comes from PLL */ 953 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 954 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC); 955 956 /* set up N , fractional mode and pre-divisor if necessary */ 957 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 958 (pll_div.div2?WM8990_PRESCALE:0)); 959 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 960 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 961 } else { 962 /* Turn off PLL */ 963 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 964 WM8990_PLL_ENA, 0); 965 } 966 return 0; 967 } 968 969 /* 970 * Clock after PLL and dividers 971 */ 972 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 973 int clk_id, unsigned int freq, int dir) 974 { 975 struct snd_soc_codec *codec = codec_dai->codec; 976 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 977 978 wm8990->sysclk = freq; 979 return 0; 980 } 981 982 /* 983 * Set's ADC and Voice DAC format. 984 */ 985 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 986 unsigned int fmt) 987 { 988 struct snd_soc_codec *codec = codec_dai->codec; 989 u16 audio1, audio3; 990 991 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 992 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3); 993 994 /* set master/slave audio interface */ 995 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 996 case SND_SOC_DAIFMT_CBS_CFS: 997 audio3 &= ~WM8990_AIF_MSTR1; 998 break; 999 case SND_SOC_DAIFMT_CBM_CFM: 1000 audio3 |= WM8990_AIF_MSTR1; 1001 break; 1002 default: 1003 return -EINVAL; 1004 } 1005 1006 audio1 &= ~WM8990_AIF_FMT_MASK; 1007 1008 /* interface format */ 1009 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1010 case SND_SOC_DAIFMT_I2S: 1011 audio1 |= WM8990_AIF_TMF_I2S; 1012 audio1 &= ~WM8990_AIF_LRCLK_INV; 1013 break; 1014 case SND_SOC_DAIFMT_RIGHT_J: 1015 audio1 |= WM8990_AIF_TMF_RIGHTJ; 1016 audio1 &= ~WM8990_AIF_LRCLK_INV; 1017 break; 1018 case SND_SOC_DAIFMT_LEFT_J: 1019 audio1 |= WM8990_AIF_TMF_LEFTJ; 1020 audio1 &= ~WM8990_AIF_LRCLK_INV; 1021 break; 1022 case SND_SOC_DAIFMT_DSP_A: 1023 audio1 |= WM8990_AIF_TMF_DSP; 1024 audio1 &= ~WM8990_AIF_LRCLK_INV; 1025 break; 1026 case SND_SOC_DAIFMT_DSP_B: 1027 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1028 break; 1029 default: 1030 return -EINVAL; 1031 } 1032 1033 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1034 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1035 return 0; 1036 } 1037 1038 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1039 int div_id, int div) 1040 { 1041 struct snd_soc_codec *codec = codec_dai->codec; 1042 1043 switch (div_id) { 1044 case WM8990_MCLK_DIV: 1045 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1046 WM8990_MCLK_DIV_MASK, div); 1047 break; 1048 case WM8990_DACCLK_DIV: 1049 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1050 WM8990_DAC_CLKDIV_MASK, div); 1051 break; 1052 case WM8990_ADCCLK_DIV: 1053 snd_soc_update_bits(codec, WM8990_CLOCKING_2, 1054 WM8990_ADC_CLKDIV_MASK, div); 1055 break; 1056 case WM8990_BCLK_DIV: 1057 snd_soc_update_bits(codec, WM8990_CLOCKING_1, 1058 WM8990_BCLK_DIV_MASK, div); 1059 break; 1060 default: 1061 return -EINVAL; 1062 } 1063 1064 return 0; 1065 } 1066 1067 /* 1068 * Set PCM DAI bit size and sample rate. 1069 */ 1070 static int wm8990_hw_params(struct snd_pcm_substream *substream, 1071 struct snd_pcm_hw_params *params, 1072 struct snd_soc_dai *dai) 1073 { 1074 struct snd_soc_codec *codec = dai->codec; 1075 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1076 1077 audio1 &= ~WM8990_AIF_WL_MASK; 1078 /* bit size */ 1079 switch (params_format(params)) { 1080 case SNDRV_PCM_FORMAT_S16_LE: 1081 break; 1082 case SNDRV_PCM_FORMAT_S20_3LE: 1083 audio1 |= WM8990_AIF_WL_20BITS; 1084 break; 1085 case SNDRV_PCM_FORMAT_S24_LE: 1086 audio1 |= WM8990_AIF_WL_24BITS; 1087 break; 1088 case SNDRV_PCM_FORMAT_S32_LE: 1089 audio1 |= WM8990_AIF_WL_32BITS; 1090 break; 1091 } 1092 1093 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1094 return 0; 1095 } 1096 1097 static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1098 { 1099 struct snd_soc_codec *codec = dai->codec; 1100 u16 val; 1101 1102 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1103 1104 if (mute) 1105 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1106 else 1107 snd_soc_write(codec, WM8990_DAC_CTRL, val); 1108 1109 return 0; 1110 } 1111 1112 static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1113 enum snd_soc_bias_level level) 1114 { 1115 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1116 int ret; 1117 1118 switch (level) { 1119 case SND_SOC_BIAS_ON: 1120 break; 1121 1122 case SND_SOC_BIAS_PREPARE: 1123 /* VMID=2*50k */ 1124 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1, 1125 WM8990_VMID_MODE_MASK, 0x2); 1126 break; 1127 1128 case SND_SOC_BIAS_STANDBY: 1129 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1130 ret = regcache_sync(wm8990->regmap); 1131 if (ret < 0) { 1132 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1133 return ret; 1134 } 1135 1136 /* Enable all output discharge bits */ 1137 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1138 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1139 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1140 WM8990_DIS_ROUT); 1141 1142 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1143 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1144 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1145 WM8990_VMIDTOG); 1146 1147 /* Delay to allow output caps to discharge */ 1148 msleep(300); 1149 1150 /* Disable VMIDTOG */ 1151 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1152 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1153 1154 /* disable all output discharge bits */ 1155 snd_soc_write(codec, WM8990_ANTIPOP1, 0); 1156 1157 /* Enable outputs */ 1158 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1159 1160 msleep(50); 1161 1162 /* Enable VMID at 2x50k */ 1163 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1164 1165 msleep(100); 1166 1167 /* Enable VREF */ 1168 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1169 1170 msleep(600); 1171 1172 /* Enable BUFIOEN */ 1173 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1174 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1175 WM8990_BUFIOEN); 1176 1177 /* Disable outputs */ 1178 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1179 1180 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1181 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1182 1183 /* Enable workaround for ADC clocking issue. */ 1184 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1185 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003); 1186 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1187 } 1188 1189 /* VMID=2*250k */ 1190 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1, 1191 WM8990_VMID_MODE_MASK, 0x4); 1192 break; 1193 1194 case SND_SOC_BIAS_OFF: 1195 /* Enable POBCTRL and SOFT_ST */ 1196 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1197 WM8990_POBCTRL | WM8990_BUFIOEN); 1198 1199 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1200 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1201 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1202 WM8990_BUFIOEN); 1203 1204 /* mute DAC */ 1205 snd_soc_update_bits(codec, WM8990_DAC_CTRL, 1206 WM8990_DAC_MUTE, WM8990_DAC_MUTE); 1207 1208 /* Enable any disabled outputs */ 1209 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1210 1211 /* Disable VMID */ 1212 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1213 1214 msleep(300); 1215 1216 /* Enable all output discharge bits */ 1217 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1218 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1219 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1220 WM8990_DIS_ROUT); 1221 1222 /* Disable VREF */ 1223 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1224 1225 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1226 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1227 1228 regcache_mark_dirty(wm8990->regmap); 1229 break; 1230 } 1231 1232 codec->dapm.bias_level = level; 1233 return 0; 1234 } 1235 1236 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1237 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1238 SNDRV_PCM_RATE_48000) 1239 1240 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1241 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1242 1243 /* 1244 * The WM8990 supports 2 different and mutually exclusive DAI 1245 * configurations. 1246 * 1247 * 1. ADC/DAC on Primary Interface 1248 * 2. ADC on Primary Interface/DAC on secondary 1249 */ 1250 static const struct snd_soc_dai_ops wm8990_dai_ops = { 1251 .hw_params = wm8990_hw_params, 1252 .digital_mute = wm8990_mute, 1253 .set_fmt = wm8990_set_dai_fmt, 1254 .set_clkdiv = wm8990_set_dai_clkdiv, 1255 .set_pll = wm8990_set_dai_pll, 1256 .set_sysclk = wm8990_set_dai_sysclk, 1257 }; 1258 1259 static struct snd_soc_dai_driver wm8990_dai = { 1260 /* ADC/DAC on primary */ 1261 .name = "wm8990-hifi", 1262 .playback = { 1263 .stream_name = "Playback", 1264 .channels_min = 1, 1265 .channels_max = 2, 1266 .rates = WM8990_RATES, 1267 .formats = WM8990_FORMATS,}, 1268 .capture = { 1269 .stream_name = "Capture", 1270 .channels_min = 1, 1271 .channels_max = 2, 1272 .rates = WM8990_RATES, 1273 .formats = WM8990_FORMATS,}, 1274 .ops = &wm8990_dai_ops, 1275 }; 1276 1277 static int wm8990_suspend(struct snd_soc_codec *codec) 1278 { 1279 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1280 return 0; 1281 } 1282 1283 static int wm8990_resume(struct snd_soc_codec *codec) 1284 { 1285 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1286 return 0; 1287 } 1288 1289 /* 1290 * initialise the WM8990 driver 1291 * register the mixer and dsp interfaces with the kernel 1292 */ 1293 static int wm8990_probe(struct snd_soc_codec *codec) 1294 { 1295 int ret; 1296 1297 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); 1298 if (ret < 0) { 1299 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret); 1300 return ret; 1301 } 1302 1303 wm8990_reset(codec); 1304 1305 /* charge output caps */ 1306 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1307 1308 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4, 1309 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1); 1310 1311 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2, 1312 WM8990_GPIO1_SEL_MASK, 1); 1313 1314 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2, 1315 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA); 1316 1317 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1318 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1319 1320 return 0; 1321 } 1322 1323 /* power down chip */ 1324 static int wm8990_remove(struct snd_soc_codec *codec) 1325 { 1326 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1327 return 0; 1328 } 1329 1330 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = { 1331 .probe = wm8990_probe, 1332 .remove = wm8990_remove, 1333 .suspend = wm8990_suspend, 1334 .resume = wm8990_resume, 1335 .set_bias_level = wm8990_set_bias_level, 1336 .controls = wm8990_snd_controls, 1337 .num_controls = ARRAY_SIZE(wm8990_snd_controls), 1338 .dapm_widgets = wm8990_dapm_widgets, 1339 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets), 1340 .dapm_routes = wm8990_dapm_routes, 1341 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes), 1342 }; 1343 1344 static const struct regmap_config wm8990_regmap = { 1345 .reg_bits = 8, 1346 .val_bits = 16, 1347 1348 .max_register = WM8990_PLL3, 1349 .volatile_reg = wm8990_volatile_register, 1350 .reg_defaults = wm8990_reg_defaults, 1351 .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults), 1352 .cache_type = REGCACHE_RBTREE, 1353 }; 1354 1355 static int wm8990_i2c_probe(struct i2c_client *i2c, 1356 const struct i2c_device_id *id) 1357 { 1358 struct wm8990_priv *wm8990; 1359 int ret; 1360 1361 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv), 1362 GFP_KERNEL); 1363 if (wm8990 == NULL) 1364 return -ENOMEM; 1365 1366 i2c_set_clientdata(i2c, wm8990); 1367 1368 ret = snd_soc_register_codec(&i2c->dev, 1369 &soc_codec_dev_wm8990, &wm8990_dai, 1); 1370 1371 return ret; 1372 } 1373 1374 static int wm8990_i2c_remove(struct i2c_client *client) 1375 { 1376 snd_soc_unregister_codec(&client->dev); 1377 1378 return 0; 1379 } 1380 1381 static const struct i2c_device_id wm8990_i2c_id[] = { 1382 { "wm8990", 0 }, 1383 { } 1384 }; 1385 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1386 1387 static struct i2c_driver wm8990_i2c_driver = { 1388 .driver = { 1389 .name = "wm8990", 1390 .owner = THIS_MODULE, 1391 }, 1392 .probe = wm8990_i2c_probe, 1393 .remove = wm8990_i2c_remove, 1394 .id_table = wm8990_i2c_id, 1395 }; 1396 1397 module_i2c_driver(wm8990_i2c_driver); 1398 1399 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1400 MODULE_AUTHOR("Liam Girdwood"); 1401 MODULE_LICENSE("GPL"); 1402