1 /* 2 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <asm/div64.h> 29 30 #include "wm8990.h" 31 32 #define WM8990_VERSION "0.2" 33 34 /* codec private data */ 35 struct wm8990_priv { 36 unsigned int sysclk; 37 unsigned int pcmclk; 38 }; 39 40 /* 41 * wm8990 register cache. Note that register 0 is not included in the 42 * cache. 43 */ 44 static const u16 wm8990_reg[] = { 45 0x8990, /* R0 - Reset */ 46 0x0000, /* R1 - Power Management (1) */ 47 0x6000, /* R2 - Power Management (2) */ 48 0x0000, /* R3 - Power Management (3) */ 49 0x4050, /* R4 - Audio Interface (1) */ 50 0x4000, /* R5 - Audio Interface (2) */ 51 0x01C8, /* R6 - Clocking (1) */ 52 0x0000, /* R7 - Clocking (2) */ 53 0x0040, /* R8 - Audio Interface (3) */ 54 0x0040, /* R9 - Audio Interface (4) */ 55 0x0004, /* R10 - DAC CTRL */ 56 0x00C0, /* R11 - Left DAC Digital Volume */ 57 0x00C0, /* R12 - Right DAC Digital Volume */ 58 0x0000, /* R13 - Digital Side Tone */ 59 0x0100, /* R14 - ADC CTRL */ 60 0x00C0, /* R15 - Left ADC Digital Volume */ 61 0x00C0, /* R16 - Right ADC Digital Volume */ 62 0x0000, /* R17 */ 63 0x0000, /* R18 - GPIO CTRL 1 */ 64 0x1000, /* R19 - GPIO1 & GPIO2 */ 65 0x1010, /* R20 - GPIO3 & GPIO4 */ 66 0x1010, /* R21 - GPIO5 & GPIO6 */ 67 0x8000, /* R22 - GPIOCTRL 2 */ 68 0x0800, /* R23 - GPIO_POL */ 69 0x008B, /* R24 - Left Line Input 1&2 Volume */ 70 0x008B, /* R25 - Left Line Input 3&4 Volume */ 71 0x008B, /* R26 - Right Line Input 1&2 Volume */ 72 0x008B, /* R27 - Right Line Input 3&4 Volume */ 73 0x0000, /* R28 - Left Output Volume */ 74 0x0000, /* R29 - Right Output Volume */ 75 0x0066, /* R30 - Line Outputs Volume */ 76 0x0022, /* R31 - Out3/4 Volume */ 77 0x0079, /* R32 - Left OPGA Volume */ 78 0x0079, /* R33 - Right OPGA Volume */ 79 0x0003, /* R34 - Speaker Volume */ 80 0x0003, /* R35 - ClassD1 */ 81 0x0000, /* R36 */ 82 0x0100, /* R37 - ClassD3 */ 83 0x0079, /* R38 - ClassD4 */ 84 0x0000, /* R39 - Input Mixer1 */ 85 0x0000, /* R40 - Input Mixer2 */ 86 0x0000, /* R41 - Input Mixer3 */ 87 0x0000, /* R42 - Input Mixer4 */ 88 0x0000, /* R43 - Input Mixer5 */ 89 0x0000, /* R44 - Input Mixer6 */ 90 0x0000, /* R45 - Output Mixer1 */ 91 0x0000, /* R46 - Output Mixer2 */ 92 0x0000, /* R47 - Output Mixer3 */ 93 0x0000, /* R48 - Output Mixer4 */ 94 0x0000, /* R49 - Output Mixer5 */ 95 0x0000, /* R50 - Output Mixer6 */ 96 0x0180, /* R51 - Out3/4 Mixer */ 97 0x0000, /* R52 - Line Mixer1 */ 98 0x0000, /* R53 - Line Mixer2 */ 99 0x0000, /* R54 - Speaker Mixer */ 100 0x0000, /* R55 - Additional Control */ 101 0x0000, /* R56 - AntiPOP1 */ 102 0x0000, /* R57 - AntiPOP2 */ 103 0x0000, /* R58 - MICBIAS */ 104 0x0000, /* R59 */ 105 0x0008, /* R60 - PLL1 */ 106 0x0031, /* R61 - PLL2 */ 107 0x0026, /* R62 - PLL3 */ 108 0x0000, /* R63 - Driver internal */ 109 }; 110 111 /* 112 * read wm8990 register cache 113 */ 114 static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec, 115 unsigned int reg) 116 { 117 u16 *cache = codec->reg_cache; 118 BUG_ON(reg >= ARRAY_SIZE(wm8990_reg)); 119 return cache[reg]; 120 } 121 122 /* 123 * write wm8990 register cache 124 */ 125 static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec, 126 unsigned int reg, unsigned int value) 127 { 128 u16 *cache = codec->reg_cache; 129 130 /* Reset register and reserved registers are uncached */ 131 if (reg == 0 || reg >= ARRAY_SIZE(wm8990_reg)) 132 return; 133 134 cache[reg] = value; 135 } 136 137 /* 138 * write to the wm8990 register space 139 */ 140 static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg, 141 unsigned int value) 142 { 143 u8 data[3]; 144 145 data[0] = reg & 0xFF; 146 data[1] = (value >> 8) & 0xFF; 147 data[2] = value & 0xFF; 148 149 wm8990_write_reg_cache(codec, reg, value); 150 151 if (codec->hw_write(codec->control_data, data, 3) == 2) 152 return 0; 153 else 154 return -EIO; 155 } 156 157 #define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0) 158 159 static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); 160 161 static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000); 162 163 static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100); 164 165 static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600); 166 167 static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0); 168 169 static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0); 170 171 static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763); 172 173 static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0); 174 175 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 176 struct snd_ctl_elem_value *ucontrol) 177 { 178 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 179 struct soc_mixer_control *mc = 180 (struct soc_mixer_control *)kcontrol->private_value; 181 int reg = mc->reg; 182 int ret; 183 u16 val; 184 185 ret = snd_soc_put_volsw(kcontrol, ucontrol); 186 if (ret < 0) 187 return ret; 188 189 /* now hit the volume update bits (always bit 8) */ 190 val = wm8990_read_reg_cache(codec, reg); 191 return wm8990_write(codec, reg, val | 0x0100); 192 } 193 194 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 195 tlv_array) {\ 196 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 197 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 198 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 199 .tlv.p = (tlv_array), \ 200 .info = snd_soc_info_volsw, \ 201 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 202 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 203 204 205 static const char *wm8990_digital_sidetone[] = 206 {"None", "Left ADC", "Right ADC", "Reserved"}; 207 208 static const struct soc_enum wm8990_left_digital_sidetone_enum = 209 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 210 WM8990_ADC_TO_DACL_SHIFT, 211 WM8990_ADC_TO_DACL_MASK, 212 wm8990_digital_sidetone); 213 214 static const struct soc_enum wm8990_right_digital_sidetone_enum = 215 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 216 WM8990_ADC_TO_DACR_SHIFT, 217 WM8990_ADC_TO_DACR_MASK, 218 wm8990_digital_sidetone); 219 220 static const char *wm8990_adcmode[] = 221 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 222 223 static const struct soc_enum wm8990_right_adcmode_enum = 224 SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 225 WM8990_ADC_HPF_CUT_SHIFT, 226 WM8990_ADC_HPF_CUT_MASK, 227 wm8990_adcmode); 228 229 static const struct snd_kcontrol_new wm8990_snd_controls[] = { 230 /* INMIXL */ 231 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 232 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 233 /* INMIXR */ 234 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 235 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 236 237 /* LOMIX */ 238 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 239 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 240 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 241 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 242 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 243 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 244 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 245 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 246 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 247 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 248 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 249 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 250 251 /* ROMIX */ 252 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 253 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 254 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 255 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 256 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 257 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 258 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 259 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 260 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 261 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 262 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 263 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 264 265 /* LOUT */ 266 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 267 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 268 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 269 270 /* ROUT */ 271 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 272 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 273 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 274 275 /* LOPGA */ 276 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 277 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 278 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 279 WM8990_LOPGAZC_BIT, 1, 0), 280 281 /* ROPGA */ 282 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 283 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 284 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 285 WM8990_ROPGAZC_BIT, 1, 0), 286 287 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 288 WM8990_LONMUTE_BIT, 1, 0), 289 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 290 WM8990_LOPMUTE_BIT, 1, 0), 291 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 292 WM8990_LOATTN_BIT, 1, 0), 293 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 294 WM8990_RONMUTE_BIT, 1, 0), 295 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 296 WM8990_ROPMUTE_BIT, 1, 0), 297 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 298 WM8990_ROATTN_BIT, 1, 0), 299 300 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 301 WM8990_OUT3MUTE_BIT, 1, 0), 302 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 303 WM8990_OUT3ATTN_BIT, 1, 0), 304 305 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 306 WM8990_OUT4MUTE_BIT, 1, 0), 307 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 308 WM8990_OUT4ATTN_BIT, 1, 0), 309 310 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 311 WM8990_CDMODE_BIT, 1, 0), 312 313 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 314 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 315 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 316 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 317 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 318 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 319 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 320 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 321 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 322 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 323 324 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 325 WM8990_LEFT_DAC_DIGITAL_VOLUME, 326 WM8990_DACL_VOL_SHIFT, 327 WM8990_DACL_VOL_MASK, 328 0, 329 out_dac_tlv), 330 331 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 332 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 333 WM8990_DACR_VOL_SHIFT, 334 WM8990_DACR_VOL_MASK, 335 0, 336 out_dac_tlv), 337 338 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 339 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 340 341 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 342 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 343 out_sidetone_tlv), 344 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 345 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 346 out_sidetone_tlv), 347 348 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 349 WM8990_ADC_HPF_ENA_BIT, 1, 0), 350 351 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 352 353 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 354 WM8990_LEFT_ADC_DIGITAL_VOLUME, 355 WM8990_ADCL_VOL_SHIFT, 356 WM8990_ADCL_VOL_MASK, 357 0, 358 in_adc_tlv), 359 360 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 361 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 362 WM8990_ADCR_VOL_SHIFT, 363 WM8990_ADCR_VOL_MASK, 364 0, 365 in_adc_tlv), 366 367 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 368 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 369 WM8990_LIN12VOL_SHIFT, 370 WM8990_LIN12VOL_MASK, 371 0, 372 in_pga_tlv), 373 374 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 375 WM8990_LI12ZC_BIT, 1, 0), 376 377 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 378 WM8990_LI12MUTE_BIT, 1, 0), 379 380 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 381 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 382 WM8990_LIN34VOL_SHIFT, 383 WM8990_LIN34VOL_MASK, 384 0, 385 in_pga_tlv), 386 387 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 388 WM8990_LI34ZC_BIT, 1, 0), 389 390 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 391 WM8990_LI34MUTE_BIT, 1, 0), 392 393 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 394 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 395 WM8990_RIN12VOL_SHIFT, 396 WM8990_RIN12VOL_MASK, 397 0, 398 in_pga_tlv), 399 400 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 401 WM8990_RI12ZC_BIT, 1, 0), 402 403 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 404 WM8990_RI12MUTE_BIT, 1, 0), 405 406 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 407 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 408 WM8990_RIN34VOL_SHIFT, 409 WM8990_RIN34VOL_MASK, 410 0, 411 in_pga_tlv), 412 413 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 414 WM8990_RI34ZC_BIT, 1, 0), 415 416 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 417 WM8990_RI34MUTE_BIT, 1, 0), 418 419 }; 420 421 /* 422 * _DAPM_ Controls 423 */ 424 425 static int inmixer_event(struct snd_soc_dapm_widget *w, 426 struct snd_kcontrol *kcontrol, int event) 427 { 428 u16 reg, fakepower; 429 430 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); 431 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); 432 433 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 434 (1 << WM8990_AINLMUX_PWR_BIT))) { 435 reg |= WM8990_AINL_ENA; 436 } else { 437 reg &= ~WM8990_AINL_ENA; 438 } 439 440 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 441 (1 << WM8990_AINRMUX_PWR_BIT))) { 442 reg |= WM8990_AINR_ENA; 443 } else { 444 reg &= ~WM8990_AINL_ENA; 445 } 446 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 447 448 return 0; 449 } 450 451 static int outmixer_event(struct snd_soc_dapm_widget *w, 452 struct snd_kcontrol *kcontrol, int event) 453 { 454 u32 reg_shift = kcontrol->private_value & 0xfff; 455 int ret = 0; 456 u16 reg; 457 458 switch (reg_shift) { 459 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 460 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); 461 if (reg & WM8990_LDLO) { 462 printk(KERN_WARNING 463 "Cannot set as Output Mixer 1 LDLO Set\n"); 464 ret = -1; 465 } 466 break; 467 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 468 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2); 469 if (reg & WM8990_RDRO) { 470 printk(KERN_WARNING 471 "Cannot set as Output Mixer 2 RDRO Set\n"); 472 ret = -1; 473 } 474 break; 475 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 476 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 477 if (reg & WM8990_LDSPK) { 478 printk(KERN_WARNING 479 "Cannot set as Speaker Mixer LDSPK Set\n"); 480 ret = -1; 481 } 482 break; 483 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 484 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 485 if (reg & WM8990_RDSPK) { 486 printk(KERN_WARNING 487 "Cannot set as Speaker Mixer RDSPK Set\n"); 488 ret = -1; 489 } 490 break; 491 } 492 493 return ret; 494 } 495 496 /* INMIX dB values */ 497 static const unsigned int in_mix_tlv[] = { 498 TLV_DB_RANGE_HEAD(1), 499 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), 500 }; 501 502 /* Left In PGA Connections */ 503 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 504 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 505 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 506 }; 507 508 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 509 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 510 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 511 }; 512 513 /* Right In PGA Connections */ 514 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 515 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 516 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 517 }; 518 519 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 520 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 521 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 522 }; 523 524 /* INMIXL */ 525 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 526 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 527 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 528 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 529 7, 0, in_mix_tlv), 530 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 531 1, 0), 532 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 533 1, 0), 534 }; 535 536 /* INMIXR */ 537 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 538 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 539 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 540 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 541 7, 0, in_mix_tlv), 542 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 543 1, 0), 544 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 545 1, 0), 546 }; 547 548 /* AINLMUX */ 549 static const char *wm8990_ainlmux[] = 550 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 551 552 static const struct soc_enum wm8990_ainlmux_enum = 553 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 554 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 555 556 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 557 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 558 559 /* DIFFINL */ 560 561 /* AINRMUX */ 562 static const char *wm8990_ainrmux[] = 563 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 564 565 static const struct soc_enum wm8990_ainrmux_enum = 566 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 567 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 568 569 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 570 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 571 572 /* RXVOICE */ 573 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 574 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 575 WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 576 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 577 WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 578 }; 579 580 /* LOMIX */ 581 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 582 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 583 WM8990_LRBLO_BIT, 1, 0), 584 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 585 WM8990_LLBLO_BIT, 1, 0), 586 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 587 WM8990_LRI3LO_BIT, 1, 0), 588 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 589 WM8990_LLI3LO_BIT, 1, 0), 590 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 591 WM8990_LR12LO_BIT, 1, 0), 592 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 593 WM8990_LL12LO_BIT, 1, 0), 594 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 595 WM8990_LDLO_BIT, 1, 0), 596 }; 597 598 /* ROMIX */ 599 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 600 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 601 WM8990_RLBRO_BIT, 1, 0), 602 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 603 WM8990_RRBRO_BIT, 1, 0), 604 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 605 WM8990_RLI3RO_BIT, 1, 0), 606 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 607 WM8990_RRI3RO_BIT, 1, 0), 608 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 609 WM8990_RL12RO_BIT, 1, 0), 610 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 611 WM8990_RR12RO_BIT, 1, 0), 612 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 613 WM8990_RDRO_BIT, 1, 0), 614 }; 615 616 /* LONMIX */ 617 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 618 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 619 WM8990_LLOPGALON_BIT, 1, 0), 620 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 621 WM8990_LROPGALON_BIT, 1, 0), 622 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 623 WM8990_LOPLON_BIT, 1, 0), 624 }; 625 626 /* LOPMIX */ 627 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 628 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 629 WM8990_LR12LOP_BIT, 1, 0), 630 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 631 WM8990_LL12LOP_BIT, 1, 0), 632 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 633 WM8990_LLOPGALOP_BIT, 1, 0), 634 }; 635 636 /* RONMIX */ 637 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 638 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 639 WM8990_RROPGARON_BIT, 1, 0), 640 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 641 WM8990_RLOPGARON_BIT, 1, 0), 642 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 643 WM8990_ROPRON_BIT, 1, 0), 644 }; 645 646 /* ROPMIX */ 647 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 648 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 649 WM8990_RL12ROP_BIT, 1, 0), 650 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 651 WM8990_RR12ROP_BIT, 1, 0), 652 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 653 WM8990_RROPGAROP_BIT, 1, 0), 654 }; 655 656 /* OUT3MIX */ 657 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 658 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 659 WM8990_LI4O3_BIT, 1, 0), 660 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 661 WM8990_LPGAO3_BIT, 1, 0), 662 }; 663 664 /* OUT4MIX */ 665 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 666 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 667 WM8990_RPGAO4_BIT, 1, 0), 668 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 669 WM8990_RI4O4_BIT, 1, 0), 670 }; 671 672 /* SPKMIX */ 673 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 674 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 675 WM8990_LI2SPK_BIT, 1, 0), 676 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 677 WM8990_LB2SPK_BIT, 1, 0), 678 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 679 WM8990_LOPGASPK_BIT, 1, 0), 680 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 681 WM8990_LDSPK_BIT, 1, 0), 682 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 683 WM8990_RDSPK_BIT, 1, 0), 684 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 685 WM8990_ROPGASPK_BIT, 1, 0), 686 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 687 WM8990_RL12ROP_BIT, 1, 0), 688 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 689 WM8990_RI2SPK_BIT, 1, 0), 690 }; 691 692 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 693 /* Input Side */ 694 /* Input Lines */ 695 SND_SOC_DAPM_INPUT("LIN1"), 696 SND_SOC_DAPM_INPUT("LIN2"), 697 SND_SOC_DAPM_INPUT("LIN3"), 698 SND_SOC_DAPM_INPUT("LIN4/RXN"), 699 SND_SOC_DAPM_INPUT("RIN3"), 700 SND_SOC_DAPM_INPUT("RIN4/RXP"), 701 SND_SOC_DAPM_INPUT("RIN1"), 702 SND_SOC_DAPM_INPUT("RIN2"), 703 SND_SOC_DAPM_INPUT("Internal ADC Source"), 704 705 /* DACs */ 706 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 707 WM8990_ADCL_ENA_BIT, 0), 708 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 709 WM8990_ADCR_ENA_BIT, 0), 710 711 /* Input PGAs */ 712 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 713 0, &wm8990_dapm_lin12_pga_controls[0], 714 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 715 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 716 0, &wm8990_dapm_lin34_pga_controls[0], 717 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 718 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 719 0, &wm8990_dapm_rin12_pga_controls[0], 720 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 721 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 722 0, &wm8990_dapm_rin34_pga_controls[0], 723 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 724 725 /* INMIXL */ 726 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 727 &wm8990_dapm_inmixl_controls[0], 728 ARRAY_SIZE(wm8990_dapm_inmixl_controls), 729 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 730 731 /* AINLMUX */ 732 SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 733 &wm8990_dapm_ainlmux_controls, inmixer_event, 734 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 735 736 /* INMIXR */ 737 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 738 &wm8990_dapm_inmixr_controls[0], 739 ARRAY_SIZE(wm8990_dapm_inmixr_controls), 740 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 741 742 /* AINRMUX */ 743 SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 744 &wm8990_dapm_ainrmux_controls, inmixer_event, 745 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 746 747 /* Output Side */ 748 /* DACs */ 749 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 750 WM8990_DACL_ENA_BIT, 0), 751 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 752 WM8990_DACR_ENA_BIT, 0), 753 754 /* LOMIX */ 755 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 756 0, &wm8990_dapm_lomix_controls[0], 757 ARRAY_SIZE(wm8990_dapm_lomix_controls), 758 outmixer_event, SND_SOC_DAPM_PRE_REG), 759 760 /* LONMIX */ 761 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 762 &wm8990_dapm_lonmix_controls[0], 763 ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 764 765 /* LOPMIX */ 766 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 767 &wm8990_dapm_lopmix_controls[0], 768 ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 769 770 /* OUT3MIX */ 771 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 772 &wm8990_dapm_out3mix_controls[0], 773 ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 774 775 /* SPKMIX */ 776 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 777 &wm8990_dapm_spkmix_controls[0], 778 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 779 SND_SOC_DAPM_PRE_REG), 780 781 /* OUT4MIX */ 782 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 783 &wm8990_dapm_out4mix_controls[0], 784 ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 785 786 /* ROPMIX */ 787 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 788 &wm8990_dapm_ropmix_controls[0], 789 ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 790 791 /* RONMIX */ 792 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 793 &wm8990_dapm_ronmix_controls[0], 794 ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 795 796 /* ROMIX */ 797 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 798 0, &wm8990_dapm_romix_controls[0], 799 ARRAY_SIZE(wm8990_dapm_romix_controls), 800 outmixer_event, SND_SOC_DAPM_PRE_REG), 801 802 /* LOUT PGA */ 803 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 804 NULL, 0), 805 806 /* ROUT PGA */ 807 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 808 NULL, 0), 809 810 /* LOPGA */ 811 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 812 NULL, 0), 813 814 /* ROPGA */ 815 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 816 NULL, 0), 817 818 /* MICBIAS */ 819 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 820 WM8990_MICBIAS_ENA_BIT, 0), 821 822 SND_SOC_DAPM_OUTPUT("LON"), 823 SND_SOC_DAPM_OUTPUT("LOP"), 824 SND_SOC_DAPM_OUTPUT("OUT3"), 825 SND_SOC_DAPM_OUTPUT("LOUT"), 826 SND_SOC_DAPM_OUTPUT("SPKN"), 827 SND_SOC_DAPM_OUTPUT("SPKP"), 828 SND_SOC_DAPM_OUTPUT("ROUT"), 829 SND_SOC_DAPM_OUTPUT("OUT4"), 830 SND_SOC_DAPM_OUTPUT("ROP"), 831 SND_SOC_DAPM_OUTPUT("RON"), 832 833 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 834 }; 835 836 static const struct snd_soc_dapm_route audio_map[] = { 837 /* Make DACs turn on when playing even if not mixed into any outputs */ 838 {"Internal DAC Sink", NULL, "Left DAC"}, 839 {"Internal DAC Sink", NULL, "Right DAC"}, 840 841 /* Make ADCs turn on when recording even if not mixed from any inputs */ 842 {"Left ADC", NULL, "Internal ADC Source"}, 843 {"Right ADC", NULL, "Internal ADC Source"}, 844 845 /* Input Side */ 846 /* LIN12 PGA */ 847 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 848 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 849 /* LIN34 PGA */ 850 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 851 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 852 /* INMIXL */ 853 {"INMIXL", "Record Left Volume", "LOMIX"}, 854 {"INMIXL", "LIN2 Volume", "LIN2"}, 855 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 856 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 857 /* AINLMUX */ 858 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 859 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 860 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 861 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 862 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 863 /* ADC */ 864 {"Left ADC", NULL, "AINLMUX"}, 865 866 /* RIN12 PGA */ 867 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 868 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 869 /* RIN34 PGA */ 870 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 871 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 872 /* INMIXL */ 873 {"INMIXR", "Record Right Volume", "ROMIX"}, 874 {"INMIXR", "RIN2 Volume", "RIN2"}, 875 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 876 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 877 /* AINRMUX */ 878 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 879 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 880 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 881 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 882 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 883 /* ADC */ 884 {"Right ADC", NULL, "AINRMUX"}, 885 886 /* LOMIX */ 887 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 888 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 889 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 890 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 891 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 892 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 893 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 894 895 /* ROMIX */ 896 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 897 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 898 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 899 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 900 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 901 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 902 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 903 904 /* SPKMIX */ 905 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 906 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 907 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 908 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 909 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 910 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 911 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 912 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 913 914 /* LONMIX */ 915 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 916 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 917 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 918 919 /* LOPMIX */ 920 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 921 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 922 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 923 924 /* OUT3MIX */ 925 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 926 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 927 928 /* OUT4MIX */ 929 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 930 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 931 932 /* RONMIX */ 933 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 934 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 935 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 936 937 /* ROPMIX */ 938 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 939 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 940 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 941 942 /* Out Mixer PGAs */ 943 {"LOPGA", NULL, "LOMIX"}, 944 {"ROPGA", NULL, "ROMIX"}, 945 946 {"LOUT PGA", NULL, "LOMIX"}, 947 {"ROUT PGA", NULL, "ROMIX"}, 948 949 /* Output Pins */ 950 {"LON", NULL, "LONMIX"}, 951 {"LOP", NULL, "LOPMIX"}, 952 {"OUT3", NULL, "OUT3MIX"}, 953 {"LOUT", NULL, "LOUT PGA"}, 954 {"SPKN", NULL, "SPKMIX"}, 955 {"ROUT", NULL, "ROUT PGA"}, 956 {"OUT4", NULL, "OUT4MIX"}, 957 {"ROP", NULL, "ROPMIX"}, 958 {"RON", NULL, "RONMIX"}, 959 }; 960 961 static int wm8990_add_widgets(struct snd_soc_codec *codec) 962 { 963 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, 964 ARRAY_SIZE(wm8990_dapm_widgets)); 965 966 /* set up the WM8990 audio map */ 967 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 968 969 snd_soc_dapm_new_widgets(codec); 970 return 0; 971 } 972 973 /* PLL divisors */ 974 struct _pll_div { 975 u32 div2; 976 u32 n; 977 u32 k; 978 }; 979 980 /* The size in bits of the pll divide multiplied by 10 981 * to allow rounding later */ 982 #define FIXED_PLL_SIZE ((1 << 16) * 10) 983 984 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 985 unsigned int source) 986 { 987 u64 Kpart; 988 unsigned int K, Ndiv, Nmod; 989 990 991 Ndiv = target / source; 992 if (Ndiv < 6) { 993 source >>= 1; 994 pll_div->div2 = 1; 995 Ndiv = target / source; 996 } else 997 pll_div->div2 = 0; 998 999 if ((Ndiv < 6) || (Ndiv > 12)) 1000 printk(KERN_WARNING 1001 "WM8990 N value outwith recommended range! N = %d\n", Ndiv); 1002 1003 pll_div->n = Ndiv; 1004 Nmod = target % source; 1005 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 1006 1007 do_div(Kpart, source); 1008 1009 K = Kpart & 0xFFFFFFFF; 1010 1011 /* Check if we need to round */ 1012 if ((K % 10) >= 5) 1013 K += 5; 1014 1015 /* Move down to proper range now rounding is done */ 1016 K /= 10; 1017 1018 pll_div->k = K; 1019 } 1020 1021 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, 1022 int pll_id, unsigned int freq_in, unsigned int freq_out) 1023 { 1024 u16 reg; 1025 struct snd_soc_codec *codec = codec_dai->codec; 1026 struct _pll_div pll_div; 1027 1028 if (freq_in && freq_out) { 1029 pll_factors(&pll_div, freq_out * 4, freq_in); 1030 1031 /* Turn on PLL */ 1032 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1033 reg |= WM8990_PLL_ENA; 1034 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1035 1036 /* sysclk comes from PLL */ 1037 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2); 1038 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 1039 1040 /* set up N , fractional mode and pre-divisor if neccessary */ 1041 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 1042 (pll_div.div2?WM8990_PRESCALE:0)); 1043 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 1044 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 1045 } else { 1046 /* Turn on PLL */ 1047 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1048 reg &= ~WM8990_PLL_ENA; 1049 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1050 } 1051 return 0; 1052 } 1053 1054 /* 1055 * Clock after PLL and dividers 1056 */ 1057 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1058 int clk_id, unsigned int freq, int dir) 1059 { 1060 struct snd_soc_codec *codec = codec_dai->codec; 1061 struct wm8990_priv *wm8990 = codec->private_data; 1062 1063 wm8990->sysclk = freq; 1064 return 0; 1065 } 1066 1067 /* 1068 * Set's ADC and Voice DAC format. 1069 */ 1070 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1071 unsigned int fmt) 1072 { 1073 struct snd_soc_codec *codec = codec_dai->codec; 1074 u16 audio1, audio3; 1075 1076 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1077 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3); 1078 1079 /* set master/slave audio interface */ 1080 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1081 case SND_SOC_DAIFMT_CBS_CFS: 1082 audio3 &= ~WM8990_AIF_MSTR1; 1083 break; 1084 case SND_SOC_DAIFMT_CBM_CFM: 1085 audio3 |= WM8990_AIF_MSTR1; 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 1091 audio1 &= ~WM8990_AIF_FMT_MASK; 1092 1093 /* interface format */ 1094 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1095 case SND_SOC_DAIFMT_I2S: 1096 audio1 |= WM8990_AIF_TMF_I2S; 1097 audio1 &= ~WM8990_AIF_LRCLK_INV; 1098 break; 1099 case SND_SOC_DAIFMT_RIGHT_J: 1100 audio1 |= WM8990_AIF_TMF_RIGHTJ; 1101 audio1 &= ~WM8990_AIF_LRCLK_INV; 1102 break; 1103 case SND_SOC_DAIFMT_LEFT_J: 1104 audio1 |= WM8990_AIF_TMF_LEFTJ; 1105 audio1 &= ~WM8990_AIF_LRCLK_INV; 1106 break; 1107 case SND_SOC_DAIFMT_DSP_A: 1108 audio1 |= WM8990_AIF_TMF_DSP; 1109 audio1 &= ~WM8990_AIF_LRCLK_INV; 1110 break; 1111 case SND_SOC_DAIFMT_DSP_B: 1112 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1113 break; 1114 default: 1115 return -EINVAL; 1116 } 1117 1118 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1119 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1120 return 0; 1121 } 1122 1123 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1124 int div_id, int div) 1125 { 1126 struct snd_soc_codec *codec = codec_dai->codec; 1127 u16 reg; 1128 1129 switch (div_id) { 1130 case WM8990_MCLK_DIV: 1131 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1132 ~WM8990_MCLK_DIV_MASK; 1133 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1134 break; 1135 case WM8990_DACCLK_DIV: 1136 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1137 ~WM8990_DAC_CLKDIV_MASK; 1138 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1139 break; 1140 case WM8990_ADCCLK_DIV: 1141 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1142 ~WM8990_ADC_CLKDIV_MASK; 1143 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1144 break; 1145 case WM8990_BCLK_DIV: 1146 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) & 1147 ~WM8990_BCLK_DIV_MASK; 1148 wm8990_write(codec, WM8990_CLOCKING_1, reg | div); 1149 break; 1150 default: 1151 return -EINVAL; 1152 } 1153 1154 return 0; 1155 } 1156 1157 /* 1158 * Set PCM DAI bit size and sample rate. 1159 */ 1160 static int wm8990_hw_params(struct snd_pcm_substream *substream, 1161 struct snd_pcm_hw_params *params, 1162 struct snd_soc_dai *dai) 1163 { 1164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1165 struct snd_soc_device *socdev = rtd->socdev; 1166 struct snd_soc_codec *codec = socdev->card->codec; 1167 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1168 1169 audio1 &= ~WM8990_AIF_WL_MASK; 1170 /* bit size */ 1171 switch (params_format(params)) { 1172 case SNDRV_PCM_FORMAT_S16_LE: 1173 break; 1174 case SNDRV_PCM_FORMAT_S20_3LE: 1175 audio1 |= WM8990_AIF_WL_20BITS; 1176 break; 1177 case SNDRV_PCM_FORMAT_S24_LE: 1178 audio1 |= WM8990_AIF_WL_24BITS; 1179 break; 1180 case SNDRV_PCM_FORMAT_S32_LE: 1181 audio1 |= WM8990_AIF_WL_32BITS; 1182 break; 1183 } 1184 1185 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1186 return 0; 1187 } 1188 1189 static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1190 { 1191 struct snd_soc_codec *codec = dai->codec; 1192 u16 val; 1193 1194 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1195 1196 if (mute) 1197 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1198 else 1199 wm8990_write(codec, WM8990_DAC_CTRL, val); 1200 1201 return 0; 1202 } 1203 1204 static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1205 enum snd_soc_bias_level level) 1206 { 1207 u16 val; 1208 1209 switch (level) { 1210 case SND_SOC_BIAS_ON: 1211 break; 1212 1213 case SND_SOC_BIAS_PREPARE: 1214 /* VMID=2*50k */ 1215 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1216 ~WM8990_VMID_MODE_MASK; 1217 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1218 break; 1219 1220 case SND_SOC_BIAS_STANDBY: 1221 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1222 /* Enable all output discharge bits */ 1223 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1224 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1225 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1226 WM8990_DIS_ROUT); 1227 1228 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1229 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1230 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1231 WM8990_VMIDTOG); 1232 1233 /* Delay to allow output caps to discharge */ 1234 msleep(msecs_to_jiffies(300)); 1235 1236 /* Disable VMIDTOG */ 1237 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1238 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1239 1240 /* disable all output discharge bits */ 1241 wm8990_write(codec, WM8990_ANTIPOP1, 0); 1242 1243 /* Enable outputs */ 1244 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1245 1246 msleep(msecs_to_jiffies(50)); 1247 1248 /* Enable VMID at 2x50k */ 1249 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1250 1251 msleep(msecs_to_jiffies(100)); 1252 1253 /* Enable VREF */ 1254 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1255 1256 msleep(msecs_to_jiffies(600)); 1257 1258 /* Enable BUFIOEN */ 1259 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1260 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1261 WM8990_BUFIOEN); 1262 1263 /* Disable outputs */ 1264 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1265 1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1267 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1268 1269 /* Enable workaround for ADC clocking issue. */ 1270 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1271 wm8990_write(codec, WM8990_EXT_CTL1, 0xa003); 1272 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1273 } 1274 1275 /* VMID=2*250k */ 1276 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1277 ~WM8990_VMID_MODE_MASK; 1278 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1279 break; 1280 1281 case SND_SOC_BIAS_OFF: 1282 /* Enable POBCTRL and SOFT_ST */ 1283 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1284 WM8990_POBCTRL | WM8990_BUFIOEN); 1285 1286 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1287 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1288 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1289 WM8990_BUFIOEN); 1290 1291 /* mute DAC */ 1292 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL); 1293 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1294 1295 /* Enable any disabled outputs */ 1296 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1297 1298 /* Disable VMID */ 1299 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1300 1301 msleep(msecs_to_jiffies(300)); 1302 1303 /* Enable all output discharge bits */ 1304 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1305 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1306 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1307 WM8990_DIS_ROUT); 1308 1309 /* Disable VREF */ 1310 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1311 1312 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1313 wm8990_write(codec, WM8990_ANTIPOP2, 0x0); 1314 break; 1315 } 1316 1317 codec->bias_level = level; 1318 return 0; 1319 } 1320 1321 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1322 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1323 SNDRV_PCM_RATE_48000) 1324 1325 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1326 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1327 1328 /* 1329 * The WM8990 supports 2 different and mutually exclusive DAI 1330 * configurations. 1331 * 1332 * 1. ADC/DAC on Primary Interface 1333 * 2. ADC on Primary Interface/DAC on secondary 1334 */ 1335 static struct snd_soc_dai_ops wm8990_dai_ops = { 1336 .hw_params = wm8990_hw_params, 1337 .digital_mute = wm8990_mute, 1338 .set_fmt = wm8990_set_dai_fmt, 1339 .set_clkdiv = wm8990_set_dai_clkdiv, 1340 .set_pll = wm8990_set_dai_pll, 1341 .set_sysclk = wm8990_set_dai_sysclk, 1342 }; 1343 1344 struct snd_soc_dai wm8990_dai = { 1345 /* ADC/DAC on primary */ 1346 .name = "WM8990 ADC/DAC Primary", 1347 .id = 1, 1348 .playback = { 1349 .stream_name = "Playback", 1350 .channels_min = 1, 1351 .channels_max = 2, 1352 .rates = WM8990_RATES, 1353 .formats = WM8990_FORMATS,}, 1354 .capture = { 1355 .stream_name = "Capture", 1356 .channels_min = 1, 1357 .channels_max = 2, 1358 .rates = WM8990_RATES, 1359 .formats = WM8990_FORMATS,}, 1360 .ops = &wm8990_dai_ops, 1361 }; 1362 EXPORT_SYMBOL_GPL(wm8990_dai); 1363 1364 static int wm8990_suspend(struct platform_device *pdev, pm_message_t state) 1365 { 1366 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1367 struct snd_soc_codec *codec = socdev->card->codec; 1368 1369 /* we only need to suspend if we are a valid card */ 1370 if (!codec->card) 1371 return 0; 1372 1373 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1374 return 0; 1375 } 1376 1377 static int wm8990_resume(struct platform_device *pdev) 1378 { 1379 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1380 struct snd_soc_codec *codec = socdev->card->codec; 1381 int i; 1382 u8 data[2]; 1383 u16 *cache = codec->reg_cache; 1384 1385 /* we only need to resume if we are a valid card */ 1386 if (!codec->card) 1387 return 0; 1388 1389 /* Sync reg_cache with the hardware */ 1390 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) { 1391 if (i + 1 == WM8990_RESET) 1392 continue; 1393 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1394 data[1] = cache[i] & 0x00ff; 1395 codec->hw_write(codec->control_data, data, 2); 1396 } 1397 1398 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1399 return 0; 1400 } 1401 1402 /* 1403 * initialise the WM8990 driver 1404 * register the mixer and dsp interfaces with the kernel 1405 */ 1406 static int wm8990_init(struct snd_soc_device *socdev) 1407 { 1408 struct snd_soc_codec *codec = socdev->card->codec; 1409 u16 reg; 1410 int ret = 0; 1411 1412 codec->name = "WM8990"; 1413 codec->owner = THIS_MODULE; 1414 codec->read = wm8990_read_reg_cache; 1415 codec->write = wm8990_write; 1416 codec->set_bias_level = wm8990_set_bias_level; 1417 codec->dai = &wm8990_dai; 1418 codec->num_dai = 2; 1419 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg); 1420 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL); 1421 1422 if (codec->reg_cache == NULL) 1423 return -ENOMEM; 1424 1425 wm8990_reset(codec); 1426 1427 /* register pcms */ 1428 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1429 if (ret < 0) { 1430 printk(KERN_ERR "wm8990: failed to create pcms\n"); 1431 goto pcm_err; 1432 } 1433 1434 /* charge output caps */ 1435 codec->bias_level = SND_SOC_BIAS_OFF; 1436 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1437 1438 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); 1439 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1440 1441 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & 1442 ~WM8990_GPIO1_SEL_MASK; 1443 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1444 1445 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1446 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1447 1448 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1449 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1450 1451 snd_soc_add_controls(codec, wm8990_snd_controls, 1452 ARRAY_SIZE(wm8990_snd_controls)); 1453 wm8990_add_widgets(codec); 1454 ret = snd_soc_init_card(socdev); 1455 if (ret < 0) { 1456 printk(KERN_ERR "wm8990: failed to register card\n"); 1457 goto card_err; 1458 } 1459 return ret; 1460 1461 card_err: 1462 snd_soc_free_pcms(socdev); 1463 snd_soc_dapm_free(socdev); 1464 pcm_err: 1465 kfree(codec->reg_cache); 1466 return ret; 1467 } 1468 1469 /* If the i2c layer weren't so broken, we could pass this kind of data 1470 around */ 1471 static struct snd_soc_device *wm8990_socdev; 1472 1473 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1474 1475 /* 1476 * WM891 2 wire address is determined by GPIO5 1477 * state during powerup. 1478 * low = 0x34 1479 * high = 0x36 1480 */ 1481 1482 static int wm8990_i2c_probe(struct i2c_client *i2c, 1483 const struct i2c_device_id *id) 1484 { 1485 struct snd_soc_device *socdev = wm8990_socdev; 1486 struct snd_soc_codec *codec = socdev->card->codec; 1487 int ret; 1488 1489 i2c_set_clientdata(i2c, codec); 1490 codec->control_data = i2c; 1491 1492 ret = wm8990_init(socdev); 1493 if (ret < 0) 1494 pr_err("failed to initialise WM8990\n"); 1495 1496 return ret; 1497 } 1498 1499 static int wm8990_i2c_remove(struct i2c_client *client) 1500 { 1501 struct snd_soc_codec *codec = i2c_get_clientdata(client); 1502 kfree(codec->reg_cache); 1503 return 0; 1504 } 1505 1506 static const struct i2c_device_id wm8990_i2c_id[] = { 1507 { "wm8990", 0 }, 1508 { } 1509 }; 1510 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1511 1512 static struct i2c_driver wm8990_i2c_driver = { 1513 .driver = { 1514 .name = "WM8990 I2C Codec", 1515 .owner = THIS_MODULE, 1516 }, 1517 .probe = wm8990_i2c_probe, 1518 .remove = wm8990_i2c_remove, 1519 .id_table = wm8990_i2c_id, 1520 }; 1521 1522 static int wm8990_add_i2c_device(struct platform_device *pdev, 1523 const struct wm8990_setup_data *setup) 1524 { 1525 struct i2c_board_info info; 1526 struct i2c_adapter *adapter; 1527 struct i2c_client *client; 1528 int ret; 1529 1530 ret = i2c_add_driver(&wm8990_i2c_driver); 1531 if (ret != 0) { 1532 dev_err(&pdev->dev, "can't add i2c driver\n"); 1533 return ret; 1534 } 1535 1536 memset(&info, 0, sizeof(struct i2c_board_info)); 1537 info.addr = setup->i2c_address; 1538 strlcpy(info.type, "wm8990", I2C_NAME_SIZE); 1539 1540 adapter = i2c_get_adapter(setup->i2c_bus); 1541 if (!adapter) { 1542 dev_err(&pdev->dev, "can't get i2c adapter %d\n", 1543 setup->i2c_bus); 1544 goto err_driver; 1545 } 1546 1547 client = i2c_new_device(adapter, &info); 1548 i2c_put_adapter(adapter); 1549 if (!client) { 1550 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n", 1551 (unsigned int)info.addr); 1552 goto err_driver; 1553 } 1554 1555 return 0; 1556 1557 err_driver: 1558 i2c_del_driver(&wm8990_i2c_driver); 1559 return -ENODEV; 1560 } 1561 #endif 1562 1563 static int wm8990_probe(struct platform_device *pdev) 1564 { 1565 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1566 struct wm8990_setup_data *setup; 1567 struct snd_soc_codec *codec; 1568 struct wm8990_priv *wm8990; 1569 int ret; 1570 1571 pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION); 1572 1573 setup = socdev->codec_data; 1574 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 1575 if (codec == NULL) 1576 return -ENOMEM; 1577 1578 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1579 if (wm8990 == NULL) { 1580 kfree(codec); 1581 return -ENOMEM; 1582 } 1583 1584 codec->private_data = wm8990; 1585 socdev->card->codec = codec; 1586 mutex_init(&codec->mutex); 1587 INIT_LIST_HEAD(&codec->dapm_widgets); 1588 INIT_LIST_HEAD(&codec->dapm_paths); 1589 wm8990_socdev = socdev; 1590 1591 ret = -ENODEV; 1592 1593 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1594 if (setup->i2c_address) { 1595 codec->hw_write = (hw_write_t)i2c_master_send; 1596 ret = wm8990_add_i2c_device(pdev, setup); 1597 } 1598 #endif 1599 1600 if (ret != 0) { 1601 kfree(codec->private_data); 1602 kfree(codec); 1603 } 1604 return ret; 1605 } 1606 1607 /* power down chip */ 1608 static int wm8990_remove(struct platform_device *pdev) 1609 { 1610 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1611 struct snd_soc_codec *codec = socdev->card->codec; 1612 1613 if (codec->control_data) 1614 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1615 snd_soc_free_pcms(socdev); 1616 snd_soc_dapm_free(socdev); 1617 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1618 i2c_unregister_device(codec->control_data); 1619 i2c_del_driver(&wm8990_i2c_driver); 1620 #endif 1621 kfree(codec->private_data); 1622 kfree(codec); 1623 1624 return 0; 1625 } 1626 1627 struct snd_soc_codec_device soc_codec_dev_wm8990 = { 1628 .probe = wm8990_probe, 1629 .remove = wm8990_remove, 1630 .suspend = wm8990_suspend, 1631 .resume = wm8990_resume, 1632 }; 1633 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990); 1634 1635 static int __init wm8990_modinit(void) 1636 { 1637 return snd_soc_register_dai(&wm8990_dai); 1638 } 1639 module_init(wm8990_modinit); 1640 1641 static void __exit wm8990_exit(void) 1642 { 1643 snd_soc_unregister_dai(&wm8990_dai); 1644 } 1645 module_exit(wm8990_exit); 1646 1647 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1648 MODULE_AUTHOR("Liam Girdwood"); 1649 MODULE_LICENSE("GPL"); 1650