1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * wm8978.h -- codec driver for WM8978 4 * 5 * Copyright 2009 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 6 */ 7 8 #ifndef __WM8978_H__ 9 #define __WM8978_H__ 10 11 /* 12 * Register values. 13 */ 14 #define WM8978_RESET 0x00 15 #define WM8978_POWER_MANAGEMENT_1 0x01 16 #define WM8978_POWER_MANAGEMENT_2 0x02 17 #define WM8978_POWER_MANAGEMENT_3 0x03 18 #define WM8978_AUDIO_INTERFACE 0x04 19 #define WM8978_COMPANDING_CONTROL 0x05 20 #define WM8978_CLOCKING 0x06 21 #define WM8978_ADDITIONAL_CONTROL 0x07 22 #define WM8978_GPIO_CONTROL 0x08 23 #define WM8978_JACK_DETECT_CONTROL_1 0x09 24 #define WM8978_DAC_CONTROL 0x0A 25 #define WM8978_LEFT_DAC_DIGITAL_VOLUME 0x0B 26 #define WM8978_RIGHT_DAC_DIGITAL_VOLUME 0x0C 27 #define WM8978_JACK_DETECT_CONTROL_2 0x0D 28 #define WM8978_ADC_CONTROL 0x0E 29 #define WM8978_LEFT_ADC_DIGITAL_VOLUME 0x0F 30 #define WM8978_RIGHT_ADC_DIGITAL_VOLUME 0x10 31 #define WM8978_EQ1 0x12 32 #define WM8978_EQ2 0x13 33 #define WM8978_EQ3 0x14 34 #define WM8978_EQ4 0x15 35 #define WM8978_EQ5 0x16 36 #define WM8978_DAC_LIMITER_1 0x18 37 #define WM8978_DAC_LIMITER_2 0x19 38 #define WM8978_NOTCH_FILTER_1 0x1b 39 #define WM8978_NOTCH_FILTER_2 0x1c 40 #define WM8978_NOTCH_FILTER_3 0x1d 41 #define WM8978_NOTCH_FILTER_4 0x1e 42 #define WM8978_ALC_CONTROL_1 0x20 43 #define WM8978_ALC_CONTROL_2 0x21 44 #define WM8978_ALC_CONTROL_3 0x22 45 #define WM8978_NOISE_GATE 0x23 46 #define WM8978_PLL_N 0x24 47 #define WM8978_PLL_K1 0x25 48 #define WM8978_PLL_K2 0x26 49 #define WM8978_PLL_K3 0x27 50 #define WM8978_3D_CONTROL 0x29 51 #define WM8978_BEEP_CONTROL 0x2b 52 #define WM8978_INPUT_CONTROL 0x2c 53 #define WM8978_LEFT_INP_PGA_CONTROL 0x2d 54 #define WM8978_RIGHT_INP_PGA_CONTROL 0x2e 55 #define WM8978_LEFT_ADC_BOOST_CONTROL 0x2f 56 #define WM8978_RIGHT_ADC_BOOST_CONTROL 0x30 57 #define WM8978_OUTPUT_CONTROL 0x31 58 #define WM8978_LEFT_MIXER_CONTROL 0x32 59 #define WM8978_RIGHT_MIXER_CONTROL 0x33 60 #define WM8978_LOUT1_HP_CONTROL 0x34 61 #define WM8978_ROUT1_HP_CONTROL 0x35 62 #define WM8978_LOUT2_SPK_CONTROL 0x36 63 #define WM8978_ROUT2_SPK_CONTROL 0x37 64 #define WM8978_OUT3_MIXER_CONTROL 0x38 65 #define WM8978_OUT4_MIXER_CONTROL 0x39 66 67 #define WM8978_MAX_REGISTER 0x39 68 69 #define WM8978_CACHEREGNUM 58 70 71 /* Clock divider Id's */ 72 enum wm8978_clk_id { 73 WM8978_OPCLKRATE, 74 WM8978_BCLKDIV, 75 }; 76 77 enum wm8978_sysclk_src { 78 WM8978_MCLK = 0, 79 WM8978_PLL, 80 }; 81 82 #endif /* __WM8978_H__ */ 83