1 /* 2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver 3 * 4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com> 6 * Copyright 2006-2009 Wolfson Microelectronics PLC. 7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <asm/div64.h> 30 31 #include "wm8978.h" 32 33 /* wm8978 register cache. Note that register 0 is not included in the cache. */ 34 static const u16 wm8978_reg[WM8978_CACHEREGNUM] = { 35 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */ 36 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */ 37 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */ 38 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */ 39 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */ 40 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */ 41 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */ 42 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */ 43 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */ 44 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */ 45 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */ 46 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */ 47 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */ 48 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */ 49 0x0001, 0x0001, /* 0x38...0x3b */ 50 }; 51 52 /* codec private data */ 53 struct wm8978_priv { 54 enum snd_soc_control_type control_type; 55 void *control_data; 56 unsigned int f_pllout; 57 unsigned int f_mclk; 58 unsigned int f_256fs; 59 unsigned int f_opclk; 60 int mclk_idx; 61 enum wm8978_sysclk_src sysclk; 62 }; 63 64 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; 65 static const char *wm8978_eqmode[] = {"Capture", "Playback"}; 66 static const char *wm8978_bw[] = {"Narrow", "Wide"}; 67 static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"}; 68 static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"}; 69 static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"}; 70 static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"}; 71 static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"}; 72 static const char *wm8978_alc3[] = {"ALC", "Limiter"}; 73 static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"}; 74 75 static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1, 76 wm8978_companding); 77 static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3, 78 wm8978_companding); 79 static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode); 80 static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1); 81 static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw); 82 static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2); 83 static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw); 84 static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3); 85 static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw); 86 static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4); 87 static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5); 88 static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3); 89 static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1); 90 91 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 92 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 93 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); 94 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); 95 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); 96 97 static const struct snd_kcontrol_new wm8978_snd_controls[] = { 98 99 SOC_SINGLE("Digital Loopback Switch", 100 WM8978_COMPANDING_CONTROL, 0, 1, 0), 101 102 SOC_ENUM("ADC Companding", adc_compand), 103 SOC_ENUM("DAC Companding", dac_compand), 104 105 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0), 106 107 SOC_DOUBLE_R_TLV("PCM Volume", 108 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME, 109 0, 255, 0, digital_tlv), 110 111 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0), 112 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0), 113 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0), 114 115 SOC_DOUBLE_R_TLV("ADC Volume", 116 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME, 117 0, 255, 0, digital_tlv), 118 119 SOC_ENUM("Equaliser Function", eqmode), 120 SOC_ENUM("EQ1 Cut Off", eq1), 121 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv), 122 123 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw), 124 SOC_ENUM("EQ2 Cut Off", eq2), 125 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv), 126 127 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw), 128 SOC_ENUM("EQ3 Cut Off", eq3), 129 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv), 130 131 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw), 132 SOC_ENUM("EQ4 Cut Off", eq4), 133 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv), 134 135 SOC_ENUM("EQ5 Cut Off", eq5), 136 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv), 137 138 SOC_SINGLE("DAC Playback Limiter Switch", 139 WM8978_DAC_LIMITER_1, 8, 1, 0), 140 SOC_SINGLE("DAC Playback Limiter Decay", 141 WM8978_DAC_LIMITER_1, 4, 15, 0), 142 SOC_SINGLE("DAC Playback Limiter Attack", 143 WM8978_DAC_LIMITER_1, 0, 15, 0), 144 145 SOC_SINGLE("DAC Playback Limiter Threshold", 146 WM8978_DAC_LIMITER_2, 4, 7, 0), 147 SOC_SINGLE("DAC Playback Limiter Boost", 148 WM8978_DAC_LIMITER_2, 0, 15, 0), 149 150 SOC_ENUM("ALC Enable Switch", alc1), 151 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0), 152 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0), 153 154 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0), 155 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0), 156 157 SOC_ENUM("ALC Capture Mode", alc3), 158 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0), 159 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0), 160 161 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0), 162 SOC_SINGLE("ALC Capture Noise Gate Threshold", 163 WM8978_NOISE_GATE, 0, 7, 0), 164 165 SOC_DOUBLE_R("Capture PGA ZC Switch", 166 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, 167 7, 1, 0), 168 169 /* OUT1 - Headphones */ 170 SOC_DOUBLE_R("Headphone Playback ZC Switch", 171 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0), 172 173 SOC_DOUBLE_R_TLV("Headphone Playback Volume", 174 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 175 0, 63, 0, spk_tlv), 176 177 /* OUT2 - Speakers */ 178 SOC_DOUBLE_R("Speaker Playback ZC Switch", 179 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0), 180 181 SOC_DOUBLE_R_TLV("Speaker Playback Volume", 182 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 183 0, 63, 0, spk_tlv), 184 185 /* OUT3/4 - Line Output */ 186 SOC_DOUBLE_R("Line Playback Switch", 187 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1), 188 189 /* Mixer #3: Boost (Input) mixer */ 190 SOC_DOUBLE_R("PGA Boost (+20dB)", 191 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 192 8, 1, 0), 193 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", 194 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 195 4, 7, 0, boost_tlv), 196 SOC_DOUBLE_R_TLV("Aux Boost Volume", 197 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 198 0, 7, 0, boost_tlv), 199 200 /* Input PGA volume */ 201 SOC_DOUBLE_R_TLV("Input PGA Volume", 202 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, 203 0, 63, 0, inpga_tlv), 204 205 /* Headphone */ 206 SOC_DOUBLE_R("Headphone Switch", 207 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1), 208 209 /* Speaker */ 210 SOC_DOUBLE_R("Speaker Switch", 211 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1), 212 213 /* DAC / ADC oversampling */ 214 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0), 215 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0), 216 }; 217 218 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */ 219 static const struct snd_kcontrol_new wm8978_left_out_mixer[] = { 220 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0), 221 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0), 222 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0), 223 }; 224 225 static const struct snd_kcontrol_new wm8978_right_out_mixer[] = { 226 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0), 227 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0), 228 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0), 229 }; 230 231 /* OUT3/OUT4 Mixer not implemented */ 232 233 /* Mixer #2: Input PGA Mute */ 234 static const struct snd_kcontrol_new wm8978_left_input_mixer[] = { 235 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0), 236 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0), 237 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0), 238 }; 239 static const struct snd_kcontrol_new wm8978_right_input_mixer[] = { 240 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0), 241 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0), 242 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0), 243 }; 244 245 static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = { 246 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", 247 WM8978_POWER_MANAGEMENT_3, 0, 0), 248 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", 249 WM8978_POWER_MANAGEMENT_3, 1, 0), 250 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", 251 WM8978_POWER_MANAGEMENT_2, 0, 0), 252 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", 253 WM8978_POWER_MANAGEMENT_2, 1, 0), 254 255 /* Mixer #1: OUT1,2 */ 256 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3, 257 2, 0, wm8978_left_out_mixer), 258 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3, 259 3, 0, wm8978_right_out_mixer), 260 261 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2, 262 2, 0, wm8978_left_input_mixer), 263 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2, 264 3, 0, wm8978_right_input_mixer), 265 266 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2, 267 4, 0, NULL, 0), 268 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2, 269 5, 0, NULL, 0), 270 271 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL, 272 6, 1, NULL, 0), 273 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL, 274 6, 1, NULL, 0), 275 276 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2, 277 7, 0, NULL, 0), 278 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2, 279 8, 0, NULL, 0), 280 281 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3, 282 6, 0, NULL, 0), 283 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3, 284 5, 0, NULL, 0), 285 286 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3, 287 8, 0, NULL, 0), 288 289 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0), 290 291 SND_SOC_DAPM_INPUT("LMICN"), 292 SND_SOC_DAPM_INPUT("LMICP"), 293 SND_SOC_DAPM_INPUT("RMICN"), 294 SND_SOC_DAPM_INPUT("RMICP"), 295 SND_SOC_DAPM_INPUT("LAUX"), 296 SND_SOC_DAPM_INPUT("RAUX"), 297 SND_SOC_DAPM_INPUT("L2"), 298 SND_SOC_DAPM_INPUT("R2"), 299 SND_SOC_DAPM_OUTPUT("LHP"), 300 SND_SOC_DAPM_OUTPUT("RHP"), 301 SND_SOC_DAPM_OUTPUT("LSPK"), 302 SND_SOC_DAPM_OUTPUT("RSPK"), 303 }; 304 305 static const struct snd_soc_dapm_route audio_map[] = { 306 /* Output mixer */ 307 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"}, 308 {"Right Output Mixer", "Aux Playback Switch", "RAUX"}, 309 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"}, 310 311 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"}, 312 {"Left Output Mixer", "Aux Playback Switch", "LAUX"}, 313 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"}, 314 315 /* Outputs */ 316 {"Right Headphone Out", NULL, "Right Output Mixer"}, 317 {"RHP", NULL, "Right Headphone Out"}, 318 319 {"Left Headphone Out", NULL, "Left Output Mixer"}, 320 {"LHP", NULL, "Left Headphone Out"}, 321 322 {"Right Speaker Out", NULL, "Right Output Mixer"}, 323 {"RSPK", NULL, "Right Speaker Out"}, 324 325 {"Left Speaker Out", NULL, "Left Output Mixer"}, 326 {"LSPK", NULL, "Left Speaker Out"}, 327 328 /* Boost Mixer */ 329 {"Right ADC", NULL, "Right Boost Mixer"}, 330 331 {"Right Boost Mixer", NULL, "RAUX"}, 332 {"Right Boost Mixer", NULL, "Right Capture PGA"}, 333 {"Right Boost Mixer", NULL, "R2"}, 334 335 {"Left ADC", NULL, "Left Boost Mixer"}, 336 337 {"Left Boost Mixer", NULL, "LAUX"}, 338 {"Left Boost Mixer", NULL, "Left Capture PGA"}, 339 {"Left Boost Mixer", NULL, "L2"}, 340 341 /* Input PGA */ 342 {"Right Capture PGA", NULL, "Right Input Mixer"}, 343 {"Left Capture PGA", NULL, "Left Input Mixer"}, 344 345 {"Right Input Mixer", "R2 Switch", "R2"}, 346 {"Right Input Mixer", "MicN Switch", "RMICN"}, 347 {"Right Input Mixer", "MicP Switch", "RMICP"}, 348 349 {"Left Input Mixer", "L2 Switch", "L2"}, 350 {"Left Input Mixer", "MicN Switch", "LMICN"}, 351 {"Left Input Mixer", "MicP Switch", "LMICP"}, 352 }; 353 354 static int wm8978_add_widgets(struct snd_soc_codec *codec) 355 { 356 struct snd_soc_dapm_context *dapm = &codec->dapm; 357 358 snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets, 359 ARRAY_SIZE(wm8978_dapm_widgets)); 360 /* set up the WM8978 audio map */ 361 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 362 363 return 0; 364 } 365 366 /* PLL divisors */ 367 struct wm8978_pll_div { 368 u32 k; 369 u8 n; 370 u8 div2; 371 }; 372 373 #define FIXED_PLL_SIZE (1 << 24) 374 375 static void pll_factors(struct snd_soc_codec *codec, 376 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source) 377 { 378 u64 k_part; 379 unsigned int k, n_div, n_mod; 380 381 n_div = target / source; 382 if (n_div < 6) { 383 source >>= 1; 384 pll_div->div2 = 1; 385 n_div = target / source; 386 } else { 387 pll_div->div2 = 0; 388 } 389 390 if (n_div < 6 || n_div > 12) 391 dev_warn(codec->dev, 392 "WM8978 N value exceeds recommended range! N = %u\n", 393 n_div); 394 395 pll_div->n = n_div; 396 n_mod = target - source * n_div; 397 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2; 398 399 do_div(k_part, source); 400 401 k = k_part & 0xFFFFFFFF; 402 403 pll_div->k = k; 404 } 405 406 /* MCLK dividers */ 407 static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12}; 408 static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1}; 409 410 /* 411 * find index >= idx, such that, for a given f_out, 412 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4 413 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be 414 * generalised for f_opclk with suitable coefficient arrays, but currently 415 * the OPCLK divisor is calculated directly, not iteratively. 416 */ 417 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk, 418 unsigned int *f_pllout) 419 { 420 int i; 421 422 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { 423 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] / 424 mclk_denominator[i]; 425 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) { 426 *f_pllout = f_pllout_x4 / 4; 427 return i; 428 } 429 } 430 431 return -EINVAL; 432 } 433 434 /* 435 * Calculate internal frequencies and dividers, according to Figure 40 436 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6 437 */ 438 static int wm8978_configure_pll(struct snd_soc_codec *codec) 439 { 440 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 441 struct wm8978_pll_div pll_div; 442 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk, 443 f_256fs = wm8978->f_256fs; 444 unsigned int f2; 445 446 if (!f_mclk) 447 return -EINVAL; 448 449 if (f_opclk) { 450 unsigned int opclk_div; 451 /* Cannot set up MCLK divider now, do later */ 452 wm8978->mclk_idx = -1; 453 454 /* 455 * The user needs OPCLK. Choose OPCLKDIV to put 456 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4. 457 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where 458 * prescale = 1, or prescale = 2. Prescale is calculated inside 459 * pll_factors(). We have to select f_PLLOUT, such that 460 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be 461 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4. 462 */ 463 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk) 464 return -EINVAL; 465 466 if (4 * f_opclk < 3 * f_mclk) 467 /* Have to use OPCLKDIV */ 468 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk; 469 else 470 opclk_div = 1; 471 472 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div); 473 474 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30, 475 (opclk_div - 1) << 4); 476 477 wm8978->f_pllout = f_opclk * opclk_div; 478 } else if (f_256fs) { 479 /* 480 * Not using OPCLK, but PLL is used for the codec, choose R: 481 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12. 482 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where 483 * prescale = 1, or prescale = 2. Prescale is calculated inside 484 * pll_factors(). We have to select f_PLLOUT, such that 485 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be 486 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK 487 * must be 3.781MHz <= f_MCLK <= 32.768MHz 488 */ 489 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout); 490 if (idx < 0) 491 return idx; 492 493 wm8978->mclk_idx = idx; 494 495 /* GPIO1 into default mode as input - before configuring PLL */ 496 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); 497 } else { 498 return -EINVAL; 499 } 500 501 f2 = wm8978->f_pllout * 4; 502 503 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__, 504 wm8978->f_mclk, wm8978->f_pllout); 505 506 pll_factors(codec, &pll_div, f2, wm8978->f_mclk); 507 508 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n", 509 __func__, pll_div.n, pll_div.k, pll_div.div2); 510 511 /* Turn PLL off for configuration... */ 512 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); 513 514 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); 515 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18); 516 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff); 517 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff); 518 519 /* ...and on again */ 520 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); 521 522 if (f_opclk) 523 /* Output PLL (OPCLK) to GPIO1 */ 524 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4); 525 526 return 0; 527 } 528 529 /* 530 * Configure WM8978 clock dividers. 531 */ 532 static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 533 int div_id, int div) 534 { 535 struct snd_soc_codec *codec = codec_dai->codec; 536 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 537 int ret = 0; 538 539 switch (div_id) { 540 case WM8978_OPCLKRATE: 541 wm8978->f_opclk = div; 542 543 if (wm8978->f_mclk) 544 /* 545 * We know the MCLK frequency, the user has requested 546 * OPCLK, configure the PLL based on that and start it 547 * and OPCLK immediately. We will configure PLL to match 548 * user-requested OPCLK frquency as good as possible. 549 * In fact, it is likely, that matching the sampling 550 * rate, when it becomes known, is more important, and 551 * we will not be reconfiguring PLL then, because we 552 * must not interrupt OPCLK. But it should be fine, 553 * because typically the user will request OPCLK to run 554 * at 256fs or 512fs, and for these cases we will also 555 * find an exact MCLK divider configuration - it will 556 * be equal to or double the OPCLK divisor. 557 */ 558 ret = wm8978_configure_pll(codec); 559 break; 560 case WM8978_BCLKDIV: 561 if (div & ~0x1c) 562 return -EINVAL; 563 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div); 564 break; 565 default: 566 return -EINVAL; 567 } 568 569 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div); 570 571 return ret; 572 } 573 574 /* 575 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency 576 */ 577 static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 578 unsigned int freq, int dir) 579 { 580 struct snd_soc_codec *codec = codec_dai->codec; 581 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 582 int ret = 0; 583 584 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq); 585 586 if (freq) { 587 wm8978->f_mclk = freq; 588 589 /* Even if MCLK is used for system clock, might have to drive OPCLK */ 590 if (wm8978->f_opclk) 591 ret = wm8978_configure_pll(codec); 592 593 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */ 594 595 if (!ret) 596 wm8978->sysclk = clk_id; 597 } 598 599 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) { 600 /* Clock CODEC directly from MCLK */ 601 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); 602 603 /* GPIO1 into default mode as input - before configuring PLL */ 604 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); 605 606 /* Turn off PLL */ 607 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); 608 wm8978->sysclk = WM8978_MCLK; 609 wm8978->f_pllout = 0; 610 wm8978->f_opclk = 0; 611 } 612 613 return ret; 614 } 615 616 /* 617 * Set ADC and Voice DAC format. 618 */ 619 static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 620 { 621 struct snd_soc_codec *codec = codec_dai->codec; 622 /* 623 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, 624 * Data Format mask = 0x18: all will be calculated anew 625 */ 626 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198; 627 u16 clk = snd_soc_read(codec, WM8978_CLOCKING); 628 629 dev_dbg(codec->dev, "%s\n", __func__); 630 631 /* set master/slave audio interface */ 632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 633 case SND_SOC_DAIFMT_CBM_CFM: 634 clk |= 1; 635 break; 636 case SND_SOC_DAIFMT_CBS_CFS: 637 clk &= ~1; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 /* interface format */ 644 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 645 case SND_SOC_DAIFMT_I2S: 646 iface |= 0x10; 647 break; 648 case SND_SOC_DAIFMT_RIGHT_J: 649 break; 650 case SND_SOC_DAIFMT_LEFT_J: 651 iface |= 0x8; 652 break; 653 case SND_SOC_DAIFMT_DSP_A: 654 iface |= 0x18; 655 break; 656 default: 657 return -EINVAL; 658 } 659 660 /* clock inversion */ 661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 662 case SND_SOC_DAIFMT_NB_NF: 663 break; 664 case SND_SOC_DAIFMT_IB_IF: 665 iface |= 0x180; 666 break; 667 case SND_SOC_DAIFMT_IB_NF: 668 iface |= 0x100; 669 break; 670 case SND_SOC_DAIFMT_NB_IF: 671 iface |= 0x80; 672 break; 673 default: 674 return -EINVAL; 675 } 676 677 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface); 678 snd_soc_write(codec, WM8978_CLOCKING, clk); 679 680 return 0; 681 } 682 683 /* 684 * Set PCM DAI bit size and sample rate. 685 */ 686 static int wm8978_hw_params(struct snd_pcm_substream *substream, 687 struct snd_pcm_hw_params *params, 688 struct snd_soc_dai *dai) 689 { 690 struct snd_soc_pcm_runtime *rtd = substream->private_data; 691 struct snd_soc_codec *codec = rtd->codec; 692 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 693 /* Word length mask = 0x60 */ 694 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60; 695 /* Sampling rate mask = 0xe (for filters) */ 696 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe; 697 u16 clking = snd_soc_read(codec, WM8978_CLOCKING); 698 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ? 699 WM8978_PLL : WM8978_MCLK; 700 unsigned int f_sel, diff, diff_best = INT_MAX; 701 int i, best = 0; 702 703 if (!wm8978->f_mclk) 704 return -EINVAL; 705 706 /* bit size */ 707 switch (params_format(params)) { 708 case SNDRV_PCM_FORMAT_S16_LE: 709 break; 710 case SNDRV_PCM_FORMAT_S20_3LE: 711 iface_ctl |= 0x20; 712 break; 713 case SNDRV_PCM_FORMAT_S24_LE: 714 iface_ctl |= 0x40; 715 break; 716 case SNDRV_PCM_FORMAT_S32_LE: 717 iface_ctl |= 0x60; 718 break; 719 } 720 721 /* filter coefficient */ 722 switch (params_rate(params)) { 723 case 8000: 724 add_ctl |= 0x5 << 1; 725 break; 726 case 11025: 727 add_ctl |= 0x4 << 1; 728 break; 729 case 16000: 730 add_ctl |= 0x3 << 1; 731 break; 732 case 22050: 733 add_ctl |= 0x2 << 1; 734 break; 735 case 32000: 736 add_ctl |= 0x1 << 1; 737 break; 738 case 44100: 739 case 48000: 740 break; 741 } 742 743 /* Sampling rate is known now, can configure the MCLK divider */ 744 wm8978->f_256fs = params_rate(params) * 256; 745 746 if (wm8978->sysclk == WM8978_MCLK) { 747 wm8978->mclk_idx = -1; 748 f_sel = wm8978->f_mclk; 749 } else { 750 if (!wm8978->f_pllout) { 751 /* We only enter here, if OPCLK is not used */ 752 int ret = wm8978_configure_pll(codec); 753 if (ret < 0) 754 return ret; 755 } 756 f_sel = wm8978->f_pllout; 757 } 758 759 if (wm8978->mclk_idx < 0) { 760 /* Either MCLK is used directly, or OPCLK is used */ 761 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs) 762 return -EINVAL; 763 764 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { 765 diff = abs(wm8978->f_256fs * 3 - 766 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]); 767 768 if (diff < diff_best) { 769 diff_best = diff; 770 best = i; 771 } 772 773 if (!diff) 774 break; 775 } 776 } else { 777 /* OPCLK not used, codec driven by PLL */ 778 best = wm8978->mclk_idx; 779 diff = 0; 780 } 781 782 if (diff) 783 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n", 784 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256, 785 wm8978->sysclk == WM8978_MCLK ? 786 ", consider using PLL" : ""); 787 788 dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__, 789 params_format(params), params_rate(params), best); 790 791 /* MCLK divisor mask = 0xe0 */ 792 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5); 793 794 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl); 795 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl); 796 797 if (wm8978->sysclk != current_clk_id) { 798 if (wm8978->sysclk == WM8978_PLL) 799 /* Run CODEC from PLL instead of MCLK */ 800 snd_soc_update_bits(codec, WM8978_CLOCKING, 801 0x100, 0x100); 802 else 803 /* Clock CODEC directly from MCLK */ 804 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); 805 } 806 807 return 0; 808 } 809 810 static int wm8978_mute(struct snd_soc_dai *dai, int mute) 811 { 812 struct snd_soc_codec *codec = dai->codec; 813 814 dev_dbg(codec->dev, "%s: %d\n", __func__, mute); 815 816 if (mute) 817 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40); 818 else 819 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0); 820 821 return 0; 822 } 823 824 static int wm8978_set_bias_level(struct snd_soc_codec *codec, 825 enum snd_soc_bias_level level) 826 { 827 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3; 828 829 switch (level) { 830 case SND_SOC_BIAS_ON: 831 case SND_SOC_BIAS_PREPARE: 832 power1 |= 1; /* VMID 75k */ 833 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); 834 break; 835 case SND_SOC_BIAS_STANDBY: 836 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ 837 power1 |= 0xc; 838 839 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 840 /* Initial cap charge at VMID 5k */ 841 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 842 power1 | 0x3); 843 mdelay(100); 844 } 845 846 power1 |= 0x2; /* VMID 500k */ 847 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); 848 break; 849 case SND_SOC_BIAS_OFF: 850 /* Preserve PLL - OPCLK may be used by someone */ 851 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0); 852 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0); 853 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0); 854 break; 855 } 856 857 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); 858 859 codec->dapm.bias_level = level; 860 return 0; 861 } 862 863 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 864 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 865 866 static struct snd_soc_dai_ops wm8978_dai_ops = { 867 .hw_params = wm8978_hw_params, 868 .digital_mute = wm8978_mute, 869 .set_fmt = wm8978_set_dai_fmt, 870 .set_clkdiv = wm8978_set_dai_clkdiv, 871 .set_sysclk = wm8978_set_dai_sysclk, 872 }; 873 874 /* Also supports 12kHz */ 875 static struct snd_soc_dai_driver wm8978_dai = { 876 .name = "wm8978-hifi", 877 .playback = { 878 .stream_name = "Playback", 879 .channels_min = 1, 880 .channels_max = 2, 881 .rates = SNDRV_PCM_RATE_8000_48000, 882 .formats = WM8978_FORMATS, 883 }, 884 .capture = { 885 .stream_name = "Capture", 886 .channels_min = 1, 887 .channels_max = 2, 888 .rates = SNDRV_PCM_RATE_8000_48000, 889 .formats = WM8978_FORMATS, 890 }, 891 .ops = &wm8978_dai_ops, 892 }; 893 894 static int wm8978_suspend(struct snd_soc_codec *codec, pm_message_t state) 895 { 896 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); 897 /* Also switch PLL off */ 898 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0); 899 900 return 0; 901 } 902 903 static int wm8978_resume(struct snd_soc_codec *codec) 904 { 905 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 906 int i; 907 u16 *cache = codec->reg_cache; 908 909 /* Sync reg_cache with the hardware */ 910 for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) { 911 if (i == WM8978_RESET) 912 continue; 913 if (cache[i] != wm8978_reg[i]) 914 snd_soc_write(codec, i, cache[i]); 915 } 916 917 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 918 919 if (wm8978->f_pllout) 920 /* Switch PLL on */ 921 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); 922 923 return 0; 924 } 925 926 /* 927 * These registers contain an "update" bit - bit 8. This means, for example, 928 * that one can write new DAC digital volume for both channels, but only when 929 * the update bit is set, will also the volume be updated - simultaneously for 930 * both channels. 931 */ 932 static const int update_reg[] = { 933 WM8978_LEFT_DAC_DIGITAL_VOLUME, 934 WM8978_RIGHT_DAC_DIGITAL_VOLUME, 935 WM8978_LEFT_ADC_DIGITAL_VOLUME, 936 WM8978_RIGHT_ADC_DIGITAL_VOLUME, 937 WM8978_LEFT_INP_PGA_CONTROL, 938 WM8978_RIGHT_INP_PGA_CONTROL, 939 WM8978_LOUT1_HP_CONTROL, 940 WM8978_ROUT1_HP_CONTROL, 941 WM8978_LOUT2_SPK_CONTROL, 942 WM8978_ROUT2_SPK_CONTROL, 943 }; 944 945 static int wm8978_probe(struct snd_soc_codec *codec) 946 { 947 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 948 int ret = 0, i; 949 950 /* 951 * Set default system clock to PLL, it is more precise, this is also the 952 * default hardware setting 953 */ 954 wm8978->sysclk = WM8978_PLL; 955 codec->control_data = wm8978->control_data; 956 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C); 957 if (ret < 0) { 958 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 959 return ret; 960 } 961 962 /* 963 * Set the update bit in all registers, that have one. This way all 964 * writes to those registers will also cause the update bit to be 965 * written. 966 */ 967 for (i = 0; i < ARRAY_SIZE(update_reg); i++) 968 ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100; 969 970 /* Reset the codec */ 971 ret = snd_soc_write(codec, WM8978_RESET, 0); 972 if (ret < 0) { 973 dev_err(codec->dev, "Failed to issue reset\n"); 974 return ret; 975 } 976 977 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 978 979 snd_soc_add_controls(codec, wm8978_snd_controls, 980 ARRAY_SIZE(wm8978_snd_controls)); 981 wm8978_add_widgets(codec); 982 983 return 0; 984 } 985 986 /* power down chip */ 987 static int wm8978_remove(struct snd_soc_codec *codec) 988 { 989 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); 990 return 0; 991 } 992 993 static struct snd_soc_codec_driver soc_codec_dev_wm8978 = { 994 .probe = wm8978_probe, 995 .remove = wm8978_remove, 996 .suspend = wm8978_suspend, 997 .resume = wm8978_resume, 998 .set_bias_level = wm8978_set_bias_level, 999 .reg_cache_size = ARRAY_SIZE(wm8978_reg), 1000 .reg_word_size = sizeof(u16), 1001 .reg_cache_default = wm8978_reg, 1002 }; 1003 1004 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1005 static __devinit int wm8978_i2c_probe(struct i2c_client *i2c, 1006 const struct i2c_device_id *id) 1007 { 1008 struct wm8978_priv *wm8978; 1009 int ret; 1010 1011 wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL); 1012 if (wm8978 == NULL) 1013 return -ENOMEM; 1014 1015 i2c_set_clientdata(i2c, wm8978); 1016 wm8978->control_data = i2c; 1017 1018 ret = snd_soc_register_codec(&i2c->dev, 1019 &soc_codec_dev_wm8978, &wm8978_dai, 1); 1020 if (ret < 0) 1021 kfree(wm8978); 1022 return ret; 1023 } 1024 1025 static __devexit int wm8978_i2c_remove(struct i2c_client *client) 1026 { 1027 snd_soc_unregister_codec(&client->dev); 1028 kfree(i2c_get_clientdata(client)); 1029 return 0; 1030 } 1031 1032 static const struct i2c_device_id wm8978_i2c_id[] = { 1033 { "wm8978", 0 }, 1034 { } 1035 }; 1036 MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); 1037 1038 static struct i2c_driver wm8978_i2c_driver = { 1039 .driver = { 1040 .name = "wm8978", 1041 .owner = THIS_MODULE, 1042 }, 1043 .probe = wm8978_i2c_probe, 1044 .remove = __devexit_p(wm8978_i2c_remove), 1045 .id_table = wm8978_i2c_id, 1046 }; 1047 #endif 1048 1049 static int __init wm8978_modinit(void) 1050 { 1051 int ret = 0; 1052 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1053 ret = i2c_add_driver(&wm8978_i2c_driver); 1054 if (ret != 0) { 1055 printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n", 1056 ret); 1057 } 1058 #endif 1059 return ret; 1060 } 1061 module_init(wm8978_modinit); 1062 1063 static void __exit wm8978_exit(void) 1064 { 1065 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1066 i2c_del_driver(&wm8978_i2c_driver); 1067 #endif 1068 } 1069 module_exit(wm8978_exit); 1070 1071 MODULE_DESCRIPTION("ASoC WM8978 codec driver"); 1072 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); 1073 MODULE_LICENSE("GPL"); 1074