1 /* 2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver 3 * 4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com> 6 * Copyright 2006-2009 Wolfson Microelectronics PLC. 7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <asm/div64.h> 31 32 #include "wm8978.h" 33 34 /* wm8978 register cache. Note that register 0 is not included in the cache. */ 35 static const u16 wm8978_reg[WM8978_CACHEREGNUM] = { 36 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */ 37 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */ 38 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */ 39 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */ 40 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */ 41 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */ 42 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */ 43 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */ 44 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */ 45 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */ 46 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */ 47 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */ 48 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */ 49 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */ 50 0x0001, 0x0001, /* 0x38...0x3b */ 51 }; 52 53 /* codec private data */ 54 struct wm8978_priv { 55 enum snd_soc_control_type control_type; 56 void *control_data; 57 unsigned int f_pllout; 58 unsigned int f_mclk; 59 unsigned int f_256fs; 60 unsigned int f_opclk; 61 int mclk_idx; 62 enum wm8978_sysclk_src sysclk; 63 u16 reg_cache[WM8978_CACHEREGNUM]; 64 }; 65 66 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; 67 static const char *wm8978_eqmode[] = {"Capture", "Playback"}; 68 static const char *wm8978_bw[] = {"Narrow", "Wide"}; 69 static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"}; 70 static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"}; 71 static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"}; 72 static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"}; 73 static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"}; 74 static const char *wm8978_alc3[] = {"ALC", "Limiter"}; 75 static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"}; 76 77 static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1, 78 wm8978_companding); 79 static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3, 80 wm8978_companding); 81 static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode); 82 static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1); 83 static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw); 84 static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2); 85 static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw); 86 static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3); 87 static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw); 88 static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4); 89 static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5); 90 static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3); 91 static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1); 92 93 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 94 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 95 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); 96 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); 97 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); 98 99 static const struct snd_kcontrol_new wm8978_snd_controls[] = { 100 101 SOC_SINGLE("Digital Loopback Switch", 102 WM8978_COMPANDING_CONTROL, 0, 1, 0), 103 104 SOC_ENUM("ADC Companding", adc_compand), 105 SOC_ENUM("DAC Companding", dac_compand), 106 107 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0), 108 109 SOC_DOUBLE_R_TLV("PCM Volume", 110 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME, 111 0, 255, 0, digital_tlv), 112 113 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0), 114 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0), 115 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0), 116 117 SOC_DOUBLE_R_TLV("ADC Volume", 118 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME, 119 0, 255, 0, digital_tlv), 120 121 SOC_ENUM("Equaliser Function", eqmode), 122 SOC_ENUM("EQ1 Cut Off", eq1), 123 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv), 124 125 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw), 126 SOC_ENUM("EQ2 Cut Off", eq2), 127 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv), 128 129 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw), 130 SOC_ENUM("EQ3 Cut Off", eq3), 131 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv), 132 133 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw), 134 SOC_ENUM("EQ4 Cut Off", eq4), 135 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv), 136 137 SOC_ENUM("EQ5 Cut Off", eq5), 138 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv), 139 140 SOC_SINGLE("DAC Playback Limiter Switch", 141 WM8978_DAC_LIMITER_1, 8, 1, 0), 142 SOC_SINGLE("DAC Playback Limiter Decay", 143 WM8978_DAC_LIMITER_1, 4, 15, 0), 144 SOC_SINGLE("DAC Playback Limiter Attack", 145 WM8978_DAC_LIMITER_1, 0, 15, 0), 146 147 SOC_SINGLE("DAC Playback Limiter Threshold", 148 WM8978_DAC_LIMITER_2, 4, 7, 0), 149 SOC_SINGLE("DAC Playback Limiter Boost", 150 WM8978_DAC_LIMITER_2, 0, 15, 0), 151 152 SOC_ENUM("ALC Enable Switch", alc1), 153 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0), 154 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0), 155 156 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0), 157 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0), 158 159 SOC_ENUM("ALC Capture Mode", alc3), 160 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0), 161 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0), 162 163 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0), 164 SOC_SINGLE("ALC Capture Noise Gate Threshold", 165 WM8978_NOISE_GATE, 0, 7, 0), 166 167 SOC_DOUBLE_R("Capture PGA ZC Switch", 168 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, 169 7, 1, 0), 170 171 /* OUT1 - Headphones */ 172 SOC_DOUBLE_R("Headphone Playback ZC Switch", 173 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0), 174 175 SOC_DOUBLE_R_TLV("Headphone Playback Volume", 176 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 177 0, 63, 0, spk_tlv), 178 179 /* OUT2 - Speakers */ 180 SOC_DOUBLE_R("Speaker Playback ZC Switch", 181 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0), 182 183 SOC_DOUBLE_R_TLV("Speaker Playback Volume", 184 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 185 0, 63, 0, spk_tlv), 186 187 /* OUT3/4 - Line Output */ 188 SOC_DOUBLE_R("Line Playback Switch", 189 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1), 190 191 /* Mixer #3: Boost (Input) mixer */ 192 SOC_DOUBLE_R("PGA Boost (+20dB)", 193 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 194 8, 1, 0), 195 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", 196 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 197 4, 7, 0, boost_tlv), 198 SOC_DOUBLE_R_TLV("Aux Boost Volume", 199 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL, 200 0, 7, 0, boost_tlv), 201 202 /* Input PGA volume */ 203 SOC_DOUBLE_R_TLV("Input PGA Volume", 204 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL, 205 0, 63, 0, inpga_tlv), 206 207 /* Headphone */ 208 SOC_DOUBLE_R("Headphone Switch", 209 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1), 210 211 /* Speaker */ 212 SOC_DOUBLE_R("Speaker Switch", 213 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1), 214 215 /* DAC / ADC oversampling */ 216 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0), 217 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0), 218 }; 219 220 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */ 221 static const struct snd_kcontrol_new wm8978_left_out_mixer[] = { 222 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0), 223 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0), 224 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0), 225 }; 226 227 static const struct snd_kcontrol_new wm8978_right_out_mixer[] = { 228 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0), 229 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0), 230 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0), 231 }; 232 233 /* OUT3/OUT4 Mixer not implemented */ 234 235 /* Mixer #2: Input PGA Mute */ 236 static const struct snd_kcontrol_new wm8978_left_input_mixer[] = { 237 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0), 238 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0), 239 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0), 240 }; 241 static const struct snd_kcontrol_new wm8978_right_input_mixer[] = { 242 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0), 243 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0), 244 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0), 245 }; 246 247 static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = { 248 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", 249 WM8978_POWER_MANAGEMENT_3, 0, 0), 250 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", 251 WM8978_POWER_MANAGEMENT_3, 1, 0), 252 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", 253 WM8978_POWER_MANAGEMENT_2, 0, 0), 254 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", 255 WM8978_POWER_MANAGEMENT_2, 1, 0), 256 257 /* Mixer #1: OUT1,2 */ 258 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3, 259 2, 0, wm8978_left_out_mixer), 260 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3, 261 3, 0, wm8978_right_out_mixer), 262 263 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2, 264 2, 0, wm8978_left_input_mixer), 265 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2, 266 3, 0, wm8978_right_input_mixer), 267 268 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2, 269 4, 0, NULL, 0), 270 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2, 271 5, 0, NULL, 0), 272 273 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL, 274 6, 1, NULL, 0), 275 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL, 276 6, 1, NULL, 0), 277 278 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2, 279 7, 0, NULL, 0), 280 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2, 281 8, 0, NULL, 0), 282 283 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3, 284 6, 0, NULL, 0), 285 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3, 286 5, 0, NULL, 0), 287 288 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3, 289 8, 0, NULL, 0), 290 291 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0), 292 293 SND_SOC_DAPM_INPUT("LMICN"), 294 SND_SOC_DAPM_INPUT("LMICP"), 295 SND_SOC_DAPM_INPUT("RMICN"), 296 SND_SOC_DAPM_INPUT("RMICP"), 297 SND_SOC_DAPM_INPUT("LAUX"), 298 SND_SOC_DAPM_INPUT("RAUX"), 299 SND_SOC_DAPM_INPUT("L2"), 300 SND_SOC_DAPM_INPUT("R2"), 301 SND_SOC_DAPM_OUTPUT("LHP"), 302 SND_SOC_DAPM_OUTPUT("RHP"), 303 SND_SOC_DAPM_OUTPUT("LSPK"), 304 SND_SOC_DAPM_OUTPUT("RSPK"), 305 }; 306 307 static const struct snd_soc_dapm_route audio_map[] = { 308 /* Output mixer */ 309 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"}, 310 {"Right Output Mixer", "Aux Playback Switch", "RAUX"}, 311 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"}, 312 313 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"}, 314 {"Left Output Mixer", "Aux Playback Switch", "LAUX"}, 315 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"}, 316 317 /* Outputs */ 318 {"Right Headphone Out", NULL, "Right Output Mixer"}, 319 {"RHP", NULL, "Right Headphone Out"}, 320 321 {"Left Headphone Out", NULL, "Left Output Mixer"}, 322 {"LHP", NULL, "Left Headphone Out"}, 323 324 {"Right Speaker Out", NULL, "Right Output Mixer"}, 325 {"RSPK", NULL, "Right Speaker Out"}, 326 327 {"Left Speaker Out", NULL, "Left Output Mixer"}, 328 {"LSPK", NULL, "Left Speaker Out"}, 329 330 /* Boost Mixer */ 331 {"Right ADC", NULL, "Right Boost Mixer"}, 332 333 {"Right Boost Mixer", NULL, "RAUX"}, 334 {"Right Boost Mixer", NULL, "Right Capture PGA"}, 335 {"Right Boost Mixer", NULL, "R2"}, 336 337 {"Left ADC", NULL, "Left Boost Mixer"}, 338 339 {"Left Boost Mixer", NULL, "LAUX"}, 340 {"Left Boost Mixer", NULL, "Left Capture PGA"}, 341 {"Left Boost Mixer", NULL, "L2"}, 342 343 /* Input PGA */ 344 {"Right Capture PGA", NULL, "Right Input Mixer"}, 345 {"Left Capture PGA", NULL, "Left Input Mixer"}, 346 347 {"Right Input Mixer", "R2 Switch", "R2"}, 348 {"Right Input Mixer", "MicN Switch", "RMICN"}, 349 {"Right Input Mixer", "MicP Switch", "RMICP"}, 350 351 {"Left Input Mixer", "L2 Switch", "L2"}, 352 {"Left Input Mixer", "MicN Switch", "LMICN"}, 353 {"Left Input Mixer", "MicP Switch", "LMICP"}, 354 }; 355 356 static int wm8978_add_widgets(struct snd_soc_codec *codec) 357 { 358 snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets, 359 ARRAY_SIZE(wm8978_dapm_widgets)); 360 361 /* set up the WM8978 audio map */ 362 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 363 364 return 0; 365 } 366 367 /* PLL divisors */ 368 struct wm8978_pll_div { 369 u32 k; 370 u8 n; 371 u8 div2; 372 }; 373 374 #define FIXED_PLL_SIZE (1 << 24) 375 376 static void pll_factors(struct snd_soc_codec *codec, 377 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source) 378 { 379 u64 k_part; 380 unsigned int k, n_div, n_mod; 381 382 n_div = target / source; 383 if (n_div < 6) { 384 source >>= 1; 385 pll_div->div2 = 1; 386 n_div = target / source; 387 } else { 388 pll_div->div2 = 0; 389 } 390 391 if (n_div < 6 || n_div > 12) 392 dev_warn(codec->dev, 393 "WM8978 N value exceeds recommended range! N = %u\n", 394 n_div); 395 396 pll_div->n = n_div; 397 n_mod = target - source * n_div; 398 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2; 399 400 do_div(k_part, source); 401 402 k = k_part & 0xFFFFFFFF; 403 404 pll_div->k = k; 405 } 406 407 /* MCLK dividers */ 408 static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12}; 409 static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1}; 410 411 /* 412 * find index >= idx, such that, for a given f_out, 413 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4 414 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be 415 * generalised for f_opclk with suitable coefficient arrays, but currently 416 * the OPCLK divisor is calculated directly, not iteratively. 417 */ 418 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk, 419 unsigned int *f_pllout) 420 { 421 int i; 422 423 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { 424 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] / 425 mclk_denominator[i]; 426 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) { 427 *f_pllout = f_pllout_x4 / 4; 428 return i; 429 } 430 } 431 432 return -EINVAL; 433 } 434 435 /* 436 * Calculate internal frequencies and dividers, according to Figure 40 437 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6 438 */ 439 static int wm8978_configure_pll(struct snd_soc_codec *codec) 440 { 441 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 442 struct wm8978_pll_div pll_div; 443 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk, 444 f_256fs = wm8978->f_256fs; 445 unsigned int f2; 446 447 if (!f_mclk) 448 return -EINVAL; 449 450 if (f_opclk) { 451 unsigned int opclk_div; 452 /* Cannot set up MCLK divider now, do later */ 453 wm8978->mclk_idx = -1; 454 455 /* 456 * The user needs OPCLK. Choose OPCLKDIV to put 457 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4. 458 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where 459 * prescale = 1, or prescale = 2. Prescale is calculated inside 460 * pll_factors(). We have to select f_PLLOUT, such that 461 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be 462 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4. 463 */ 464 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk) 465 return -EINVAL; 466 467 if (4 * f_opclk < 3 * f_mclk) 468 /* Have to use OPCLKDIV */ 469 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk; 470 else 471 opclk_div = 1; 472 473 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div); 474 475 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30, 476 (opclk_div - 1) << 4); 477 478 wm8978->f_pllout = f_opclk * opclk_div; 479 } else if (f_256fs) { 480 /* 481 * Not using OPCLK, but PLL is used for the codec, choose R: 482 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12. 483 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where 484 * prescale = 1, or prescale = 2. Prescale is calculated inside 485 * pll_factors(). We have to select f_PLLOUT, such that 486 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be 487 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK 488 * must be 3.781MHz <= f_MCLK <= 32.768MHz 489 */ 490 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout); 491 if (idx < 0) 492 return idx; 493 494 wm8978->mclk_idx = idx; 495 496 /* GPIO1 into default mode as input - before configuring PLL */ 497 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); 498 } else { 499 return -EINVAL; 500 } 501 502 f2 = wm8978->f_pllout * 4; 503 504 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__, 505 wm8978->f_mclk, wm8978->f_pllout); 506 507 pll_factors(codec, &pll_div, f2, wm8978->f_mclk); 508 509 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n", 510 __func__, pll_div.n, pll_div.k, pll_div.div2); 511 512 /* Turn PLL off for configuration... */ 513 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); 514 515 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); 516 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18); 517 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff); 518 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff); 519 520 /* ...and on again */ 521 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); 522 523 if (f_opclk) 524 /* Output PLL (OPCLK) to GPIO1 */ 525 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4); 526 527 return 0; 528 } 529 530 /* 531 * Configure WM8978 clock dividers. 532 */ 533 static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 534 int div_id, int div) 535 { 536 struct snd_soc_codec *codec = codec_dai->codec; 537 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 538 int ret = 0; 539 540 switch (div_id) { 541 case WM8978_OPCLKRATE: 542 wm8978->f_opclk = div; 543 544 if (wm8978->f_mclk) 545 /* 546 * We know the MCLK frequency, the user has requested 547 * OPCLK, configure the PLL based on that and start it 548 * and OPCLK immediately. We will configure PLL to match 549 * user-requested OPCLK frquency as good as possible. 550 * In fact, it is likely, that matching the sampling 551 * rate, when it becomes known, is more important, and 552 * we will not be reconfiguring PLL then, because we 553 * must not interrupt OPCLK. But it should be fine, 554 * because typically the user will request OPCLK to run 555 * at 256fs or 512fs, and for these cases we will also 556 * find an exact MCLK divider configuration - it will 557 * be equal to or double the OPCLK divisor. 558 */ 559 ret = wm8978_configure_pll(codec); 560 break; 561 case WM8978_BCLKDIV: 562 if (div & ~0x1c) 563 return -EINVAL; 564 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div); 565 break; 566 default: 567 return -EINVAL; 568 } 569 570 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div); 571 572 return ret; 573 } 574 575 /* 576 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency 577 */ 578 static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 579 unsigned int freq, int dir) 580 { 581 struct snd_soc_codec *codec = codec_dai->codec; 582 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 583 int ret = 0; 584 585 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq); 586 587 if (freq) { 588 wm8978->f_mclk = freq; 589 590 /* Even if MCLK is used for system clock, might have to drive OPCLK */ 591 if (wm8978->f_opclk) 592 ret = wm8978_configure_pll(codec); 593 594 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */ 595 596 if (!ret) 597 wm8978->sysclk = clk_id; 598 } 599 600 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) { 601 /* Clock CODEC directly from MCLK */ 602 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); 603 604 /* GPIO1 into default mode as input - before configuring PLL */ 605 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); 606 607 /* Turn off PLL */ 608 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0); 609 wm8978->sysclk = WM8978_MCLK; 610 wm8978->f_pllout = 0; 611 wm8978->f_opclk = 0; 612 } 613 614 return ret; 615 } 616 617 /* 618 * Set ADC and Voice DAC format. 619 */ 620 static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 621 { 622 struct snd_soc_codec *codec = codec_dai->codec; 623 /* 624 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, 625 * Data Format mask = 0x18: all will be calculated anew 626 */ 627 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198; 628 u16 clk = snd_soc_read(codec, WM8978_CLOCKING); 629 630 dev_dbg(codec->dev, "%s\n", __func__); 631 632 /* set master/slave audio interface */ 633 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 634 case SND_SOC_DAIFMT_CBM_CFM: 635 clk |= 1; 636 break; 637 case SND_SOC_DAIFMT_CBS_CFS: 638 clk &= ~1; 639 break; 640 default: 641 return -EINVAL; 642 } 643 644 /* interface format */ 645 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 646 case SND_SOC_DAIFMT_I2S: 647 iface |= 0x10; 648 break; 649 case SND_SOC_DAIFMT_RIGHT_J: 650 break; 651 case SND_SOC_DAIFMT_LEFT_J: 652 iface |= 0x8; 653 break; 654 case SND_SOC_DAIFMT_DSP_A: 655 iface |= 0x18; 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 /* clock inversion */ 662 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 663 case SND_SOC_DAIFMT_NB_NF: 664 break; 665 case SND_SOC_DAIFMT_IB_IF: 666 iface |= 0x180; 667 break; 668 case SND_SOC_DAIFMT_IB_NF: 669 iface |= 0x100; 670 break; 671 case SND_SOC_DAIFMT_NB_IF: 672 iface |= 0x80; 673 break; 674 default: 675 return -EINVAL; 676 } 677 678 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface); 679 snd_soc_write(codec, WM8978_CLOCKING, clk); 680 681 return 0; 682 } 683 684 /* 685 * Set PCM DAI bit size and sample rate. 686 */ 687 static int wm8978_hw_params(struct snd_pcm_substream *substream, 688 struct snd_pcm_hw_params *params, 689 struct snd_soc_dai *dai) 690 { 691 struct snd_soc_pcm_runtime *rtd = substream->private_data; 692 struct snd_soc_codec *codec = rtd->codec; 693 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 694 /* Word length mask = 0x60 */ 695 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60; 696 /* Sampling rate mask = 0xe (for filters) */ 697 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe; 698 u16 clking = snd_soc_read(codec, WM8978_CLOCKING); 699 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ? 700 WM8978_PLL : WM8978_MCLK; 701 unsigned int f_sel, diff, diff_best = INT_MAX; 702 int i, best = 0; 703 704 if (!wm8978->f_mclk) 705 return -EINVAL; 706 707 /* bit size */ 708 switch (params_format(params)) { 709 case SNDRV_PCM_FORMAT_S16_LE: 710 break; 711 case SNDRV_PCM_FORMAT_S20_3LE: 712 iface_ctl |= 0x20; 713 break; 714 case SNDRV_PCM_FORMAT_S24_LE: 715 iface_ctl |= 0x40; 716 break; 717 case SNDRV_PCM_FORMAT_S32_LE: 718 iface_ctl |= 0x60; 719 break; 720 } 721 722 /* filter coefficient */ 723 switch (params_rate(params)) { 724 case 8000: 725 add_ctl |= 0x5 << 1; 726 break; 727 case 11025: 728 add_ctl |= 0x4 << 1; 729 break; 730 case 16000: 731 add_ctl |= 0x3 << 1; 732 break; 733 case 22050: 734 add_ctl |= 0x2 << 1; 735 break; 736 case 32000: 737 add_ctl |= 0x1 << 1; 738 break; 739 case 44100: 740 case 48000: 741 break; 742 } 743 744 /* Sampling rate is known now, can configure the MCLK divider */ 745 wm8978->f_256fs = params_rate(params) * 256; 746 747 if (wm8978->sysclk == WM8978_MCLK) { 748 wm8978->mclk_idx = -1; 749 f_sel = wm8978->f_mclk; 750 } else { 751 if (!wm8978->f_pllout) { 752 /* We only enter here, if OPCLK is not used */ 753 int ret = wm8978_configure_pll(codec); 754 if (ret < 0) 755 return ret; 756 } 757 f_sel = wm8978->f_pllout; 758 } 759 760 if (wm8978->mclk_idx < 0) { 761 /* Either MCLK is used directly, or OPCLK is used */ 762 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs) 763 return -EINVAL; 764 765 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) { 766 diff = abs(wm8978->f_256fs * 3 - 767 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]); 768 769 if (diff < diff_best) { 770 diff_best = diff; 771 best = i; 772 } 773 774 if (!diff) 775 break; 776 } 777 } else { 778 /* OPCLK not used, codec driven by PLL */ 779 best = wm8978->mclk_idx; 780 diff = 0; 781 } 782 783 if (diff) 784 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n", 785 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256, 786 wm8978->sysclk == WM8978_MCLK ? 787 ", consider using PLL" : ""); 788 789 dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__, 790 params_format(params), params_rate(params), best); 791 792 /* MCLK divisor mask = 0xe0 */ 793 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5); 794 795 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl); 796 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl); 797 798 if (wm8978->sysclk != current_clk_id) { 799 if (wm8978->sysclk == WM8978_PLL) 800 /* Run CODEC from PLL instead of MCLK */ 801 snd_soc_update_bits(codec, WM8978_CLOCKING, 802 0x100, 0x100); 803 else 804 /* Clock CODEC directly from MCLK */ 805 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0); 806 } 807 808 return 0; 809 } 810 811 static int wm8978_mute(struct snd_soc_dai *dai, int mute) 812 { 813 struct snd_soc_codec *codec = dai->codec; 814 815 dev_dbg(codec->dev, "%s: %d\n", __func__, mute); 816 817 if (mute) 818 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40); 819 else 820 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0); 821 822 return 0; 823 } 824 825 static int wm8978_set_bias_level(struct snd_soc_codec *codec, 826 enum snd_soc_bias_level level) 827 { 828 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3; 829 830 switch (level) { 831 case SND_SOC_BIAS_ON: 832 case SND_SOC_BIAS_PREPARE: 833 power1 |= 1; /* VMID 75k */ 834 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); 835 break; 836 case SND_SOC_BIAS_STANDBY: 837 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ 838 power1 |= 0xc; 839 840 if (codec->bias_level == SND_SOC_BIAS_OFF) { 841 /* Initial cap charge at VMID 5k */ 842 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 843 power1 | 0x3); 844 mdelay(100); 845 } 846 847 power1 |= 0x2; /* VMID 500k */ 848 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1); 849 break; 850 case SND_SOC_BIAS_OFF: 851 /* Preserve PLL - OPCLK may be used by someone */ 852 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0); 853 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0); 854 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0); 855 break; 856 } 857 858 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); 859 860 codec->bias_level = level; 861 return 0; 862 } 863 864 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 865 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 866 867 static struct snd_soc_dai_ops wm8978_dai_ops = { 868 .hw_params = wm8978_hw_params, 869 .digital_mute = wm8978_mute, 870 .set_fmt = wm8978_set_dai_fmt, 871 .set_clkdiv = wm8978_set_dai_clkdiv, 872 .set_sysclk = wm8978_set_dai_sysclk, 873 }; 874 875 /* Also supports 12kHz */ 876 static struct snd_soc_dai_driver wm8978_dai = { 877 .name = "wm8978-hifi", 878 .playback = { 879 .stream_name = "Playback", 880 .channels_min = 1, 881 .channels_max = 2, 882 .rates = SNDRV_PCM_RATE_8000_48000, 883 .formats = WM8978_FORMATS, 884 }, 885 .capture = { 886 .stream_name = "Capture", 887 .channels_min = 1, 888 .channels_max = 2, 889 .rates = SNDRV_PCM_RATE_8000_48000, 890 .formats = WM8978_FORMATS, 891 }, 892 .ops = &wm8978_dai_ops, 893 }; 894 895 static int wm8978_suspend(struct snd_soc_codec *codec, pm_message_t state) 896 { 897 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); 898 /* Also switch PLL off */ 899 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0); 900 901 return 0; 902 } 903 904 static int wm8978_resume(struct snd_soc_codec *codec) 905 { 906 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 907 int i; 908 u16 *cache = codec->reg_cache; 909 910 /* Sync reg_cache with the hardware */ 911 for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) { 912 if (i == WM8978_RESET) 913 continue; 914 if (cache[i] != wm8978_reg[i]) 915 snd_soc_write(codec, i, cache[i]); 916 } 917 918 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 919 920 if (wm8978->f_pllout) 921 /* Switch PLL on */ 922 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20); 923 924 return 0; 925 } 926 927 /* 928 * These registers contain an "update" bit - bit 8. This means, for example, 929 * that one can write new DAC digital volume for both channels, but only when 930 * the update bit is set, will also the volume be updated - simultaneously for 931 * both channels. 932 */ 933 static const int update_reg[] = { 934 WM8978_LEFT_DAC_DIGITAL_VOLUME, 935 WM8978_RIGHT_DAC_DIGITAL_VOLUME, 936 WM8978_LEFT_ADC_DIGITAL_VOLUME, 937 WM8978_RIGHT_ADC_DIGITAL_VOLUME, 938 WM8978_LEFT_INP_PGA_CONTROL, 939 WM8978_RIGHT_INP_PGA_CONTROL, 940 WM8978_LOUT1_HP_CONTROL, 941 WM8978_ROUT1_HP_CONTROL, 942 WM8978_LOUT2_SPK_CONTROL, 943 WM8978_ROUT2_SPK_CONTROL, 944 }; 945 946 static int wm8978_probe(struct snd_soc_codec *codec) 947 { 948 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 949 int ret = 0, i; 950 951 /* 952 * Set default system clock to PLL, it is more precise, this is also the 953 * default hardware setting 954 */ 955 wm8978->sysclk = WM8978_PLL; 956 codec->control_data = wm8978->control_data; 957 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C); 958 if (ret < 0) { 959 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 960 return ret; 961 } 962 963 /* 964 * Set the update bit in all registers, that have one. This way all 965 * writes to those registers will also cause the update bit to be 966 * written. 967 */ 968 for (i = 0; i < ARRAY_SIZE(update_reg); i++) 969 ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100; 970 971 /* Reset the codec */ 972 ret = snd_soc_write(codec, WM8978_RESET, 0); 973 if (ret < 0) { 974 dev_err(codec->dev, "Failed to issue reset\n"); 975 return ret; 976 } 977 978 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 979 980 snd_soc_add_controls(codec, wm8978_snd_controls, 981 ARRAY_SIZE(wm8978_snd_controls)); 982 wm8978_add_widgets(codec); 983 984 return 0; 985 } 986 987 /* power down chip */ 988 static int wm8978_remove(struct snd_soc_codec *codec) 989 { 990 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); 991 return 0; 992 } 993 994 static struct snd_soc_codec_driver soc_codec_dev_wm8978 = { 995 .probe = wm8978_probe, 996 .remove = wm8978_remove, 997 .suspend = wm8978_suspend, 998 .resume = wm8978_resume, 999 .set_bias_level = wm8978_set_bias_level, 1000 .reg_cache_size = ARRAY_SIZE(wm8978_reg), 1001 .reg_word_size = sizeof(u16), 1002 .reg_cache_default = wm8978_reg, 1003 }; 1004 1005 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1006 static __devinit int wm8978_i2c_probe(struct i2c_client *i2c, 1007 const struct i2c_device_id *id) 1008 { 1009 struct wm8978_priv *wm8978; 1010 int ret; 1011 1012 wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL); 1013 if (wm8978 == NULL) 1014 return -ENOMEM; 1015 1016 i2c_set_clientdata(i2c, wm8978); 1017 wm8978->control_data = i2c; 1018 1019 ret = snd_soc_register_codec(&i2c->dev, 1020 &soc_codec_dev_wm8978, &wm8978_dai, 1); 1021 if (ret < 0) 1022 kfree(wm8978); 1023 return ret; 1024 } 1025 1026 static __devexit int wm8978_i2c_remove(struct i2c_client *client) 1027 { 1028 snd_soc_unregister_codec(&client->dev); 1029 kfree(i2c_get_clientdata(client)); 1030 return 0; 1031 } 1032 1033 static const struct i2c_device_id wm8978_i2c_id[] = { 1034 { "wm8978", 0 }, 1035 { } 1036 }; 1037 MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); 1038 1039 static struct i2c_driver wm8978_i2c_driver = { 1040 .driver = { 1041 .name = "wm8978", 1042 .owner = THIS_MODULE, 1043 }, 1044 .probe = wm8978_i2c_probe, 1045 .remove = __devexit_p(wm8978_i2c_remove), 1046 .id_table = wm8978_i2c_id, 1047 }; 1048 #endif 1049 1050 static int __init wm8978_modinit(void) 1051 { 1052 int ret = 0; 1053 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1054 ret = i2c_add_driver(&wm8978_i2c_driver); 1055 if (ret != 0) { 1056 printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n", 1057 ret); 1058 } 1059 #endif 1060 return ret; 1061 } 1062 module_init(wm8978_modinit); 1063 1064 static void __exit wm8978_exit(void) 1065 { 1066 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1067 i2c_del_driver(&wm8978_i2c_driver); 1068 #endif 1069 } 1070 module_exit(wm8978_exit); 1071 1072 MODULE_DESCRIPTION("ASoC WM8978 codec driver"); 1073 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); 1074 MODULE_LICENSE("GPL"); 1075