xref: /openbmc/linux/sound/soc/codecs/wm8974.h (revision 0a1bf553)
10a1bf553SMark Brown /*
20a1bf553SMark Brown  * wm8974.h  --  WM8974 Soc Audio driver
30a1bf553SMark Brown  *
40a1bf553SMark Brown  * This program is free software; you can redistribute it and/or modify
50a1bf553SMark Brown  * it under the terms of the GNU General Public License version 2 as
60a1bf553SMark Brown  * published by the Free Software Foundation.
70a1bf553SMark Brown  */
80a1bf553SMark Brown 
90a1bf553SMark Brown #ifndef _WM8974_H
100a1bf553SMark Brown #define _WM8974_H
110a1bf553SMark Brown 
120a1bf553SMark Brown /* WM8974 register space */
130a1bf553SMark Brown 
140a1bf553SMark Brown #define WM8974_RESET		0x0
150a1bf553SMark Brown #define WM8974_POWER1		0x1
160a1bf553SMark Brown #define WM8974_POWER2		0x2
170a1bf553SMark Brown #define WM8974_POWER3		0x3
180a1bf553SMark Brown #define WM8974_IFACE		0x4
190a1bf553SMark Brown #define WM8974_COMP			0x5
200a1bf553SMark Brown #define WM8974_CLOCK		0x6
210a1bf553SMark Brown #define WM8974_ADD			0x7
220a1bf553SMark Brown #define WM8974_GPIO			0x8
230a1bf553SMark Brown #define WM8974_DAC			0xa
240a1bf553SMark Brown #define WM8974_DACVOL		0xb
250a1bf553SMark Brown #define WM8974_ADC			0xe
260a1bf553SMark Brown #define WM8974_ADCVOL		0xf
270a1bf553SMark Brown #define WM8974_EQ1			0x12
280a1bf553SMark Brown #define WM8974_EQ2			0x13
290a1bf553SMark Brown #define WM8974_EQ3			0x14
300a1bf553SMark Brown #define WM8974_EQ4			0x15
310a1bf553SMark Brown #define WM8974_EQ5			0x16
320a1bf553SMark Brown #define WM8974_DACLIM1		0x18
330a1bf553SMark Brown #define WM8974_DACLIM2		0x19
340a1bf553SMark Brown #define WM8974_NOTCH1		0x1b
350a1bf553SMark Brown #define WM8974_NOTCH2		0x1c
360a1bf553SMark Brown #define WM8974_NOTCH3		0x1d
370a1bf553SMark Brown #define WM8974_NOTCH4		0x1e
380a1bf553SMark Brown #define WM8974_ALC1			0x20
390a1bf553SMark Brown #define WM8974_ALC2			0x21
400a1bf553SMark Brown #define WM8974_ALC3			0x22
410a1bf553SMark Brown #define WM8974_NGATE		0x23
420a1bf553SMark Brown #define WM8974_PLLN			0x24
430a1bf553SMark Brown #define WM8974_PLLK1		0x25
440a1bf553SMark Brown #define WM8974_PLLK2		0x26
450a1bf553SMark Brown #define WM8974_PLLK3		0x27
460a1bf553SMark Brown #define WM8974_ATTEN		0x28
470a1bf553SMark Brown #define WM8974_INPUT		0x2c
480a1bf553SMark Brown #define WM8974_INPPGA		0x2d
490a1bf553SMark Brown #define WM8974_ADCBOOST		0x2f
500a1bf553SMark Brown #define WM8974_OUTPUT		0x31
510a1bf553SMark Brown #define WM8974_SPKMIX		0x32
520a1bf553SMark Brown #define WM8974_SPKVOL		0x36
530a1bf553SMark Brown #define WM8974_MONOMIX		0x38
540a1bf553SMark Brown 
550a1bf553SMark Brown #define WM8974_CACHEREGNUM 	57
560a1bf553SMark Brown 
570a1bf553SMark Brown /* Clock divider Id's */
580a1bf553SMark Brown #define WM8974_OPCLKDIV		0
590a1bf553SMark Brown #define WM8974_MCLKDIV		1
600a1bf553SMark Brown #define WM8974_ADCCLK		2
610a1bf553SMark Brown #define WM8974_DACCLK		3
620a1bf553SMark Brown #define WM8974_BCLKDIV		4
630a1bf553SMark Brown 
640a1bf553SMark Brown /* DAC clock dividers */
650a1bf553SMark Brown #define WM8974_DACCLK_F2	(1 << 3)
660a1bf553SMark Brown #define WM8974_DACCLK_F4	(0 << 3)
670a1bf553SMark Brown 
680a1bf553SMark Brown /* ADC clock dividers */
690a1bf553SMark Brown #define WM8974_ADCCLK_F2	(1 << 3)
700a1bf553SMark Brown #define WM8974_ADCCLK_F4	(0 << 3)
710a1bf553SMark Brown 
720a1bf553SMark Brown /* PLL Out dividers */
730a1bf553SMark Brown #define WM8974_OPCLKDIV_1	(0 << 4)
740a1bf553SMark Brown #define WM8974_OPCLKDIV_2	(1 << 4)
750a1bf553SMark Brown #define WM8974_OPCLKDIV_3	(2 << 4)
760a1bf553SMark Brown #define WM8974_OPCLKDIV_4	(3 << 4)
770a1bf553SMark Brown 
780a1bf553SMark Brown /* BCLK clock dividers */
790a1bf553SMark Brown #define WM8974_BCLKDIV_1	(0 << 2)
800a1bf553SMark Brown #define WM8974_BCLKDIV_2	(1 << 2)
810a1bf553SMark Brown #define WM8974_BCLKDIV_4	(2 << 2)
820a1bf553SMark Brown #define WM8974_BCLKDIV_8	(3 << 2)
830a1bf553SMark Brown #define WM8974_BCLKDIV_16	(4 << 2)
840a1bf553SMark Brown #define WM8974_BCLKDIV_32	(5 << 2)
850a1bf553SMark Brown 
860a1bf553SMark Brown /* MCLK clock dividers */
870a1bf553SMark Brown #define WM8974_MCLKDIV_1	(0 << 5)
880a1bf553SMark Brown #define WM8974_MCLKDIV_1_5	(1 << 5)
890a1bf553SMark Brown #define WM8974_MCLKDIV_2	(2 << 5)
900a1bf553SMark Brown #define WM8974_MCLKDIV_3	(3 << 5)
910a1bf553SMark Brown #define WM8974_MCLKDIV_4	(4 << 5)
920a1bf553SMark Brown #define WM8974_MCLKDIV_6	(5 << 5)
930a1bf553SMark Brown #define WM8974_MCLKDIV_8	(6 << 5)
940a1bf553SMark Brown #define WM8974_MCLKDIV_12	(7 << 5)
950a1bf553SMark Brown 
960a1bf553SMark Brown 
970a1bf553SMark Brown struct wm8974_setup_data {
980a1bf553SMark Brown 	unsigned short i2c_address;
990a1bf553SMark Brown };
1000a1bf553SMark Brown 
1010a1bf553SMark Brown extern struct snd_soc_dai wm8974_dai;
1020a1bf553SMark Brown extern struct snd_soc_codec_device soc_codec_dev_wm8974;
1030a1bf553SMark Brown 
1040a1bf553SMark Brown #endif
105