xref: /openbmc/linux/sound/soc/codecs/wm8962.c (revision 6774def6)
1 /*
2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
3  *
4  * Copyright 2010-2 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/gcd.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28 #include <linux/workqueue.h>
29 #include <sound/core.h>
30 #include <sound/jack.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
36 #include <sound/wm8962.h>
37 #include <trace/events/asoc.h>
38 
39 #include "wm8962.h"
40 
41 #define WM8962_NUM_SUPPLIES 8
42 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
43 	"DCVDD",
44 	"DBVDD",
45 	"AVDD",
46 	"CPVDD",
47 	"MICVDD",
48 	"PLLVDD",
49 	"SPKVDD1",
50 	"SPKVDD2",
51 };
52 
53 /* codec private data */
54 struct wm8962_priv {
55 	struct wm8962_pdata pdata;
56 	struct regmap *regmap;
57 	struct snd_soc_codec *codec;
58 
59 	int sysclk;
60 	int sysclk_rate;
61 
62 	int bclk;  /* Desired BCLK */
63 	int lrclk;
64 
65 	struct completion fll_lock;
66 	int fll_src;
67 	int fll_fref;
68 	int fll_fout;
69 
70 	u16 dsp2_ena;
71 
72 	struct delayed_work mic_work;
73 	struct snd_soc_jack *jack;
74 
75 	struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
76 	struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
77 
78 	struct input_dev *beep;
79 	struct work_struct beep_work;
80 	int beep_rate;
81 
82 #ifdef CONFIG_GPIOLIB
83 	struct gpio_chip gpio_chip;
84 #endif
85 
86 	int irq;
87 };
88 
89 /* We can't use the same notifier block for more than one supply and
90  * there's no way I can see to get from a callback to the caller
91  * except container_of().
92  */
93 #define WM8962_REGULATOR_EVENT(n) \
94 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 				    unsigned long event, void *data)	\
96 { \
97 	struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 						  disable_nb[n]); \
99 	if (event & REGULATOR_EVENT_DISABLE) { \
100 		regcache_mark_dirty(wm8962->regmap);	\
101 	} \
102 	return 0; \
103 }
104 
105 WM8962_REGULATOR_EVENT(0)
106 WM8962_REGULATOR_EVENT(1)
107 WM8962_REGULATOR_EVENT(2)
108 WM8962_REGULATOR_EVENT(3)
109 WM8962_REGULATOR_EVENT(4)
110 WM8962_REGULATOR_EVENT(5)
111 WM8962_REGULATOR_EVENT(6)
112 WM8962_REGULATOR_EVENT(7)
113 
114 static struct reg_default wm8962_reg[] = {
115 	{ 0, 0x009F },   /* R0     - Left Input volume */
116 	{ 1, 0x049F },   /* R1     - Right Input volume */
117 	{ 2, 0x0000 },   /* R2     - HPOUTL volume */
118 	{ 3, 0x0000 },   /* R3     - HPOUTR volume */
119 
120 	{ 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
121 	{ 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
122 	{ 7, 0x000A },   /* R7     - Audio Interface 0 */
123 
124 	{ 9, 0x0300 },   /* R9     - Audio Interface 1 */
125 	{ 10, 0x00C0 },  /* R10    - Left DAC volume */
126 	{ 11, 0x00C0 },  /* R11    - Right DAC volume */
127 
128 	{ 14, 0x0040 },   /* R14    - Audio Interface 2 */
129 	{ 15, 0x6243 },   /* R15    - Software Reset */
130 
131 	{ 17, 0x007B },   /* R17    - ALC1 */
132 
133 	{ 19, 0x1C32 },   /* R19    - ALC3 */
134 	{ 20, 0x3200 },   /* R20    - Noise Gate */
135 	{ 21, 0x00C0 },   /* R21    - Left ADC volume */
136 	{ 22, 0x00C0 },   /* R22    - Right ADC volume */
137 	{ 23, 0x0160 },   /* R23    - Additional control(1) */
138 	{ 24, 0x0000 },   /* R24    - Additional control(2) */
139 	{ 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
140 	{ 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
141 	{ 27, 0x0010 },   /* R27    - Additional Control (3) */
142 	{ 28, 0x0000 },   /* R28    - Anti-pop */
143 
144 	{ 30, 0x005E },   /* R30    - Clocking 3 */
145 	{ 31, 0x0000 },   /* R31    - Input mixer control (1) */
146 	{ 32, 0x0145 },   /* R32    - Left input mixer volume */
147 	{ 33, 0x0145 },   /* R33    - Right input mixer volume */
148 	{ 34, 0x0009 },   /* R34    - Input mixer control (2) */
149 	{ 35, 0x0003 },   /* R35    - Input bias control */
150 	{ 37, 0x0008 },   /* R37    - Left input PGA control */
151 	{ 38, 0x0008 },   /* R38    - Right input PGA control */
152 
153 	{ 40, 0x0000 },   /* R40    - SPKOUTL volume */
154 	{ 41, 0x0000 },   /* R41    - SPKOUTR volume */
155 
156 	{ 49, 0x0010 },   /* R49    - Class D Control 1 */
157 	{ 51, 0x0003 },   /* R51    - Class D Control 2 */
158 
159 	{ 56, 0x0506 },   /* R56    - Clocking 4 */
160 	{ 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
161 	{ 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
162 
163 	{ 60, 0x0300 },   /* R60    - DC Servo 0 */
164 	{ 61, 0x0300 },   /* R61    - DC Servo 1 */
165 
166 	{ 64, 0x0810 },   /* R64    - DC Servo 4 */
167 
168 	{ 68, 0x001B },   /* R68    - Analogue PGA Bias */
169 	{ 69, 0x0000 },   /* R69    - Analogue HP 0 */
170 
171 	{ 71, 0x01FB },   /* R71    - Analogue HP 2 */
172 	{ 72, 0x0000 },   /* R72    - Charge Pump 1 */
173 
174 	{ 82, 0x0004 },   /* R82    - Charge Pump B */
175 
176 	{ 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
177 
178 	{ 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
179 
180 	{ 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
181 	{ 94, 0x0000 },   /* R94    - Control Interface */
182 
183 	{ 99, 0x0000 },   /* R99    - Mixer Enables */
184 	{ 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
185 	{ 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
186 	{ 102, 0x013F },   /* R102   - Headphone Mixer (3) */
187 	{ 103, 0x013F },   /* R103   - Headphone Mixer (4) */
188 
189 	{ 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
190 	{ 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
191 	{ 107, 0x013F },   /* R107   - Speaker Mixer (3) */
192 	{ 108, 0x013F },   /* R108   - Speaker Mixer (4) */
193 	{ 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
194 	{ 110, 0x0002 },   /* R110   - Beep Generator (1) */
195 
196 	{ 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
197 	{ 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
198 
199 	{ 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
200 
201 	{ 124, 0x0011 },   /* R124   - Analogue Clocking1 */
202 	{ 125, 0x004B },   /* R125   - Analogue Clocking2 */
203 	{ 126, 0x000D },   /* R126   - Analogue Clocking3 */
204 	{ 127, 0x0000 },   /* R127   - PLL Software Reset */
205 
206 	{ 131, 0x0000 },   /* R131   - PLL 4 */
207 
208 	{ 136, 0x0067 },   /* R136   - PLL 9 */
209 	{ 137, 0x001C },   /* R137   - PLL 10 */
210 	{ 138, 0x0071 },   /* R138   - PLL 11 */
211 	{ 139, 0x00C7 },   /* R139   - PLL 12 */
212 	{ 140, 0x0067 },   /* R140   - PLL 13 */
213 	{ 141, 0x0048 },   /* R141   - PLL 14 */
214 	{ 142, 0x0022 },   /* R142   - PLL 15 */
215 	{ 143, 0x0097 },   /* R143   - PLL 16 */
216 
217 	{ 155, 0x000C },   /* R155   - FLL Control (1) */
218 	{ 156, 0x0039 },   /* R156   - FLL Control (2) */
219 	{ 157, 0x0180 },   /* R157   - FLL Control (3) */
220 
221 	{ 159, 0x0032 },   /* R159   - FLL Control (5) */
222 	{ 160, 0x0018 },   /* R160   - FLL Control (6) */
223 	{ 161, 0x007D },   /* R161   - FLL Control (7) */
224 	{ 162, 0x0008 },   /* R162   - FLL Control (8) */
225 
226 	{ 252, 0x0005 },   /* R252   - General test 1 */
227 
228 	{ 256, 0x0000 },   /* R256   - DF1 */
229 	{ 257, 0x0000 },   /* R257   - DF2 */
230 	{ 258, 0x0000 },   /* R258   - DF3 */
231 	{ 259, 0x0000 },   /* R259   - DF4 */
232 	{ 260, 0x0000 },   /* R260   - DF5 */
233 	{ 261, 0x0000 },   /* R261   - DF6 */
234 	{ 262, 0x0000 },   /* R262   - DF7 */
235 
236 	{ 264, 0x0000 },   /* R264   - LHPF1 */
237 	{ 265, 0x0000 },   /* R265   - LHPF2 */
238 
239 	{ 268, 0x0000 },   /* R268   - THREED1 */
240 	{ 269, 0x0000 },   /* R269   - THREED2 */
241 	{ 270, 0x0000 },   /* R270   - THREED3 */
242 	{ 271, 0x0000 },   /* R271   - THREED4 */
243 
244 	{ 276, 0x000C },   /* R276   - DRC 1 */
245 	{ 277, 0x0925 },   /* R277   - DRC 2 */
246 	{ 278, 0x0000 },   /* R278   - DRC 3 */
247 	{ 279, 0x0000 },   /* R279   - DRC 4 */
248 	{ 280, 0x0000 },   /* R280   - DRC 5 */
249 
250 	{ 285, 0x0000 },   /* R285   - Tloopback */
251 
252 	{ 335, 0x0004 },   /* R335   - EQ1 */
253 	{ 336, 0x6318 },   /* R336   - EQ2 */
254 	{ 337, 0x6300 },   /* R337   - EQ3 */
255 	{ 338, 0x0FCA },   /* R338   - EQ4 */
256 	{ 339, 0x0400 },   /* R339   - EQ5 */
257 	{ 340, 0x00D8 },   /* R340   - EQ6 */
258 	{ 341, 0x1EB5 },   /* R341   - EQ7 */
259 	{ 342, 0xF145 },   /* R342   - EQ8 */
260 	{ 343, 0x0B75 },   /* R343   - EQ9 */
261 	{ 344, 0x01C5 },   /* R344   - EQ10 */
262 	{ 345, 0x1C58 },   /* R345   - EQ11 */
263 	{ 346, 0xF373 },   /* R346   - EQ12 */
264 	{ 347, 0x0A54 },   /* R347   - EQ13 */
265 	{ 348, 0x0558 },   /* R348   - EQ14 */
266 	{ 349, 0x168E },   /* R349   - EQ15 */
267 	{ 350, 0xF829 },   /* R350   - EQ16 */
268 	{ 351, 0x07AD },   /* R351   - EQ17 */
269 	{ 352, 0x1103 },   /* R352   - EQ18 */
270 	{ 353, 0x0564 },   /* R353   - EQ19 */
271 	{ 354, 0x0559 },   /* R354   - EQ20 */
272 	{ 355, 0x4000 },   /* R355   - EQ21 */
273 	{ 356, 0x6318 },   /* R356   - EQ22 */
274 	{ 357, 0x6300 },   /* R357   - EQ23 */
275 	{ 358, 0x0FCA },   /* R358   - EQ24 */
276 	{ 359, 0x0400 },   /* R359   - EQ25 */
277 	{ 360, 0x00D8 },   /* R360   - EQ26 */
278 	{ 361, 0x1EB5 },   /* R361   - EQ27 */
279 	{ 362, 0xF145 },   /* R362   - EQ28 */
280 	{ 363, 0x0B75 },   /* R363   - EQ29 */
281 	{ 364, 0x01C5 },   /* R364   - EQ30 */
282 	{ 365, 0x1C58 },   /* R365   - EQ31 */
283 	{ 366, 0xF373 },   /* R366   - EQ32 */
284 	{ 367, 0x0A54 },   /* R367   - EQ33 */
285 	{ 368, 0x0558 },   /* R368   - EQ34 */
286 	{ 369, 0x168E },   /* R369   - EQ35 */
287 	{ 370, 0xF829 },   /* R370   - EQ36 */
288 	{ 371, 0x07AD },   /* R371   - EQ37 */
289 	{ 372, 0x1103 },   /* R372   - EQ38 */
290 	{ 373, 0x0564 },   /* R373   - EQ39 */
291 	{ 374, 0x0559 },   /* R374   - EQ40 */
292 	{ 375, 0x4000 },   /* R375   - EQ41 */
293 
294 	{ 513, 0x0000 },   /* R513   - GPIO 2 */
295 	{ 514, 0x0000 },   /* R514   - GPIO 3 */
296 
297 	{ 516, 0x8100 },   /* R516   - GPIO 5 */
298 	{ 517, 0x8100 },   /* R517   - GPIO 6 */
299 
300 	{ 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
301 	{ 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
302 
303 	{ 576, 0x0000 },   /* R576   - Interrupt Control */
304 
305 	{ 584, 0x002D },   /* R584   - IRQ Debounce */
306 
307 	{ 586, 0x0000 },   /* R586   -  MICINT Source Pol */
308 
309 	{ 768, 0x1C00 },   /* R768   - DSP2 Power Management */
310 
311 	{ 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
312 
313 	{ 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
314 	{ 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
315 	{ 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
316 
317 	{ 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
318 	{ 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
319 
320 	{ 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
321 	{ 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
322 
323 	{ 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
324 	{ 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
325 
326 	{ 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
327 
328 	{ 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
329 	{ 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
330 	{ 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
331 	{ 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
332 	{ 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
333 	{ 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
334 
335 	{ 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
336 	{ 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
337 	{ 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
338 	{ 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
339 	{ 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
340 	{ 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
341 	{ 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
342 	{ 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
343 	{ 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
344 	{ 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
345 	{ 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
346 	{ 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
347 	{ 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
348 	{ 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
349 	{ 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
350 	{ 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
351 	{ 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
352 	{ 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
353 	{ 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
354 	{ 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
355 	{ 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
356 	{ 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
357 	{ 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
358 	{ 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
359 	{ 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
360 	{ 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
361 	{ 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
362 	{ 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
363 	{ 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
364 	{ 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
365 
366 	{ 17048, 0x0083 },   /* R17408 - HPF_C_1 */
367 	{ 17049, 0x98AD },   /* R17409 - HPF_C_0 */
368 
369 	{ 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
370 	{ 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
371 	{ 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
372 	{ 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
373 	{ 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
374 	{ 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
375 	{ 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
376 	{ 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
377 	{ 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
378 	{ 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
379 	{ 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
380 	{ 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
381 	{ 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
382 	{ 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
383 	{ 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
384 	{ 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
385 	{ 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
386 	{ 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
387 	{ 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
388 	{ 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
389 	{ 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
390 	{ 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
391 	{ 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
392 	{ 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
393 	{ 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
394 	{ 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
395 	{ 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
396 	{ 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
397 	{ 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
398 	{ 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
399 	{ 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
400 	{ 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
401 	{ 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
402 	{ 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
403 	{ 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
404 	{ 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
405 	{ 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
406 	{ 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
407 	{ 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
408 	{ 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
409 	{ 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
410 	{ 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
411 	{ 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
412 	{ 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
413 	{ 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
414 	{ 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
415 	{ 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
416 	{ 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
417 	{ 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
418 	{ 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
419 	{ 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
420 	{ 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
421 	{ 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
422 	{ 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
423 	{ 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
424 	{ 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
425 	{ 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
426 	{ 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
427 	{ 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
428 	{ 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
429 	{ 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
430 	{ 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
431 	{ 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
432 	{ 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
433 
434 	{ 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
435 	{ 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
436 	{ 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
437 	{ 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
438 
439 	{ 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
440 	{ 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
441 	{ 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
442 	{ 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
443 	{ 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
444 	{ 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
445 	{ 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
446 	{ 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
447 	{ 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
448 	{ 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
449 	{ 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
450 	{ 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
451 	{ 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
452 	{ 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
453 	{ 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
454 	{ 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
455 	{ 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
456 	{ 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
457 	{ 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
458 	{ 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
459 	{ 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
460 	{ 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
461 	{ 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
462 	{ 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
463 	{ 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
464 	{ 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
465 	{ 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
466 	{ 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
467 	{ 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
468 	{ 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
469 	{ 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
470 	{ 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
471 	{ 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
472 	{ 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
473 	{ 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
474 	{ 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
475 	{ 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
476 	{ 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
477 	{ 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
478 	{ 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
479 	{ 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
480 	{ 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
481 	{ 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
482 	{ 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
483 	{ 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
484 	{ 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
485 	{ 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
486 	{ 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
487 	{ 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
488 	{ 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
489 	{ 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
490 	{ 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
491 	{ 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
492 	{ 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
493 	{ 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
494 	{ 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
495 	{ 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
496 	{ 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
497 	{ 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
498 	{ 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
499 	{ 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
500 	{ 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
501 	{ 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
502 	{ 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
503 
504 	{ 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
505 	{ 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
506 	{ 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
507 	{ 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
508 	{ 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
509 	{ 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
510 	{ 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
511 	{ 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
512 	{ 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
513 	{ 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
514 	{ 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
515 	{ 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
516 	{ 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
517 	{ 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
518 	{ 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
519 	{ 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
520 	{ 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
521 	{ 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
522 	{ 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
523 	{ 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
524 	{ 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
525 	{ 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
526 	{ 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
527 	{ 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
528 	{ 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
529 	{ 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
530 	{ 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
531 	{ 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
532 	{ 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
533 	{ 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
534 	{ 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
535 	{ 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
536 	{ 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
537 	{ 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
538 	{ 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
539 	{ 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
540 	{ 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
541 	{ 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
542 	{ 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
543 	{ 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
544 	{ 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
545 	{ 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
546 	{ 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
547 	{ 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
548 	{ 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
549 	{ 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
550 	{ 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
551 	{ 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
552 	{ 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
553 	{ 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
554 	{ 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
555 	{ 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
556 	{ 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
557 	{ 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
558 	{ 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
559 	{ 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
560 	{ 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
561 	{ 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
562 	{ 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
563 	{ 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
564 	{ 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
565 	{ 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
566 	{ 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
567 	{ 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
568 
569 	{ 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
570 	{ 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
571 	{ 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
572 	{ 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
573 
574 	{ 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
575 	{ 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
576 	{ 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
577 	{ 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
578 	{ 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
579 	{ 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
580 	{ 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
581 	{ 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
582 	{ 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
583 	{ 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
584 	{ 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
585 	{ 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
586 	{ 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
587 	{ 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
588 	{ 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
589 	{ 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
590 	{ 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
591 	{ 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
592 	{ 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
593 	{ 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
594 	{ 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
595 	{ 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
596 	{ 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
597 	{ 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
598 	{ 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
599 	{ 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
600 	{ 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
601 	{ 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
602 	{ 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
603 	{ 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
604 	{ 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
605 	{ 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
606 	{ 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
607 	{ 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
608 	{ 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
609 	{ 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
610 	{ 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
611 	{ 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
612 	{ 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
613 	{ 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
614 	{ 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
615 	{ 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
616 	{ 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
617 	{ 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
618 	{ 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
619 	{ 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
620 	{ 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
621 	{ 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
622 	{ 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
623 	{ 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
624 	{ 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
625 	{ 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
626 	{ 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
627 	{ 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
628 	{ 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
629 	{ 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
630 	{ 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
631 	{ 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
632 	{ 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
633 	{ 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
634 	{ 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
635 	{ 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
636 	{ 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
637 	{ 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
638 
639 	{ 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
640 	{ 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
641 	{ 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
642 	{ 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
643 	{ 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
644 	{ 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
645 	{ 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
646 	{ 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
647 	{ 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
648 	{ 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
649 	{ 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
650 	{ 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
651 	{ 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
652 	{ 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
653 	{ 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
654 	{ 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
655 	{ 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
656 	{ 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
657 	{ 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
658 	{ 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
659 	{ 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
660 	{ 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
661 	{ 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
662 	{ 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
663 	{ 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
664 	{ 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
665 	{ 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
666 	{ 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
667 	{ 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
668 	{ 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
669 	{ 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
670 	{ 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
671 	{ 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
672 	{ 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
673 	{ 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
674 	{ 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
675 	{ 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
676 	{ 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
677 	{ 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
678 	{ 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
679 	{ 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
680 	{ 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
681 	{ 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
682 	{ 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
683 	{ 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
684 	{ 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
685 	{ 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
686 	{ 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
687 	{ 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
688 	{ 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
689 	{ 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
690 	{ 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
691 	{ 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
692 	{ 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
693 	{ 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
694 	{ 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
695 	{ 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
696 	{ 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
697 	{ 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
698 	{ 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
699 	{ 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
700 	{ 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
701 	{ 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
702 	{ 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
703 	{ 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
704 	{ 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
705 	{ 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
706 	{ 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
707 	{ 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
708 	{ 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
709 	{ 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
710 	{ 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
711 	{ 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
712 	{ 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
713 	{ 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
714 	{ 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
715 	{ 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
716 	{ 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
717 	{ 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
718 	{ 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
719 	{ 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
720 	{ 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
721 	{ 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
722 	{ 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
723 	{ 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
724 	{ 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
725 	{ 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
726 	{ 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
727 	{ 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
728 	{ 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
729 	{ 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
730 	{ 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
731 	{ 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
732 	{ 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
733 	{ 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
734 	{ 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
735 	{ 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
736 	{ 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
737 	{ 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
738 	{ 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
739 	{ 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
740 	{ 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
741 	{ 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
742 	{ 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
743 	{ 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
744 	{ 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
745 	{ 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
746 	{ 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
747 	{ 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
748 	{ 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
749 	{ 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
750 	{ 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
751 	{ 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
752 	{ 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
753 	{ 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
754 	{ 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
755 	{ 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
756 	{ 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
757 	{ 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
758 	{ 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
759 	{ 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
760 	{ 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
761 	{ 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
762 	{ 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
763 	{ 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
764 	{ 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
765 	{ 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
766 	{ 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
767 	{ 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
768 	{ 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
769 	{ 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
770 	{ 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
771 	{ 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
772 	{ 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
773 	{ 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
774 	{ 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
775 	{ 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
776 	{ 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
777 	{ 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
778 	{ 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
779 	{ 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
780 	{ 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
781 	{ 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
782 	{ 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
783 	{ 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
784 	{ 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
785 	{ 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
786 	{ 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
787 };
788 
789 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
790 {
791 	switch (reg) {
792 	case WM8962_CLOCKING1:
793 	case WM8962_CLOCKING2:
794 	case WM8962_SOFTWARE_RESET:
795 	case WM8962_ALC2:
796 	case WM8962_THERMAL_SHUTDOWN_STATUS:
797 	case WM8962_ADDITIONAL_CONTROL_4:
798 	case WM8962_DC_SERVO_6:
799 	case WM8962_INTERRUPT_STATUS_1:
800 	case WM8962_INTERRUPT_STATUS_2:
801 	case WM8962_DSP2_EXECCONTROL:
802 		return true;
803 	default:
804 		return false;
805 	}
806 }
807 
808 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
809 {
810 	switch (reg) {
811 	case WM8962_LEFT_INPUT_VOLUME:
812 	case WM8962_RIGHT_INPUT_VOLUME:
813 	case WM8962_HPOUTL_VOLUME:
814 	case WM8962_HPOUTR_VOLUME:
815 	case WM8962_CLOCKING1:
816 	case WM8962_ADC_DAC_CONTROL_1:
817 	case WM8962_ADC_DAC_CONTROL_2:
818 	case WM8962_AUDIO_INTERFACE_0:
819 	case WM8962_CLOCKING2:
820 	case WM8962_AUDIO_INTERFACE_1:
821 	case WM8962_LEFT_DAC_VOLUME:
822 	case WM8962_RIGHT_DAC_VOLUME:
823 	case WM8962_AUDIO_INTERFACE_2:
824 	case WM8962_SOFTWARE_RESET:
825 	case WM8962_ALC1:
826 	case WM8962_ALC2:
827 	case WM8962_ALC3:
828 	case WM8962_NOISE_GATE:
829 	case WM8962_LEFT_ADC_VOLUME:
830 	case WM8962_RIGHT_ADC_VOLUME:
831 	case WM8962_ADDITIONAL_CONTROL_1:
832 	case WM8962_ADDITIONAL_CONTROL_2:
833 	case WM8962_PWR_MGMT_1:
834 	case WM8962_PWR_MGMT_2:
835 	case WM8962_ADDITIONAL_CONTROL_3:
836 	case WM8962_ANTI_POP:
837 	case WM8962_CLOCKING_3:
838 	case WM8962_INPUT_MIXER_CONTROL_1:
839 	case WM8962_LEFT_INPUT_MIXER_VOLUME:
840 	case WM8962_RIGHT_INPUT_MIXER_VOLUME:
841 	case WM8962_INPUT_MIXER_CONTROL_2:
842 	case WM8962_INPUT_BIAS_CONTROL:
843 	case WM8962_LEFT_INPUT_PGA_CONTROL:
844 	case WM8962_RIGHT_INPUT_PGA_CONTROL:
845 	case WM8962_SPKOUTL_VOLUME:
846 	case WM8962_SPKOUTR_VOLUME:
847 	case WM8962_THERMAL_SHUTDOWN_STATUS:
848 	case WM8962_ADDITIONAL_CONTROL_4:
849 	case WM8962_CLASS_D_CONTROL_1:
850 	case WM8962_CLASS_D_CONTROL_2:
851 	case WM8962_CLOCKING_4:
852 	case WM8962_DAC_DSP_MIXING_1:
853 	case WM8962_DAC_DSP_MIXING_2:
854 	case WM8962_DC_SERVO_0:
855 	case WM8962_DC_SERVO_1:
856 	case WM8962_DC_SERVO_4:
857 	case WM8962_DC_SERVO_6:
858 	case WM8962_ANALOGUE_PGA_BIAS:
859 	case WM8962_ANALOGUE_HP_0:
860 	case WM8962_ANALOGUE_HP_2:
861 	case WM8962_CHARGE_PUMP_1:
862 	case WM8962_CHARGE_PUMP_B:
863 	case WM8962_WRITE_SEQUENCER_CONTROL_1:
864 	case WM8962_WRITE_SEQUENCER_CONTROL_2:
865 	case WM8962_WRITE_SEQUENCER_CONTROL_3:
866 	case WM8962_CONTROL_INTERFACE:
867 	case WM8962_MIXER_ENABLES:
868 	case WM8962_HEADPHONE_MIXER_1:
869 	case WM8962_HEADPHONE_MIXER_2:
870 	case WM8962_HEADPHONE_MIXER_3:
871 	case WM8962_HEADPHONE_MIXER_4:
872 	case WM8962_SPEAKER_MIXER_1:
873 	case WM8962_SPEAKER_MIXER_2:
874 	case WM8962_SPEAKER_MIXER_3:
875 	case WM8962_SPEAKER_MIXER_4:
876 	case WM8962_SPEAKER_MIXER_5:
877 	case WM8962_BEEP_GENERATOR_1:
878 	case WM8962_OSCILLATOR_TRIM_3:
879 	case WM8962_OSCILLATOR_TRIM_4:
880 	case WM8962_OSCILLATOR_TRIM_7:
881 	case WM8962_ANALOGUE_CLOCKING1:
882 	case WM8962_ANALOGUE_CLOCKING2:
883 	case WM8962_ANALOGUE_CLOCKING3:
884 	case WM8962_PLL_SOFTWARE_RESET:
885 	case WM8962_PLL2:
886 	case WM8962_PLL_4:
887 	case WM8962_PLL_9:
888 	case WM8962_PLL_10:
889 	case WM8962_PLL_11:
890 	case WM8962_PLL_12:
891 	case WM8962_PLL_13:
892 	case WM8962_PLL_14:
893 	case WM8962_PLL_15:
894 	case WM8962_PLL_16:
895 	case WM8962_FLL_CONTROL_1:
896 	case WM8962_FLL_CONTROL_2:
897 	case WM8962_FLL_CONTROL_3:
898 	case WM8962_FLL_CONTROL_5:
899 	case WM8962_FLL_CONTROL_6:
900 	case WM8962_FLL_CONTROL_7:
901 	case WM8962_FLL_CONTROL_8:
902 	case WM8962_GENERAL_TEST_1:
903 	case WM8962_DF1:
904 	case WM8962_DF2:
905 	case WM8962_DF3:
906 	case WM8962_DF4:
907 	case WM8962_DF5:
908 	case WM8962_DF6:
909 	case WM8962_DF7:
910 	case WM8962_LHPF1:
911 	case WM8962_LHPF2:
912 	case WM8962_THREED1:
913 	case WM8962_THREED2:
914 	case WM8962_THREED3:
915 	case WM8962_THREED4:
916 	case WM8962_DRC_1:
917 	case WM8962_DRC_2:
918 	case WM8962_DRC_3:
919 	case WM8962_DRC_4:
920 	case WM8962_DRC_5:
921 	case WM8962_TLOOPBACK:
922 	case WM8962_EQ1:
923 	case WM8962_EQ2:
924 	case WM8962_EQ3:
925 	case WM8962_EQ4:
926 	case WM8962_EQ5:
927 	case WM8962_EQ6:
928 	case WM8962_EQ7:
929 	case WM8962_EQ8:
930 	case WM8962_EQ9:
931 	case WM8962_EQ10:
932 	case WM8962_EQ11:
933 	case WM8962_EQ12:
934 	case WM8962_EQ13:
935 	case WM8962_EQ14:
936 	case WM8962_EQ15:
937 	case WM8962_EQ16:
938 	case WM8962_EQ17:
939 	case WM8962_EQ18:
940 	case WM8962_EQ19:
941 	case WM8962_EQ20:
942 	case WM8962_EQ21:
943 	case WM8962_EQ22:
944 	case WM8962_EQ23:
945 	case WM8962_EQ24:
946 	case WM8962_EQ25:
947 	case WM8962_EQ26:
948 	case WM8962_EQ27:
949 	case WM8962_EQ28:
950 	case WM8962_EQ29:
951 	case WM8962_EQ30:
952 	case WM8962_EQ31:
953 	case WM8962_EQ32:
954 	case WM8962_EQ33:
955 	case WM8962_EQ34:
956 	case WM8962_EQ35:
957 	case WM8962_EQ36:
958 	case WM8962_EQ37:
959 	case WM8962_EQ38:
960 	case WM8962_EQ39:
961 	case WM8962_EQ40:
962 	case WM8962_EQ41:
963 	case WM8962_GPIO_BASE:
964 	case WM8962_GPIO_2:
965 	case WM8962_GPIO_3:
966 	case WM8962_GPIO_5:
967 	case WM8962_GPIO_6:
968 	case WM8962_INTERRUPT_STATUS_1:
969 	case WM8962_INTERRUPT_STATUS_2:
970 	case WM8962_INTERRUPT_STATUS_1_MASK:
971 	case WM8962_INTERRUPT_STATUS_2_MASK:
972 	case WM8962_INTERRUPT_CONTROL:
973 	case WM8962_IRQ_DEBOUNCE:
974 	case WM8962_MICINT_SOURCE_POL:
975 	case WM8962_DSP2_POWER_MANAGEMENT:
976 	case WM8962_DSP2_EXECCONTROL:
977 	case WM8962_DSP2_INSTRUCTION_RAM_0:
978 	case WM8962_DSP2_ADDRESS_RAM_2:
979 	case WM8962_DSP2_ADDRESS_RAM_1:
980 	case WM8962_DSP2_ADDRESS_RAM_0:
981 	case WM8962_DSP2_DATA1_RAM_1:
982 	case WM8962_DSP2_DATA1_RAM_0:
983 	case WM8962_DSP2_DATA2_RAM_1:
984 	case WM8962_DSP2_DATA2_RAM_0:
985 	case WM8962_DSP2_DATA3_RAM_1:
986 	case WM8962_DSP2_DATA3_RAM_0:
987 	case WM8962_DSP2_COEFF_RAM_0:
988 	case WM8962_RETUNEADC_SHARED_COEFF_1:
989 	case WM8962_RETUNEADC_SHARED_COEFF_0:
990 	case WM8962_RETUNEDAC_SHARED_COEFF_1:
991 	case WM8962_RETUNEDAC_SHARED_COEFF_0:
992 	case WM8962_SOUNDSTAGE_ENABLES_1:
993 	case WM8962_SOUNDSTAGE_ENABLES_0:
994 	case WM8962_HDBASS_AI_1:
995 	case WM8962_HDBASS_AI_0:
996 	case WM8962_HDBASS_AR_1:
997 	case WM8962_HDBASS_AR_0:
998 	case WM8962_HDBASS_B_1:
999 	case WM8962_HDBASS_B_0:
1000 	case WM8962_HDBASS_K_1:
1001 	case WM8962_HDBASS_K_0:
1002 	case WM8962_HDBASS_N1_1:
1003 	case WM8962_HDBASS_N1_0:
1004 	case WM8962_HDBASS_N2_1:
1005 	case WM8962_HDBASS_N2_0:
1006 	case WM8962_HDBASS_N3_1:
1007 	case WM8962_HDBASS_N3_0:
1008 	case WM8962_HDBASS_N4_1:
1009 	case WM8962_HDBASS_N4_0:
1010 	case WM8962_HDBASS_N5_1:
1011 	case WM8962_HDBASS_N5_0:
1012 	case WM8962_HDBASS_X1_1:
1013 	case WM8962_HDBASS_X1_0:
1014 	case WM8962_HDBASS_X2_1:
1015 	case WM8962_HDBASS_X2_0:
1016 	case WM8962_HDBASS_X3_1:
1017 	case WM8962_HDBASS_X3_0:
1018 	case WM8962_HDBASS_ATK_1:
1019 	case WM8962_HDBASS_ATK_0:
1020 	case WM8962_HDBASS_DCY_1:
1021 	case WM8962_HDBASS_DCY_0:
1022 	case WM8962_HDBASS_PG_1:
1023 	case WM8962_HDBASS_PG_0:
1024 	case WM8962_HPF_C_1:
1025 	case WM8962_HPF_C_0:
1026 	case WM8962_ADCL_RETUNE_C1_1:
1027 	case WM8962_ADCL_RETUNE_C1_0:
1028 	case WM8962_ADCL_RETUNE_C2_1:
1029 	case WM8962_ADCL_RETUNE_C2_0:
1030 	case WM8962_ADCL_RETUNE_C3_1:
1031 	case WM8962_ADCL_RETUNE_C3_0:
1032 	case WM8962_ADCL_RETUNE_C4_1:
1033 	case WM8962_ADCL_RETUNE_C4_0:
1034 	case WM8962_ADCL_RETUNE_C5_1:
1035 	case WM8962_ADCL_RETUNE_C5_0:
1036 	case WM8962_ADCL_RETUNE_C6_1:
1037 	case WM8962_ADCL_RETUNE_C6_0:
1038 	case WM8962_ADCL_RETUNE_C7_1:
1039 	case WM8962_ADCL_RETUNE_C7_0:
1040 	case WM8962_ADCL_RETUNE_C8_1:
1041 	case WM8962_ADCL_RETUNE_C8_0:
1042 	case WM8962_ADCL_RETUNE_C9_1:
1043 	case WM8962_ADCL_RETUNE_C9_0:
1044 	case WM8962_ADCL_RETUNE_C10_1:
1045 	case WM8962_ADCL_RETUNE_C10_0:
1046 	case WM8962_ADCL_RETUNE_C11_1:
1047 	case WM8962_ADCL_RETUNE_C11_0:
1048 	case WM8962_ADCL_RETUNE_C12_1:
1049 	case WM8962_ADCL_RETUNE_C12_0:
1050 	case WM8962_ADCL_RETUNE_C13_1:
1051 	case WM8962_ADCL_RETUNE_C13_0:
1052 	case WM8962_ADCL_RETUNE_C14_1:
1053 	case WM8962_ADCL_RETUNE_C14_0:
1054 	case WM8962_ADCL_RETUNE_C15_1:
1055 	case WM8962_ADCL_RETUNE_C15_0:
1056 	case WM8962_ADCL_RETUNE_C16_1:
1057 	case WM8962_ADCL_RETUNE_C16_0:
1058 	case WM8962_ADCL_RETUNE_C17_1:
1059 	case WM8962_ADCL_RETUNE_C17_0:
1060 	case WM8962_ADCL_RETUNE_C18_1:
1061 	case WM8962_ADCL_RETUNE_C18_0:
1062 	case WM8962_ADCL_RETUNE_C19_1:
1063 	case WM8962_ADCL_RETUNE_C19_0:
1064 	case WM8962_ADCL_RETUNE_C20_1:
1065 	case WM8962_ADCL_RETUNE_C20_0:
1066 	case WM8962_ADCL_RETUNE_C21_1:
1067 	case WM8962_ADCL_RETUNE_C21_0:
1068 	case WM8962_ADCL_RETUNE_C22_1:
1069 	case WM8962_ADCL_RETUNE_C22_0:
1070 	case WM8962_ADCL_RETUNE_C23_1:
1071 	case WM8962_ADCL_RETUNE_C23_0:
1072 	case WM8962_ADCL_RETUNE_C24_1:
1073 	case WM8962_ADCL_RETUNE_C24_0:
1074 	case WM8962_ADCL_RETUNE_C25_1:
1075 	case WM8962_ADCL_RETUNE_C25_0:
1076 	case WM8962_ADCL_RETUNE_C26_1:
1077 	case WM8962_ADCL_RETUNE_C26_0:
1078 	case WM8962_ADCL_RETUNE_C27_1:
1079 	case WM8962_ADCL_RETUNE_C27_0:
1080 	case WM8962_ADCL_RETUNE_C28_1:
1081 	case WM8962_ADCL_RETUNE_C28_0:
1082 	case WM8962_ADCL_RETUNE_C29_1:
1083 	case WM8962_ADCL_RETUNE_C29_0:
1084 	case WM8962_ADCL_RETUNE_C30_1:
1085 	case WM8962_ADCL_RETUNE_C30_0:
1086 	case WM8962_ADCL_RETUNE_C31_1:
1087 	case WM8962_ADCL_RETUNE_C31_0:
1088 	case WM8962_ADCL_RETUNE_C32_1:
1089 	case WM8962_ADCL_RETUNE_C32_0:
1090 	case WM8962_RETUNEADC_PG2_1:
1091 	case WM8962_RETUNEADC_PG2_0:
1092 	case WM8962_RETUNEADC_PG_1:
1093 	case WM8962_RETUNEADC_PG_0:
1094 	case WM8962_ADCR_RETUNE_C1_1:
1095 	case WM8962_ADCR_RETUNE_C1_0:
1096 	case WM8962_ADCR_RETUNE_C2_1:
1097 	case WM8962_ADCR_RETUNE_C2_0:
1098 	case WM8962_ADCR_RETUNE_C3_1:
1099 	case WM8962_ADCR_RETUNE_C3_0:
1100 	case WM8962_ADCR_RETUNE_C4_1:
1101 	case WM8962_ADCR_RETUNE_C4_0:
1102 	case WM8962_ADCR_RETUNE_C5_1:
1103 	case WM8962_ADCR_RETUNE_C5_0:
1104 	case WM8962_ADCR_RETUNE_C6_1:
1105 	case WM8962_ADCR_RETUNE_C6_0:
1106 	case WM8962_ADCR_RETUNE_C7_1:
1107 	case WM8962_ADCR_RETUNE_C7_0:
1108 	case WM8962_ADCR_RETUNE_C8_1:
1109 	case WM8962_ADCR_RETUNE_C8_0:
1110 	case WM8962_ADCR_RETUNE_C9_1:
1111 	case WM8962_ADCR_RETUNE_C9_0:
1112 	case WM8962_ADCR_RETUNE_C10_1:
1113 	case WM8962_ADCR_RETUNE_C10_0:
1114 	case WM8962_ADCR_RETUNE_C11_1:
1115 	case WM8962_ADCR_RETUNE_C11_0:
1116 	case WM8962_ADCR_RETUNE_C12_1:
1117 	case WM8962_ADCR_RETUNE_C12_0:
1118 	case WM8962_ADCR_RETUNE_C13_1:
1119 	case WM8962_ADCR_RETUNE_C13_0:
1120 	case WM8962_ADCR_RETUNE_C14_1:
1121 	case WM8962_ADCR_RETUNE_C14_0:
1122 	case WM8962_ADCR_RETUNE_C15_1:
1123 	case WM8962_ADCR_RETUNE_C15_0:
1124 	case WM8962_ADCR_RETUNE_C16_1:
1125 	case WM8962_ADCR_RETUNE_C16_0:
1126 	case WM8962_ADCR_RETUNE_C17_1:
1127 	case WM8962_ADCR_RETUNE_C17_0:
1128 	case WM8962_ADCR_RETUNE_C18_1:
1129 	case WM8962_ADCR_RETUNE_C18_0:
1130 	case WM8962_ADCR_RETUNE_C19_1:
1131 	case WM8962_ADCR_RETUNE_C19_0:
1132 	case WM8962_ADCR_RETUNE_C20_1:
1133 	case WM8962_ADCR_RETUNE_C20_0:
1134 	case WM8962_ADCR_RETUNE_C21_1:
1135 	case WM8962_ADCR_RETUNE_C21_0:
1136 	case WM8962_ADCR_RETUNE_C22_1:
1137 	case WM8962_ADCR_RETUNE_C22_0:
1138 	case WM8962_ADCR_RETUNE_C23_1:
1139 	case WM8962_ADCR_RETUNE_C23_0:
1140 	case WM8962_ADCR_RETUNE_C24_1:
1141 	case WM8962_ADCR_RETUNE_C24_0:
1142 	case WM8962_ADCR_RETUNE_C25_1:
1143 	case WM8962_ADCR_RETUNE_C25_0:
1144 	case WM8962_ADCR_RETUNE_C26_1:
1145 	case WM8962_ADCR_RETUNE_C26_0:
1146 	case WM8962_ADCR_RETUNE_C27_1:
1147 	case WM8962_ADCR_RETUNE_C27_0:
1148 	case WM8962_ADCR_RETUNE_C28_1:
1149 	case WM8962_ADCR_RETUNE_C28_0:
1150 	case WM8962_ADCR_RETUNE_C29_1:
1151 	case WM8962_ADCR_RETUNE_C29_0:
1152 	case WM8962_ADCR_RETUNE_C30_1:
1153 	case WM8962_ADCR_RETUNE_C30_0:
1154 	case WM8962_ADCR_RETUNE_C31_1:
1155 	case WM8962_ADCR_RETUNE_C31_0:
1156 	case WM8962_ADCR_RETUNE_C32_1:
1157 	case WM8962_ADCR_RETUNE_C32_0:
1158 	case WM8962_DACL_RETUNE_C1_1:
1159 	case WM8962_DACL_RETUNE_C1_0:
1160 	case WM8962_DACL_RETUNE_C2_1:
1161 	case WM8962_DACL_RETUNE_C2_0:
1162 	case WM8962_DACL_RETUNE_C3_1:
1163 	case WM8962_DACL_RETUNE_C3_0:
1164 	case WM8962_DACL_RETUNE_C4_1:
1165 	case WM8962_DACL_RETUNE_C4_0:
1166 	case WM8962_DACL_RETUNE_C5_1:
1167 	case WM8962_DACL_RETUNE_C5_0:
1168 	case WM8962_DACL_RETUNE_C6_1:
1169 	case WM8962_DACL_RETUNE_C6_0:
1170 	case WM8962_DACL_RETUNE_C7_1:
1171 	case WM8962_DACL_RETUNE_C7_0:
1172 	case WM8962_DACL_RETUNE_C8_1:
1173 	case WM8962_DACL_RETUNE_C8_0:
1174 	case WM8962_DACL_RETUNE_C9_1:
1175 	case WM8962_DACL_RETUNE_C9_0:
1176 	case WM8962_DACL_RETUNE_C10_1:
1177 	case WM8962_DACL_RETUNE_C10_0:
1178 	case WM8962_DACL_RETUNE_C11_1:
1179 	case WM8962_DACL_RETUNE_C11_0:
1180 	case WM8962_DACL_RETUNE_C12_1:
1181 	case WM8962_DACL_RETUNE_C12_0:
1182 	case WM8962_DACL_RETUNE_C13_1:
1183 	case WM8962_DACL_RETUNE_C13_0:
1184 	case WM8962_DACL_RETUNE_C14_1:
1185 	case WM8962_DACL_RETUNE_C14_0:
1186 	case WM8962_DACL_RETUNE_C15_1:
1187 	case WM8962_DACL_RETUNE_C15_0:
1188 	case WM8962_DACL_RETUNE_C16_1:
1189 	case WM8962_DACL_RETUNE_C16_0:
1190 	case WM8962_DACL_RETUNE_C17_1:
1191 	case WM8962_DACL_RETUNE_C17_0:
1192 	case WM8962_DACL_RETUNE_C18_1:
1193 	case WM8962_DACL_RETUNE_C18_0:
1194 	case WM8962_DACL_RETUNE_C19_1:
1195 	case WM8962_DACL_RETUNE_C19_0:
1196 	case WM8962_DACL_RETUNE_C20_1:
1197 	case WM8962_DACL_RETUNE_C20_0:
1198 	case WM8962_DACL_RETUNE_C21_1:
1199 	case WM8962_DACL_RETUNE_C21_0:
1200 	case WM8962_DACL_RETUNE_C22_1:
1201 	case WM8962_DACL_RETUNE_C22_0:
1202 	case WM8962_DACL_RETUNE_C23_1:
1203 	case WM8962_DACL_RETUNE_C23_0:
1204 	case WM8962_DACL_RETUNE_C24_1:
1205 	case WM8962_DACL_RETUNE_C24_0:
1206 	case WM8962_DACL_RETUNE_C25_1:
1207 	case WM8962_DACL_RETUNE_C25_0:
1208 	case WM8962_DACL_RETUNE_C26_1:
1209 	case WM8962_DACL_RETUNE_C26_0:
1210 	case WM8962_DACL_RETUNE_C27_1:
1211 	case WM8962_DACL_RETUNE_C27_0:
1212 	case WM8962_DACL_RETUNE_C28_1:
1213 	case WM8962_DACL_RETUNE_C28_0:
1214 	case WM8962_DACL_RETUNE_C29_1:
1215 	case WM8962_DACL_RETUNE_C29_0:
1216 	case WM8962_DACL_RETUNE_C30_1:
1217 	case WM8962_DACL_RETUNE_C30_0:
1218 	case WM8962_DACL_RETUNE_C31_1:
1219 	case WM8962_DACL_RETUNE_C31_0:
1220 	case WM8962_DACL_RETUNE_C32_1:
1221 	case WM8962_DACL_RETUNE_C32_0:
1222 	case WM8962_RETUNEDAC_PG2_1:
1223 	case WM8962_RETUNEDAC_PG2_0:
1224 	case WM8962_RETUNEDAC_PG_1:
1225 	case WM8962_RETUNEDAC_PG_0:
1226 	case WM8962_DACR_RETUNE_C1_1:
1227 	case WM8962_DACR_RETUNE_C1_0:
1228 	case WM8962_DACR_RETUNE_C2_1:
1229 	case WM8962_DACR_RETUNE_C2_0:
1230 	case WM8962_DACR_RETUNE_C3_1:
1231 	case WM8962_DACR_RETUNE_C3_0:
1232 	case WM8962_DACR_RETUNE_C4_1:
1233 	case WM8962_DACR_RETUNE_C4_0:
1234 	case WM8962_DACR_RETUNE_C5_1:
1235 	case WM8962_DACR_RETUNE_C5_0:
1236 	case WM8962_DACR_RETUNE_C6_1:
1237 	case WM8962_DACR_RETUNE_C6_0:
1238 	case WM8962_DACR_RETUNE_C7_1:
1239 	case WM8962_DACR_RETUNE_C7_0:
1240 	case WM8962_DACR_RETUNE_C8_1:
1241 	case WM8962_DACR_RETUNE_C8_0:
1242 	case WM8962_DACR_RETUNE_C9_1:
1243 	case WM8962_DACR_RETUNE_C9_0:
1244 	case WM8962_DACR_RETUNE_C10_1:
1245 	case WM8962_DACR_RETUNE_C10_0:
1246 	case WM8962_DACR_RETUNE_C11_1:
1247 	case WM8962_DACR_RETUNE_C11_0:
1248 	case WM8962_DACR_RETUNE_C12_1:
1249 	case WM8962_DACR_RETUNE_C12_0:
1250 	case WM8962_DACR_RETUNE_C13_1:
1251 	case WM8962_DACR_RETUNE_C13_0:
1252 	case WM8962_DACR_RETUNE_C14_1:
1253 	case WM8962_DACR_RETUNE_C14_0:
1254 	case WM8962_DACR_RETUNE_C15_1:
1255 	case WM8962_DACR_RETUNE_C15_0:
1256 	case WM8962_DACR_RETUNE_C16_1:
1257 	case WM8962_DACR_RETUNE_C16_0:
1258 	case WM8962_DACR_RETUNE_C17_1:
1259 	case WM8962_DACR_RETUNE_C17_0:
1260 	case WM8962_DACR_RETUNE_C18_1:
1261 	case WM8962_DACR_RETUNE_C18_0:
1262 	case WM8962_DACR_RETUNE_C19_1:
1263 	case WM8962_DACR_RETUNE_C19_0:
1264 	case WM8962_DACR_RETUNE_C20_1:
1265 	case WM8962_DACR_RETUNE_C20_0:
1266 	case WM8962_DACR_RETUNE_C21_1:
1267 	case WM8962_DACR_RETUNE_C21_0:
1268 	case WM8962_DACR_RETUNE_C22_1:
1269 	case WM8962_DACR_RETUNE_C22_0:
1270 	case WM8962_DACR_RETUNE_C23_1:
1271 	case WM8962_DACR_RETUNE_C23_0:
1272 	case WM8962_DACR_RETUNE_C24_1:
1273 	case WM8962_DACR_RETUNE_C24_0:
1274 	case WM8962_DACR_RETUNE_C25_1:
1275 	case WM8962_DACR_RETUNE_C25_0:
1276 	case WM8962_DACR_RETUNE_C26_1:
1277 	case WM8962_DACR_RETUNE_C26_0:
1278 	case WM8962_DACR_RETUNE_C27_1:
1279 	case WM8962_DACR_RETUNE_C27_0:
1280 	case WM8962_DACR_RETUNE_C28_1:
1281 	case WM8962_DACR_RETUNE_C28_0:
1282 	case WM8962_DACR_RETUNE_C29_1:
1283 	case WM8962_DACR_RETUNE_C29_0:
1284 	case WM8962_DACR_RETUNE_C30_1:
1285 	case WM8962_DACR_RETUNE_C30_0:
1286 	case WM8962_DACR_RETUNE_C31_1:
1287 	case WM8962_DACR_RETUNE_C31_0:
1288 	case WM8962_DACR_RETUNE_C32_1:
1289 	case WM8962_DACR_RETUNE_C32_0:
1290 	case WM8962_VSS_XHD2_1:
1291 	case WM8962_VSS_XHD2_0:
1292 	case WM8962_VSS_XHD3_1:
1293 	case WM8962_VSS_XHD3_0:
1294 	case WM8962_VSS_XHN1_1:
1295 	case WM8962_VSS_XHN1_0:
1296 	case WM8962_VSS_XHN2_1:
1297 	case WM8962_VSS_XHN2_0:
1298 	case WM8962_VSS_XHN3_1:
1299 	case WM8962_VSS_XHN3_0:
1300 	case WM8962_VSS_XLA_1:
1301 	case WM8962_VSS_XLA_0:
1302 	case WM8962_VSS_XLB_1:
1303 	case WM8962_VSS_XLB_0:
1304 	case WM8962_VSS_XLG_1:
1305 	case WM8962_VSS_XLG_0:
1306 	case WM8962_VSS_PG2_1:
1307 	case WM8962_VSS_PG2_0:
1308 	case WM8962_VSS_PG_1:
1309 	case WM8962_VSS_PG_0:
1310 	case WM8962_VSS_XTD1_1:
1311 	case WM8962_VSS_XTD1_0:
1312 	case WM8962_VSS_XTD2_1:
1313 	case WM8962_VSS_XTD2_0:
1314 	case WM8962_VSS_XTD3_1:
1315 	case WM8962_VSS_XTD3_0:
1316 	case WM8962_VSS_XTD4_1:
1317 	case WM8962_VSS_XTD4_0:
1318 	case WM8962_VSS_XTD5_1:
1319 	case WM8962_VSS_XTD5_0:
1320 	case WM8962_VSS_XTD6_1:
1321 	case WM8962_VSS_XTD6_0:
1322 	case WM8962_VSS_XTD7_1:
1323 	case WM8962_VSS_XTD7_0:
1324 	case WM8962_VSS_XTD8_1:
1325 	case WM8962_VSS_XTD8_0:
1326 	case WM8962_VSS_XTD9_1:
1327 	case WM8962_VSS_XTD9_0:
1328 	case WM8962_VSS_XTD10_1:
1329 	case WM8962_VSS_XTD10_0:
1330 	case WM8962_VSS_XTD11_1:
1331 	case WM8962_VSS_XTD11_0:
1332 	case WM8962_VSS_XTD12_1:
1333 	case WM8962_VSS_XTD12_0:
1334 	case WM8962_VSS_XTD13_1:
1335 	case WM8962_VSS_XTD13_0:
1336 	case WM8962_VSS_XTD14_1:
1337 	case WM8962_VSS_XTD14_0:
1338 	case WM8962_VSS_XTD15_1:
1339 	case WM8962_VSS_XTD15_0:
1340 	case WM8962_VSS_XTD16_1:
1341 	case WM8962_VSS_XTD16_0:
1342 	case WM8962_VSS_XTD17_1:
1343 	case WM8962_VSS_XTD17_0:
1344 	case WM8962_VSS_XTD18_1:
1345 	case WM8962_VSS_XTD18_0:
1346 	case WM8962_VSS_XTD19_1:
1347 	case WM8962_VSS_XTD19_0:
1348 	case WM8962_VSS_XTD20_1:
1349 	case WM8962_VSS_XTD20_0:
1350 	case WM8962_VSS_XTD21_1:
1351 	case WM8962_VSS_XTD21_0:
1352 	case WM8962_VSS_XTD22_1:
1353 	case WM8962_VSS_XTD22_0:
1354 	case WM8962_VSS_XTD23_1:
1355 	case WM8962_VSS_XTD23_0:
1356 	case WM8962_VSS_XTD24_1:
1357 	case WM8962_VSS_XTD24_0:
1358 	case WM8962_VSS_XTD25_1:
1359 	case WM8962_VSS_XTD25_0:
1360 	case WM8962_VSS_XTD26_1:
1361 	case WM8962_VSS_XTD26_0:
1362 	case WM8962_VSS_XTD27_1:
1363 	case WM8962_VSS_XTD27_0:
1364 	case WM8962_VSS_XTD28_1:
1365 	case WM8962_VSS_XTD28_0:
1366 	case WM8962_VSS_XTD29_1:
1367 	case WM8962_VSS_XTD29_0:
1368 	case WM8962_VSS_XTD30_1:
1369 	case WM8962_VSS_XTD30_0:
1370 	case WM8962_VSS_XTD31_1:
1371 	case WM8962_VSS_XTD31_0:
1372 	case WM8962_VSS_XTD32_1:
1373 	case WM8962_VSS_XTD32_0:
1374 	case WM8962_VSS_XTS1_1:
1375 	case WM8962_VSS_XTS1_0:
1376 	case WM8962_VSS_XTS2_1:
1377 	case WM8962_VSS_XTS2_0:
1378 	case WM8962_VSS_XTS3_1:
1379 	case WM8962_VSS_XTS3_0:
1380 	case WM8962_VSS_XTS4_1:
1381 	case WM8962_VSS_XTS4_0:
1382 	case WM8962_VSS_XTS5_1:
1383 	case WM8962_VSS_XTS5_0:
1384 	case WM8962_VSS_XTS6_1:
1385 	case WM8962_VSS_XTS6_0:
1386 	case WM8962_VSS_XTS7_1:
1387 	case WM8962_VSS_XTS7_0:
1388 	case WM8962_VSS_XTS8_1:
1389 	case WM8962_VSS_XTS8_0:
1390 	case WM8962_VSS_XTS9_1:
1391 	case WM8962_VSS_XTS9_0:
1392 	case WM8962_VSS_XTS10_1:
1393 	case WM8962_VSS_XTS10_0:
1394 	case WM8962_VSS_XTS11_1:
1395 	case WM8962_VSS_XTS11_0:
1396 	case WM8962_VSS_XTS12_1:
1397 	case WM8962_VSS_XTS12_0:
1398 	case WM8962_VSS_XTS13_1:
1399 	case WM8962_VSS_XTS13_0:
1400 	case WM8962_VSS_XTS14_1:
1401 	case WM8962_VSS_XTS14_0:
1402 	case WM8962_VSS_XTS15_1:
1403 	case WM8962_VSS_XTS15_0:
1404 	case WM8962_VSS_XTS16_1:
1405 	case WM8962_VSS_XTS16_0:
1406 	case WM8962_VSS_XTS17_1:
1407 	case WM8962_VSS_XTS17_0:
1408 	case WM8962_VSS_XTS18_1:
1409 	case WM8962_VSS_XTS18_0:
1410 	case WM8962_VSS_XTS19_1:
1411 	case WM8962_VSS_XTS19_0:
1412 	case WM8962_VSS_XTS20_1:
1413 	case WM8962_VSS_XTS20_0:
1414 	case WM8962_VSS_XTS21_1:
1415 	case WM8962_VSS_XTS21_0:
1416 	case WM8962_VSS_XTS22_1:
1417 	case WM8962_VSS_XTS22_0:
1418 	case WM8962_VSS_XTS23_1:
1419 	case WM8962_VSS_XTS23_0:
1420 	case WM8962_VSS_XTS24_1:
1421 	case WM8962_VSS_XTS24_0:
1422 	case WM8962_VSS_XTS25_1:
1423 	case WM8962_VSS_XTS25_0:
1424 	case WM8962_VSS_XTS26_1:
1425 	case WM8962_VSS_XTS26_0:
1426 	case WM8962_VSS_XTS27_1:
1427 	case WM8962_VSS_XTS27_0:
1428 	case WM8962_VSS_XTS28_1:
1429 	case WM8962_VSS_XTS28_0:
1430 	case WM8962_VSS_XTS29_1:
1431 	case WM8962_VSS_XTS29_0:
1432 	case WM8962_VSS_XTS30_1:
1433 	case WM8962_VSS_XTS30_0:
1434 	case WM8962_VSS_XTS31_1:
1435 	case WM8962_VSS_XTS31_0:
1436 	case WM8962_VSS_XTS32_1:
1437 	case WM8962_VSS_XTS32_0:
1438 		return true;
1439 	default:
1440 		return false;
1441 	}
1442 }
1443 
1444 static int wm8962_reset(struct wm8962_priv *wm8962)
1445 {
1446 	int ret;
1447 
1448 	ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1449 	if (ret != 0)
1450 		return ret;
1451 
1452 	return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1453 }
1454 
1455 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457 static const unsigned int mixinpga_tlv[] = {
1458 	TLV_DB_RANGE_HEAD(5),
1459 	0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460 	2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461 	3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462 	5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463 	6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464 };
1465 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472 static const unsigned int classd_tlv[] = {
1473 	TLV_DB_RANGE_HEAD(2),
1474 	0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475 	7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476 };
1477 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478 
1479 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480 {
1481 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1482 
1483 	return regcache_sync_region(wm8962->regmap,
1484 				    WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1485 }
1486 
1487 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1488 {
1489 	u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1490 	u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1491 	u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1492 
1493 	/* Mute the ADCs and DACs */
1494 	snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1495 	snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1496 	snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1497 			    WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1498 
1499 	snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1500 
1501 	/* Restore the ADCs and DACs */
1502 	snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1503 	snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1504 	snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1505 			    WM8962_DAC_MUTE, dac);
1506 
1507 	return 0;
1508 }
1509 
1510 static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1511 {
1512 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1513 
1514 	wm8962_dsp2_write_config(codec);
1515 
1516 	snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1517 
1518 	wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1519 
1520 	return 0;
1521 }
1522 
1523 static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1524 {
1525 	wm8962_dsp2_set_enable(codec, 0);
1526 
1527 	snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1528 
1529 	return 0;
1530 }
1531 
1532 #define WM8962_DSP2_ENABLE(xname, xshift) \
1533 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1534 	.info = wm8962_dsp2_ena_info, \
1535 	.get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1536 	.private_value = xshift }
1537 
1538 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1539 				struct snd_ctl_elem_info *uinfo)
1540 {
1541 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1542 
1543 	uinfo->count = 1;
1544 	uinfo->value.integer.min = 0;
1545 	uinfo->value.integer.max = 1;
1546 
1547 	return 0;
1548 }
1549 
1550 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1551 			       struct snd_ctl_elem_value *ucontrol)
1552 {
1553 	int shift = kcontrol->private_value;
1554 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1555 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1556 
1557 	ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1558 
1559 	return 0;
1560 }
1561 
1562 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1563 			       struct snd_ctl_elem_value *ucontrol)
1564 {
1565 	int shift = kcontrol->private_value;
1566 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1567 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1568 	int old = wm8962->dsp2_ena;
1569 	int ret = 0;
1570 	int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1571 		WM8962_DSP2_ENA;
1572 
1573 	mutex_lock(&codec->mutex);
1574 
1575 	if (ucontrol->value.integer.value[0])
1576 		wm8962->dsp2_ena |= 1 << shift;
1577 	else
1578 		wm8962->dsp2_ena &= ~(1 << shift);
1579 
1580 	if (wm8962->dsp2_ena == old)
1581 		goto out;
1582 
1583 	ret = 1;
1584 
1585 	if (dsp2_running) {
1586 		if (wm8962->dsp2_ena)
1587 			wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1588 		else
1589 			wm8962_dsp2_stop(codec);
1590 	}
1591 
1592 out:
1593 	mutex_unlock(&codec->mutex);
1594 
1595 	return ret;
1596 }
1597 
1598 /* The VU bits for the headphones are in a different register to the mute
1599  * bits and only take effect on the PGA if it is actually powered.
1600  */
1601 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1602 			    struct snd_ctl_elem_value *ucontrol)
1603 {
1604 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1605 	int ret;
1606 
1607 	/* Apply the update (if any) */
1608         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1609 	if (ret == 0)
1610 		return 0;
1611 
1612 	/* If the left PGA is enabled hit that VU bit... */
1613 	ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1614 	if (ret & WM8962_HPOUTL_PGA_ENA) {
1615 		snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1616 			      snd_soc_read(codec, WM8962_HPOUTL_VOLUME));
1617 		return 1;
1618 	}
1619 
1620 	/* ...otherwise the right.  The VU is stereo. */
1621 	if (ret & WM8962_HPOUTR_PGA_ENA)
1622 		snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1623 			      snd_soc_read(codec, WM8962_HPOUTR_VOLUME));
1624 
1625 	return 1;
1626 }
1627 
1628 /* The VU bits for the speakers are in a different register to the mute
1629  * bits and only take effect on the PGA if it is actually powered.
1630  */
1631 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1632 			    struct snd_ctl_elem_value *ucontrol)
1633 {
1634 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1635 	int ret;
1636 
1637 	/* Apply the update (if any) */
1638         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1639 	if (ret == 0)
1640 		return 0;
1641 
1642 	/* If the left PGA is enabled hit that VU bit... */
1643 	ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1644 	if (ret & WM8962_SPKOUTL_PGA_ENA) {
1645 		snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1646 			      snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1647 		return 1;
1648 	}
1649 
1650 	/* ...otherwise the right.  The VU is stereo. */
1651 	if (ret & WM8962_SPKOUTR_PGA_ENA)
1652 		snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1653 			      snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1654 
1655 	return 1;
1656 }
1657 
1658 static const char *cap_hpf_mode_text[] = {
1659 	"Hi-fi", "Application"
1660 };
1661 
1662 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1663 			    WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1664 
1665 
1666 static const char *cap_lhpf_mode_text[] = {
1667 	"LPF", "HPF"
1668 };
1669 
1670 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1671 			    WM8962_LHPF1, 1, cap_lhpf_mode_text);
1672 
1673 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1674 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1675 
1676 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1677 	       mixin_tlv),
1678 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1679 	       mixinpga_tlv),
1680 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1681 	       mixin_tlv),
1682 
1683 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1684 	       mixin_tlv),
1685 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1686 	       mixinpga_tlv),
1687 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1688 	       mixin_tlv),
1689 
1690 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1691 		 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1692 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1693 		 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1694 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1695 	     WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1696 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1697 	     WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1698 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1699 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1700 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1701 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1702 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1703 
1704 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1705 		 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1706 
1707 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1708 		 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1709 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1710 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1711 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1712 
1713 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1714 	   5, 1, 0),
1715 
1716 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1717 
1718 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1719 		 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1720 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1721 	       snd_soc_get_volsw, wm8962_put_hp_sw),
1722 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1723 	     7, 1, 0),
1724 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1725 	       hp_tlv),
1726 
1727 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1728 	     WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1729 
1730 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1731 	       3, 7, 0, bypass_tlv),
1732 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1733 	       0, 7, 0, bypass_tlv),
1734 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1735 	       7, 1, 1, inmix_tlv),
1736 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1737 	       6, 1, 1, inmix_tlv),
1738 
1739 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1740 	       3, 7, 0, bypass_tlv),
1741 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1742 	       0, 7, 0, bypass_tlv),
1743 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1744 	       7, 1, 1, inmix_tlv),
1745 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1746 	       6, 1, 1, inmix_tlv),
1747 
1748 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1749 	       classd_tlv),
1750 
1751 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1752 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1753 		 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1754 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1755 		 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1756 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1757 		 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1758 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1759 		 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1760 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1761 		 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1762 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1763 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1764 
1765 
1766 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1767 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1768 
1769 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1770 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1771 
1772 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1773 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1774 
1775 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1776 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1777 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1778 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1779 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1780 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1781 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1782 
1783 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1784 		WM8962_ALCR_ENA_SHIFT, 1, 0),
1785 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1786 		WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1787 };
1788 
1789 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1790 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1791 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1792 	       snd_soc_get_volsw, wm8962_put_spk_sw),
1793 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1794 
1795 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1796 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1797 	       3, 7, 0, bypass_tlv),
1798 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1799 	       0, 7, 0, bypass_tlv),
1800 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1801 	       7, 1, 1, inmix_tlv),
1802 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1803 	       6, 1, 1, inmix_tlv),
1804 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1805 	       7, 1, 0, inmix_tlv),
1806 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1807 	       6, 1, 0, inmix_tlv),
1808 };
1809 
1810 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1811 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1812 		 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1813 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1814 	       snd_soc_get_volsw, wm8962_put_spk_sw),
1815 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1816 	     7, 1, 0),
1817 
1818 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1819 	     WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1820 
1821 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1822 	       3, 7, 0, bypass_tlv),
1823 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1824 	       0, 7, 0, bypass_tlv),
1825 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1826 	       7, 1, 1, inmix_tlv),
1827 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1828 	       6, 1, 1, inmix_tlv),
1829 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1830 	       7, 1, 0, inmix_tlv),
1831 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1832 	       6, 1, 0, inmix_tlv),
1833 
1834 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1835 	       3, 7, 0, bypass_tlv),
1836 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1837 	       0, 7, 0, bypass_tlv),
1838 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1839 	       7, 1, 1, inmix_tlv),
1840 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1841 	       6, 1, 1, inmix_tlv),
1842 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1843 	       5, 1, 0, inmix_tlv),
1844 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1845 	       4, 1, 0, inmix_tlv),
1846 };
1847 
1848 static int cp_event(struct snd_soc_dapm_widget *w,
1849 		    struct snd_kcontrol *kcontrol, int event)
1850 {
1851 	switch (event) {
1852 	case SND_SOC_DAPM_POST_PMU:
1853 		msleep(5);
1854 		break;
1855 
1856 	default:
1857 		WARN(1, "Invalid event %d\n", event);
1858 		return -EINVAL;
1859 	}
1860 
1861 	return 0;
1862 }
1863 
1864 static int hp_event(struct snd_soc_dapm_widget *w,
1865 		    struct snd_kcontrol *kcontrol, int event)
1866 {
1867 	struct snd_soc_codec *codec = w->codec;
1868 	int timeout;
1869 	int reg;
1870 	int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1871 			WM8962_DCS_STARTUP_DONE_HP1R);
1872 
1873 	switch (event) {
1874 	case SND_SOC_DAPM_POST_PMU:
1875 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1876 				    WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1877 				    WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1878 		udelay(20);
1879 
1880 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1881 				    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1882 				    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1883 
1884 		/* Start the DC servo */
1885 		snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1886 				    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1887 				    WM8962_HP1L_DCS_STARTUP |
1888 				    WM8962_HP1R_DCS_STARTUP,
1889 				    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1890 				    WM8962_HP1L_DCS_STARTUP |
1891 				    WM8962_HP1R_DCS_STARTUP);
1892 
1893 		/* Wait for it to complete, should be well under 100ms */
1894 		timeout = 0;
1895 		do {
1896 			msleep(1);
1897 			reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1898 			if (reg < 0) {
1899 				dev_err(codec->dev,
1900 					"Failed to read DCS status: %d\n",
1901 					reg);
1902 				continue;
1903 			}
1904 			dev_dbg(codec->dev, "DCS status: %x\n", reg);
1905 		} while (++timeout < 200 && (reg & expected) != expected);
1906 
1907 		if ((reg & expected) != expected)
1908 			dev_err(codec->dev, "DC servo timed out\n");
1909 		else
1910 			dev_dbg(codec->dev, "DC servo complete after %dms\n",
1911 				timeout);
1912 
1913 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1914 				    WM8962_HP1L_ENA_OUTP |
1915 				    WM8962_HP1R_ENA_OUTP,
1916 				    WM8962_HP1L_ENA_OUTP |
1917 				    WM8962_HP1R_ENA_OUTP);
1918 		udelay(20);
1919 
1920 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1921 				    WM8962_HP1L_RMV_SHORT |
1922 				    WM8962_HP1R_RMV_SHORT,
1923 				    WM8962_HP1L_RMV_SHORT |
1924 				    WM8962_HP1R_RMV_SHORT);
1925 		break;
1926 
1927 	case SND_SOC_DAPM_PRE_PMD:
1928 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1929 				    WM8962_HP1L_RMV_SHORT |
1930 				    WM8962_HP1R_RMV_SHORT, 0);
1931 
1932 		udelay(20);
1933 
1934 		snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1935 				    WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1936 				    WM8962_HP1L_DCS_STARTUP |
1937 				    WM8962_HP1R_DCS_STARTUP,
1938 				    0);
1939 
1940 		snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1941 				    WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1942 				    WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1943 				    WM8962_HP1L_ENA_OUTP |
1944 				    WM8962_HP1R_ENA_OUTP, 0);
1945 
1946 		break;
1947 
1948 	default:
1949 		WARN(1, "Invalid event %d\n", event);
1950 		return -EINVAL;
1951 
1952 	}
1953 
1954 	return 0;
1955 }
1956 
1957 /* VU bits for the output PGAs only take effect while the PGA is powered */
1958 static int out_pga_event(struct snd_soc_dapm_widget *w,
1959 			 struct snd_kcontrol *kcontrol, int event)
1960 {
1961 	struct snd_soc_codec *codec = w->codec;
1962 	int reg;
1963 
1964 	switch (w->shift) {
1965 	case WM8962_HPOUTR_PGA_ENA_SHIFT:
1966 		reg = WM8962_HPOUTR_VOLUME;
1967 		break;
1968 	case WM8962_HPOUTL_PGA_ENA_SHIFT:
1969 		reg = WM8962_HPOUTL_VOLUME;
1970 		break;
1971 	case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1972 		reg = WM8962_SPKOUTR_VOLUME;
1973 		break;
1974 	case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1975 		reg = WM8962_SPKOUTL_VOLUME;
1976 		break;
1977 	default:
1978 		WARN(1, "Invalid shift %d\n", w->shift);
1979 		return -EINVAL;
1980 	}
1981 
1982 	switch (event) {
1983 	case SND_SOC_DAPM_POST_PMU:
1984 		return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1985 	default:
1986 		WARN(1, "Invalid event %d\n", event);
1987 		return -EINVAL;
1988 	}
1989 }
1990 
1991 static int dsp2_event(struct snd_soc_dapm_widget *w,
1992 		      struct snd_kcontrol *kcontrol, int event)
1993 {
1994 	struct snd_soc_codec *codec = w->codec;
1995 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1996 
1997 	switch (event) {
1998 	case SND_SOC_DAPM_POST_PMU:
1999 		if (wm8962->dsp2_ena)
2000 			wm8962_dsp2_start(codec);
2001 		break;
2002 
2003 	case SND_SOC_DAPM_PRE_PMD:
2004 		if (wm8962->dsp2_ena)
2005 			wm8962_dsp2_stop(codec);
2006 		break;
2007 
2008 	default:
2009 		WARN(1, "Invalid event %d\n", event);
2010 		return -EINVAL;
2011 	}
2012 
2013 	return 0;
2014 }
2015 
2016 static const char *st_text[] = { "None", "Left", "Right" };
2017 
2018 static SOC_ENUM_SINGLE_DECL(str_enum,
2019 			    WM8962_DAC_DSP_MIXING_1, 2, st_text);
2020 
2021 static const struct snd_kcontrol_new str_mux =
2022 	SOC_DAPM_ENUM("Right Sidetone", str_enum);
2023 
2024 static SOC_ENUM_SINGLE_DECL(stl_enum,
2025 			    WM8962_DAC_DSP_MIXING_2, 2, st_text);
2026 
2027 static const struct snd_kcontrol_new stl_mux =
2028 	SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2029 
2030 static const char *outmux_text[] = { "DAC", "Mixer" };
2031 
2032 static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2033 			    WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2034 
2035 static const struct snd_kcontrol_new spkoutr_mux =
2036 	SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2037 
2038 static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2039 			    WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2040 
2041 static const struct snd_kcontrol_new spkoutl_mux =
2042 	SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2043 
2044 static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2045 			    WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2046 
2047 static const struct snd_kcontrol_new hpoutr_mux =
2048 	SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2049 
2050 static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2051 			    WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2052 
2053 static const struct snd_kcontrol_new hpoutl_mux =
2054 	SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2055 
2056 static const struct snd_kcontrol_new inpgal[] = {
2057 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2058 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2059 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2060 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2061 };
2062 
2063 static const struct snd_kcontrol_new inpgar[] = {
2064 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2065 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2066 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2067 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2068 };
2069 
2070 static const struct snd_kcontrol_new mixinl[] = {
2071 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2072 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2073 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2074 };
2075 
2076 static const struct snd_kcontrol_new mixinr[] = {
2077 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2078 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2079 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2080 };
2081 
2082 static const struct snd_kcontrol_new hpmixl[] = {
2083 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2084 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2085 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2086 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2087 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2088 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2089 };
2090 
2091 static const struct snd_kcontrol_new hpmixr[] = {
2092 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2093 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2094 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2095 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2096 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2097 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2098 };
2099 
2100 static const struct snd_kcontrol_new spkmixl[] = {
2101 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2102 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2103 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2104 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2105 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2106 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2107 };
2108 
2109 static const struct snd_kcontrol_new spkmixr[] = {
2110 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2111 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2112 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2113 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2114 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2115 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2116 };
2117 
2118 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2119 SND_SOC_DAPM_INPUT("IN1L"),
2120 SND_SOC_DAPM_INPUT("IN1R"),
2121 SND_SOC_DAPM_INPUT("IN2L"),
2122 SND_SOC_DAPM_INPUT("IN2R"),
2123 SND_SOC_DAPM_INPUT("IN3L"),
2124 SND_SOC_DAPM_INPUT("IN3R"),
2125 SND_SOC_DAPM_INPUT("IN4L"),
2126 SND_SOC_DAPM_INPUT("IN4R"),
2127 SND_SOC_DAPM_SIGGEN("Beep"),
2128 SND_SOC_DAPM_INPUT("DMICDAT"),
2129 
2130 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2131 
2132 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2133 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2134 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2135 		    SND_SOC_DAPM_POST_PMU),
2136 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2137 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2138 		      WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2139 		      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2140 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2141 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2142 
2143 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2144 		   inpgal, ARRAY_SIZE(inpgal)),
2145 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2146 		   inpgar, ARRAY_SIZE(inpgar)),
2147 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2148 		   mixinl, ARRAY_SIZE(mixinl)),
2149 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2150 		   mixinr, ARRAY_SIZE(mixinr)),
2151 
2152 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2153 
2154 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2155 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2156 
2157 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2158 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2159 
2160 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2161 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2162 
2163 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2164 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2165 
2166 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2167 		   hpmixl, ARRAY_SIZE(hpmixl)),
2168 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2169 		   hpmixr, ARRAY_SIZE(hpmixr)),
2170 
2171 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2172 		   out_pga_event, SND_SOC_DAPM_POST_PMU),
2173 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2174 		   out_pga_event, SND_SOC_DAPM_POST_PMU),
2175 
2176 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2177 		   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2178 
2179 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2180 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2181 };
2182 
2183 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2184 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2185 		   spkmixl, ARRAY_SIZE(spkmixl)),
2186 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2187 		   out_pga_event, SND_SOC_DAPM_POST_PMU),
2188 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2189 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2190 };
2191 
2192 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2193 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2194 		   spkmixl, ARRAY_SIZE(spkmixl)),
2195 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2196 		   spkmixr, ARRAY_SIZE(spkmixr)),
2197 
2198 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2199 		   out_pga_event, SND_SOC_DAPM_POST_PMU),
2200 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2201 		   out_pga_event, SND_SOC_DAPM_POST_PMU),
2202 
2203 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2204 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2205 
2206 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2207 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2208 };
2209 
2210 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2211 	{ "INPGAL", "IN1L Switch", "IN1L" },
2212 	{ "INPGAL", "IN2L Switch", "IN2L" },
2213 	{ "INPGAL", "IN3L Switch", "IN3L" },
2214 	{ "INPGAL", "IN4L Switch", "IN4L" },
2215 
2216 	{ "INPGAR", "IN1R Switch", "IN1R" },
2217 	{ "INPGAR", "IN2R Switch", "IN2R" },
2218 	{ "INPGAR", "IN3R Switch", "IN3R" },
2219 	{ "INPGAR", "IN4R Switch", "IN4R" },
2220 
2221 	{ "MIXINL", "IN2L Switch", "IN2L" },
2222 	{ "MIXINL", "IN3L Switch", "IN3L" },
2223 	{ "MIXINL", "PGA Switch", "INPGAL" },
2224 
2225 	{ "MIXINR", "IN2R Switch", "IN2R" },
2226 	{ "MIXINR", "IN3R Switch", "IN3R" },
2227 	{ "MIXINR", "PGA Switch", "INPGAR" },
2228 
2229 	{ "MICBIAS", NULL, "SYSCLK" },
2230 
2231 	{ "DMIC_ENA", NULL, "DMICDAT" },
2232 
2233 	{ "ADCL", NULL, "SYSCLK" },
2234 	{ "ADCL", NULL, "TOCLK" },
2235 	{ "ADCL", NULL, "MIXINL" },
2236 	{ "ADCL", NULL, "DMIC_ENA" },
2237 	{ "ADCL", NULL, "DSP2" },
2238 
2239 	{ "ADCR", NULL, "SYSCLK" },
2240 	{ "ADCR", NULL, "TOCLK" },
2241 	{ "ADCR", NULL, "MIXINR" },
2242 	{ "ADCR", NULL, "DMIC_ENA" },
2243 	{ "ADCR", NULL, "DSP2" },
2244 
2245 	{ "STL", "Left", "ADCL" },
2246 	{ "STL", "Right", "ADCR" },
2247 	{ "STL", NULL, "Class G" },
2248 
2249 	{ "STR", "Left", "ADCL" },
2250 	{ "STR", "Right", "ADCR" },
2251 	{ "STR", NULL, "Class G" },
2252 
2253 	{ "DACL", NULL, "SYSCLK" },
2254 	{ "DACL", NULL, "TOCLK" },
2255 	{ "DACL", NULL, "Beep" },
2256 	{ "DACL", NULL, "STL" },
2257 	{ "DACL", NULL, "DSP2" },
2258 
2259 	{ "DACR", NULL, "SYSCLK" },
2260 	{ "DACR", NULL, "TOCLK" },
2261 	{ "DACR", NULL, "Beep" },
2262 	{ "DACR", NULL, "STR" },
2263 	{ "DACR", NULL, "DSP2" },
2264 
2265 	{ "HPMIXL", "IN4L Switch", "IN4L" },
2266 	{ "HPMIXL", "IN4R Switch", "IN4R" },
2267 	{ "HPMIXL", "DACL Switch", "DACL" },
2268 	{ "HPMIXL", "DACR Switch", "DACR" },
2269 	{ "HPMIXL", "MIXINL Switch", "MIXINL" },
2270 	{ "HPMIXL", "MIXINR Switch", "MIXINR" },
2271 
2272 	{ "HPMIXR", "IN4L Switch", "IN4L" },
2273 	{ "HPMIXR", "IN4R Switch", "IN4R" },
2274 	{ "HPMIXR", "DACL Switch", "DACL" },
2275 	{ "HPMIXR", "DACR Switch", "DACR" },
2276 	{ "HPMIXR", "MIXINL Switch", "MIXINL" },
2277 	{ "HPMIXR", "MIXINR Switch", "MIXINR" },
2278 
2279 	{ "Left Bypass", NULL, "HPMIXL" },
2280 	{ "Left Bypass", NULL, "Class G" },
2281 
2282 	{ "Right Bypass", NULL, "HPMIXR" },
2283 	{ "Right Bypass", NULL, "Class G" },
2284 
2285 	{ "HPOUTL PGA", "Mixer", "Left Bypass" },
2286 	{ "HPOUTL PGA", "DAC", "DACL" },
2287 
2288 	{ "HPOUTR PGA", "Mixer", "Right Bypass" },
2289 	{ "HPOUTR PGA", "DAC", "DACR" },
2290 
2291 	{ "HPOUT", NULL, "HPOUTL PGA" },
2292 	{ "HPOUT", NULL, "HPOUTR PGA" },
2293 	{ "HPOUT", NULL, "Charge Pump" },
2294 	{ "HPOUT", NULL, "SYSCLK" },
2295 	{ "HPOUT", NULL, "TOCLK" },
2296 
2297 	{ "HPOUTL", NULL, "HPOUT" },
2298 	{ "HPOUTR", NULL, "HPOUT" },
2299 
2300 	{ "HPOUTL", NULL, "TEMP_HP" },
2301 	{ "HPOUTR", NULL, "TEMP_HP" },
2302 };
2303 
2304 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2305 	{ "Speaker Mixer", "IN4L Switch", "IN4L" },
2306 	{ "Speaker Mixer", "IN4R Switch", "IN4R" },
2307 	{ "Speaker Mixer", "DACL Switch", "DACL" },
2308 	{ "Speaker Mixer", "DACR Switch", "DACR" },
2309 	{ "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2310 	{ "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2311 
2312 	{ "Speaker PGA", "Mixer", "Speaker Mixer" },
2313 	{ "Speaker PGA", "DAC", "DACL" },
2314 
2315 	{ "Speaker Output", NULL, "Speaker PGA" },
2316 	{ "Speaker Output", NULL, "SYSCLK" },
2317 	{ "Speaker Output", NULL, "TOCLK" },
2318 	{ "Speaker Output", NULL, "TEMP_SPK" },
2319 
2320 	{ "SPKOUT", NULL, "Speaker Output" },
2321 };
2322 
2323 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2324 	{ "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2325 	{ "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2326 	{ "SPKOUTL Mixer", "DACL Switch", "DACL" },
2327 	{ "SPKOUTL Mixer", "DACR Switch", "DACR" },
2328 	{ "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2329 	{ "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2330 
2331 	{ "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2332 	{ "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2333 	{ "SPKOUTR Mixer", "DACL Switch", "DACL" },
2334 	{ "SPKOUTR Mixer", "DACR Switch", "DACR" },
2335 	{ "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2336 	{ "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2337 
2338 	{ "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2339 	{ "SPKOUTL PGA", "DAC", "DACL" },
2340 
2341 	{ "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2342 	{ "SPKOUTR PGA", "DAC", "DACR" },
2343 
2344 	{ "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2345 	{ "SPKOUTL Output", NULL, "SYSCLK" },
2346 	{ "SPKOUTL Output", NULL, "TOCLK" },
2347 	{ "SPKOUTL Output", NULL, "TEMP_SPK" },
2348 
2349 	{ "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2350 	{ "SPKOUTR Output", NULL, "SYSCLK" },
2351 	{ "SPKOUTR Output", NULL, "TOCLK" },
2352 	{ "SPKOUTR Output", NULL, "TEMP_SPK" },
2353 
2354 	{ "SPKOUTL", NULL, "SPKOUTL Output" },
2355 	{ "SPKOUTR", NULL, "SPKOUTR Output" },
2356 };
2357 
2358 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2359 {
2360 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2361 	struct wm8962_pdata *pdata = &wm8962->pdata;
2362 	struct snd_soc_dapm_context *dapm = &codec->dapm;
2363 
2364 	snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2365 			     ARRAY_SIZE(wm8962_snd_controls));
2366 	if (pdata->spk_mono)
2367 		snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2368 				     ARRAY_SIZE(wm8962_spk_mono_controls));
2369 	else
2370 		snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2371 				     ARRAY_SIZE(wm8962_spk_stereo_controls));
2372 
2373 
2374 	snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2375 				  ARRAY_SIZE(wm8962_dapm_widgets));
2376 	if (pdata->spk_mono)
2377 		snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2378 					  ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2379 	else
2380 		snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2381 					  ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2382 
2383 	snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2384 				ARRAY_SIZE(wm8962_intercon));
2385 	if (pdata->spk_mono)
2386 		snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2387 					ARRAY_SIZE(wm8962_spk_mono_intercon));
2388 	else
2389 		snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2390 					ARRAY_SIZE(wm8962_spk_stereo_intercon));
2391 
2392 
2393 	snd_soc_dapm_disable_pin(dapm, "Beep");
2394 
2395 	return 0;
2396 }
2397 
2398 /* -1 for reserved values */
2399 static const int bclk_divs[] = {
2400 	1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2401 };
2402 
2403 static const int sysclk_rates[] = {
2404 	64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2405 };
2406 
2407 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2408 {
2409 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2410 	int dspclk, i;
2411 	int clocking2 = 0;
2412 	int clocking4 = 0;
2413 	int aif2 = 0;
2414 
2415 	if (!wm8962->sysclk_rate) {
2416 		dev_dbg(codec->dev, "No SYSCLK configured\n");
2417 		return;
2418 	}
2419 
2420 	if (!wm8962->bclk || !wm8962->lrclk) {
2421 		dev_dbg(codec->dev, "No audio clocks configured\n");
2422 		return;
2423 	}
2424 
2425 	for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2426 		if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2427 			clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2428 			break;
2429 		}
2430 	}
2431 
2432 	if (i == ARRAY_SIZE(sysclk_rates)) {
2433 		dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2434 			wm8962->sysclk_rate / wm8962->lrclk);
2435 		return;
2436 	}
2437 
2438 	dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2439 
2440 	snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2441 			    WM8962_SYSCLK_RATE_MASK, clocking4);
2442 
2443 	/* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2444 	 * So we here provisionally enable it and then disable it afterward
2445 	 * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2446 	 */
2447 	if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2448 		snd_soc_update_bits(codec, WM8962_CLOCKING2,
2449 				WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2450 
2451 	dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2452 
2453 	if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2454 		snd_soc_update_bits(codec, WM8962_CLOCKING2,
2455 				WM8962_SYSCLK_ENA_MASK, 0);
2456 
2457 	if (dspclk < 0) {
2458 		dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2459 		return;
2460 	}
2461 
2462 	dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2463 	switch (dspclk) {
2464 	case 0:
2465 		dspclk = wm8962->sysclk_rate;
2466 		break;
2467 	case 1:
2468 		dspclk = wm8962->sysclk_rate / 2;
2469 		break;
2470 	case 2:
2471 		dspclk = wm8962->sysclk_rate / 4;
2472 		break;
2473 	default:
2474 		dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2475 		dspclk = wm8962->sysclk;
2476 	}
2477 
2478 	dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2479 
2480 	/* We're expecting an exact match */
2481 	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2482 		if (bclk_divs[i] < 0)
2483 			continue;
2484 
2485 		if (dspclk / bclk_divs[i] == wm8962->bclk) {
2486 			dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2487 				bclk_divs[i], wm8962->bclk);
2488 			clocking2 |= i;
2489 			break;
2490 		}
2491 	}
2492 	if (i == ARRAY_SIZE(bclk_divs)) {
2493 		dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2494 			dspclk / wm8962->bclk);
2495 		return;
2496 	}
2497 
2498 	aif2 |= wm8962->bclk / wm8962->lrclk;
2499 	dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2500 		wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2501 
2502 	snd_soc_update_bits(codec, WM8962_CLOCKING2,
2503 			    WM8962_BCLK_DIV_MASK, clocking2);
2504 	snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2505 			    WM8962_AIF_RATE_MASK, aif2);
2506 }
2507 
2508 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2509 				 enum snd_soc_bias_level level)
2510 {
2511 	if (level == codec->dapm.bias_level)
2512 		return 0;
2513 
2514 	switch (level) {
2515 	case SND_SOC_BIAS_ON:
2516 		break;
2517 
2518 	case SND_SOC_BIAS_PREPARE:
2519 		/* VMID 2*50k */
2520 		snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2521 				    WM8962_VMID_SEL_MASK, 0x80);
2522 
2523 		wm8962_configure_bclk(codec);
2524 		break;
2525 
2526 	case SND_SOC_BIAS_STANDBY:
2527 		/* VMID 2*250k */
2528 		snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2529 				    WM8962_VMID_SEL_MASK, 0x100);
2530 
2531 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2532 			msleep(100);
2533 		break;
2534 
2535 	case SND_SOC_BIAS_OFF:
2536 		break;
2537 	}
2538 
2539 	codec->dapm.bias_level = level;
2540 	return 0;
2541 }
2542 
2543 static const struct {
2544 	int rate;
2545 	int reg;
2546 } sr_vals[] = {
2547 	{ 48000, 0 },
2548 	{ 44100, 0 },
2549 	{ 32000, 1 },
2550 	{ 22050, 2 },
2551 	{ 24000, 2 },
2552 	{ 16000, 3 },
2553 	{ 11025, 4 },
2554 	{ 12000, 4 },
2555 	{ 8000,  5 },
2556 	{ 88200, 6 },
2557 	{ 96000, 6 },
2558 };
2559 
2560 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2561 			    struct snd_pcm_hw_params *params,
2562 			    struct snd_soc_dai *dai)
2563 {
2564 	struct snd_soc_codec *codec = dai->codec;
2565 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2566 	int i;
2567 	int aif0 = 0;
2568 	int adctl3 = 0;
2569 
2570 	wm8962->bclk = snd_soc_params_to_bclk(params);
2571 	if (params_channels(params) == 1)
2572 		wm8962->bclk *= 2;
2573 
2574 	wm8962->lrclk = params_rate(params);
2575 
2576 	for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2577 		if (sr_vals[i].rate == wm8962->lrclk) {
2578 			adctl3 |= sr_vals[i].reg;
2579 			break;
2580 		}
2581 	}
2582 	if (i == ARRAY_SIZE(sr_vals)) {
2583 		dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2584 		return -EINVAL;
2585 	}
2586 
2587 	if (wm8962->lrclk % 8000 == 0)
2588 		adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2589 
2590 	switch (params_width(params)) {
2591 	case 16:
2592 		break;
2593 	case 20:
2594 		aif0 |= 0x4;
2595 		break;
2596 	case 24:
2597 		aif0 |= 0x8;
2598 		break;
2599 	case 32:
2600 		aif0 |= 0xc;
2601 		break;
2602 	default:
2603 		return -EINVAL;
2604 	}
2605 
2606 	snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2607 			    WM8962_WL_MASK, aif0);
2608 	snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2609 			    WM8962_SAMPLE_RATE_INT_MODE |
2610 			    WM8962_SAMPLE_RATE_MASK, adctl3);
2611 
2612 	dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2613 		wm8962->bclk, wm8962->lrclk);
2614 
2615 	if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2616 		wm8962_configure_bclk(codec);
2617 
2618 	return 0;
2619 }
2620 
2621 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2622 				 unsigned int freq, int dir)
2623 {
2624 	struct snd_soc_codec *codec = dai->codec;
2625 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2626 	int src;
2627 
2628 	switch (clk_id) {
2629 	case WM8962_SYSCLK_MCLK:
2630 		wm8962->sysclk = WM8962_SYSCLK_MCLK;
2631 		src = 0;
2632 		break;
2633 	case WM8962_SYSCLK_FLL:
2634 		wm8962->sysclk = WM8962_SYSCLK_FLL;
2635 		src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2636 		break;
2637 	default:
2638 		return -EINVAL;
2639 	}
2640 
2641 	snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2642 			    src);
2643 
2644 	wm8962->sysclk_rate = freq;
2645 
2646 	return 0;
2647 }
2648 
2649 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2650 {
2651 	struct snd_soc_codec *codec = dai->codec;
2652 	int aif0 = 0;
2653 
2654 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2655 	case SND_SOC_DAIFMT_DSP_B:
2656 		aif0 |= WM8962_LRCLK_INV | 3;
2657 	case SND_SOC_DAIFMT_DSP_A:
2658 		aif0 |= 3;
2659 
2660 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2661 		case SND_SOC_DAIFMT_NB_NF:
2662 		case SND_SOC_DAIFMT_IB_NF:
2663 			break;
2664 		default:
2665 			return -EINVAL;
2666 		}
2667 		break;
2668 
2669 	case SND_SOC_DAIFMT_RIGHT_J:
2670 		break;
2671 	case SND_SOC_DAIFMT_LEFT_J:
2672 		aif0 |= 1;
2673 		break;
2674 	case SND_SOC_DAIFMT_I2S:
2675 		aif0 |= 2;
2676 		break;
2677 	default:
2678 		return -EINVAL;
2679 	}
2680 
2681 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2682 	case SND_SOC_DAIFMT_NB_NF:
2683 		break;
2684 	case SND_SOC_DAIFMT_IB_NF:
2685 		aif0 |= WM8962_BCLK_INV;
2686 		break;
2687 	case SND_SOC_DAIFMT_NB_IF:
2688 		aif0 |= WM8962_LRCLK_INV;
2689 		break;
2690 	case SND_SOC_DAIFMT_IB_IF:
2691 		aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2692 		break;
2693 	default:
2694 		return -EINVAL;
2695 	}
2696 
2697 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2698 	case SND_SOC_DAIFMT_CBM_CFM:
2699 		aif0 |= WM8962_MSTR;
2700 		break;
2701 	case SND_SOC_DAIFMT_CBS_CFS:
2702 		break;
2703 	default:
2704 		return -EINVAL;
2705 	}
2706 
2707 	snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2708 			    WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2709 			    WM8962_LRCLK_INV, aif0);
2710 
2711 	return 0;
2712 }
2713 
2714 struct _fll_div {
2715 	u16 fll_fratio;
2716 	u16 fll_outdiv;
2717 	u16 fll_refclk_div;
2718 	u16 n;
2719 	u16 theta;
2720 	u16 lambda;
2721 };
2722 
2723 /* The size in bits of the FLL divide multiplied by 10
2724  * to allow rounding later */
2725 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2726 
2727 static struct {
2728 	unsigned int min;
2729 	unsigned int max;
2730 	u16 fll_fratio;
2731 	int ratio;
2732 } fll_fratios[] = {
2733 	{       0,    64000, 4, 16 },
2734 	{   64000,   128000, 3,  8 },
2735 	{  128000,   256000, 2,  4 },
2736 	{  256000,  1000000, 1,  2 },
2737 	{ 1000000, 13500000, 0,  1 },
2738 };
2739 
2740 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2741 		       unsigned int Fout)
2742 {
2743 	unsigned int target;
2744 	unsigned int div;
2745 	unsigned int fratio, gcd_fll;
2746 	int i;
2747 
2748 	/* Fref must be <=13.5MHz */
2749 	div = 1;
2750 	fll_div->fll_refclk_div = 0;
2751 	while ((Fref / div) > 13500000) {
2752 		div *= 2;
2753 		fll_div->fll_refclk_div++;
2754 
2755 		if (div > 4) {
2756 			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2757 			       Fref);
2758 			return -EINVAL;
2759 		}
2760 	}
2761 
2762 	pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2763 
2764 	/* Apply the division for our remaining calculations */
2765 	Fref /= div;
2766 
2767 	/* Fvco should be 90-100MHz; don't check the upper bound */
2768 	div = 2;
2769 	while (Fout * div < 90000000) {
2770 		div++;
2771 		if (div > 64) {
2772 			pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2773 			       Fout);
2774 			return -EINVAL;
2775 		}
2776 	}
2777 	target = Fout * div;
2778 	fll_div->fll_outdiv = div - 1;
2779 
2780 	pr_debug("FLL Fvco=%dHz\n", target);
2781 
2782 	/* Find an appropriate FLL_FRATIO and factor it out of the target */
2783 	for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2784 		if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2785 			fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2786 			fratio = fll_fratios[i].ratio;
2787 			break;
2788 		}
2789 	}
2790 	if (i == ARRAY_SIZE(fll_fratios)) {
2791 		pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2792 		return -EINVAL;
2793 	}
2794 
2795 	fll_div->n = target / (fratio * Fref);
2796 
2797 	if (target % Fref == 0) {
2798 		fll_div->theta = 0;
2799 		fll_div->lambda = 0;
2800 	} else {
2801 		gcd_fll = gcd(target, fratio * Fref);
2802 
2803 		fll_div->theta = (target - (fll_div->n * fratio * Fref))
2804 			/ gcd_fll;
2805 		fll_div->lambda = (fratio * Fref) / gcd_fll;
2806 	}
2807 
2808 	pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2809 		 fll_div->n, fll_div->theta, fll_div->lambda);
2810 	pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2811 		 fll_div->fll_fratio, fll_div->fll_outdiv,
2812 		 fll_div->fll_refclk_div);
2813 
2814 	return 0;
2815 }
2816 
2817 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2818 			  unsigned int Fref, unsigned int Fout)
2819 {
2820 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2821 	struct _fll_div fll_div;
2822 	unsigned long timeout;
2823 	int ret;
2824 	int fll1 = 0;
2825 
2826 	/* Any change? */
2827 	if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2828 	    Fout == wm8962->fll_fout)
2829 		return 0;
2830 
2831 	if (Fout == 0) {
2832 		dev_dbg(codec->dev, "FLL disabled\n");
2833 
2834 		wm8962->fll_fref = 0;
2835 		wm8962->fll_fout = 0;
2836 
2837 		snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2838 				    WM8962_FLL_ENA, 0);
2839 
2840 		pm_runtime_put(codec->dev);
2841 
2842 		return 0;
2843 	}
2844 
2845 	ret = fll_factors(&fll_div, Fref, Fout);
2846 	if (ret != 0)
2847 		return ret;
2848 
2849 	/* Parameters good, disable so we can reprogram */
2850 	snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2851 
2852 	switch (fll_id) {
2853 	case WM8962_FLL_MCLK:
2854 	case WM8962_FLL_BCLK:
2855 	case WM8962_FLL_OSC:
2856 		fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2857 		break;
2858 	case WM8962_FLL_INT:
2859 		snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2860 				    WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2861 		snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2862 				    WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2863 		break;
2864 	default:
2865 		dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2866 		return -EINVAL;
2867 	}
2868 
2869 	if (fll_div.theta || fll_div.lambda)
2870 		fll1 |= WM8962_FLL_FRAC;
2871 
2872 	/* Stop the FLL while we reconfigure */
2873 	snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2874 
2875 	snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2876 			    WM8962_FLL_OUTDIV_MASK |
2877 			    WM8962_FLL_REFCLK_DIV_MASK,
2878 			    (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2879 			    (fll_div.fll_refclk_div));
2880 
2881 	snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2882 			    WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2883 
2884 	snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2885 	snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2886 	snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2887 
2888 	reinit_completion(&wm8962->fll_lock);
2889 
2890 	ret = pm_runtime_get_sync(codec->dev);
2891 	if (ret < 0) {
2892 		dev_err(codec->dev, "Failed to resume device: %d\n", ret);
2893 		return ret;
2894 	}
2895 
2896 	snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2897 			    WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2898 			    WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2899 
2900 	dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2901 
2902 	/* This should be a massive overestimate but go even
2903 	 * higher if we'll error out
2904 	 */
2905 	if (wm8962->irq)
2906 		timeout = msecs_to_jiffies(5);
2907 	else
2908 		timeout = msecs_to_jiffies(1);
2909 
2910 	timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2911 					      timeout);
2912 
2913 	if (timeout == 0 && wm8962->irq) {
2914 		dev_err(codec->dev, "FLL lock timed out");
2915 		snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2916 				    WM8962_FLL_ENA, 0);
2917 		pm_runtime_put(codec->dev);
2918 		return -ETIMEDOUT;
2919 	}
2920 
2921 	wm8962->fll_fref = Fref;
2922 	wm8962->fll_fout = Fout;
2923 	wm8962->fll_src = source;
2924 
2925 	return 0;
2926 }
2927 
2928 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2929 {
2930 	struct snd_soc_codec *codec = dai->codec;
2931 	int val, ret;
2932 
2933 	if (mute)
2934 		val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2935 	else
2936 		val = 0;
2937 
2938 	/**
2939 	 * The DAC mute bit is mirrored in two registers, update both to keep
2940 	 * the register cache consistent.
2941 	 */
2942 	ret = snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_1,
2943 				  WM8962_DAC_MUTE_ALT, val);
2944 	if (ret < 0)
2945 		return ret;
2946 
2947 	return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2948 				   WM8962_DAC_MUTE, val);
2949 }
2950 
2951 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2952 
2953 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2954 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2955 
2956 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2957 	.hw_params = wm8962_hw_params,
2958 	.set_sysclk = wm8962_set_dai_sysclk,
2959 	.set_fmt = wm8962_set_dai_fmt,
2960 	.digital_mute = wm8962_mute,
2961 };
2962 
2963 static struct snd_soc_dai_driver wm8962_dai = {
2964 	.name = "wm8962",
2965 	.playback = {
2966 		.stream_name = "Playback",
2967 		.channels_min = 1,
2968 		.channels_max = 2,
2969 		.rates = WM8962_RATES,
2970 		.formats = WM8962_FORMATS,
2971 	},
2972 	.capture = {
2973 		.stream_name = "Capture",
2974 		.channels_min = 1,
2975 		.channels_max = 2,
2976 		.rates = WM8962_RATES,
2977 		.formats = WM8962_FORMATS,
2978 	},
2979 	.ops = &wm8962_dai_ops,
2980 	.symmetric_rates = 1,
2981 };
2982 
2983 static void wm8962_mic_work(struct work_struct *work)
2984 {
2985 	struct wm8962_priv *wm8962 = container_of(work,
2986 						  struct wm8962_priv,
2987 						  mic_work.work);
2988 	struct snd_soc_codec *codec = wm8962->codec;
2989 	int status = 0;
2990 	int irq_pol = 0;
2991 	int reg;
2992 
2993 	reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2994 
2995 	if (reg & WM8962_MICDET_STS) {
2996 		status |= SND_JACK_MICROPHONE;
2997 		irq_pol |= WM8962_MICD_IRQ_POL;
2998 	}
2999 
3000 	if (reg & WM8962_MICSHORT_STS) {
3001 		status |= SND_JACK_BTN_0;
3002 		irq_pol |= WM8962_MICSCD_IRQ_POL;
3003 	}
3004 
3005 	snd_soc_jack_report(wm8962->jack, status,
3006 			    SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3007 
3008 	snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
3009 			    WM8962_MICSCD_IRQ_POL |
3010 			    WM8962_MICD_IRQ_POL, irq_pol);
3011 }
3012 
3013 static irqreturn_t wm8962_irq(int irq, void *data)
3014 {
3015 	struct device *dev = data;
3016 	struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3017 	unsigned int mask;
3018 	unsigned int active;
3019 	int reg, ret;
3020 
3021 	ret = pm_runtime_get_sync(dev);
3022 	if (ret < 0) {
3023 		dev_err(dev, "Failed to resume: %d\n", ret);
3024 		return IRQ_NONE;
3025 	}
3026 
3027 	ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3028 			  &mask);
3029 	if (ret != 0) {
3030 		pm_runtime_put(dev);
3031 		dev_err(dev, "Failed to read interrupt mask: %d\n",
3032 			ret);
3033 		return IRQ_NONE;
3034 	}
3035 
3036 	ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3037 	if (ret != 0) {
3038 		pm_runtime_put(dev);
3039 		dev_err(dev, "Failed to read interrupt: %d\n", ret);
3040 		return IRQ_NONE;
3041 	}
3042 
3043 	active &= ~mask;
3044 
3045 	if (!active) {
3046 		pm_runtime_put(dev);
3047 		return IRQ_NONE;
3048 	}
3049 
3050 	/* Acknowledge the interrupts */
3051 	ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3052 	if (ret != 0)
3053 		dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3054 
3055 	if (active & WM8962_FLL_LOCK_EINT) {
3056 		dev_dbg(dev, "FLL locked\n");
3057 		complete(&wm8962->fll_lock);
3058 	}
3059 
3060 	if (active & WM8962_FIFOS_ERR_EINT)
3061 		dev_err(dev, "FIFO error\n");
3062 
3063 	if (active & WM8962_TEMP_SHUT_EINT) {
3064 		dev_crit(dev, "Thermal shutdown\n");
3065 
3066 		ret = regmap_read(wm8962->regmap,
3067 				  WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3068 		if (ret != 0) {
3069 			dev_warn(dev, "Failed to read thermal status: %d\n",
3070 				 ret);
3071 			reg = 0;
3072 		}
3073 
3074 		if (reg & WM8962_TEMP_ERR_HP)
3075 			dev_crit(dev, "Headphone thermal error\n");
3076 		if (reg & WM8962_TEMP_WARN_HP)
3077 			dev_crit(dev, "Headphone thermal warning\n");
3078 		if (reg & WM8962_TEMP_ERR_SPK)
3079 			dev_crit(dev, "Speaker thermal error\n");
3080 		if (reg & WM8962_TEMP_WARN_SPK)
3081 			dev_crit(dev, "Speaker thermal warning\n");
3082 	}
3083 
3084 	if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3085 		dev_dbg(dev, "Microphone event detected\n");
3086 
3087 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3088 		trace_snd_soc_jack_irq(dev_name(dev));
3089 #endif
3090 
3091 		pm_wakeup_event(dev, 300);
3092 
3093 		queue_delayed_work(system_power_efficient_wq,
3094 				   &wm8962->mic_work,
3095 				   msecs_to_jiffies(250));
3096 	}
3097 
3098 	pm_runtime_put(dev);
3099 
3100 	return IRQ_HANDLED;
3101 }
3102 
3103 /**
3104  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3105  *
3106  * @codec:  WM8962 codec
3107  * @jack:   jack to report detection events on
3108  *
3109  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3110  * being used to bring out signals to the processor then only platform
3111  * data configuration is needed for WM8962 and processor GPIOs should
3112  * be configured using snd_soc_jack_add_gpios() instead.
3113  *
3114  * If no jack is supplied detection will be disabled.
3115  */
3116 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3117 {
3118 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3119 	struct snd_soc_dapm_context *dapm = &codec->dapm;
3120 	int irq_mask, enable;
3121 
3122 	wm8962->jack = jack;
3123 	if (jack) {
3124 		irq_mask = 0;
3125 		enable = WM8962_MICDET_ENA;
3126 	} else {
3127 		irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3128 		enable = 0;
3129 	}
3130 
3131 	snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3132 			    WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3133 	snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3134 			    WM8962_MICDET_ENA, enable);
3135 
3136 	/* Send an initial empty report */
3137 	snd_soc_jack_report(wm8962->jack, 0,
3138 			    SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3139 
3140 	snd_soc_dapm_mutex_lock(dapm);
3141 
3142 	if (jack) {
3143 		snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3144 		snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3145 	} else {
3146 		snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3147 		snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3148 	}
3149 
3150 	snd_soc_dapm_mutex_unlock(dapm);
3151 
3152 	return 0;
3153 }
3154 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3155 
3156 static int beep_rates[] = {
3157 	500, 1000, 2000, 4000,
3158 };
3159 
3160 static void wm8962_beep_work(struct work_struct *work)
3161 {
3162 	struct wm8962_priv *wm8962 =
3163 		container_of(work, struct wm8962_priv, beep_work);
3164 	struct snd_soc_codec *codec = wm8962->codec;
3165 	struct snd_soc_dapm_context *dapm = &codec->dapm;
3166 	int i;
3167 	int reg = 0;
3168 	int best = 0;
3169 
3170 	if (wm8962->beep_rate) {
3171 		for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3172 			if (abs(wm8962->beep_rate - beep_rates[i]) <
3173 			    abs(wm8962->beep_rate - beep_rates[best]))
3174 				best = i;
3175 		}
3176 
3177 		dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3178 			beep_rates[best], wm8962->beep_rate);
3179 
3180 		reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3181 
3182 		snd_soc_dapm_enable_pin(dapm, "Beep");
3183 	} else {
3184 		dev_dbg(codec->dev, "Disabling beep\n");
3185 		snd_soc_dapm_disable_pin(dapm, "Beep");
3186 	}
3187 
3188 	snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3189 			    WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3190 
3191 	snd_soc_dapm_sync(dapm);
3192 }
3193 
3194 /* For usability define a way of injecting beep events for the device -
3195  * many systems will not have a keyboard.
3196  */
3197 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3198 			     unsigned int code, int hz)
3199 {
3200 	struct snd_soc_codec *codec = input_get_drvdata(dev);
3201 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3202 
3203 	dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3204 
3205 	switch (code) {
3206 	case SND_BELL:
3207 		if (hz)
3208 			hz = 1000;
3209 	case SND_TONE:
3210 		break;
3211 	default:
3212 		return -1;
3213 	}
3214 
3215 	/* Kick the beep from a workqueue */
3216 	wm8962->beep_rate = hz;
3217 	schedule_work(&wm8962->beep_work);
3218 	return 0;
3219 }
3220 
3221 static ssize_t wm8962_beep_set(struct device *dev,
3222 			       struct device_attribute *attr,
3223 			       const char *buf, size_t count)
3224 {
3225 	struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3226 	long int time;
3227 	int ret;
3228 
3229 	ret = kstrtol(buf, 10, &time);
3230 	if (ret != 0)
3231 		return ret;
3232 
3233 	input_event(wm8962->beep, EV_SND, SND_TONE, time);
3234 
3235 	return count;
3236 }
3237 
3238 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3239 
3240 static void wm8962_init_beep(struct snd_soc_codec *codec)
3241 {
3242 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3243 	int ret;
3244 
3245 	wm8962->beep = devm_input_allocate_device(codec->dev);
3246 	if (!wm8962->beep) {
3247 		dev_err(codec->dev, "Failed to allocate beep device\n");
3248 		return;
3249 	}
3250 
3251 	INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3252 	wm8962->beep_rate = 0;
3253 
3254 	wm8962->beep->name = "WM8962 Beep Generator";
3255 	wm8962->beep->phys = dev_name(codec->dev);
3256 	wm8962->beep->id.bustype = BUS_I2C;
3257 
3258 	wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3259 	wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3260 	wm8962->beep->event = wm8962_beep_event;
3261 	wm8962->beep->dev.parent = codec->dev;
3262 	input_set_drvdata(wm8962->beep, codec);
3263 
3264 	ret = input_register_device(wm8962->beep);
3265 	if (ret != 0) {
3266 		wm8962->beep = NULL;
3267 		dev_err(codec->dev, "Failed to register beep device\n");
3268 	}
3269 
3270 	ret = device_create_file(codec->dev, &dev_attr_beep);
3271 	if (ret != 0) {
3272 		dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3273 			ret);
3274 	}
3275 }
3276 
3277 static void wm8962_free_beep(struct snd_soc_codec *codec)
3278 {
3279 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3280 
3281 	device_remove_file(codec->dev, &dev_attr_beep);
3282 	cancel_work_sync(&wm8962->beep_work);
3283 	wm8962->beep = NULL;
3284 
3285 	snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3286 }
3287 
3288 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3289 {
3290 	int mask = 0;
3291 	int val = 0;
3292 
3293 	/* Some of the GPIOs are behind MFP configuration and need to
3294 	 * be put into GPIO mode. */
3295 	switch (gpio) {
3296 	case 2:
3297 		mask = WM8962_CLKOUT2_SEL_MASK;
3298 		val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3299 		break;
3300 	case 3:
3301 		mask = WM8962_CLKOUT3_SEL_MASK;
3302 		val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3303 		break;
3304 	default:
3305 		break;
3306 	}
3307 
3308 	if (mask)
3309 		regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3310 				   mask, val);
3311 }
3312 
3313 #ifdef CONFIG_GPIOLIB
3314 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3315 {
3316 	return container_of(chip, struct wm8962_priv, gpio_chip);
3317 }
3318 
3319 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3320 {
3321 	struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3322 
3323 	/* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3324 	 * we export linear numbers and error out if the unsupported
3325 	 * ones are requsted.
3326 	 */
3327 	switch (offset + 1) {
3328 	case 2:
3329 	case 3:
3330 	case 5:
3331 	case 6:
3332 		break;
3333 	default:
3334 		return -EINVAL;
3335 	}
3336 
3337 	wm8962_set_gpio_mode(wm8962, offset + 1);
3338 
3339 	return 0;
3340 }
3341 
3342 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3343 {
3344 	struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3345 	struct snd_soc_codec *codec = wm8962->codec;
3346 
3347 	snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3348 			    WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3349 }
3350 
3351 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3352 				     unsigned offset, int value)
3353 {
3354 	struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3355 	struct snd_soc_codec *codec = wm8962->codec;
3356 	int ret, val;
3357 
3358 	/* Force function 1 (logic output) */
3359 	val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3360 
3361 	ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3362 				  WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3363 	if (ret < 0)
3364 		return ret;
3365 
3366 	return 0;
3367 }
3368 
3369 static struct gpio_chip wm8962_template_chip = {
3370 	.label			= "wm8962",
3371 	.owner			= THIS_MODULE,
3372 	.request		= wm8962_gpio_request,
3373 	.direction_output	= wm8962_gpio_direction_out,
3374 	.set			= wm8962_gpio_set,
3375 	.can_sleep		= 1,
3376 };
3377 
3378 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3379 {
3380 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3381 	struct wm8962_pdata *pdata = &wm8962->pdata;
3382 	int ret;
3383 
3384 	wm8962->gpio_chip = wm8962_template_chip;
3385 	wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3386 	wm8962->gpio_chip.dev = codec->dev;
3387 
3388 	if (pdata->gpio_base)
3389 		wm8962->gpio_chip.base = pdata->gpio_base;
3390 	else
3391 		wm8962->gpio_chip.base = -1;
3392 
3393 	ret = gpiochip_add(&wm8962->gpio_chip);
3394 	if (ret != 0)
3395 		dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3396 }
3397 
3398 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3399 {
3400 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3401 
3402 	gpiochip_remove(&wm8962->gpio_chip);
3403 }
3404 #else
3405 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3406 {
3407 }
3408 
3409 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3410 {
3411 }
3412 #endif
3413 
3414 static int wm8962_probe(struct snd_soc_codec *codec)
3415 {
3416 	int ret;
3417 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3418 	int i;
3419 	bool dmicclk, dmicdat;
3420 
3421 	wm8962->codec = codec;
3422 
3423 	wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3424 	wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3425 	wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3426 	wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3427 	wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3428 	wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3429 	wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3430 	wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3431 
3432 	/* This should really be moved into the regulator core */
3433 	for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3434 		ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3435 						  &wm8962->disable_nb[i]);
3436 		if (ret != 0) {
3437 			dev_err(codec->dev,
3438 				"Failed to register regulator notifier: %d\n",
3439 				ret);
3440 		}
3441 	}
3442 
3443 	wm8962_add_widgets(codec);
3444 
3445 	/* Save boards having to disable DMIC when not in use */
3446 	dmicclk = false;
3447 	dmicdat = false;
3448 	for (i = 0; i < WM8962_MAX_GPIO; i++) {
3449 		switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3450 			& WM8962_GP2_FN_MASK) {
3451 		case WM8962_GPIO_FN_DMICCLK:
3452 			dmicclk = true;
3453 			break;
3454 		case WM8962_GPIO_FN_DMICDAT:
3455 			dmicdat = true;
3456 			break;
3457 		default:
3458 			break;
3459 		}
3460 	}
3461 	if (!dmicclk || !dmicdat) {
3462 		dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3463 		snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3464 	}
3465 	if (dmicclk != dmicdat)
3466 		dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3467 
3468 	wm8962_init_beep(codec);
3469 	wm8962_init_gpio(codec);
3470 
3471 	return 0;
3472 }
3473 
3474 static int wm8962_remove(struct snd_soc_codec *codec)
3475 {
3476 	struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3477 	int i;
3478 
3479 	cancel_delayed_work_sync(&wm8962->mic_work);
3480 
3481 	wm8962_free_gpio(codec);
3482 	wm8962_free_beep(codec);
3483 	for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3484 		regulator_unregister_notifier(wm8962->supplies[i].consumer,
3485 					      &wm8962->disable_nb[i]);
3486 
3487 	return 0;
3488 }
3489 
3490 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3491 	.probe =	wm8962_probe,
3492 	.remove =	wm8962_remove,
3493 	.set_bias_level = wm8962_set_bias_level,
3494 	.set_pll = wm8962_set_fll,
3495 	.idle_bias_off = true,
3496 };
3497 
3498 /* Improve power consumption for IN4 DC measurement mode */
3499 static const struct reg_default wm8962_dc_measure[] = {
3500 	{ 0xfd, 0x1 },
3501 	{ 0xcc, 0x40 },
3502 	{ 0xfd, 0 },
3503 };
3504 
3505 static const struct regmap_config wm8962_regmap = {
3506 	.reg_bits = 16,
3507 	.val_bits = 16,
3508 
3509 	.max_register = WM8962_MAX_REGISTER,
3510 	.reg_defaults = wm8962_reg,
3511 	.num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3512 	.volatile_reg = wm8962_volatile_register,
3513 	.readable_reg = wm8962_readable_register,
3514 	.cache_type = REGCACHE_RBTREE,
3515 };
3516 
3517 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3518 				    struct wm8962_pdata *pdata)
3519 {
3520 	const struct device_node *np = i2c->dev.of_node;
3521 	u32 val32;
3522 	int i;
3523 
3524 	if (of_property_read_bool(np, "spk-mono"))
3525 		pdata->spk_mono = true;
3526 
3527 	if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3528 		pdata->mic_cfg = val32;
3529 
3530 	if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3531 				       ARRAY_SIZE(pdata->gpio_init)) >= 0)
3532 		for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3533 			/*
3534 			 * The range of GPIO register value is [0x0, 0xffff]
3535 			 * While the default value of each register is 0x0
3536 			 * Any other value will be regarded as default value
3537 			 */
3538 			if (pdata->gpio_init[i] > 0xffff)
3539 				pdata->gpio_init[i] = 0x0;
3540 		}
3541 
3542 	pdata->mclk = devm_clk_get(&i2c->dev, NULL);
3543 
3544 	return 0;
3545 }
3546 
3547 static int wm8962_i2c_probe(struct i2c_client *i2c,
3548 			    const struct i2c_device_id *id)
3549 {
3550 	struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3551 	struct wm8962_priv *wm8962;
3552 	unsigned int reg;
3553 	int ret, i, irq_pol, trigger;
3554 
3555 	wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3556 			      GFP_KERNEL);
3557 	if (wm8962 == NULL)
3558 		return -ENOMEM;
3559 
3560 	i2c_set_clientdata(i2c, wm8962);
3561 
3562 	INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3563 	init_completion(&wm8962->fll_lock);
3564 	wm8962->irq = i2c->irq;
3565 
3566 	/* If platform data was supplied, update the default data in priv */
3567 	if (pdata) {
3568 		memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3569 	} else if (i2c->dev.of_node) {
3570 		ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3571 		if (ret != 0)
3572 			return ret;
3573 	}
3574 
3575 	/* Mark the mclk pointer to NULL if no mclk assigned */
3576 	if (IS_ERR(wm8962->pdata.mclk)) {
3577 		/* But do not ignore the request for probe defer */
3578 		if (PTR_ERR(wm8962->pdata.mclk) == -EPROBE_DEFER)
3579 			return -EPROBE_DEFER;
3580 		wm8962->pdata.mclk = NULL;
3581 	}
3582 
3583 	for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3584 		wm8962->supplies[i].supply = wm8962_supply_names[i];
3585 
3586 	ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3587 				 wm8962->supplies);
3588 	if (ret != 0) {
3589 		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3590 		goto err;
3591 	}
3592 
3593 	ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3594 				    wm8962->supplies);
3595 	if (ret != 0) {
3596 		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3597 		return ret;
3598 	}
3599 
3600 	wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3601 	if (IS_ERR(wm8962->regmap)) {
3602 		ret = PTR_ERR(wm8962->regmap);
3603 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3604 		goto err_enable;
3605 	}
3606 
3607 	/*
3608 	 * We haven't marked the chip revision as volatile due to
3609 	 * sharing a register with the right input volume; explicitly
3610 	 * bypass the cache to read it.
3611 	 */
3612 	regcache_cache_bypass(wm8962->regmap, true);
3613 
3614 	ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3615 	if (ret < 0) {
3616 		dev_err(&i2c->dev, "Failed to read ID register\n");
3617 		goto err_enable;
3618 	}
3619 	if (reg != 0x6243) {
3620 		dev_err(&i2c->dev,
3621 			"Device is not a WM8962, ID %x != 0x6243\n", reg);
3622 		ret = -EINVAL;
3623 		goto err_enable;
3624 	}
3625 
3626 	ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3627 	if (ret < 0) {
3628 		dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3629 			ret);
3630 		goto err_enable;
3631 	}
3632 
3633 	dev_info(&i2c->dev, "customer id %x revision %c\n",
3634 		 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3635 		 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3636 		 + 'A');
3637 
3638 	regcache_cache_bypass(wm8962->regmap, false);
3639 
3640 	ret = wm8962_reset(wm8962);
3641 	if (ret < 0) {
3642 		dev_err(&i2c->dev, "Failed to issue reset\n");
3643 		goto err_enable;
3644 	}
3645 
3646 	/* SYSCLK defaults to on; make sure it is off so we can safely
3647 	 * write to registers if the device is declocked.
3648 	 */
3649 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3650 			   WM8962_SYSCLK_ENA, 0);
3651 
3652 	/* Ensure we have soft control over all registers */
3653 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3654 			   WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3655 
3656 	/* Ensure that the oscillator and PLLs are disabled */
3657 	regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3658 			   WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3659 			   0);
3660 
3661 	/* Apply static configuration for GPIOs */
3662 	for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3663 		if (wm8962->pdata.gpio_init[i]) {
3664 			wm8962_set_gpio_mode(wm8962, i + 1);
3665 			regmap_write(wm8962->regmap, 0x200 + i,
3666 				     wm8962->pdata.gpio_init[i] & 0xffff);
3667 		}
3668 
3669 
3670 	/* Put the speakers into mono mode? */
3671 	if (wm8962->pdata.spk_mono)
3672 		regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3673 				   WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3674 
3675 	/* Micbias setup, detection enable and detection
3676 	 * threasholds. */
3677 	if (wm8962->pdata.mic_cfg)
3678 		regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3679 				   WM8962_MICDET_ENA |
3680 				   WM8962_MICDET_THR_MASK |
3681 				   WM8962_MICSHORT_THR_MASK |
3682 				   WM8962_MICBIAS_LVL,
3683 				   wm8962->pdata.mic_cfg);
3684 
3685 	/* Latch volume update bits */
3686 	regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3687 			   WM8962_IN_VU, WM8962_IN_VU);
3688 	regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3689 			   WM8962_IN_VU, WM8962_IN_VU);
3690 	regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3691 			   WM8962_ADC_VU, WM8962_ADC_VU);
3692 	regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3693 			   WM8962_ADC_VU, WM8962_ADC_VU);
3694 	regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3695 			   WM8962_DAC_VU, WM8962_DAC_VU);
3696 	regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3697 			   WM8962_DAC_VU, WM8962_DAC_VU);
3698 	regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3699 			   WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3700 	regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3701 			   WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3702 	regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3703 			   WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3704 	regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3705 			   WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3706 
3707 	/* Stereo control for EQ */
3708 	regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3709 			   WM8962_EQ_SHARED_COEFF, 0);
3710 
3711 	/* Don't debouce interrupts so we don't need SYSCLK */
3712 	regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3713 			   WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3714 			   WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3715 			   0);
3716 
3717 	if (wm8962->pdata.in4_dc_measure) {
3718 		ret = regmap_register_patch(wm8962->regmap,
3719 					    wm8962_dc_measure,
3720 					    ARRAY_SIZE(wm8962_dc_measure));
3721 		if (ret != 0)
3722 			dev_err(&i2c->dev,
3723 				"Failed to configure for DC mesurement: %d\n",
3724 				ret);
3725 	}
3726 
3727 	if (wm8962->irq) {
3728 		if (wm8962->pdata.irq_active_low) {
3729 			trigger = IRQF_TRIGGER_LOW;
3730 			irq_pol = WM8962_IRQ_POL;
3731 		} else {
3732 			trigger = IRQF_TRIGGER_HIGH;
3733 			irq_pol = 0;
3734 		}
3735 
3736 		regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3737 				   WM8962_IRQ_POL, irq_pol);
3738 
3739 		ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3740 						wm8962_irq,
3741 						trigger | IRQF_ONESHOT,
3742 						"wm8962", &i2c->dev);
3743 		if (ret != 0) {
3744 			dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3745 				wm8962->irq, ret);
3746 			wm8962->irq = 0;
3747 			/* Non-fatal */
3748 		} else {
3749 			/* Enable some IRQs by default */
3750 			regmap_update_bits(wm8962->regmap,
3751 					   WM8962_INTERRUPT_STATUS_2_MASK,
3752 					   WM8962_FLL_LOCK_EINT |
3753 					   WM8962_TEMP_SHUT_EINT |
3754 					   WM8962_FIFOS_ERR_EINT, 0);
3755 		}
3756 	}
3757 
3758 	pm_runtime_enable(&i2c->dev);
3759 	pm_request_idle(&i2c->dev);
3760 
3761 	ret = snd_soc_register_codec(&i2c->dev,
3762 				     &soc_codec_dev_wm8962, &wm8962_dai, 1);
3763 	if (ret < 0)
3764 		goto err_enable;
3765 
3766 	regcache_cache_only(wm8962->regmap, true);
3767 
3768 	/* The drivers should power up as needed */
3769 	regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3770 
3771 	return 0;
3772 
3773 err_enable:
3774 	regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3775 err:
3776 	return ret;
3777 }
3778 
3779 static int wm8962_i2c_remove(struct i2c_client *client)
3780 {
3781 	snd_soc_unregister_codec(&client->dev);
3782 	return 0;
3783 }
3784 
3785 #ifdef CONFIG_PM_RUNTIME
3786 static int wm8962_runtime_resume(struct device *dev)
3787 {
3788 	struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3789 	int ret;
3790 
3791 	ret = clk_prepare_enable(wm8962->pdata.mclk);
3792 	if (ret) {
3793 		dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3794 		return ret;
3795 	}
3796 
3797 	ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3798 				    wm8962->supplies);
3799 	if (ret != 0) {
3800 		dev_err(dev,
3801 			"Failed to enable supplies: %d\n", ret);
3802 		return ret;
3803 	}
3804 
3805 	regcache_cache_only(wm8962->regmap, false);
3806 
3807 	wm8962_reset(wm8962);
3808 
3809 	/* SYSCLK defaults to on; make sure it is off so we can safely
3810 	 * write to registers if the device is declocked.
3811 	 */
3812 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3813 			   WM8962_SYSCLK_ENA, 0);
3814 
3815 	/* Ensure we have soft control over all registers */
3816 	regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3817 			   WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3818 
3819 	/* Ensure that the oscillator and PLLs are disabled */
3820 	regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3821 			   WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3822 			   0);
3823 
3824 	regcache_sync(wm8962->regmap);
3825 
3826 	regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3827 			   WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3828 			   WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3829 
3830 	/* Bias enable at 2*5k (fast start-up) */
3831 	regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3832 			   WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3833 			   WM8962_BIAS_ENA | 0x180);
3834 
3835 	msleep(5);
3836 
3837 	return 0;
3838 }
3839 
3840 static int wm8962_runtime_suspend(struct device *dev)
3841 {
3842 	struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3843 
3844 	regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3845 			   WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3846 
3847 	regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3848 			   WM8962_STARTUP_BIAS_ENA |
3849 			   WM8962_VMID_BUF_ENA, 0);
3850 
3851 	regcache_cache_only(wm8962->regmap, true);
3852 
3853 	regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3854 			       wm8962->supplies);
3855 
3856 	clk_disable_unprepare(wm8962->pdata.mclk);
3857 
3858 	return 0;
3859 }
3860 #endif
3861 
3862 static struct dev_pm_ops wm8962_pm = {
3863 	SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3864 };
3865 
3866 static const struct i2c_device_id wm8962_i2c_id[] = {
3867 	{ "wm8962", 0 },
3868 	{ }
3869 };
3870 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3871 
3872 static const struct of_device_id wm8962_of_match[] = {
3873 	{ .compatible = "wlf,wm8962", },
3874 	{ }
3875 };
3876 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3877 
3878 static struct i2c_driver wm8962_i2c_driver = {
3879 	.driver = {
3880 		.name = "wm8962",
3881 		.owner = THIS_MODULE,
3882 		.of_match_table = wm8962_of_match,
3883 		.pm = &wm8962_pm,
3884 	},
3885 	.probe =    wm8962_i2c_probe,
3886 	.remove =   wm8962_i2c_remove,
3887 	.id_table = wm8962_i2c_id,
3888 };
3889 
3890 module_i2c_driver(wm8962_i2c_driver);
3891 
3892 MODULE_DESCRIPTION("ASoC WM8962 driver");
3893 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3894 MODULE_LICENSE("GPL");
3895