1 /* 2 * wm8961.c -- WM8961 ALSA SoC Audio driver 3 * 4 * Author: Mark Brown 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Currently unimplemented features: 11 * - ALC 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 29 #include "wm8961.h" 30 31 #define WM8961_MAX_REGISTER 0xFC 32 33 static u16 wm8961_reg_defaults[] = { 34 0x009F, /* R0 - Left Input volume */ 35 0x009F, /* R1 - Right Input volume */ 36 0x0000, /* R2 - LOUT1 volume */ 37 0x0000, /* R3 - ROUT1 volume */ 38 0x0020, /* R4 - Clocking1 */ 39 0x0008, /* R5 - ADC & DAC Control 1 */ 40 0x0000, /* R6 - ADC & DAC Control 2 */ 41 0x000A, /* R7 - Audio Interface 0 */ 42 0x01F4, /* R8 - Clocking2 */ 43 0x0000, /* R9 - Audio Interface 1 */ 44 0x00FF, /* R10 - Left DAC volume */ 45 0x00FF, /* R11 - Right DAC volume */ 46 0x0000, /* R12 */ 47 0x0000, /* R13 */ 48 0x0040, /* R14 - Audio Interface 2 */ 49 0x0000, /* R15 - Software Reset */ 50 0x0000, /* R16 */ 51 0x007B, /* R17 - ALC1 */ 52 0x0000, /* R18 - ALC2 */ 53 0x0032, /* R19 - ALC3 */ 54 0x0000, /* R20 - Noise Gate */ 55 0x00C0, /* R21 - Left ADC volume */ 56 0x00C0, /* R22 - Right ADC volume */ 57 0x0120, /* R23 - Additional control(1) */ 58 0x0000, /* R24 - Additional control(2) */ 59 0x0000, /* R25 - Pwr Mgmt (1) */ 60 0x0000, /* R26 - Pwr Mgmt (2) */ 61 0x0000, /* R27 - Additional Control (3) */ 62 0x0000, /* R28 - Anti-pop */ 63 0x0000, /* R29 */ 64 0x005F, /* R30 - Clocking 3 */ 65 0x0000, /* R31 */ 66 0x0000, /* R32 - ADCL signal path */ 67 0x0000, /* R33 - ADCR signal path */ 68 0x0000, /* R34 */ 69 0x0000, /* R35 */ 70 0x0000, /* R36 */ 71 0x0000, /* R37 */ 72 0x0000, /* R38 */ 73 0x0000, /* R39 */ 74 0x0000, /* R40 - LOUT2 volume */ 75 0x0000, /* R41 - ROUT2 volume */ 76 0x0000, /* R42 */ 77 0x0000, /* R43 */ 78 0x0000, /* R44 */ 79 0x0000, /* R45 */ 80 0x0000, /* R46 */ 81 0x0000, /* R47 - Pwr Mgmt (3) */ 82 0x0023, /* R48 - Additional Control (4) */ 83 0x0000, /* R49 - Class D Control 1 */ 84 0x0000, /* R50 */ 85 0x0003, /* R51 - Class D Control 2 */ 86 0x0000, /* R52 */ 87 0x0000, /* R53 */ 88 0x0000, /* R54 */ 89 0x0000, /* R55 */ 90 0x0106, /* R56 - Clocking 4 */ 91 0x0000, /* R57 - DSP Sidetone 0 */ 92 0x0000, /* R58 - DSP Sidetone 1 */ 93 0x0000, /* R59 */ 94 0x0000, /* R60 - DC Servo 0 */ 95 0x0000, /* R61 - DC Servo 1 */ 96 0x0000, /* R62 */ 97 0x015E, /* R63 - DC Servo 3 */ 98 0x0010, /* R64 */ 99 0x0010, /* R65 - DC Servo 5 */ 100 0x0000, /* R66 */ 101 0x0001, /* R67 */ 102 0x0003, /* R68 - Analogue PGA Bias */ 103 0x0000, /* R69 - Analogue HP 0 */ 104 0x0060, /* R70 */ 105 0x01FB, /* R71 - Analogue HP 2 */ 106 0x0000, /* R72 - Charge Pump 1 */ 107 0x0065, /* R73 */ 108 0x005F, /* R74 */ 109 0x0059, /* R75 */ 110 0x006B, /* R76 */ 111 0x0038, /* R77 */ 112 0x000C, /* R78 */ 113 0x000A, /* R79 */ 114 0x006B, /* R80 */ 115 0x0000, /* R81 */ 116 0x0000, /* R82 - Charge Pump B */ 117 0x0087, /* R83 */ 118 0x0000, /* R84 */ 119 0x005C, /* R85 */ 120 0x0000, /* R86 */ 121 0x0000, /* R87 - Write Sequencer 1 */ 122 0x0000, /* R88 - Write Sequencer 2 */ 123 0x0000, /* R89 - Write Sequencer 3 */ 124 0x0000, /* R90 - Write Sequencer 4 */ 125 0x0000, /* R91 - Write Sequencer 5 */ 126 0x0000, /* R92 - Write Sequencer 6 */ 127 0x0000, /* R93 - Write Sequencer 7 */ 128 0x0000, /* R94 */ 129 0x0000, /* R95 */ 130 0x0000, /* R96 */ 131 0x0000, /* R97 */ 132 0x0000, /* R98 */ 133 0x0000, /* R99 */ 134 0x0000, /* R100 */ 135 0x0000, /* R101 */ 136 0x0000, /* R102 */ 137 0x0000, /* R103 */ 138 0x0000, /* R104 */ 139 0x0000, /* R105 */ 140 0x0000, /* R106 */ 141 0x0000, /* R107 */ 142 0x0000, /* R108 */ 143 0x0000, /* R109 */ 144 0x0000, /* R110 */ 145 0x0000, /* R111 */ 146 0x0000, /* R112 */ 147 0x0000, /* R113 */ 148 0x0000, /* R114 */ 149 0x0000, /* R115 */ 150 0x0000, /* R116 */ 151 0x0000, /* R117 */ 152 0x0000, /* R118 */ 153 0x0000, /* R119 */ 154 0x0000, /* R120 */ 155 0x0000, /* R121 */ 156 0x0000, /* R122 */ 157 0x0000, /* R123 */ 158 0x0000, /* R124 */ 159 0x0000, /* R125 */ 160 0x0000, /* R126 */ 161 0x0000, /* R127 */ 162 0x0000, /* R128 */ 163 0x0000, /* R129 */ 164 0x0000, /* R130 */ 165 0x0000, /* R131 */ 166 0x0000, /* R132 */ 167 0x0000, /* R133 */ 168 0x0000, /* R134 */ 169 0x0000, /* R135 */ 170 0x0000, /* R136 */ 171 0x0000, /* R137 */ 172 0x0000, /* R138 */ 173 0x0000, /* R139 */ 174 0x0000, /* R140 */ 175 0x0000, /* R141 */ 176 0x0000, /* R142 */ 177 0x0000, /* R143 */ 178 0x0000, /* R144 */ 179 0x0000, /* R145 */ 180 0x0000, /* R146 */ 181 0x0000, /* R147 */ 182 0x0000, /* R148 */ 183 0x0000, /* R149 */ 184 0x0000, /* R150 */ 185 0x0000, /* R151 */ 186 0x0000, /* R152 */ 187 0x0000, /* R153 */ 188 0x0000, /* R154 */ 189 0x0000, /* R155 */ 190 0x0000, /* R156 */ 191 0x0000, /* R157 */ 192 0x0000, /* R158 */ 193 0x0000, /* R159 */ 194 0x0000, /* R160 */ 195 0x0000, /* R161 */ 196 0x0000, /* R162 */ 197 0x0000, /* R163 */ 198 0x0000, /* R164 */ 199 0x0000, /* R165 */ 200 0x0000, /* R166 */ 201 0x0000, /* R167 */ 202 0x0000, /* R168 */ 203 0x0000, /* R169 */ 204 0x0000, /* R170 */ 205 0x0000, /* R171 */ 206 0x0000, /* R172 */ 207 0x0000, /* R173 */ 208 0x0000, /* R174 */ 209 0x0000, /* R175 */ 210 0x0000, /* R176 */ 211 0x0000, /* R177 */ 212 0x0000, /* R178 */ 213 0x0000, /* R179 */ 214 0x0000, /* R180 */ 215 0x0000, /* R181 */ 216 0x0000, /* R182 */ 217 0x0000, /* R183 */ 218 0x0000, /* R184 */ 219 0x0000, /* R185 */ 220 0x0000, /* R186 */ 221 0x0000, /* R187 */ 222 0x0000, /* R188 */ 223 0x0000, /* R189 */ 224 0x0000, /* R190 */ 225 0x0000, /* R191 */ 226 0x0000, /* R192 */ 227 0x0000, /* R193 */ 228 0x0000, /* R194 */ 229 0x0000, /* R195 */ 230 0x0030, /* R196 */ 231 0x0006, /* R197 */ 232 0x0000, /* R198 */ 233 0x0060, /* R199 */ 234 0x0000, /* R200 */ 235 0x003F, /* R201 */ 236 0x0000, /* R202 */ 237 0x0000, /* R203 */ 238 0x0000, /* R204 */ 239 0x0001, /* R205 */ 240 0x0000, /* R206 */ 241 0x0181, /* R207 */ 242 0x0005, /* R208 */ 243 0x0008, /* R209 */ 244 0x0008, /* R210 */ 245 0x0000, /* R211 */ 246 0x013B, /* R212 */ 247 0x0000, /* R213 */ 248 0x0000, /* R214 */ 249 0x0000, /* R215 */ 250 0x0000, /* R216 */ 251 0x0070, /* R217 */ 252 0x0000, /* R218 */ 253 0x0000, /* R219 */ 254 0x0000, /* R220 */ 255 0x0000, /* R221 */ 256 0x0000, /* R222 */ 257 0x0003, /* R223 */ 258 0x0000, /* R224 */ 259 0x0000, /* R225 */ 260 0x0001, /* R226 */ 261 0x0008, /* R227 */ 262 0x0000, /* R228 */ 263 0x0000, /* R229 */ 264 0x0000, /* R230 */ 265 0x0000, /* R231 */ 266 0x0004, /* R232 */ 267 0x0000, /* R233 */ 268 0x0000, /* R234 */ 269 0x0000, /* R235 */ 270 0x0000, /* R236 */ 271 0x0000, /* R237 */ 272 0x0080, /* R238 */ 273 0x0000, /* R239 */ 274 0x0000, /* R240 */ 275 0x0000, /* R241 */ 276 0x0000, /* R242 */ 277 0x0000, /* R243 */ 278 0x0000, /* R244 */ 279 0x0052, /* R245 */ 280 0x0110, /* R246 */ 281 0x0040, /* R247 */ 282 0x0000, /* R248 */ 283 0x0030, /* R249 */ 284 0x0000, /* R250 */ 285 0x0000, /* R251 */ 286 0x0001, /* R252 - General test 1 */ 287 }; 288 289 struct wm8961_priv { 290 struct snd_soc_codec codec; 291 int sysclk; 292 u16 reg_cache[WM8961_MAX_REGISTER]; 293 }; 294 295 static int wm8961_reg_is_volatile(int reg) 296 { 297 switch (reg) { 298 case WM8961_WRITE_SEQUENCER_7: 299 case WM8961_DC_SERVO_1: 300 return 1; 301 302 default: 303 return 0; 304 } 305 } 306 307 static unsigned int wm8961_read_reg_cache(struct snd_soc_codec *codec, 308 unsigned int reg) 309 { 310 u16 *cache = codec->reg_cache; 311 BUG_ON(reg > WM8961_MAX_REGISTER); 312 return cache[reg]; 313 } 314 315 static unsigned int wm8961_read_hw(struct snd_soc_codec *codec, u8 reg) 316 { 317 struct i2c_msg xfer[2]; 318 u16 data; 319 int ret; 320 struct i2c_client *client = codec->control_data; 321 322 BUG_ON(reg > WM8961_MAX_REGISTER); 323 324 /* Write register */ 325 xfer[0].addr = client->addr; 326 xfer[0].flags = 0; 327 xfer[0].len = 1; 328 xfer[0].buf = ® 329 330 /* Read data */ 331 xfer[1].addr = client->addr; 332 xfer[1].flags = I2C_M_RD; 333 xfer[1].len = 2; 334 xfer[1].buf = (u8 *)&data; 335 336 ret = i2c_transfer(client->adapter, xfer, 2); 337 if (ret != 2) { 338 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); 339 return 0; 340 } 341 342 return (data >> 8) | ((data & 0xff) << 8); 343 } 344 345 static unsigned int wm8961_read(struct snd_soc_codec *codec, unsigned int reg) 346 { 347 if (wm8961_reg_is_volatile(reg)) 348 return wm8961_read_hw(codec, reg); 349 else 350 return wm8961_read_reg_cache(codec, reg); 351 } 352 353 static int wm8961_write(struct snd_soc_codec *codec, unsigned int reg, 354 unsigned int value) 355 { 356 u16 *cache = codec->reg_cache; 357 u8 data[3]; 358 359 BUG_ON(reg > WM8961_MAX_REGISTER); 360 361 if (!wm8961_reg_is_volatile(reg)) 362 cache[reg] = value; 363 364 data[0] = reg; 365 data[1] = value >> 8; 366 data[2] = value & 0x00ff; 367 368 if (codec->hw_write(codec->control_data, data, 3) == 3) 369 return 0; 370 else 371 return -EIO; 372 } 373 374 static int wm8961_reset(struct snd_soc_codec *codec) 375 { 376 return wm8961_write(codec, WM8961_SOFTWARE_RESET, 0); 377 } 378 379 /* 380 * The headphone output supports special anti-pop sequences giving 381 * silent power up and power down. 382 */ 383 static int wm8961_hp_event(struct snd_soc_dapm_widget *w, 384 struct snd_kcontrol *kcontrol, int event) 385 { 386 struct snd_soc_codec *codec = w->codec; 387 u16 hp_reg = wm8961_read(codec, WM8961_ANALOGUE_HP_0); 388 u16 cp_reg = wm8961_read(codec, WM8961_CHARGE_PUMP_1); 389 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 390 u16 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 391 int timeout = 500; 392 393 if (event & SND_SOC_DAPM_POST_PMU) { 394 /* Make sure the output is shorted */ 395 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 396 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 397 398 /* Enable the charge pump */ 399 cp_reg |= WM8961_CP_ENA; 400 wm8961_write(codec, WM8961_CHARGE_PUMP_1, cp_reg); 401 mdelay(5); 402 403 /* Enable the PGA */ 404 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; 405 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 406 407 /* Enable the amplifier */ 408 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; 409 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 410 411 /* Second stage enable */ 412 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; 413 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 414 415 /* Enable the DC servo & trigger startup */ 416 dcs_reg |= 417 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR | 418 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; 419 dev_dbg(codec->dev, "Enabling DC servo\n"); 420 421 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 422 do { 423 msleep(1); 424 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 425 } while (--timeout && 426 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 427 WM8961_DCS_TRIG_STARTUP_HPL)); 428 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 429 WM8961_DCS_TRIG_STARTUP_HPL)) 430 dev_err(codec->dev, "DC servo timed out\n"); 431 else 432 dev_dbg(codec->dev, "DC servo startup complete\n"); 433 434 /* Enable the output stage */ 435 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; 436 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 437 438 /* Remove the short on the output stage */ 439 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; 440 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 441 } 442 443 if (event & SND_SOC_DAPM_PRE_PMD) { 444 /* Short the output */ 445 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 446 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 447 448 /* Disable the output stage */ 449 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); 450 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 451 452 /* Disable DC offset cancellation */ 453 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | 454 WM8961_DCS_ENA_CHAN_HPL); 455 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 456 457 /* Finish up */ 458 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | 459 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); 460 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 461 462 /* Disable the PGA */ 463 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); 464 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 465 466 /* Disable the charge pump */ 467 dev_dbg(codec->dev, "Disabling charge pump\n"); 468 wm8961_write(codec, WM8961_CHARGE_PUMP_1, 469 cp_reg & ~WM8961_CP_ENA); 470 } 471 472 return 0; 473 } 474 475 static int wm8961_spk_event(struct snd_soc_dapm_widget *w, 476 struct snd_kcontrol *kcontrol, int event) 477 { 478 struct snd_soc_codec *codec = w->codec; 479 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 480 u16 spk_reg = wm8961_read(codec, WM8961_CLASS_D_CONTROL_1); 481 482 if (event & SND_SOC_DAPM_POST_PMU) { 483 /* Enable the PGA */ 484 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; 485 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 486 487 /* Enable the amplifier */ 488 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; 489 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 490 } 491 492 if (event & SND_SOC_DAPM_PRE_PMD) { 493 /* Enable the amplifier */ 494 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); 495 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 496 497 /* Enable the PGA */ 498 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); 499 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 500 } 501 502 return 0; 503 } 504 505 static const char *adc_hpf_text[] = { 506 "Hi-fi", "Voice 1", "Voice 2", "Voice 3", 507 }; 508 509 static const struct soc_enum adc_hpf = 510 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text); 511 512 static const char *dac_deemph_text[] = { 513 "None", "32kHz", "44.1kHz", "48kHz", 514 }; 515 516 static const struct soc_enum dac_deemph = 517 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text); 518 519 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 520 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0); 521 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); 522 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 523 static unsigned int boost_tlv[] = { 524 TLV_DB_RANGE_HEAD(4), 525 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 526 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0), 527 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0), 528 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0), 529 }; 530 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0); 531 532 static const struct snd_kcontrol_new wm8961_snd_controls[] = { 533 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME, 534 0, 127, 0, out_tlv), 535 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2, 536 6, 3, 7, 0, hp_sec_tlv), 537 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME, 538 7, 1, 0), 539 540 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME, 541 0, 127, 0, out_tlv), 542 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME, 543 7, 1, 0), 544 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0), 545 546 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0), 547 SOC_ENUM("DAC Deemphasis", dac_deemph), 548 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0), 549 550 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0, 551 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv), 552 553 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0), 554 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 555 556 SOC_DOUBLE_R_TLV("Capture Volume", 557 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME, 558 1, 119, 0, adc_tlv), 559 SOC_DOUBLE_R_TLV("Capture Boost Volume", 560 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH, 561 4, 3, 0, boost_tlv), 562 SOC_DOUBLE_R_TLV("Capture PGA Volume", 563 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 564 0, 62, 0, pga_tlv), 565 SOC_DOUBLE_R("Capture PGA ZC Switch", 566 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 567 6, 1, 1), 568 SOC_DOUBLE_R("Capture PGA Switch", 569 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 570 7, 1, 1), 571 }; 572 573 static const char *sidetone_text[] = { 574 "None", "Left", "Right" 575 }; 576 577 static const struct soc_enum dacl_sidetone = 578 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text); 579 580 static const struct soc_enum dacr_sidetone = 581 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text); 582 583 static const struct snd_kcontrol_new dacl_mux = 584 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone); 585 586 static const struct snd_kcontrol_new dacr_mux = 587 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone); 588 589 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = { 590 SND_SOC_DAPM_INPUT("LINPUT"), 591 SND_SOC_DAPM_INPUT("RINPUT"), 592 593 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0), 594 595 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0), 596 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0), 597 598 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0), 599 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0), 600 601 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0), 602 603 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux), 604 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux), 605 606 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0), 607 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0), 608 609 /* Handle as a mono path for DCS */ 610 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, 611 4, 0, NULL, 0, wm8961_hp_event, 612 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 613 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM, 614 4, 0, NULL, 0, wm8961_spk_event, 615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 616 617 SND_SOC_DAPM_OUTPUT("HP_L"), 618 SND_SOC_DAPM_OUTPUT("HP_R"), 619 SND_SOC_DAPM_OUTPUT("SPK_LN"), 620 SND_SOC_DAPM_OUTPUT("SPK_LP"), 621 SND_SOC_DAPM_OUTPUT("SPK_RN"), 622 SND_SOC_DAPM_OUTPUT("SPK_RP"), 623 }; 624 625 626 static const struct snd_soc_dapm_route audio_paths[] = { 627 { "DACL", NULL, "CLK_DSP" }, 628 { "DACL", NULL, "DACL Sidetone" }, 629 { "DACR", NULL, "CLK_DSP" }, 630 { "DACR", NULL, "DACR Sidetone" }, 631 632 { "DACL Sidetone", "Left", "ADCL" }, 633 { "DACL Sidetone", "Right", "ADCR" }, 634 635 { "DACR Sidetone", "Left", "ADCL" }, 636 { "DACR Sidetone", "Right", "ADCR" }, 637 638 { "HP_L", NULL, "Headphone Output" }, 639 { "HP_R", NULL, "Headphone Output" }, 640 { "Headphone Output", NULL, "DACL" }, 641 { "Headphone Output", NULL, "DACR" }, 642 643 { "SPK_LN", NULL, "Speaker Output" }, 644 { "SPK_LP", NULL, "Speaker Output" }, 645 { "SPK_RN", NULL, "Speaker Output" }, 646 { "SPK_RP", NULL, "Speaker Output" }, 647 648 { "Speaker Output", NULL, "DACL" }, 649 { "Speaker Output", NULL, "DACR" }, 650 651 { "ADCL", NULL, "Left Input" }, 652 { "ADCL", NULL, "CLK_DSP" }, 653 { "ADCR", NULL, "Right Input" }, 654 { "ADCR", NULL, "CLK_DSP" }, 655 656 { "Left Input", NULL, "LINPUT" }, 657 { "Right Input", NULL, "RINPUT" }, 658 659 }; 660 661 /* Values for CLK_SYS_RATE */ 662 static struct { 663 int ratio; 664 u16 val; 665 } wm8961_clk_sys_ratio[] = { 666 { 64, 0 }, 667 { 128, 1 }, 668 { 192, 2 }, 669 { 256, 3 }, 670 { 384, 4 }, 671 { 512, 5 }, 672 { 768, 6 }, 673 { 1024, 7 }, 674 { 1408, 8 }, 675 { 1536, 9 }, 676 }; 677 678 /* Values for SAMPLE_RATE */ 679 static struct { 680 int rate; 681 u16 val; 682 } wm8961_srate[] = { 683 { 48000, 0 }, 684 { 44100, 0 }, 685 { 32000, 1 }, 686 { 22050, 2 }, 687 { 24000, 2 }, 688 { 16000, 3 }, 689 { 11250, 4 }, 690 { 12000, 4 }, 691 { 8000, 5 }, 692 }; 693 694 static int wm8961_hw_params(struct snd_pcm_substream *substream, 695 struct snd_pcm_hw_params *params, 696 struct snd_soc_dai *dai) 697 { 698 struct snd_soc_codec *codec = dai->codec; 699 struct wm8961_priv *wm8961 = codec->private_data; 700 int i, best, target, fs; 701 u16 reg; 702 703 fs = params_rate(params); 704 705 if (!wm8961->sysclk) { 706 dev_err(codec->dev, "MCLK has not been specified\n"); 707 return -EINVAL; 708 } 709 710 /* Find the closest sample rate for the filters */ 711 best = 0; 712 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) { 713 if (abs(wm8961_srate[i].rate - fs) < 714 abs(wm8961_srate[best].rate - fs)) 715 best = i; 716 } 717 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_3); 718 reg &= ~WM8961_SAMPLE_RATE_MASK; 719 reg |= wm8961_srate[best].val; 720 wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); 721 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n", 722 wm8961_srate[best].rate, fs); 723 724 /* Select a CLK_SYS/fs ratio equal to or higher than required */ 725 target = wm8961->sysclk / fs; 726 727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) { 728 dev_err(codec->dev, 729 "SYSCLK must be at least 64*fs for DAC\n"); 730 return -EINVAL; 731 } 732 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) { 733 dev_err(codec->dev, 734 "SYSCLK must be at least 256*fs for ADC\n"); 735 return -EINVAL; 736 } 737 738 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) { 739 if (wm8961_clk_sys_ratio[i].ratio >= target) 740 break; 741 } 742 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) { 743 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n"); 744 return -EINVAL; 745 } 746 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n", 747 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, 748 wm8961->sysclk / fs); 749 750 reg = wm8961_read(codec, WM8961_CLOCKING_4); 751 reg &= ~WM8961_CLK_SYS_RATE_MASK; 752 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; 753 wm8961_write(codec, WM8961_CLOCKING_4, reg); 754 755 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 756 reg &= ~WM8961_WL_MASK; 757 switch (params_format(params)) { 758 case SNDRV_PCM_FORMAT_S16_LE: 759 break; 760 case SNDRV_PCM_FORMAT_S20_3LE: 761 reg |= 1 << WM8961_WL_SHIFT; 762 break; 763 case SNDRV_PCM_FORMAT_S24_LE: 764 reg |= 2 << WM8961_WL_SHIFT; 765 break; 766 case SNDRV_PCM_FORMAT_S32_LE: 767 reg |= 3 << WM8961_WL_SHIFT; 768 break; 769 default: 770 return -EINVAL; 771 } 772 wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, reg); 773 774 /* Sloping stop-band filter is recommended for <= 24kHz */ 775 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 776 if (fs <= 24000) 777 reg |= WM8961_DACSLOPE; 778 else 779 reg &= WM8961_DACSLOPE; 780 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 781 782 return 0; 783 } 784 785 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id, 786 unsigned int freq, 787 int dir) 788 { 789 struct snd_soc_codec *codec = dai->codec; 790 struct wm8961_priv *wm8961 = codec->private_data; 791 u16 reg = wm8961_read(codec, WM8961_CLOCKING1); 792 793 if (freq > 33000000) { 794 dev_err(codec->dev, "MCLK must be <33MHz\n"); 795 return -EINVAL; 796 } 797 798 if (freq > 16500000) { 799 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq); 800 reg |= WM8961_MCLKDIV; 801 freq /= 2; 802 } else { 803 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq); 804 reg &= WM8961_MCLKDIV; 805 } 806 807 wm8961_write(codec, WM8961_CLOCKING1, reg); 808 809 wm8961->sysclk = freq; 810 811 return 0; 812 } 813 814 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 815 { 816 struct snd_soc_codec *codec = dai->codec; 817 u16 aif = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 818 819 aif &= ~(WM8961_BCLKINV | WM8961_LRP | 820 WM8961_MS | WM8961_FORMAT_MASK); 821 822 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 823 case SND_SOC_DAIFMT_CBM_CFM: 824 aif |= WM8961_MS; 825 break; 826 case SND_SOC_DAIFMT_CBS_CFS: 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 833 case SND_SOC_DAIFMT_RIGHT_J: 834 break; 835 836 case SND_SOC_DAIFMT_LEFT_J: 837 aif |= 1; 838 break; 839 840 case SND_SOC_DAIFMT_I2S: 841 aif |= 2; 842 break; 843 844 case SND_SOC_DAIFMT_DSP_B: 845 aif |= WM8961_LRP; 846 case SND_SOC_DAIFMT_DSP_A: 847 aif |= 3; 848 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 849 case SND_SOC_DAIFMT_NB_NF: 850 case SND_SOC_DAIFMT_IB_NF: 851 break; 852 default: 853 return -EINVAL; 854 } 855 break; 856 857 default: 858 return -EINVAL; 859 } 860 861 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 862 case SND_SOC_DAIFMT_NB_NF: 863 break; 864 case SND_SOC_DAIFMT_NB_IF: 865 aif |= WM8961_LRP; 866 break; 867 case SND_SOC_DAIFMT_IB_NF: 868 aif |= WM8961_BCLKINV; 869 break; 870 case SND_SOC_DAIFMT_IB_IF: 871 aif |= WM8961_BCLKINV | WM8961_LRP; 872 break; 873 default: 874 return -EINVAL; 875 } 876 877 return wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, aif); 878 } 879 880 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) 881 { 882 struct snd_soc_codec *codec = dai->codec; 883 u16 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_2); 884 885 if (tristate) 886 reg |= WM8961_TRIS; 887 else 888 reg &= ~WM8961_TRIS; 889 890 return wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg); 891 } 892 893 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) 894 { 895 struct snd_soc_codec *codec = dai->codec; 896 u16 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_1); 897 898 if (mute) 899 reg |= WM8961_DACMU; 900 else 901 reg &= ~WM8961_DACMU; 902 903 msleep(17); 904 905 return wm8961_write(codec, WM8961_ADC_DAC_CONTROL_1, reg); 906 } 907 908 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 909 { 910 struct snd_soc_codec *codec = dai->codec; 911 u16 reg; 912 913 switch (div_id) { 914 case WM8961_BCLK: 915 reg = wm8961_read(codec, WM8961_CLOCKING2); 916 reg &= ~WM8961_BCLKDIV_MASK; 917 reg |= div; 918 wm8961_write(codec, WM8961_CLOCKING2, reg); 919 break; 920 921 case WM8961_LRCLK: 922 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_2); 923 reg &= ~WM8961_LRCLK_RATE_MASK; 924 reg |= div; 925 wm8961_write(codec, WM8961_AUDIO_INTERFACE_2, reg); 926 break; 927 928 default: 929 return -EINVAL; 930 } 931 932 return 0; 933 } 934 935 static int wm8961_set_bias_level(struct snd_soc_codec *codec, 936 enum snd_soc_bias_level level) 937 { 938 u16 reg; 939 940 /* This is all slightly unusual since we have no bypass paths 941 * and the output amplifier structure means we can just slam 942 * the biases straight up rather than having to ramp them 943 * slowly. 944 */ 945 switch (level) { 946 case SND_SOC_BIAS_ON: 947 break; 948 949 case SND_SOC_BIAS_PREPARE: 950 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 951 /* Enable bias generation */ 952 reg = wm8961_read(codec, WM8961_ANTI_POP); 953 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; 954 wm8961_write(codec, WM8961_ANTI_POP, reg); 955 956 /* VMID=2*50k, VREF */ 957 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 958 reg &= ~WM8961_VMIDSEL_MASK; 959 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; 960 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 961 } 962 break; 963 964 case SND_SOC_BIAS_STANDBY: 965 if (codec->bias_level == SND_SOC_BIAS_PREPARE) { 966 /* VREF off */ 967 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 968 reg &= ~WM8961_VREF; 969 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 970 971 /* Bias generation off */ 972 reg = wm8961_read(codec, WM8961_ANTI_POP); 973 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); 974 wm8961_write(codec, WM8961_ANTI_POP, reg); 975 976 /* VMID off */ 977 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 978 reg &= ~WM8961_VMIDSEL_MASK; 979 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 980 } 981 break; 982 983 case SND_SOC_BIAS_OFF: 984 break; 985 } 986 987 codec->bias_level = level; 988 989 return 0; 990 } 991 992 993 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000 994 995 #define WM8961_FORMATS \ 996 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 997 SNDRV_PCM_FMTBIT_S24_LE) 998 999 static struct snd_soc_dai_ops wm8961_dai_ops = { 1000 .hw_params = wm8961_hw_params, 1001 .set_sysclk = wm8961_set_sysclk, 1002 .set_fmt = wm8961_set_fmt, 1003 .digital_mute = wm8961_digital_mute, 1004 .set_tristate = wm8961_set_tristate, 1005 .set_clkdiv = wm8961_set_clkdiv, 1006 }; 1007 1008 struct snd_soc_dai wm8961_dai = { 1009 .name = "WM8961", 1010 .playback = { 1011 .stream_name = "HiFi Playback", 1012 .channels_min = 1, 1013 .channels_max = 2, 1014 .rates = WM8961_RATES, 1015 .formats = WM8961_FORMATS,}, 1016 .capture = { 1017 .stream_name = "HiFi Capture", 1018 .channels_min = 1, 1019 .channels_max = 2, 1020 .rates = WM8961_RATES, 1021 .formats = WM8961_FORMATS,}, 1022 .ops = &wm8961_dai_ops, 1023 }; 1024 EXPORT_SYMBOL_GPL(wm8961_dai); 1025 1026 1027 static struct snd_soc_codec *wm8961_codec; 1028 1029 static int wm8961_probe(struct platform_device *pdev) 1030 { 1031 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1032 struct snd_soc_codec *codec; 1033 int ret = 0; 1034 1035 if (wm8961_codec == NULL) { 1036 dev_err(&pdev->dev, "Codec device not registered\n"); 1037 return -ENODEV; 1038 } 1039 1040 socdev->card->codec = wm8961_codec; 1041 codec = wm8961_codec; 1042 1043 /* register pcms */ 1044 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1045 if (ret < 0) { 1046 dev_err(codec->dev, "failed to create pcms: %d\n", ret); 1047 goto pcm_err; 1048 } 1049 1050 snd_soc_add_controls(codec, wm8961_snd_controls, 1051 ARRAY_SIZE(wm8961_snd_controls)); 1052 snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets, 1053 ARRAY_SIZE(wm8961_dapm_widgets)); 1054 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 1055 snd_soc_dapm_new_widgets(codec); 1056 1057 ret = snd_soc_init_card(socdev); 1058 if (ret < 0) { 1059 dev_err(codec->dev, "failed to register card: %d\n", ret); 1060 goto card_err; 1061 } 1062 1063 return ret; 1064 1065 card_err: 1066 snd_soc_free_pcms(socdev); 1067 snd_soc_dapm_free(socdev); 1068 pcm_err: 1069 return ret; 1070 } 1071 1072 static int wm8961_remove(struct platform_device *pdev) 1073 { 1074 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1075 1076 snd_soc_free_pcms(socdev); 1077 snd_soc_dapm_free(socdev); 1078 1079 return 0; 1080 } 1081 1082 #ifdef CONFIG_PM 1083 static int wm8961_suspend(struct platform_device *pdev, pm_message_t state) 1084 { 1085 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1086 struct snd_soc_codec *codec = socdev->card->codec; 1087 1088 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF); 1089 1090 return 0; 1091 } 1092 1093 static int wm8961_resume(struct platform_device *pdev) 1094 { 1095 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1096 struct snd_soc_codec *codec = socdev->card->codec; 1097 u16 *reg_cache = codec->reg_cache; 1098 int i; 1099 1100 for (i = 0; i < codec->reg_cache_size; i++) { 1101 if (i == WM8961_SOFTWARE_RESET) 1102 continue; 1103 1104 wm8961_write(codec, i, reg_cache[i]); 1105 } 1106 1107 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1108 1109 return 0; 1110 } 1111 #else 1112 #define wm8961_suspend NULL 1113 #define wm8961_resume NULL 1114 #endif 1115 1116 struct snd_soc_codec_device soc_codec_dev_wm8961 = { 1117 .probe = wm8961_probe, 1118 .remove = wm8961_remove, 1119 .suspend = wm8961_suspend, 1120 .resume = wm8961_resume, 1121 }; 1122 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8961); 1123 1124 static int wm8961_register(struct wm8961_priv *wm8961) 1125 { 1126 struct snd_soc_codec *codec = &wm8961->codec; 1127 int ret; 1128 u16 reg; 1129 1130 if (wm8961_codec) { 1131 dev_err(codec->dev, "Another WM8961 is registered\n"); 1132 ret = -EINVAL; 1133 goto err; 1134 } 1135 1136 mutex_init(&codec->mutex); 1137 INIT_LIST_HEAD(&codec->dapm_widgets); 1138 INIT_LIST_HEAD(&codec->dapm_paths); 1139 1140 codec->private_data = wm8961; 1141 codec->name = "WM8961"; 1142 codec->owner = THIS_MODULE; 1143 codec->read = wm8961_read; 1144 codec->write = wm8961_write; 1145 codec->dai = &wm8961_dai; 1146 codec->num_dai = 1; 1147 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache); 1148 codec->reg_cache = &wm8961->reg_cache; 1149 codec->bias_level = SND_SOC_BIAS_OFF; 1150 codec->set_bias_level = wm8961_set_bias_level; 1151 1152 memcpy(codec->reg_cache, wm8961_reg_defaults, 1153 sizeof(wm8961_reg_defaults)); 1154 1155 reg = wm8961_read_hw(codec, WM8961_SOFTWARE_RESET); 1156 if (reg != 0x1801) { 1157 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg); 1158 ret = -EINVAL; 1159 goto err; 1160 } 1161 1162 reg = wm8961_read_hw(codec, WM8961_RIGHT_INPUT_VOLUME); 1163 dev_info(codec->dev, "WM8961 family %d revision %c\n", 1164 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, 1165 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) 1166 + 'A'); 1167 1168 ret = wm8961_reset(codec); 1169 if (ret < 0) { 1170 dev_err(codec->dev, "Failed to issue reset\n"); 1171 return ret; 1172 } 1173 1174 /* Enable class W */ 1175 reg = wm8961_read(codec, WM8961_CHARGE_PUMP_B); 1176 reg |= WM8961_CP_DYN_PWR_MASK; 1177 wm8961_write(codec, WM8961_CHARGE_PUMP_B, reg); 1178 1179 /* Latch volume update bits (right channel only, we always 1180 * write both out) and default ZC on. */ 1181 reg = wm8961_read(codec, WM8961_ROUT1_VOLUME); 1182 wm8961_write(codec, WM8961_ROUT1_VOLUME, 1183 reg | WM8961_LO1ZC | WM8961_OUT1VU); 1184 wm8961_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); 1185 reg = wm8961_read(codec, WM8961_ROUT2_VOLUME); 1186 wm8961_write(codec, WM8961_ROUT2_VOLUME, 1187 reg | WM8961_SPKRZC | WM8961_SPKVU); 1188 wm8961_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); 1189 1190 reg = wm8961_read(codec, WM8961_RIGHT_ADC_VOLUME); 1191 wm8961_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); 1192 reg = wm8961_read(codec, WM8961_RIGHT_INPUT_VOLUME); 1193 wm8961_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); 1194 1195 /* Use soft mute by default */ 1196 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 1197 reg |= WM8961_DACSMM; 1198 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 1199 1200 /* Use automatic clocking mode by default; for now this is all 1201 * we support. 1202 */ 1203 reg = wm8961_read(codec, WM8961_CLOCKING_3); 1204 reg &= ~WM8961_MANUAL_MODE; 1205 wm8961_write(codec, WM8961_CLOCKING_3, reg); 1206 1207 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1208 1209 wm8961_dai.dev = codec->dev; 1210 1211 wm8961_codec = codec; 1212 1213 ret = snd_soc_register_codec(codec); 1214 if (ret != 0) { 1215 dev_err(codec->dev, "Failed to register codec: %d\n", ret); 1216 return ret; 1217 } 1218 1219 ret = snd_soc_register_dai(&wm8961_dai); 1220 if (ret != 0) { 1221 dev_err(codec->dev, "Failed to register DAI: %d\n", ret); 1222 snd_soc_unregister_codec(codec); 1223 return ret; 1224 } 1225 1226 return 0; 1227 1228 err: 1229 kfree(wm8961); 1230 return ret; 1231 } 1232 1233 static void wm8961_unregister(struct wm8961_priv *wm8961) 1234 { 1235 wm8961_set_bias_level(&wm8961->codec, SND_SOC_BIAS_OFF); 1236 snd_soc_unregister_dai(&wm8961_dai); 1237 snd_soc_unregister_codec(&wm8961->codec); 1238 kfree(wm8961); 1239 wm8961_codec = NULL; 1240 } 1241 1242 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c, 1243 const struct i2c_device_id *id) 1244 { 1245 struct wm8961_priv *wm8961; 1246 struct snd_soc_codec *codec; 1247 1248 wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL); 1249 if (wm8961 == NULL) 1250 return -ENOMEM; 1251 1252 codec = &wm8961->codec; 1253 codec->hw_write = (hw_write_t)i2c_master_send; 1254 1255 i2c_set_clientdata(i2c, wm8961); 1256 codec->control_data = i2c; 1257 1258 codec->dev = &i2c->dev; 1259 1260 return wm8961_register(wm8961); 1261 } 1262 1263 static __devexit int wm8961_i2c_remove(struct i2c_client *client) 1264 { 1265 struct wm8961_priv *wm8961 = i2c_get_clientdata(client); 1266 wm8961_unregister(wm8961); 1267 return 0; 1268 } 1269 1270 static const struct i2c_device_id wm8961_i2c_id[] = { 1271 { "wm8961", 0 }, 1272 { } 1273 }; 1274 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id); 1275 1276 static struct i2c_driver wm8961_i2c_driver = { 1277 .driver = { 1278 .name = "wm8961", 1279 .owner = THIS_MODULE, 1280 }, 1281 .probe = wm8961_i2c_probe, 1282 .remove = __devexit_p(wm8961_i2c_remove), 1283 .id_table = wm8961_i2c_id, 1284 }; 1285 1286 static int __init wm8961_modinit(void) 1287 { 1288 int ret; 1289 1290 ret = i2c_add_driver(&wm8961_i2c_driver); 1291 if (ret != 0) { 1292 printk(KERN_ERR "Failed to register WM8961 I2C driver: %d\n", 1293 ret); 1294 } 1295 1296 return ret; 1297 } 1298 module_init(wm8961_modinit); 1299 1300 static void __exit wm8961_exit(void) 1301 { 1302 i2c_del_driver(&wm8961_i2c_driver); 1303 } 1304 module_exit(wm8961_exit); 1305 1306 1307 MODULE_DESCRIPTION("ASoC WM8961 driver"); 1308 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1309 MODULE_LICENSE("GPL"); 1310