1 /* 2 * wm8961.c -- WM8961 ALSA SoC Audio driver 3 * 4 * Author: Mark Brown 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Currently unimplemented features: 11 * - ALC 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/initval.h> 26 #include <sound/tlv.h> 27 28 #include "wm8961.h" 29 30 #define WM8961_MAX_REGISTER 0xFC 31 32 static u16 wm8961_reg_defaults[] = { 33 0x009F, /* R0 - Left Input volume */ 34 0x009F, /* R1 - Right Input volume */ 35 0x0000, /* R2 - LOUT1 volume */ 36 0x0000, /* R3 - ROUT1 volume */ 37 0x0020, /* R4 - Clocking1 */ 38 0x0008, /* R5 - ADC & DAC Control 1 */ 39 0x0000, /* R6 - ADC & DAC Control 2 */ 40 0x000A, /* R7 - Audio Interface 0 */ 41 0x01F4, /* R8 - Clocking2 */ 42 0x0000, /* R9 - Audio Interface 1 */ 43 0x00FF, /* R10 - Left DAC volume */ 44 0x00FF, /* R11 - Right DAC volume */ 45 0x0000, /* R12 */ 46 0x0000, /* R13 */ 47 0x0040, /* R14 - Audio Interface 2 */ 48 0x0000, /* R15 - Software Reset */ 49 0x0000, /* R16 */ 50 0x007B, /* R17 - ALC1 */ 51 0x0000, /* R18 - ALC2 */ 52 0x0032, /* R19 - ALC3 */ 53 0x0000, /* R20 - Noise Gate */ 54 0x00C0, /* R21 - Left ADC volume */ 55 0x00C0, /* R22 - Right ADC volume */ 56 0x0120, /* R23 - Additional control(1) */ 57 0x0000, /* R24 - Additional control(2) */ 58 0x0000, /* R25 - Pwr Mgmt (1) */ 59 0x0000, /* R26 - Pwr Mgmt (2) */ 60 0x0000, /* R27 - Additional Control (3) */ 61 0x0000, /* R28 - Anti-pop */ 62 0x0000, /* R29 */ 63 0x005F, /* R30 - Clocking 3 */ 64 0x0000, /* R31 */ 65 0x0000, /* R32 - ADCL signal path */ 66 0x0000, /* R33 - ADCR signal path */ 67 0x0000, /* R34 */ 68 0x0000, /* R35 */ 69 0x0000, /* R36 */ 70 0x0000, /* R37 */ 71 0x0000, /* R38 */ 72 0x0000, /* R39 */ 73 0x0000, /* R40 - LOUT2 volume */ 74 0x0000, /* R41 - ROUT2 volume */ 75 0x0000, /* R42 */ 76 0x0000, /* R43 */ 77 0x0000, /* R44 */ 78 0x0000, /* R45 */ 79 0x0000, /* R46 */ 80 0x0000, /* R47 - Pwr Mgmt (3) */ 81 0x0023, /* R48 - Additional Control (4) */ 82 0x0000, /* R49 - Class D Control 1 */ 83 0x0000, /* R50 */ 84 0x0003, /* R51 - Class D Control 2 */ 85 0x0000, /* R52 */ 86 0x0000, /* R53 */ 87 0x0000, /* R54 */ 88 0x0000, /* R55 */ 89 0x0106, /* R56 - Clocking 4 */ 90 0x0000, /* R57 - DSP Sidetone 0 */ 91 0x0000, /* R58 - DSP Sidetone 1 */ 92 0x0000, /* R59 */ 93 0x0000, /* R60 - DC Servo 0 */ 94 0x0000, /* R61 - DC Servo 1 */ 95 0x0000, /* R62 */ 96 0x015E, /* R63 - DC Servo 3 */ 97 0x0010, /* R64 */ 98 0x0010, /* R65 - DC Servo 5 */ 99 0x0000, /* R66 */ 100 0x0001, /* R67 */ 101 0x0003, /* R68 - Analogue PGA Bias */ 102 0x0000, /* R69 - Analogue HP 0 */ 103 0x0060, /* R70 */ 104 0x01FB, /* R71 - Analogue HP 2 */ 105 0x0000, /* R72 - Charge Pump 1 */ 106 0x0065, /* R73 */ 107 0x005F, /* R74 */ 108 0x0059, /* R75 */ 109 0x006B, /* R76 */ 110 0x0038, /* R77 */ 111 0x000C, /* R78 */ 112 0x000A, /* R79 */ 113 0x006B, /* R80 */ 114 0x0000, /* R81 */ 115 0x0000, /* R82 - Charge Pump B */ 116 0x0087, /* R83 */ 117 0x0000, /* R84 */ 118 0x005C, /* R85 */ 119 0x0000, /* R86 */ 120 0x0000, /* R87 - Write Sequencer 1 */ 121 0x0000, /* R88 - Write Sequencer 2 */ 122 0x0000, /* R89 - Write Sequencer 3 */ 123 0x0000, /* R90 - Write Sequencer 4 */ 124 0x0000, /* R91 - Write Sequencer 5 */ 125 0x0000, /* R92 - Write Sequencer 6 */ 126 0x0000, /* R93 - Write Sequencer 7 */ 127 0x0000, /* R94 */ 128 0x0000, /* R95 */ 129 0x0000, /* R96 */ 130 0x0000, /* R97 */ 131 0x0000, /* R98 */ 132 0x0000, /* R99 */ 133 0x0000, /* R100 */ 134 0x0000, /* R101 */ 135 0x0000, /* R102 */ 136 0x0000, /* R103 */ 137 0x0000, /* R104 */ 138 0x0000, /* R105 */ 139 0x0000, /* R106 */ 140 0x0000, /* R107 */ 141 0x0000, /* R108 */ 142 0x0000, /* R109 */ 143 0x0000, /* R110 */ 144 0x0000, /* R111 */ 145 0x0000, /* R112 */ 146 0x0000, /* R113 */ 147 0x0000, /* R114 */ 148 0x0000, /* R115 */ 149 0x0000, /* R116 */ 150 0x0000, /* R117 */ 151 0x0000, /* R118 */ 152 0x0000, /* R119 */ 153 0x0000, /* R120 */ 154 0x0000, /* R121 */ 155 0x0000, /* R122 */ 156 0x0000, /* R123 */ 157 0x0000, /* R124 */ 158 0x0000, /* R125 */ 159 0x0000, /* R126 */ 160 0x0000, /* R127 */ 161 0x0000, /* R128 */ 162 0x0000, /* R129 */ 163 0x0000, /* R130 */ 164 0x0000, /* R131 */ 165 0x0000, /* R132 */ 166 0x0000, /* R133 */ 167 0x0000, /* R134 */ 168 0x0000, /* R135 */ 169 0x0000, /* R136 */ 170 0x0000, /* R137 */ 171 0x0000, /* R138 */ 172 0x0000, /* R139 */ 173 0x0000, /* R140 */ 174 0x0000, /* R141 */ 175 0x0000, /* R142 */ 176 0x0000, /* R143 */ 177 0x0000, /* R144 */ 178 0x0000, /* R145 */ 179 0x0000, /* R146 */ 180 0x0000, /* R147 */ 181 0x0000, /* R148 */ 182 0x0000, /* R149 */ 183 0x0000, /* R150 */ 184 0x0000, /* R151 */ 185 0x0000, /* R152 */ 186 0x0000, /* R153 */ 187 0x0000, /* R154 */ 188 0x0000, /* R155 */ 189 0x0000, /* R156 */ 190 0x0000, /* R157 */ 191 0x0000, /* R158 */ 192 0x0000, /* R159 */ 193 0x0000, /* R160 */ 194 0x0000, /* R161 */ 195 0x0000, /* R162 */ 196 0x0000, /* R163 */ 197 0x0000, /* R164 */ 198 0x0000, /* R165 */ 199 0x0000, /* R166 */ 200 0x0000, /* R167 */ 201 0x0000, /* R168 */ 202 0x0000, /* R169 */ 203 0x0000, /* R170 */ 204 0x0000, /* R171 */ 205 0x0000, /* R172 */ 206 0x0000, /* R173 */ 207 0x0000, /* R174 */ 208 0x0000, /* R175 */ 209 0x0000, /* R176 */ 210 0x0000, /* R177 */ 211 0x0000, /* R178 */ 212 0x0000, /* R179 */ 213 0x0000, /* R180 */ 214 0x0000, /* R181 */ 215 0x0000, /* R182 */ 216 0x0000, /* R183 */ 217 0x0000, /* R184 */ 218 0x0000, /* R185 */ 219 0x0000, /* R186 */ 220 0x0000, /* R187 */ 221 0x0000, /* R188 */ 222 0x0000, /* R189 */ 223 0x0000, /* R190 */ 224 0x0000, /* R191 */ 225 0x0000, /* R192 */ 226 0x0000, /* R193 */ 227 0x0000, /* R194 */ 228 0x0000, /* R195 */ 229 0x0030, /* R196 */ 230 0x0006, /* R197 */ 231 0x0000, /* R198 */ 232 0x0060, /* R199 */ 233 0x0000, /* R200 */ 234 0x003F, /* R201 */ 235 0x0000, /* R202 */ 236 0x0000, /* R203 */ 237 0x0000, /* R204 */ 238 0x0001, /* R205 */ 239 0x0000, /* R206 */ 240 0x0181, /* R207 */ 241 0x0005, /* R208 */ 242 0x0008, /* R209 */ 243 0x0008, /* R210 */ 244 0x0000, /* R211 */ 245 0x013B, /* R212 */ 246 0x0000, /* R213 */ 247 0x0000, /* R214 */ 248 0x0000, /* R215 */ 249 0x0000, /* R216 */ 250 0x0070, /* R217 */ 251 0x0000, /* R218 */ 252 0x0000, /* R219 */ 253 0x0000, /* R220 */ 254 0x0000, /* R221 */ 255 0x0000, /* R222 */ 256 0x0003, /* R223 */ 257 0x0000, /* R224 */ 258 0x0000, /* R225 */ 259 0x0001, /* R226 */ 260 0x0008, /* R227 */ 261 0x0000, /* R228 */ 262 0x0000, /* R229 */ 263 0x0000, /* R230 */ 264 0x0000, /* R231 */ 265 0x0004, /* R232 */ 266 0x0000, /* R233 */ 267 0x0000, /* R234 */ 268 0x0000, /* R235 */ 269 0x0000, /* R236 */ 270 0x0000, /* R237 */ 271 0x0080, /* R238 */ 272 0x0000, /* R239 */ 273 0x0000, /* R240 */ 274 0x0000, /* R241 */ 275 0x0000, /* R242 */ 276 0x0000, /* R243 */ 277 0x0000, /* R244 */ 278 0x0052, /* R245 */ 279 0x0110, /* R246 */ 280 0x0040, /* R247 */ 281 0x0000, /* R248 */ 282 0x0030, /* R249 */ 283 0x0000, /* R250 */ 284 0x0000, /* R251 */ 285 0x0001, /* R252 - General test 1 */ 286 }; 287 288 struct wm8961_priv { 289 enum snd_soc_control_type control_type; 290 int sysclk; 291 }; 292 293 static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 294 { 295 switch (reg) { 296 case WM8961_SOFTWARE_RESET: 297 case WM8961_WRITE_SEQUENCER_7: 298 case WM8961_DC_SERVO_1: 299 return 1; 300 301 default: 302 return 0; 303 } 304 } 305 306 static int wm8961_reset(struct snd_soc_codec *codec) 307 { 308 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0); 309 } 310 311 /* 312 * The headphone output supports special anti-pop sequences giving 313 * silent power up and power down. 314 */ 315 static int wm8961_hp_event(struct snd_soc_dapm_widget *w, 316 struct snd_kcontrol *kcontrol, int event) 317 { 318 struct snd_soc_codec *codec = w->codec; 319 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0); 320 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1); 321 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2); 322 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1); 323 int timeout = 500; 324 325 if (event & SND_SOC_DAPM_POST_PMU) { 326 /* Make sure the output is shorted */ 327 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 328 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 329 330 /* Enable the charge pump */ 331 cp_reg |= WM8961_CP_ENA; 332 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg); 333 mdelay(5); 334 335 /* Enable the PGA */ 336 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; 337 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 338 339 /* Enable the amplifier */ 340 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; 341 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 342 343 /* Second stage enable */ 344 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; 345 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 346 347 /* Enable the DC servo & trigger startup */ 348 dcs_reg |= 349 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR | 350 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; 351 dev_dbg(codec->dev, "Enabling DC servo\n"); 352 353 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg); 354 do { 355 msleep(1); 356 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1); 357 } while (--timeout && 358 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 359 WM8961_DCS_TRIG_STARTUP_HPL)); 360 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 361 WM8961_DCS_TRIG_STARTUP_HPL)) 362 dev_err(codec->dev, "DC servo timed out\n"); 363 else 364 dev_dbg(codec->dev, "DC servo startup complete\n"); 365 366 /* Enable the output stage */ 367 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; 368 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 369 370 /* Remove the short on the output stage */ 371 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; 372 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 373 } 374 375 if (event & SND_SOC_DAPM_PRE_PMD) { 376 /* Short the output */ 377 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 378 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 379 380 /* Disable the output stage */ 381 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); 382 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 383 384 /* Disable DC offset cancellation */ 385 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | 386 WM8961_DCS_ENA_CHAN_HPL); 387 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg); 388 389 /* Finish up */ 390 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | 391 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); 392 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 393 394 /* Disable the PGA */ 395 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); 396 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 397 398 /* Disable the charge pump */ 399 dev_dbg(codec->dev, "Disabling charge pump\n"); 400 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, 401 cp_reg & ~WM8961_CP_ENA); 402 } 403 404 return 0; 405 } 406 407 static int wm8961_spk_event(struct snd_soc_dapm_widget *w, 408 struct snd_kcontrol *kcontrol, int event) 409 { 410 struct snd_soc_codec *codec = w->codec; 411 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2); 412 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1); 413 414 if (event & SND_SOC_DAPM_POST_PMU) { 415 /* Enable the PGA */ 416 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; 417 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 418 419 /* Enable the amplifier */ 420 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; 421 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 422 } 423 424 if (event & SND_SOC_DAPM_PRE_PMD) { 425 /* Disable the amplifier */ 426 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); 427 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 428 429 /* Disable the PGA */ 430 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); 431 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 432 } 433 434 return 0; 435 } 436 437 static const char *adc_hpf_text[] = { 438 "Hi-fi", "Voice 1", "Voice 2", "Voice 3", 439 }; 440 441 static const struct soc_enum adc_hpf = 442 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text); 443 444 static const char *dac_deemph_text[] = { 445 "None", "32kHz", "44.1kHz", "48kHz", 446 }; 447 448 static const struct soc_enum dac_deemph = 449 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text); 450 451 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 452 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0); 453 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); 454 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 455 static unsigned int boost_tlv[] = { 456 TLV_DB_RANGE_HEAD(4), 457 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 458 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0), 459 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0), 460 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0), 461 }; 462 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0); 463 464 static const struct snd_kcontrol_new wm8961_snd_controls[] = { 465 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME, 466 0, 127, 0, out_tlv), 467 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2, 468 6, 3, 7, 0, hp_sec_tlv), 469 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME, 470 7, 1, 0), 471 472 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME, 473 0, 127, 0, out_tlv), 474 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME, 475 7, 1, 0), 476 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0), 477 478 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0), 479 SOC_ENUM("DAC Deemphasis", dac_deemph), 480 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0), 481 482 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0, 483 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv), 484 485 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0), 486 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 487 488 SOC_DOUBLE_R_TLV("Capture Volume", 489 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME, 490 1, 119, 0, adc_tlv), 491 SOC_DOUBLE_R_TLV("Capture Boost Volume", 492 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH, 493 4, 3, 0, boost_tlv), 494 SOC_DOUBLE_R_TLV("Capture PGA Volume", 495 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 496 0, 62, 0, pga_tlv), 497 SOC_DOUBLE_R("Capture PGA ZC Switch", 498 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 499 6, 1, 1), 500 SOC_DOUBLE_R("Capture PGA Switch", 501 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME, 502 7, 1, 1), 503 }; 504 505 static const char *sidetone_text[] = { 506 "None", "Left", "Right" 507 }; 508 509 static const struct soc_enum dacl_sidetone = 510 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text); 511 512 static const struct soc_enum dacr_sidetone = 513 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text); 514 515 static const struct snd_kcontrol_new dacl_mux = 516 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone); 517 518 static const struct snd_kcontrol_new dacr_mux = 519 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone); 520 521 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = { 522 SND_SOC_DAPM_INPUT("LINPUT"), 523 SND_SOC_DAPM_INPUT("RINPUT"), 524 525 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0), 526 527 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0), 528 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0), 529 530 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0), 531 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0), 532 533 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0), 534 535 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux), 536 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux), 537 538 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0), 539 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0), 540 541 /* Handle as a mono path for DCS */ 542 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, 543 4, 0, NULL, 0, wm8961_hp_event, 544 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 545 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM, 546 4, 0, NULL, 0, wm8961_spk_event, 547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 548 549 SND_SOC_DAPM_OUTPUT("HP_L"), 550 SND_SOC_DAPM_OUTPUT("HP_R"), 551 SND_SOC_DAPM_OUTPUT("SPK_LN"), 552 SND_SOC_DAPM_OUTPUT("SPK_LP"), 553 SND_SOC_DAPM_OUTPUT("SPK_RN"), 554 SND_SOC_DAPM_OUTPUT("SPK_RP"), 555 }; 556 557 558 static const struct snd_soc_dapm_route audio_paths[] = { 559 { "DACL", NULL, "CLK_DSP" }, 560 { "DACL", NULL, "DACL Sidetone" }, 561 { "DACR", NULL, "CLK_DSP" }, 562 { "DACR", NULL, "DACR Sidetone" }, 563 564 { "DACL Sidetone", "Left", "ADCL" }, 565 { "DACL Sidetone", "Right", "ADCR" }, 566 567 { "DACR Sidetone", "Left", "ADCL" }, 568 { "DACR Sidetone", "Right", "ADCR" }, 569 570 { "HP_L", NULL, "Headphone Output" }, 571 { "HP_R", NULL, "Headphone Output" }, 572 { "Headphone Output", NULL, "DACL" }, 573 { "Headphone Output", NULL, "DACR" }, 574 575 { "SPK_LN", NULL, "Speaker Output" }, 576 { "SPK_LP", NULL, "Speaker Output" }, 577 { "SPK_RN", NULL, "Speaker Output" }, 578 { "SPK_RP", NULL, "Speaker Output" }, 579 580 { "Speaker Output", NULL, "DACL" }, 581 { "Speaker Output", NULL, "DACR" }, 582 583 { "ADCL", NULL, "Left Input" }, 584 { "ADCL", NULL, "CLK_DSP" }, 585 { "ADCR", NULL, "Right Input" }, 586 { "ADCR", NULL, "CLK_DSP" }, 587 588 { "Left Input", NULL, "LINPUT" }, 589 { "Right Input", NULL, "RINPUT" }, 590 591 }; 592 593 /* Values for CLK_SYS_RATE */ 594 static struct { 595 int ratio; 596 u16 val; 597 } wm8961_clk_sys_ratio[] = { 598 { 64, 0 }, 599 { 128, 1 }, 600 { 192, 2 }, 601 { 256, 3 }, 602 { 384, 4 }, 603 { 512, 5 }, 604 { 768, 6 }, 605 { 1024, 7 }, 606 { 1408, 8 }, 607 { 1536, 9 }, 608 }; 609 610 /* Values for SAMPLE_RATE */ 611 static struct { 612 int rate; 613 u16 val; 614 } wm8961_srate[] = { 615 { 48000, 0 }, 616 { 44100, 0 }, 617 { 32000, 1 }, 618 { 22050, 2 }, 619 { 24000, 2 }, 620 { 16000, 3 }, 621 { 11250, 4 }, 622 { 12000, 4 }, 623 { 8000, 5 }, 624 }; 625 626 static int wm8961_hw_params(struct snd_pcm_substream *substream, 627 struct snd_pcm_hw_params *params, 628 struct snd_soc_dai *dai) 629 { 630 struct snd_soc_codec *codec = dai->codec; 631 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec); 632 int i, best, target, fs; 633 u16 reg; 634 635 fs = params_rate(params); 636 637 if (!wm8961->sysclk) { 638 dev_err(codec->dev, "MCLK has not been specified\n"); 639 return -EINVAL; 640 } 641 642 /* Find the closest sample rate for the filters */ 643 best = 0; 644 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) { 645 if (abs(wm8961_srate[i].rate - fs) < 646 abs(wm8961_srate[best].rate - fs)) 647 best = i; 648 } 649 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3); 650 reg &= ~WM8961_SAMPLE_RATE_MASK; 651 reg |= wm8961_srate[best].val; 652 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); 653 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n", 654 wm8961_srate[best].rate, fs); 655 656 /* Select a CLK_SYS/fs ratio equal to or higher than required */ 657 target = wm8961->sysclk / fs; 658 659 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) { 660 dev_err(codec->dev, 661 "SYSCLK must be at least 64*fs for DAC\n"); 662 return -EINVAL; 663 } 664 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) { 665 dev_err(codec->dev, 666 "SYSCLK must be at least 256*fs for ADC\n"); 667 return -EINVAL; 668 } 669 670 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) { 671 if (wm8961_clk_sys_ratio[i].ratio >= target) 672 break; 673 } 674 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) { 675 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n"); 676 return -EINVAL; 677 } 678 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n", 679 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, 680 wm8961->sysclk / fs); 681 682 reg = snd_soc_read(codec, WM8961_CLOCKING_4); 683 reg &= ~WM8961_CLK_SYS_RATE_MASK; 684 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; 685 snd_soc_write(codec, WM8961_CLOCKING_4, reg); 686 687 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0); 688 reg &= ~WM8961_WL_MASK; 689 switch (params_format(params)) { 690 case SNDRV_PCM_FORMAT_S16_LE: 691 break; 692 case SNDRV_PCM_FORMAT_S20_3LE: 693 reg |= 1 << WM8961_WL_SHIFT; 694 break; 695 case SNDRV_PCM_FORMAT_S24_LE: 696 reg |= 2 << WM8961_WL_SHIFT; 697 break; 698 case SNDRV_PCM_FORMAT_S32_LE: 699 reg |= 3 << WM8961_WL_SHIFT; 700 break; 701 default: 702 return -EINVAL; 703 } 704 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg); 705 706 /* Sloping stop-band filter is recommended for <= 24kHz */ 707 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2); 708 if (fs <= 24000) 709 reg |= WM8961_DACSLOPE; 710 else 711 reg &= ~WM8961_DACSLOPE; 712 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 713 714 return 0; 715 } 716 717 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id, 718 unsigned int freq, 719 int dir) 720 { 721 struct snd_soc_codec *codec = dai->codec; 722 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec); 723 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1); 724 725 if (freq > 33000000) { 726 dev_err(codec->dev, "MCLK must be <33MHz\n"); 727 return -EINVAL; 728 } 729 730 if (freq > 16500000) { 731 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq); 732 reg |= WM8961_MCLKDIV; 733 freq /= 2; 734 } else { 735 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq); 736 reg &= ~WM8961_MCLKDIV; 737 } 738 739 snd_soc_write(codec, WM8961_CLOCKING1, reg); 740 741 wm8961->sysclk = freq; 742 743 return 0; 744 } 745 746 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 747 { 748 struct snd_soc_codec *codec = dai->codec; 749 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0); 750 751 aif &= ~(WM8961_BCLKINV | WM8961_LRP | 752 WM8961_MS | WM8961_FORMAT_MASK); 753 754 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 755 case SND_SOC_DAIFMT_CBM_CFM: 756 aif |= WM8961_MS; 757 break; 758 case SND_SOC_DAIFMT_CBS_CFS: 759 break; 760 default: 761 return -EINVAL; 762 } 763 764 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 765 case SND_SOC_DAIFMT_RIGHT_J: 766 break; 767 768 case SND_SOC_DAIFMT_LEFT_J: 769 aif |= 1; 770 break; 771 772 case SND_SOC_DAIFMT_I2S: 773 aif |= 2; 774 break; 775 776 case SND_SOC_DAIFMT_DSP_B: 777 aif |= WM8961_LRP; 778 case SND_SOC_DAIFMT_DSP_A: 779 aif |= 3; 780 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 781 case SND_SOC_DAIFMT_NB_NF: 782 case SND_SOC_DAIFMT_IB_NF: 783 break; 784 default: 785 return -EINVAL; 786 } 787 break; 788 789 default: 790 return -EINVAL; 791 } 792 793 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 794 case SND_SOC_DAIFMT_NB_NF: 795 break; 796 case SND_SOC_DAIFMT_NB_IF: 797 aif |= WM8961_LRP; 798 break; 799 case SND_SOC_DAIFMT_IB_NF: 800 aif |= WM8961_BCLKINV; 801 break; 802 case SND_SOC_DAIFMT_IB_IF: 803 aif |= WM8961_BCLKINV | WM8961_LRP; 804 break; 805 default: 806 return -EINVAL; 807 } 808 809 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif); 810 } 811 812 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) 813 { 814 struct snd_soc_codec *codec = dai->codec; 815 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2); 816 817 if (tristate) 818 reg |= WM8961_TRIS; 819 else 820 reg &= ~WM8961_TRIS; 821 822 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg); 823 } 824 825 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) 826 { 827 struct snd_soc_codec *codec = dai->codec; 828 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1); 829 830 if (mute) 831 reg |= WM8961_DACMU; 832 else 833 reg &= ~WM8961_DACMU; 834 835 msleep(17); 836 837 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg); 838 } 839 840 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 841 { 842 struct snd_soc_codec *codec = dai->codec; 843 u16 reg; 844 845 switch (div_id) { 846 case WM8961_BCLK: 847 reg = snd_soc_read(codec, WM8961_CLOCKING2); 848 reg &= ~WM8961_BCLKDIV_MASK; 849 reg |= div; 850 snd_soc_write(codec, WM8961_CLOCKING2, reg); 851 break; 852 853 case WM8961_LRCLK: 854 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2); 855 reg &= ~WM8961_LRCLK_RATE_MASK; 856 reg |= div; 857 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg); 858 break; 859 860 default: 861 return -EINVAL; 862 } 863 864 return 0; 865 } 866 867 static int wm8961_set_bias_level(struct snd_soc_codec *codec, 868 enum snd_soc_bias_level level) 869 { 870 u16 reg; 871 872 /* This is all slightly unusual since we have no bypass paths 873 * and the output amplifier structure means we can just slam 874 * the biases straight up rather than having to ramp them 875 * slowly. 876 */ 877 switch (level) { 878 case SND_SOC_BIAS_ON: 879 break; 880 881 case SND_SOC_BIAS_PREPARE: 882 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 883 /* Enable bias generation */ 884 reg = snd_soc_read(codec, WM8961_ANTI_POP); 885 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; 886 snd_soc_write(codec, WM8961_ANTI_POP, reg); 887 888 /* VMID=2*50k, VREF */ 889 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); 890 reg &= ~WM8961_VMIDSEL_MASK; 891 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; 892 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); 893 } 894 break; 895 896 case SND_SOC_BIAS_STANDBY: 897 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) { 898 /* VREF off */ 899 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); 900 reg &= ~WM8961_VREF; 901 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); 902 903 /* Bias generation off */ 904 reg = snd_soc_read(codec, WM8961_ANTI_POP); 905 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); 906 snd_soc_write(codec, WM8961_ANTI_POP, reg); 907 908 /* VMID off */ 909 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); 910 reg &= ~WM8961_VMIDSEL_MASK; 911 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg); 912 } 913 break; 914 915 case SND_SOC_BIAS_OFF: 916 break; 917 } 918 919 codec->dapm.bias_level = level; 920 921 return 0; 922 } 923 924 925 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000 926 927 #define WM8961_FORMATS \ 928 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 929 SNDRV_PCM_FMTBIT_S24_LE) 930 931 static const struct snd_soc_dai_ops wm8961_dai_ops = { 932 .hw_params = wm8961_hw_params, 933 .set_sysclk = wm8961_set_sysclk, 934 .set_fmt = wm8961_set_fmt, 935 .digital_mute = wm8961_digital_mute, 936 .set_tristate = wm8961_set_tristate, 937 .set_clkdiv = wm8961_set_clkdiv, 938 }; 939 940 static struct snd_soc_dai_driver wm8961_dai = { 941 .name = "wm8961-hifi", 942 .playback = { 943 .stream_name = "HiFi Playback", 944 .channels_min = 1, 945 .channels_max = 2, 946 .rates = WM8961_RATES, 947 .formats = WM8961_FORMATS,}, 948 .capture = { 949 .stream_name = "HiFi Capture", 950 .channels_min = 1, 951 .channels_max = 2, 952 .rates = WM8961_RATES, 953 .formats = WM8961_FORMATS,}, 954 .ops = &wm8961_dai_ops, 955 }; 956 957 static int wm8961_probe(struct snd_soc_codec *codec) 958 { 959 struct snd_soc_dapm_context *dapm = &codec->dapm; 960 int ret = 0; 961 u16 reg; 962 963 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 964 if (ret != 0) { 965 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 966 return ret; 967 } 968 969 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET); 970 if (reg != 0x1801) { 971 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg); 972 return -EINVAL; 973 } 974 975 /* This isn't volatile - readback doesn't correspond to write */ 976 codec->cache_bypass = 1; 977 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME); 978 codec->cache_bypass = 0; 979 dev_info(codec->dev, "WM8961 family %d revision %c\n", 980 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, 981 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) 982 + 'A'); 983 984 ret = wm8961_reset(codec); 985 if (ret < 0) { 986 dev_err(codec->dev, "Failed to issue reset\n"); 987 return ret; 988 } 989 990 /* Enable class W */ 991 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B); 992 reg |= WM8961_CP_DYN_PWR_MASK; 993 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg); 994 995 /* Latch volume update bits (right channel only, we always 996 * write both out) and default ZC on. */ 997 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME); 998 snd_soc_write(codec, WM8961_ROUT1_VOLUME, 999 reg | WM8961_LO1ZC | WM8961_OUT1VU); 1000 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); 1001 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME); 1002 snd_soc_write(codec, WM8961_ROUT2_VOLUME, 1003 reg | WM8961_SPKRZC | WM8961_SPKVU); 1004 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); 1005 1006 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME); 1007 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); 1008 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME); 1009 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); 1010 1011 /* Use soft mute by default */ 1012 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2); 1013 reg |= WM8961_DACSMM; 1014 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 1015 1016 /* Use automatic clocking mode by default; for now this is all 1017 * we support. 1018 */ 1019 reg = snd_soc_read(codec, WM8961_CLOCKING_3); 1020 reg &= ~WM8961_MANUAL_MODE; 1021 snd_soc_write(codec, WM8961_CLOCKING_3, reg); 1022 1023 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1024 1025 snd_soc_add_controls(codec, wm8961_snd_controls, 1026 ARRAY_SIZE(wm8961_snd_controls)); 1027 snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets, 1028 ARRAY_SIZE(wm8961_dapm_widgets)); 1029 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); 1030 1031 return 0; 1032 } 1033 1034 static int wm8961_remove(struct snd_soc_codec *codec) 1035 { 1036 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF); 1037 return 0; 1038 } 1039 1040 #ifdef CONFIG_PM 1041 static int wm8961_suspend(struct snd_soc_codec *codec) 1042 { 1043 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF); 1044 1045 return 0; 1046 } 1047 1048 static int wm8961_resume(struct snd_soc_codec *codec) 1049 { 1050 snd_soc_cache_sync(codec); 1051 1052 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1053 1054 return 0; 1055 } 1056 #else 1057 #define wm8961_suspend NULL 1058 #define wm8961_resume NULL 1059 #endif 1060 1061 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = { 1062 .probe = wm8961_probe, 1063 .remove = wm8961_remove, 1064 .suspend = wm8961_suspend, 1065 .resume = wm8961_resume, 1066 .set_bias_level = wm8961_set_bias_level, 1067 .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults), 1068 .reg_word_size = sizeof(u16), 1069 .reg_cache_default = wm8961_reg_defaults, 1070 .volatile_register = wm8961_volatile_register, 1071 }; 1072 1073 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c, 1074 const struct i2c_device_id *id) 1075 { 1076 struct wm8961_priv *wm8961; 1077 int ret; 1078 1079 wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv), 1080 GFP_KERNEL); 1081 if (wm8961 == NULL) 1082 return -ENOMEM; 1083 1084 i2c_set_clientdata(i2c, wm8961); 1085 1086 ret = snd_soc_register_codec(&i2c->dev, 1087 &soc_codec_dev_wm8961, &wm8961_dai, 1); 1088 1089 return ret; 1090 } 1091 1092 static __devexit int wm8961_i2c_remove(struct i2c_client *client) 1093 { 1094 snd_soc_unregister_codec(&client->dev); 1095 1096 return 0; 1097 } 1098 1099 static const struct i2c_device_id wm8961_i2c_id[] = { 1100 { "wm8961", 0 }, 1101 { } 1102 }; 1103 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id); 1104 1105 static struct i2c_driver wm8961_i2c_driver = { 1106 .driver = { 1107 .name = "wm8961", 1108 .owner = THIS_MODULE, 1109 }, 1110 .probe = wm8961_i2c_probe, 1111 .remove = __devexit_p(wm8961_i2c_remove), 1112 .id_table = wm8961_i2c_id, 1113 }; 1114 1115 static int __init wm8961_modinit(void) 1116 { 1117 int ret = 0; 1118 ret = i2c_add_driver(&wm8961_i2c_driver); 1119 if (ret != 0) { 1120 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n", 1121 ret); 1122 } 1123 return ret; 1124 } 1125 module_init(wm8961_modinit); 1126 1127 static void __exit wm8961_exit(void) 1128 { 1129 i2c_del_driver(&wm8961_i2c_driver); 1130 } 1131 module_exit(wm8961_exit); 1132 1133 MODULE_DESCRIPTION("ASoC WM8961 driver"); 1134 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1135 MODULE_LICENSE("GPL"); 1136