1 /* 2 * wm8904.h -- WM8904 ASoC driver 3 * 4 * Copyright 2009 Wolfson Microelectronics, plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef _WM8904_H 14 #define _WM8904_H 15 16 #define WM8904_CLK_MCLK 1 17 #define WM8904_CLK_FLL 2 18 19 #define WM8904_FLL_MCLK 1 20 #define WM8904_FLL_BCLK 2 21 #define WM8904_FLL_LRCLK 3 22 #define WM8904_FLL_FREE_RUNNING 4 23 24 extern struct snd_soc_dai wm8904_dai; 25 extern struct snd_soc_codec_device soc_codec_dev_wm8904; 26 27 /* 28 * Register values. 29 */ 30 #define WM8904_SW_RESET_AND_ID 0x00 31 #define WM8904_REVISION 0x01 32 #define WM8904_BIAS_CONTROL_0 0x04 33 #define WM8904_VMID_CONTROL_0 0x05 34 #define WM8904_MIC_BIAS_CONTROL_0 0x06 35 #define WM8904_MIC_BIAS_CONTROL_1 0x07 36 #define WM8904_ANALOGUE_DAC_0 0x08 37 #define WM8904_MIC_FILTER_CONTROL 0x09 38 #define WM8904_ANALOGUE_ADC_0 0x0A 39 #define WM8904_POWER_MANAGEMENT_0 0x0C 40 #define WM8904_POWER_MANAGEMENT_2 0x0E 41 #define WM8904_POWER_MANAGEMENT_3 0x0F 42 #define WM8904_POWER_MANAGEMENT_6 0x12 43 #define WM8904_CLOCK_RATES_0 0x14 44 #define WM8904_CLOCK_RATES_1 0x15 45 #define WM8904_CLOCK_RATES_2 0x16 46 #define WM8904_AUDIO_INTERFACE_0 0x18 47 #define WM8904_AUDIO_INTERFACE_1 0x19 48 #define WM8904_AUDIO_INTERFACE_2 0x1A 49 #define WM8904_AUDIO_INTERFACE_3 0x1B 50 #define WM8904_DAC_DIGITAL_VOLUME_LEFT 0x1E 51 #define WM8904_DAC_DIGITAL_VOLUME_RIGHT 0x1F 52 #define WM8904_DAC_DIGITAL_0 0x20 53 #define WM8904_DAC_DIGITAL_1 0x21 54 #define WM8904_ADC_DIGITAL_VOLUME_LEFT 0x24 55 #define WM8904_ADC_DIGITAL_VOLUME_RIGHT 0x25 56 #define WM8904_ADC_DIGITAL_0 0x26 57 #define WM8904_DIGITAL_MICROPHONE_0 0x27 58 #define WM8904_DRC_0 0x28 59 #define WM8904_DRC_1 0x29 60 #define WM8904_DRC_2 0x2A 61 #define WM8904_DRC_3 0x2B 62 #define WM8904_ANALOGUE_LEFT_INPUT_0 0x2C 63 #define WM8904_ANALOGUE_RIGHT_INPUT_0 0x2D 64 #define WM8904_ANALOGUE_LEFT_INPUT_1 0x2E 65 #define WM8904_ANALOGUE_RIGHT_INPUT_1 0x2F 66 #define WM8904_ANALOGUE_OUT1_LEFT 0x39 67 #define WM8904_ANALOGUE_OUT1_RIGHT 0x3A 68 #define WM8904_ANALOGUE_OUT2_LEFT 0x3B 69 #define WM8904_ANALOGUE_OUT2_RIGHT 0x3C 70 #define WM8904_ANALOGUE_OUT12_ZC 0x3D 71 #define WM8904_DC_SERVO_0 0x43 72 #define WM8904_DC_SERVO_1 0x44 73 #define WM8904_DC_SERVO_2 0x45 74 #define WM8904_DC_SERVO_4 0x47 75 #define WM8904_DC_SERVO_5 0x48 76 #define WM8904_DC_SERVO_6 0x49 77 #define WM8904_DC_SERVO_7 0x4A 78 #define WM8904_DC_SERVO_8 0x4B 79 #define WM8904_DC_SERVO_9 0x4C 80 #define WM8904_DC_SERVO_READBACK_0 0x4D 81 #define WM8904_ANALOGUE_HP_0 0x5A 82 #define WM8904_ANALOGUE_LINEOUT_0 0x5E 83 #define WM8904_CHARGE_PUMP_0 0x62 84 #define WM8904_CLASS_W_0 0x68 85 #define WM8904_WRITE_SEQUENCER_0 0x6C 86 #define WM8904_WRITE_SEQUENCER_1 0x6D 87 #define WM8904_WRITE_SEQUENCER_2 0x6E 88 #define WM8904_WRITE_SEQUENCER_3 0x6F 89 #define WM8904_WRITE_SEQUENCER_4 0x70 90 #define WM8904_FLL_CONTROL_1 0x74 91 #define WM8904_FLL_CONTROL_2 0x75 92 #define WM8904_FLL_CONTROL_3 0x76 93 #define WM8904_FLL_CONTROL_4 0x77 94 #define WM8904_FLL_CONTROL_5 0x78 95 #define WM8904_GPIO_CONTROL_1 0x79 96 #define WM8904_GPIO_CONTROL_2 0x7A 97 #define WM8904_GPIO_CONTROL_3 0x7B 98 #define WM8904_GPIO_CONTROL_4 0x7C 99 #define WM8904_DIGITAL_PULLS 0x7E 100 #define WM8904_INTERRUPT_STATUS 0x7F 101 #define WM8904_INTERRUPT_STATUS_MASK 0x80 102 #define WM8904_INTERRUPT_POLARITY 0x81 103 #define WM8904_INTERRUPT_DEBOUNCE 0x82 104 #define WM8904_EQ1 0x86 105 #define WM8904_EQ2 0x87 106 #define WM8904_EQ3 0x88 107 #define WM8904_EQ4 0x89 108 #define WM8904_EQ5 0x8A 109 #define WM8904_EQ6 0x8B 110 #define WM8904_EQ7 0x8C 111 #define WM8904_EQ8 0x8D 112 #define WM8904_EQ9 0x8E 113 #define WM8904_EQ10 0x8F 114 #define WM8904_EQ11 0x90 115 #define WM8904_EQ12 0x91 116 #define WM8904_EQ13 0x92 117 #define WM8904_EQ14 0x93 118 #define WM8904_EQ15 0x94 119 #define WM8904_EQ16 0x95 120 #define WM8904_EQ17 0x96 121 #define WM8904_EQ18 0x97 122 #define WM8904_EQ19 0x98 123 #define WM8904_EQ20 0x99 124 #define WM8904_EQ21 0x9A 125 #define WM8904_EQ22 0x9B 126 #define WM8904_EQ23 0x9C 127 #define WM8904_EQ24 0x9D 128 #define WM8904_CONTROL_INTERFACE_TEST_1 0xA1 129 #define WM8904_ANALOGUE_OUTPUT_BIAS_0 0xCC 130 #define WM8904_FLL_NCO_TEST_0 0xF7 131 #define WM8904_FLL_NCO_TEST_1 0xF8 132 133 #define WM8904_REGISTER_COUNT 101 134 #define WM8904_MAX_REGISTER 0xF8 135 136 /* 137 * Field Definitions. 138 */ 139 140 /* 141 * R0 (0x00) - SW Reset and ID 142 */ 143 #define WM8904_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 144 #define WM8904_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 145 #define WM8904_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 146 147 /* 148 * R1 (0x01) - Revision 149 */ 150 #define WM8904_REVISION_MASK 0x000F /* REVISION - [3:0] */ 151 #define WM8904_REVISION_SHIFT 0 /* REVISION - [3:0] */ 152 #define WM8904_REVISION_WIDTH 16 /* REVISION - [3:0] */ 153 154 /* 155 * R4 (0x04) - Bias Control 0 156 */ 157 #define WM8904_POBCTRL 0x0010 /* POBCTRL */ 158 #define WM8904_POBCTRL_MASK 0x0010 /* POBCTRL */ 159 #define WM8904_POBCTRL_SHIFT 4 /* POBCTRL */ 160 #define WM8904_POBCTRL_WIDTH 1 /* POBCTRL */ 161 #define WM8904_ISEL_MASK 0x000C /* ISEL - [3:2] */ 162 #define WM8904_ISEL_SHIFT 2 /* ISEL - [3:2] */ 163 #define WM8904_ISEL_WIDTH 2 /* ISEL - [3:2] */ 164 #define WM8904_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ 165 #define WM8904_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ 166 #define WM8904_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ 167 #define WM8904_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 168 #define WM8904_BIAS_ENA 0x0001 /* BIAS_ENA */ 169 #define WM8904_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 170 #define WM8904_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 171 #define WM8904_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 172 173 /* 174 * R5 (0x05) - VMID Control 0 175 */ 176 #define WM8904_VMID_BUF_ENA 0x0040 /* VMID_BUF_ENA */ 177 #define WM8904_VMID_BUF_ENA_MASK 0x0040 /* VMID_BUF_ENA */ 178 #define WM8904_VMID_BUF_ENA_SHIFT 6 /* VMID_BUF_ENA */ 179 #define WM8904_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 180 #define WM8904_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 181 #define WM8904_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 182 #define WM8904_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 183 #define WM8904_VMID_ENA 0x0001 /* VMID_ENA */ 184 #define WM8904_VMID_ENA_MASK 0x0001 /* VMID_ENA */ 185 #define WM8904_VMID_ENA_SHIFT 0 /* VMID_ENA */ 186 #define WM8904_VMID_ENA_WIDTH 1 /* VMID_ENA */ 187 188 /* 189 * R6 (0x06) - Mic Bias Control 0 190 */ 191 #define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ 192 #define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ 193 #define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ 194 #define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ 195 #define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ 196 #define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ 197 #define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */ 198 #define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ 199 #define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ 200 #define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ 201 #define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ 202 #define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ 203 #define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ 204 #define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ 205 206 /* 207 * R7 (0x07) - Mic Bias Control 1 208 */ 209 #define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */ 210 #define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */ 211 #define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */ 212 #define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */ 213 #define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */ 214 #define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */ 215 #define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */ 216 #define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */ 217 #define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */ 218 #define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */ 219 #define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */ 220 221 /* 222 * R8 (0x08) - Analogue DAC 0 223 */ 224 #define WM8904_DAC_BIAS_SEL_MASK 0x0018 /* DAC_BIAS_SEL - [4:3] */ 225 #define WM8904_DAC_BIAS_SEL_SHIFT 3 /* DAC_BIAS_SEL - [4:3] */ 226 #define WM8904_DAC_BIAS_SEL_WIDTH 2 /* DAC_BIAS_SEL - [4:3] */ 227 #define WM8904_DAC_VMID_BIAS_SEL_MASK 0x0006 /* DAC_VMID_BIAS_SEL - [2:1] */ 228 #define WM8904_DAC_VMID_BIAS_SEL_SHIFT 1 /* DAC_VMID_BIAS_SEL - [2:1] */ 229 #define WM8904_DAC_VMID_BIAS_SEL_WIDTH 2 /* DAC_VMID_BIAS_SEL - [2:1] */ 230 231 /* 232 * R9 (0x09) - mic Filter Control 233 */ 234 #define WM8904_MIC_DET_SET_THRESHOLD_MASK 0xF000 /* MIC_DET_SET_THRESHOLD - [15:12] */ 235 #define WM8904_MIC_DET_SET_THRESHOLD_SHIFT 12 /* MIC_DET_SET_THRESHOLD - [15:12] */ 236 #define WM8904_MIC_DET_SET_THRESHOLD_WIDTH 4 /* MIC_DET_SET_THRESHOLD - [15:12] */ 237 #define WM8904_MIC_DET_RESET_THRESHOLD_MASK 0x0F00 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 238 #define WM8904_MIC_DET_RESET_THRESHOLD_SHIFT 8 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 239 #define WM8904_MIC_DET_RESET_THRESHOLD_WIDTH 4 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 240 #define WM8904_MIC_SHORT_SET_THRESHOLD_MASK 0x00F0 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 241 #define WM8904_MIC_SHORT_SET_THRESHOLD_SHIFT 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 242 #define WM8904_MIC_SHORT_SET_THRESHOLD_WIDTH 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 243 #define WM8904_MIC_SHORT_RESET_THRESHOLD_MASK 0x000F /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 244 #define WM8904_MIC_SHORT_RESET_THRESHOLD_SHIFT 0 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 245 #define WM8904_MIC_SHORT_RESET_THRESHOLD_WIDTH 4 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 246 247 /* 248 * R10 (0x0A) - Analogue ADC 0 249 */ 250 #define WM8904_ADC_OSR128 0x0001 /* ADC_OSR128 */ 251 #define WM8904_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ 252 #define WM8904_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ 253 #define WM8904_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 254 255 /* 256 * R12 (0x0C) - Power Management 0 257 */ 258 #define WM8904_INL_ENA 0x0002 /* INL_ENA */ 259 #define WM8904_INL_ENA_MASK 0x0002 /* INL_ENA */ 260 #define WM8904_INL_ENA_SHIFT 1 /* INL_ENA */ 261 #define WM8904_INL_ENA_WIDTH 1 /* INL_ENA */ 262 #define WM8904_INR_ENA 0x0001 /* INR_ENA */ 263 #define WM8904_INR_ENA_MASK 0x0001 /* INR_ENA */ 264 #define WM8904_INR_ENA_SHIFT 0 /* INR_ENA */ 265 #define WM8904_INR_ENA_WIDTH 1 /* INR_ENA */ 266 267 /* 268 * R14 (0x0E) - Power Management 2 269 */ 270 #define WM8904_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ 271 #define WM8904_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ 272 #define WM8904_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ 273 #define WM8904_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ 274 #define WM8904_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ 275 #define WM8904_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ 276 #define WM8904_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ 277 #define WM8904_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ 278 279 /* 280 * R15 (0x0F) - Power Management 3 281 */ 282 #define WM8904_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ 283 #define WM8904_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ 284 #define WM8904_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ 285 #define WM8904_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ 286 #define WM8904_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ 287 #define WM8904_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ 288 #define WM8904_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ 289 #define WM8904_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ 290 291 /* 292 * R18 (0x12) - Power Management 6 293 */ 294 #define WM8904_DACL_ENA 0x0008 /* DACL_ENA */ 295 #define WM8904_DACL_ENA_MASK 0x0008 /* DACL_ENA */ 296 #define WM8904_DACL_ENA_SHIFT 3 /* DACL_ENA */ 297 #define WM8904_DACL_ENA_WIDTH 1 /* DACL_ENA */ 298 #define WM8904_DACR_ENA 0x0004 /* DACR_ENA */ 299 #define WM8904_DACR_ENA_MASK 0x0004 /* DACR_ENA */ 300 #define WM8904_DACR_ENA_SHIFT 2 /* DACR_ENA */ 301 #define WM8904_DACR_ENA_WIDTH 1 /* DACR_ENA */ 302 #define WM8904_ADCL_ENA 0x0002 /* ADCL_ENA */ 303 #define WM8904_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 304 #define WM8904_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 305 #define WM8904_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 306 #define WM8904_ADCR_ENA 0x0001 /* ADCR_ENA */ 307 #define WM8904_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 308 #define WM8904_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 309 #define WM8904_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 310 311 /* 312 * R20 (0x14) - Clock Rates 0 313 */ 314 #define WM8904_TOCLK_RATE_DIV16 0x4000 /* TOCLK_RATE_DIV16 */ 315 #define WM8904_TOCLK_RATE_DIV16_MASK 0x4000 /* TOCLK_RATE_DIV16 */ 316 #define WM8904_TOCLK_RATE_DIV16_SHIFT 14 /* TOCLK_RATE_DIV16 */ 317 #define WM8904_TOCLK_RATE_DIV16_WIDTH 1 /* TOCLK_RATE_DIV16 */ 318 #define WM8904_TOCLK_RATE_X4 0x2000 /* TOCLK_RATE_X4 */ 319 #define WM8904_TOCLK_RATE_X4_MASK 0x2000 /* TOCLK_RATE_X4 */ 320 #define WM8904_TOCLK_RATE_X4_SHIFT 13 /* TOCLK_RATE_X4 */ 321 #define WM8904_TOCLK_RATE_X4_WIDTH 1 /* TOCLK_RATE_X4 */ 322 #define WM8904_SR_MODE 0x1000 /* SR_MODE */ 323 #define WM8904_SR_MODE_MASK 0x1000 /* SR_MODE */ 324 #define WM8904_SR_MODE_SHIFT 12 /* SR_MODE */ 325 #define WM8904_SR_MODE_WIDTH 1 /* SR_MODE */ 326 #define WM8904_MCLK_DIV 0x0001 /* MCLK_DIV */ 327 #define WM8904_MCLK_DIV_MASK 0x0001 /* MCLK_DIV */ 328 #define WM8904_MCLK_DIV_SHIFT 0 /* MCLK_DIV */ 329 #define WM8904_MCLK_DIV_WIDTH 1 /* MCLK_DIV */ 330 331 /* 332 * R21 (0x15) - Clock Rates 1 333 */ 334 #define WM8904_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ 335 #define WM8904_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ 336 #define WM8904_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ 337 #define WM8904_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 338 #define WM8904_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 339 #define WM8904_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 340 341 /* 342 * R22 (0x16) - Clock Rates 2 343 */ 344 #define WM8904_MCLK_INV 0x8000 /* MCLK_INV */ 345 #define WM8904_MCLK_INV_MASK 0x8000 /* MCLK_INV */ 346 #define WM8904_MCLK_INV_SHIFT 15 /* MCLK_INV */ 347 #define WM8904_MCLK_INV_WIDTH 1 /* MCLK_INV */ 348 #define WM8904_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ 349 #define WM8904_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */ 350 #define WM8904_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */ 351 #define WM8904_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 352 #define WM8904_TOCLK_RATE 0x1000 /* TOCLK_RATE */ 353 #define WM8904_TOCLK_RATE_MASK 0x1000 /* TOCLK_RATE */ 354 #define WM8904_TOCLK_RATE_SHIFT 12 /* TOCLK_RATE */ 355 #define WM8904_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */ 356 #define WM8904_OPCLK_ENA 0x0008 /* OPCLK_ENA */ 357 #define WM8904_OPCLK_ENA_MASK 0x0008 /* OPCLK_ENA */ 358 #define WM8904_OPCLK_ENA_SHIFT 3 /* OPCLK_ENA */ 359 #define WM8904_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 360 #define WM8904_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ 361 #define WM8904_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ 362 #define WM8904_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ 363 #define WM8904_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 364 #define WM8904_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 365 #define WM8904_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 366 #define WM8904_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 367 #define WM8904_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 368 #define WM8904_TOCLK_ENA 0x0001 /* TOCLK_ENA */ 369 #define WM8904_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */ 370 #define WM8904_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */ 371 #define WM8904_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 372 373 /* 374 * R24 (0x18) - Audio Interface 0 375 */ 376 #define WM8904_DACL_DATINV 0x1000 /* DACL_DATINV */ 377 #define WM8904_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ 378 #define WM8904_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ 379 #define WM8904_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ 380 #define WM8904_DACR_DATINV 0x0800 /* DACR_DATINV */ 381 #define WM8904_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ 382 #define WM8904_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ 383 #define WM8904_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ 384 #define WM8904_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ 385 #define WM8904_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ 386 #define WM8904_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ 387 #define WM8904_LOOPBACK 0x0100 /* LOOPBACK */ 388 #define WM8904_LOOPBACK_MASK 0x0100 /* LOOPBACK */ 389 #define WM8904_LOOPBACK_SHIFT 8 /* LOOPBACK */ 390 #define WM8904_LOOPBACK_WIDTH 1 /* LOOPBACK */ 391 #define WM8904_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ 392 #define WM8904_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ 393 #define WM8904_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ 394 #define WM8904_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ 395 #define WM8904_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ 396 #define WM8904_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ 397 #define WM8904_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ 398 #define WM8904_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ 399 #define WM8904_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ 400 #define WM8904_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ 401 #define WM8904_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ 402 #define WM8904_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ 403 #define WM8904_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ 404 #define WM8904_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ 405 #define WM8904_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ 406 #define WM8904_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ 407 #define WM8904_ADC_COMP 0x0008 /* ADC_COMP */ 408 #define WM8904_ADC_COMP_MASK 0x0008 /* ADC_COMP */ 409 #define WM8904_ADC_COMP_SHIFT 3 /* ADC_COMP */ 410 #define WM8904_ADC_COMP_WIDTH 1 /* ADC_COMP */ 411 #define WM8904_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ 412 #define WM8904_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ 413 #define WM8904_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ 414 #define WM8904_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 415 #define WM8904_DAC_COMP 0x0002 /* DAC_COMP */ 416 #define WM8904_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 417 #define WM8904_DAC_COMP_SHIFT 1 /* DAC_COMP */ 418 #define WM8904_DAC_COMP_WIDTH 1 /* DAC_COMP */ 419 #define WM8904_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 420 #define WM8904_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 421 #define WM8904_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 422 #define WM8904_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 423 424 /* 425 * R25 (0x19) - Audio Interface 1 426 */ 427 #define WM8904_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 428 #define WM8904_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ 429 #define WM8904_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ 430 #define WM8904_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ 431 #define WM8904_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 432 #define WM8904_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ 433 #define WM8904_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ 434 #define WM8904_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ 435 #define WM8904_AIFADC_TDM 0x0800 /* AIFADC_TDM */ 436 #define WM8904_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ 437 #define WM8904_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ 438 #define WM8904_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ 439 #define WM8904_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ 440 #define WM8904_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ 441 #define WM8904_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ 442 #define WM8904_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ 443 #define WM8904_AIF_TRIS 0x0100 /* AIF_TRIS */ 444 #define WM8904_AIF_TRIS_MASK 0x0100 /* AIF_TRIS */ 445 #define WM8904_AIF_TRIS_SHIFT 8 /* AIF_TRIS */ 446 #define WM8904_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ 447 #define WM8904_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 448 #define WM8904_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 449 #define WM8904_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 450 #define WM8904_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 451 #define WM8904_BCLK_DIR 0x0040 /* BCLK_DIR */ 452 #define WM8904_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 453 #define WM8904_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 454 #define WM8904_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 455 #define WM8904_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 456 #define WM8904_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 457 #define WM8904_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 458 #define WM8904_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 459 #define WM8904_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 460 #define WM8904_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 461 #define WM8904_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 462 #define WM8904_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 463 #define WM8904_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 464 #define WM8904_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 465 466 /* 467 * R26 (0x1A) - Audio Interface 2 468 */ 469 #define WM8904_OPCLK_DIV_MASK 0x0F00 /* OPCLK_DIV - [11:8] */ 470 #define WM8904_OPCLK_DIV_SHIFT 8 /* OPCLK_DIV - [11:8] */ 471 #define WM8904_OPCLK_DIV_WIDTH 4 /* OPCLK_DIV - [11:8] */ 472 #define WM8904_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 473 #define WM8904_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 474 #define WM8904_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 475 476 /* 477 * R27 (0x1B) - Audio Interface 3 478 */ 479 #define WM8904_LRCLK_DIR 0x0800 /* LRCLK_DIR */ 480 #define WM8904_LRCLK_DIR_MASK 0x0800 /* LRCLK_DIR */ 481 #define WM8904_LRCLK_DIR_SHIFT 11 /* LRCLK_DIR */ 482 #define WM8904_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 483 #define WM8904_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 484 #define WM8904_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 485 #define WM8904_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 486 487 /* 488 * R30 (0x1E) - DAC Digital Volume Left 489 */ 490 #define WM8904_DAC_VU 0x0100 /* DAC_VU */ 491 #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ 492 #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ 493 #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ 494 #define WM8904_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 495 #define WM8904_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 496 #define WM8904_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 497 498 /* 499 * R31 (0x1F) - DAC Digital Volume Right 500 */ 501 #define WM8904_DAC_VU 0x0100 /* DAC_VU */ 502 #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ 503 #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ 504 #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ 505 #define WM8904_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 506 #define WM8904_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 507 #define WM8904_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 508 509 /* 510 * R32 (0x20) - DAC Digital 0 511 */ 512 #define WM8904_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ 513 #define WM8904_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ 514 #define WM8904_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ 515 #define WM8904_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 516 #define WM8904_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 517 #define WM8904_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 518 #define WM8904_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 519 #define WM8904_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 520 #define WM8904_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 521 #define WM8904_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ 522 #define WM8904_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ 523 #define WM8904_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ 524 525 /* 526 * R33 (0x21) - DAC Digital 1 527 */ 528 #define WM8904_DAC_MONO 0x1000 /* DAC_MONO */ 529 #define WM8904_DAC_MONO_MASK 0x1000 /* DAC_MONO */ 530 #define WM8904_DAC_MONO_SHIFT 12 /* DAC_MONO */ 531 #define WM8904_DAC_MONO_WIDTH 1 /* DAC_MONO */ 532 #define WM8904_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ 533 #define WM8904_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ 534 #define WM8904_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ 535 #define WM8904_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ 536 #define WM8904_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 537 #define WM8904_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 538 #define WM8904_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 539 #define WM8904_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 540 #define WM8904_DAC_UNMUTE_RAMP 0x0200 /* DAC_UNMUTE_RAMP */ 541 #define WM8904_DAC_UNMUTE_RAMP_MASK 0x0200 /* DAC_UNMUTE_RAMP */ 542 #define WM8904_DAC_UNMUTE_RAMP_SHIFT 9 /* DAC_UNMUTE_RAMP */ 543 #define WM8904_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */ 544 #define WM8904_DAC_OSR128 0x0040 /* DAC_OSR128 */ 545 #define WM8904_DAC_OSR128_MASK 0x0040 /* DAC_OSR128 */ 546 #define WM8904_DAC_OSR128_SHIFT 6 /* DAC_OSR128 */ 547 #define WM8904_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 548 #define WM8904_DAC_MUTE 0x0008 /* DAC_MUTE */ 549 #define WM8904_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 550 #define WM8904_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 551 #define WM8904_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 552 #define WM8904_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 553 #define WM8904_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 554 #define WM8904_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 555 556 /* 557 * R36 (0x24) - ADC Digital Volume Left 558 */ 559 #define WM8904_ADC_VU 0x0100 /* ADC_VU */ 560 #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ 561 #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ 562 #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ 563 #define WM8904_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 564 #define WM8904_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 565 #define WM8904_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 566 567 /* 568 * R37 (0x25) - ADC Digital Volume Right 569 */ 570 #define WM8904_ADC_VU 0x0100 /* ADC_VU */ 571 #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ 572 #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ 573 #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ 574 #define WM8904_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 575 #define WM8904_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 576 #define WM8904_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 577 578 /* 579 * R38 (0x26) - ADC Digital 0 580 */ 581 #define WM8904_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ 582 #define WM8904_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ 583 #define WM8904_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ 584 #define WM8904_ADC_HPF 0x0010 /* ADC_HPF */ 585 #define WM8904_ADC_HPF_MASK 0x0010 /* ADC_HPF */ 586 #define WM8904_ADC_HPF_SHIFT 4 /* ADC_HPF */ 587 #define WM8904_ADC_HPF_WIDTH 1 /* ADC_HPF */ 588 #define WM8904_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 589 #define WM8904_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ 590 #define WM8904_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ 591 #define WM8904_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ 592 #define WM8904_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 593 #define WM8904_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ 594 #define WM8904_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ 595 #define WM8904_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ 596 597 /* 598 * R39 (0x27) - Digital Microphone 0 599 */ 600 #define WM8904_DMIC_ENA 0x1000 /* DMIC_ENA */ 601 #define WM8904_DMIC_ENA_MASK 0x1000 /* DMIC_ENA */ 602 #define WM8904_DMIC_ENA_SHIFT 12 /* DMIC_ENA */ 603 #define WM8904_DMIC_ENA_WIDTH 1 /* DMIC_ENA */ 604 #define WM8904_DMIC_SRC 0x0800 /* DMIC_SRC */ 605 #define WM8904_DMIC_SRC_MASK 0x0800 /* DMIC_SRC */ 606 #define WM8904_DMIC_SRC_SHIFT 11 /* DMIC_SRC */ 607 #define WM8904_DMIC_SRC_WIDTH 1 /* DMIC_SRC */ 608 609 /* 610 * R40 (0x28) - DRC 0 611 */ 612 #define WM8904_DRC_ENA 0x8000 /* DRC_ENA */ 613 #define WM8904_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 614 #define WM8904_DRC_ENA_SHIFT 15 /* DRC_ENA */ 615 #define WM8904_DRC_ENA_WIDTH 1 /* DRC_ENA */ 616 #define WM8904_DRC_DAC_PATH 0x4000 /* DRC_DAC_PATH */ 617 #define WM8904_DRC_DAC_PATH_MASK 0x4000 /* DRC_DAC_PATH */ 618 #define WM8904_DRC_DAC_PATH_SHIFT 14 /* DRC_DAC_PATH */ 619 #define WM8904_DRC_DAC_PATH_WIDTH 1 /* DRC_DAC_PATH */ 620 #define WM8904_DRC_GS_HYST_LVL_MASK 0x1800 /* DRC_GS_HYST_LVL - [12:11] */ 621 #define WM8904_DRC_GS_HYST_LVL_SHIFT 11 /* DRC_GS_HYST_LVL - [12:11] */ 622 #define WM8904_DRC_GS_HYST_LVL_WIDTH 2 /* DRC_GS_HYST_LVL - [12:11] */ 623 #define WM8904_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 624 #define WM8904_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 625 #define WM8904_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 626 #define WM8904_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ 627 #define WM8904_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ 628 #define WM8904_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ 629 #define WM8904_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ 630 #define WM8904_DRC_GS_ENA 0x0008 /* DRC_GS_ENA */ 631 #define WM8904_DRC_GS_ENA_MASK 0x0008 /* DRC_GS_ENA */ 632 #define WM8904_DRC_GS_ENA_SHIFT 3 /* DRC_GS_ENA */ 633 #define WM8904_DRC_GS_ENA_WIDTH 1 /* DRC_GS_ENA */ 634 #define WM8904_DRC_QR 0x0004 /* DRC_QR */ 635 #define WM8904_DRC_QR_MASK 0x0004 /* DRC_QR */ 636 #define WM8904_DRC_QR_SHIFT 2 /* DRC_QR */ 637 #define WM8904_DRC_QR_WIDTH 1 /* DRC_QR */ 638 #define WM8904_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */ 639 #define WM8904_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */ 640 #define WM8904_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */ 641 #define WM8904_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 642 #define WM8904_DRC_GS_HYST 0x0001 /* DRC_GS_HYST */ 643 #define WM8904_DRC_GS_HYST_MASK 0x0001 /* DRC_GS_HYST */ 644 #define WM8904_DRC_GS_HYST_SHIFT 0 /* DRC_GS_HYST */ 645 #define WM8904_DRC_GS_HYST_WIDTH 1 /* DRC_GS_HYST */ 646 647 /* 648 * R41 (0x29) - DRC 1 649 */ 650 #define WM8904_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */ 651 #define WM8904_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */ 652 #define WM8904_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */ 653 #define WM8904_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */ 654 #define WM8904_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */ 655 #define WM8904_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */ 656 #define WM8904_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */ 657 #define WM8904_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */ 658 #define WM8904_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */ 659 #define WM8904_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */ 660 #define WM8904_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */ 661 #define WM8904_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */ 662 #define WM8904_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 663 #define WM8904_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 664 #define WM8904_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 665 #define WM8904_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 666 #define WM8904_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 667 #define WM8904_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 668 669 /* 670 * R42 (0x2A) - DRC 2 671 */ 672 #define WM8904_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 673 #define WM8904_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 674 #define WM8904_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 675 #define WM8904_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 676 #define WM8904_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 677 #define WM8904_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 678 679 /* 680 * R43 (0x2B) - DRC 3 681 */ 682 #define WM8904_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 683 #define WM8904_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 684 #define WM8904_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 685 #define WM8904_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 686 #define WM8904_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 687 #define WM8904_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 688 689 /* 690 * R44 (0x2C) - Analogue Left Input 0 691 */ 692 #define WM8904_LINMUTE 0x0080 /* LINMUTE */ 693 #define WM8904_LINMUTE_MASK 0x0080 /* LINMUTE */ 694 #define WM8904_LINMUTE_SHIFT 7 /* LINMUTE */ 695 #define WM8904_LINMUTE_WIDTH 1 /* LINMUTE */ 696 #define WM8904_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ 697 #define WM8904_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ 698 #define WM8904_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ 699 700 /* 701 * R45 (0x2D) - Analogue Right Input 0 702 */ 703 #define WM8904_RINMUTE 0x0080 /* RINMUTE */ 704 #define WM8904_RINMUTE_MASK 0x0080 /* RINMUTE */ 705 #define WM8904_RINMUTE_SHIFT 7 /* RINMUTE */ 706 #define WM8904_RINMUTE_WIDTH 1 /* RINMUTE */ 707 #define WM8904_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ 708 #define WM8904_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ 709 #define WM8904_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ 710 711 /* 712 * R46 (0x2E) - Analogue Left Input 1 713 */ 714 #define WM8904_INL_CM_ENA 0x0040 /* INL_CM_ENA */ 715 #define WM8904_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ 716 #define WM8904_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ 717 #define WM8904_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ 718 #define WM8904_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ 719 #define WM8904_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ 720 #define WM8904_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ 721 #define WM8904_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ 722 #define WM8904_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ 723 #define WM8904_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ 724 #define WM8904_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ 725 #define WM8904_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ 726 #define WM8904_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ 727 728 /* 729 * R47 (0x2F) - Analogue Right Input 1 730 */ 731 #define WM8904_INR_CM_ENA 0x0040 /* INR_CM_ENA */ 732 #define WM8904_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ 733 #define WM8904_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ 734 #define WM8904_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ 735 #define WM8904_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ 736 #define WM8904_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ 737 #define WM8904_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ 738 #define WM8904_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ 739 #define WM8904_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ 740 #define WM8904_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ 741 #define WM8904_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ 742 #define WM8904_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ 743 #define WM8904_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ 744 745 /* 746 * R57 (0x39) - Analogue OUT1 Left 747 */ 748 #define WM8904_HPOUTL_MUTE 0x0100 /* HPOUTL_MUTE */ 749 #define WM8904_HPOUTL_MUTE_MASK 0x0100 /* HPOUTL_MUTE */ 750 #define WM8904_HPOUTL_MUTE_SHIFT 8 /* HPOUTL_MUTE */ 751 #define WM8904_HPOUTL_MUTE_WIDTH 1 /* HPOUTL_MUTE */ 752 #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ 753 #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ 754 #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ 755 #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 756 #define WM8904_HPOUTLZC 0x0040 /* HPOUTLZC */ 757 #define WM8904_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ 758 #define WM8904_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ 759 #define WM8904_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ 760 #define WM8904_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ 761 #define WM8904_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ 762 #define WM8904_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ 763 764 /* 765 * R58 (0x3A) - Analogue OUT1 Right 766 */ 767 #define WM8904_HPOUTR_MUTE 0x0100 /* HPOUTR_MUTE */ 768 #define WM8904_HPOUTR_MUTE_MASK 0x0100 /* HPOUTR_MUTE */ 769 #define WM8904_HPOUTR_MUTE_SHIFT 8 /* HPOUTR_MUTE */ 770 #define WM8904_HPOUTR_MUTE_WIDTH 1 /* HPOUTR_MUTE */ 771 #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ 772 #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ 773 #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ 774 #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 775 #define WM8904_HPOUTRZC 0x0040 /* HPOUTRZC */ 776 #define WM8904_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ 777 #define WM8904_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ 778 #define WM8904_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ 779 #define WM8904_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ 780 #define WM8904_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ 781 #define WM8904_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ 782 783 /* 784 * R59 (0x3B) - Analogue OUT2 Left 785 */ 786 #define WM8904_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ 787 #define WM8904_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ 788 #define WM8904_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ 789 #define WM8904_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ 790 #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ 791 #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ 792 #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ 793 #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ 794 #define WM8904_LINEOUTLZC 0x0040 /* LINEOUTLZC */ 795 #define WM8904_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ 796 #define WM8904_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ 797 #define WM8904_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ 798 #define WM8904_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ 799 #define WM8904_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ 800 #define WM8904_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ 801 802 /* 803 * R60 (0x3C) - Analogue OUT2 Right 804 */ 805 #define WM8904_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ 806 #define WM8904_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ 807 #define WM8904_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ 808 #define WM8904_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ 809 #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ 810 #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ 811 #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ 812 #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ 813 #define WM8904_LINEOUTRZC 0x0040 /* LINEOUTRZC */ 814 #define WM8904_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ 815 #define WM8904_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ 816 #define WM8904_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ 817 #define WM8904_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ 818 #define WM8904_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ 819 #define WM8904_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ 820 821 /* 822 * R61 (0x3D) - Analogue OUT12 ZC 823 */ 824 #define WM8904_HPL_BYP_ENA 0x0008 /* HPL_BYP_ENA */ 825 #define WM8904_HPL_BYP_ENA_MASK 0x0008 /* HPL_BYP_ENA */ 826 #define WM8904_HPL_BYP_ENA_SHIFT 3 /* HPL_BYP_ENA */ 827 #define WM8904_HPL_BYP_ENA_WIDTH 1 /* HPL_BYP_ENA */ 828 #define WM8904_HPR_BYP_ENA 0x0004 /* HPR_BYP_ENA */ 829 #define WM8904_HPR_BYP_ENA_MASK 0x0004 /* HPR_BYP_ENA */ 830 #define WM8904_HPR_BYP_ENA_SHIFT 2 /* HPR_BYP_ENA */ 831 #define WM8904_HPR_BYP_ENA_WIDTH 1 /* HPR_BYP_ENA */ 832 #define WM8904_LINEOUTL_BYP_ENA 0x0002 /* LINEOUTL_BYP_ENA */ 833 #define WM8904_LINEOUTL_BYP_ENA_MASK 0x0002 /* LINEOUTL_BYP_ENA */ 834 #define WM8904_LINEOUTL_BYP_ENA_SHIFT 1 /* LINEOUTL_BYP_ENA */ 835 #define WM8904_LINEOUTL_BYP_ENA_WIDTH 1 /* LINEOUTL_BYP_ENA */ 836 #define WM8904_LINEOUTR_BYP_ENA 0x0001 /* LINEOUTR_BYP_ENA */ 837 #define WM8904_LINEOUTR_BYP_ENA_MASK 0x0001 /* LINEOUTR_BYP_ENA */ 838 #define WM8904_LINEOUTR_BYP_ENA_SHIFT 0 /* LINEOUTR_BYP_ENA */ 839 #define WM8904_LINEOUTR_BYP_ENA_WIDTH 1 /* LINEOUTR_BYP_ENA */ 840 841 /* 842 * R67 (0x43) - DC Servo 0 843 */ 844 #define WM8904_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 845 #define WM8904_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 846 #define WM8904_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 847 #define WM8904_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 848 #define WM8904_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 849 #define WM8904_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 850 #define WM8904_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 851 #define WM8904_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 852 #define WM8904_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 853 #define WM8904_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 854 #define WM8904_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 855 #define WM8904_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 856 #define WM8904_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 857 #define WM8904_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 858 #define WM8904_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 859 #define WM8904_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 860 861 /* 862 * R68 (0x44) - DC Servo 1 863 */ 864 #define WM8904_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 865 #define WM8904_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 866 #define WM8904_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 867 #define WM8904_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 868 #define WM8904_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 869 #define WM8904_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 870 #define WM8904_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 871 #define WM8904_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 872 #define WM8904_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 873 #define WM8904_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 874 #define WM8904_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 875 #define WM8904_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 876 #define WM8904_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 877 #define WM8904_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 878 #define WM8904_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 879 #define WM8904_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 880 #define WM8904_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 881 #define WM8904_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 882 #define WM8904_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 883 #define WM8904_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 884 #define WM8904_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 885 #define WM8904_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 886 #define WM8904_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 887 #define WM8904_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 888 #define WM8904_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 889 #define WM8904_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 890 #define WM8904_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 891 #define WM8904_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 892 #define WM8904_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 893 #define WM8904_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 894 #define WM8904_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 895 #define WM8904_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 896 #define WM8904_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 897 #define WM8904_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 898 #define WM8904_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 899 #define WM8904_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 900 #define WM8904_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 901 #define WM8904_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 902 #define WM8904_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 903 #define WM8904_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 904 #define WM8904_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 905 #define WM8904_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 906 #define WM8904_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 907 #define WM8904_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 908 #define WM8904_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 909 #define WM8904_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 910 #define WM8904_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 911 #define WM8904_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 912 #define WM8904_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 913 #define WM8904_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 914 #define WM8904_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 915 #define WM8904_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 916 #define WM8904_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 917 #define WM8904_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 918 #define WM8904_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 919 #define WM8904_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 920 #define WM8904_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 921 #define WM8904_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 922 #define WM8904_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 923 #define WM8904_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 924 #define WM8904_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 925 #define WM8904_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 926 #define WM8904_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 927 #define WM8904_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 928 929 /* 930 * R69 (0x45) - DC Servo 2 931 */ 932 #define WM8904_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 933 #define WM8904_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 934 #define WM8904_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 935 #define WM8904_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 936 #define WM8904_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 937 #define WM8904_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 938 939 /* 940 * R71 (0x47) - DC Servo 4 941 */ 942 #define WM8904_DCS_SERIES_NO_23_MASK 0x007F /* DCS_SERIES_NO_23 - [6:0] */ 943 #define WM8904_DCS_SERIES_NO_23_SHIFT 0 /* DCS_SERIES_NO_23 - [6:0] */ 944 #define WM8904_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [6:0] */ 945 946 /* 947 * R72 (0x48) - DC Servo 5 948 */ 949 #define WM8904_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 950 #define WM8904_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 951 #define WM8904_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 952 953 /* 954 * R73 (0x49) - DC Servo 6 955 */ 956 #define WM8904_DCS_DAC_WR_VAL_3_MASK 0x00FF /* DCS_DAC_WR_VAL_3 - [7:0] */ 957 #define WM8904_DCS_DAC_WR_VAL_3_SHIFT 0 /* DCS_DAC_WR_VAL_3 - [7:0] */ 958 #define WM8904_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [7:0] */ 959 960 /* 961 * R74 (0x4A) - DC Servo 7 962 */ 963 #define WM8904_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 964 #define WM8904_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 965 #define WM8904_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 966 967 /* 968 * R75 (0x4B) - DC Servo 8 969 */ 970 #define WM8904_DCS_DAC_WR_VAL_1_MASK 0x00FF /* DCS_DAC_WR_VAL_1 - [7:0] */ 971 #define WM8904_DCS_DAC_WR_VAL_1_SHIFT 0 /* DCS_DAC_WR_VAL_1 - [7:0] */ 972 #define WM8904_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [7:0] */ 973 974 /* 975 * R76 (0x4C) - DC Servo 9 976 */ 977 #define WM8904_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 978 #define WM8904_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 979 #define WM8904_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 980 981 /* 982 * R77 (0x4D) - DC Servo Readback 0 983 */ 984 #define WM8904_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 985 #define WM8904_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 986 #define WM8904_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 987 #define WM8904_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 988 #define WM8904_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 989 #define WM8904_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 990 #define WM8904_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 991 #define WM8904_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 992 #define WM8904_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 993 994 /* 995 * R90 (0x5A) - Analogue HP 0 996 */ 997 #define WM8904_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 998 #define WM8904_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 999 #define WM8904_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 1000 #define WM8904_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 1001 #define WM8904_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 1002 #define WM8904_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 1003 #define WM8904_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 1004 #define WM8904_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 1005 #define WM8904_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 1006 #define WM8904_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 1007 #define WM8904_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 1008 #define WM8904_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 1009 #define WM8904_HPL_ENA 0x0010 /* HPL_ENA */ 1010 #define WM8904_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 1011 #define WM8904_HPL_ENA_SHIFT 4 /* HPL_ENA */ 1012 #define WM8904_HPL_ENA_WIDTH 1 /* HPL_ENA */ 1013 #define WM8904_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 1014 #define WM8904_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 1015 #define WM8904_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 1016 #define WM8904_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 1017 #define WM8904_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 1018 #define WM8904_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 1019 #define WM8904_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 1020 #define WM8904_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 1021 #define WM8904_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 1022 #define WM8904_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 1023 #define WM8904_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 1024 #define WM8904_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 1025 #define WM8904_HPR_ENA 0x0001 /* HPR_ENA */ 1026 #define WM8904_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 1027 #define WM8904_HPR_ENA_SHIFT 0 /* HPR_ENA */ 1028 #define WM8904_HPR_ENA_WIDTH 1 /* HPR_ENA */ 1029 1030 /* 1031 * R94 (0x5E) - Analogue Lineout 0 1032 */ 1033 #define WM8904_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ 1034 #define WM8904_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ 1035 #define WM8904_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ 1036 #define WM8904_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ 1037 #define WM8904_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ 1038 #define WM8904_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ 1039 #define WM8904_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ 1040 #define WM8904_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ 1041 #define WM8904_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ 1042 #define WM8904_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ 1043 #define WM8904_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ 1044 #define WM8904_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ 1045 #define WM8904_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ 1046 #define WM8904_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ 1047 #define WM8904_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ 1048 #define WM8904_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ 1049 #define WM8904_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ 1050 #define WM8904_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ 1051 #define WM8904_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ 1052 #define WM8904_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ 1053 #define WM8904_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ 1054 #define WM8904_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ 1055 #define WM8904_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ 1056 #define WM8904_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ 1057 #define WM8904_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ 1058 #define WM8904_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ 1059 #define WM8904_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ 1060 #define WM8904_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ 1061 #define WM8904_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ 1062 #define WM8904_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ 1063 #define WM8904_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ 1064 #define WM8904_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ 1065 1066 /* 1067 * R98 (0x62) - Charge Pump 0 1068 */ 1069 #define WM8904_CP_ENA 0x0001 /* CP_ENA */ 1070 #define WM8904_CP_ENA_MASK 0x0001 /* CP_ENA */ 1071 #define WM8904_CP_ENA_SHIFT 0 /* CP_ENA */ 1072 #define WM8904_CP_ENA_WIDTH 1 /* CP_ENA */ 1073 1074 /* 1075 * R104 (0x68) - Class W 0 1076 */ 1077 #define WM8904_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1078 #define WM8904_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1079 #define WM8904_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1080 #define WM8904_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1081 1082 /* 1083 * R108 (0x6C) - Write Sequencer 0 1084 */ 1085 #define WM8904_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 1086 #define WM8904_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 1087 #define WM8904_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 1088 #define WM8904_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1089 #define WM8904_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 1090 #define WM8904_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 1091 #define WM8904_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 1092 1093 /* 1094 * R109 (0x6D) - Write Sequencer 1 1095 */ 1096 #define WM8904_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 1097 #define WM8904_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 1098 #define WM8904_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 1099 #define WM8904_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 1100 #define WM8904_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 1101 #define WM8904_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 1102 #define WM8904_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 1103 #define WM8904_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 1104 #define WM8904_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 1105 1106 /* 1107 * R110 (0x6E) - Write Sequencer 2 1108 */ 1109 #define WM8904_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 1110 #define WM8904_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 1111 #define WM8904_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 1112 #define WM8904_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 1113 #define WM8904_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 1114 #define WM8904_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 1115 #define WM8904_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 1116 #define WM8904_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 1117 #define WM8904_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 1118 #define WM8904_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 1119 1120 /* 1121 * R111 (0x6F) - Write Sequencer 3 1122 */ 1123 #define WM8904_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1124 #define WM8904_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1125 #define WM8904_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1126 #define WM8904_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1127 #define WM8904_WSEQ_START 0x0100 /* WSEQ_START */ 1128 #define WM8904_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1129 #define WM8904_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1130 #define WM8904_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1131 #define WM8904_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 1132 #define WM8904_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 1133 #define WM8904_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 1134 1135 /* 1136 * R112 (0x70) - Write Sequencer 4 1137 */ 1138 #define WM8904_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ 1139 #define WM8904_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ 1140 #define WM8904_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ 1141 #define WM8904_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 1142 #define WM8904_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 1143 #define WM8904_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 1144 #define WM8904_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1145 1146 /* 1147 * R116 (0x74) - FLL Control 1 1148 */ 1149 #define WM8904_FLL_FRACN_ENA 0x0004 /* FLL_FRACN_ENA */ 1150 #define WM8904_FLL_FRACN_ENA_MASK 0x0004 /* FLL_FRACN_ENA */ 1151 #define WM8904_FLL_FRACN_ENA_SHIFT 2 /* FLL_FRACN_ENA */ 1152 #define WM8904_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ 1153 #define WM8904_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ 1154 #define WM8904_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ 1155 #define WM8904_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ 1156 #define WM8904_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ 1157 #define WM8904_FLL_ENA 0x0001 /* FLL_ENA */ 1158 #define WM8904_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 1159 #define WM8904_FLL_ENA_SHIFT 0 /* FLL_ENA */ 1160 #define WM8904_FLL_ENA_WIDTH 1 /* FLL_ENA */ 1161 1162 /* 1163 * R117 (0x75) - FLL Control 2 1164 */ 1165 #define WM8904_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 1166 #define WM8904_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 1167 #define WM8904_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 1168 #define WM8904_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ 1169 #define WM8904_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ 1170 #define WM8904_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ 1171 #define WM8904_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 1172 #define WM8904_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 1173 #define WM8904_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 1174 1175 /* 1176 * R118 (0x76) - FLL Control 3 1177 */ 1178 #define WM8904_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ 1179 #define WM8904_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ 1180 #define WM8904_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ 1181 1182 /* 1183 * R119 (0x77) - FLL Control 4 1184 */ 1185 #define WM8904_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ 1186 #define WM8904_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ 1187 #define WM8904_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ 1188 #define WM8904_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ 1189 #define WM8904_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ 1190 #define WM8904_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ 1191 1192 /* 1193 * R120 (0x78) - FLL Control 5 1194 */ 1195 #define WM8904_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ 1196 #define WM8904_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ 1197 #define WM8904_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ 1198 #define WM8904_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ 1199 #define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ 1200 #define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ 1201 1202 /* 1203 * R121 (0x79) - GPIO Control 1 1204 */ 1205 #define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */ 1206 #define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ 1207 #define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ 1208 #define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ 1209 #define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */ 1210 #define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ 1211 #define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ 1212 #define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ 1213 #define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ 1214 #define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ 1215 #define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ 1216 1217 /* 1218 * R122 (0x7A) - GPIO Control 2 1219 */ 1220 #define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */ 1221 #define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */ 1222 #define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */ 1223 #define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ 1224 #define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */ 1225 #define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */ 1226 #define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */ 1227 #define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ 1228 #define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */ 1229 #define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */ 1230 #define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */ 1231 1232 /* 1233 * R123 (0x7B) - GPIO Control 3 1234 */ 1235 #define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */ 1236 #define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ 1237 #define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ 1238 #define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ 1239 #define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */ 1240 #define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ 1241 #define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ 1242 #define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ 1243 #define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ 1244 #define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ 1245 #define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ 1246 1247 /* 1248 * R124 (0x7C) - GPIO Control 4 1249 */ 1250 #define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */ 1251 #define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */ 1252 #define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */ 1253 #define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ 1254 #define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */ 1255 #define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */ 1256 #define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */ 1257 #define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ 1258 #define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */ 1259 #define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */ 1260 #define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */ 1261 #define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */ 1262 #define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */ 1263 #define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */ 1264 #define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */ 1265 1266 /* 1267 * R126 (0x7E) - Digital Pulls 1268 */ 1269 #define WM8904_MCLK_PU 0x0080 /* MCLK_PU */ 1270 #define WM8904_MCLK_PU_MASK 0x0080 /* MCLK_PU */ 1271 #define WM8904_MCLK_PU_SHIFT 7 /* MCLK_PU */ 1272 #define WM8904_MCLK_PU_WIDTH 1 /* MCLK_PU */ 1273 #define WM8904_MCLK_PD 0x0040 /* MCLK_PD */ 1274 #define WM8904_MCLK_PD_MASK 0x0040 /* MCLK_PD */ 1275 #define WM8904_MCLK_PD_SHIFT 6 /* MCLK_PD */ 1276 #define WM8904_MCLK_PD_WIDTH 1 /* MCLK_PD */ 1277 #define WM8904_DACDAT_PU 0x0020 /* DACDAT_PU */ 1278 #define WM8904_DACDAT_PU_MASK 0x0020 /* DACDAT_PU */ 1279 #define WM8904_DACDAT_PU_SHIFT 5 /* DACDAT_PU */ 1280 #define WM8904_DACDAT_PU_WIDTH 1 /* DACDAT_PU */ 1281 #define WM8904_DACDAT_PD 0x0010 /* DACDAT_PD */ 1282 #define WM8904_DACDAT_PD_MASK 0x0010 /* DACDAT_PD */ 1283 #define WM8904_DACDAT_PD_SHIFT 4 /* DACDAT_PD */ 1284 #define WM8904_DACDAT_PD_WIDTH 1 /* DACDAT_PD */ 1285 #define WM8904_LRCLK_PU 0x0008 /* LRCLK_PU */ 1286 #define WM8904_LRCLK_PU_MASK 0x0008 /* LRCLK_PU */ 1287 #define WM8904_LRCLK_PU_SHIFT 3 /* LRCLK_PU */ 1288 #define WM8904_LRCLK_PU_WIDTH 1 /* LRCLK_PU */ 1289 #define WM8904_LRCLK_PD 0x0004 /* LRCLK_PD */ 1290 #define WM8904_LRCLK_PD_MASK 0x0004 /* LRCLK_PD */ 1291 #define WM8904_LRCLK_PD_SHIFT 2 /* LRCLK_PD */ 1292 #define WM8904_LRCLK_PD_WIDTH 1 /* LRCLK_PD */ 1293 #define WM8904_BCLK_PU 0x0002 /* BCLK_PU */ 1294 #define WM8904_BCLK_PU_MASK 0x0002 /* BCLK_PU */ 1295 #define WM8904_BCLK_PU_SHIFT 1 /* BCLK_PU */ 1296 #define WM8904_BCLK_PU_WIDTH 1 /* BCLK_PU */ 1297 #define WM8904_BCLK_PD 0x0001 /* BCLK_PD */ 1298 #define WM8904_BCLK_PD_MASK 0x0001 /* BCLK_PD */ 1299 #define WM8904_BCLK_PD_SHIFT 0 /* BCLK_PD */ 1300 #define WM8904_BCLK_PD_WIDTH 1 /* BCLK_PD */ 1301 1302 /* 1303 * R127 (0x7F) - Interrupt Status 1304 */ 1305 #define WM8904_IRQ 0x0400 /* IRQ */ 1306 #define WM8904_IRQ_MASK 0x0400 /* IRQ */ 1307 #define WM8904_IRQ_SHIFT 10 /* IRQ */ 1308 #define WM8904_IRQ_WIDTH 1 /* IRQ */ 1309 #define WM8904_GPIO_BCLK_EINT 0x0200 /* GPIO_BCLK_EINT */ 1310 #define WM8904_GPIO_BCLK_EINT_MASK 0x0200 /* GPIO_BCLK_EINT */ 1311 #define WM8904_GPIO_BCLK_EINT_SHIFT 9 /* GPIO_BCLK_EINT */ 1312 #define WM8904_GPIO_BCLK_EINT_WIDTH 1 /* GPIO_BCLK_EINT */ 1313 #define WM8904_WSEQ_EINT 0x0100 /* WSEQ_EINT */ 1314 #define WM8904_WSEQ_EINT_MASK 0x0100 /* WSEQ_EINT */ 1315 #define WM8904_WSEQ_EINT_SHIFT 8 /* WSEQ_EINT */ 1316 #define WM8904_WSEQ_EINT_WIDTH 1 /* WSEQ_EINT */ 1317 #define WM8904_GPIO3_EINT 0x0080 /* GPIO3_EINT */ 1318 #define WM8904_GPIO3_EINT_MASK 0x0080 /* GPIO3_EINT */ 1319 #define WM8904_GPIO3_EINT_SHIFT 7 /* GPIO3_EINT */ 1320 #define WM8904_GPIO3_EINT_WIDTH 1 /* GPIO3_EINT */ 1321 #define WM8904_GPIO2_EINT 0x0040 /* GPIO2_EINT */ 1322 #define WM8904_GPIO2_EINT_MASK 0x0040 /* GPIO2_EINT */ 1323 #define WM8904_GPIO2_EINT_SHIFT 6 /* GPIO2_EINT */ 1324 #define WM8904_GPIO2_EINT_WIDTH 1 /* GPIO2_EINT */ 1325 #define WM8904_GPIO1_EINT 0x0020 /* GPIO1_EINT */ 1326 #define WM8904_GPIO1_EINT_MASK 0x0020 /* GPIO1_EINT */ 1327 #define WM8904_GPIO1_EINT_SHIFT 5 /* GPIO1_EINT */ 1328 #define WM8904_GPIO1_EINT_WIDTH 1 /* GPIO1_EINT */ 1329 #define WM8904_GPI8_EINT 0x0010 /* GPI8_EINT */ 1330 #define WM8904_GPI8_EINT_MASK 0x0010 /* GPI8_EINT */ 1331 #define WM8904_GPI8_EINT_SHIFT 4 /* GPI8_EINT */ 1332 #define WM8904_GPI8_EINT_WIDTH 1 /* GPI8_EINT */ 1333 #define WM8904_GPI7_EINT 0x0008 /* GPI7_EINT */ 1334 #define WM8904_GPI7_EINT_MASK 0x0008 /* GPI7_EINT */ 1335 #define WM8904_GPI7_EINT_SHIFT 3 /* GPI7_EINT */ 1336 #define WM8904_GPI7_EINT_WIDTH 1 /* GPI7_EINT */ 1337 #define WM8904_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ 1338 #define WM8904_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ 1339 #define WM8904_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ 1340 #define WM8904_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 1341 #define WM8904_MIC_SHRT_EINT 0x0002 /* MIC_SHRT_EINT */ 1342 #define WM8904_MIC_SHRT_EINT_MASK 0x0002 /* MIC_SHRT_EINT */ 1343 #define WM8904_MIC_SHRT_EINT_SHIFT 1 /* MIC_SHRT_EINT */ 1344 #define WM8904_MIC_SHRT_EINT_WIDTH 1 /* MIC_SHRT_EINT */ 1345 #define WM8904_MIC_DET_EINT 0x0001 /* MIC_DET_EINT */ 1346 #define WM8904_MIC_DET_EINT_MASK 0x0001 /* MIC_DET_EINT */ 1347 #define WM8904_MIC_DET_EINT_SHIFT 0 /* MIC_DET_EINT */ 1348 #define WM8904_MIC_DET_EINT_WIDTH 1 /* MIC_DET_EINT */ 1349 1350 /* 1351 * R128 (0x80) - Interrupt Status Mask 1352 */ 1353 #define WM8904_IM_GPIO_BCLK_EINT 0x0200 /* IM_GPIO_BCLK_EINT */ 1354 #define WM8904_IM_GPIO_BCLK_EINT_MASK 0x0200 /* IM_GPIO_BCLK_EINT */ 1355 #define WM8904_IM_GPIO_BCLK_EINT_SHIFT 9 /* IM_GPIO_BCLK_EINT */ 1356 #define WM8904_IM_GPIO_BCLK_EINT_WIDTH 1 /* IM_GPIO_BCLK_EINT */ 1357 #define WM8904_IM_WSEQ_EINT 0x0100 /* IM_WSEQ_EINT */ 1358 #define WM8904_IM_WSEQ_EINT_MASK 0x0100 /* IM_WSEQ_EINT */ 1359 #define WM8904_IM_WSEQ_EINT_SHIFT 8 /* IM_WSEQ_EINT */ 1360 #define WM8904_IM_WSEQ_EINT_WIDTH 1 /* IM_WSEQ_EINT */ 1361 #define WM8904_IM_GPIO3_EINT 0x0080 /* IM_GPIO3_EINT */ 1362 #define WM8904_IM_GPIO3_EINT_MASK 0x0080 /* IM_GPIO3_EINT */ 1363 #define WM8904_IM_GPIO3_EINT_SHIFT 7 /* IM_GPIO3_EINT */ 1364 #define WM8904_IM_GPIO3_EINT_WIDTH 1 /* IM_GPIO3_EINT */ 1365 #define WM8904_IM_GPIO2_EINT 0x0040 /* IM_GPIO2_EINT */ 1366 #define WM8904_IM_GPIO2_EINT_MASK 0x0040 /* IM_GPIO2_EINT */ 1367 #define WM8904_IM_GPIO2_EINT_SHIFT 6 /* IM_GPIO2_EINT */ 1368 #define WM8904_IM_GPIO2_EINT_WIDTH 1 /* IM_GPIO2_EINT */ 1369 #define WM8904_IM_GPIO1_EINT 0x0020 /* IM_GPIO1_EINT */ 1370 #define WM8904_IM_GPIO1_EINT_MASK 0x0020 /* IM_GPIO1_EINT */ 1371 #define WM8904_IM_GPIO1_EINT_SHIFT 5 /* IM_GPIO1_EINT */ 1372 #define WM8904_IM_GPIO1_EINT_WIDTH 1 /* IM_GPIO1_EINT */ 1373 #define WM8904_IM_GPI8_EINT 0x0010 /* IM_GPI8_EINT */ 1374 #define WM8904_IM_GPI8_EINT_MASK 0x0010 /* IM_GPI8_EINT */ 1375 #define WM8904_IM_GPI8_EINT_SHIFT 4 /* IM_GPI8_EINT */ 1376 #define WM8904_IM_GPI8_EINT_WIDTH 1 /* IM_GPI8_EINT */ 1377 #define WM8904_IM_GPI7_EINT 0x0008 /* IM_GPI7_EINT */ 1378 #define WM8904_IM_GPI7_EINT_MASK 0x0008 /* IM_GPI7_EINT */ 1379 #define WM8904_IM_GPI7_EINT_SHIFT 3 /* IM_GPI7_EINT */ 1380 #define WM8904_IM_GPI7_EINT_WIDTH 1 /* IM_GPI7_EINT */ 1381 #define WM8904_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ 1382 #define WM8904_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ 1383 #define WM8904_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ 1384 #define WM8904_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 1385 #define WM8904_IM_MIC_SHRT_EINT 0x0002 /* IM_MIC_SHRT_EINT */ 1386 #define WM8904_IM_MIC_SHRT_EINT_MASK 0x0002 /* IM_MIC_SHRT_EINT */ 1387 #define WM8904_IM_MIC_SHRT_EINT_SHIFT 1 /* IM_MIC_SHRT_EINT */ 1388 #define WM8904_IM_MIC_SHRT_EINT_WIDTH 1 /* IM_MIC_SHRT_EINT */ 1389 #define WM8904_IM_MIC_DET_EINT 0x0001 /* IM_MIC_DET_EINT */ 1390 #define WM8904_IM_MIC_DET_EINT_MASK 0x0001 /* IM_MIC_DET_EINT */ 1391 #define WM8904_IM_MIC_DET_EINT_SHIFT 0 /* IM_MIC_DET_EINT */ 1392 #define WM8904_IM_MIC_DET_EINT_WIDTH 1 /* IM_MIC_DET_EINT */ 1393 1394 /* 1395 * R129 (0x81) - Interrupt Polarity 1396 */ 1397 #define WM8904_GPIO_BCLK_EINT_POL 0x0200 /* GPIO_BCLK_EINT_POL */ 1398 #define WM8904_GPIO_BCLK_EINT_POL_MASK 0x0200 /* GPIO_BCLK_EINT_POL */ 1399 #define WM8904_GPIO_BCLK_EINT_POL_SHIFT 9 /* GPIO_BCLK_EINT_POL */ 1400 #define WM8904_GPIO_BCLK_EINT_POL_WIDTH 1 /* GPIO_BCLK_EINT_POL */ 1401 #define WM8904_WSEQ_EINT_POL 0x0100 /* WSEQ_EINT_POL */ 1402 #define WM8904_WSEQ_EINT_POL_MASK 0x0100 /* WSEQ_EINT_POL */ 1403 #define WM8904_WSEQ_EINT_POL_SHIFT 8 /* WSEQ_EINT_POL */ 1404 #define WM8904_WSEQ_EINT_POL_WIDTH 1 /* WSEQ_EINT_POL */ 1405 #define WM8904_GPIO3_EINT_POL 0x0080 /* GPIO3_EINT_POL */ 1406 #define WM8904_GPIO3_EINT_POL_MASK 0x0080 /* GPIO3_EINT_POL */ 1407 #define WM8904_GPIO3_EINT_POL_SHIFT 7 /* GPIO3_EINT_POL */ 1408 #define WM8904_GPIO3_EINT_POL_WIDTH 1 /* GPIO3_EINT_POL */ 1409 #define WM8904_GPIO2_EINT_POL 0x0040 /* GPIO2_EINT_POL */ 1410 #define WM8904_GPIO2_EINT_POL_MASK 0x0040 /* GPIO2_EINT_POL */ 1411 #define WM8904_GPIO2_EINT_POL_SHIFT 6 /* GPIO2_EINT_POL */ 1412 #define WM8904_GPIO2_EINT_POL_WIDTH 1 /* GPIO2_EINT_POL */ 1413 #define WM8904_GPIO1_EINT_POL 0x0020 /* GPIO1_EINT_POL */ 1414 #define WM8904_GPIO1_EINT_POL_MASK 0x0020 /* GPIO1_EINT_POL */ 1415 #define WM8904_GPIO1_EINT_POL_SHIFT 5 /* GPIO1_EINT_POL */ 1416 #define WM8904_GPIO1_EINT_POL_WIDTH 1 /* GPIO1_EINT_POL */ 1417 #define WM8904_GPI8_EINT_POL 0x0010 /* GPI8_EINT_POL */ 1418 #define WM8904_GPI8_EINT_POL_MASK 0x0010 /* GPI8_EINT_POL */ 1419 #define WM8904_GPI8_EINT_POL_SHIFT 4 /* GPI8_EINT_POL */ 1420 #define WM8904_GPI8_EINT_POL_WIDTH 1 /* GPI8_EINT_POL */ 1421 #define WM8904_GPI7_EINT_POL 0x0008 /* GPI7_EINT_POL */ 1422 #define WM8904_GPI7_EINT_POL_MASK 0x0008 /* GPI7_EINT_POL */ 1423 #define WM8904_GPI7_EINT_POL_SHIFT 3 /* GPI7_EINT_POL */ 1424 #define WM8904_GPI7_EINT_POL_WIDTH 1 /* GPI7_EINT_POL */ 1425 #define WM8904_FLL_LOCK_EINT_POL 0x0004 /* FLL_LOCK_EINT_POL */ 1426 #define WM8904_FLL_LOCK_EINT_POL_MASK 0x0004 /* FLL_LOCK_EINT_POL */ 1427 #define WM8904_FLL_LOCK_EINT_POL_SHIFT 2 /* FLL_LOCK_EINT_POL */ 1428 #define WM8904_FLL_LOCK_EINT_POL_WIDTH 1 /* FLL_LOCK_EINT_POL */ 1429 #define WM8904_MIC_SHRT_EINT_POL 0x0002 /* MIC_SHRT_EINT_POL */ 1430 #define WM8904_MIC_SHRT_EINT_POL_MASK 0x0002 /* MIC_SHRT_EINT_POL */ 1431 #define WM8904_MIC_SHRT_EINT_POL_SHIFT 1 /* MIC_SHRT_EINT_POL */ 1432 #define WM8904_MIC_SHRT_EINT_POL_WIDTH 1 /* MIC_SHRT_EINT_POL */ 1433 #define WM8904_MIC_DET_EINT_POL 0x0001 /* MIC_DET_EINT_POL */ 1434 #define WM8904_MIC_DET_EINT_POL_MASK 0x0001 /* MIC_DET_EINT_POL */ 1435 #define WM8904_MIC_DET_EINT_POL_SHIFT 0 /* MIC_DET_EINT_POL */ 1436 #define WM8904_MIC_DET_EINT_POL_WIDTH 1 /* MIC_DET_EINT_POL */ 1437 1438 /* 1439 * R130 (0x82) - Interrupt Debounce 1440 */ 1441 #define WM8904_GPIO_BCLK_EINT_DB 0x0200 /* GPIO_BCLK_EINT_DB */ 1442 #define WM8904_GPIO_BCLK_EINT_DB_MASK 0x0200 /* GPIO_BCLK_EINT_DB */ 1443 #define WM8904_GPIO_BCLK_EINT_DB_SHIFT 9 /* GPIO_BCLK_EINT_DB */ 1444 #define WM8904_GPIO_BCLK_EINT_DB_WIDTH 1 /* GPIO_BCLK_EINT_DB */ 1445 #define WM8904_WSEQ_EINT_DB 0x0100 /* WSEQ_EINT_DB */ 1446 #define WM8904_WSEQ_EINT_DB_MASK 0x0100 /* WSEQ_EINT_DB */ 1447 #define WM8904_WSEQ_EINT_DB_SHIFT 8 /* WSEQ_EINT_DB */ 1448 #define WM8904_WSEQ_EINT_DB_WIDTH 1 /* WSEQ_EINT_DB */ 1449 #define WM8904_GPIO3_EINT_DB 0x0080 /* GPIO3_EINT_DB */ 1450 #define WM8904_GPIO3_EINT_DB_MASK 0x0080 /* GPIO3_EINT_DB */ 1451 #define WM8904_GPIO3_EINT_DB_SHIFT 7 /* GPIO3_EINT_DB */ 1452 #define WM8904_GPIO3_EINT_DB_WIDTH 1 /* GPIO3_EINT_DB */ 1453 #define WM8904_GPIO2_EINT_DB 0x0040 /* GPIO2_EINT_DB */ 1454 #define WM8904_GPIO2_EINT_DB_MASK 0x0040 /* GPIO2_EINT_DB */ 1455 #define WM8904_GPIO2_EINT_DB_SHIFT 6 /* GPIO2_EINT_DB */ 1456 #define WM8904_GPIO2_EINT_DB_WIDTH 1 /* GPIO2_EINT_DB */ 1457 #define WM8904_GPIO1_EINT_DB 0x0020 /* GPIO1_EINT_DB */ 1458 #define WM8904_GPIO1_EINT_DB_MASK 0x0020 /* GPIO1_EINT_DB */ 1459 #define WM8904_GPIO1_EINT_DB_SHIFT 5 /* GPIO1_EINT_DB */ 1460 #define WM8904_GPIO1_EINT_DB_WIDTH 1 /* GPIO1_EINT_DB */ 1461 #define WM8904_GPI8_EINT_DB 0x0010 /* GPI8_EINT_DB */ 1462 #define WM8904_GPI8_EINT_DB_MASK 0x0010 /* GPI8_EINT_DB */ 1463 #define WM8904_GPI8_EINT_DB_SHIFT 4 /* GPI8_EINT_DB */ 1464 #define WM8904_GPI8_EINT_DB_WIDTH 1 /* GPI8_EINT_DB */ 1465 #define WM8904_GPI7_EINT_DB 0x0008 /* GPI7_EINT_DB */ 1466 #define WM8904_GPI7_EINT_DB_MASK 0x0008 /* GPI7_EINT_DB */ 1467 #define WM8904_GPI7_EINT_DB_SHIFT 3 /* GPI7_EINT_DB */ 1468 #define WM8904_GPI7_EINT_DB_WIDTH 1 /* GPI7_EINT_DB */ 1469 #define WM8904_FLL_LOCK_EINT_DB 0x0004 /* FLL_LOCK_EINT_DB */ 1470 #define WM8904_FLL_LOCK_EINT_DB_MASK 0x0004 /* FLL_LOCK_EINT_DB */ 1471 #define WM8904_FLL_LOCK_EINT_DB_SHIFT 2 /* FLL_LOCK_EINT_DB */ 1472 #define WM8904_FLL_LOCK_EINT_DB_WIDTH 1 /* FLL_LOCK_EINT_DB */ 1473 #define WM8904_MIC_SHRT_EINT_DB 0x0002 /* MIC_SHRT_EINT_DB */ 1474 #define WM8904_MIC_SHRT_EINT_DB_MASK 0x0002 /* MIC_SHRT_EINT_DB */ 1475 #define WM8904_MIC_SHRT_EINT_DB_SHIFT 1 /* MIC_SHRT_EINT_DB */ 1476 #define WM8904_MIC_SHRT_EINT_DB_WIDTH 1 /* MIC_SHRT_EINT_DB */ 1477 #define WM8904_MIC_DET_EINT_DB 0x0001 /* MIC_DET_EINT_DB */ 1478 #define WM8904_MIC_DET_EINT_DB_MASK 0x0001 /* MIC_DET_EINT_DB */ 1479 #define WM8904_MIC_DET_EINT_DB_SHIFT 0 /* MIC_DET_EINT_DB */ 1480 #define WM8904_MIC_DET_EINT_DB_WIDTH 1 /* MIC_DET_EINT_DB */ 1481 1482 /* 1483 * R134 (0x86) - EQ1 1484 */ 1485 #define WM8904_EQ_ENA 0x0001 /* EQ_ENA */ 1486 #define WM8904_EQ_ENA_MASK 0x0001 /* EQ_ENA */ 1487 #define WM8904_EQ_ENA_SHIFT 0 /* EQ_ENA */ 1488 #define WM8904_EQ_ENA_WIDTH 1 /* EQ_ENA */ 1489 1490 /* 1491 * R135 (0x87) - EQ2 1492 */ 1493 #define WM8904_EQ_B1_GAIN_MASK 0x001F /* EQ_B1_GAIN - [4:0] */ 1494 #define WM8904_EQ_B1_GAIN_SHIFT 0 /* EQ_B1_GAIN - [4:0] */ 1495 #define WM8904_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [4:0] */ 1496 1497 /* 1498 * R136 (0x88) - EQ3 1499 */ 1500 #define WM8904_EQ_B2_GAIN_MASK 0x001F /* EQ_B2_GAIN - [4:0] */ 1501 #define WM8904_EQ_B2_GAIN_SHIFT 0 /* EQ_B2_GAIN - [4:0] */ 1502 #define WM8904_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [4:0] */ 1503 1504 /* 1505 * R137 (0x89) - EQ4 1506 */ 1507 #define WM8904_EQ_B3_GAIN_MASK 0x001F /* EQ_B3_GAIN - [4:0] */ 1508 #define WM8904_EQ_B3_GAIN_SHIFT 0 /* EQ_B3_GAIN - [4:0] */ 1509 #define WM8904_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [4:0] */ 1510 1511 /* 1512 * R138 (0x8A) - EQ5 1513 */ 1514 #define WM8904_EQ_B4_GAIN_MASK 0x001F /* EQ_B4_GAIN - [4:0] */ 1515 #define WM8904_EQ_B4_GAIN_SHIFT 0 /* EQ_B4_GAIN - [4:0] */ 1516 #define WM8904_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [4:0] */ 1517 1518 /* 1519 * R139 (0x8B) - EQ6 1520 */ 1521 #define WM8904_EQ_B5_GAIN_MASK 0x001F /* EQ_B5_GAIN - [4:0] */ 1522 #define WM8904_EQ_B5_GAIN_SHIFT 0 /* EQ_B5_GAIN - [4:0] */ 1523 #define WM8904_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [4:0] */ 1524 1525 /* 1526 * R140 (0x8C) - EQ7 1527 */ 1528 #define WM8904_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */ 1529 #define WM8904_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */ 1530 #define WM8904_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */ 1531 1532 /* 1533 * R141 (0x8D) - EQ8 1534 */ 1535 #define WM8904_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */ 1536 #define WM8904_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */ 1537 #define WM8904_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */ 1538 1539 /* 1540 * R142 (0x8E) - EQ9 1541 */ 1542 #define WM8904_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */ 1543 #define WM8904_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */ 1544 #define WM8904_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */ 1545 1546 /* 1547 * R143 (0x8F) - EQ10 1548 */ 1549 #define WM8904_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */ 1550 #define WM8904_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */ 1551 #define WM8904_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */ 1552 1553 /* 1554 * R144 (0x90) - EQ11 1555 */ 1556 #define WM8904_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */ 1557 #define WM8904_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */ 1558 #define WM8904_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */ 1559 1560 /* 1561 * R145 (0x91) - EQ12 1562 */ 1563 #define WM8904_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */ 1564 #define WM8904_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */ 1565 #define WM8904_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */ 1566 1567 /* 1568 * R146 (0x92) - EQ13 1569 */ 1570 #define WM8904_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */ 1571 #define WM8904_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */ 1572 #define WM8904_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */ 1573 1574 /* 1575 * R147 (0x93) - EQ14 1576 */ 1577 #define WM8904_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */ 1578 #define WM8904_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */ 1579 #define WM8904_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */ 1580 1581 /* 1582 * R148 (0x94) - EQ15 1583 */ 1584 #define WM8904_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */ 1585 #define WM8904_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */ 1586 #define WM8904_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */ 1587 1588 /* 1589 * R149 (0x95) - EQ16 1590 */ 1591 #define WM8904_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */ 1592 #define WM8904_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */ 1593 #define WM8904_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */ 1594 1595 /* 1596 * R150 (0x96) - EQ17 1597 */ 1598 #define WM8904_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */ 1599 #define WM8904_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */ 1600 #define WM8904_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */ 1601 1602 /* 1603 * R151 (0x97) - EQ18 1604 */ 1605 #define WM8904_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */ 1606 #define WM8904_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */ 1607 #define WM8904_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */ 1608 1609 /* 1610 * R152 (0x98) - EQ19 1611 */ 1612 #define WM8904_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */ 1613 #define WM8904_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */ 1614 #define WM8904_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */ 1615 1616 /* 1617 * R153 (0x99) - EQ20 1618 */ 1619 #define WM8904_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */ 1620 #define WM8904_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */ 1621 #define WM8904_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */ 1622 1623 /* 1624 * R154 (0x9A) - EQ21 1625 */ 1626 #define WM8904_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */ 1627 #define WM8904_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */ 1628 #define WM8904_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */ 1629 1630 /* 1631 * R155 (0x9B) - EQ22 1632 */ 1633 #define WM8904_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */ 1634 #define WM8904_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */ 1635 #define WM8904_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */ 1636 1637 /* 1638 * R156 (0x9C) - EQ23 1639 */ 1640 #define WM8904_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */ 1641 #define WM8904_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */ 1642 #define WM8904_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */ 1643 1644 /* 1645 * R157 (0x9D) - EQ24 1646 */ 1647 #define WM8904_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */ 1648 #define WM8904_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */ 1649 #define WM8904_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */ 1650 1651 /* 1652 * R161 (0xA1) - Control Interface Test 1 1653 */ 1654 #define WM8904_USER_KEY 0x0002 /* USER_KEY */ 1655 #define WM8904_USER_KEY_MASK 0x0002 /* USER_KEY */ 1656 #define WM8904_USER_KEY_SHIFT 1 /* USER_KEY */ 1657 #define WM8904_USER_KEY_WIDTH 1 /* USER_KEY */ 1658 1659 /* 1660 * R204 (0xCC) - Analogue Output Bias 0 1661 */ 1662 #define WM8904_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ 1663 #define WM8904_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ 1664 #define WM8904_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ 1665 1666 /* 1667 * R247 (0xF7) - FLL NCO Test 0 1668 */ 1669 #define WM8904_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */ 1670 #define WM8904_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */ 1671 #define WM8904_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */ 1672 #define WM8904_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ 1673 1674 /* 1675 * R248 (0xF8) - FLL NCO Test 1 1676 */ 1677 #define WM8904_FLL_FRC_NCO_VAL_MASK 0x003F /* FLL_FRC_NCO_VAL - [5:0] */ 1678 #define WM8904_FLL_FRC_NCO_VAL_SHIFT 0 /* FLL_FRC_NCO_VAL - [5:0] */ 1679 #define WM8904_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [5:0] */ 1680 1681 #endif 1682