xref: /openbmc/linux/sound/soc/codecs/wm8904.c (revision e8f6f3b4)
1 /*
2  * wm8904.c  --  WM8904 ALSA SoC Audio driver
3  *
4  * Copyright 2009-12 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/clk.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/wm8904.h>
31 
32 #include "wm8904.h"
33 
34 enum wm8904_type {
35 	WM8904,
36 	WM8912,
37 };
38 
39 #define WM8904_NUM_DCS_CHANNELS 4
40 
41 #define WM8904_NUM_SUPPLIES 5
42 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
43 	"DCVDD",
44 	"DBVDD",
45 	"AVDD",
46 	"CPVDD",
47 	"MICVDD",
48 };
49 
50 /* codec private data */
51 struct wm8904_priv {
52 	struct regmap *regmap;
53 	struct clk *mclk;
54 
55 	enum wm8904_type devtype;
56 
57 	struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
58 
59 	struct wm8904_pdata *pdata;
60 
61 	int deemph;
62 
63 	/* Platform provided DRC configuration */
64 	const char **drc_texts;
65 	int drc_cfg;
66 	struct soc_enum drc_enum;
67 
68 	/* Platform provided ReTune mobile configuration */
69 	int num_retune_mobile_texts;
70 	const char **retune_mobile_texts;
71 	int retune_mobile_cfg;
72 	struct soc_enum retune_mobile_enum;
73 
74 	/* FLL setup */
75 	int fll_src;
76 	int fll_fref;
77 	int fll_fout;
78 
79 	/* Clocking configuration */
80 	unsigned int mclk_rate;
81 	int sysclk_src;
82 	unsigned int sysclk_rate;
83 
84 	int tdm_width;
85 	int tdm_slots;
86 	int bclk;
87 	int fs;
88 
89 	/* DC servo configuration - cached offset values */
90 	int dcs_state[WM8904_NUM_DCS_CHANNELS];
91 };
92 
93 static const struct reg_default wm8904_reg_defaults[] = {
94 	{ 4,   0x0018 },     /* R4   - Bias Control 0 */
95 	{ 5,   0x0000 },     /* R5   - VMID Control 0 */
96 	{ 6,   0x0000 },     /* R6   - Mic Bias Control 0 */
97 	{ 7,   0x0000 },     /* R7   - Mic Bias Control 1 */
98 	{ 8,   0x0001 },     /* R8   - Analogue DAC 0 */
99 	{ 9,   0x9696 },     /* R9   - mic Filter Control */
100 	{ 10,  0x0001 },     /* R10  - Analogue ADC 0 */
101 	{ 12,  0x0000 },     /* R12  - Power Management 0 */
102 	{ 14,  0x0000 },     /* R14  - Power Management 2 */
103 	{ 15,  0x0000 },     /* R15  - Power Management 3 */
104 	{ 18,  0x0000 },     /* R18  - Power Management 6 */
105 	{ 20,  0x945E },     /* R20  - Clock Rates 0 */
106 	{ 21,  0x0C05 },     /* R21  - Clock Rates 1 */
107 	{ 22,  0x0006 },     /* R22  - Clock Rates 2 */
108 	{ 24,  0x0050 },     /* R24  - Audio Interface 0 */
109 	{ 25,  0x000A },     /* R25  - Audio Interface 1 */
110 	{ 26,  0x00E4 },     /* R26  - Audio Interface 2 */
111 	{ 27,  0x0040 },     /* R27  - Audio Interface 3 */
112 	{ 30,  0x00C0 },     /* R30  - DAC Digital Volume Left */
113 	{ 31,  0x00C0 },     /* R31  - DAC Digital Volume Right */
114 	{ 32,  0x0000 },     /* R32  - DAC Digital 0 */
115 	{ 33,  0x0008 },     /* R33  - DAC Digital 1 */
116 	{ 36,  0x00C0 },     /* R36  - ADC Digital Volume Left */
117 	{ 37,  0x00C0 },     /* R37  - ADC Digital Volume Right */
118 	{ 38,  0x0010 },     /* R38  - ADC Digital 0 */
119 	{ 39,  0x0000 },     /* R39  - Digital Microphone 0 */
120 	{ 40,  0x01AF },     /* R40  - DRC 0 */
121 	{ 41,  0x3248 },     /* R41  - DRC 1 */
122 	{ 42,  0x0000 },     /* R42  - DRC 2 */
123 	{ 43,  0x0000 },     /* R43  - DRC 3 */
124 	{ 44,  0x0085 },     /* R44  - Analogue Left Input 0 */
125 	{ 45,  0x0085 },     /* R45  - Analogue Right Input 0 */
126 	{ 46,  0x0044 },     /* R46  - Analogue Left Input 1 */
127 	{ 47,  0x0044 },     /* R47  - Analogue Right Input 1 */
128 	{ 57,  0x002D },     /* R57  - Analogue OUT1 Left */
129 	{ 58,  0x002D },     /* R58  - Analogue OUT1 Right */
130 	{ 59,  0x0039 },     /* R59  - Analogue OUT2 Left */
131 	{ 60,  0x0039 },     /* R60  - Analogue OUT2 Right */
132 	{ 61,  0x0000 },     /* R61  - Analogue OUT12 ZC */
133 	{ 67,  0x0000 },     /* R67  - DC Servo 0 */
134 	{ 69,  0xAAAA },     /* R69  - DC Servo 2 */
135 	{ 71,  0xAAAA },     /* R71  - DC Servo 4 */
136 	{ 72,  0xAAAA },     /* R72  - DC Servo 5 */
137 	{ 90,  0x0000 },     /* R90  - Analogue HP 0 */
138 	{ 94,  0x0000 },     /* R94  - Analogue Lineout 0 */
139 	{ 98,  0x0000 },     /* R98  - Charge Pump 0 */
140 	{ 104, 0x0004 },     /* R104 - Class W 0 */
141 	{ 108, 0x0000 },     /* R108 - Write Sequencer 0 */
142 	{ 109, 0x0000 },     /* R109 - Write Sequencer 1 */
143 	{ 110, 0x0000 },     /* R110 - Write Sequencer 2 */
144 	{ 111, 0x0000 },     /* R111 - Write Sequencer 3 */
145 	{ 112, 0x0000 },     /* R112 - Write Sequencer 4 */
146 	{ 116, 0x0000 },     /* R116 - FLL Control 1 */
147 	{ 117, 0x0007 },     /* R117 - FLL Control 2 */
148 	{ 118, 0x0000 },     /* R118 - FLL Control 3 */
149 	{ 119, 0x2EE0 },     /* R119 - FLL Control 4 */
150 	{ 120, 0x0004 },     /* R120 - FLL Control 5 */
151 	{ 121, 0x0014 },     /* R121 - GPIO Control 1 */
152 	{ 122, 0x0010 },     /* R122 - GPIO Control 2 */
153 	{ 123, 0x0010 },     /* R123 - GPIO Control 3 */
154 	{ 124, 0x0000 },     /* R124 - GPIO Control 4 */
155 	{ 126, 0x0000 },     /* R126 - Digital Pulls */
156 	{ 128, 0xFFFF },     /* R128 - Interrupt Status Mask */
157 	{ 129, 0x0000 },     /* R129 - Interrupt Polarity */
158 	{ 130, 0x0000 },     /* R130 - Interrupt Debounce */
159 	{ 134, 0x0000 },     /* R134 - EQ1 */
160 	{ 135, 0x000C },     /* R135 - EQ2 */
161 	{ 136, 0x000C },     /* R136 - EQ3 */
162 	{ 137, 0x000C },     /* R137 - EQ4 */
163 	{ 138, 0x000C },     /* R138 - EQ5 */
164 	{ 139, 0x000C },     /* R139 - EQ6 */
165 	{ 140, 0x0FCA },     /* R140 - EQ7 */
166 	{ 141, 0x0400 },     /* R141 - EQ8 */
167 	{ 142, 0x00D8 },     /* R142 - EQ9 */
168 	{ 143, 0x1EB5 },     /* R143 - EQ10 */
169 	{ 144, 0xF145 },     /* R144 - EQ11 */
170 	{ 145, 0x0B75 },     /* R145 - EQ12 */
171 	{ 146, 0x01C5 },     /* R146 - EQ13 */
172 	{ 147, 0x1C58 },     /* R147 - EQ14 */
173 	{ 148, 0xF373 },     /* R148 - EQ15 */
174 	{ 149, 0x0A54 },     /* R149 - EQ16 */
175 	{ 150, 0x0558 },     /* R150 - EQ17 */
176 	{ 151, 0x168E },     /* R151 - EQ18 */
177 	{ 152, 0xF829 },     /* R152 - EQ19 */
178 	{ 153, 0x07AD },     /* R153 - EQ20 */
179 	{ 154, 0x1103 },     /* R154 - EQ21 */
180 	{ 155, 0x0564 },     /* R155 - EQ22 */
181 	{ 156, 0x0559 },     /* R156 - EQ23 */
182 	{ 157, 0x4000 },     /* R157 - EQ24 */
183 	{ 161, 0x0000 },     /* R161 - Control Interface Test 1 */
184 	{ 204, 0x0000 },     /* R204 - Analogue Output Bias 0 */
185 	{ 247, 0x0000 },     /* R247 - FLL NCO Test 0 */
186 	{ 248, 0x0019 },     /* R248 - FLL NCO Test 1 */
187 };
188 
189 static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
190 {
191 	switch (reg) {
192 	case WM8904_SW_RESET_AND_ID:
193 	case WM8904_REVISION:
194 	case WM8904_DC_SERVO_1:
195 	case WM8904_DC_SERVO_6:
196 	case WM8904_DC_SERVO_7:
197 	case WM8904_DC_SERVO_8:
198 	case WM8904_DC_SERVO_9:
199 	case WM8904_DC_SERVO_READBACK_0:
200 	case WM8904_INTERRUPT_STATUS:
201 		return true;
202 	default:
203 		return false;
204 	}
205 }
206 
207 static bool wm8904_readable_register(struct device *dev, unsigned int reg)
208 {
209 	switch (reg) {
210 	case WM8904_SW_RESET_AND_ID:
211 	case WM8904_REVISION:
212 	case WM8904_BIAS_CONTROL_0:
213 	case WM8904_VMID_CONTROL_0:
214 	case WM8904_MIC_BIAS_CONTROL_0:
215 	case WM8904_MIC_BIAS_CONTROL_1:
216 	case WM8904_ANALOGUE_DAC_0:
217 	case WM8904_MIC_FILTER_CONTROL:
218 	case WM8904_ANALOGUE_ADC_0:
219 	case WM8904_POWER_MANAGEMENT_0:
220 	case WM8904_POWER_MANAGEMENT_2:
221 	case WM8904_POWER_MANAGEMENT_3:
222 	case WM8904_POWER_MANAGEMENT_6:
223 	case WM8904_CLOCK_RATES_0:
224 	case WM8904_CLOCK_RATES_1:
225 	case WM8904_CLOCK_RATES_2:
226 	case WM8904_AUDIO_INTERFACE_0:
227 	case WM8904_AUDIO_INTERFACE_1:
228 	case WM8904_AUDIO_INTERFACE_2:
229 	case WM8904_AUDIO_INTERFACE_3:
230 	case WM8904_DAC_DIGITAL_VOLUME_LEFT:
231 	case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
232 	case WM8904_DAC_DIGITAL_0:
233 	case WM8904_DAC_DIGITAL_1:
234 	case WM8904_ADC_DIGITAL_VOLUME_LEFT:
235 	case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
236 	case WM8904_ADC_DIGITAL_0:
237 	case WM8904_DIGITAL_MICROPHONE_0:
238 	case WM8904_DRC_0:
239 	case WM8904_DRC_1:
240 	case WM8904_DRC_2:
241 	case WM8904_DRC_3:
242 	case WM8904_ANALOGUE_LEFT_INPUT_0:
243 	case WM8904_ANALOGUE_RIGHT_INPUT_0:
244 	case WM8904_ANALOGUE_LEFT_INPUT_1:
245 	case WM8904_ANALOGUE_RIGHT_INPUT_1:
246 	case WM8904_ANALOGUE_OUT1_LEFT:
247 	case WM8904_ANALOGUE_OUT1_RIGHT:
248 	case WM8904_ANALOGUE_OUT2_LEFT:
249 	case WM8904_ANALOGUE_OUT2_RIGHT:
250 	case WM8904_ANALOGUE_OUT12_ZC:
251 	case WM8904_DC_SERVO_0:
252 	case WM8904_DC_SERVO_1:
253 	case WM8904_DC_SERVO_2:
254 	case WM8904_DC_SERVO_4:
255 	case WM8904_DC_SERVO_5:
256 	case WM8904_DC_SERVO_6:
257 	case WM8904_DC_SERVO_7:
258 	case WM8904_DC_SERVO_8:
259 	case WM8904_DC_SERVO_9:
260 	case WM8904_DC_SERVO_READBACK_0:
261 	case WM8904_ANALOGUE_HP_0:
262 	case WM8904_ANALOGUE_LINEOUT_0:
263 	case WM8904_CHARGE_PUMP_0:
264 	case WM8904_CLASS_W_0:
265 	case WM8904_WRITE_SEQUENCER_0:
266 	case WM8904_WRITE_SEQUENCER_1:
267 	case WM8904_WRITE_SEQUENCER_2:
268 	case WM8904_WRITE_SEQUENCER_3:
269 	case WM8904_WRITE_SEQUENCER_4:
270 	case WM8904_FLL_CONTROL_1:
271 	case WM8904_FLL_CONTROL_2:
272 	case WM8904_FLL_CONTROL_3:
273 	case WM8904_FLL_CONTROL_4:
274 	case WM8904_FLL_CONTROL_5:
275 	case WM8904_GPIO_CONTROL_1:
276 	case WM8904_GPIO_CONTROL_2:
277 	case WM8904_GPIO_CONTROL_3:
278 	case WM8904_GPIO_CONTROL_4:
279 	case WM8904_DIGITAL_PULLS:
280 	case WM8904_INTERRUPT_STATUS:
281 	case WM8904_INTERRUPT_STATUS_MASK:
282 	case WM8904_INTERRUPT_POLARITY:
283 	case WM8904_INTERRUPT_DEBOUNCE:
284 	case WM8904_EQ1:
285 	case WM8904_EQ2:
286 	case WM8904_EQ3:
287 	case WM8904_EQ4:
288 	case WM8904_EQ5:
289 	case WM8904_EQ6:
290 	case WM8904_EQ7:
291 	case WM8904_EQ8:
292 	case WM8904_EQ9:
293 	case WM8904_EQ10:
294 	case WM8904_EQ11:
295 	case WM8904_EQ12:
296 	case WM8904_EQ13:
297 	case WM8904_EQ14:
298 	case WM8904_EQ15:
299 	case WM8904_EQ16:
300 	case WM8904_EQ17:
301 	case WM8904_EQ18:
302 	case WM8904_EQ19:
303 	case WM8904_EQ20:
304 	case WM8904_EQ21:
305 	case WM8904_EQ22:
306 	case WM8904_EQ23:
307 	case WM8904_EQ24:
308 	case WM8904_CONTROL_INTERFACE_TEST_1:
309 	case WM8904_ADC_TEST_0:
310 	case WM8904_ANALOGUE_OUTPUT_BIAS_0:
311 	case WM8904_FLL_NCO_TEST_0:
312 	case WM8904_FLL_NCO_TEST_1:
313 		return true;
314 	default:
315 		return true;
316 	}
317 }
318 
319 static int wm8904_configure_clocking(struct snd_soc_codec *codec)
320 {
321 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
322 	unsigned int clock0, clock2, rate;
323 
324 	/* Gate the clock while we're updating to avoid misclocking */
325 	clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
326 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
327 			    WM8904_SYSCLK_SRC, 0);
328 
329 	/* This should be done on init() for bypass paths */
330 	switch (wm8904->sysclk_src) {
331 	case WM8904_CLK_MCLK:
332 		dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
333 
334 		clock2 &= ~WM8904_SYSCLK_SRC;
335 		rate = wm8904->mclk_rate;
336 
337 		/* Ensure the FLL is stopped */
338 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
339 				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
340 		break;
341 
342 	case WM8904_CLK_FLL:
343 		dev_dbg(codec->dev, "Using %dHz FLL clock\n",
344 			wm8904->fll_fout);
345 
346 		clock2 |= WM8904_SYSCLK_SRC;
347 		rate = wm8904->fll_fout;
348 		break;
349 
350 	default:
351 		dev_err(codec->dev, "System clock not configured\n");
352 		return -EINVAL;
353 	}
354 
355 	/* SYSCLK shouldn't be over 13.5MHz */
356 	if (rate > 13500000) {
357 		clock0 = WM8904_MCLK_DIV;
358 		wm8904->sysclk_rate = rate / 2;
359 	} else {
360 		clock0 = 0;
361 		wm8904->sysclk_rate = rate;
362 	}
363 
364 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
365 			    clock0);
366 
367 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
368 			    WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
369 
370 	dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
371 
372 	return 0;
373 }
374 
375 static void wm8904_set_drc(struct snd_soc_codec *codec)
376 {
377 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
378 	struct wm8904_pdata *pdata = wm8904->pdata;
379 	int save, i;
380 
381 	/* Save any enables; the configuration should clear them. */
382 	save = snd_soc_read(codec, WM8904_DRC_0);
383 
384 	for (i = 0; i < WM8904_DRC_REGS; i++)
385 		snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
386 				    pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
387 
388 	/* Reenable the DRC */
389 	snd_soc_update_bits(codec, WM8904_DRC_0,
390 			    WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
391 }
392 
393 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
394 			       struct snd_ctl_elem_value *ucontrol)
395 {
396 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
397 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
398 	struct wm8904_pdata *pdata = wm8904->pdata;
399 	int value = ucontrol->value.integer.value[0];
400 
401 	if (value >= pdata->num_drc_cfgs)
402 		return -EINVAL;
403 
404 	wm8904->drc_cfg = value;
405 
406 	wm8904_set_drc(codec);
407 
408 	return 0;
409 }
410 
411 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
412 			       struct snd_ctl_elem_value *ucontrol)
413 {
414 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
415 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
416 
417 	ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
418 
419 	return 0;
420 }
421 
422 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
423 {
424 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
425 	struct wm8904_pdata *pdata = wm8904->pdata;
426 	int best, best_val, save, i, cfg;
427 
428 	if (!pdata || !wm8904->num_retune_mobile_texts)
429 		return;
430 
431 	/* Find the version of the currently selected configuration
432 	 * with the nearest sample rate. */
433 	cfg = wm8904->retune_mobile_cfg;
434 	best = 0;
435 	best_val = INT_MAX;
436 	for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
437 		if (strcmp(pdata->retune_mobile_cfgs[i].name,
438 			   wm8904->retune_mobile_texts[cfg]) == 0 &&
439 		    abs(pdata->retune_mobile_cfgs[i].rate
440 			- wm8904->fs) < best_val) {
441 			best = i;
442 			best_val = abs(pdata->retune_mobile_cfgs[i].rate
443 				       - wm8904->fs);
444 		}
445 	}
446 
447 	dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
448 		pdata->retune_mobile_cfgs[best].name,
449 		pdata->retune_mobile_cfgs[best].rate,
450 		wm8904->fs);
451 
452 	/* The EQ will be disabled while reconfiguring it, remember the
453 	 * current configuration.
454 	 */
455 	save = snd_soc_read(codec, WM8904_EQ1);
456 
457 	for (i = 0; i < WM8904_EQ_REGS; i++)
458 		snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
459 				pdata->retune_mobile_cfgs[best].regs[i]);
460 
461 	snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
462 }
463 
464 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
465 					 struct snd_ctl_elem_value *ucontrol)
466 {
467 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
468 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
469 	struct wm8904_pdata *pdata = wm8904->pdata;
470 	int value = ucontrol->value.integer.value[0];
471 
472 	if (value >= pdata->num_retune_mobile_cfgs)
473 		return -EINVAL;
474 
475 	wm8904->retune_mobile_cfg = value;
476 
477 	wm8904_set_retune_mobile(codec);
478 
479 	return 0;
480 }
481 
482 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
483 					 struct snd_ctl_elem_value *ucontrol)
484 {
485 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
486 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
487 
488 	ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
489 
490 	return 0;
491 }
492 
493 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
494 
495 static int wm8904_set_deemph(struct snd_soc_codec *codec)
496 {
497 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
498 	int val, i, best;
499 
500 	/* If we're using deemphasis select the nearest available sample
501 	 * rate.
502 	 */
503 	if (wm8904->deemph) {
504 		best = 1;
505 		for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
506 			if (abs(deemph_settings[i] - wm8904->fs) <
507 			    abs(deemph_settings[best] - wm8904->fs))
508 				best = i;
509 		}
510 
511 		val = best << WM8904_DEEMPH_SHIFT;
512 	} else {
513 		val = 0;
514 	}
515 
516 	dev_dbg(codec->dev, "Set deemphasis %d\n", val);
517 
518 	return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
519 				   WM8904_DEEMPH_MASK, val);
520 }
521 
522 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
523 			     struct snd_ctl_elem_value *ucontrol)
524 {
525 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
526 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
527 
528 	ucontrol->value.enumerated.item[0] = wm8904->deemph;
529 	return 0;
530 }
531 
532 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
533 			      struct snd_ctl_elem_value *ucontrol)
534 {
535 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
536 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
537 	int deemph = ucontrol->value.enumerated.item[0];
538 
539 	if (deemph > 1)
540 		return -EINVAL;
541 
542 	wm8904->deemph = deemph;
543 
544 	return wm8904_set_deemph(codec);
545 }
546 
547 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
548 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
549 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
550 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
551 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
552 
553 static const char *input_mode_text[] = {
554 	"Single-Ended", "Differential Line", "Differential Mic"
555 };
556 
557 static SOC_ENUM_SINGLE_DECL(lin_mode,
558 			    WM8904_ANALOGUE_LEFT_INPUT_1, 0,
559 			    input_mode_text);
560 
561 static SOC_ENUM_SINGLE_DECL(rin_mode,
562 			    WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
563 			    input_mode_text);
564 
565 static const char *hpf_mode_text[] = {
566 	"Hi-fi", "Voice 1", "Voice 2", "Voice 3"
567 };
568 
569 static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
570 			    hpf_mode_text);
571 
572 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
573 			      struct snd_ctl_elem_value *ucontrol)
574 {
575 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
576 	unsigned int val;
577 	int ret;
578 
579 	ret = snd_soc_put_volsw(kcontrol, ucontrol);
580 	if (ret < 0)
581 		return ret;
582 
583 	if (ucontrol->value.integer.value[0])
584 		val = 0;
585 	else
586 		val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
587 
588 	snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
589 			    WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
590 			    val);
591 
592 	return ret;
593 }
594 
595 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
596 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
597 		 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
598 
599 SOC_ENUM("Left Caputure Mode", lin_mode),
600 SOC_ENUM("Right Capture Mode", rin_mode),
601 
602 /* No TLV since it depends on mode */
603 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
604 	     WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
605 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
606 	     WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
607 
608 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
609 SOC_ENUM("High Pass Filter Mode", hpf_mode),
610 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
611 	snd_soc_get_volsw, wm8904_adc_osr_put),
612 };
613 
614 static const char *drc_path_text[] = {
615 	"ADC", "DAC"
616 };
617 
618 static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
619 
620 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
621 SOC_SINGLE_TLV("Digital Playback Boost Volume",
622 	       WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
623 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
624 		 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
625 
626 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
627 		 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
628 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
629 	     WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
630 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
631 	     WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
632 
633 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
634 		 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
635 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
636 	     WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
637 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
638 	     WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
639 
640 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
641 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
642 SOC_ENUM("DRC Path", drc_path),
643 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
644 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
645 		    wm8904_get_deemph, wm8904_put_deemph),
646 };
647 
648 static const struct snd_kcontrol_new wm8904_snd_controls[] = {
649 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
650 	       sidetone_tlv),
651 };
652 
653 static const struct snd_kcontrol_new wm8904_eq_controls[] = {
654 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
655 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
656 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
657 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
658 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
659 };
660 
661 static int cp_event(struct snd_soc_dapm_widget *w,
662 		    struct snd_kcontrol *kcontrol, int event)
663 {
664 	if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
665 		return -EINVAL;
666 
667 	/* Maximum startup time */
668 	udelay(500);
669 
670 	return 0;
671 }
672 
673 static int sysclk_event(struct snd_soc_dapm_widget *w,
674 			 struct snd_kcontrol *kcontrol, int event)
675 {
676 	struct snd_soc_codec *codec = w->codec;
677 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
678 
679 	switch (event) {
680 	case SND_SOC_DAPM_PRE_PMU:
681 		/* If we're using the FLL then we only start it when
682 		 * required; we assume that the configuration has been
683 		 * done previously and all we need to do is kick it
684 		 * off.
685 		 */
686 		switch (wm8904->sysclk_src) {
687 		case WM8904_CLK_FLL:
688 			snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
689 					    WM8904_FLL_OSC_ENA,
690 					    WM8904_FLL_OSC_ENA);
691 
692 			snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
693 					    WM8904_FLL_ENA,
694 					    WM8904_FLL_ENA);
695 			break;
696 
697 		default:
698 			break;
699 		}
700 		break;
701 
702 	case SND_SOC_DAPM_POST_PMD:
703 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
704 				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
705 		break;
706 	}
707 
708 	return 0;
709 }
710 
711 static int out_pga_event(struct snd_soc_dapm_widget *w,
712 			 struct snd_kcontrol *kcontrol, int event)
713 {
714 	struct snd_soc_codec *codec = w->codec;
715 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
716 	int reg, val;
717 	int dcs_mask;
718 	int dcs_l, dcs_r;
719 	int dcs_l_reg, dcs_r_reg;
720 	int timeout;
721 	int pwr_reg;
722 
723 	/* This code is shared between HP and LINEOUT; we do all our
724 	 * power management in stereo pairs to avoid latency issues so
725 	 * we reuse shift to identify which rather than strcmp() the
726 	 * name. */
727 	reg = w->shift;
728 
729 	switch (reg) {
730 	case WM8904_ANALOGUE_HP_0:
731 		pwr_reg = WM8904_POWER_MANAGEMENT_2;
732 		dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
733 		dcs_r_reg = WM8904_DC_SERVO_8;
734 		dcs_l_reg = WM8904_DC_SERVO_9;
735 		dcs_l = 0;
736 		dcs_r = 1;
737 		break;
738 	case WM8904_ANALOGUE_LINEOUT_0:
739 		pwr_reg = WM8904_POWER_MANAGEMENT_3;
740 		dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
741 		dcs_r_reg = WM8904_DC_SERVO_6;
742 		dcs_l_reg = WM8904_DC_SERVO_7;
743 		dcs_l = 2;
744 		dcs_r = 3;
745 		break;
746 	default:
747 		WARN(1, "Invalid reg %d\n", reg);
748 		return -EINVAL;
749 	}
750 
751 	switch (event) {
752 	case SND_SOC_DAPM_PRE_PMU:
753 		/* Power on the PGAs */
754 		snd_soc_update_bits(codec, pwr_reg,
755 				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
756 				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
757 
758 		/* Power on the amplifier */
759 		snd_soc_update_bits(codec, reg,
760 				    WM8904_HPL_ENA | WM8904_HPR_ENA,
761 				    WM8904_HPL_ENA | WM8904_HPR_ENA);
762 
763 
764 		/* Enable the first stage */
765 		snd_soc_update_bits(codec, reg,
766 				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
767 				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
768 
769 		/* Power up the DC servo */
770 		snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
771 				    dcs_mask, dcs_mask);
772 
773 		/* Either calibrate the DC servo or restore cached state
774 		 * if we have that.
775 		 */
776 		if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
777 			dev_dbg(codec->dev, "Restoring DC servo state\n");
778 
779 			snd_soc_write(codec, dcs_l_reg,
780 				      wm8904->dcs_state[dcs_l]);
781 			snd_soc_write(codec, dcs_r_reg,
782 				      wm8904->dcs_state[dcs_r]);
783 
784 			snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
785 
786 			timeout = 20;
787 		} else {
788 			dev_dbg(codec->dev, "Calibrating DC servo\n");
789 
790 			snd_soc_write(codec, WM8904_DC_SERVO_1,
791 				dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
792 
793 			timeout = 500;
794 		}
795 
796 		/* Wait for DC servo to complete */
797 		dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
798 		do {
799 			val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
800 			if ((val & dcs_mask) == dcs_mask)
801 				break;
802 
803 			msleep(1);
804 		} while (--timeout);
805 
806 		if ((val & dcs_mask) != dcs_mask)
807 			dev_warn(codec->dev, "DC servo timed out\n");
808 		else
809 			dev_dbg(codec->dev, "DC servo ready\n");
810 
811 		/* Enable the output stage */
812 		snd_soc_update_bits(codec, reg,
813 				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
814 				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
815 		break;
816 
817 	case SND_SOC_DAPM_POST_PMU:
818 		/* Unshort the output itself */
819 		snd_soc_update_bits(codec, reg,
820 				    WM8904_HPL_RMV_SHORT |
821 				    WM8904_HPR_RMV_SHORT,
822 				    WM8904_HPL_RMV_SHORT |
823 				    WM8904_HPR_RMV_SHORT);
824 
825 		break;
826 
827 	case SND_SOC_DAPM_PRE_PMD:
828 		/* Short the output */
829 		snd_soc_update_bits(codec, reg,
830 				    WM8904_HPL_RMV_SHORT |
831 				    WM8904_HPR_RMV_SHORT, 0);
832 		break;
833 
834 	case SND_SOC_DAPM_POST_PMD:
835 		/* Cache the DC servo configuration; this will be
836 		 * invalidated if we change the configuration. */
837 		wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
838 		wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
839 
840 		snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
841 				    dcs_mask, 0);
842 
843 		/* Disable the amplifier input and output stages */
844 		snd_soc_update_bits(codec, reg,
845 				    WM8904_HPL_ENA | WM8904_HPR_ENA |
846 				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
847 				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
848 				    0);
849 
850 		/* PGAs too */
851 		snd_soc_update_bits(codec, pwr_reg,
852 				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
853 				    0);
854 		break;
855 	}
856 
857 	return 0;
858 }
859 
860 static const char *lin_text[] = {
861 	"IN1L", "IN2L", "IN3L"
862 };
863 
864 static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
865 			    lin_text);
866 
867 static const struct snd_kcontrol_new lin_mux =
868 	SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
869 
870 static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
871 			    lin_text);
872 
873 static const struct snd_kcontrol_new lin_inv_mux =
874 	SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
875 
876 static const char *rin_text[] = {
877 	"IN1R", "IN2R", "IN3R"
878 };
879 
880 static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
881 			    rin_text);
882 
883 static const struct snd_kcontrol_new rin_mux =
884 	SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
885 
886 static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
887 			    rin_text);
888 
889 static const struct snd_kcontrol_new rin_inv_mux =
890 	SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
891 
892 static const char *aif_text[] = {
893 	"Left", "Right"
894 };
895 
896 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
897 			    aif_text);
898 
899 static const struct snd_kcontrol_new aifoutl_mux =
900 	SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
901 
902 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
903 			    aif_text);
904 
905 static const struct snd_kcontrol_new aifoutr_mux =
906 	SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
907 
908 static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
909 			    aif_text);
910 
911 static const struct snd_kcontrol_new aifinl_mux =
912 	SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
913 
914 static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
915 			    aif_text);
916 
917 static const struct snd_kcontrol_new aifinr_mux =
918 	SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
919 
920 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
921 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
922 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
923 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
924 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
925 };
926 
927 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
928 SND_SOC_DAPM_INPUT("IN1L"),
929 SND_SOC_DAPM_INPUT("IN1R"),
930 SND_SOC_DAPM_INPUT("IN2L"),
931 SND_SOC_DAPM_INPUT("IN2R"),
932 SND_SOC_DAPM_INPUT("IN3L"),
933 SND_SOC_DAPM_INPUT("IN3R"),
934 
935 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
936 
937 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
938 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
939 		 &lin_inv_mux),
940 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
941 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
942 		 &rin_inv_mux),
943 
944 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
945 		 NULL, 0),
946 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
947 		 NULL, 0),
948 
949 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
950 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
951 
952 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
953 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
954 
955 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
956 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
957 };
958 
959 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
960 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
961 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
962 
963 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
964 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
965 
966 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
967 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
968 
969 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
970 		    SND_SOC_DAPM_POST_PMU),
971 
972 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
973 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
974 
975 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
976 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
977 
978 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
979 		   0, NULL, 0, out_pga_event,
980 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
981 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
982 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
983 		   0, NULL, 0, out_pga_event,
984 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
985 		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
986 
987 SND_SOC_DAPM_OUTPUT("HPOUTL"),
988 SND_SOC_DAPM_OUTPUT("HPOUTR"),
989 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
990 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
991 };
992 
993 static const char *out_mux_text[] = {
994 	"DAC", "Bypass"
995 };
996 
997 static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
998 			    out_mux_text);
999 
1000 static const struct snd_kcontrol_new hpl_mux =
1001 	SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1002 
1003 static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1004 			    out_mux_text);
1005 
1006 static const struct snd_kcontrol_new hpr_mux =
1007 	SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1008 
1009 static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1010 			    out_mux_text);
1011 
1012 static const struct snd_kcontrol_new linel_mux =
1013 	SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1014 
1015 static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1016 			    out_mux_text);
1017 
1018 static const struct snd_kcontrol_new liner_mux =
1019 	SOC_DAPM_ENUM("LINER Mux", liner_enum);
1020 
1021 static const char *sidetone_text[] = {
1022 	"None", "Left", "Right"
1023 };
1024 
1025 static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1026 			    sidetone_text);
1027 
1028 static const struct snd_kcontrol_new dacl_sidetone_mux =
1029 	SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1030 
1031 static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1032 			    sidetone_text);
1033 
1034 static const struct snd_kcontrol_new dacr_sidetone_mux =
1035 	SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1036 
1037 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1038 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1039 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1040 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1041 
1042 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1043 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1044 
1045 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1046 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1047 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1048 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1049 };
1050 
1051 static const struct snd_soc_dapm_route core_intercon[] = {
1052 	{ "CLK_DSP", NULL, "SYSCLK" },
1053 	{ "TOCLK", NULL, "SYSCLK" },
1054 };
1055 
1056 static const struct snd_soc_dapm_route adc_intercon[] = {
1057 	{ "Left Capture Mux", "IN1L", "IN1L" },
1058 	{ "Left Capture Mux", "IN2L", "IN2L" },
1059 	{ "Left Capture Mux", "IN3L", "IN3L" },
1060 
1061 	{ "Left Capture Inverting Mux", "IN1L", "IN1L" },
1062 	{ "Left Capture Inverting Mux", "IN2L", "IN2L" },
1063 	{ "Left Capture Inverting Mux", "IN3L", "IN3L" },
1064 
1065 	{ "Right Capture Mux", "IN1R", "IN1R" },
1066 	{ "Right Capture Mux", "IN2R", "IN2R" },
1067 	{ "Right Capture Mux", "IN3R", "IN3R" },
1068 
1069 	{ "Right Capture Inverting Mux", "IN1R", "IN1R" },
1070 	{ "Right Capture Inverting Mux", "IN2R", "IN2R" },
1071 	{ "Right Capture Inverting Mux", "IN3R", "IN3R" },
1072 
1073 	{ "Left Capture PGA", NULL, "Left Capture Mux" },
1074 	{ "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1075 
1076 	{ "Right Capture PGA", NULL, "Right Capture Mux" },
1077 	{ "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1078 
1079 	{ "AIFOUTL", "Left",  "ADCL" },
1080 	{ "AIFOUTL", "Right", "ADCR" },
1081 	{ "AIFOUTR", "Left",  "ADCL" },
1082 	{ "AIFOUTR", "Right", "ADCR" },
1083 
1084 	{ "ADCL", NULL, "CLK_DSP" },
1085 	{ "ADCL", NULL, "Left Capture PGA" },
1086 
1087 	{ "ADCR", NULL, "CLK_DSP" },
1088 	{ "ADCR", NULL, "Right Capture PGA" },
1089 };
1090 
1091 static const struct snd_soc_dapm_route dac_intercon[] = {
1092 	{ "DACL", "Right", "AIFINR" },
1093 	{ "DACL", "Left",  "AIFINL" },
1094 	{ "DACL", NULL, "CLK_DSP" },
1095 
1096 	{ "DACR", "Right", "AIFINR" },
1097 	{ "DACR", "Left",  "AIFINL" },
1098 	{ "DACR", NULL, "CLK_DSP" },
1099 
1100 	{ "Charge pump", NULL, "SYSCLK" },
1101 
1102 	{ "Headphone Output", NULL, "HPL PGA" },
1103 	{ "Headphone Output", NULL, "HPR PGA" },
1104 	{ "Headphone Output", NULL, "Charge pump" },
1105 	{ "Headphone Output", NULL, "TOCLK" },
1106 
1107 	{ "Line Output", NULL, "LINEL PGA" },
1108 	{ "Line Output", NULL, "LINER PGA" },
1109 	{ "Line Output", NULL, "Charge pump" },
1110 	{ "Line Output", NULL, "TOCLK" },
1111 
1112 	{ "HPOUTL", NULL, "Headphone Output" },
1113 	{ "HPOUTR", NULL, "Headphone Output" },
1114 
1115 	{ "LINEOUTL", NULL, "Line Output" },
1116 	{ "LINEOUTR", NULL, "Line Output" },
1117 };
1118 
1119 static const struct snd_soc_dapm_route wm8904_intercon[] = {
1120 	{ "Left Sidetone", "Left", "ADCL" },
1121 	{ "Left Sidetone", "Right", "ADCR" },
1122 	{ "DACL", NULL, "Left Sidetone" },
1123 
1124 	{ "Right Sidetone", "Left", "ADCL" },
1125 	{ "Right Sidetone", "Right", "ADCR" },
1126 	{ "DACR", NULL, "Right Sidetone" },
1127 
1128 	{ "Left Bypass", NULL, "Class G" },
1129 	{ "Left Bypass", NULL, "Left Capture PGA" },
1130 
1131 	{ "Right Bypass", NULL, "Class G" },
1132 	{ "Right Bypass", NULL, "Right Capture PGA" },
1133 
1134 	{ "HPL Mux", "DAC", "DACL" },
1135 	{ "HPL Mux", "Bypass", "Left Bypass" },
1136 
1137 	{ "HPR Mux", "DAC", "DACR" },
1138 	{ "HPR Mux", "Bypass", "Right Bypass" },
1139 
1140 	{ "LINEL Mux", "DAC", "DACL" },
1141 	{ "LINEL Mux", "Bypass", "Left Bypass" },
1142 
1143 	{ "LINER Mux", "DAC", "DACR" },
1144 	{ "LINER Mux", "Bypass", "Right Bypass" },
1145 
1146 	{ "HPL PGA", NULL, "HPL Mux" },
1147 	{ "HPR PGA", NULL, "HPR Mux" },
1148 
1149 	{ "LINEL PGA", NULL, "LINEL Mux" },
1150 	{ "LINER PGA", NULL, "LINER Mux" },
1151 };
1152 
1153 static const struct snd_soc_dapm_route wm8912_intercon[] = {
1154 	{ "HPL PGA", NULL, "DACL" },
1155 	{ "HPR PGA", NULL, "DACR" },
1156 
1157 	{ "LINEL PGA", NULL, "DACL" },
1158 	{ "LINER PGA", NULL, "DACR" },
1159 };
1160 
1161 static int wm8904_add_widgets(struct snd_soc_codec *codec)
1162 {
1163 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1164 	struct snd_soc_dapm_context *dapm = &codec->dapm;
1165 
1166 	snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1167 				  ARRAY_SIZE(wm8904_core_dapm_widgets));
1168 	snd_soc_dapm_add_routes(dapm, core_intercon,
1169 				ARRAY_SIZE(core_intercon));
1170 
1171 	switch (wm8904->devtype) {
1172 	case WM8904:
1173 		snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
1174 				     ARRAY_SIZE(wm8904_adc_snd_controls));
1175 		snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1176 				     ARRAY_SIZE(wm8904_dac_snd_controls));
1177 		snd_soc_add_codec_controls(codec, wm8904_snd_controls,
1178 				     ARRAY_SIZE(wm8904_snd_controls));
1179 
1180 		snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1181 					  ARRAY_SIZE(wm8904_adc_dapm_widgets));
1182 		snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1183 					  ARRAY_SIZE(wm8904_dac_dapm_widgets));
1184 		snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1185 					  ARRAY_SIZE(wm8904_dapm_widgets));
1186 
1187 		snd_soc_dapm_add_routes(dapm, adc_intercon,
1188 					ARRAY_SIZE(adc_intercon));
1189 		snd_soc_dapm_add_routes(dapm, dac_intercon,
1190 					ARRAY_SIZE(dac_intercon));
1191 		snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1192 					ARRAY_SIZE(wm8904_intercon));
1193 		break;
1194 
1195 	case WM8912:
1196 		snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1197 				     ARRAY_SIZE(wm8904_dac_snd_controls));
1198 
1199 		snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1200 					  ARRAY_SIZE(wm8904_dac_dapm_widgets));
1201 
1202 		snd_soc_dapm_add_routes(dapm, dac_intercon,
1203 					ARRAY_SIZE(dac_intercon));
1204 		snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1205 					ARRAY_SIZE(wm8912_intercon));
1206 		break;
1207 	}
1208 
1209 	return 0;
1210 }
1211 
1212 static struct {
1213 	int ratio;
1214 	unsigned int clk_sys_rate;
1215 } clk_sys_rates[] = {
1216 	{   64,  0 },
1217 	{  128,  1 },
1218 	{  192,  2 },
1219 	{  256,  3 },
1220 	{  384,  4 },
1221 	{  512,  5 },
1222 	{  786,  6 },
1223 	{ 1024,  7 },
1224 	{ 1408,  8 },
1225 	{ 1536,  9 },
1226 };
1227 
1228 static struct {
1229 	int rate;
1230 	int sample_rate;
1231 } sample_rates[] = {
1232 	{ 8000,  0  },
1233 	{ 11025, 1  },
1234 	{ 12000, 1  },
1235 	{ 16000, 2  },
1236 	{ 22050, 3  },
1237 	{ 24000, 3  },
1238 	{ 32000, 4  },
1239 	{ 44100, 5  },
1240 	{ 48000, 5  },
1241 };
1242 
1243 static struct {
1244 	int div; /* *10 due to .5s */
1245 	int bclk_div;
1246 } bclk_divs[] = {
1247 	{ 10,  0  },
1248 	{ 15,  1  },
1249 	{ 20,  2  },
1250 	{ 30,  3  },
1251 	{ 40,  4  },
1252 	{ 50,  5  },
1253 	{ 55,  6  },
1254 	{ 60,  7  },
1255 	{ 80,  8  },
1256 	{ 100, 9  },
1257 	{ 110, 10 },
1258 	{ 120, 11 },
1259 	{ 160, 12 },
1260 	{ 200, 13 },
1261 	{ 220, 14 },
1262 	{ 240, 16 },
1263 	{ 200, 17 },
1264 	{ 320, 18 },
1265 	{ 440, 19 },
1266 	{ 480, 20 },
1267 };
1268 
1269 
1270 static int wm8904_hw_params(struct snd_pcm_substream *substream,
1271 			    struct snd_pcm_hw_params *params,
1272 			    struct snd_soc_dai *dai)
1273 {
1274 	struct snd_soc_codec *codec = dai->codec;
1275 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1276 	int ret, i, best, best_val, cur_val;
1277 	unsigned int aif1 = 0;
1278 	unsigned int aif2 = 0;
1279 	unsigned int aif3 = 0;
1280 	unsigned int clock1 = 0;
1281 	unsigned int dac_digital1 = 0;
1282 
1283 	/* What BCLK do we need? */
1284 	wm8904->fs = params_rate(params);
1285 	if (wm8904->tdm_slots) {
1286 		dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1287 			wm8904->tdm_slots, wm8904->tdm_width);
1288 		wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1289 						 wm8904->tdm_width, 2,
1290 						 wm8904->tdm_slots);
1291 	} else {
1292 		wm8904->bclk = snd_soc_params_to_bclk(params);
1293 	}
1294 
1295 	switch (params_width(params)) {
1296 	case 16:
1297 		break;
1298 	case 20:
1299 		aif1 |= 0x40;
1300 		break;
1301 	case 24:
1302 		aif1 |= 0x80;
1303 		break;
1304 	case 32:
1305 		aif1 |= 0xc0;
1306 		break;
1307 	default:
1308 		return -EINVAL;
1309 	}
1310 
1311 
1312 	dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1313 
1314 	ret = wm8904_configure_clocking(codec);
1315 	if (ret != 0)
1316 		return ret;
1317 
1318 	/* Select nearest CLK_SYS_RATE */
1319 	best = 0;
1320 	best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1321 		       - wm8904->fs);
1322 	for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1323 		cur_val = abs((wm8904->sysclk_rate /
1324 			       clk_sys_rates[i].ratio) - wm8904->fs);
1325 		if (cur_val < best_val) {
1326 			best = i;
1327 			best_val = cur_val;
1328 		}
1329 	}
1330 	dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1331 		clk_sys_rates[best].ratio);
1332 	clock1 |= (clk_sys_rates[best].clk_sys_rate
1333 		   << WM8904_CLK_SYS_RATE_SHIFT);
1334 
1335 	/* SAMPLE_RATE */
1336 	best = 0;
1337 	best_val = abs(wm8904->fs - sample_rates[0].rate);
1338 	for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1339 		/* Closest match */
1340 		cur_val = abs(wm8904->fs - sample_rates[i].rate);
1341 		if (cur_val < best_val) {
1342 			best = i;
1343 			best_val = cur_val;
1344 		}
1345 	}
1346 	dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1347 		sample_rates[best].rate);
1348 	clock1 |= (sample_rates[best].sample_rate
1349 		   << WM8904_SAMPLE_RATE_SHIFT);
1350 
1351 	/* Enable sloping stopband filter for low sample rates */
1352 	if (wm8904->fs <= 24000)
1353 		dac_digital1 |= WM8904_DAC_SB_FILT;
1354 
1355 	/* BCLK_DIV */
1356 	best = 0;
1357 	best_val = INT_MAX;
1358 	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1359 		cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1360 			- wm8904->bclk;
1361 		if (cur_val < 0) /* Table is sorted */
1362 			break;
1363 		if (cur_val < best_val) {
1364 			best = i;
1365 			best_val = cur_val;
1366 		}
1367 	}
1368 	wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1369 	dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1370 		bclk_divs[best].div, wm8904->bclk);
1371 	aif2 |= bclk_divs[best].bclk_div;
1372 
1373 	/* LRCLK is a simple fraction of BCLK */
1374 	dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1375 	aif3 |= wm8904->bclk / wm8904->fs;
1376 
1377 	/* Apply the settings */
1378 	snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1379 			    WM8904_DAC_SB_FILT, dac_digital1);
1380 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1381 			    WM8904_AIF_WL_MASK, aif1);
1382 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1383 			    WM8904_BCLK_DIV_MASK, aif2);
1384 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1385 			    WM8904_LRCLK_RATE_MASK, aif3);
1386 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1387 			    WM8904_SAMPLE_RATE_MASK |
1388 			    WM8904_CLK_SYS_RATE_MASK, clock1);
1389 
1390 	/* Update filters for the new settings */
1391 	wm8904_set_retune_mobile(codec);
1392 	wm8904_set_deemph(codec);
1393 
1394 	return 0;
1395 }
1396 
1397 
1398 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1399 			     unsigned int freq, int dir)
1400 {
1401 	struct snd_soc_codec *codec = dai->codec;
1402 	struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
1403 
1404 	switch (clk_id) {
1405 	case WM8904_CLK_MCLK:
1406 		priv->sysclk_src = clk_id;
1407 		priv->mclk_rate = freq;
1408 		break;
1409 
1410 	case WM8904_CLK_FLL:
1411 		priv->sysclk_src = clk_id;
1412 		break;
1413 
1414 	default:
1415 		return -EINVAL;
1416 	}
1417 
1418 	dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1419 
1420 	wm8904_configure_clocking(codec);
1421 
1422 	return 0;
1423 }
1424 
1425 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1426 {
1427 	struct snd_soc_codec *codec = dai->codec;
1428 	unsigned int aif1 = 0;
1429 	unsigned int aif3 = 0;
1430 
1431 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1432 	case SND_SOC_DAIFMT_CBS_CFS:
1433 		break;
1434 	case SND_SOC_DAIFMT_CBS_CFM:
1435 		aif3 |= WM8904_LRCLK_DIR;
1436 		break;
1437 	case SND_SOC_DAIFMT_CBM_CFS:
1438 		aif1 |= WM8904_BCLK_DIR;
1439 		break;
1440 	case SND_SOC_DAIFMT_CBM_CFM:
1441 		aif1 |= WM8904_BCLK_DIR;
1442 		aif3 |= WM8904_LRCLK_DIR;
1443 		break;
1444 	default:
1445 		return -EINVAL;
1446 	}
1447 
1448 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1449 	case SND_SOC_DAIFMT_DSP_B:
1450 		aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
1451 	case SND_SOC_DAIFMT_DSP_A:
1452 		aif1 |= 0x3;
1453 		break;
1454 	case SND_SOC_DAIFMT_I2S:
1455 		aif1 |= 0x2;
1456 		break;
1457 	case SND_SOC_DAIFMT_RIGHT_J:
1458 		break;
1459 	case SND_SOC_DAIFMT_LEFT_J:
1460 		aif1 |= 0x1;
1461 		break;
1462 	default:
1463 		return -EINVAL;
1464 	}
1465 
1466 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1467 	case SND_SOC_DAIFMT_DSP_A:
1468 	case SND_SOC_DAIFMT_DSP_B:
1469 		/* frame inversion not valid for DSP modes */
1470 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1471 		case SND_SOC_DAIFMT_NB_NF:
1472 			break;
1473 		case SND_SOC_DAIFMT_IB_NF:
1474 			aif1 |= WM8904_AIF_BCLK_INV;
1475 			break;
1476 		default:
1477 			return -EINVAL;
1478 		}
1479 		break;
1480 
1481 	case SND_SOC_DAIFMT_I2S:
1482 	case SND_SOC_DAIFMT_RIGHT_J:
1483 	case SND_SOC_DAIFMT_LEFT_J:
1484 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1485 		case SND_SOC_DAIFMT_NB_NF:
1486 			break;
1487 		case SND_SOC_DAIFMT_IB_IF:
1488 			aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1489 			break;
1490 		case SND_SOC_DAIFMT_IB_NF:
1491 			aif1 |= WM8904_AIF_BCLK_INV;
1492 			break;
1493 		case SND_SOC_DAIFMT_NB_IF:
1494 			aif1 |= WM8904_AIF_LRCLK_INV;
1495 			break;
1496 		default:
1497 			return -EINVAL;
1498 		}
1499 		break;
1500 	default:
1501 		return -EINVAL;
1502 	}
1503 
1504 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1505 			    WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1506 			    WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1507 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1508 			    WM8904_LRCLK_DIR, aif3);
1509 
1510 	return 0;
1511 }
1512 
1513 
1514 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1515 			       unsigned int rx_mask, int slots, int slot_width)
1516 {
1517 	struct snd_soc_codec *codec = dai->codec;
1518 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1519 	int aif1 = 0;
1520 
1521 	/* Don't need to validate anything if we're turning off TDM */
1522 	if (slots == 0)
1523 		goto out;
1524 
1525 	/* Note that we allow configurations we can't handle ourselves -
1526 	 * for example, we can generate clocks for slots 2 and up even if
1527 	 * we can't use those slots ourselves.
1528 	 */
1529 	aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1530 
1531 	switch (rx_mask) {
1532 	case 3:
1533 		break;
1534 	case 0xc:
1535 		aif1 |= WM8904_AIFADC_TDM_CHAN;
1536 		break;
1537 	default:
1538 		return -EINVAL;
1539 	}
1540 
1541 
1542 	switch (tx_mask) {
1543 	case 3:
1544 		break;
1545 	case 0xc:
1546 		aif1 |= WM8904_AIFDAC_TDM_CHAN;
1547 		break;
1548 	default:
1549 		return -EINVAL;
1550 	}
1551 
1552 out:
1553 	wm8904->tdm_width = slot_width;
1554 	wm8904->tdm_slots = slots / 2;
1555 
1556 	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1557 			    WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1558 			    WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1559 
1560 	return 0;
1561 }
1562 
1563 struct _fll_div {
1564 	u16 fll_fratio;
1565 	u16 fll_outdiv;
1566 	u16 fll_clk_ref_div;
1567 	u16 n;
1568 	u16 k;
1569 };
1570 
1571 /* The size in bits of the FLL divide multiplied by 10
1572  * to allow rounding later */
1573 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1574 
1575 static struct {
1576 	unsigned int min;
1577 	unsigned int max;
1578 	u16 fll_fratio;
1579 	int ratio;
1580 } fll_fratios[] = {
1581 	{       0,    64000, 4, 16 },
1582 	{   64000,   128000, 3,  8 },
1583 	{  128000,   256000, 2,  4 },
1584 	{  256000,  1000000, 1,  2 },
1585 	{ 1000000, 13500000, 0,  1 },
1586 };
1587 
1588 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1589 		       unsigned int Fout)
1590 {
1591 	u64 Kpart;
1592 	unsigned int K, Ndiv, Nmod, target;
1593 	unsigned int div;
1594 	int i;
1595 
1596 	/* Fref must be <=13.5MHz */
1597 	div = 1;
1598 	fll_div->fll_clk_ref_div = 0;
1599 	while ((Fref / div) > 13500000) {
1600 		div *= 2;
1601 		fll_div->fll_clk_ref_div++;
1602 
1603 		if (div > 8) {
1604 			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1605 			       Fref);
1606 			return -EINVAL;
1607 		}
1608 	}
1609 
1610 	pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1611 
1612 	/* Apply the division for our remaining calculations */
1613 	Fref /= div;
1614 
1615 	/* Fvco should be 90-100MHz; don't check the upper bound */
1616 	div = 4;
1617 	while (Fout * div < 90000000) {
1618 		div++;
1619 		if (div > 64) {
1620 			pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1621 			       Fout);
1622 			return -EINVAL;
1623 		}
1624 	}
1625 	target = Fout * div;
1626 	fll_div->fll_outdiv = div - 1;
1627 
1628 	pr_debug("Fvco=%dHz\n", target);
1629 
1630 	/* Find an appropriate FLL_FRATIO and factor it out of the target */
1631 	for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1632 		if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1633 			fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1634 			target /= fll_fratios[i].ratio;
1635 			break;
1636 		}
1637 	}
1638 	if (i == ARRAY_SIZE(fll_fratios)) {
1639 		pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1640 		return -EINVAL;
1641 	}
1642 
1643 	/* Now, calculate N.K */
1644 	Ndiv = target / Fref;
1645 
1646 	fll_div->n = Ndiv;
1647 	Nmod = target % Fref;
1648 	pr_debug("Nmod=%d\n", Nmod);
1649 
1650 	/* Calculate fractional part - scale up so we can round. */
1651 	Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1652 
1653 	do_div(Kpart, Fref);
1654 
1655 	K = Kpart & 0xFFFFFFFF;
1656 
1657 	if ((K % 10) >= 5)
1658 		K += 5;
1659 
1660 	/* Move down to proper range now rounding is done */
1661 	fll_div->k = K / 10;
1662 
1663 	pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1664 		 fll_div->n, fll_div->k,
1665 		 fll_div->fll_fratio, fll_div->fll_outdiv,
1666 		 fll_div->fll_clk_ref_div);
1667 
1668 	return 0;
1669 }
1670 
1671 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1672 			  unsigned int Fref, unsigned int Fout)
1673 {
1674 	struct snd_soc_codec *codec = dai->codec;
1675 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1676 	struct _fll_div fll_div;
1677 	int ret, val;
1678 	int clock2, fll1;
1679 
1680 	/* Any change? */
1681 	if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1682 	    Fout == wm8904->fll_fout)
1683 		return 0;
1684 
1685 	clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1686 
1687 	if (Fout == 0) {
1688 		dev_dbg(codec->dev, "FLL disabled\n");
1689 
1690 		wm8904->fll_fref = 0;
1691 		wm8904->fll_fout = 0;
1692 
1693 		/* Gate SYSCLK to avoid glitches */
1694 		snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1695 				    WM8904_CLK_SYS_ENA, 0);
1696 
1697 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1698 				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1699 
1700 		goto out;
1701 	}
1702 
1703 	/* Validate the FLL ID */
1704 	switch (source) {
1705 	case WM8904_FLL_MCLK:
1706 	case WM8904_FLL_LRCLK:
1707 	case WM8904_FLL_BCLK:
1708 		ret = fll_factors(&fll_div, Fref, Fout);
1709 		if (ret != 0)
1710 			return ret;
1711 		break;
1712 
1713 	case WM8904_FLL_FREE_RUNNING:
1714 		dev_dbg(codec->dev, "Using free running FLL\n");
1715 		/* Force 12MHz and output/4 for now */
1716 		Fout = 12000000;
1717 		Fref = 12000000;
1718 
1719 		memset(&fll_div, 0, sizeof(fll_div));
1720 		fll_div.fll_outdiv = 3;
1721 		break;
1722 
1723 	default:
1724 		dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1725 		return -EINVAL;
1726 	}
1727 
1728 	/* Save current state then disable the FLL and SYSCLK to avoid
1729 	 * misclocking */
1730 	fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1731 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1732 			    WM8904_CLK_SYS_ENA, 0);
1733 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1734 			    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1735 
1736 	/* Unlock forced oscilator control to switch it on/off */
1737 	snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1738 			    WM8904_USER_KEY, WM8904_USER_KEY);
1739 
1740 	if (fll_id == WM8904_FLL_FREE_RUNNING) {
1741 		val = WM8904_FLL_FRC_NCO;
1742 	} else {
1743 		val = 0;
1744 	}
1745 
1746 	snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1747 			    val);
1748 	snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1749 			    WM8904_USER_KEY, 0);
1750 
1751 	switch (fll_id) {
1752 	case WM8904_FLL_MCLK:
1753 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1754 				    WM8904_FLL_CLK_REF_SRC_MASK, 0);
1755 		break;
1756 
1757 	case WM8904_FLL_LRCLK:
1758 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1759 				    WM8904_FLL_CLK_REF_SRC_MASK, 1);
1760 		break;
1761 
1762 	case WM8904_FLL_BCLK:
1763 		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1764 				    WM8904_FLL_CLK_REF_SRC_MASK, 2);
1765 		break;
1766 	}
1767 
1768 	if (fll_div.k)
1769 		val = WM8904_FLL_FRACN_ENA;
1770 	else
1771 		val = 0;
1772 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1773 			    WM8904_FLL_FRACN_ENA, val);
1774 
1775 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1776 			    WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1777 			    (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1778 			    (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1779 
1780 	snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1781 
1782 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1783 			    fll_div.n << WM8904_FLL_N_SHIFT);
1784 
1785 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1786 			    WM8904_FLL_CLK_REF_DIV_MASK,
1787 			    fll_div.fll_clk_ref_div
1788 			    << WM8904_FLL_CLK_REF_DIV_SHIFT);
1789 
1790 	dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1791 
1792 	wm8904->fll_fref = Fref;
1793 	wm8904->fll_fout = Fout;
1794 	wm8904->fll_src = source;
1795 
1796 	/* Enable the FLL if it was previously active */
1797 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1798 			    WM8904_FLL_OSC_ENA, fll1);
1799 	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1800 			    WM8904_FLL_ENA, fll1);
1801 
1802 out:
1803 	/* Reenable SYSCLK if it was previously active */
1804 	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1805 			    WM8904_CLK_SYS_ENA, clock2);
1806 
1807 	return 0;
1808 }
1809 
1810 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1811 {
1812 	struct snd_soc_codec *codec = codec_dai->codec;
1813 	int val;
1814 
1815 	if (mute)
1816 		val = WM8904_DAC_MUTE;
1817 	else
1818 		val = 0;
1819 
1820 	snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1821 
1822 	return 0;
1823 }
1824 
1825 static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1826 				 enum snd_soc_bias_level level)
1827 {
1828 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1829 	int ret;
1830 
1831 	switch (level) {
1832 	case SND_SOC_BIAS_ON:
1833 		clk_prepare_enable(wm8904->mclk);
1834 		break;
1835 
1836 	case SND_SOC_BIAS_PREPARE:
1837 		/* VMID resistance 2*50k */
1838 		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1839 				    WM8904_VMID_RES_MASK,
1840 				    0x1 << WM8904_VMID_RES_SHIFT);
1841 
1842 		/* Normal bias current */
1843 		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1844 				    WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1845 		break;
1846 
1847 	case SND_SOC_BIAS_STANDBY:
1848 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1849 			ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1850 						    wm8904->supplies);
1851 			if (ret != 0) {
1852 				dev_err(codec->dev,
1853 					"Failed to enable supplies: %d\n",
1854 					ret);
1855 				return ret;
1856 			}
1857 
1858 			regcache_cache_only(wm8904->regmap, false);
1859 			regcache_sync(wm8904->regmap);
1860 
1861 			/* Enable bias */
1862 			snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1863 					    WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1864 
1865 			/* Enable VMID, VMID buffering, 2*5k resistance */
1866 			snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1867 					    WM8904_VMID_ENA |
1868 					    WM8904_VMID_RES_MASK,
1869 					    WM8904_VMID_ENA |
1870 					    0x3 << WM8904_VMID_RES_SHIFT);
1871 
1872 			/* Let VMID ramp */
1873 			msleep(1);
1874 		}
1875 
1876 		/* Maintain VMID with 2*250k */
1877 		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1878 				    WM8904_VMID_RES_MASK,
1879 				    0x2 << WM8904_VMID_RES_SHIFT);
1880 
1881 		/* Bias current *0.5 */
1882 		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1883 				    WM8904_ISEL_MASK, 0);
1884 		break;
1885 
1886 	case SND_SOC_BIAS_OFF:
1887 		/* Turn off VMID */
1888 		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1889 				    WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1890 
1891 		/* Stop bias generation */
1892 		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1893 				    WM8904_BIAS_ENA, 0);
1894 
1895 		regcache_cache_only(wm8904->regmap, true);
1896 		regcache_mark_dirty(wm8904->regmap);
1897 
1898 		regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1899 				       wm8904->supplies);
1900 		clk_disable_unprepare(wm8904->mclk);
1901 		break;
1902 	}
1903 	codec->dapm.bias_level = level;
1904 	return 0;
1905 }
1906 
1907 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1908 
1909 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1910 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1911 
1912 static const struct snd_soc_dai_ops wm8904_dai_ops = {
1913 	.set_sysclk = wm8904_set_sysclk,
1914 	.set_fmt = wm8904_set_fmt,
1915 	.set_tdm_slot = wm8904_set_tdm_slot,
1916 	.set_pll = wm8904_set_fll,
1917 	.hw_params = wm8904_hw_params,
1918 	.digital_mute = wm8904_digital_mute,
1919 };
1920 
1921 static struct snd_soc_dai_driver wm8904_dai = {
1922 	.name = "wm8904-hifi",
1923 	.playback = {
1924 		.stream_name = "Playback",
1925 		.channels_min = 2,
1926 		.channels_max = 2,
1927 		.rates = WM8904_RATES,
1928 		.formats = WM8904_FORMATS,
1929 	},
1930 	.capture = {
1931 		.stream_name = "Capture",
1932 		.channels_min = 2,
1933 		.channels_max = 2,
1934 		.rates = WM8904_RATES,
1935 		.formats = WM8904_FORMATS,
1936 	},
1937 	.ops = &wm8904_dai_ops,
1938 	.symmetric_rates = 1,
1939 };
1940 
1941 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
1942 {
1943 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1944 	struct wm8904_pdata *pdata = wm8904->pdata;
1945 	struct snd_kcontrol_new control =
1946 		SOC_ENUM_EXT("EQ Mode",
1947 			     wm8904->retune_mobile_enum,
1948 			     wm8904_get_retune_mobile_enum,
1949 			     wm8904_put_retune_mobile_enum);
1950 	int ret, i, j;
1951 	const char **t;
1952 
1953 	/* We need an array of texts for the enum API but the number
1954 	 * of texts is likely to be less than the number of
1955 	 * configurations due to the sample rate dependency of the
1956 	 * configurations. */
1957 	wm8904->num_retune_mobile_texts = 0;
1958 	wm8904->retune_mobile_texts = NULL;
1959 	for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1960 		for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
1961 			if (strcmp(pdata->retune_mobile_cfgs[i].name,
1962 				   wm8904->retune_mobile_texts[j]) == 0)
1963 				break;
1964 		}
1965 
1966 		if (j != wm8904->num_retune_mobile_texts)
1967 			continue;
1968 
1969 		/* Expand the array... */
1970 		t = krealloc(wm8904->retune_mobile_texts,
1971 			     sizeof(char *) *
1972 			     (wm8904->num_retune_mobile_texts + 1),
1973 			     GFP_KERNEL);
1974 		if (t == NULL)
1975 			continue;
1976 
1977 		/* ...store the new entry... */
1978 		t[wm8904->num_retune_mobile_texts] =
1979 			pdata->retune_mobile_cfgs[i].name;
1980 
1981 		/* ...and remember the new version. */
1982 		wm8904->num_retune_mobile_texts++;
1983 		wm8904->retune_mobile_texts = t;
1984 	}
1985 
1986 	dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
1987 		wm8904->num_retune_mobile_texts);
1988 
1989 	wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
1990 	wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
1991 
1992 	ret = snd_soc_add_codec_controls(codec, &control, 1);
1993 	if (ret != 0)
1994 		dev_err(codec->dev,
1995 			"Failed to add ReTune Mobile control: %d\n", ret);
1996 }
1997 
1998 static void wm8904_handle_pdata(struct snd_soc_codec *codec)
1999 {
2000 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2001 	struct wm8904_pdata *pdata = wm8904->pdata;
2002 	int ret, i;
2003 
2004 	if (!pdata) {
2005 		snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2006 				     ARRAY_SIZE(wm8904_eq_controls));
2007 		return;
2008 	}
2009 
2010 	dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2011 
2012 	if (pdata->num_drc_cfgs) {
2013 		struct snd_kcontrol_new control =
2014 			SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2015 				     wm8904_get_drc_enum, wm8904_put_drc_enum);
2016 
2017 		/* We need an array of texts for the enum API */
2018 		wm8904->drc_texts = kmalloc(sizeof(char *)
2019 					    * pdata->num_drc_cfgs, GFP_KERNEL);
2020 		if (!wm8904->drc_texts)
2021 			return;
2022 
2023 		for (i = 0; i < pdata->num_drc_cfgs; i++)
2024 			wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2025 
2026 		wm8904->drc_enum.items = pdata->num_drc_cfgs;
2027 		wm8904->drc_enum.texts = wm8904->drc_texts;
2028 
2029 		ret = snd_soc_add_codec_controls(codec, &control, 1);
2030 		if (ret != 0)
2031 			dev_err(codec->dev,
2032 				"Failed to add DRC mode control: %d\n", ret);
2033 
2034 		wm8904_set_drc(codec);
2035 	}
2036 
2037 	dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2038 		pdata->num_retune_mobile_cfgs);
2039 
2040 	if (pdata->num_retune_mobile_cfgs)
2041 		wm8904_handle_retune_mobile_pdata(codec);
2042 	else
2043 		snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2044 				     ARRAY_SIZE(wm8904_eq_controls));
2045 }
2046 
2047 
2048 static int wm8904_probe(struct snd_soc_codec *codec)
2049 {
2050 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2051 
2052 	switch (wm8904->devtype) {
2053 	case WM8904:
2054 		break;
2055 	case WM8912:
2056 		memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2057 		break;
2058 	default:
2059 		dev_err(codec->dev, "Unknown device type %d\n",
2060 			wm8904->devtype);
2061 		return -EINVAL;
2062 	}
2063 
2064 	wm8904_handle_pdata(codec);
2065 
2066 	wm8904_add_widgets(codec);
2067 
2068 	return 0;
2069 }
2070 
2071 static int wm8904_remove(struct snd_soc_codec *codec)
2072 {
2073 	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2074 
2075 	kfree(wm8904->retune_mobile_texts);
2076 	kfree(wm8904->drc_texts);
2077 
2078 	return 0;
2079 }
2080 
2081 static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2082 	.probe =	wm8904_probe,
2083 	.remove =	wm8904_remove,
2084 	.set_bias_level = wm8904_set_bias_level,
2085 	.idle_bias_off = true,
2086 };
2087 
2088 static const struct regmap_config wm8904_regmap = {
2089 	.reg_bits = 8,
2090 	.val_bits = 16,
2091 
2092 	.max_register = WM8904_MAX_REGISTER,
2093 	.volatile_reg = wm8904_volatile_register,
2094 	.readable_reg = wm8904_readable_register,
2095 
2096 	.cache_type = REGCACHE_RBTREE,
2097 	.reg_defaults = wm8904_reg_defaults,
2098 	.num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2099 };
2100 
2101 static int wm8904_i2c_probe(struct i2c_client *i2c,
2102 			    const struct i2c_device_id *id)
2103 {
2104 	struct wm8904_priv *wm8904;
2105 	unsigned int val;
2106 	int ret, i;
2107 
2108 	wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2109 			      GFP_KERNEL);
2110 	if (wm8904 == NULL)
2111 		return -ENOMEM;
2112 
2113 	wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
2114 	if (IS_ERR(wm8904->mclk)) {
2115 		ret = PTR_ERR(wm8904->mclk);
2116 		dev_err(&i2c->dev, "Failed to get MCLK\n");
2117 		return ret;
2118 	}
2119 
2120 	wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
2121 	if (IS_ERR(wm8904->regmap)) {
2122 		ret = PTR_ERR(wm8904->regmap);
2123 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2124 			ret);
2125 		return ret;
2126 	}
2127 
2128 	wm8904->devtype = id->driver_data;
2129 	i2c_set_clientdata(i2c, wm8904);
2130 	wm8904->pdata = i2c->dev.platform_data;
2131 
2132 	for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2133 		wm8904->supplies[i].supply = wm8904_supply_names[i];
2134 
2135 	ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2136 				      wm8904->supplies);
2137 	if (ret != 0) {
2138 		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2139 		return ret;
2140 	}
2141 
2142 	ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2143 				    wm8904->supplies);
2144 	if (ret != 0) {
2145 		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2146 		return ret;
2147 	}
2148 
2149 	ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2150 	if (ret < 0) {
2151 		dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2152 		goto err_enable;
2153 	}
2154 	if (val != 0x8904) {
2155 		dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2156 		ret = -EINVAL;
2157 		goto err_enable;
2158 	}
2159 
2160 	ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2161 	if (ret < 0) {
2162 		dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2163 			ret);
2164 		goto err_enable;
2165 	}
2166 	dev_info(&i2c->dev, "revision %c\n", val + 'A');
2167 
2168 	ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2169 	if (ret < 0) {
2170 		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2171 		goto err_enable;
2172 	}
2173 
2174 	/* Change some default settings - latch VU and enable ZC */
2175 	regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2176 			   WM8904_ADC_VU, WM8904_ADC_VU);
2177 	regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2178 			   WM8904_ADC_VU, WM8904_ADC_VU);
2179 	regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2180 			   WM8904_DAC_VU, WM8904_DAC_VU);
2181 	regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2182 			   WM8904_DAC_VU, WM8904_DAC_VU);
2183 	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2184 			   WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2185 			   WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2186 	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2187 			   WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2188 			   WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2189 	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2190 			   WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2191 			   WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2192 	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2193 			   WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2194 			   WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2195 	regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2196 			   WM8904_SR_MODE, 0);
2197 
2198 	/* Apply configuration from the platform data. */
2199 	if (wm8904->pdata) {
2200 		for (i = 0; i < WM8904_GPIO_REGS; i++) {
2201 			if (!wm8904->pdata->gpio_cfg[i])
2202 				continue;
2203 
2204 			regmap_update_bits(wm8904->regmap,
2205 					   WM8904_GPIO_CONTROL_1 + i,
2206 					   0xffff,
2207 					   wm8904->pdata->gpio_cfg[i]);
2208 		}
2209 
2210 		/* Zero is the default value for these anyway */
2211 		for (i = 0; i < WM8904_MIC_REGS; i++)
2212 			regmap_update_bits(wm8904->regmap,
2213 					   WM8904_MIC_BIAS_CONTROL_0 + i,
2214 					   0xffff,
2215 					   wm8904->pdata->mic_cfg[i]);
2216 	}
2217 
2218 	/* Set Class W by default - this will be managed by the Class
2219 	 * G widget at runtime where bypass paths are available.
2220 	 */
2221 	regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2222 			    WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2223 
2224 	/* Use normal bias source */
2225 	regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2226 			    WM8904_POBCTRL, 0);
2227 
2228 	/* Can leave the device powered off until we need it */
2229 	regcache_cache_only(wm8904->regmap, true);
2230 	regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2231 
2232 	ret = snd_soc_register_codec(&i2c->dev,
2233 			&soc_codec_dev_wm8904, &wm8904_dai, 1);
2234 	if (ret != 0)
2235 		return ret;
2236 
2237 	return 0;
2238 
2239 err_enable:
2240 	regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2241 	return ret;
2242 }
2243 
2244 static int wm8904_i2c_remove(struct i2c_client *client)
2245 {
2246 	snd_soc_unregister_codec(&client->dev);
2247 	return 0;
2248 }
2249 
2250 static const struct i2c_device_id wm8904_i2c_id[] = {
2251 	{ "wm8904", WM8904 },
2252 	{ "wm8912", WM8912 },
2253 	{ "wm8918", WM8904 },   /* Actually a subset, updates to follow */
2254 	{ }
2255 };
2256 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2257 
2258 static struct i2c_driver wm8904_i2c_driver = {
2259 	.driver = {
2260 		.name = "wm8904",
2261 		.owner = THIS_MODULE,
2262 	},
2263 	.probe =    wm8904_i2c_probe,
2264 	.remove =   wm8904_i2c_remove,
2265 	.id_table = wm8904_i2c_id,
2266 };
2267 
2268 module_i2c_driver(wm8904_i2c_driver);
2269 
2270 MODULE_DESCRIPTION("ASoC WM8904 driver");
2271 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2272 MODULE_LICENSE("GPL");
2273