1 /* 2 * wm8904.c -- WM8904 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/wm8904.h> 31 32 #include "wm8904.h" 33 34 static struct snd_soc_codec *wm8904_codec; 35 struct snd_soc_codec_device soc_codec_dev_wm8904; 36 37 enum wm8904_type { 38 WM8904, 39 WM8912, 40 }; 41 42 #define WM8904_NUM_DCS_CHANNELS 4 43 44 #define WM8904_NUM_SUPPLIES 5 45 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 46 "DCVDD", 47 "DBVDD", 48 "AVDD", 49 "CPVDD", 50 "MICVDD", 51 }; 52 53 /* codec private data */ 54 struct wm8904_priv { 55 struct snd_soc_codec codec; 56 u16 reg_cache[WM8904_MAX_REGISTER + 1]; 57 58 enum wm8904_type devtype; 59 60 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 61 62 struct wm8904_pdata *pdata; 63 64 int deemph; 65 66 /* Platform provided DRC configuration */ 67 const char **drc_texts; 68 int drc_cfg; 69 struct soc_enum drc_enum; 70 71 /* Platform provided ReTune mobile configuration */ 72 int num_retune_mobile_texts; 73 const char **retune_mobile_texts; 74 int retune_mobile_cfg; 75 struct soc_enum retune_mobile_enum; 76 77 /* FLL setup */ 78 int fll_src; 79 int fll_fref; 80 int fll_fout; 81 82 /* Clocking configuration */ 83 unsigned int mclk_rate; 84 int sysclk_src; 85 unsigned int sysclk_rate; 86 87 int tdm_width; 88 int tdm_slots; 89 int bclk; 90 int fs; 91 92 /* DC servo configuration - cached offset values */ 93 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 94 }; 95 96 static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { 97 0x8904, /* R0 - SW Reset and ID */ 98 0x0000, /* R1 - Revision */ 99 0x0000, /* R2 */ 100 0x0000, /* R3 */ 101 0x0018, /* R4 - Bias Control 0 */ 102 0x0000, /* R5 - VMID Control 0 */ 103 0x0000, /* R6 - Mic Bias Control 0 */ 104 0x0000, /* R7 - Mic Bias Control 1 */ 105 0x0001, /* R8 - Analogue DAC 0 */ 106 0x9696, /* R9 - mic Filter Control */ 107 0x0001, /* R10 - Analogue ADC 0 */ 108 0x0000, /* R11 */ 109 0x0000, /* R12 - Power Management 0 */ 110 0x0000, /* R13 */ 111 0x0000, /* R14 - Power Management 2 */ 112 0x0000, /* R15 - Power Management 3 */ 113 0x0000, /* R16 */ 114 0x0000, /* R17 */ 115 0x0000, /* R18 - Power Management 6 */ 116 0x0000, /* R19 */ 117 0x945E, /* R20 - Clock Rates 0 */ 118 0x0C05, /* R21 - Clock Rates 1 */ 119 0x0006, /* R22 - Clock Rates 2 */ 120 0x0000, /* R23 */ 121 0x0050, /* R24 - Audio Interface 0 */ 122 0x000A, /* R25 - Audio Interface 1 */ 123 0x00E4, /* R26 - Audio Interface 2 */ 124 0x0040, /* R27 - Audio Interface 3 */ 125 0x0000, /* R28 */ 126 0x0000, /* R29 */ 127 0x00C0, /* R30 - DAC Digital Volume Left */ 128 0x00C0, /* R31 - DAC Digital Volume Right */ 129 0x0000, /* R32 - DAC Digital 0 */ 130 0x0008, /* R33 - DAC Digital 1 */ 131 0x0000, /* R34 */ 132 0x0000, /* R35 */ 133 0x00C0, /* R36 - ADC Digital Volume Left */ 134 0x00C0, /* R37 - ADC Digital Volume Right */ 135 0x0010, /* R38 - ADC Digital 0 */ 136 0x0000, /* R39 - Digital Microphone 0 */ 137 0x01AF, /* R40 - DRC 0 */ 138 0x3248, /* R41 - DRC 1 */ 139 0x0000, /* R42 - DRC 2 */ 140 0x0000, /* R43 - DRC 3 */ 141 0x0085, /* R44 - Analogue Left Input 0 */ 142 0x0085, /* R45 - Analogue Right Input 0 */ 143 0x0044, /* R46 - Analogue Left Input 1 */ 144 0x0044, /* R47 - Analogue Right Input 1 */ 145 0x0000, /* R48 */ 146 0x0000, /* R49 */ 147 0x0000, /* R50 */ 148 0x0000, /* R51 */ 149 0x0000, /* R52 */ 150 0x0000, /* R53 */ 151 0x0000, /* R54 */ 152 0x0000, /* R55 */ 153 0x0000, /* R56 */ 154 0x002D, /* R57 - Analogue OUT1 Left */ 155 0x002D, /* R58 - Analogue OUT1 Right */ 156 0x0039, /* R59 - Analogue OUT2 Left */ 157 0x0039, /* R60 - Analogue OUT2 Right */ 158 0x0000, /* R61 - Analogue OUT12 ZC */ 159 0x0000, /* R62 */ 160 0x0000, /* R63 */ 161 0x0000, /* R64 */ 162 0x0000, /* R65 */ 163 0x0000, /* R66 */ 164 0x0000, /* R67 - DC Servo 0 */ 165 0x0000, /* R68 - DC Servo 1 */ 166 0xAAAA, /* R69 - DC Servo 2 */ 167 0x0000, /* R70 */ 168 0xAAAA, /* R71 - DC Servo 4 */ 169 0xAAAA, /* R72 - DC Servo 5 */ 170 0x0000, /* R73 - DC Servo 6 */ 171 0x0000, /* R74 - DC Servo 7 */ 172 0x0000, /* R75 - DC Servo 8 */ 173 0x0000, /* R76 - DC Servo 9 */ 174 0x0000, /* R77 - DC Servo Readback 0 */ 175 0x0000, /* R78 */ 176 0x0000, /* R79 */ 177 0x0000, /* R80 */ 178 0x0000, /* R81 */ 179 0x0000, /* R82 */ 180 0x0000, /* R83 */ 181 0x0000, /* R84 */ 182 0x0000, /* R85 */ 183 0x0000, /* R86 */ 184 0x0000, /* R87 */ 185 0x0000, /* R88 */ 186 0x0000, /* R89 */ 187 0x0000, /* R90 - Analogue HP 0 */ 188 0x0000, /* R91 */ 189 0x0000, /* R92 */ 190 0x0000, /* R93 */ 191 0x0000, /* R94 - Analogue Lineout 0 */ 192 0x0000, /* R95 */ 193 0x0000, /* R96 */ 194 0x0000, /* R97 */ 195 0x0000, /* R98 - Charge Pump 0 */ 196 0x0000, /* R99 */ 197 0x0000, /* R100 */ 198 0x0000, /* R101 */ 199 0x0000, /* R102 */ 200 0x0000, /* R103 */ 201 0x0004, /* R104 - Class W 0 */ 202 0x0000, /* R105 */ 203 0x0000, /* R106 */ 204 0x0000, /* R107 */ 205 0x0000, /* R108 - Write Sequencer 0 */ 206 0x0000, /* R109 - Write Sequencer 1 */ 207 0x0000, /* R110 - Write Sequencer 2 */ 208 0x0000, /* R111 - Write Sequencer 3 */ 209 0x0000, /* R112 - Write Sequencer 4 */ 210 0x0000, /* R113 */ 211 0x0000, /* R114 */ 212 0x0000, /* R115 */ 213 0x0000, /* R116 - FLL Control 1 */ 214 0x0007, /* R117 - FLL Control 2 */ 215 0x0000, /* R118 - FLL Control 3 */ 216 0x2EE0, /* R119 - FLL Control 4 */ 217 0x0004, /* R120 - FLL Control 5 */ 218 0x0014, /* R121 - GPIO Control 1 */ 219 0x0010, /* R122 - GPIO Control 2 */ 220 0x0010, /* R123 - GPIO Control 3 */ 221 0x0000, /* R124 - GPIO Control 4 */ 222 0x0000, /* R125 */ 223 0x0000, /* R126 - Digital Pulls */ 224 0x0000, /* R127 - Interrupt Status */ 225 0xFFFF, /* R128 - Interrupt Status Mask */ 226 0x0000, /* R129 - Interrupt Polarity */ 227 0x0000, /* R130 - Interrupt Debounce */ 228 0x0000, /* R131 */ 229 0x0000, /* R132 */ 230 0x0000, /* R133 */ 231 0x0000, /* R134 - EQ1 */ 232 0x000C, /* R135 - EQ2 */ 233 0x000C, /* R136 - EQ3 */ 234 0x000C, /* R137 - EQ4 */ 235 0x000C, /* R138 - EQ5 */ 236 0x000C, /* R139 - EQ6 */ 237 0x0FCA, /* R140 - EQ7 */ 238 0x0400, /* R141 - EQ8 */ 239 0x00D8, /* R142 - EQ9 */ 240 0x1EB5, /* R143 - EQ10 */ 241 0xF145, /* R144 - EQ11 */ 242 0x0B75, /* R145 - EQ12 */ 243 0x01C5, /* R146 - EQ13 */ 244 0x1C58, /* R147 - EQ14 */ 245 0xF373, /* R148 - EQ15 */ 246 0x0A54, /* R149 - EQ16 */ 247 0x0558, /* R150 - EQ17 */ 248 0x168E, /* R151 - EQ18 */ 249 0xF829, /* R152 - EQ19 */ 250 0x07AD, /* R153 - EQ20 */ 251 0x1103, /* R154 - EQ21 */ 252 0x0564, /* R155 - EQ22 */ 253 0x0559, /* R156 - EQ23 */ 254 0x4000, /* R157 - EQ24 */ 255 0x0000, /* R158 */ 256 0x0000, /* R159 */ 257 0x0000, /* R160 */ 258 0x0000, /* R161 - Control Interface Test 1 */ 259 0x0000, /* R162 */ 260 0x0000, /* R163 */ 261 0x0000, /* R164 */ 262 0x0000, /* R165 */ 263 0x0000, /* R166 */ 264 0x0000, /* R167 */ 265 0x0000, /* R168 */ 266 0x0000, /* R169 */ 267 0x0000, /* R170 */ 268 0x0000, /* R171 */ 269 0x0000, /* R172 */ 270 0x0000, /* R173 */ 271 0x0000, /* R174 */ 272 0x0000, /* R175 */ 273 0x0000, /* R176 */ 274 0x0000, /* R177 */ 275 0x0000, /* R178 */ 276 0x0000, /* R179 */ 277 0x0000, /* R180 */ 278 0x0000, /* R181 */ 279 0x0000, /* R182 */ 280 0x0000, /* R183 */ 281 0x0000, /* R184 */ 282 0x0000, /* R185 */ 283 0x0000, /* R186 */ 284 0x0000, /* R187 */ 285 0x0000, /* R188 */ 286 0x0000, /* R189 */ 287 0x0000, /* R190 */ 288 0x0000, /* R191 */ 289 0x0000, /* R192 */ 290 0x0000, /* R193 */ 291 0x0000, /* R194 */ 292 0x0000, /* R195 */ 293 0x0000, /* R196 */ 294 0x0000, /* R197 */ 295 0x0000, /* R198 */ 296 0x0000, /* R199 */ 297 0x0000, /* R200 */ 298 0x0000, /* R201 */ 299 0x0000, /* R202 */ 300 0x0000, /* R203 */ 301 0x0000, /* R204 - Analogue Output Bias 0 */ 302 0x0000, /* R205 */ 303 0x0000, /* R206 */ 304 0x0000, /* R207 */ 305 0x0000, /* R208 */ 306 0x0000, /* R209 */ 307 0x0000, /* R210 */ 308 0x0000, /* R211 */ 309 0x0000, /* R212 */ 310 0x0000, /* R213 */ 311 0x0000, /* R214 */ 312 0x0000, /* R215 */ 313 0x0000, /* R216 */ 314 0x0000, /* R217 */ 315 0x0000, /* R218 */ 316 0x0000, /* R219 */ 317 0x0000, /* R220 */ 318 0x0000, /* R221 */ 319 0x0000, /* R222 */ 320 0x0000, /* R223 */ 321 0x0000, /* R224 */ 322 0x0000, /* R225 */ 323 0x0000, /* R226 */ 324 0x0000, /* R227 */ 325 0x0000, /* R228 */ 326 0x0000, /* R229 */ 327 0x0000, /* R230 */ 328 0x0000, /* R231 */ 329 0x0000, /* R232 */ 330 0x0000, /* R233 */ 331 0x0000, /* R234 */ 332 0x0000, /* R235 */ 333 0x0000, /* R236 */ 334 0x0000, /* R237 */ 335 0x0000, /* R238 */ 336 0x0000, /* R239 */ 337 0x0000, /* R240 */ 338 0x0000, /* R241 */ 339 0x0000, /* R242 */ 340 0x0000, /* R243 */ 341 0x0000, /* R244 */ 342 0x0000, /* R245 */ 343 0x0000, /* R246 */ 344 0x0000, /* R247 - FLL NCO Test 0 */ 345 0x0019, /* R248 - FLL NCO Test 1 */ 346 }; 347 348 static struct { 349 int readable; 350 int writable; 351 int vol; 352 } wm8904_access[] = { 353 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ 354 { 0x0000, 0x0000, 0 }, /* R1 - Revision */ 355 { 0x0000, 0x0000, 0 }, /* R2 */ 356 { 0x0000, 0x0000, 0 }, /* R3 */ 357 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ 358 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ 359 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ 360 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ 361 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ 362 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ 363 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ 364 { 0x0000, 0x0000, 0 }, /* R11 */ 365 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ 366 { 0x0000, 0x0000, 0 }, /* R13 */ 367 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ 368 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ 369 { 0x0000, 0x0000, 0 }, /* R16 */ 370 { 0x0000, 0x0000, 0 }, /* R17 */ 371 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ 372 { 0x0000, 0x0000, 0 }, /* R19 */ 373 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ 374 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ 375 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ 376 { 0x0000, 0x0000, 0 }, /* R23 */ 377 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ 378 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ 379 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ 380 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ 381 { 0x0000, 0x0000, 0 }, /* R28 */ 382 { 0x0000, 0x0000, 0 }, /* R29 */ 383 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ 384 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ 385 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ 386 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ 387 { 0x0000, 0x0000, 0 }, /* R34 */ 388 { 0x0000, 0x0000, 0 }, /* R35 */ 389 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ 390 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ 391 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ 392 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ 393 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ 394 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ 395 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ 396 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ 397 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ 398 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ 399 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ 400 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ 401 { 0x0000, 0x0000, 0 }, /* R48 */ 402 { 0x0000, 0x0000, 0 }, /* R49 */ 403 { 0x0000, 0x0000, 0 }, /* R50 */ 404 { 0x0000, 0x0000, 0 }, /* R51 */ 405 { 0x0000, 0x0000, 0 }, /* R52 */ 406 { 0x0000, 0x0000, 0 }, /* R53 */ 407 { 0x0000, 0x0000, 0 }, /* R54 */ 408 { 0x0000, 0x0000, 0 }, /* R55 */ 409 { 0x0000, 0x0000, 0 }, /* R56 */ 410 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ 411 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ 412 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ 413 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ 414 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ 415 { 0x0000, 0x0000, 0 }, /* R62 */ 416 { 0x0000, 0x0000, 0 }, /* R63 */ 417 { 0x0000, 0x0000, 0 }, /* R64 */ 418 { 0x0000, 0x0000, 0 }, /* R65 */ 419 { 0x0000, 0x0000, 0 }, /* R66 */ 420 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ 421 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ 422 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ 423 { 0x0000, 0x0000, 0 }, /* R70 */ 424 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ 425 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ 426 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ 427 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ 428 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ 429 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ 430 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ 431 { 0x0000, 0x0000, 0 }, /* R78 */ 432 { 0x0000, 0x0000, 0 }, /* R79 */ 433 { 0x0000, 0x0000, 0 }, /* R80 */ 434 { 0x0000, 0x0000, 0 }, /* R81 */ 435 { 0x0000, 0x0000, 0 }, /* R82 */ 436 { 0x0000, 0x0000, 0 }, /* R83 */ 437 { 0x0000, 0x0000, 0 }, /* R84 */ 438 { 0x0000, 0x0000, 0 }, /* R85 */ 439 { 0x0000, 0x0000, 0 }, /* R86 */ 440 { 0x0000, 0x0000, 0 }, /* R87 */ 441 { 0x0000, 0x0000, 0 }, /* R88 */ 442 { 0x0000, 0x0000, 0 }, /* R89 */ 443 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ 444 { 0x0000, 0x0000, 0 }, /* R91 */ 445 { 0x0000, 0x0000, 0 }, /* R92 */ 446 { 0x0000, 0x0000, 0 }, /* R93 */ 447 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ 448 { 0x0000, 0x0000, 0 }, /* R95 */ 449 { 0x0000, 0x0000, 0 }, /* R96 */ 450 { 0x0000, 0x0000, 0 }, /* R97 */ 451 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ 452 { 0x0000, 0x0000, 0 }, /* R99 */ 453 { 0x0000, 0x0000, 0 }, /* R100 */ 454 { 0x0000, 0x0000, 0 }, /* R101 */ 455 { 0x0000, 0x0000, 0 }, /* R102 */ 456 { 0x0000, 0x0000, 0 }, /* R103 */ 457 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ 458 { 0x0000, 0x0000, 0 }, /* R105 */ 459 { 0x0000, 0x0000, 0 }, /* R106 */ 460 { 0x0000, 0x0000, 0 }, /* R107 */ 461 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ 462 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ 463 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ 464 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ 465 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ 466 { 0x0000, 0x0000, 0 }, /* R113 */ 467 { 0x0000, 0x0000, 0 }, /* R114 */ 468 { 0x0000, 0x0000, 0 }, /* R115 */ 469 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ 470 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ 471 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ 472 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ 473 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ 474 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ 475 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ 476 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ 477 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ 478 { 0x0000, 0x0000, 0 }, /* R125 */ 479 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ 480 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ 481 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ 482 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ 483 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ 484 { 0x0000, 0x0000, 0 }, /* R131 */ 485 { 0x0000, 0x0000, 0 }, /* R132 */ 486 { 0x0000, 0x0000, 0 }, /* R133 */ 487 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ 488 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ 489 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ 490 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ 491 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ 492 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ 493 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ 494 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ 495 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ 496 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ 497 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ 498 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ 499 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ 500 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ 501 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ 502 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ 503 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ 504 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ 505 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ 506 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ 507 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ 508 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ 509 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ 510 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ 511 { 0x0000, 0x0000, 0 }, /* R158 */ 512 { 0x0000, 0x0000, 0 }, /* R159 */ 513 { 0x0000, 0x0000, 0 }, /* R160 */ 514 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ 515 { 0x0000, 0x0000, 0 }, /* R162 */ 516 { 0x0000, 0x0000, 0 }, /* R163 */ 517 { 0x0000, 0x0000, 0 }, /* R164 */ 518 { 0x0000, 0x0000, 0 }, /* R165 */ 519 { 0x0000, 0x0000, 0 }, /* R166 */ 520 { 0x0000, 0x0000, 0 }, /* R167 */ 521 { 0x0000, 0x0000, 0 }, /* R168 */ 522 { 0x0000, 0x0000, 0 }, /* R169 */ 523 { 0x0000, 0x0000, 0 }, /* R170 */ 524 { 0x0000, 0x0000, 0 }, /* R171 */ 525 { 0x0000, 0x0000, 0 }, /* R172 */ 526 { 0x0000, 0x0000, 0 }, /* R173 */ 527 { 0x0000, 0x0000, 0 }, /* R174 */ 528 { 0x0000, 0x0000, 0 }, /* R175 */ 529 { 0x0000, 0x0000, 0 }, /* R176 */ 530 { 0x0000, 0x0000, 0 }, /* R177 */ 531 { 0x0000, 0x0000, 0 }, /* R178 */ 532 { 0x0000, 0x0000, 0 }, /* R179 */ 533 { 0x0000, 0x0000, 0 }, /* R180 */ 534 { 0x0000, 0x0000, 0 }, /* R181 */ 535 { 0x0000, 0x0000, 0 }, /* R182 */ 536 { 0x0000, 0x0000, 0 }, /* R183 */ 537 { 0x0000, 0x0000, 0 }, /* R184 */ 538 { 0x0000, 0x0000, 0 }, /* R185 */ 539 { 0x0000, 0x0000, 0 }, /* R186 */ 540 { 0x0000, 0x0000, 0 }, /* R187 */ 541 { 0x0000, 0x0000, 0 }, /* R188 */ 542 { 0x0000, 0x0000, 0 }, /* R189 */ 543 { 0x0000, 0x0000, 0 }, /* R190 */ 544 { 0x0000, 0x0000, 0 }, /* R191 */ 545 { 0x0000, 0x0000, 0 }, /* R192 */ 546 { 0x0000, 0x0000, 0 }, /* R193 */ 547 { 0x0000, 0x0000, 0 }, /* R194 */ 548 { 0x0000, 0x0000, 0 }, /* R195 */ 549 { 0x0000, 0x0000, 0 }, /* R196 */ 550 { 0x0000, 0x0000, 0 }, /* R197 */ 551 { 0x0000, 0x0000, 0 }, /* R198 */ 552 { 0x0000, 0x0000, 0 }, /* R199 */ 553 { 0x0000, 0x0000, 0 }, /* R200 */ 554 { 0x0000, 0x0000, 0 }, /* R201 */ 555 { 0x0000, 0x0000, 0 }, /* R202 */ 556 { 0x0000, 0x0000, 0 }, /* R203 */ 557 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ 558 { 0x0000, 0x0000, 0 }, /* R205 */ 559 { 0x0000, 0x0000, 0 }, /* R206 */ 560 { 0x0000, 0x0000, 0 }, /* R207 */ 561 { 0x0000, 0x0000, 0 }, /* R208 */ 562 { 0x0000, 0x0000, 0 }, /* R209 */ 563 { 0x0000, 0x0000, 0 }, /* R210 */ 564 { 0x0000, 0x0000, 0 }, /* R211 */ 565 { 0x0000, 0x0000, 0 }, /* R212 */ 566 { 0x0000, 0x0000, 0 }, /* R213 */ 567 { 0x0000, 0x0000, 0 }, /* R214 */ 568 { 0x0000, 0x0000, 0 }, /* R215 */ 569 { 0x0000, 0x0000, 0 }, /* R216 */ 570 { 0x0000, 0x0000, 0 }, /* R217 */ 571 { 0x0000, 0x0000, 0 }, /* R218 */ 572 { 0x0000, 0x0000, 0 }, /* R219 */ 573 { 0x0000, 0x0000, 0 }, /* R220 */ 574 { 0x0000, 0x0000, 0 }, /* R221 */ 575 { 0x0000, 0x0000, 0 }, /* R222 */ 576 { 0x0000, 0x0000, 0 }, /* R223 */ 577 { 0x0000, 0x0000, 0 }, /* R224 */ 578 { 0x0000, 0x0000, 0 }, /* R225 */ 579 { 0x0000, 0x0000, 0 }, /* R226 */ 580 { 0x0000, 0x0000, 0 }, /* R227 */ 581 { 0x0000, 0x0000, 0 }, /* R228 */ 582 { 0x0000, 0x0000, 0 }, /* R229 */ 583 { 0x0000, 0x0000, 0 }, /* R230 */ 584 { 0x0000, 0x0000, 0 }, /* R231 */ 585 { 0x0000, 0x0000, 0 }, /* R232 */ 586 { 0x0000, 0x0000, 0 }, /* R233 */ 587 { 0x0000, 0x0000, 0 }, /* R234 */ 588 { 0x0000, 0x0000, 0 }, /* R235 */ 589 { 0x0000, 0x0000, 0 }, /* R236 */ 590 { 0x0000, 0x0000, 0 }, /* R237 */ 591 { 0x0000, 0x0000, 0 }, /* R238 */ 592 { 0x0000, 0x0000, 0 }, /* R239 */ 593 { 0x0000, 0x0000, 0 }, /* R240 */ 594 { 0x0000, 0x0000, 0 }, /* R241 */ 595 { 0x0000, 0x0000, 0 }, /* R242 */ 596 { 0x0000, 0x0000, 0 }, /* R243 */ 597 { 0x0000, 0x0000, 0 }, /* R244 */ 598 { 0x0000, 0x0000, 0 }, /* R245 */ 599 { 0x0000, 0x0000, 0 }, /* R246 */ 600 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ 601 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ 602 }; 603 604 static int wm8904_volatile_register(unsigned int reg) 605 { 606 return wm8904_access[reg].vol; 607 } 608 609 static int wm8904_reset(struct snd_soc_codec *codec) 610 { 611 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); 612 } 613 614 static int wm8904_configure_clocking(struct snd_soc_codec *codec) 615 { 616 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 617 unsigned int clock0, clock2, rate; 618 619 /* Gate the clock while we're updating to avoid misclocking */ 620 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 621 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 622 WM8904_SYSCLK_SRC, 0); 623 624 /* This should be done on init() for bypass paths */ 625 switch (wm8904->sysclk_src) { 626 case WM8904_CLK_MCLK: 627 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 628 629 clock2 &= ~WM8904_SYSCLK_SRC; 630 rate = wm8904->mclk_rate; 631 632 /* Ensure the FLL is stopped */ 633 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 634 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 635 break; 636 637 case WM8904_CLK_FLL: 638 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 639 wm8904->fll_fout); 640 641 clock2 |= WM8904_SYSCLK_SRC; 642 rate = wm8904->fll_fout; 643 break; 644 645 default: 646 dev_err(codec->dev, "System clock not configured\n"); 647 return -EINVAL; 648 } 649 650 /* SYSCLK shouldn't be over 13.5MHz */ 651 if (rate > 13500000) { 652 clock0 = WM8904_MCLK_DIV; 653 wm8904->sysclk_rate = rate / 2; 654 } else { 655 clock0 = 0; 656 wm8904->sysclk_rate = rate; 657 } 658 659 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 660 clock0); 661 662 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 663 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 664 665 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 666 667 return 0; 668 } 669 670 static void wm8904_set_drc(struct snd_soc_codec *codec) 671 { 672 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 673 struct wm8904_pdata *pdata = wm8904->pdata; 674 int save, i; 675 676 /* Save any enables; the configuration should clear them. */ 677 save = snd_soc_read(codec, WM8904_DRC_0); 678 679 for (i = 0; i < WM8904_DRC_REGS; i++) 680 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, 681 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 682 683 /* Reenable the DRC */ 684 snd_soc_update_bits(codec, WM8904_DRC_0, 685 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 686 } 687 688 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 689 struct snd_ctl_elem_value *ucontrol) 690 { 691 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 692 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 693 struct wm8904_pdata *pdata = wm8904->pdata; 694 int value = ucontrol->value.integer.value[0]; 695 696 if (value >= pdata->num_drc_cfgs) 697 return -EINVAL; 698 699 wm8904->drc_cfg = value; 700 701 wm8904_set_drc(codec); 702 703 return 0; 704 } 705 706 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 707 struct snd_ctl_elem_value *ucontrol) 708 { 709 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 710 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 711 712 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 713 714 return 0; 715 } 716 717 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) 718 { 719 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 720 struct wm8904_pdata *pdata = wm8904->pdata; 721 int best, best_val, save, i, cfg; 722 723 if (!pdata || !wm8904->num_retune_mobile_texts) 724 return; 725 726 /* Find the version of the currently selected configuration 727 * with the nearest sample rate. */ 728 cfg = wm8904->retune_mobile_cfg; 729 best = 0; 730 best_val = INT_MAX; 731 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 732 if (strcmp(pdata->retune_mobile_cfgs[i].name, 733 wm8904->retune_mobile_texts[cfg]) == 0 && 734 abs(pdata->retune_mobile_cfgs[i].rate 735 - wm8904->fs) < best_val) { 736 best = i; 737 best_val = abs(pdata->retune_mobile_cfgs[i].rate 738 - wm8904->fs); 739 } 740 } 741 742 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 743 pdata->retune_mobile_cfgs[best].name, 744 pdata->retune_mobile_cfgs[best].rate, 745 wm8904->fs); 746 747 /* The EQ will be disabled while reconfiguring it, remember the 748 * current configuration. 749 */ 750 save = snd_soc_read(codec, WM8904_EQ1); 751 752 for (i = 0; i < WM8904_EQ_REGS; i++) 753 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, 754 pdata->retune_mobile_cfgs[best].regs[i]); 755 756 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); 757 } 758 759 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 760 struct snd_ctl_elem_value *ucontrol) 761 { 762 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 763 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 764 struct wm8904_pdata *pdata = wm8904->pdata; 765 int value = ucontrol->value.integer.value[0]; 766 767 if (value >= pdata->num_retune_mobile_cfgs) 768 return -EINVAL; 769 770 wm8904->retune_mobile_cfg = value; 771 772 wm8904_set_retune_mobile(codec); 773 774 return 0; 775 } 776 777 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 778 struct snd_ctl_elem_value *ucontrol) 779 { 780 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 781 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 782 783 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 784 785 return 0; 786 } 787 788 static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 789 790 static int wm8904_set_deemph(struct snd_soc_codec *codec) 791 { 792 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 793 int val, i, best; 794 795 /* If we're using deemphasis select the nearest available sample 796 * rate. 797 */ 798 if (wm8904->deemph) { 799 best = 1; 800 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 801 if (abs(deemph_settings[i] - wm8904->fs) < 802 abs(deemph_settings[best] - wm8904->fs)) 803 best = i; 804 } 805 806 val = best << WM8904_DEEMPH_SHIFT; 807 } else { 808 val = 0; 809 } 810 811 dev_dbg(codec->dev, "Set deemphasis %d\n", val); 812 813 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 814 WM8904_DEEMPH_MASK, val); 815 } 816 817 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 818 struct snd_ctl_elem_value *ucontrol) 819 { 820 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 821 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 822 823 return wm8904->deemph; 824 } 825 826 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 827 struct snd_ctl_elem_value *ucontrol) 828 { 829 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 830 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 831 int deemph = ucontrol->value.enumerated.item[0]; 832 833 if (deemph > 1) 834 return -EINVAL; 835 836 wm8904->deemph = deemph; 837 838 return wm8904_set_deemph(codec); 839 } 840 841 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 842 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 843 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 844 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 845 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 846 847 static const char *input_mode_text[] = { 848 "Single-Ended", "Differential Line", "Differential Mic" 849 }; 850 851 static const struct soc_enum lin_mode = 852 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 853 854 static const struct soc_enum rin_mode = 855 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 856 857 static const char *hpf_mode_text[] = { 858 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 859 }; 860 861 static const struct soc_enum hpf_mode = 862 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 863 864 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 865 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 866 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 867 868 SOC_ENUM("Left Caputure Mode", lin_mode), 869 SOC_ENUM("Right Capture Mode", rin_mode), 870 871 /* No TLV since it depends on mode */ 872 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 873 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 874 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 875 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), 876 877 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 878 SOC_ENUM("High Pass Filter Mode", hpf_mode), 879 880 SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), 881 }; 882 883 static const char *drc_path_text[] = { 884 "ADC", "DAC" 885 }; 886 887 static const struct soc_enum drc_path = 888 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); 889 890 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 891 SOC_SINGLE_TLV("Digital Playback Boost Volume", 892 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 893 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 894 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 895 896 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 897 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 898 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 899 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 900 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 901 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 902 903 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 904 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 905 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 906 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 907 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 908 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 909 910 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 911 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 912 SOC_ENUM("DRC Path", drc_path), 913 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 914 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 915 wm8904_get_deemph, wm8904_put_deemph), 916 }; 917 918 static const struct snd_kcontrol_new wm8904_snd_controls[] = { 919 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 920 sidetone_tlv), 921 }; 922 923 static const struct snd_kcontrol_new wm8904_eq_controls[] = { 924 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 925 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 926 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 927 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 928 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 929 }; 930 931 static int cp_event(struct snd_soc_dapm_widget *w, 932 struct snd_kcontrol *kcontrol, int event) 933 { 934 BUG_ON(event != SND_SOC_DAPM_POST_PMU); 935 936 /* Maximum startup time */ 937 udelay(500); 938 939 return 0; 940 } 941 942 static int sysclk_event(struct snd_soc_dapm_widget *w, 943 struct snd_kcontrol *kcontrol, int event) 944 { 945 struct snd_soc_codec *codec = w->codec; 946 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 947 948 switch (event) { 949 case SND_SOC_DAPM_PRE_PMU: 950 /* If we're using the FLL then we only start it when 951 * required; we assume that the configuration has been 952 * done previously and all we need to do is kick it 953 * off. 954 */ 955 switch (wm8904->sysclk_src) { 956 case WM8904_CLK_FLL: 957 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 958 WM8904_FLL_OSC_ENA, 959 WM8904_FLL_OSC_ENA); 960 961 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 962 WM8904_FLL_ENA, 963 WM8904_FLL_ENA); 964 break; 965 966 default: 967 break; 968 } 969 break; 970 971 case SND_SOC_DAPM_POST_PMD: 972 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 973 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 974 break; 975 } 976 977 return 0; 978 } 979 980 static int out_pga_event(struct snd_soc_dapm_widget *w, 981 struct snd_kcontrol *kcontrol, int event) 982 { 983 struct snd_soc_codec *codec = w->codec; 984 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 985 int reg, val; 986 int dcs_mask; 987 int dcs_l, dcs_r; 988 int dcs_l_reg, dcs_r_reg; 989 int timeout; 990 int pwr_reg; 991 992 /* This code is shared between HP and LINEOUT; we do all our 993 * power management in stereo pairs to avoid latency issues so 994 * we reuse shift to identify which rather than strcmp() the 995 * name. */ 996 reg = w->shift; 997 998 switch (reg) { 999 case WM8904_ANALOGUE_HP_0: 1000 pwr_reg = WM8904_POWER_MANAGEMENT_2; 1001 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 1002 dcs_r_reg = WM8904_DC_SERVO_8; 1003 dcs_l_reg = WM8904_DC_SERVO_9; 1004 dcs_l = 0; 1005 dcs_r = 1; 1006 break; 1007 case WM8904_ANALOGUE_LINEOUT_0: 1008 pwr_reg = WM8904_POWER_MANAGEMENT_3; 1009 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 1010 dcs_r_reg = WM8904_DC_SERVO_6; 1011 dcs_l_reg = WM8904_DC_SERVO_7; 1012 dcs_l = 2; 1013 dcs_r = 3; 1014 break; 1015 default: 1016 BUG(); 1017 return -EINVAL; 1018 } 1019 1020 switch (event) { 1021 case SND_SOC_DAPM_PRE_PMU: 1022 /* Power on the PGAs */ 1023 snd_soc_update_bits(codec, pwr_reg, 1024 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1025 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 1026 1027 /* Power on the amplifier */ 1028 snd_soc_update_bits(codec, reg, 1029 WM8904_HPL_ENA | WM8904_HPR_ENA, 1030 WM8904_HPL_ENA | WM8904_HPR_ENA); 1031 1032 1033 /* Enable the first stage */ 1034 snd_soc_update_bits(codec, reg, 1035 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 1036 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 1037 1038 /* Power up the DC servo */ 1039 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1040 dcs_mask, dcs_mask); 1041 1042 /* Either calibrate the DC servo or restore cached state 1043 * if we have that. 1044 */ 1045 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 1046 dev_dbg(codec->dev, "Restoring DC servo state\n"); 1047 1048 snd_soc_write(codec, dcs_l_reg, 1049 wm8904->dcs_state[dcs_l]); 1050 snd_soc_write(codec, dcs_r_reg, 1051 wm8904->dcs_state[dcs_r]); 1052 1053 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); 1054 1055 timeout = 20; 1056 } else { 1057 dev_dbg(codec->dev, "Calibrating DC servo\n"); 1058 1059 snd_soc_write(codec, WM8904_DC_SERVO_1, 1060 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 1061 1062 timeout = 500; 1063 } 1064 1065 /* Wait for DC servo to complete */ 1066 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 1067 do { 1068 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); 1069 if ((val & dcs_mask) == dcs_mask) 1070 break; 1071 1072 msleep(1); 1073 } while (--timeout); 1074 1075 if ((val & dcs_mask) != dcs_mask) 1076 dev_warn(codec->dev, "DC servo timed out\n"); 1077 else 1078 dev_dbg(codec->dev, "DC servo ready\n"); 1079 1080 /* Enable the output stage */ 1081 snd_soc_update_bits(codec, reg, 1082 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1083 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 1084 break; 1085 1086 case SND_SOC_DAPM_POST_PMU: 1087 /* Unshort the output itself */ 1088 snd_soc_update_bits(codec, reg, 1089 WM8904_HPL_RMV_SHORT | 1090 WM8904_HPR_RMV_SHORT, 1091 WM8904_HPL_RMV_SHORT | 1092 WM8904_HPR_RMV_SHORT); 1093 1094 break; 1095 1096 case SND_SOC_DAPM_PRE_PMD: 1097 /* Short the output */ 1098 snd_soc_update_bits(codec, reg, 1099 WM8904_HPL_RMV_SHORT | 1100 WM8904_HPR_RMV_SHORT, 0); 1101 break; 1102 1103 case SND_SOC_DAPM_POST_PMD: 1104 /* Cache the DC servo configuration; this will be 1105 * invalidated if we change the configuration. */ 1106 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); 1107 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); 1108 1109 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1110 dcs_mask, 0); 1111 1112 /* Disable the amplifier input and output stages */ 1113 snd_soc_update_bits(codec, reg, 1114 WM8904_HPL_ENA | WM8904_HPR_ENA | 1115 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 1116 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1117 0); 1118 1119 /* PGAs too */ 1120 snd_soc_update_bits(codec, pwr_reg, 1121 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1122 0); 1123 break; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static const char *lin_text[] = { 1130 "IN1L", "IN2L", "IN3L" 1131 }; 1132 1133 static const struct soc_enum lin_enum = 1134 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); 1135 1136 static const struct snd_kcontrol_new lin_mux = 1137 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 1138 1139 static const struct soc_enum lin_inv_enum = 1140 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); 1141 1142 static const struct snd_kcontrol_new lin_inv_mux = 1143 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 1144 1145 static const char *rin_text[] = { 1146 "IN1R", "IN2R", "IN3R" 1147 }; 1148 1149 static const struct soc_enum rin_enum = 1150 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); 1151 1152 static const struct snd_kcontrol_new rin_mux = 1153 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 1154 1155 static const struct soc_enum rin_inv_enum = 1156 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); 1157 1158 static const struct snd_kcontrol_new rin_inv_mux = 1159 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 1160 1161 static const char *aif_text[] = { 1162 "Left", "Right" 1163 }; 1164 1165 static const struct soc_enum aifoutl_enum = 1166 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); 1167 1168 static const struct snd_kcontrol_new aifoutl_mux = 1169 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 1170 1171 static const struct soc_enum aifoutr_enum = 1172 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); 1173 1174 static const struct snd_kcontrol_new aifoutr_mux = 1175 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 1176 1177 static const struct soc_enum aifinl_enum = 1178 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); 1179 1180 static const struct snd_kcontrol_new aifinl_mux = 1181 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 1182 1183 static const struct soc_enum aifinr_enum = 1184 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); 1185 1186 static const struct snd_kcontrol_new aifinr_mux = 1187 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 1188 1189 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 1190 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 1191 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1192 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 1193 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 1194 }; 1195 1196 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 1197 SND_SOC_DAPM_INPUT("IN1L"), 1198 SND_SOC_DAPM_INPUT("IN1R"), 1199 SND_SOC_DAPM_INPUT("IN2L"), 1200 SND_SOC_DAPM_INPUT("IN2R"), 1201 SND_SOC_DAPM_INPUT("IN3L"), 1202 SND_SOC_DAPM_INPUT("IN3R"), 1203 1204 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), 1205 1206 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 1207 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1208 &lin_inv_mux), 1209 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 1210 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1211 &rin_inv_mux), 1212 1213 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 1214 NULL, 0), 1215 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 1216 NULL, 0), 1217 1218 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 1219 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 1220 1221 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 1222 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 1223 1224 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 1225 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 1226 }; 1227 1228 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 1229 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 1230 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 1231 1232 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 1233 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 1234 1235 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 1236 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 1237 1238 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 1239 SND_SOC_DAPM_POST_PMU), 1240 1241 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1242 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1243 1244 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1245 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1246 1247 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 1248 0, NULL, 0, out_pga_event, 1249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1250 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1251 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 1252 0, NULL, 0, out_pga_event, 1253 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1254 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1255 1256 SND_SOC_DAPM_OUTPUT("HPOUTL"), 1257 SND_SOC_DAPM_OUTPUT("HPOUTR"), 1258 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 1259 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 1260 }; 1261 1262 static const char *out_mux_text[] = { 1263 "DAC", "Bypass" 1264 }; 1265 1266 static const struct soc_enum hpl_enum = 1267 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); 1268 1269 static const struct snd_kcontrol_new hpl_mux = 1270 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1271 1272 static const struct soc_enum hpr_enum = 1273 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); 1274 1275 static const struct snd_kcontrol_new hpr_mux = 1276 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1277 1278 static const struct soc_enum linel_enum = 1279 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); 1280 1281 static const struct snd_kcontrol_new linel_mux = 1282 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1283 1284 static const struct soc_enum liner_enum = 1285 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); 1286 1287 static const struct snd_kcontrol_new liner_mux = 1288 SOC_DAPM_ENUM("LINEL Mux", liner_enum); 1289 1290 static const char *sidetone_text[] = { 1291 "None", "Left", "Right" 1292 }; 1293 1294 static const struct soc_enum dacl_sidetone_enum = 1295 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); 1296 1297 static const struct snd_kcontrol_new dacl_sidetone_mux = 1298 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1299 1300 static const struct soc_enum dacr_sidetone_enum = 1301 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); 1302 1303 static const struct snd_kcontrol_new dacr_sidetone_mux = 1304 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1305 1306 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1307 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1308 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1309 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1310 1311 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1312 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1313 1314 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1315 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1316 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1317 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1318 }; 1319 1320 static const struct snd_soc_dapm_route core_intercon[] = { 1321 { "CLK_DSP", NULL, "SYSCLK" }, 1322 { "TOCLK", NULL, "SYSCLK" }, 1323 }; 1324 1325 static const struct snd_soc_dapm_route adc_intercon[] = { 1326 { "Left Capture Mux", "IN1L", "IN1L" }, 1327 { "Left Capture Mux", "IN2L", "IN2L" }, 1328 { "Left Capture Mux", "IN3L", "IN3L" }, 1329 1330 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1331 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1332 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1333 1334 { "Right Capture Mux", "IN1R", "IN1R" }, 1335 { "Right Capture Mux", "IN2R", "IN2R" }, 1336 { "Right Capture Mux", "IN3R", "IN3R" }, 1337 1338 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1339 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1340 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1341 1342 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1343 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1344 1345 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1346 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1347 1348 { "AIFOUTL", "Left", "ADCL" }, 1349 { "AIFOUTL", "Right", "ADCR" }, 1350 { "AIFOUTR", "Left", "ADCL" }, 1351 { "AIFOUTR", "Right", "ADCR" }, 1352 1353 { "ADCL", NULL, "CLK_DSP" }, 1354 { "ADCL", NULL, "Left Capture PGA" }, 1355 1356 { "ADCR", NULL, "CLK_DSP" }, 1357 { "ADCR", NULL, "Right Capture PGA" }, 1358 }; 1359 1360 static const struct snd_soc_dapm_route dac_intercon[] = { 1361 { "DACL", "Right", "AIFINR" }, 1362 { "DACL", "Left", "AIFINL" }, 1363 { "DACL", NULL, "CLK_DSP" }, 1364 1365 { "DACR", "Right", "AIFINR" }, 1366 { "DACR", "Left", "AIFINL" }, 1367 { "DACR", NULL, "CLK_DSP" }, 1368 1369 { "Charge pump", NULL, "SYSCLK" }, 1370 1371 { "Headphone Output", NULL, "HPL PGA" }, 1372 { "Headphone Output", NULL, "HPR PGA" }, 1373 { "Headphone Output", NULL, "Charge pump" }, 1374 { "Headphone Output", NULL, "TOCLK" }, 1375 1376 { "Line Output", NULL, "LINEL PGA" }, 1377 { "Line Output", NULL, "LINER PGA" }, 1378 { "Line Output", NULL, "Charge pump" }, 1379 { "Line Output", NULL, "TOCLK" }, 1380 1381 { "HPOUTL", NULL, "Headphone Output" }, 1382 { "HPOUTR", NULL, "Headphone Output" }, 1383 1384 { "LINEOUTL", NULL, "Line Output" }, 1385 { "LINEOUTR", NULL, "Line Output" }, 1386 }; 1387 1388 static const struct snd_soc_dapm_route wm8904_intercon[] = { 1389 { "Left Sidetone", "Left", "ADCL" }, 1390 { "Left Sidetone", "Right", "ADCR" }, 1391 { "DACL", NULL, "Left Sidetone" }, 1392 1393 { "Right Sidetone", "Left", "ADCL" }, 1394 { "Right Sidetone", "Right", "ADCR" }, 1395 { "DACR", NULL, "Right Sidetone" }, 1396 1397 { "Left Bypass", NULL, "Class G" }, 1398 { "Left Bypass", NULL, "Left Capture PGA" }, 1399 1400 { "Right Bypass", NULL, "Class G" }, 1401 { "Right Bypass", NULL, "Right Capture PGA" }, 1402 1403 { "HPL Mux", "DAC", "DACL" }, 1404 { "HPL Mux", "Bypass", "Left Bypass" }, 1405 1406 { "HPR Mux", "DAC", "DACR" }, 1407 { "HPR Mux", "Bypass", "Right Bypass" }, 1408 1409 { "LINEL Mux", "DAC", "DACL" }, 1410 { "LINEL Mux", "Bypass", "Left Bypass" }, 1411 1412 { "LINER Mux", "DAC", "DACR" }, 1413 { "LINER Mux", "Bypass", "Right Bypass" }, 1414 1415 { "HPL PGA", NULL, "HPL Mux" }, 1416 { "HPR PGA", NULL, "HPR Mux" }, 1417 1418 { "LINEL PGA", NULL, "LINEL Mux" }, 1419 { "LINER PGA", NULL, "LINER Mux" }, 1420 }; 1421 1422 static const struct snd_soc_dapm_route wm8912_intercon[] = { 1423 { "HPL PGA", NULL, "DACL" }, 1424 { "HPR PGA", NULL, "DACR" }, 1425 1426 { "LINEL PGA", NULL, "DACL" }, 1427 { "LINER PGA", NULL, "DACR" }, 1428 }; 1429 1430 static int wm8904_add_widgets(struct snd_soc_codec *codec) 1431 { 1432 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1433 1434 snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, 1435 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1436 snd_soc_dapm_add_routes(codec, core_intercon, 1437 ARRAY_SIZE(core_intercon)); 1438 1439 switch (wm8904->devtype) { 1440 case WM8904: 1441 snd_soc_add_controls(codec, wm8904_adc_snd_controls, 1442 ARRAY_SIZE(wm8904_adc_snd_controls)); 1443 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1444 ARRAY_SIZE(wm8904_dac_snd_controls)); 1445 snd_soc_add_controls(codec, wm8904_snd_controls, 1446 ARRAY_SIZE(wm8904_snd_controls)); 1447 1448 snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, 1449 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1450 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1451 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1452 snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, 1453 ARRAY_SIZE(wm8904_dapm_widgets)); 1454 1455 snd_soc_dapm_add_routes(codec, core_intercon, 1456 ARRAY_SIZE(core_intercon)); 1457 snd_soc_dapm_add_routes(codec, adc_intercon, 1458 ARRAY_SIZE(adc_intercon)); 1459 snd_soc_dapm_add_routes(codec, dac_intercon, 1460 ARRAY_SIZE(dac_intercon)); 1461 snd_soc_dapm_add_routes(codec, wm8904_intercon, 1462 ARRAY_SIZE(wm8904_intercon)); 1463 break; 1464 1465 case WM8912: 1466 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1467 ARRAY_SIZE(wm8904_dac_snd_controls)); 1468 1469 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1470 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1471 1472 snd_soc_dapm_add_routes(codec, dac_intercon, 1473 ARRAY_SIZE(dac_intercon)); 1474 snd_soc_dapm_add_routes(codec, wm8912_intercon, 1475 ARRAY_SIZE(wm8912_intercon)); 1476 break; 1477 } 1478 1479 snd_soc_dapm_new_widgets(codec); 1480 return 0; 1481 } 1482 1483 static struct { 1484 int ratio; 1485 unsigned int clk_sys_rate; 1486 } clk_sys_rates[] = { 1487 { 64, 0 }, 1488 { 128, 1 }, 1489 { 192, 2 }, 1490 { 256, 3 }, 1491 { 384, 4 }, 1492 { 512, 5 }, 1493 { 786, 6 }, 1494 { 1024, 7 }, 1495 { 1408, 8 }, 1496 { 1536, 9 }, 1497 }; 1498 1499 static struct { 1500 int rate; 1501 int sample_rate; 1502 } sample_rates[] = { 1503 { 8000, 0 }, 1504 { 11025, 1 }, 1505 { 12000, 1 }, 1506 { 16000, 2 }, 1507 { 22050, 3 }, 1508 { 24000, 3 }, 1509 { 32000, 4 }, 1510 { 44100, 5 }, 1511 { 48000, 5 }, 1512 }; 1513 1514 static struct { 1515 int div; /* *10 due to .5s */ 1516 int bclk_div; 1517 } bclk_divs[] = { 1518 { 10, 0 }, 1519 { 15, 1 }, 1520 { 20, 2 }, 1521 { 30, 3 }, 1522 { 40, 4 }, 1523 { 50, 5 }, 1524 { 55, 6 }, 1525 { 60, 7 }, 1526 { 80, 8 }, 1527 { 100, 9 }, 1528 { 110, 10 }, 1529 { 120, 11 }, 1530 { 160, 12 }, 1531 { 200, 13 }, 1532 { 220, 14 }, 1533 { 240, 16 }, 1534 { 200, 17 }, 1535 { 320, 18 }, 1536 { 440, 19 }, 1537 { 480, 20 }, 1538 }; 1539 1540 1541 static int wm8904_hw_params(struct snd_pcm_substream *substream, 1542 struct snd_pcm_hw_params *params, 1543 struct snd_soc_dai *dai) 1544 { 1545 struct snd_soc_codec *codec = dai->codec; 1546 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1547 int ret, i, best, best_val, cur_val; 1548 unsigned int aif1 = 0; 1549 unsigned int aif2 = 0; 1550 unsigned int aif3 = 0; 1551 unsigned int clock1 = 0; 1552 unsigned int dac_digital1 = 0; 1553 1554 /* What BCLK do we need? */ 1555 wm8904->fs = params_rate(params); 1556 if (wm8904->tdm_slots) { 1557 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1558 wm8904->tdm_slots, wm8904->tdm_width); 1559 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1560 wm8904->tdm_width, 2, 1561 wm8904->tdm_slots); 1562 } else { 1563 wm8904->bclk = snd_soc_params_to_bclk(params); 1564 } 1565 1566 switch (params_format(params)) { 1567 case SNDRV_PCM_FORMAT_S16_LE: 1568 break; 1569 case SNDRV_PCM_FORMAT_S20_3LE: 1570 aif1 |= 0x40; 1571 break; 1572 case SNDRV_PCM_FORMAT_S24_LE: 1573 aif1 |= 0x80; 1574 break; 1575 case SNDRV_PCM_FORMAT_S32_LE: 1576 aif1 |= 0xc0; 1577 break; 1578 default: 1579 return -EINVAL; 1580 } 1581 1582 1583 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1584 1585 ret = wm8904_configure_clocking(codec); 1586 if (ret != 0) 1587 return ret; 1588 1589 /* Select nearest CLK_SYS_RATE */ 1590 best = 0; 1591 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1592 - wm8904->fs); 1593 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1594 cur_val = abs((wm8904->sysclk_rate / 1595 clk_sys_rates[i].ratio) - wm8904->fs);; 1596 if (cur_val < best_val) { 1597 best = i; 1598 best_val = cur_val; 1599 } 1600 } 1601 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1602 clk_sys_rates[best].ratio); 1603 clock1 |= (clk_sys_rates[best].clk_sys_rate 1604 << WM8904_CLK_SYS_RATE_SHIFT); 1605 1606 /* SAMPLE_RATE */ 1607 best = 0; 1608 best_val = abs(wm8904->fs - sample_rates[0].rate); 1609 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1610 /* Closest match */ 1611 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1612 if (cur_val < best_val) { 1613 best = i; 1614 best_val = cur_val; 1615 } 1616 } 1617 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1618 sample_rates[best].rate); 1619 clock1 |= (sample_rates[best].sample_rate 1620 << WM8904_SAMPLE_RATE_SHIFT); 1621 1622 /* Enable sloping stopband filter for low sample rates */ 1623 if (wm8904->fs <= 24000) 1624 dac_digital1 |= WM8904_DAC_SB_FILT; 1625 1626 /* BCLK_DIV */ 1627 best = 0; 1628 best_val = INT_MAX; 1629 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1630 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1631 - wm8904->bclk; 1632 if (cur_val < 0) /* Table is sorted */ 1633 break; 1634 if (cur_val < best_val) { 1635 best = i; 1636 best_val = cur_val; 1637 } 1638 } 1639 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1640 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1641 bclk_divs[best].div, wm8904->bclk); 1642 aif2 |= bclk_divs[best].bclk_div; 1643 1644 /* LRCLK is a simple fraction of BCLK */ 1645 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1646 aif3 |= wm8904->bclk / wm8904->fs; 1647 1648 /* Apply the settings */ 1649 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 1650 WM8904_DAC_SB_FILT, dac_digital1); 1651 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1652 WM8904_AIF_WL_MASK, aif1); 1653 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, 1654 WM8904_BCLK_DIV_MASK, aif2); 1655 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1656 WM8904_LRCLK_RATE_MASK, aif3); 1657 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, 1658 WM8904_SAMPLE_RATE_MASK | 1659 WM8904_CLK_SYS_RATE_MASK, clock1); 1660 1661 /* Update filters for the new settings */ 1662 wm8904_set_retune_mobile(codec); 1663 wm8904_set_deemph(codec); 1664 1665 return 0; 1666 } 1667 1668 1669 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1670 unsigned int freq, int dir) 1671 { 1672 struct snd_soc_codec *codec = dai->codec; 1673 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); 1674 1675 switch (clk_id) { 1676 case WM8904_CLK_MCLK: 1677 priv->sysclk_src = clk_id; 1678 priv->mclk_rate = freq; 1679 break; 1680 1681 case WM8904_CLK_FLL: 1682 priv->sysclk_src = clk_id; 1683 break; 1684 1685 default: 1686 return -EINVAL; 1687 } 1688 1689 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1690 1691 wm8904_configure_clocking(codec); 1692 1693 return 0; 1694 } 1695 1696 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1697 { 1698 struct snd_soc_codec *codec = dai->codec; 1699 unsigned int aif1 = 0; 1700 unsigned int aif3 = 0; 1701 1702 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1703 case SND_SOC_DAIFMT_CBS_CFS: 1704 break; 1705 case SND_SOC_DAIFMT_CBS_CFM: 1706 aif3 |= WM8904_LRCLK_DIR; 1707 break; 1708 case SND_SOC_DAIFMT_CBM_CFS: 1709 aif1 |= WM8904_BCLK_DIR; 1710 break; 1711 case SND_SOC_DAIFMT_CBM_CFM: 1712 aif1 |= WM8904_BCLK_DIR; 1713 aif3 |= WM8904_LRCLK_DIR; 1714 break; 1715 default: 1716 return -EINVAL; 1717 } 1718 1719 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1720 case SND_SOC_DAIFMT_DSP_B: 1721 aif1 |= WM8904_AIF_LRCLK_INV; 1722 case SND_SOC_DAIFMT_DSP_A: 1723 aif1 |= 0x3; 1724 break; 1725 case SND_SOC_DAIFMT_I2S: 1726 aif1 |= 0x2; 1727 break; 1728 case SND_SOC_DAIFMT_RIGHT_J: 1729 break; 1730 case SND_SOC_DAIFMT_LEFT_J: 1731 aif1 |= 0x1; 1732 break; 1733 default: 1734 return -EINVAL; 1735 } 1736 1737 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1738 case SND_SOC_DAIFMT_DSP_A: 1739 case SND_SOC_DAIFMT_DSP_B: 1740 /* frame inversion not valid for DSP modes */ 1741 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1742 case SND_SOC_DAIFMT_NB_NF: 1743 break; 1744 case SND_SOC_DAIFMT_IB_NF: 1745 aif1 |= WM8904_AIF_BCLK_INV; 1746 break; 1747 default: 1748 return -EINVAL; 1749 } 1750 break; 1751 1752 case SND_SOC_DAIFMT_I2S: 1753 case SND_SOC_DAIFMT_RIGHT_J: 1754 case SND_SOC_DAIFMT_LEFT_J: 1755 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1756 case SND_SOC_DAIFMT_NB_NF: 1757 break; 1758 case SND_SOC_DAIFMT_IB_IF: 1759 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1760 break; 1761 case SND_SOC_DAIFMT_IB_NF: 1762 aif1 |= WM8904_AIF_BCLK_INV; 1763 break; 1764 case SND_SOC_DAIFMT_NB_IF: 1765 aif1 |= WM8904_AIF_LRCLK_INV; 1766 break; 1767 default: 1768 return -EINVAL; 1769 } 1770 break; 1771 default: 1772 return -EINVAL; 1773 } 1774 1775 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1776 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1777 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1778 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1779 WM8904_LRCLK_DIR, aif3); 1780 1781 return 0; 1782 } 1783 1784 1785 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1786 unsigned int rx_mask, int slots, int slot_width) 1787 { 1788 struct snd_soc_codec *codec = dai->codec; 1789 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1790 int aif1 = 0; 1791 1792 /* Don't need to validate anything if we're turning off TDM */ 1793 if (slots == 0) 1794 goto out; 1795 1796 /* Note that we allow configurations we can't handle ourselves - 1797 * for example, we can generate clocks for slots 2 and up even if 1798 * we can't use those slots ourselves. 1799 */ 1800 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1801 1802 switch (rx_mask) { 1803 case 3: 1804 break; 1805 case 0xc: 1806 aif1 |= WM8904_AIFADC_TDM_CHAN; 1807 break; 1808 default: 1809 return -EINVAL; 1810 } 1811 1812 1813 switch (tx_mask) { 1814 case 3: 1815 break; 1816 case 0xc: 1817 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1818 break; 1819 default: 1820 return -EINVAL; 1821 } 1822 1823 out: 1824 wm8904->tdm_width = slot_width; 1825 wm8904->tdm_slots = slots / 2; 1826 1827 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1828 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1829 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1830 1831 return 0; 1832 } 1833 1834 struct _fll_div { 1835 u16 fll_fratio; 1836 u16 fll_outdiv; 1837 u16 fll_clk_ref_div; 1838 u16 n; 1839 u16 k; 1840 }; 1841 1842 /* The size in bits of the FLL divide multiplied by 10 1843 * to allow rounding later */ 1844 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1845 1846 static struct { 1847 unsigned int min; 1848 unsigned int max; 1849 u16 fll_fratio; 1850 int ratio; 1851 } fll_fratios[] = { 1852 { 0, 64000, 4, 16 }, 1853 { 64000, 128000, 3, 8 }, 1854 { 128000, 256000, 2, 4 }, 1855 { 256000, 1000000, 1, 2 }, 1856 { 1000000, 13500000, 0, 1 }, 1857 }; 1858 1859 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1860 unsigned int Fout) 1861 { 1862 u64 Kpart; 1863 unsigned int K, Ndiv, Nmod, target; 1864 unsigned int div; 1865 int i; 1866 1867 /* Fref must be <=13.5MHz */ 1868 div = 1; 1869 fll_div->fll_clk_ref_div = 0; 1870 while ((Fref / div) > 13500000) { 1871 div *= 2; 1872 fll_div->fll_clk_ref_div++; 1873 1874 if (div > 8) { 1875 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1876 Fref); 1877 return -EINVAL; 1878 } 1879 } 1880 1881 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1882 1883 /* Apply the division for our remaining calculations */ 1884 Fref /= div; 1885 1886 /* Fvco should be 90-100MHz; don't check the upper bound */ 1887 div = 4; 1888 while (Fout * div < 90000000) { 1889 div++; 1890 if (div > 64) { 1891 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1892 Fout); 1893 return -EINVAL; 1894 } 1895 } 1896 target = Fout * div; 1897 fll_div->fll_outdiv = div - 1; 1898 1899 pr_debug("Fvco=%dHz\n", target); 1900 1901 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1902 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1903 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1904 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1905 target /= fll_fratios[i].ratio; 1906 break; 1907 } 1908 } 1909 if (i == ARRAY_SIZE(fll_fratios)) { 1910 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1911 return -EINVAL; 1912 } 1913 1914 /* Now, calculate N.K */ 1915 Ndiv = target / Fref; 1916 1917 fll_div->n = Ndiv; 1918 Nmod = target % Fref; 1919 pr_debug("Nmod=%d\n", Nmod); 1920 1921 /* Calculate fractional part - scale up so we can round. */ 1922 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1923 1924 do_div(Kpart, Fref); 1925 1926 K = Kpart & 0xFFFFFFFF; 1927 1928 if ((K % 10) >= 5) 1929 K += 5; 1930 1931 /* Move down to proper range now rounding is done */ 1932 fll_div->k = K / 10; 1933 1934 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1935 fll_div->n, fll_div->k, 1936 fll_div->fll_fratio, fll_div->fll_outdiv, 1937 fll_div->fll_clk_ref_div); 1938 1939 return 0; 1940 } 1941 1942 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1943 unsigned int Fref, unsigned int Fout) 1944 { 1945 struct snd_soc_codec *codec = dai->codec; 1946 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1947 struct _fll_div fll_div; 1948 int ret, val; 1949 int clock2, fll1; 1950 1951 /* Any change? */ 1952 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1953 Fout == wm8904->fll_fout) 1954 return 0; 1955 1956 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 1957 1958 if (Fout == 0) { 1959 dev_dbg(codec->dev, "FLL disabled\n"); 1960 1961 wm8904->fll_fref = 0; 1962 wm8904->fll_fout = 0; 1963 1964 /* Gate SYSCLK to avoid glitches */ 1965 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 1966 WM8904_CLK_SYS_ENA, 0); 1967 1968 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 1969 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1970 1971 goto out; 1972 } 1973 1974 /* Validate the FLL ID */ 1975 switch (source) { 1976 case WM8904_FLL_MCLK: 1977 case WM8904_FLL_LRCLK: 1978 case WM8904_FLL_BCLK: 1979 ret = fll_factors(&fll_div, Fref, Fout); 1980 if (ret != 0) 1981 return ret; 1982 break; 1983 1984 case WM8904_FLL_FREE_RUNNING: 1985 dev_dbg(codec->dev, "Using free running FLL\n"); 1986 /* Force 12MHz and output/4 for now */ 1987 Fout = 12000000; 1988 Fref = 12000000; 1989 1990 memset(&fll_div, 0, sizeof(fll_div)); 1991 fll_div.fll_outdiv = 3; 1992 break; 1993 1994 default: 1995 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 1996 return -EINVAL; 1997 } 1998 1999 /* Save current state then disable the FLL and SYSCLK to avoid 2000 * misclocking */ 2001 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); 2002 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2003 WM8904_CLK_SYS_ENA, 0); 2004 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2005 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 2006 2007 /* Unlock forced oscilator control to switch it on/off */ 2008 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2009 WM8904_USER_KEY, WM8904_USER_KEY); 2010 2011 if (fll_id == WM8904_FLL_FREE_RUNNING) { 2012 val = WM8904_FLL_FRC_NCO; 2013 } else { 2014 val = 0; 2015 } 2016 2017 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 2018 val); 2019 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2020 WM8904_USER_KEY, 0); 2021 2022 switch (fll_id) { 2023 case WM8904_FLL_MCLK: 2024 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2025 WM8904_FLL_CLK_REF_SRC_MASK, 0); 2026 break; 2027 2028 case WM8904_FLL_LRCLK: 2029 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2030 WM8904_FLL_CLK_REF_SRC_MASK, 1); 2031 break; 2032 2033 case WM8904_FLL_BCLK: 2034 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2035 WM8904_FLL_CLK_REF_SRC_MASK, 2); 2036 break; 2037 } 2038 2039 if (fll_div.k) 2040 val = WM8904_FLL_FRACN_ENA; 2041 else 2042 val = 0; 2043 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2044 WM8904_FLL_FRACN_ENA, val); 2045 2046 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, 2047 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 2048 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 2049 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 2050 2051 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); 2052 2053 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 2054 fll_div.n << WM8904_FLL_N_SHIFT); 2055 2056 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2057 WM8904_FLL_CLK_REF_DIV_MASK, 2058 fll_div.fll_clk_ref_div 2059 << WM8904_FLL_CLK_REF_DIV_SHIFT); 2060 2061 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2062 2063 wm8904->fll_fref = Fref; 2064 wm8904->fll_fout = Fout; 2065 wm8904->fll_src = source; 2066 2067 /* Enable the FLL if it was previously active */ 2068 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2069 WM8904_FLL_OSC_ENA, fll1); 2070 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2071 WM8904_FLL_ENA, fll1); 2072 2073 out: 2074 /* Reenable SYSCLK if it was previously active */ 2075 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2076 WM8904_CLK_SYS_ENA, clock2); 2077 2078 return 0; 2079 } 2080 2081 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 2082 { 2083 struct snd_soc_codec *codec = codec_dai->codec; 2084 int val; 2085 2086 if (mute) 2087 val = WM8904_DAC_MUTE; 2088 else 2089 val = 0; 2090 2091 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 2092 2093 return 0; 2094 } 2095 2096 static void wm8904_sync_cache(struct snd_soc_codec *codec) 2097 { 2098 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2099 int i; 2100 2101 if (!codec->cache_sync) 2102 return; 2103 2104 codec->cache_only = 0; 2105 2106 /* Sync back cached values if they're different from the 2107 * hardware default. 2108 */ 2109 for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { 2110 if (!wm8904_access[i].writable) 2111 continue; 2112 2113 if (wm8904->reg_cache[i] == wm8904_reg[i]) 2114 continue; 2115 2116 snd_soc_write(codec, i, wm8904->reg_cache[i]); 2117 } 2118 2119 codec->cache_sync = 0; 2120 } 2121 2122 static int wm8904_set_bias_level(struct snd_soc_codec *codec, 2123 enum snd_soc_bias_level level) 2124 { 2125 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2126 int ret; 2127 2128 switch (level) { 2129 case SND_SOC_BIAS_ON: 2130 break; 2131 2132 case SND_SOC_BIAS_PREPARE: 2133 /* VMID resistance 2*50k */ 2134 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2135 WM8904_VMID_RES_MASK, 2136 0x1 << WM8904_VMID_RES_SHIFT); 2137 2138 /* Normal bias current */ 2139 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2140 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 2141 break; 2142 2143 case SND_SOC_BIAS_STANDBY: 2144 if (codec->bias_level == SND_SOC_BIAS_OFF) { 2145 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2146 wm8904->supplies); 2147 if (ret != 0) { 2148 dev_err(codec->dev, 2149 "Failed to enable supplies: %d\n", 2150 ret); 2151 return ret; 2152 } 2153 2154 wm8904_sync_cache(codec); 2155 2156 /* Enable bias */ 2157 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2158 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 2159 2160 /* Enable VMID, VMID buffering, 2*5k resistance */ 2161 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2162 WM8904_VMID_ENA | 2163 WM8904_VMID_RES_MASK, 2164 WM8904_VMID_ENA | 2165 0x3 << WM8904_VMID_RES_SHIFT); 2166 2167 /* Let VMID ramp */ 2168 msleep(1); 2169 } 2170 2171 /* Maintain VMID with 2*250k */ 2172 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2173 WM8904_VMID_RES_MASK, 2174 0x2 << WM8904_VMID_RES_SHIFT); 2175 2176 /* Bias current *0.5 */ 2177 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2178 WM8904_ISEL_MASK, 0); 2179 break; 2180 2181 case SND_SOC_BIAS_OFF: 2182 /* Turn off VMID */ 2183 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2184 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 2185 2186 /* Stop bias generation */ 2187 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2188 WM8904_BIAS_ENA, 0); 2189 2190 #ifdef CONFIG_REGULATOR 2191 /* Post 2.6.34 we will be able to get a callback when 2192 * the regulators are disabled which we can use but 2193 * for now just assume that the power will be cut if 2194 * the regulator API is in use. 2195 */ 2196 codec->cache_sync = 1; 2197 #endif 2198 2199 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 2200 wm8904->supplies); 2201 break; 2202 } 2203 codec->bias_level = level; 2204 return 0; 2205 } 2206 2207 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 2208 2209 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2210 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2211 2212 static struct snd_soc_dai_ops wm8904_dai_ops = { 2213 .set_sysclk = wm8904_set_sysclk, 2214 .set_fmt = wm8904_set_fmt, 2215 .set_tdm_slot = wm8904_set_tdm_slot, 2216 .set_pll = wm8904_set_fll, 2217 .hw_params = wm8904_hw_params, 2218 .digital_mute = wm8904_digital_mute, 2219 }; 2220 2221 struct snd_soc_dai wm8904_dai = { 2222 .name = "WM8904", 2223 .playback = { 2224 .stream_name = "Playback", 2225 .channels_min = 2, 2226 .channels_max = 2, 2227 .rates = WM8904_RATES, 2228 .formats = WM8904_FORMATS, 2229 }, 2230 .capture = { 2231 .stream_name = "Capture", 2232 .channels_min = 2, 2233 .channels_max = 2, 2234 .rates = WM8904_RATES, 2235 .formats = WM8904_FORMATS, 2236 }, 2237 .ops = &wm8904_dai_ops, 2238 .symmetric_rates = 1, 2239 }; 2240 EXPORT_SYMBOL_GPL(wm8904_dai); 2241 2242 #ifdef CONFIG_PM 2243 static int wm8904_suspend(struct platform_device *pdev, pm_message_t state) 2244 { 2245 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2246 struct snd_soc_codec *codec = socdev->card->codec; 2247 2248 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2249 2250 return 0; 2251 } 2252 2253 static int wm8904_resume(struct platform_device *pdev) 2254 { 2255 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2256 struct snd_soc_codec *codec = socdev->card->codec; 2257 2258 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2259 2260 return 0; 2261 } 2262 #else 2263 #define wm8904_suspend NULL 2264 #define wm8904_resume NULL 2265 #endif 2266 2267 static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904) 2268 { 2269 struct snd_soc_codec *codec = &wm8904->codec; 2270 struct wm8904_pdata *pdata = wm8904->pdata; 2271 struct snd_kcontrol_new control = 2272 SOC_ENUM_EXT("EQ Mode", 2273 wm8904->retune_mobile_enum, 2274 wm8904_get_retune_mobile_enum, 2275 wm8904_put_retune_mobile_enum); 2276 int ret, i, j; 2277 const char **t; 2278 2279 /* We need an array of texts for the enum API but the number 2280 * of texts is likely to be less than the number of 2281 * configurations due to the sample rate dependency of the 2282 * configurations. */ 2283 wm8904->num_retune_mobile_texts = 0; 2284 wm8904->retune_mobile_texts = NULL; 2285 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2286 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 2287 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2288 wm8904->retune_mobile_texts[j]) == 0) 2289 break; 2290 } 2291 2292 if (j != wm8904->num_retune_mobile_texts) 2293 continue; 2294 2295 /* Expand the array... */ 2296 t = krealloc(wm8904->retune_mobile_texts, 2297 sizeof(char *) * 2298 (wm8904->num_retune_mobile_texts + 1), 2299 GFP_KERNEL); 2300 if (t == NULL) 2301 continue; 2302 2303 /* ...store the new entry... */ 2304 t[wm8904->num_retune_mobile_texts] = 2305 pdata->retune_mobile_cfgs[i].name; 2306 2307 /* ...and remember the new version. */ 2308 wm8904->num_retune_mobile_texts++; 2309 wm8904->retune_mobile_texts = t; 2310 } 2311 2312 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2313 wm8904->num_retune_mobile_texts); 2314 2315 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; 2316 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2317 2318 ret = snd_soc_add_controls(&wm8904->codec, &control, 1); 2319 if (ret != 0) 2320 dev_err(wm8904->codec.dev, 2321 "Failed to add ReTune Mobile control: %d\n", ret); 2322 } 2323 2324 static void wm8904_handle_pdata(struct wm8904_priv *wm8904) 2325 { 2326 struct snd_soc_codec *codec = &wm8904->codec; 2327 struct wm8904_pdata *pdata = wm8904->pdata; 2328 int ret, i; 2329 2330 if (!pdata) { 2331 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, 2332 ARRAY_SIZE(wm8904_eq_controls)); 2333 return; 2334 } 2335 2336 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2337 2338 if (pdata->num_drc_cfgs) { 2339 struct snd_kcontrol_new control = 2340 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2341 wm8904_get_drc_enum, wm8904_put_drc_enum); 2342 2343 /* We need an array of texts for the enum API */ 2344 wm8904->drc_texts = kmalloc(sizeof(char *) 2345 * pdata->num_drc_cfgs, GFP_KERNEL); 2346 if (!wm8904->drc_texts) { 2347 dev_err(wm8904->codec.dev, 2348 "Failed to allocate %d DRC config texts\n", 2349 pdata->num_drc_cfgs); 2350 return; 2351 } 2352 2353 for (i = 0; i < pdata->num_drc_cfgs; i++) 2354 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2355 2356 wm8904->drc_enum.max = pdata->num_drc_cfgs; 2357 wm8904->drc_enum.texts = wm8904->drc_texts; 2358 2359 ret = snd_soc_add_controls(&wm8904->codec, &control, 1); 2360 if (ret != 0) 2361 dev_err(wm8904->codec.dev, 2362 "Failed to add DRC mode control: %d\n", ret); 2363 2364 wm8904_set_drc(codec); 2365 } 2366 2367 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2368 pdata->num_retune_mobile_cfgs); 2369 2370 if (pdata->num_retune_mobile_cfgs) 2371 wm8904_handle_retune_mobile_pdata(wm8904); 2372 else 2373 snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, 2374 ARRAY_SIZE(wm8904_eq_controls)); 2375 } 2376 2377 static int wm8904_probe(struct platform_device *pdev) 2378 { 2379 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2380 struct snd_soc_codec *codec; 2381 int ret = 0; 2382 2383 if (wm8904_codec == NULL) { 2384 dev_err(&pdev->dev, "Codec device not registered\n"); 2385 return -ENODEV; 2386 } 2387 2388 socdev->card->codec = wm8904_codec; 2389 codec = wm8904_codec; 2390 2391 /* register pcms */ 2392 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 2393 if (ret < 0) { 2394 dev_err(codec->dev, "failed to create pcms: %d\n", ret); 2395 goto pcm_err; 2396 } 2397 2398 wm8904_handle_pdata(snd_soc_codec_get_drvdata(codec)); 2399 2400 wm8904_add_widgets(codec); 2401 2402 return ret; 2403 2404 pcm_err: 2405 return ret; 2406 } 2407 2408 static int wm8904_remove(struct platform_device *pdev) 2409 { 2410 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2411 2412 snd_soc_free_pcms(socdev); 2413 snd_soc_dapm_free(socdev); 2414 2415 return 0; 2416 } 2417 2418 struct snd_soc_codec_device soc_codec_dev_wm8904 = { 2419 .probe = wm8904_probe, 2420 .remove = wm8904_remove, 2421 .suspend = wm8904_suspend, 2422 .resume = wm8904_resume, 2423 }; 2424 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904); 2425 2426 static int wm8904_register(struct wm8904_priv *wm8904, 2427 enum snd_soc_control_type control) 2428 { 2429 struct wm8904_pdata *pdata = wm8904->pdata; 2430 int ret; 2431 struct snd_soc_codec *codec = &wm8904->codec; 2432 int i; 2433 2434 if (wm8904_codec) { 2435 dev_err(codec->dev, "Another WM8904 is registered\n"); 2436 return -EINVAL; 2437 } 2438 2439 mutex_init(&codec->mutex); 2440 INIT_LIST_HEAD(&codec->dapm_widgets); 2441 INIT_LIST_HEAD(&codec->dapm_paths); 2442 2443 snd_soc_codec_set_drvdata(codec, wm8904); 2444 codec->name = "WM8904"; 2445 codec->owner = THIS_MODULE; 2446 codec->bias_level = SND_SOC_BIAS_OFF; 2447 codec->set_bias_level = wm8904_set_bias_level; 2448 codec->dai = &wm8904_dai; 2449 codec->num_dai = 1; 2450 codec->reg_cache_size = WM8904_MAX_REGISTER; 2451 codec->reg_cache = &wm8904->reg_cache; 2452 codec->volatile_register = wm8904_volatile_register; 2453 codec->cache_sync = 1; 2454 codec->idle_bias_off = 1; 2455 2456 switch (wm8904->devtype) { 2457 case WM8904: 2458 break; 2459 case WM8912: 2460 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2461 break; 2462 default: 2463 dev_err(codec->dev, "Unknown device type %d\n", 2464 wm8904->devtype); 2465 return -EINVAL; 2466 } 2467 2468 memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg)); 2469 2470 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control); 2471 if (ret != 0) { 2472 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2473 goto err; 2474 } 2475 2476 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2477 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2478 2479 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), 2480 wm8904->supplies); 2481 if (ret != 0) { 2482 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2483 goto err; 2484 } 2485 2486 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2487 wm8904->supplies); 2488 if (ret != 0) { 2489 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2490 goto err_get; 2491 } 2492 2493 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); 2494 if (ret < 0) { 2495 dev_err(codec->dev, "Failed to read ID register\n"); 2496 goto err_enable; 2497 } 2498 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { 2499 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); 2500 ret = -EINVAL; 2501 goto err_enable; 2502 } 2503 2504 ret = snd_soc_read(codec, WM8904_REVISION); 2505 if (ret < 0) { 2506 dev_err(codec->dev, "Failed to read device revision: %d\n", 2507 ret); 2508 goto err_enable; 2509 } 2510 dev_info(codec->dev, "revision %c\n", ret + 'A'); 2511 2512 ret = wm8904_reset(codec); 2513 if (ret < 0) { 2514 dev_err(codec->dev, "Failed to issue reset\n"); 2515 goto err_enable; 2516 } 2517 2518 wm8904_dai.dev = codec->dev; 2519 2520 /* Change some default settings - latch VU and enable ZC */ 2521 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; 2522 wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; 2523 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; 2524 wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; 2525 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | 2526 WM8904_HPOUTLZC; 2527 wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | 2528 WM8904_HPOUTRZC; 2529 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | 2530 WM8904_LINEOUTLZC; 2531 wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | 2532 WM8904_LINEOUTRZC; 2533 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; 2534 2535 /* Apply configuration from the platform data. */ 2536 if (wm8904->pdata) { 2537 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2538 if (!pdata->gpio_cfg[i]) 2539 continue; 2540 2541 wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i] 2542 = pdata->gpio_cfg[i] & 0xffff; 2543 } 2544 2545 /* Zero is the default value for these anyway */ 2546 for (i = 0; i < WM8904_MIC_REGS; i++) 2547 wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2548 = pdata->mic_cfg[i]; 2549 } 2550 2551 /* Set Class W by default - this will be managed by the Class 2552 * G widget at runtime where bypass paths are available. 2553 */ 2554 wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; 2555 2556 /* Use normal bias source */ 2557 wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; 2558 2559 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2560 2561 /* Bias level configuration will have done an extra enable */ 2562 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2563 2564 wm8904_codec = codec; 2565 2566 ret = snd_soc_register_codec(codec); 2567 if (ret != 0) { 2568 dev_err(codec->dev, "Failed to register codec: %d\n", ret); 2569 return ret; 2570 } 2571 2572 ret = snd_soc_register_dai(&wm8904_dai); 2573 if (ret != 0) { 2574 dev_err(codec->dev, "Failed to register DAI: %d\n", ret); 2575 snd_soc_unregister_codec(codec); 2576 return ret; 2577 } 2578 2579 return 0; 2580 2581 err_enable: 2582 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2583 err_get: 2584 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2585 err: 2586 kfree(wm8904); 2587 return ret; 2588 } 2589 2590 static void wm8904_unregister(struct wm8904_priv *wm8904) 2591 { 2592 wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF); 2593 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2594 snd_soc_unregister_dai(&wm8904_dai); 2595 snd_soc_unregister_codec(&wm8904->codec); 2596 kfree(wm8904); 2597 wm8904_codec = NULL; 2598 } 2599 2600 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2601 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, 2602 const struct i2c_device_id *id) 2603 { 2604 struct wm8904_priv *wm8904; 2605 struct snd_soc_codec *codec; 2606 2607 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); 2608 if (wm8904 == NULL) 2609 return -ENOMEM; 2610 2611 codec = &wm8904->codec; 2612 codec->hw_write = (hw_write_t)i2c_master_send; 2613 2614 wm8904->devtype = id->driver_data; 2615 2616 i2c_set_clientdata(i2c, wm8904); 2617 codec->control_data = i2c; 2618 wm8904->pdata = i2c->dev.platform_data; 2619 2620 codec->dev = &i2c->dev; 2621 2622 return wm8904_register(wm8904, SND_SOC_I2C); 2623 } 2624 2625 static __devexit int wm8904_i2c_remove(struct i2c_client *client) 2626 { 2627 struct wm8904_priv *wm8904 = i2c_get_clientdata(client); 2628 wm8904_unregister(wm8904); 2629 return 0; 2630 } 2631 2632 static const struct i2c_device_id wm8904_i2c_id[] = { 2633 { "wm8904", WM8904 }, 2634 { "wm8912", WM8912 }, 2635 { } 2636 }; 2637 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2638 2639 static struct i2c_driver wm8904_i2c_driver = { 2640 .driver = { 2641 .name = "WM8904", 2642 .owner = THIS_MODULE, 2643 }, 2644 .probe = wm8904_i2c_probe, 2645 .remove = __devexit_p(wm8904_i2c_remove), 2646 .id_table = wm8904_i2c_id, 2647 }; 2648 #endif 2649 2650 static int __init wm8904_modinit(void) 2651 { 2652 int ret; 2653 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2654 ret = i2c_add_driver(&wm8904_i2c_driver); 2655 if (ret != 0) { 2656 printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n", 2657 ret); 2658 } 2659 #endif 2660 return 0; 2661 } 2662 module_init(wm8904_modinit); 2663 2664 static void __exit wm8904_exit(void) 2665 { 2666 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2667 i2c_del_driver(&wm8904_i2c_driver); 2668 #endif 2669 } 2670 module_exit(wm8904_exit); 2671 2672 MODULE_DESCRIPTION("ASoC WM8904 driver"); 2673 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2674 MODULE_LICENSE("GPL"); 2675