1 /* 2 * wm8904.c -- WM8904 ALSA SoC Audio driver 3 * 4 * Copyright 2009-12 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/wm8904.h> 30 31 #include "wm8904.h" 32 33 enum wm8904_type { 34 WM8904, 35 WM8912, 36 }; 37 38 #define WM8904_NUM_DCS_CHANNELS 4 39 40 #define WM8904_NUM_SUPPLIES 5 41 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 42 "DCVDD", 43 "DBVDD", 44 "AVDD", 45 "CPVDD", 46 "MICVDD", 47 }; 48 49 /* codec private data */ 50 struct wm8904_priv { 51 struct regmap *regmap; 52 struct clk *mclk; 53 54 enum wm8904_type devtype; 55 56 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 57 58 struct wm8904_pdata *pdata; 59 60 int deemph; 61 62 /* Platform provided DRC configuration */ 63 const char **drc_texts; 64 int drc_cfg; 65 struct soc_enum drc_enum; 66 67 /* Platform provided ReTune mobile configuration */ 68 int num_retune_mobile_texts; 69 const char **retune_mobile_texts; 70 int retune_mobile_cfg; 71 struct soc_enum retune_mobile_enum; 72 73 /* FLL setup */ 74 int fll_src; 75 int fll_fref; 76 int fll_fout; 77 78 /* Clocking configuration */ 79 unsigned int mclk_rate; 80 int sysclk_src; 81 unsigned int sysclk_rate; 82 83 int tdm_width; 84 int tdm_slots; 85 int bclk; 86 int fs; 87 88 /* DC servo configuration - cached offset values */ 89 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 90 }; 91 92 static const struct reg_default wm8904_reg_defaults[] = { 93 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 94 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 95 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 96 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */ 97 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 98 { 9, 0x9696 }, /* R9 - mic Filter Control */ 99 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 100 { 12, 0x0000 }, /* R12 - Power Management 0 */ 101 { 14, 0x0000 }, /* R14 - Power Management 2 */ 102 { 15, 0x0000 }, /* R15 - Power Management 3 */ 103 { 18, 0x0000 }, /* R18 - Power Management 6 */ 104 { 20, 0x945E }, /* R20 - Clock Rates 0 */ 105 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */ 106 { 22, 0x0006 }, /* R22 - Clock Rates 2 */ 107 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 108 { 25, 0x000A }, /* R25 - Audio Interface 1 */ 109 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */ 110 { 27, 0x0040 }, /* R27 - Audio Interface 3 */ 111 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 112 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 113 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 114 { 33, 0x0008 }, /* R33 - DAC Digital 1 */ 115 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 116 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 117 { 38, 0x0010 }, /* R38 - ADC Digital 0 */ 118 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */ 119 { 40, 0x01AF }, /* R40 - DRC 0 */ 120 { 41, 0x3248 }, /* R41 - DRC 1 */ 121 { 42, 0x0000 }, /* R42 - DRC 2 */ 122 { 43, 0x0000 }, /* R43 - DRC 3 */ 123 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 124 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 125 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 126 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 127 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 128 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 129 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 130 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 131 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */ 132 { 67, 0x0000 }, /* R67 - DC Servo 0 */ 133 { 69, 0xAAAA }, /* R69 - DC Servo 2 */ 134 { 71, 0xAAAA }, /* R71 - DC Servo 4 */ 135 { 72, 0xAAAA }, /* R72 - DC Servo 5 */ 136 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 137 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 138 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 139 { 104, 0x0004 }, /* R104 - Class W 0 */ 140 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 141 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 142 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 143 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 144 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 145 { 116, 0x0000 }, /* R116 - FLL Control 1 */ 146 { 117, 0x0007 }, /* R117 - FLL Control 2 */ 147 { 118, 0x0000 }, /* R118 - FLL Control 3 */ 148 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */ 149 { 120, 0x0004 }, /* R120 - FLL Control 5 */ 150 { 121, 0x0014 }, /* R121 - GPIO Control 1 */ 151 { 122, 0x0010 }, /* R122 - GPIO Control 2 */ 152 { 123, 0x0010 }, /* R123 - GPIO Control 3 */ 153 { 124, 0x0000 }, /* R124 - GPIO Control 4 */ 154 { 126, 0x0000 }, /* R126 - Digital Pulls */ 155 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */ 156 { 129, 0x0000 }, /* R129 - Interrupt Polarity */ 157 { 130, 0x0000 }, /* R130 - Interrupt Debounce */ 158 { 134, 0x0000 }, /* R134 - EQ1 */ 159 { 135, 0x000C }, /* R135 - EQ2 */ 160 { 136, 0x000C }, /* R136 - EQ3 */ 161 { 137, 0x000C }, /* R137 - EQ4 */ 162 { 138, 0x000C }, /* R138 - EQ5 */ 163 { 139, 0x000C }, /* R139 - EQ6 */ 164 { 140, 0x0FCA }, /* R140 - EQ7 */ 165 { 141, 0x0400 }, /* R141 - EQ8 */ 166 { 142, 0x00D8 }, /* R142 - EQ9 */ 167 { 143, 0x1EB5 }, /* R143 - EQ10 */ 168 { 144, 0xF145 }, /* R144 - EQ11 */ 169 { 145, 0x0B75 }, /* R145 - EQ12 */ 170 { 146, 0x01C5 }, /* R146 - EQ13 */ 171 { 147, 0x1C58 }, /* R147 - EQ14 */ 172 { 148, 0xF373 }, /* R148 - EQ15 */ 173 { 149, 0x0A54 }, /* R149 - EQ16 */ 174 { 150, 0x0558 }, /* R150 - EQ17 */ 175 { 151, 0x168E }, /* R151 - EQ18 */ 176 { 152, 0xF829 }, /* R152 - EQ19 */ 177 { 153, 0x07AD }, /* R153 - EQ20 */ 178 { 154, 0x1103 }, /* R154 - EQ21 */ 179 { 155, 0x0564 }, /* R155 - EQ22 */ 180 { 156, 0x0559 }, /* R156 - EQ23 */ 181 { 157, 0x4000 }, /* R157 - EQ24 */ 182 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */ 183 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */ 184 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */ 185 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */ 186 }; 187 188 static bool wm8904_volatile_register(struct device *dev, unsigned int reg) 189 { 190 switch (reg) { 191 case WM8904_SW_RESET_AND_ID: 192 case WM8904_REVISION: 193 case WM8904_DC_SERVO_1: 194 case WM8904_DC_SERVO_6: 195 case WM8904_DC_SERVO_7: 196 case WM8904_DC_SERVO_8: 197 case WM8904_DC_SERVO_9: 198 case WM8904_DC_SERVO_READBACK_0: 199 case WM8904_INTERRUPT_STATUS: 200 return true; 201 default: 202 return false; 203 } 204 } 205 206 static bool wm8904_readable_register(struct device *dev, unsigned int reg) 207 { 208 switch (reg) { 209 case WM8904_SW_RESET_AND_ID: 210 case WM8904_REVISION: 211 case WM8904_BIAS_CONTROL_0: 212 case WM8904_VMID_CONTROL_0: 213 case WM8904_MIC_BIAS_CONTROL_0: 214 case WM8904_MIC_BIAS_CONTROL_1: 215 case WM8904_ANALOGUE_DAC_0: 216 case WM8904_MIC_FILTER_CONTROL: 217 case WM8904_ANALOGUE_ADC_0: 218 case WM8904_POWER_MANAGEMENT_0: 219 case WM8904_POWER_MANAGEMENT_2: 220 case WM8904_POWER_MANAGEMENT_3: 221 case WM8904_POWER_MANAGEMENT_6: 222 case WM8904_CLOCK_RATES_0: 223 case WM8904_CLOCK_RATES_1: 224 case WM8904_CLOCK_RATES_2: 225 case WM8904_AUDIO_INTERFACE_0: 226 case WM8904_AUDIO_INTERFACE_1: 227 case WM8904_AUDIO_INTERFACE_2: 228 case WM8904_AUDIO_INTERFACE_3: 229 case WM8904_DAC_DIGITAL_VOLUME_LEFT: 230 case WM8904_DAC_DIGITAL_VOLUME_RIGHT: 231 case WM8904_DAC_DIGITAL_0: 232 case WM8904_DAC_DIGITAL_1: 233 case WM8904_ADC_DIGITAL_VOLUME_LEFT: 234 case WM8904_ADC_DIGITAL_VOLUME_RIGHT: 235 case WM8904_ADC_DIGITAL_0: 236 case WM8904_DIGITAL_MICROPHONE_0: 237 case WM8904_DRC_0: 238 case WM8904_DRC_1: 239 case WM8904_DRC_2: 240 case WM8904_DRC_3: 241 case WM8904_ANALOGUE_LEFT_INPUT_0: 242 case WM8904_ANALOGUE_RIGHT_INPUT_0: 243 case WM8904_ANALOGUE_LEFT_INPUT_1: 244 case WM8904_ANALOGUE_RIGHT_INPUT_1: 245 case WM8904_ANALOGUE_OUT1_LEFT: 246 case WM8904_ANALOGUE_OUT1_RIGHT: 247 case WM8904_ANALOGUE_OUT2_LEFT: 248 case WM8904_ANALOGUE_OUT2_RIGHT: 249 case WM8904_ANALOGUE_OUT12_ZC: 250 case WM8904_DC_SERVO_0: 251 case WM8904_DC_SERVO_1: 252 case WM8904_DC_SERVO_2: 253 case WM8904_DC_SERVO_4: 254 case WM8904_DC_SERVO_5: 255 case WM8904_DC_SERVO_6: 256 case WM8904_DC_SERVO_7: 257 case WM8904_DC_SERVO_8: 258 case WM8904_DC_SERVO_9: 259 case WM8904_DC_SERVO_READBACK_0: 260 case WM8904_ANALOGUE_HP_0: 261 case WM8904_ANALOGUE_LINEOUT_0: 262 case WM8904_CHARGE_PUMP_0: 263 case WM8904_CLASS_W_0: 264 case WM8904_WRITE_SEQUENCER_0: 265 case WM8904_WRITE_SEQUENCER_1: 266 case WM8904_WRITE_SEQUENCER_2: 267 case WM8904_WRITE_SEQUENCER_3: 268 case WM8904_WRITE_SEQUENCER_4: 269 case WM8904_FLL_CONTROL_1: 270 case WM8904_FLL_CONTROL_2: 271 case WM8904_FLL_CONTROL_3: 272 case WM8904_FLL_CONTROL_4: 273 case WM8904_FLL_CONTROL_5: 274 case WM8904_GPIO_CONTROL_1: 275 case WM8904_GPIO_CONTROL_2: 276 case WM8904_GPIO_CONTROL_3: 277 case WM8904_GPIO_CONTROL_4: 278 case WM8904_DIGITAL_PULLS: 279 case WM8904_INTERRUPT_STATUS: 280 case WM8904_INTERRUPT_STATUS_MASK: 281 case WM8904_INTERRUPT_POLARITY: 282 case WM8904_INTERRUPT_DEBOUNCE: 283 case WM8904_EQ1: 284 case WM8904_EQ2: 285 case WM8904_EQ3: 286 case WM8904_EQ4: 287 case WM8904_EQ5: 288 case WM8904_EQ6: 289 case WM8904_EQ7: 290 case WM8904_EQ8: 291 case WM8904_EQ9: 292 case WM8904_EQ10: 293 case WM8904_EQ11: 294 case WM8904_EQ12: 295 case WM8904_EQ13: 296 case WM8904_EQ14: 297 case WM8904_EQ15: 298 case WM8904_EQ16: 299 case WM8904_EQ17: 300 case WM8904_EQ18: 301 case WM8904_EQ19: 302 case WM8904_EQ20: 303 case WM8904_EQ21: 304 case WM8904_EQ22: 305 case WM8904_EQ23: 306 case WM8904_EQ24: 307 case WM8904_CONTROL_INTERFACE_TEST_1: 308 case WM8904_ADC_TEST_0: 309 case WM8904_ANALOGUE_OUTPUT_BIAS_0: 310 case WM8904_FLL_NCO_TEST_0: 311 case WM8904_FLL_NCO_TEST_1: 312 return true; 313 default: 314 return false; 315 } 316 } 317 318 static int wm8904_configure_clocking(struct snd_soc_component *component) 319 { 320 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 321 unsigned int clock0, clock2, rate; 322 323 /* Gate the clock while we're updating to avoid misclocking */ 324 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2); 325 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 326 WM8904_SYSCLK_SRC, 0); 327 328 /* This should be done on init() for bypass paths */ 329 switch (wm8904->sysclk_src) { 330 case WM8904_CLK_MCLK: 331 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 332 333 clock2 &= ~WM8904_SYSCLK_SRC; 334 rate = wm8904->mclk_rate; 335 336 /* Ensure the FLL is stopped */ 337 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 338 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 339 break; 340 341 case WM8904_CLK_FLL: 342 dev_dbg(component->dev, "Using %dHz FLL clock\n", 343 wm8904->fll_fout); 344 345 clock2 |= WM8904_SYSCLK_SRC; 346 rate = wm8904->fll_fout; 347 break; 348 349 default: 350 dev_err(component->dev, "System clock not configured\n"); 351 return -EINVAL; 352 } 353 354 /* SYSCLK shouldn't be over 13.5MHz */ 355 if (rate > 13500000) { 356 clock0 = WM8904_MCLK_DIV; 357 wm8904->sysclk_rate = rate / 2; 358 } else { 359 clock0 = 0; 360 wm8904->sysclk_rate = rate; 361 } 362 363 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 364 clock0); 365 366 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 367 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 368 369 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 370 371 return 0; 372 } 373 374 static void wm8904_set_drc(struct snd_soc_component *component) 375 { 376 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 377 struct wm8904_pdata *pdata = wm8904->pdata; 378 int save, i; 379 380 /* Save any enables; the configuration should clear them. */ 381 save = snd_soc_component_read32(component, WM8904_DRC_0); 382 383 for (i = 0; i < WM8904_DRC_REGS; i++) 384 snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff, 385 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 386 387 /* Reenable the DRC */ 388 snd_soc_component_update_bits(component, WM8904_DRC_0, 389 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 390 } 391 392 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 393 struct snd_ctl_elem_value *ucontrol) 394 { 395 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 396 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 397 struct wm8904_pdata *pdata = wm8904->pdata; 398 int value = ucontrol->value.enumerated.item[0]; 399 400 if (value >= pdata->num_drc_cfgs) 401 return -EINVAL; 402 403 wm8904->drc_cfg = value; 404 405 wm8904_set_drc(component); 406 407 return 0; 408 } 409 410 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 411 struct snd_ctl_elem_value *ucontrol) 412 { 413 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 414 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 415 416 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 417 418 return 0; 419 } 420 421 static void wm8904_set_retune_mobile(struct snd_soc_component *component) 422 { 423 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 424 struct wm8904_pdata *pdata = wm8904->pdata; 425 int best, best_val, save, i, cfg; 426 427 if (!pdata || !wm8904->num_retune_mobile_texts) 428 return; 429 430 /* Find the version of the currently selected configuration 431 * with the nearest sample rate. */ 432 cfg = wm8904->retune_mobile_cfg; 433 best = 0; 434 best_val = INT_MAX; 435 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 436 if (strcmp(pdata->retune_mobile_cfgs[i].name, 437 wm8904->retune_mobile_texts[cfg]) == 0 && 438 abs(pdata->retune_mobile_cfgs[i].rate 439 - wm8904->fs) < best_val) { 440 best = i; 441 best_val = abs(pdata->retune_mobile_cfgs[i].rate 442 - wm8904->fs); 443 } 444 } 445 446 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 447 pdata->retune_mobile_cfgs[best].name, 448 pdata->retune_mobile_cfgs[best].rate, 449 wm8904->fs); 450 451 /* The EQ will be disabled while reconfiguring it, remember the 452 * current configuration. 453 */ 454 save = snd_soc_component_read32(component, WM8904_EQ1); 455 456 for (i = 0; i < WM8904_EQ_REGS; i++) 457 snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff, 458 pdata->retune_mobile_cfgs[best].regs[i]); 459 460 snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save); 461 } 462 463 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 464 struct snd_ctl_elem_value *ucontrol) 465 { 466 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 467 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 468 struct wm8904_pdata *pdata = wm8904->pdata; 469 int value = ucontrol->value.enumerated.item[0]; 470 471 if (value >= pdata->num_retune_mobile_cfgs) 472 return -EINVAL; 473 474 wm8904->retune_mobile_cfg = value; 475 476 wm8904_set_retune_mobile(component); 477 478 return 0; 479 } 480 481 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 482 struct snd_ctl_elem_value *ucontrol) 483 { 484 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 485 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 486 487 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 488 489 return 0; 490 } 491 492 static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 493 494 static int wm8904_set_deemph(struct snd_soc_component *component) 495 { 496 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 497 int val, i, best; 498 499 /* If we're using deemphasis select the nearest available sample 500 * rate. 501 */ 502 if (wm8904->deemph) { 503 best = 1; 504 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 505 if (abs(deemph_settings[i] - wm8904->fs) < 506 abs(deemph_settings[best] - wm8904->fs)) 507 best = i; 508 } 509 510 val = best << WM8904_DEEMPH_SHIFT; 511 } else { 512 val = 0; 513 } 514 515 dev_dbg(component->dev, "Set deemphasis %d\n", val); 516 517 return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 518 WM8904_DEEMPH_MASK, val); 519 } 520 521 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 522 struct snd_ctl_elem_value *ucontrol) 523 { 524 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 525 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 526 527 ucontrol->value.integer.value[0] = wm8904->deemph; 528 return 0; 529 } 530 531 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 532 struct snd_ctl_elem_value *ucontrol) 533 { 534 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 535 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 536 unsigned int deemph = ucontrol->value.integer.value[0]; 537 538 if (deemph > 1) 539 return -EINVAL; 540 541 wm8904->deemph = deemph; 542 543 return wm8904_set_deemph(component); 544 } 545 546 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 547 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 548 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 549 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 550 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 551 552 static const char *input_mode_text[] = { 553 "Single-Ended", "Differential Line", "Differential Mic" 554 }; 555 556 static SOC_ENUM_SINGLE_DECL(lin_mode, 557 WM8904_ANALOGUE_LEFT_INPUT_1, 0, 558 input_mode_text); 559 560 static SOC_ENUM_SINGLE_DECL(rin_mode, 561 WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 562 input_mode_text); 563 564 static const char *hpf_mode_text[] = { 565 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 566 }; 567 568 static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5, 569 hpf_mode_text); 570 571 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, 572 struct snd_ctl_elem_value *ucontrol) 573 { 574 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 575 unsigned int val; 576 int ret; 577 578 ret = snd_soc_put_volsw(kcontrol, ucontrol); 579 if (ret < 0) 580 return ret; 581 582 if (ucontrol->value.integer.value[0]) 583 val = 0; 584 else 585 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; 586 587 snd_soc_component_update_bits(component, WM8904_ADC_TEST_0, 588 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5, 589 val); 590 591 return ret; 592 } 593 594 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 595 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 596 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 597 598 SOC_ENUM("Left Capture Mode", lin_mode), 599 SOC_ENUM("Right Capture Mode", rin_mode), 600 601 /* No TLV since it depends on mode */ 602 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 603 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 604 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 605 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), 606 607 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 608 SOC_ENUM("High Pass Filter Mode", hpf_mode), 609 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0, 610 snd_soc_get_volsw, wm8904_adc_osr_put), 611 }; 612 613 static const char *drc_path_text[] = { 614 "ADC", "DAC" 615 }; 616 617 static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text); 618 619 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 620 SOC_SINGLE_TLV("Digital Playback Boost Volume", 621 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 622 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 623 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 624 625 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 626 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 627 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 628 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 629 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 630 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 631 632 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 633 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 634 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 635 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 636 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 637 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 638 639 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 640 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 641 SOC_ENUM("DRC Path", drc_path), 642 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 643 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 644 wm8904_get_deemph, wm8904_put_deemph), 645 }; 646 647 static const struct snd_kcontrol_new wm8904_snd_controls[] = { 648 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 649 sidetone_tlv), 650 }; 651 652 static const struct snd_kcontrol_new wm8904_eq_controls[] = { 653 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 654 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 655 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 656 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 657 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 658 }; 659 660 static int cp_event(struct snd_soc_dapm_widget *w, 661 struct snd_kcontrol *kcontrol, int event) 662 { 663 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU)) 664 return -EINVAL; 665 666 /* Maximum startup time */ 667 udelay(500); 668 669 return 0; 670 } 671 672 static int sysclk_event(struct snd_soc_dapm_widget *w, 673 struct snd_kcontrol *kcontrol, int event) 674 { 675 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 676 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 677 678 switch (event) { 679 case SND_SOC_DAPM_PRE_PMU: 680 /* If we're using the FLL then we only start it when 681 * required; we assume that the configuration has been 682 * done previously and all we need to do is kick it 683 * off. 684 */ 685 switch (wm8904->sysclk_src) { 686 case WM8904_CLK_FLL: 687 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 688 WM8904_FLL_OSC_ENA, 689 WM8904_FLL_OSC_ENA); 690 691 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 692 WM8904_FLL_ENA, 693 WM8904_FLL_ENA); 694 break; 695 696 default: 697 break; 698 } 699 break; 700 701 case SND_SOC_DAPM_POST_PMD: 702 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 703 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 704 break; 705 } 706 707 return 0; 708 } 709 710 static int out_pga_event(struct snd_soc_dapm_widget *w, 711 struct snd_kcontrol *kcontrol, int event) 712 { 713 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 714 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 715 int reg, val; 716 int dcs_mask; 717 int dcs_l, dcs_r; 718 int dcs_l_reg, dcs_r_reg; 719 int timeout; 720 int pwr_reg; 721 722 /* This code is shared between HP and LINEOUT; we do all our 723 * power management in stereo pairs to avoid latency issues so 724 * we reuse shift to identify which rather than strcmp() the 725 * name. */ 726 reg = w->shift; 727 728 switch (reg) { 729 case WM8904_ANALOGUE_HP_0: 730 pwr_reg = WM8904_POWER_MANAGEMENT_2; 731 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 732 dcs_r_reg = WM8904_DC_SERVO_8; 733 dcs_l_reg = WM8904_DC_SERVO_9; 734 dcs_l = 0; 735 dcs_r = 1; 736 break; 737 case WM8904_ANALOGUE_LINEOUT_0: 738 pwr_reg = WM8904_POWER_MANAGEMENT_3; 739 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 740 dcs_r_reg = WM8904_DC_SERVO_6; 741 dcs_l_reg = WM8904_DC_SERVO_7; 742 dcs_l = 2; 743 dcs_r = 3; 744 break; 745 default: 746 WARN(1, "Invalid reg %d\n", reg); 747 return -EINVAL; 748 } 749 750 switch (event) { 751 case SND_SOC_DAPM_PRE_PMU: 752 /* Power on the PGAs */ 753 snd_soc_component_update_bits(component, pwr_reg, 754 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 755 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 756 757 /* Power on the amplifier */ 758 snd_soc_component_update_bits(component, reg, 759 WM8904_HPL_ENA | WM8904_HPR_ENA, 760 WM8904_HPL_ENA | WM8904_HPR_ENA); 761 762 763 /* Enable the first stage */ 764 snd_soc_component_update_bits(component, reg, 765 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 766 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 767 768 /* Power up the DC servo */ 769 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 770 dcs_mask, dcs_mask); 771 772 /* Either calibrate the DC servo or restore cached state 773 * if we have that. 774 */ 775 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 776 dev_dbg(component->dev, "Restoring DC servo state\n"); 777 778 snd_soc_component_write(component, dcs_l_reg, 779 wm8904->dcs_state[dcs_l]); 780 snd_soc_component_write(component, dcs_r_reg, 781 wm8904->dcs_state[dcs_r]); 782 783 snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask); 784 785 timeout = 20; 786 } else { 787 dev_dbg(component->dev, "Calibrating DC servo\n"); 788 789 snd_soc_component_write(component, WM8904_DC_SERVO_1, 790 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 791 792 timeout = 500; 793 } 794 795 /* Wait for DC servo to complete */ 796 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 797 do { 798 val = snd_soc_component_read32(component, WM8904_DC_SERVO_READBACK_0); 799 if ((val & dcs_mask) == dcs_mask) 800 break; 801 802 msleep(1); 803 } while (--timeout); 804 805 if ((val & dcs_mask) != dcs_mask) 806 dev_warn(component->dev, "DC servo timed out\n"); 807 else 808 dev_dbg(component->dev, "DC servo ready\n"); 809 810 /* Enable the output stage */ 811 snd_soc_component_update_bits(component, reg, 812 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 813 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 814 break; 815 816 case SND_SOC_DAPM_POST_PMU: 817 /* Unshort the output itself */ 818 snd_soc_component_update_bits(component, reg, 819 WM8904_HPL_RMV_SHORT | 820 WM8904_HPR_RMV_SHORT, 821 WM8904_HPL_RMV_SHORT | 822 WM8904_HPR_RMV_SHORT); 823 824 break; 825 826 case SND_SOC_DAPM_PRE_PMD: 827 /* Short the output */ 828 snd_soc_component_update_bits(component, reg, 829 WM8904_HPL_RMV_SHORT | 830 WM8904_HPR_RMV_SHORT, 0); 831 break; 832 833 case SND_SOC_DAPM_POST_PMD: 834 /* Cache the DC servo configuration; this will be 835 * invalidated if we change the configuration. */ 836 wm8904->dcs_state[dcs_l] = snd_soc_component_read32(component, dcs_l_reg); 837 wm8904->dcs_state[dcs_r] = snd_soc_component_read32(component, dcs_r_reg); 838 839 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 840 dcs_mask, 0); 841 842 /* Disable the amplifier input and output stages */ 843 snd_soc_component_update_bits(component, reg, 844 WM8904_HPL_ENA | WM8904_HPR_ENA | 845 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 846 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 847 0); 848 849 /* PGAs too */ 850 snd_soc_component_update_bits(component, pwr_reg, 851 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 852 0); 853 break; 854 } 855 856 return 0; 857 } 858 859 static const char *lin_text[] = { 860 "IN1L", "IN2L", "IN3L" 861 }; 862 863 static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2, 864 lin_text); 865 866 static const struct snd_kcontrol_new lin_mux = 867 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 868 869 static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4, 870 lin_text); 871 872 static const struct snd_kcontrol_new lin_inv_mux = 873 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 874 875 static const char *rin_text[] = { 876 "IN1R", "IN2R", "IN3R" 877 }; 878 879 static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 880 rin_text); 881 882 static const struct snd_kcontrol_new rin_mux = 883 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 884 885 static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 886 rin_text); 887 888 static const struct snd_kcontrol_new rin_inv_mux = 889 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 890 891 static const char *aif_text[] = { 892 "Left", "Right" 893 }; 894 895 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7, 896 aif_text); 897 898 static const struct snd_kcontrol_new aifoutl_mux = 899 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 900 901 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6, 902 aif_text); 903 904 static const struct snd_kcontrol_new aifoutr_mux = 905 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 906 907 static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5, 908 aif_text); 909 910 static const struct snd_kcontrol_new aifinl_mux = 911 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 912 913 static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4, 914 aif_text); 915 916 static const struct snd_kcontrol_new aifinr_mux = 917 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 918 919 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 920 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 921 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 922 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 923 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 924 }; 925 926 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 927 SND_SOC_DAPM_INPUT("IN1L"), 928 SND_SOC_DAPM_INPUT("IN1R"), 929 SND_SOC_DAPM_INPUT("IN2L"), 930 SND_SOC_DAPM_INPUT("IN2R"), 931 SND_SOC_DAPM_INPUT("IN3L"), 932 SND_SOC_DAPM_INPUT("IN3R"), 933 934 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 935 936 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 937 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 938 &lin_inv_mux), 939 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 940 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 941 &rin_inv_mux), 942 943 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 944 NULL, 0), 945 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 946 NULL, 0), 947 948 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 949 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 950 951 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 952 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 953 954 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 955 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 956 }; 957 958 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 959 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 960 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 961 962 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 963 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 964 965 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 966 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 967 968 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 969 SND_SOC_DAPM_POST_PMU), 970 971 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 972 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 973 974 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 975 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 976 977 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 978 0, NULL, 0, out_pga_event, 979 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 980 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 981 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 982 0, NULL, 0, out_pga_event, 983 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 984 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 985 986 SND_SOC_DAPM_OUTPUT("HPOUTL"), 987 SND_SOC_DAPM_OUTPUT("HPOUTR"), 988 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 989 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 990 }; 991 992 static const char *out_mux_text[] = { 993 "DAC", "Bypass" 994 }; 995 996 static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3, 997 out_mux_text); 998 999 static const struct snd_kcontrol_new hpl_mux = 1000 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1001 1002 static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2, 1003 out_mux_text); 1004 1005 static const struct snd_kcontrol_new hpr_mux = 1006 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1007 1008 static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1, 1009 out_mux_text); 1010 1011 static const struct snd_kcontrol_new linel_mux = 1012 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1013 1014 static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0, 1015 out_mux_text); 1016 1017 static const struct snd_kcontrol_new liner_mux = 1018 SOC_DAPM_ENUM("LINER Mux", liner_enum); 1019 1020 static const char *sidetone_text[] = { 1021 "None", "Left", "Right" 1022 }; 1023 1024 static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2, 1025 sidetone_text); 1026 1027 static const struct snd_kcontrol_new dacl_sidetone_mux = 1028 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1029 1030 static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0, 1031 sidetone_text); 1032 1033 static const struct snd_kcontrol_new dacr_sidetone_mux = 1034 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1035 1036 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1037 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1038 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1039 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1040 1041 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1042 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1043 1044 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1045 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1046 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1047 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1048 }; 1049 1050 static const struct snd_soc_dapm_route core_intercon[] = { 1051 { "CLK_DSP", NULL, "SYSCLK" }, 1052 { "TOCLK", NULL, "SYSCLK" }, 1053 }; 1054 1055 static const struct snd_soc_dapm_route adc_intercon[] = { 1056 { "Left Capture Mux", "IN1L", "IN1L" }, 1057 { "Left Capture Mux", "IN2L", "IN2L" }, 1058 { "Left Capture Mux", "IN3L", "IN3L" }, 1059 1060 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1061 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1062 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1063 1064 { "Right Capture Mux", "IN1R", "IN1R" }, 1065 { "Right Capture Mux", "IN2R", "IN2R" }, 1066 { "Right Capture Mux", "IN3R", "IN3R" }, 1067 1068 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1069 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1070 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1071 1072 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1073 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1074 1075 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1076 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1077 1078 { "AIFOUTL Mux", "Left", "ADCL" }, 1079 { "AIFOUTL Mux", "Right", "ADCR" }, 1080 { "AIFOUTR Mux", "Left", "ADCL" }, 1081 { "AIFOUTR Mux", "Right", "ADCR" }, 1082 1083 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 1084 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 1085 1086 { "ADCL", NULL, "CLK_DSP" }, 1087 { "ADCL", NULL, "Left Capture PGA" }, 1088 1089 { "ADCR", NULL, "CLK_DSP" }, 1090 { "ADCR", NULL, "Right Capture PGA" }, 1091 }; 1092 1093 static const struct snd_soc_dapm_route dac_intercon[] = { 1094 { "DACL Mux", "Left", "AIFINL" }, 1095 { "DACL Mux", "Right", "AIFINR" }, 1096 1097 { "DACR Mux", "Left", "AIFINL" }, 1098 { "DACR Mux", "Right", "AIFINR" }, 1099 1100 { "DACL", NULL, "DACL Mux" }, 1101 { "DACL", NULL, "CLK_DSP" }, 1102 1103 { "DACR", NULL, "DACR Mux" }, 1104 { "DACR", NULL, "CLK_DSP" }, 1105 1106 { "Charge pump", NULL, "SYSCLK" }, 1107 1108 { "Headphone Output", NULL, "HPL PGA" }, 1109 { "Headphone Output", NULL, "HPR PGA" }, 1110 { "Headphone Output", NULL, "Charge pump" }, 1111 { "Headphone Output", NULL, "TOCLK" }, 1112 1113 { "Line Output", NULL, "LINEL PGA" }, 1114 { "Line Output", NULL, "LINER PGA" }, 1115 { "Line Output", NULL, "Charge pump" }, 1116 { "Line Output", NULL, "TOCLK" }, 1117 1118 { "HPOUTL", NULL, "Headphone Output" }, 1119 { "HPOUTR", NULL, "Headphone Output" }, 1120 1121 { "LINEOUTL", NULL, "Line Output" }, 1122 { "LINEOUTR", NULL, "Line Output" }, 1123 }; 1124 1125 static const struct snd_soc_dapm_route wm8904_intercon[] = { 1126 { "Left Sidetone", "Left", "ADCL" }, 1127 { "Left Sidetone", "Right", "ADCR" }, 1128 { "DACL", NULL, "Left Sidetone" }, 1129 1130 { "Right Sidetone", "Left", "ADCL" }, 1131 { "Right Sidetone", "Right", "ADCR" }, 1132 { "DACR", NULL, "Right Sidetone" }, 1133 1134 { "Left Bypass", NULL, "Class G" }, 1135 { "Left Bypass", NULL, "Left Capture PGA" }, 1136 1137 { "Right Bypass", NULL, "Class G" }, 1138 { "Right Bypass", NULL, "Right Capture PGA" }, 1139 1140 { "HPL Mux", "DAC", "DACL" }, 1141 { "HPL Mux", "Bypass", "Left Bypass" }, 1142 1143 { "HPR Mux", "DAC", "DACR" }, 1144 { "HPR Mux", "Bypass", "Right Bypass" }, 1145 1146 { "LINEL Mux", "DAC", "DACL" }, 1147 { "LINEL Mux", "Bypass", "Left Bypass" }, 1148 1149 { "LINER Mux", "DAC", "DACR" }, 1150 { "LINER Mux", "Bypass", "Right Bypass" }, 1151 1152 { "HPL PGA", NULL, "HPL Mux" }, 1153 { "HPR PGA", NULL, "HPR Mux" }, 1154 1155 { "LINEL PGA", NULL, "LINEL Mux" }, 1156 { "LINER PGA", NULL, "LINER Mux" }, 1157 }; 1158 1159 static const struct snd_soc_dapm_route wm8912_intercon[] = { 1160 { "HPL PGA", NULL, "DACL" }, 1161 { "HPR PGA", NULL, "DACR" }, 1162 1163 { "LINEL PGA", NULL, "DACL" }, 1164 { "LINER PGA", NULL, "DACR" }, 1165 }; 1166 1167 static int wm8904_add_widgets(struct snd_soc_component *component) 1168 { 1169 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1170 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1171 1172 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, 1173 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1174 snd_soc_dapm_add_routes(dapm, core_intercon, 1175 ARRAY_SIZE(core_intercon)); 1176 1177 switch (wm8904->devtype) { 1178 case WM8904: 1179 snd_soc_add_component_controls(component, wm8904_adc_snd_controls, 1180 ARRAY_SIZE(wm8904_adc_snd_controls)); 1181 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1182 ARRAY_SIZE(wm8904_dac_snd_controls)); 1183 snd_soc_add_component_controls(component, wm8904_snd_controls, 1184 ARRAY_SIZE(wm8904_snd_controls)); 1185 1186 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, 1187 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1188 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1189 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1190 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, 1191 ARRAY_SIZE(wm8904_dapm_widgets)); 1192 1193 snd_soc_dapm_add_routes(dapm, adc_intercon, 1194 ARRAY_SIZE(adc_intercon)); 1195 snd_soc_dapm_add_routes(dapm, dac_intercon, 1196 ARRAY_SIZE(dac_intercon)); 1197 snd_soc_dapm_add_routes(dapm, wm8904_intercon, 1198 ARRAY_SIZE(wm8904_intercon)); 1199 break; 1200 1201 case WM8912: 1202 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1203 ARRAY_SIZE(wm8904_dac_snd_controls)); 1204 1205 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1206 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1207 1208 snd_soc_dapm_add_routes(dapm, dac_intercon, 1209 ARRAY_SIZE(dac_intercon)); 1210 snd_soc_dapm_add_routes(dapm, wm8912_intercon, 1211 ARRAY_SIZE(wm8912_intercon)); 1212 break; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static struct { 1219 int ratio; 1220 unsigned int clk_sys_rate; 1221 } clk_sys_rates[] = { 1222 { 64, 0 }, 1223 { 128, 1 }, 1224 { 192, 2 }, 1225 { 256, 3 }, 1226 { 384, 4 }, 1227 { 512, 5 }, 1228 { 786, 6 }, 1229 { 1024, 7 }, 1230 { 1408, 8 }, 1231 { 1536, 9 }, 1232 }; 1233 1234 static struct { 1235 int rate; 1236 int sample_rate; 1237 } sample_rates[] = { 1238 { 8000, 0 }, 1239 { 11025, 1 }, 1240 { 12000, 1 }, 1241 { 16000, 2 }, 1242 { 22050, 3 }, 1243 { 24000, 3 }, 1244 { 32000, 4 }, 1245 { 44100, 5 }, 1246 { 48000, 5 }, 1247 }; 1248 1249 static struct { 1250 int div; /* *10 due to .5s */ 1251 int bclk_div; 1252 } bclk_divs[] = { 1253 { 10, 0 }, 1254 { 15, 1 }, 1255 { 20, 2 }, 1256 { 30, 3 }, 1257 { 40, 4 }, 1258 { 50, 5 }, 1259 { 55, 6 }, 1260 { 60, 7 }, 1261 { 80, 8 }, 1262 { 100, 9 }, 1263 { 110, 10 }, 1264 { 120, 11 }, 1265 { 160, 12 }, 1266 { 200, 13 }, 1267 { 220, 14 }, 1268 { 240, 16 }, 1269 { 200, 17 }, 1270 { 320, 18 }, 1271 { 440, 19 }, 1272 { 480, 20 }, 1273 }; 1274 1275 1276 static int wm8904_hw_params(struct snd_pcm_substream *substream, 1277 struct snd_pcm_hw_params *params, 1278 struct snd_soc_dai *dai) 1279 { 1280 struct snd_soc_component *component = dai->component; 1281 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1282 int ret, i, best, best_val, cur_val; 1283 unsigned int aif1 = 0; 1284 unsigned int aif2 = 0; 1285 unsigned int aif3 = 0; 1286 unsigned int clock1 = 0; 1287 unsigned int dac_digital1 = 0; 1288 1289 /* What BCLK do we need? */ 1290 wm8904->fs = params_rate(params); 1291 if (wm8904->tdm_slots) { 1292 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n", 1293 wm8904->tdm_slots, wm8904->tdm_width); 1294 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1295 wm8904->tdm_width, 2, 1296 wm8904->tdm_slots); 1297 } else { 1298 wm8904->bclk = snd_soc_params_to_bclk(params); 1299 } 1300 1301 switch (params_width(params)) { 1302 case 16: 1303 break; 1304 case 20: 1305 aif1 |= 0x40; 1306 break; 1307 case 24: 1308 aif1 |= 0x80; 1309 break; 1310 case 32: 1311 aif1 |= 0xc0; 1312 break; 1313 default: 1314 return -EINVAL; 1315 } 1316 1317 1318 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1319 1320 ret = wm8904_configure_clocking(component); 1321 if (ret != 0) 1322 return ret; 1323 1324 /* Select nearest CLK_SYS_RATE */ 1325 best = 0; 1326 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1327 - wm8904->fs); 1328 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1329 cur_val = abs((wm8904->sysclk_rate / 1330 clk_sys_rates[i].ratio) - wm8904->fs); 1331 if (cur_val < best_val) { 1332 best = i; 1333 best_val = cur_val; 1334 } 1335 } 1336 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", 1337 clk_sys_rates[best].ratio); 1338 clock1 |= (clk_sys_rates[best].clk_sys_rate 1339 << WM8904_CLK_SYS_RATE_SHIFT); 1340 1341 /* SAMPLE_RATE */ 1342 best = 0; 1343 best_val = abs(wm8904->fs - sample_rates[0].rate); 1344 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1345 /* Closest match */ 1346 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1347 if (cur_val < best_val) { 1348 best = i; 1349 best_val = cur_val; 1350 } 1351 } 1352 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", 1353 sample_rates[best].rate); 1354 clock1 |= (sample_rates[best].sample_rate 1355 << WM8904_SAMPLE_RATE_SHIFT); 1356 1357 /* Enable sloping stopband filter for low sample rates */ 1358 if (wm8904->fs <= 24000) 1359 dac_digital1 |= WM8904_DAC_SB_FILT; 1360 1361 /* BCLK_DIV */ 1362 best = 0; 1363 best_val = INT_MAX; 1364 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1365 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1366 - wm8904->bclk; 1367 if (cur_val < 0) /* Table is sorted */ 1368 break; 1369 if (cur_val < best_val) { 1370 best = i; 1371 best_val = cur_val; 1372 } 1373 } 1374 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1375 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1376 bclk_divs[best].div, wm8904->bclk); 1377 aif2 |= bclk_divs[best].bclk_div; 1378 1379 /* LRCLK is a simple fraction of BCLK */ 1380 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1381 aif3 |= wm8904->bclk / wm8904->fs; 1382 1383 /* Apply the settings */ 1384 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 1385 WM8904_DAC_SB_FILT, dac_digital1); 1386 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1387 WM8904_AIF_WL_MASK, aif1); 1388 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2, 1389 WM8904_BCLK_DIV_MASK, aif2); 1390 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1391 WM8904_LRCLK_RATE_MASK, aif3); 1392 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1, 1393 WM8904_SAMPLE_RATE_MASK | 1394 WM8904_CLK_SYS_RATE_MASK, clock1); 1395 1396 /* Update filters for the new settings */ 1397 wm8904_set_retune_mobile(component); 1398 wm8904_set_deemph(component); 1399 1400 return 0; 1401 } 1402 1403 1404 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1405 unsigned int freq, int dir) 1406 { 1407 struct snd_soc_component *component = dai->component; 1408 struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); 1409 1410 switch (clk_id) { 1411 case WM8904_CLK_MCLK: 1412 priv->sysclk_src = clk_id; 1413 priv->mclk_rate = freq; 1414 break; 1415 1416 case WM8904_CLK_FLL: 1417 priv->sysclk_src = clk_id; 1418 break; 1419 1420 default: 1421 return -EINVAL; 1422 } 1423 1424 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1425 1426 wm8904_configure_clocking(component); 1427 1428 return 0; 1429 } 1430 1431 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1432 { 1433 struct snd_soc_component *component = dai->component; 1434 unsigned int aif1 = 0; 1435 unsigned int aif3 = 0; 1436 1437 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1438 case SND_SOC_DAIFMT_CBS_CFS: 1439 break; 1440 case SND_SOC_DAIFMT_CBS_CFM: 1441 aif3 |= WM8904_LRCLK_DIR; 1442 break; 1443 case SND_SOC_DAIFMT_CBM_CFS: 1444 aif1 |= WM8904_BCLK_DIR; 1445 break; 1446 case SND_SOC_DAIFMT_CBM_CFM: 1447 aif1 |= WM8904_BCLK_DIR; 1448 aif3 |= WM8904_LRCLK_DIR; 1449 break; 1450 default: 1451 return -EINVAL; 1452 } 1453 1454 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1455 case SND_SOC_DAIFMT_DSP_B: 1456 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV; 1457 /* fall through */ 1458 case SND_SOC_DAIFMT_DSP_A: 1459 aif1 |= 0x3; 1460 break; 1461 case SND_SOC_DAIFMT_I2S: 1462 aif1 |= 0x2; 1463 break; 1464 case SND_SOC_DAIFMT_RIGHT_J: 1465 break; 1466 case SND_SOC_DAIFMT_LEFT_J: 1467 aif1 |= 0x1; 1468 break; 1469 default: 1470 return -EINVAL; 1471 } 1472 1473 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1474 case SND_SOC_DAIFMT_DSP_A: 1475 case SND_SOC_DAIFMT_DSP_B: 1476 /* frame inversion not valid for DSP modes */ 1477 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1478 case SND_SOC_DAIFMT_NB_NF: 1479 break; 1480 case SND_SOC_DAIFMT_IB_NF: 1481 aif1 |= WM8904_AIF_BCLK_INV; 1482 break; 1483 default: 1484 return -EINVAL; 1485 } 1486 break; 1487 1488 case SND_SOC_DAIFMT_I2S: 1489 case SND_SOC_DAIFMT_RIGHT_J: 1490 case SND_SOC_DAIFMT_LEFT_J: 1491 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1492 case SND_SOC_DAIFMT_NB_NF: 1493 break; 1494 case SND_SOC_DAIFMT_IB_IF: 1495 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1496 break; 1497 case SND_SOC_DAIFMT_IB_NF: 1498 aif1 |= WM8904_AIF_BCLK_INV; 1499 break; 1500 case SND_SOC_DAIFMT_NB_IF: 1501 aif1 |= WM8904_AIF_LRCLK_INV; 1502 break; 1503 default: 1504 return -EINVAL; 1505 } 1506 break; 1507 default: 1508 return -EINVAL; 1509 } 1510 1511 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1512 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1513 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1514 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1515 WM8904_LRCLK_DIR, aif3); 1516 1517 return 0; 1518 } 1519 1520 1521 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1522 unsigned int rx_mask, int slots, int slot_width) 1523 { 1524 struct snd_soc_component *component = dai->component; 1525 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1526 int aif1 = 0; 1527 1528 /* Don't need to validate anything if we're turning off TDM */ 1529 if (slots == 0) 1530 goto out; 1531 1532 /* Note that we allow configurations we can't handle ourselves - 1533 * for example, we can generate clocks for slots 2 and up even if 1534 * we can't use those slots ourselves. 1535 */ 1536 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1537 1538 switch (rx_mask) { 1539 case 3: 1540 break; 1541 case 0xc: 1542 aif1 |= WM8904_AIFADC_TDM_CHAN; 1543 break; 1544 default: 1545 return -EINVAL; 1546 } 1547 1548 1549 switch (tx_mask) { 1550 case 3: 1551 break; 1552 case 0xc: 1553 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1554 break; 1555 default: 1556 return -EINVAL; 1557 } 1558 1559 out: 1560 wm8904->tdm_width = slot_width; 1561 wm8904->tdm_slots = slots / 2; 1562 1563 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1564 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1565 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1566 1567 return 0; 1568 } 1569 1570 struct _fll_div { 1571 u16 fll_fratio; 1572 u16 fll_outdiv; 1573 u16 fll_clk_ref_div; 1574 u16 n; 1575 u16 k; 1576 }; 1577 1578 /* The size in bits of the FLL divide multiplied by 10 1579 * to allow rounding later */ 1580 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1581 1582 static struct { 1583 unsigned int min; 1584 unsigned int max; 1585 u16 fll_fratio; 1586 int ratio; 1587 } fll_fratios[] = { 1588 { 0, 64000, 4, 16 }, 1589 { 64000, 128000, 3, 8 }, 1590 { 128000, 256000, 2, 4 }, 1591 { 256000, 1000000, 1, 2 }, 1592 { 1000000, 13500000, 0, 1 }, 1593 }; 1594 1595 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1596 unsigned int Fout) 1597 { 1598 u64 Kpart; 1599 unsigned int K, Ndiv, Nmod, target; 1600 unsigned int div; 1601 int i; 1602 1603 /* Fref must be <=13.5MHz */ 1604 div = 1; 1605 fll_div->fll_clk_ref_div = 0; 1606 while ((Fref / div) > 13500000) { 1607 div *= 2; 1608 fll_div->fll_clk_ref_div++; 1609 1610 if (div > 8) { 1611 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1612 Fref); 1613 return -EINVAL; 1614 } 1615 } 1616 1617 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1618 1619 /* Apply the division for our remaining calculations */ 1620 Fref /= div; 1621 1622 /* Fvco should be 90-100MHz; don't check the upper bound */ 1623 div = 4; 1624 while (Fout * div < 90000000) { 1625 div++; 1626 if (div > 64) { 1627 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1628 Fout); 1629 return -EINVAL; 1630 } 1631 } 1632 target = Fout * div; 1633 fll_div->fll_outdiv = div - 1; 1634 1635 pr_debug("Fvco=%dHz\n", target); 1636 1637 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 1638 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1639 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1640 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1641 target /= fll_fratios[i].ratio; 1642 break; 1643 } 1644 } 1645 if (i == ARRAY_SIZE(fll_fratios)) { 1646 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1647 return -EINVAL; 1648 } 1649 1650 /* Now, calculate N.K */ 1651 Ndiv = target / Fref; 1652 1653 fll_div->n = Ndiv; 1654 Nmod = target % Fref; 1655 pr_debug("Nmod=%d\n", Nmod); 1656 1657 /* Calculate fractional part - scale up so we can round. */ 1658 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1659 1660 do_div(Kpart, Fref); 1661 1662 K = Kpart & 0xFFFFFFFF; 1663 1664 if ((K % 10) >= 5) 1665 K += 5; 1666 1667 /* Move down to proper range now rounding is done */ 1668 fll_div->k = K / 10; 1669 1670 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1671 fll_div->n, fll_div->k, 1672 fll_div->fll_fratio, fll_div->fll_outdiv, 1673 fll_div->fll_clk_ref_div); 1674 1675 return 0; 1676 } 1677 1678 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1679 unsigned int Fref, unsigned int Fout) 1680 { 1681 struct snd_soc_component *component = dai->component; 1682 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1683 struct _fll_div fll_div; 1684 int ret, val; 1685 int clock2, fll1; 1686 1687 /* Any change? */ 1688 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1689 Fout == wm8904->fll_fout) 1690 return 0; 1691 1692 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2); 1693 1694 if (Fout == 0) { 1695 dev_dbg(component->dev, "FLL disabled\n"); 1696 1697 wm8904->fll_fref = 0; 1698 wm8904->fll_fout = 0; 1699 1700 /* Gate SYSCLK to avoid glitches */ 1701 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1702 WM8904_CLK_SYS_ENA, 0); 1703 1704 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1705 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1706 1707 goto out; 1708 } 1709 1710 /* Validate the FLL ID */ 1711 switch (source) { 1712 case WM8904_FLL_MCLK: 1713 case WM8904_FLL_LRCLK: 1714 case WM8904_FLL_BCLK: 1715 ret = fll_factors(&fll_div, Fref, Fout); 1716 if (ret != 0) 1717 return ret; 1718 break; 1719 1720 case WM8904_FLL_FREE_RUNNING: 1721 dev_dbg(component->dev, "Using free running FLL\n"); 1722 /* Force 12MHz and output/4 for now */ 1723 Fout = 12000000; 1724 Fref = 12000000; 1725 1726 memset(&fll_div, 0, sizeof(fll_div)); 1727 fll_div.fll_outdiv = 3; 1728 break; 1729 1730 default: 1731 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); 1732 return -EINVAL; 1733 } 1734 1735 /* Save current state then disable the FLL and SYSCLK to avoid 1736 * misclocking */ 1737 fll1 = snd_soc_component_read32(component, WM8904_FLL_CONTROL_1); 1738 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1739 WM8904_CLK_SYS_ENA, 0); 1740 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1741 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1742 1743 /* Unlock forced oscilator control to switch it on/off */ 1744 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1745 WM8904_USER_KEY, WM8904_USER_KEY); 1746 1747 if (fll_id == WM8904_FLL_FREE_RUNNING) { 1748 val = WM8904_FLL_FRC_NCO; 1749 } else { 1750 val = 0; 1751 } 1752 1753 snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 1754 val); 1755 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1756 WM8904_USER_KEY, 0); 1757 1758 switch (fll_id) { 1759 case WM8904_FLL_MCLK: 1760 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1761 WM8904_FLL_CLK_REF_SRC_MASK, 0); 1762 break; 1763 1764 case WM8904_FLL_LRCLK: 1765 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1766 WM8904_FLL_CLK_REF_SRC_MASK, 1); 1767 break; 1768 1769 case WM8904_FLL_BCLK: 1770 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1771 WM8904_FLL_CLK_REF_SRC_MASK, 2); 1772 break; 1773 } 1774 1775 if (fll_div.k) 1776 val = WM8904_FLL_FRACN_ENA; 1777 else 1778 val = 0; 1779 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1780 WM8904_FLL_FRACN_ENA, val); 1781 1782 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2, 1783 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 1784 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 1785 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 1786 1787 snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k); 1788 1789 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 1790 fll_div.n << WM8904_FLL_N_SHIFT); 1791 1792 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1793 WM8904_FLL_CLK_REF_DIV_MASK, 1794 fll_div.fll_clk_ref_div 1795 << WM8904_FLL_CLK_REF_DIV_SHIFT); 1796 1797 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 1798 1799 wm8904->fll_fref = Fref; 1800 wm8904->fll_fout = Fout; 1801 wm8904->fll_src = source; 1802 1803 /* Enable the FLL if it was previously active */ 1804 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1805 WM8904_FLL_OSC_ENA, fll1); 1806 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1807 WM8904_FLL_ENA, fll1); 1808 1809 out: 1810 /* Reenable SYSCLK if it was previously active */ 1811 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1812 WM8904_CLK_SYS_ENA, clock2); 1813 1814 return 0; 1815 } 1816 1817 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1818 { 1819 struct snd_soc_component *component = codec_dai->component; 1820 int val; 1821 1822 if (mute) 1823 val = WM8904_DAC_MUTE; 1824 else 1825 val = 0; 1826 1827 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 1828 1829 return 0; 1830 } 1831 1832 static int wm8904_set_bias_level(struct snd_soc_component *component, 1833 enum snd_soc_bias_level level) 1834 { 1835 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1836 int ret; 1837 1838 switch (level) { 1839 case SND_SOC_BIAS_ON: 1840 break; 1841 1842 case SND_SOC_BIAS_PREPARE: 1843 /* VMID resistance 2*50k */ 1844 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1845 WM8904_VMID_RES_MASK, 1846 0x1 << WM8904_VMID_RES_SHIFT); 1847 1848 /* Normal bias current */ 1849 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1850 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 1851 break; 1852 1853 case SND_SOC_BIAS_STANDBY: 1854 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1855 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 1856 wm8904->supplies); 1857 if (ret != 0) { 1858 dev_err(component->dev, 1859 "Failed to enable supplies: %d\n", 1860 ret); 1861 return ret; 1862 } 1863 1864 ret = clk_prepare_enable(wm8904->mclk); 1865 if (ret) { 1866 dev_err(component->dev, 1867 "Failed to enable MCLK: %d\n", ret); 1868 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1869 wm8904->supplies); 1870 return ret; 1871 } 1872 1873 regcache_cache_only(wm8904->regmap, false); 1874 regcache_sync(wm8904->regmap); 1875 1876 /* Enable bias */ 1877 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1878 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 1879 1880 /* Enable VMID, VMID buffering, 2*5k resistance */ 1881 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1882 WM8904_VMID_ENA | 1883 WM8904_VMID_RES_MASK, 1884 WM8904_VMID_ENA | 1885 0x3 << WM8904_VMID_RES_SHIFT); 1886 1887 /* Let VMID ramp */ 1888 msleep(1); 1889 } 1890 1891 /* Maintain VMID with 2*250k */ 1892 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1893 WM8904_VMID_RES_MASK, 1894 0x2 << WM8904_VMID_RES_SHIFT); 1895 1896 /* Bias current *0.5 */ 1897 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1898 WM8904_ISEL_MASK, 0); 1899 break; 1900 1901 case SND_SOC_BIAS_OFF: 1902 /* Turn off VMID */ 1903 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1904 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 1905 1906 /* Stop bias generation */ 1907 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1908 WM8904_BIAS_ENA, 0); 1909 1910 regcache_cache_only(wm8904->regmap, true); 1911 regcache_mark_dirty(wm8904->regmap); 1912 1913 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1914 wm8904->supplies); 1915 clk_disable_unprepare(wm8904->mclk); 1916 break; 1917 } 1918 return 0; 1919 } 1920 1921 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 1922 1923 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1924 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1925 1926 static const struct snd_soc_dai_ops wm8904_dai_ops = { 1927 .set_sysclk = wm8904_set_sysclk, 1928 .set_fmt = wm8904_set_fmt, 1929 .set_tdm_slot = wm8904_set_tdm_slot, 1930 .set_pll = wm8904_set_fll, 1931 .hw_params = wm8904_hw_params, 1932 .digital_mute = wm8904_digital_mute, 1933 }; 1934 1935 static struct snd_soc_dai_driver wm8904_dai = { 1936 .name = "wm8904-hifi", 1937 .playback = { 1938 .stream_name = "Playback", 1939 .channels_min = 2, 1940 .channels_max = 2, 1941 .rates = WM8904_RATES, 1942 .formats = WM8904_FORMATS, 1943 }, 1944 .capture = { 1945 .stream_name = "Capture", 1946 .channels_min = 2, 1947 .channels_max = 2, 1948 .rates = WM8904_RATES, 1949 .formats = WM8904_FORMATS, 1950 }, 1951 .ops = &wm8904_dai_ops, 1952 .symmetric_rates = 1, 1953 }; 1954 1955 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component) 1956 { 1957 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1958 struct wm8904_pdata *pdata = wm8904->pdata; 1959 struct snd_kcontrol_new control = 1960 SOC_ENUM_EXT("EQ Mode", 1961 wm8904->retune_mobile_enum, 1962 wm8904_get_retune_mobile_enum, 1963 wm8904_put_retune_mobile_enum); 1964 int ret, i, j; 1965 const char **t; 1966 1967 /* We need an array of texts for the enum API but the number 1968 * of texts is likely to be less than the number of 1969 * configurations due to the sample rate dependency of the 1970 * configurations. */ 1971 wm8904->num_retune_mobile_texts = 0; 1972 wm8904->retune_mobile_texts = NULL; 1973 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 1974 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 1975 if (strcmp(pdata->retune_mobile_cfgs[i].name, 1976 wm8904->retune_mobile_texts[j]) == 0) 1977 break; 1978 } 1979 1980 if (j != wm8904->num_retune_mobile_texts) 1981 continue; 1982 1983 /* Expand the array... */ 1984 t = krealloc(wm8904->retune_mobile_texts, 1985 sizeof(char *) * 1986 (wm8904->num_retune_mobile_texts + 1), 1987 GFP_KERNEL); 1988 if (t == NULL) 1989 continue; 1990 1991 /* ...store the new entry... */ 1992 t[wm8904->num_retune_mobile_texts] = 1993 pdata->retune_mobile_cfgs[i].name; 1994 1995 /* ...and remember the new version. */ 1996 wm8904->num_retune_mobile_texts++; 1997 wm8904->retune_mobile_texts = t; 1998 } 1999 2000 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 2001 wm8904->num_retune_mobile_texts); 2002 2003 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts; 2004 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2005 2006 ret = snd_soc_add_component_controls(component, &control, 1); 2007 if (ret != 0) 2008 dev_err(component->dev, 2009 "Failed to add ReTune Mobile control: %d\n", ret); 2010 } 2011 2012 static void wm8904_handle_pdata(struct snd_soc_component *component) 2013 { 2014 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2015 struct wm8904_pdata *pdata = wm8904->pdata; 2016 int ret, i; 2017 2018 if (!pdata) { 2019 snd_soc_add_component_controls(component, wm8904_eq_controls, 2020 ARRAY_SIZE(wm8904_eq_controls)); 2021 return; 2022 } 2023 2024 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2025 2026 if (pdata->num_drc_cfgs) { 2027 struct snd_kcontrol_new control = 2028 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2029 wm8904_get_drc_enum, wm8904_put_drc_enum); 2030 2031 /* We need an array of texts for the enum API */ 2032 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs, 2033 sizeof(char *), 2034 GFP_KERNEL); 2035 if (!wm8904->drc_texts) 2036 return; 2037 2038 for (i = 0; i < pdata->num_drc_cfgs; i++) 2039 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2040 2041 wm8904->drc_enum.items = pdata->num_drc_cfgs; 2042 wm8904->drc_enum.texts = wm8904->drc_texts; 2043 2044 ret = snd_soc_add_component_controls(component, &control, 1); 2045 if (ret != 0) 2046 dev_err(component->dev, 2047 "Failed to add DRC mode control: %d\n", ret); 2048 2049 wm8904_set_drc(component); 2050 } 2051 2052 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 2053 pdata->num_retune_mobile_cfgs); 2054 2055 if (pdata->num_retune_mobile_cfgs) 2056 wm8904_handle_retune_mobile_pdata(component); 2057 else 2058 snd_soc_add_component_controls(component, wm8904_eq_controls, 2059 ARRAY_SIZE(wm8904_eq_controls)); 2060 } 2061 2062 2063 static int wm8904_probe(struct snd_soc_component *component) 2064 { 2065 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2066 2067 switch (wm8904->devtype) { 2068 case WM8904: 2069 break; 2070 case WM8912: 2071 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2072 break; 2073 default: 2074 dev_err(component->dev, "Unknown device type %d\n", 2075 wm8904->devtype); 2076 return -EINVAL; 2077 } 2078 2079 wm8904_handle_pdata(component); 2080 2081 wm8904_add_widgets(component); 2082 2083 return 0; 2084 } 2085 2086 static void wm8904_remove(struct snd_soc_component *component) 2087 { 2088 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2089 2090 kfree(wm8904->retune_mobile_texts); 2091 kfree(wm8904->drc_texts); 2092 } 2093 2094 static const struct snd_soc_component_driver soc_component_dev_wm8904 = { 2095 .probe = wm8904_probe, 2096 .remove = wm8904_remove, 2097 .set_bias_level = wm8904_set_bias_level, 2098 .use_pmdown_time = 1, 2099 .endianness = 1, 2100 .non_legacy_dai_naming = 1, 2101 }; 2102 2103 static const struct regmap_config wm8904_regmap = { 2104 .reg_bits = 8, 2105 .val_bits = 16, 2106 2107 .max_register = WM8904_MAX_REGISTER, 2108 .volatile_reg = wm8904_volatile_register, 2109 .readable_reg = wm8904_readable_register, 2110 2111 .cache_type = REGCACHE_RBTREE, 2112 .reg_defaults = wm8904_reg_defaults, 2113 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults), 2114 }; 2115 2116 #ifdef CONFIG_OF 2117 static const struct of_device_id wm8904_of_match[] = { 2118 { 2119 .compatible = "wlf,wm8904", 2120 .data = (void *)WM8904, 2121 }, { 2122 .compatible = "wlf,wm8912", 2123 .data = (void *)WM8912, 2124 }, { 2125 /* sentinel */ 2126 } 2127 }; 2128 MODULE_DEVICE_TABLE(of, wm8904_of_match); 2129 #endif 2130 2131 static int wm8904_i2c_probe(struct i2c_client *i2c, 2132 const struct i2c_device_id *id) 2133 { 2134 struct wm8904_priv *wm8904; 2135 unsigned int val; 2136 int ret, i; 2137 2138 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), 2139 GFP_KERNEL); 2140 if (wm8904 == NULL) 2141 return -ENOMEM; 2142 2143 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk"); 2144 if (IS_ERR(wm8904->mclk)) { 2145 ret = PTR_ERR(wm8904->mclk); 2146 dev_err(&i2c->dev, "Failed to get MCLK\n"); 2147 return ret; 2148 } 2149 2150 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); 2151 if (IS_ERR(wm8904->regmap)) { 2152 ret = PTR_ERR(wm8904->regmap); 2153 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2154 ret); 2155 return ret; 2156 } 2157 2158 if (i2c->dev.of_node) { 2159 const struct of_device_id *match; 2160 2161 match = of_match_node(wm8904_of_match, i2c->dev.of_node); 2162 if (match == NULL) 2163 return -EINVAL; 2164 wm8904->devtype = (enum wm8904_type)match->data; 2165 } else { 2166 wm8904->devtype = id->driver_data; 2167 } 2168 2169 i2c_set_clientdata(i2c, wm8904); 2170 wm8904->pdata = i2c->dev.platform_data; 2171 2172 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2173 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2174 2175 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), 2176 wm8904->supplies); 2177 if (ret != 0) { 2178 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2179 return ret; 2180 } 2181 2182 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2183 wm8904->supplies); 2184 if (ret != 0) { 2185 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2186 return ret; 2187 } 2188 2189 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); 2190 if (ret < 0) { 2191 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2192 goto err_enable; 2193 } 2194 if (val != 0x8904) { 2195 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); 2196 ret = -EINVAL; 2197 goto err_enable; 2198 } 2199 2200 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); 2201 if (ret < 0) { 2202 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2203 ret); 2204 goto err_enable; 2205 } 2206 dev_info(&i2c->dev, "revision %c\n", val + 'A'); 2207 2208 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); 2209 if (ret < 0) { 2210 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2211 goto err_enable; 2212 } 2213 2214 /* Change some default settings - latch VU and enable ZC */ 2215 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, 2216 WM8904_ADC_VU, WM8904_ADC_VU); 2217 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 2218 WM8904_ADC_VU, WM8904_ADC_VU); 2219 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, 2220 WM8904_DAC_VU, WM8904_DAC_VU); 2221 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, 2222 WM8904_DAC_VU, WM8904_DAC_VU); 2223 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, 2224 WM8904_HPOUT_VU | WM8904_HPOUTLZC, 2225 WM8904_HPOUT_VU | WM8904_HPOUTLZC); 2226 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, 2227 WM8904_HPOUT_VU | WM8904_HPOUTRZC, 2228 WM8904_HPOUT_VU | WM8904_HPOUTRZC); 2229 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, 2230 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, 2231 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); 2232 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, 2233 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, 2234 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); 2235 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, 2236 WM8904_SR_MODE, 0); 2237 2238 /* Apply configuration from the platform data. */ 2239 if (wm8904->pdata) { 2240 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2241 if (!wm8904->pdata->gpio_cfg[i]) 2242 continue; 2243 2244 regmap_update_bits(wm8904->regmap, 2245 WM8904_GPIO_CONTROL_1 + i, 2246 0xffff, 2247 wm8904->pdata->gpio_cfg[i]); 2248 } 2249 2250 /* Zero is the default value for these anyway */ 2251 for (i = 0; i < WM8904_MIC_REGS; i++) 2252 regmap_update_bits(wm8904->regmap, 2253 WM8904_MIC_BIAS_CONTROL_0 + i, 2254 0xffff, 2255 wm8904->pdata->mic_cfg[i]); 2256 } 2257 2258 /* Set Class W by default - this will be managed by the Class 2259 * G widget at runtime where bypass paths are available. 2260 */ 2261 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, 2262 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); 2263 2264 /* Use normal bias source */ 2265 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, 2266 WM8904_POBCTRL, 0); 2267 2268 /* Can leave the device powered off until we need it */ 2269 regcache_cache_only(wm8904->regmap, true); 2270 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2271 2272 ret = devm_snd_soc_register_component(&i2c->dev, 2273 &soc_component_dev_wm8904, &wm8904_dai, 1); 2274 if (ret != 0) 2275 return ret; 2276 2277 return 0; 2278 2279 err_enable: 2280 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2281 return ret; 2282 } 2283 2284 static const struct i2c_device_id wm8904_i2c_id[] = { 2285 { "wm8904", WM8904 }, 2286 { "wm8912", WM8912 }, 2287 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ 2288 { } 2289 }; 2290 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2291 2292 static struct i2c_driver wm8904_i2c_driver = { 2293 .driver = { 2294 .name = "wm8904", 2295 .of_match_table = of_match_ptr(wm8904_of_match), 2296 }, 2297 .probe = wm8904_i2c_probe, 2298 .id_table = wm8904_i2c_id, 2299 }; 2300 2301 module_i2c_driver(wm8904_i2c_driver); 2302 2303 MODULE_DESCRIPTION("ASoC WM8904 driver"); 2304 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2305 MODULE_LICENSE("GPL"); 2306