1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8904.c -- WM8904 ALSA SoC Audio driver 4 * 5 * Copyright 2009-12 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/i2c.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <sound/wm8904.h> 26 27 #include "wm8904.h" 28 29 enum wm8904_type { 30 WM8904, 31 WM8912, 32 }; 33 34 #define WM8904_NUM_DCS_CHANNELS 4 35 36 #define WM8904_NUM_SUPPLIES 5 37 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 38 "DCVDD", 39 "DBVDD", 40 "AVDD", 41 "CPVDD", 42 "MICVDD", 43 }; 44 45 /* codec private data */ 46 struct wm8904_priv { 47 struct regmap *regmap; 48 struct clk *mclk; 49 50 enum wm8904_type devtype; 51 52 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 53 54 struct wm8904_pdata *pdata; 55 56 int deemph; 57 58 /* Platform provided DRC configuration */ 59 const char **drc_texts; 60 int drc_cfg; 61 struct soc_enum drc_enum; 62 63 /* Platform provided ReTune mobile configuration */ 64 int num_retune_mobile_texts; 65 const char **retune_mobile_texts; 66 int retune_mobile_cfg; 67 struct soc_enum retune_mobile_enum; 68 69 /* FLL setup */ 70 int fll_src; 71 int fll_fref; 72 int fll_fout; 73 74 /* Clocking configuration */ 75 unsigned int mclk_rate; 76 int sysclk_src; 77 unsigned int sysclk_rate; 78 79 int tdm_width; 80 int tdm_slots; 81 int bclk; 82 int fs; 83 84 /* DC servo configuration - cached offset values */ 85 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 86 }; 87 88 static const struct reg_default wm8904_reg_defaults[] = { 89 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 90 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */ 93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 94 { 9, 0x9696 }, /* R9 - mic Filter Control */ 95 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 96 { 12, 0x0000 }, /* R12 - Power Management 0 */ 97 { 14, 0x0000 }, /* R14 - Power Management 2 */ 98 { 15, 0x0000 }, /* R15 - Power Management 3 */ 99 { 18, 0x0000 }, /* R18 - Power Management 6 */ 100 { 20, 0x945E }, /* R20 - Clock Rates 0 */ 101 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */ 102 { 22, 0x0006 }, /* R22 - Clock Rates 2 */ 103 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 104 { 25, 0x000A }, /* R25 - Audio Interface 1 */ 105 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */ 106 { 27, 0x0040 }, /* R27 - Audio Interface 3 */ 107 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 108 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 109 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 110 { 33, 0x0008 }, /* R33 - DAC Digital 1 */ 111 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 112 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 113 { 38, 0x0010 }, /* R38 - ADC Digital 0 */ 114 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */ 115 { 40, 0x01AF }, /* R40 - DRC 0 */ 116 { 41, 0x3248 }, /* R41 - DRC 1 */ 117 { 42, 0x0000 }, /* R42 - DRC 2 */ 118 { 43, 0x0000 }, /* R43 - DRC 3 */ 119 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 120 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 121 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 122 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 123 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 124 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 125 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 126 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 127 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */ 128 { 67, 0x0000 }, /* R67 - DC Servo 0 */ 129 { 69, 0xAAAA }, /* R69 - DC Servo 2 */ 130 { 71, 0xAAAA }, /* R71 - DC Servo 4 */ 131 { 72, 0xAAAA }, /* R72 - DC Servo 5 */ 132 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 133 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 134 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 135 { 104, 0x0004 }, /* R104 - Class W 0 */ 136 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 137 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 138 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 139 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 140 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 141 { 116, 0x0000 }, /* R116 - FLL Control 1 */ 142 { 117, 0x0007 }, /* R117 - FLL Control 2 */ 143 { 118, 0x0000 }, /* R118 - FLL Control 3 */ 144 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */ 145 { 120, 0x0004 }, /* R120 - FLL Control 5 */ 146 { 121, 0x0014 }, /* R121 - GPIO Control 1 */ 147 { 122, 0x0010 }, /* R122 - GPIO Control 2 */ 148 { 123, 0x0010 }, /* R123 - GPIO Control 3 */ 149 { 124, 0x0000 }, /* R124 - GPIO Control 4 */ 150 { 126, 0x0000 }, /* R126 - Digital Pulls */ 151 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */ 152 { 129, 0x0000 }, /* R129 - Interrupt Polarity */ 153 { 130, 0x0000 }, /* R130 - Interrupt Debounce */ 154 { 134, 0x0000 }, /* R134 - EQ1 */ 155 { 135, 0x000C }, /* R135 - EQ2 */ 156 { 136, 0x000C }, /* R136 - EQ3 */ 157 { 137, 0x000C }, /* R137 - EQ4 */ 158 { 138, 0x000C }, /* R138 - EQ5 */ 159 { 139, 0x000C }, /* R139 - EQ6 */ 160 { 140, 0x0FCA }, /* R140 - EQ7 */ 161 { 141, 0x0400 }, /* R141 - EQ8 */ 162 { 142, 0x00D8 }, /* R142 - EQ9 */ 163 { 143, 0x1EB5 }, /* R143 - EQ10 */ 164 { 144, 0xF145 }, /* R144 - EQ11 */ 165 { 145, 0x0B75 }, /* R145 - EQ12 */ 166 { 146, 0x01C5 }, /* R146 - EQ13 */ 167 { 147, 0x1C58 }, /* R147 - EQ14 */ 168 { 148, 0xF373 }, /* R148 - EQ15 */ 169 { 149, 0x0A54 }, /* R149 - EQ16 */ 170 { 150, 0x0558 }, /* R150 - EQ17 */ 171 { 151, 0x168E }, /* R151 - EQ18 */ 172 { 152, 0xF829 }, /* R152 - EQ19 */ 173 { 153, 0x07AD }, /* R153 - EQ20 */ 174 { 154, 0x1103 }, /* R154 - EQ21 */ 175 { 155, 0x0564 }, /* R155 - EQ22 */ 176 { 156, 0x0559 }, /* R156 - EQ23 */ 177 { 157, 0x4000 }, /* R157 - EQ24 */ 178 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */ 179 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */ 180 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */ 181 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */ 182 }; 183 184 static bool wm8904_volatile_register(struct device *dev, unsigned int reg) 185 { 186 switch (reg) { 187 case WM8904_SW_RESET_AND_ID: 188 case WM8904_REVISION: 189 case WM8904_DC_SERVO_1: 190 case WM8904_DC_SERVO_6: 191 case WM8904_DC_SERVO_7: 192 case WM8904_DC_SERVO_8: 193 case WM8904_DC_SERVO_9: 194 case WM8904_DC_SERVO_READBACK_0: 195 case WM8904_INTERRUPT_STATUS: 196 return true; 197 default: 198 return false; 199 } 200 } 201 202 static bool wm8904_readable_register(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case WM8904_SW_RESET_AND_ID: 206 case WM8904_REVISION: 207 case WM8904_BIAS_CONTROL_0: 208 case WM8904_VMID_CONTROL_0: 209 case WM8904_MIC_BIAS_CONTROL_0: 210 case WM8904_MIC_BIAS_CONTROL_1: 211 case WM8904_ANALOGUE_DAC_0: 212 case WM8904_MIC_FILTER_CONTROL: 213 case WM8904_ANALOGUE_ADC_0: 214 case WM8904_POWER_MANAGEMENT_0: 215 case WM8904_POWER_MANAGEMENT_2: 216 case WM8904_POWER_MANAGEMENT_3: 217 case WM8904_POWER_MANAGEMENT_6: 218 case WM8904_CLOCK_RATES_0: 219 case WM8904_CLOCK_RATES_1: 220 case WM8904_CLOCK_RATES_2: 221 case WM8904_AUDIO_INTERFACE_0: 222 case WM8904_AUDIO_INTERFACE_1: 223 case WM8904_AUDIO_INTERFACE_2: 224 case WM8904_AUDIO_INTERFACE_3: 225 case WM8904_DAC_DIGITAL_VOLUME_LEFT: 226 case WM8904_DAC_DIGITAL_VOLUME_RIGHT: 227 case WM8904_DAC_DIGITAL_0: 228 case WM8904_DAC_DIGITAL_1: 229 case WM8904_ADC_DIGITAL_VOLUME_LEFT: 230 case WM8904_ADC_DIGITAL_VOLUME_RIGHT: 231 case WM8904_ADC_DIGITAL_0: 232 case WM8904_DIGITAL_MICROPHONE_0: 233 case WM8904_DRC_0: 234 case WM8904_DRC_1: 235 case WM8904_DRC_2: 236 case WM8904_DRC_3: 237 case WM8904_ANALOGUE_LEFT_INPUT_0: 238 case WM8904_ANALOGUE_RIGHT_INPUT_0: 239 case WM8904_ANALOGUE_LEFT_INPUT_1: 240 case WM8904_ANALOGUE_RIGHT_INPUT_1: 241 case WM8904_ANALOGUE_OUT1_LEFT: 242 case WM8904_ANALOGUE_OUT1_RIGHT: 243 case WM8904_ANALOGUE_OUT2_LEFT: 244 case WM8904_ANALOGUE_OUT2_RIGHT: 245 case WM8904_ANALOGUE_OUT12_ZC: 246 case WM8904_DC_SERVO_0: 247 case WM8904_DC_SERVO_1: 248 case WM8904_DC_SERVO_2: 249 case WM8904_DC_SERVO_4: 250 case WM8904_DC_SERVO_5: 251 case WM8904_DC_SERVO_6: 252 case WM8904_DC_SERVO_7: 253 case WM8904_DC_SERVO_8: 254 case WM8904_DC_SERVO_9: 255 case WM8904_DC_SERVO_READBACK_0: 256 case WM8904_ANALOGUE_HP_0: 257 case WM8904_ANALOGUE_LINEOUT_0: 258 case WM8904_CHARGE_PUMP_0: 259 case WM8904_CLASS_W_0: 260 case WM8904_WRITE_SEQUENCER_0: 261 case WM8904_WRITE_SEQUENCER_1: 262 case WM8904_WRITE_SEQUENCER_2: 263 case WM8904_WRITE_SEQUENCER_3: 264 case WM8904_WRITE_SEQUENCER_4: 265 case WM8904_FLL_CONTROL_1: 266 case WM8904_FLL_CONTROL_2: 267 case WM8904_FLL_CONTROL_3: 268 case WM8904_FLL_CONTROL_4: 269 case WM8904_FLL_CONTROL_5: 270 case WM8904_GPIO_CONTROL_1: 271 case WM8904_GPIO_CONTROL_2: 272 case WM8904_GPIO_CONTROL_3: 273 case WM8904_GPIO_CONTROL_4: 274 case WM8904_DIGITAL_PULLS: 275 case WM8904_INTERRUPT_STATUS: 276 case WM8904_INTERRUPT_STATUS_MASK: 277 case WM8904_INTERRUPT_POLARITY: 278 case WM8904_INTERRUPT_DEBOUNCE: 279 case WM8904_EQ1: 280 case WM8904_EQ2: 281 case WM8904_EQ3: 282 case WM8904_EQ4: 283 case WM8904_EQ5: 284 case WM8904_EQ6: 285 case WM8904_EQ7: 286 case WM8904_EQ8: 287 case WM8904_EQ9: 288 case WM8904_EQ10: 289 case WM8904_EQ11: 290 case WM8904_EQ12: 291 case WM8904_EQ13: 292 case WM8904_EQ14: 293 case WM8904_EQ15: 294 case WM8904_EQ16: 295 case WM8904_EQ17: 296 case WM8904_EQ18: 297 case WM8904_EQ19: 298 case WM8904_EQ20: 299 case WM8904_EQ21: 300 case WM8904_EQ22: 301 case WM8904_EQ23: 302 case WM8904_EQ24: 303 case WM8904_CONTROL_INTERFACE_TEST_1: 304 case WM8904_ADC_TEST_0: 305 case WM8904_ANALOGUE_OUTPUT_BIAS_0: 306 case WM8904_FLL_NCO_TEST_0: 307 case WM8904_FLL_NCO_TEST_1: 308 return true; 309 default: 310 return false; 311 } 312 } 313 314 static int wm8904_configure_clocking(struct snd_soc_component *component) 315 { 316 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 317 unsigned int clock0, clock2, rate; 318 319 /* Gate the clock while we're updating to avoid misclocking */ 320 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2); 321 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 322 WM8904_SYSCLK_SRC, 0); 323 324 /* This should be done on init() for bypass paths */ 325 switch (wm8904->sysclk_src) { 326 case WM8904_CLK_MCLK: 327 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 328 329 clock2 &= ~WM8904_SYSCLK_SRC; 330 rate = wm8904->mclk_rate; 331 332 /* Ensure the FLL is stopped */ 333 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 334 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 335 break; 336 337 case WM8904_CLK_FLL: 338 dev_dbg(component->dev, "Using %dHz FLL clock\n", 339 wm8904->fll_fout); 340 341 clock2 |= WM8904_SYSCLK_SRC; 342 rate = wm8904->fll_fout; 343 break; 344 345 default: 346 dev_err(component->dev, "System clock not configured\n"); 347 return -EINVAL; 348 } 349 350 /* SYSCLK shouldn't be over 13.5MHz */ 351 if (rate > 13500000) { 352 clock0 = WM8904_MCLK_DIV; 353 wm8904->sysclk_rate = rate / 2; 354 } else { 355 clock0 = 0; 356 wm8904->sysclk_rate = rate; 357 } 358 359 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 360 clock0); 361 362 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 363 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 364 365 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 366 367 return 0; 368 } 369 370 static void wm8904_set_drc(struct snd_soc_component *component) 371 { 372 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 373 struct wm8904_pdata *pdata = wm8904->pdata; 374 int save, i; 375 376 /* Save any enables; the configuration should clear them. */ 377 save = snd_soc_component_read32(component, WM8904_DRC_0); 378 379 for (i = 0; i < WM8904_DRC_REGS; i++) 380 snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff, 381 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 382 383 /* Reenable the DRC */ 384 snd_soc_component_update_bits(component, WM8904_DRC_0, 385 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 386 } 387 388 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 389 struct snd_ctl_elem_value *ucontrol) 390 { 391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 392 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 393 struct wm8904_pdata *pdata = wm8904->pdata; 394 int value = ucontrol->value.enumerated.item[0]; 395 396 if (value >= pdata->num_drc_cfgs) 397 return -EINVAL; 398 399 wm8904->drc_cfg = value; 400 401 wm8904_set_drc(component); 402 403 return 0; 404 } 405 406 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408 { 409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 410 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 411 412 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 413 414 return 0; 415 } 416 417 static void wm8904_set_retune_mobile(struct snd_soc_component *component) 418 { 419 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 420 struct wm8904_pdata *pdata = wm8904->pdata; 421 int best, best_val, save, i, cfg; 422 423 if (!pdata || !wm8904->num_retune_mobile_texts) 424 return; 425 426 /* Find the version of the currently selected configuration 427 * with the nearest sample rate. */ 428 cfg = wm8904->retune_mobile_cfg; 429 best = 0; 430 best_val = INT_MAX; 431 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 432 if (strcmp(pdata->retune_mobile_cfgs[i].name, 433 wm8904->retune_mobile_texts[cfg]) == 0 && 434 abs(pdata->retune_mobile_cfgs[i].rate 435 - wm8904->fs) < best_val) { 436 best = i; 437 best_val = abs(pdata->retune_mobile_cfgs[i].rate 438 - wm8904->fs); 439 } 440 } 441 442 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 443 pdata->retune_mobile_cfgs[best].name, 444 pdata->retune_mobile_cfgs[best].rate, 445 wm8904->fs); 446 447 /* The EQ will be disabled while reconfiguring it, remember the 448 * current configuration. 449 */ 450 save = snd_soc_component_read32(component, WM8904_EQ1); 451 452 for (i = 0; i < WM8904_EQ_REGS; i++) 453 snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff, 454 pdata->retune_mobile_cfgs[best].regs[i]); 455 456 snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save); 457 } 458 459 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 460 struct snd_ctl_elem_value *ucontrol) 461 { 462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 463 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 464 struct wm8904_pdata *pdata = wm8904->pdata; 465 int value = ucontrol->value.enumerated.item[0]; 466 467 if (value >= pdata->num_retune_mobile_cfgs) 468 return -EINVAL; 469 470 wm8904->retune_mobile_cfg = value; 471 472 wm8904_set_retune_mobile(component); 473 474 return 0; 475 } 476 477 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 478 struct snd_ctl_elem_value *ucontrol) 479 { 480 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 481 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 482 483 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 484 485 return 0; 486 } 487 488 static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 489 490 static int wm8904_set_deemph(struct snd_soc_component *component) 491 { 492 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 493 int val, i, best; 494 495 /* If we're using deemphasis select the nearest available sample 496 * rate. 497 */ 498 if (wm8904->deemph) { 499 best = 1; 500 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 501 if (abs(deemph_settings[i] - wm8904->fs) < 502 abs(deemph_settings[best] - wm8904->fs)) 503 best = i; 504 } 505 506 val = best << WM8904_DEEMPH_SHIFT; 507 } else { 508 val = 0; 509 } 510 511 dev_dbg(component->dev, "Set deemphasis %d\n", val); 512 513 return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 514 WM8904_DEEMPH_MASK, val); 515 } 516 517 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 518 struct snd_ctl_elem_value *ucontrol) 519 { 520 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 521 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 522 523 ucontrol->value.integer.value[0] = wm8904->deemph; 524 return 0; 525 } 526 527 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 528 struct snd_ctl_elem_value *ucontrol) 529 { 530 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 531 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 532 unsigned int deemph = ucontrol->value.integer.value[0]; 533 534 if (deemph > 1) 535 return -EINVAL; 536 537 wm8904->deemph = deemph; 538 539 return wm8904_set_deemph(component); 540 } 541 542 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 543 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 544 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 545 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 546 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 547 548 static const char *input_mode_text[] = { 549 "Single-Ended", "Differential Line", "Differential Mic" 550 }; 551 552 static SOC_ENUM_SINGLE_DECL(lin_mode, 553 WM8904_ANALOGUE_LEFT_INPUT_1, 0, 554 input_mode_text); 555 556 static SOC_ENUM_SINGLE_DECL(rin_mode, 557 WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 558 input_mode_text); 559 560 static const char *hpf_mode_text[] = { 561 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 562 }; 563 564 static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5, 565 hpf_mode_text); 566 567 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, 568 struct snd_ctl_elem_value *ucontrol) 569 { 570 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 571 unsigned int val; 572 int ret; 573 574 ret = snd_soc_put_volsw(kcontrol, ucontrol); 575 if (ret < 0) 576 return ret; 577 578 if (ucontrol->value.integer.value[0]) 579 val = 0; 580 else 581 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; 582 583 snd_soc_component_update_bits(component, WM8904_ADC_TEST_0, 584 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5, 585 val); 586 587 return ret; 588 } 589 590 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 591 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 592 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 593 594 SOC_ENUM("Left Capture Mode", lin_mode), 595 SOC_ENUM("Right Capture Mode", rin_mode), 596 597 /* No TLV since it depends on mode */ 598 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 599 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 600 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 601 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), 602 603 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 604 SOC_ENUM("High Pass Filter Mode", hpf_mode), 605 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0, 606 snd_soc_get_volsw, wm8904_adc_osr_put), 607 }; 608 609 static const char *drc_path_text[] = { 610 "ADC", "DAC" 611 }; 612 613 static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text); 614 615 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 616 SOC_SINGLE_TLV("Digital Playback Boost Volume", 617 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 618 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 619 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 620 621 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 622 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 623 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 624 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 625 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 626 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 627 628 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 629 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 630 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 631 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 632 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 633 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 634 635 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 636 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 637 SOC_ENUM("DRC Path", drc_path), 638 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 639 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 640 wm8904_get_deemph, wm8904_put_deemph), 641 }; 642 643 static const struct snd_kcontrol_new wm8904_snd_controls[] = { 644 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 645 sidetone_tlv), 646 }; 647 648 static const struct snd_kcontrol_new wm8904_eq_controls[] = { 649 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 650 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 651 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 652 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 653 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 654 }; 655 656 static int cp_event(struct snd_soc_dapm_widget *w, 657 struct snd_kcontrol *kcontrol, int event) 658 { 659 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU)) 660 return -EINVAL; 661 662 /* Maximum startup time */ 663 udelay(500); 664 665 return 0; 666 } 667 668 static int sysclk_event(struct snd_soc_dapm_widget *w, 669 struct snd_kcontrol *kcontrol, int event) 670 { 671 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 672 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 673 674 switch (event) { 675 case SND_SOC_DAPM_PRE_PMU: 676 /* If we're using the FLL then we only start it when 677 * required; we assume that the configuration has been 678 * done previously and all we need to do is kick it 679 * off. 680 */ 681 switch (wm8904->sysclk_src) { 682 case WM8904_CLK_FLL: 683 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 684 WM8904_FLL_OSC_ENA, 685 WM8904_FLL_OSC_ENA); 686 687 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 688 WM8904_FLL_ENA, 689 WM8904_FLL_ENA); 690 break; 691 692 default: 693 break; 694 } 695 break; 696 697 case SND_SOC_DAPM_POST_PMD: 698 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 699 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 700 break; 701 } 702 703 return 0; 704 } 705 706 static int out_pga_event(struct snd_soc_dapm_widget *w, 707 struct snd_kcontrol *kcontrol, int event) 708 { 709 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 710 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 711 int reg, val; 712 int dcs_mask; 713 int dcs_l, dcs_r; 714 int dcs_l_reg, dcs_r_reg; 715 int timeout; 716 int pwr_reg; 717 718 /* This code is shared between HP and LINEOUT; we do all our 719 * power management in stereo pairs to avoid latency issues so 720 * we reuse shift to identify which rather than strcmp() the 721 * name. */ 722 reg = w->shift; 723 724 switch (reg) { 725 case WM8904_ANALOGUE_HP_0: 726 pwr_reg = WM8904_POWER_MANAGEMENT_2; 727 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 728 dcs_r_reg = WM8904_DC_SERVO_8; 729 dcs_l_reg = WM8904_DC_SERVO_9; 730 dcs_l = 0; 731 dcs_r = 1; 732 break; 733 case WM8904_ANALOGUE_LINEOUT_0: 734 pwr_reg = WM8904_POWER_MANAGEMENT_3; 735 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 736 dcs_r_reg = WM8904_DC_SERVO_6; 737 dcs_l_reg = WM8904_DC_SERVO_7; 738 dcs_l = 2; 739 dcs_r = 3; 740 break; 741 default: 742 WARN(1, "Invalid reg %d\n", reg); 743 return -EINVAL; 744 } 745 746 switch (event) { 747 case SND_SOC_DAPM_PRE_PMU: 748 /* Power on the PGAs */ 749 snd_soc_component_update_bits(component, pwr_reg, 750 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 751 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 752 753 /* Power on the amplifier */ 754 snd_soc_component_update_bits(component, reg, 755 WM8904_HPL_ENA | WM8904_HPR_ENA, 756 WM8904_HPL_ENA | WM8904_HPR_ENA); 757 758 759 /* Enable the first stage */ 760 snd_soc_component_update_bits(component, reg, 761 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 762 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 763 764 /* Power up the DC servo */ 765 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 766 dcs_mask, dcs_mask); 767 768 /* Either calibrate the DC servo or restore cached state 769 * if we have that. 770 */ 771 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 772 dev_dbg(component->dev, "Restoring DC servo state\n"); 773 774 snd_soc_component_write(component, dcs_l_reg, 775 wm8904->dcs_state[dcs_l]); 776 snd_soc_component_write(component, dcs_r_reg, 777 wm8904->dcs_state[dcs_r]); 778 779 snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask); 780 781 timeout = 20; 782 } else { 783 dev_dbg(component->dev, "Calibrating DC servo\n"); 784 785 snd_soc_component_write(component, WM8904_DC_SERVO_1, 786 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 787 788 timeout = 500; 789 } 790 791 /* Wait for DC servo to complete */ 792 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 793 do { 794 val = snd_soc_component_read32(component, WM8904_DC_SERVO_READBACK_0); 795 if ((val & dcs_mask) == dcs_mask) 796 break; 797 798 msleep(1); 799 } while (--timeout); 800 801 if ((val & dcs_mask) != dcs_mask) 802 dev_warn(component->dev, "DC servo timed out\n"); 803 else 804 dev_dbg(component->dev, "DC servo ready\n"); 805 806 /* Enable the output stage */ 807 snd_soc_component_update_bits(component, reg, 808 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 809 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 810 break; 811 812 case SND_SOC_DAPM_POST_PMU: 813 /* Unshort the output itself */ 814 snd_soc_component_update_bits(component, reg, 815 WM8904_HPL_RMV_SHORT | 816 WM8904_HPR_RMV_SHORT, 817 WM8904_HPL_RMV_SHORT | 818 WM8904_HPR_RMV_SHORT); 819 820 break; 821 822 case SND_SOC_DAPM_PRE_PMD: 823 /* Short the output */ 824 snd_soc_component_update_bits(component, reg, 825 WM8904_HPL_RMV_SHORT | 826 WM8904_HPR_RMV_SHORT, 0); 827 break; 828 829 case SND_SOC_DAPM_POST_PMD: 830 /* Cache the DC servo configuration; this will be 831 * invalidated if we change the configuration. */ 832 wm8904->dcs_state[dcs_l] = snd_soc_component_read32(component, dcs_l_reg); 833 wm8904->dcs_state[dcs_r] = snd_soc_component_read32(component, dcs_r_reg); 834 835 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, 836 dcs_mask, 0); 837 838 /* Disable the amplifier input and output stages */ 839 snd_soc_component_update_bits(component, reg, 840 WM8904_HPL_ENA | WM8904_HPR_ENA | 841 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 842 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 843 0); 844 845 /* PGAs too */ 846 snd_soc_component_update_bits(component, pwr_reg, 847 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 848 0); 849 break; 850 } 851 852 return 0; 853 } 854 855 static const char *lin_text[] = { 856 "IN1L", "IN2L", "IN3L" 857 }; 858 859 static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2, 860 lin_text); 861 862 static const struct snd_kcontrol_new lin_mux = 863 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 864 865 static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4, 866 lin_text); 867 868 static const struct snd_kcontrol_new lin_inv_mux = 869 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 870 871 static const char *rin_text[] = { 872 "IN1R", "IN2R", "IN3R" 873 }; 874 875 static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 876 rin_text); 877 878 static const struct snd_kcontrol_new rin_mux = 879 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 880 881 static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 882 rin_text); 883 884 static const struct snd_kcontrol_new rin_inv_mux = 885 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 886 887 static const char *aif_text[] = { 888 "Left", "Right" 889 }; 890 891 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7, 892 aif_text); 893 894 static const struct snd_kcontrol_new aifoutl_mux = 895 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 896 897 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6, 898 aif_text); 899 900 static const struct snd_kcontrol_new aifoutr_mux = 901 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 902 903 static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5, 904 aif_text); 905 906 static const struct snd_kcontrol_new aifinl_mux = 907 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 908 909 static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4, 910 aif_text); 911 912 static const struct snd_kcontrol_new aifinr_mux = 913 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 914 915 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 916 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 917 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 918 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 919 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 920 }; 921 922 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 923 SND_SOC_DAPM_INPUT("IN1L"), 924 SND_SOC_DAPM_INPUT("IN1R"), 925 SND_SOC_DAPM_INPUT("IN2L"), 926 SND_SOC_DAPM_INPUT("IN2R"), 927 SND_SOC_DAPM_INPUT("IN3L"), 928 SND_SOC_DAPM_INPUT("IN3R"), 929 930 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 931 932 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 933 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 934 &lin_inv_mux), 935 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 936 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 937 &rin_inv_mux), 938 939 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 940 NULL, 0), 941 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 942 NULL, 0), 943 944 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 945 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 946 947 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 948 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 949 950 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 951 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 952 }; 953 954 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 955 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 956 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 957 958 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 959 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 960 961 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 962 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 963 964 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 965 SND_SOC_DAPM_POST_PMU), 966 967 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 968 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 969 970 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 971 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 972 973 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 974 0, NULL, 0, out_pga_event, 975 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 976 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 977 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 978 0, NULL, 0, out_pga_event, 979 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 980 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 981 982 SND_SOC_DAPM_OUTPUT("HPOUTL"), 983 SND_SOC_DAPM_OUTPUT("HPOUTR"), 984 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 985 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 986 }; 987 988 static const char *out_mux_text[] = { 989 "DAC", "Bypass" 990 }; 991 992 static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3, 993 out_mux_text); 994 995 static const struct snd_kcontrol_new hpl_mux = 996 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 997 998 static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2, 999 out_mux_text); 1000 1001 static const struct snd_kcontrol_new hpr_mux = 1002 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1003 1004 static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1, 1005 out_mux_text); 1006 1007 static const struct snd_kcontrol_new linel_mux = 1008 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1009 1010 static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0, 1011 out_mux_text); 1012 1013 static const struct snd_kcontrol_new liner_mux = 1014 SOC_DAPM_ENUM("LINER Mux", liner_enum); 1015 1016 static const char *sidetone_text[] = { 1017 "None", "Left", "Right" 1018 }; 1019 1020 static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2, 1021 sidetone_text); 1022 1023 static const struct snd_kcontrol_new dacl_sidetone_mux = 1024 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1025 1026 static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0, 1027 sidetone_text); 1028 1029 static const struct snd_kcontrol_new dacr_sidetone_mux = 1030 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1031 1032 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1033 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1034 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1035 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1036 1037 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1038 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1039 1040 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1041 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1042 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1043 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1044 }; 1045 1046 static const struct snd_soc_dapm_route core_intercon[] = { 1047 { "CLK_DSP", NULL, "SYSCLK" }, 1048 { "TOCLK", NULL, "SYSCLK" }, 1049 }; 1050 1051 static const struct snd_soc_dapm_route adc_intercon[] = { 1052 { "Left Capture Mux", "IN1L", "IN1L" }, 1053 { "Left Capture Mux", "IN2L", "IN2L" }, 1054 { "Left Capture Mux", "IN3L", "IN3L" }, 1055 1056 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1057 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1058 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1059 1060 { "Right Capture Mux", "IN1R", "IN1R" }, 1061 { "Right Capture Mux", "IN2R", "IN2R" }, 1062 { "Right Capture Mux", "IN3R", "IN3R" }, 1063 1064 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1065 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1066 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1067 1068 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1069 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1070 1071 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1072 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1073 1074 { "AIFOUTL Mux", "Left", "ADCL" }, 1075 { "AIFOUTL Mux", "Right", "ADCR" }, 1076 { "AIFOUTR Mux", "Left", "ADCL" }, 1077 { "AIFOUTR Mux", "Right", "ADCR" }, 1078 1079 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 1080 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 1081 1082 { "ADCL", NULL, "CLK_DSP" }, 1083 { "ADCL", NULL, "Left Capture PGA" }, 1084 1085 { "ADCR", NULL, "CLK_DSP" }, 1086 { "ADCR", NULL, "Right Capture PGA" }, 1087 }; 1088 1089 static const struct snd_soc_dapm_route dac_intercon[] = { 1090 { "DACL Mux", "Left", "AIFINL" }, 1091 { "DACL Mux", "Right", "AIFINR" }, 1092 1093 { "DACR Mux", "Left", "AIFINL" }, 1094 { "DACR Mux", "Right", "AIFINR" }, 1095 1096 { "DACL", NULL, "DACL Mux" }, 1097 { "DACL", NULL, "CLK_DSP" }, 1098 1099 { "DACR", NULL, "DACR Mux" }, 1100 { "DACR", NULL, "CLK_DSP" }, 1101 1102 { "Charge pump", NULL, "SYSCLK" }, 1103 1104 { "Headphone Output", NULL, "HPL PGA" }, 1105 { "Headphone Output", NULL, "HPR PGA" }, 1106 { "Headphone Output", NULL, "Charge pump" }, 1107 { "Headphone Output", NULL, "TOCLK" }, 1108 1109 { "Line Output", NULL, "LINEL PGA" }, 1110 { "Line Output", NULL, "LINER PGA" }, 1111 { "Line Output", NULL, "Charge pump" }, 1112 { "Line Output", NULL, "TOCLK" }, 1113 1114 { "HPOUTL", NULL, "Headphone Output" }, 1115 { "HPOUTR", NULL, "Headphone Output" }, 1116 1117 { "LINEOUTL", NULL, "Line Output" }, 1118 { "LINEOUTR", NULL, "Line Output" }, 1119 }; 1120 1121 static const struct snd_soc_dapm_route wm8904_intercon[] = { 1122 { "Left Sidetone", "Left", "ADCL" }, 1123 { "Left Sidetone", "Right", "ADCR" }, 1124 { "DACL", NULL, "Left Sidetone" }, 1125 1126 { "Right Sidetone", "Left", "ADCL" }, 1127 { "Right Sidetone", "Right", "ADCR" }, 1128 { "DACR", NULL, "Right Sidetone" }, 1129 1130 { "Left Bypass", NULL, "Class G" }, 1131 { "Left Bypass", NULL, "Left Capture PGA" }, 1132 1133 { "Right Bypass", NULL, "Class G" }, 1134 { "Right Bypass", NULL, "Right Capture PGA" }, 1135 1136 { "HPL Mux", "DAC", "DACL" }, 1137 { "HPL Mux", "Bypass", "Left Bypass" }, 1138 1139 { "HPR Mux", "DAC", "DACR" }, 1140 { "HPR Mux", "Bypass", "Right Bypass" }, 1141 1142 { "LINEL Mux", "DAC", "DACL" }, 1143 { "LINEL Mux", "Bypass", "Left Bypass" }, 1144 1145 { "LINER Mux", "DAC", "DACR" }, 1146 { "LINER Mux", "Bypass", "Right Bypass" }, 1147 1148 { "HPL PGA", NULL, "HPL Mux" }, 1149 { "HPR PGA", NULL, "HPR Mux" }, 1150 1151 { "LINEL PGA", NULL, "LINEL Mux" }, 1152 { "LINER PGA", NULL, "LINER Mux" }, 1153 }; 1154 1155 static const struct snd_soc_dapm_route wm8912_intercon[] = { 1156 { "HPL PGA", NULL, "DACL" }, 1157 { "HPR PGA", NULL, "DACR" }, 1158 1159 { "LINEL PGA", NULL, "DACL" }, 1160 { "LINER PGA", NULL, "DACR" }, 1161 }; 1162 1163 static int wm8904_add_widgets(struct snd_soc_component *component) 1164 { 1165 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1166 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1167 1168 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, 1169 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1170 snd_soc_dapm_add_routes(dapm, core_intercon, 1171 ARRAY_SIZE(core_intercon)); 1172 1173 switch (wm8904->devtype) { 1174 case WM8904: 1175 snd_soc_add_component_controls(component, wm8904_adc_snd_controls, 1176 ARRAY_SIZE(wm8904_adc_snd_controls)); 1177 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1178 ARRAY_SIZE(wm8904_dac_snd_controls)); 1179 snd_soc_add_component_controls(component, wm8904_snd_controls, 1180 ARRAY_SIZE(wm8904_snd_controls)); 1181 1182 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, 1183 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1184 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1185 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1186 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, 1187 ARRAY_SIZE(wm8904_dapm_widgets)); 1188 1189 snd_soc_dapm_add_routes(dapm, adc_intercon, 1190 ARRAY_SIZE(adc_intercon)); 1191 snd_soc_dapm_add_routes(dapm, dac_intercon, 1192 ARRAY_SIZE(dac_intercon)); 1193 snd_soc_dapm_add_routes(dapm, wm8904_intercon, 1194 ARRAY_SIZE(wm8904_intercon)); 1195 break; 1196 1197 case WM8912: 1198 snd_soc_add_component_controls(component, wm8904_dac_snd_controls, 1199 ARRAY_SIZE(wm8904_dac_snd_controls)); 1200 1201 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1202 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1203 1204 snd_soc_dapm_add_routes(dapm, dac_intercon, 1205 ARRAY_SIZE(dac_intercon)); 1206 snd_soc_dapm_add_routes(dapm, wm8912_intercon, 1207 ARRAY_SIZE(wm8912_intercon)); 1208 break; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static struct { 1215 int ratio; 1216 unsigned int clk_sys_rate; 1217 } clk_sys_rates[] = { 1218 { 64, 0 }, 1219 { 128, 1 }, 1220 { 192, 2 }, 1221 { 256, 3 }, 1222 { 384, 4 }, 1223 { 512, 5 }, 1224 { 786, 6 }, 1225 { 1024, 7 }, 1226 { 1408, 8 }, 1227 { 1536, 9 }, 1228 }; 1229 1230 static struct { 1231 int rate; 1232 int sample_rate; 1233 } sample_rates[] = { 1234 { 8000, 0 }, 1235 { 11025, 1 }, 1236 { 12000, 1 }, 1237 { 16000, 2 }, 1238 { 22050, 3 }, 1239 { 24000, 3 }, 1240 { 32000, 4 }, 1241 { 44100, 5 }, 1242 { 48000, 5 }, 1243 }; 1244 1245 static struct { 1246 int div; /* *10 due to .5s */ 1247 int bclk_div; 1248 } bclk_divs[] = { 1249 { 10, 0 }, 1250 { 15, 1 }, 1251 { 20, 2 }, 1252 { 30, 3 }, 1253 { 40, 4 }, 1254 { 50, 5 }, 1255 { 55, 6 }, 1256 { 60, 7 }, 1257 { 80, 8 }, 1258 { 100, 9 }, 1259 { 110, 10 }, 1260 { 120, 11 }, 1261 { 160, 12 }, 1262 { 200, 13 }, 1263 { 220, 14 }, 1264 { 240, 16 }, 1265 { 200, 17 }, 1266 { 320, 18 }, 1267 { 440, 19 }, 1268 { 480, 20 }, 1269 }; 1270 1271 1272 static int wm8904_hw_params(struct snd_pcm_substream *substream, 1273 struct snd_pcm_hw_params *params, 1274 struct snd_soc_dai *dai) 1275 { 1276 struct snd_soc_component *component = dai->component; 1277 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1278 int ret, i, best, best_val, cur_val; 1279 unsigned int aif1 = 0; 1280 unsigned int aif2 = 0; 1281 unsigned int aif3 = 0; 1282 unsigned int clock1 = 0; 1283 unsigned int dac_digital1 = 0; 1284 1285 /* What BCLK do we need? */ 1286 wm8904->fs = params_rate(params); 1287 if (wm8904->tdm_slots) { 1288 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n", 1289 wm8904->tdm_slots, wm8904->tdm_width); 1290 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1291 wm8904->tdm_width, 2, 1292 wm8904->tdm_slots); 1293 } else { 1294 wm8904->bclk = snd_soc_params_to_bclk(params); 1295 } 1296 1297 switch (params_width(params)) { 1298 case 16: 1299 break; 1300 case 20: 1301 aif1 |= 0x40; 1302 break; 1303 case 24: 1304 aif1 |= 0x80; 1305 break; 1306 case 32: 1307 aif1 |= 0xc0; 1308 break; 1309 default: 1310 return -EINVAL; 1311 } 1312 1313 1314 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1315 1316 ret = wm8904_configure_clocking(component); 1317 if (ret != 0) 1318 return ret; 1319 1320 /* Select nearest CLK_SYS_RATE */ 1321 best = 0; 1322 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1323 - wm8904->fs); 1324 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1325 cur_val = abs((wm8904->sysclk_rate / 1326 clk_sys_rates[i].ratio) - wm8904->fs); 1327 if (cur_val < best_val) { 1328 best = i; 1329 best_val = cur_val; 1330 } 1331 } 1332 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", 1333 clk_sys_rates[best].ratio); 1334 clock1 |= (clk_sys_rates[best].clk_sys_rate 1335 << WM8904_CLK_SYS_RATE_SHIFT); 1336 1337 /* SAMPLE_RATE */ 1338 best = 0; 1339 best_val = abs(wm8904->fs - sample_rates[0].rate); 1340 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1341 /* Closest match */ 1342 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1343 if (cur_val < best_val) { 1344 best = i; 1345 best_val = cur_val; 1346 } 1347 } 1348 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", 1349 sample_rates[best].rate); 1350 clock1 |= (sample_rates[best].sample_rate 1351 << WM8904_SAMPLE_RATE_SHIFT); 1352 1353 /* Enable sloping stopband filter for low sample rates */ 1354 if (wm8904->fs <= 24000) 1355 dac_digital1 |= WM8904_DAC_SB_FILT; 1356 1357 /* BCLK_DIV */ 1358 best = 0; 1359 best_val = INT_MAX; 1360 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1361 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1362 - wm8904->bclk; 1363 if (cur_val < 0) /* Table is sorted */ 1364 break; 1365 if (cur_val < best_val) { 1366 best = i; 1367 best_val = cur_val; 1368 } 1369 } 1370 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1371 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1372 bclk_divs[best].div, wm8904->bclk); 1373 aif2 |= bclk_divs[best].bclk_div; 1374 1375 /* LRCLK is a simple fraction of BCLK */ 1376 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1377 aif3 |= wm8904->bclk / wm8904->fs; 1378 1379 /* Apply the settings */ 1380 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, 1381 WM8904_DAC_SB_FILT, dac_digital1); 1382 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1383 WM8904_AIF_WL_MASK, aif1); 1384 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2, 1385 WM8904_BCLK_DIV_MASK, aif2); 1386 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1387 WM8904_LRCLK_RATE_MASK, aif3); 1388 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1, 1389 WM8904_SAMPLE_RATE_MASK | 1390 WM8904_CLK_SYS_RATE_MASK, clock1); 1391 1392 /* Update filters for the new settings */ 1393 wm8904_set_retune_mobile(component); 1394 wm8904_set_deemph(component); 1395 1396 return 0; 1397 } 1398 1399 1400 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1401 unsigned int freq, int dir) 1402 { 1403 struct snd_soc_component *component = dai->component; 1404 struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); 1405 1406 switch (clk_id) { 1407 case WM8904_CLK_MCLK: 1408 priv->sysclk_src = clk_id; 1409 priv->mclk_rate = freq; 1410 break; 1411 1412 case WM8904_CLK_FLL: 1413 priv->sysclk_src = clk_id; 1414 break; 1415 1416 default: 1417 return -EINVAL; 1418 } 1419 1420 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1421 1422 wm8904_configure_clocking(component); 1423 1424 return 0; 1425 } 1426 1427 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1428 { 1429 struct snd_soc_component *component = dai->component; 1430 unsigned int aif1 = 0; 1431 unsigned int aif3 = 0; 1432 1433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1434 case SND_SOC_DAIFMT_CBS_CFS: 1435 break; 1436 case SND_SOC_DAIFMT_CBS_CFM: 1437 aif3 |= WM8904_LRCLK_DIR; 1438 break; 1439 case SND_SOC_DAIFMT_CBM_CFS: 1440 aif1 |= WM8904_BCLK_DIR; 1441 break; 1442 case SND_SOC_DAIFMT_CBM_CFM: 1443 aif1 |= WM8904_BCLK_DIR; 1444 aif3 |= WM8904_LRCLK_DIR; 1445 break; 1446 default: 1447 return -EINVAL; 1448 } 1449 1450 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1451 case SND_SOC_DAIFMT_DSP_B: 1452 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV; 1453 /* fall through */ 1454 case SND_SOC_DAIFMT_DSP_A: 1455 aif1 |= 0x3; 1456 break; 1457 case SND_SOC_DAIFMT_I2S: 1458 aif1 |= 0x2; 1459 break; 1460 case SND_SOC_DAIFMT_RIGHT_J: 1461 break; 1462 case SND_SOC_DAIFMT_LEFT_J: 1463 aif1 |= 0x1; 1464 break; 1465 default: 1466 return -EINVAL; 1467 } 1468 1469 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1470 case SND_SOC_DAIFMT_DSP_A: 1471 case SND_SOC_DAIFMT_DSP_B: 1472 /* frame inversion not valid for DSP modes */ 1473 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1474 case SND_SOC_DAIFMT_NB_NF: 1475 break; 1476 case SND_SOC_DAIFMT_IB_NF: 1477 aif1 |= WM8904_AIF_BCLK_INV; 1478 break; 1479 default: 1480 return -EINVAL; 1481 } 1482 break; 1483 1484 case SND_SOC_DAIFMT_I2S: 1485 case SND_SOC_DAIFMT_RIGHT_J: 1486 case SND_SOC_DAIFMT_LEFT_J: 1487 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1488 case SND_SOC_DAIFMT_NB_NF: 1489 break; 1490 case SND_SOC_DAIFMT_IB_IF: 1491 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1492 break; 1493 case SND_SOC_DAIFMT_IB_NF: 1494 aif1 |= WM8904_AIF_BCLK_INV; 1495 break; 1496 case SND_SOC_DAIFMT_NB_IF: 1497 aif1 |= WM8904_AIF_LRCLK_INV; 1498 break; 1499 default: 1500 return -EINVAL; 1501 } 1502 break; 1503 default: 1504 return -EINVAL; 1505 } 1506 1507 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1508 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1509 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1510 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, 1511 WM8904_LRCLK_DIR, aif3); 1512 1513 return 0; 1514 } 1515 1516 1517 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1518 unsigned int rx_mask, int slots, int slot_width) 1519 { 1520 struct snd_soc_component *component = dai->component; 1521 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1522 int aif1 = 0; 1523 1524 /* Don't need to validate anything if we're turning off TDM */ 1525 if (slots == 0) 1526 goto out; 1527 1528 /* Note that we allow configurations we can't handle ourselves - 1529 * for example, we can generate clocks for slots 2 and up even if 1530 * we can't use those slots ourselves. 1531 */ 1532 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1533 1534 switch (rx_mask) { 1535 case 3: 1536 break; 1537 case 0xc: 1538 aif1 |= WM8904_AIFADC_TDM_CHAN; 1539 break; 1540 default: 1541 return -EINVAL; 1542 } 1543 1544 1545 switch (tx_mask) { 1546 case 3: 1547 break; 1548 case 0xc: 1549 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1550 break; 1551 default: 1552 return -EINVAL; 1553 } 1554 1555 out: 1556 wm8904->tdm_width = slot_width; 1557 wm8904->tdm_slots = slots / 2; 1558 1559 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, 1560 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1561 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1562 1563 return 0; 1564 } 1565 1566 struct _fll_div { 1567 u16 fll_fratio; 1568 u16 fll_outdiv; 1569 u16 fll_clk_ref_div; 1570 u16 n; 1571 u16 k; 1572 }; 1573 1574 /* The size in bits of the FLL divide multiplied by 10 1575 * to allow rounding later */ 1576 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1577 1578 static struct { 1579 unsigned int min; 1580 unsigned int max; 1581 u16 fll_fratio; 1582 int ratio; 1583 } fll_fratios[] = { 1584 { 0, 64000, 4, 16 }, 1585 { 64000, 128000, 3, 8 }, 1586 { 128000, 256000, 2, 4 }, 1587 { 256000, 1000000, 1, 2 }, 1588 { 1000000, 13500000, 0, 1 }, 1589 }; 1590 1591 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1592 unsigned int Fout) 1593 { 1594 u64 Kpart; 1595 unsigned int K, Ndiv, Nmod, target; 1596 unsigned int div; 1597 int i; 1598 1599 /* Fref must be <=13.5MHz */ 1600 div = 1; 1601 fll_div->fll_clk_ref_div = 0; 1602 while ((Fref / div) > 13500000) { 1603 div *= 2; 1604 fll_div->fll_clk_ref_div++; 1605 1606 if (div > 8) { 1607 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1608 Fref); 1609 return -EINVAL; 1610 } 1611 } 1612 1613 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1614 1615 /* Apply the division for our remaining calculations */ 1616 Fref /= div; 1617 1618 /* Fvco should be 90-100MHz; don't check the upper bound */ 1619 div = 4; 1620 while (Fout * div < 90000000) { 1621 div++; 1622 if (div > 64) { 1623 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1624 Fout); 1625 return -EINVAL; 1626 } 1627 } 1628 target = Fout * div; 1629 fll_div->fll_outdiv = div - 1; 1630 1631 pr_debug("Fvco=%dHz\n", target); 1632 1633 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 1634 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1635 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1636 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1637 target /= fll_fratios[i].ratio; 1638 break; 1639 } 1640 } 1641 if (i == ARRAY_SIZE(fll_fratios)) { 1642 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1643 return -EINVAL; 1644 } 1645 1646 /* Now, calculate N.K */ 1647 Ndiv = target / Fref; 1648 1649 fll_div->n = Ndiv; 1650 Nmod = target % Fref; 1651 pr_debug("Nmod=%d\n", Nmod); 1652 1653 /* Calculate fractional part - scale up so we can round. */ 1654 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1655 1656 do_div(Kpart, Fref); 1657 1658 K = Kpart & 0xFFFFFFFF; 1659 1660 if ((K % 10) >= 5) 1661 K += 5; 1662 1663 /* Move down to proper range now rounding is done */ 1664 fll_div->k = K / 10; 1665 1666 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1667 fll_div->n, fll_div->k, 1668 fll_div->fll_fratio, fll_div->fll_outdiv, 1669 fll_div->fll_clk_ref_div); 1670 1671 return 0; 1672 } 1673 1674 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1675 unsigned int Fref, unsigned int Fout) 1676 { 1677 struct snd_soc_component *component = dai->component; 1678 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1679 struct _fll_div fll_div; 1680 int ret, val; 1681 int clock2, fll1; 1682 1683 /* Any change? */ 1684 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1685 Fout == wm8904->fll_fout) 1686 return 0; 1687 1688 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2); 1689 1690 if (Fout == 0) { 1691 dev_dbg(component->dev, "FLL disabled\n"); 1692 1693 wm8904->fll_fref = 0; 1694 wm8904->fll_fout = 0; 1695 1696 /* Gate SYSCLK to avoid glitches */ 1697 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1698 WM8904_CLK_SYS_ENA, 0); 1699 1700 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1701 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1702 1703 goto out; 1704 } 1705 1706 /* Validate the FLL ID */ 1707 switch (source) { 1708 case WM8904_FLL_MCLK: 1709 case WM8904_FLL_LRCLK: 1710 case WM8904_FLL_BCLK: 1711 ret = fll_factors(&fll_div, Fref, Fout); 1712 if (ret != 0) 1713 return ret; 1714 break; 1715 1716 case WM8904_FLL_FREE_RUNNING: 1717 dev_dbg(component->dev, "Using free running FLL\n"); 1718 /* Force 12MHz and output/4 for now */ 1719 Fout = 12000000; 1720 Fref = 12000000; 1721 1722 memset(&fll_div, 0, sizeof(fll_div)); 1723 fll_div.fll_outdiv = 3; 1724 break; 1725 1726 default: 1727 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); 1728 return -EINVAL; 1729 } 1730 1731 /* Save current state then disable the FLL and SYSCLK to avoid 1732 * misclocking */ 1733 fll1 = snd_soc_component_read32(component, WM8904_FLL_CONTROL_1); 1734 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1735 WM8904_CLK_SYS_ENA, 0); 1736 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1737 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1738 1739 /* Unlock forced oscilator control to switch it on/off */ 1740 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1741 WM8904_USER_KEY, WM8904_USER_KEY); 1742 1743 if (fll_id == WM8904_FLL_FREE_RUNNING) { 1744 val = WM8904_FLL_FRC_NCO; 1745 } else { 1746 val = 0; 1747 } 1748 1749 snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 1750 val); 1751 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, 1752 WM8904_USER_KEY, 0); 1753 1754 switch (fll_id) { 1755 case WM8904_FLL_MCLK: 1756 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1757 WM8904_FLL_CLK_REF_SRC_MASK, 0); 1758 break; 1759 1760 case WM8904_FLL_LRCLK: 1761 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1762 WM8904_FLL_CLK_REF_SRC_MASK, 1); 1763 break; 1764 1765 case WM8904_FLL_BCLK: 1766 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1767 WM8904_FLL_CLK_REF_SRC_MASK, 2); 1768 break; 1769 } 1770 1771 if (fll_div.k) 1772 val = WM8904_FLL_FRACN_ENA; 1773 else 1774 val = 0; 1775 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1776 WM8904_FLL_FRACN_ENA, val); 1777 1778 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2, 1779 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 1780 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 1781 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 1782 1783 snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k); 1784 1785 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 1786 fll_div.n << WM8904_FLL_N_SHIFT); 1787 1788 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, 1789 WM8904_FLL_CLK_REF_DIV_MASK, 1790 fll_div.fll_clk_ref_div 1791 << WM8904_FLL_CLK_REF_DIV_SHIFT); 1792 1793 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 1794 1795 wm8904->fll_fref = Fref; 1796 wm8904->fll_fout = Fout; 1797 wm8904->fll_src = source; 1798 1799 /* Enable the FLL if it was previously active */ 1800 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1801 WM8904_FLL_OSC_ENA, fll1); 1802 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, 1803 WM8904_FLL_ENA, fll1); 1804 1805 out: 1806 /* Reenable SYSCLK if it was previously active */ 1807 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, 1808 WM8904_CLK_SYS_ENA, clock2); 1809 1810 return 0; 1811 } 1812 1813 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1814 { 1815 struct snd_soc_component *component = codec_dai->component; 1816 int val; 1817 1818 if (mute) 1819 val = WM8904_DAC_MUTE; 1820 else 1821 val = 0; 1822 1823 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 1824 1825 return 0; 1826 } 1827 1828 static int wm8904_set_bias_level(struct snd_soc_component *component, 1829 enum snd_soc_bias_level level) 1830 { 1831 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1832 int ret; 1833 1834 switch (level) { 1835 case SND_SOC_BIAS_ON: 1836 break; 1837 1838 case SND_SOC_BIAS_PREPARE: 1839 /* VMID resistance 2*50k */ 1840 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1841 WM8904_VMID_RES_MASK, 1842 0x1 << WM8904_VMID_RES_SHIFT); 1843 1844 /* Normal bias current */ 1845 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1846 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 1847 break; 1848 1849 case SND_SOC_BIAS_STANDBY: 1850 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1851 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 1852 wm8904->supplies); 1853 if (ret != 0) { 1854 dev_err(component->dev, 1855 "Failed to enable supplies: %d\n", 1856 ret); 1857 return ret; 1858 } 1859 1860 ret = clk_prepare_enable(wm8904->mclk); 1861 if (ret) { 1862 dev_err(component->dev, 1863 "Failed to enable MCLK: %d\n", ret); 1864 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1865 wm8904->supplies); 1866 return ret; 1867 } 1868 1869 regcache_cache_only(wm8904->regmap, false); 1870 regcache_sync(wm8904->regmap); 1871 1872 /* Enable bias */ 1873 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1874 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 1875 1876 /* Enable VMID, VMID buffering, 2*5k resistance */ 1877 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1878 WM8904_VMID_ENA | 1879 WM8904_VMID_RES_MASK, 1880 WM8904_VMID_ENA | 1881 0x3 << WM8904_VMID_RES_SHIFT); 1882 1883 /* Let VMID ramp */ 1884 msleep(1); 1885 } 1886 1887 /* Maintain VMID with 2*250k */ 1888 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1889 WM8904_VMID_RES_MASK, 1890 0x2 << WM8904_VMID_RES_SHIFT); 1891 1892 /* Bias current *0.5 */ 1893 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1894 WM8904_ISEL_MASK, 0); 1895 break; 1896 1897 case SND_SOC_BIAS_OFF: 1898 /* Turn off VMID */ 1899 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, 1900 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 1901 1902 /* Stop bias generation */ 1903 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, 1904 WM8904_BIAS_ENA, 0); 1905 1906 regcache_cache_only(wm8904->regmap, true); 1907 regcache_mark_dirty(wm8904->regmap); 1908 1909 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 1910 wm8904->supplies); 1911 clk_disable_unprepare(wm8904->mclk); 1912 break; 1913 } 1914 return 0; 1915 } 1916 1917 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 1918 1919 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1920 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1921 1922 static const struct snd_soc_dai_ops wm8904_dai_ops = { 1923 .set_sysclk = wm8904_set_sysclk, 1924 .set_fmt = wm8904_set_fmt, 1925 .set_tdm_slot = wm8904_set_tdm_slot, 1926 .set_pll = wm8904_set_fll, 1927 .hw_params = wm8904_hw_params, 1928 .digital_mute = wm8904_digital_mute, 1929 }; 1930 1931 static struct snd_soc_dai_driver wm8904_dai = { 1932 .name = "wm8904-hifi", 1933 .playback = { 1934 .stream_name = "Playback", 1935 .channels_min = 2, 1936 .channels_max = 2, 1937 .rates = WM8904_RATES, 1938 .formats = WM8904_FORMATS, 1939 }, 1940 .capture = { 1941 .stream_name = "Capture", 1942 .channels_min = 2, 1943 .channels_max = 2, 1944 .rates = WM8904_RATES, 1945 .formats = WM8904_FORMATS, 1946 }, 1947 .ops = &wm8904_dai_ops, 1948 .symmetric_rates = 1, 1949 }; 1950 1951 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component) 1952 { 1953 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 1954 struct wm8904_pdata *pdata = wm8904->pdata; 1955 struct snd_kcontrol_new control = 1956 SOC_ENUM_EXT("EQ Mode", 1957 wm8904->retune_mobile_enum, 1958 wm8904_get_retune_mobile_enum, 1959 wm8904_put_retune_mobile_enum); 1960 int ret, i, j; 1961 const char **t; 1962 1963 /* We need an array of texts for the enum API but the number 1964 * of texts is likely to be less than the number of 1965 * configurations due to the sample rate dependency of the 1966 * configurations. */ 1967 wm8904->num_retune_mobile_texts = 0; 1968 wm8904->retune_mobile_texts = NULL; 1969 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 1970 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 1971 if (strcmp(pdata->retune_mobile_cfgs[i].name, 1972 wm8904->retune_mobile_texts[j]) == 0) 1973 break; 1974 } 1975 1976 if (j != wm8904->num_retune_mobile_texts) 1977 continue; 1978 1979 /* Expand the array... */ 1980 t = krealloc(wm8904->retune_mobile_texts, 1981 sizeof(char *) * 1982 (wm8904->num_retune_mobile_texts + 1), 1983 GFP_KERNEL); 1984 if (t == NULL) 1985 continue; 1986 1987 /* ...store the new entry... */ 1988 t[wm8904->num_retune_mobile_texts] = 1989 pdata->retune_mobile_cfgs[i].name; 1990 1991 /* ...and remember the new version. */ 1992 wm8904->num_retune_mobile_texts++; 1993 wm8904->retune_mobile_texts = t; 1994 } 1995 1996 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 1997 wm8904->num_retune_mobile_texts); 1998 1999 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts; 2000 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2001 2002 ret = snd_soc_add_component_controls(component, &control, 1); 2003 if (ret != 0) 2004 dev_err(component->dev, 2005 "Failed to add ReTune Mobile control: %d\n", ret); 2006 } 2007 2008 static void wm8904_handle_pdata(struct snd_soc_component *component) 2009 { 2010 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2011 struct wm8904_pdata *pdata = wm8904->pdata; 2012 int ret, i; 2013 2014 if (!pdata) { 2015 snd_soc_add_component_controls(component, wm8904_eq_controls, 2016 ARRAY_SIZE(wm8904_eq_controls)); 2017 return; 2018 } 2019 2020 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2021 2022 if (pdata->num_drc_cfgs) { 2023 struct snd_kcontrol_new control = 2024 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2025 wm8904_get_drc_enum, wm8904_put_drc_enum); 2026 2027 /* We need an array of texts for the enum API */ 2028 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs, 2029 sizeof(char *), 2030 GFP_KERNEL); 2031 if (!wm8904->drc_texts) 2032 return; 2033 2034 for (i = 0; i < pdata->num_drc_cfgs; i++) 2035 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2036 2037 wm8904->drc_enum.items = pdata->num_drc_cfgs; 2038 wm8904->drc_enum.texts = wm8904->drc_texts; 2039 2040 ret = snd_soc_add_component_controls(component, &control, 1); 2041 if (ret != 0) 2042 dev_err(component->dev, 2043 "Failed to add DRC mode control: %d\n", ret); 2044 2045 wm8904_set_drc(component); 2046 } 2047 2048 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 2049 pdata->num_retune_mobile_cfgs); 2050 2051 if (pdata->num_retune_mobile_cfgs) 2052 wm8904_handle_retune_mobile_pdata(component); 2053 else 2054 snd_soc_add_component_controls(component, wm8904_eq_controls, 2055 ARRAY_SIZE(wm8904_eq_controls)); 2056 } 2057 2058 2059 static int wm8904_probe(struct snd_soc_component *component) 2060 { 2061 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2062 2063 switch (wm8904->devtype) { 2064 case WM8904: 2065 break; 2066 case WM8912: 2067 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2068 break; 2069 default: 2070 dev_err(component->dev, "Unknown device type %d\n", 2071 wm8904->devtype); 2072 return -EINVAL; 2073 } 2074 2075 wm8904_handle_pdata(component); 2076 2077 wm8904_add_widgets(component); 2078 2079 return 0; 2080 } 2081 2082 static void wm8904_remove(struct snd_soc_component *component) 2083 { 2084 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); 2085 2086 kfree(wm8904->retune_mobile_texts); 2087 kfree(wm8904->drc_texts); 2088 } 2089 2090 static const struct snd_soc_component_driver soc_component_dev_wm8904 = { 2091 .probe = wm8904_probe, 2092 .remove = wm8904_remove, 2093 .set_bias_level = wm8904_set_bias_level, 2094 .use_pmdown_time = 1, 2095 .endianness = 1, 2096 .non_legacy_dai_naming = 1, 2097 }; 2098 2099 static const struct regmap_config wm8904_regmap = { 2100 .reg_bits = 8, 2101 .val_bits = 16, 2102 2103 .max_register = WM8904_MAX_REGISTER, 2104 .volatile_reg = wm8904_volatile_register, 2105 .readable_reg = wm8904_readable_register, 2106 2107 .cache_type = REGCACHE_RBTREE, 2108 .reg_defaults = wm8904_reg_defaults, 2109 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults), 2110 }; 2111 2112 #ifdef CONFIG_OF 2113 static const struct of_device_id wm8904_of_match[] = { 2114 { 2115 .compatible = "wlf,wm8904", 2116 .data = (void *)WM8904, 2117 }, { 2118 .compatible = "wlf,wm8912", 2119 .data = (void *)WM8912, 2120 }, { 2121 /* sentinel */ 2122 } 2123 }; 2124 MODULE_DEVICE_TABLE(of, wm8904_of_match); 2125 #endif 2126 2127 static int wm8904_i2c_probe(struct i2c_client *i2c, 2128 const struct i2c_device_id *id) 2129 { 2130 struct wm8904_priv *wm8904; 2131 unsigned int val; 2132 int ret, i; 2133 2134 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), 2135 GFP_KERNEL); 2136 if (wm8904 == NULL) 2137 return -ENOMEM; 2138 2139 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk"); 2140 if (IS_ERR(wm8904->mclk)) { 2141 ret = PTR_ERR(wm8904->mclk); 2142 dev_err(&i2c->dev, "Failed to get MCLK\n"); 2143 return ret; 2144 } 2145 2146 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); 2147 if (IS_ERR(wm8904->regmap)) { 2148 ret = PTR_ERR(wm8904->regmap); 2149 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2150 ret); 2151 return ret; 2152 } 2153 2154 if (i2c->dev.of_node) { 2155 const struct of_device_id *match; 2156 2157 match = of_match_node(wm8904_of_match, i2c->dev.of_node); 2158 if (match == NULL) 2159 return -EINVAL; 2160 wm8904->devtype = (enum wm8904_type)match->data; 2161 } else { 2162 wm8904->devtype = id->driver_data; 2163 } 2164 2165 i2c_set_clientdata(i2c, wm8904); 2166 wm8904->pdata = i2c->dev.platform_data; 2167 2168 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2169 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2170 2171 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), 2172 wm8904->supplies); 2173 if (ret != 0) { 2174 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2175 return ret; 2176 } 2177 2178 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2179 wm8904->supplies); 2180 if (ret != 0) { 2181 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2182 return ret; 2183 } 2184 2185 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); 2186 if (ret < 0) { 2187 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2188 goto err_enable; 2189 } 2190 if (val != 0x8904) { 2191 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); 2192 ret = -EINVAL; 2193 goto err_enable; 2194 } 2195 2196 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); 2197 if (ret < 0) { 2198 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2199 ret); 2200 goto err_enable; 2201 } 2202 dev_info(&i2c->dev, "revision %c\n", val + 'A'); 2203 2204 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); 2205 if (ret < 0) { 2206 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2207 goto err_enable; 2208 } 2209 2210 /* Change some default settings - latch VU and enable ZC */ 2211 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, 2212 WM8904_ADC_VU, WM8904_ADC_VU); 2213 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 2214 WM8904_ADC_VU, WM8904_ADC_VU); 2215 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, 2216 WM8904_DAC_VU, WM8904_DAC_VU); 2217 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, 2218 WM8904_DAC_VU, WM8904_DAC_VU); 2219 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, 2220 WM8904_HPOUT_VU | WM8904_HPOUTLZC, 2221 WM8904_HPOUT_VU | WM8904_HPOUTLZC); 2222 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, 2223 WM8904_HPOUT_VU | WM8904_HPOUTRZC, 2224 WM8904_HPOUT_VU | WM8904_HPOUTRZC); 2225 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, 2226 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, 2227 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); 2228 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, 2229 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, 2230 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); 2231 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, 2232 WM8904_SR_MODE, 0); 2233 2234 /* Apply configuration from the platform data. */ 2235 if (wm8904->pdata) { 2236 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2237 if (!wm8904->pdata->gpio_cfg[i]) 2238 continue; 2239 2240 regmap_update_bits(wm8904->regmap, 2241 WM8904_GPIO_CONTROL_1 + i, 2242 0xffff, 2243 wm8904->pdata->gpio_cfg[i]); 2244 } 2245 2246 /* Zero is the default value for these anyway */ 2247 for (i = 0; i < WM8904_MIC_REGS; i++) 2248 regmap_update_bits(wm8904->regmap, 2249 WM8904_MIC_BIAS_CONTROL_0 + i, 2250 0xffff, 2251 wm8904->pdata->mic_cfg[i]); 2252 } 2253 2254 /* Set Class W by default - this will be managed by the Class 2255 * G widget at runtime where bypass paths are available. 2256 */ 2257 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, 2258 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); 2259 2260 /* Use normal bias source */ 2261 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, 2262 WM8904_POBCTRL, 0); 2263 2264 /* Can leave the device powered off until we need it */ 2265 regcache_cache_only(wm8904->regmap, true); 2266 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2267 2268 ret = devm_snd_soc_register_component(&i2c->dev, 2269 &soc_component_dev_wm8904, &wm8904_dai, 1); 2270 if (ret != 0) 2271 return ret; 2272 2273 return 0; 2274 2275 err_enable: 2276 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2277 return ret; 2278 } 2279 2280 static const struct i2c_device_id wm8904_i2c_id[] = { 2281 { "wm8904", WM8904 }, 2282 { "wm8912", WM8912 }, 2283 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ 2284 { } 2285 }; 2286 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2287 2288 static struct i2c_driver wm8904_i2c_driver = { 2289 .driver = { 2290 .name = "wm8904", 2291 .of_match_table = of_match_ptr(wm8904_of_match), 2292 }, 2293 .probe = wm8904_i2c_probe, 2294 .id_table = wm8904_i2c_id, 2295 }; 2296 2297 module_i2c_driver(wm8904_i2c_driver); 2298 2299 MODULE_DESCRIPTION("ASoC WM8904 driver"); 2300 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2301 MODULE_LICENSE("GPL"); 2302