1 /* 2 * wm8904.c -- WM8904 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/wm8904.h> 30 31 #include "wm8904.h" 32 33 enum wm8904_type { 34 WM8904, 35 WM8912, 36 }; 37 38 #define WM8904_NUM_DCS_CHANNELS 4 39 40 #define WM8904_NUM_SUPPLIES 5 41 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 42 "DCVDD", 43 "DBVDD", 44 "AVDD", 45 "CPVDD", 46 "MICVDD", 47 }; 48 49 /* codec private data */ 50 struct wm8904_priv { 51 52 enum wm8904_type devtype; 53 void *control_data; 54 55 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 56 57 struct wm8904_pdata *pdata; 58 59 int deemph; 60 61 /* Platform provided DRC configuration */ 62 const char **drc_texts; 63 int drc_cfg; 64 struct soc_enum drc_enum; 65 66 /* Platform provided ReTune mobile configuration */ 67 int num_retune_mobile_texts; 68 const char **retune_mobile_texts; 69 int retune_mobile_cfg; 70 struct soc_enum retune_mobile_enum; 71 72 /* FLL setup */ 73 int fll_src; 74 int fll_fref; 75 int fll_fout; 76 77 /* Clocking configuration */ 78 unsigned int mclk_rate; 79 int sysclk_src; 80 unsigned int sysclk_rate; 81 82 int tdm_width; 83 int tdm_slots; 84 int bclk; 85 int fs; 86 87 /* DC servo configuration - cached offset values */ 88 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 89 }; 90 91 static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { 92 0x8904, /* R0 - SW Reset and ID */ 93 0x0000, /* R1 - Revision */ 94 0x0000, /* R2 */ 95 0x0000, /* R3 */ 96 0x0018, /* R4 - Bias Control 0 */ 97 0x0000, /* R5 - VMID Control 0 */ 98 0x0000, /* R6 - Mic Bias Control 0 */ 99 0x0000, /* R7 - Mic Bias Control 1 */ 100 0x0001, /* R8 - Analogue DAC 0 */ 101 0x9696, /* R9 - mic Filter Control */ 102 0x0001, /* R10 - Analogue ADC 0 */ 103 0x0000, /* R11 */ 104 0x0000, /* R12 - Power Management 0 */ 105 0x0000, /* R13 */ 106 0x0000, /* R14 - Power Management 2 */ 107 0x0000, /* R15 - Power Management 3 */ 108 0x0000, /* R16 */ 109 0x0000, /* R17 */ 110 0x0000, /* R18 - Power Management 6 */ 111 0x0000, /* R19 */ 112 0x945E, /* R20 - Clock Rates 0 */ 113 0x0C05, /* R21 - Clock Rates 1 */ 114 0x0006, /* R22 - Clock Rates 2 */ 115 0x0000, /* R23 */ 116 0x0050, /* R24 - Audio Interface 0 */ 117 0x000A, /* R25 - Audio Interface 1 */ 118 0x00E4, /* R26 - Audio Interface 2 */ 119 0x0040, /* R27 - Audio Interface 3 */ 120 0x0000, /* R28 */ 121 0x0000, /* R29 */ 122 0x00C0, /* R30 - DAC Digital Volume Left */ 123 0x00C0, /* R31 - DAC Digital Volume Right */ 124 0x0000, /* R32 - DAC Digital 0 */ 125 0x0008, /* R33 - DAC Digital 1 */ 126 0x0000, /* R34 */ 127 0x0000, /* R35 */ 128 0x00C0, /* R36 - ADC Digital Volume Left */ 129 0x00C0, /* R37 - ADC Digital Volume Right */ 130 0x0010, /* R38 - ADC Digital 0 */ 131 0x0000, /* R39 - Digital Microphone 0 */ 132 0x01AF, /* R40 - DRC 0 */ 133 0x3248, /* R41 - DRC 1 */ 134 0x0000, /* R42 - DRC 2 */ 135 0x0000, /* R43 - DRC 3 */ 136 0x0085, /* R44 - Analogue Left Input 0 */ 137 0x0085, /* R45 - Analogue Right Input 0 */ 138 0x0044, /* R46 - Analogue Left Input 1 */ 139 0x0044, /* R47 - Analogue Right Input 1 */ 140 0x0000, /* R48 */ 141 0x0000, /* R49 */ 142 0x0000, /* R50 */ 143 0x0000, /* R51 */ 144 0x0000, /* R52 */ 145 0x0000, /* R53 */ 146 0x0000, /* R54 */ 147 0x0000, /* R55 */ 148 0x0000, /* R56 */ 149 0x002D, /* R57 - Analogue OUT1 Left */ 150 0x002D, /* R58 - Analogue OUT1 Right */ 151 0x0039, /* R59 - Analogue OUT2 Left */ 152 0x0039, /* R60 - Analogue OUT2 Right */ 153 0x0000, /* R61 - Analogue OUT12 ZC */ 154 0x0000, /* R62 */ 155 0x0000, /* R63 */ 156 0x0000, /* R64 */ 157 0x0000, /* R65 */ 158 0x0000, /* R66 */ 159 0x0000, /* R67 - DC Servo 0 */ 160 0x0000, /* R68 - DC Servo 1 */ 161 0xAAAA, /* R69 - DC Servo 2 */ 162 0x0000, /* R70 */ 163 0xAAAA, /* R71 - DC Servo 4 */ 164 0xAAAA, /* R72 - DC Servo 5 */ 165 0x0000, /* R73 - DC Servo 6 */ 166 0x0000, /* R74 - DC Servo 7 */ 167 0x0000, /* R75 - DC Servo 8 */ 168 0x0000, /* R76 - DC Servo 9 */ 169 0x0000, /* R77 - DC Servo Readback 0 */ 170 0x0000, /* R78 */ 171 0x0000, /* R79 */ 172 0x0000, /* R80 */ 173 0x0000, /* R81 */ 174 0x0000, /* R82 */ 175 0x0000, /* R83 */ 176 0x0000, /* R84 */ 177 0x0000, /* R85 */ 178 0x0000, /* R86 */ 179 0x0000, /* R87 */ 180 0x0000, /* R88 */ 181 0x0000, /* R89 */ 182 0x0000, /* R90 - Analogue HP 0 */ 183 0x0000, /* R91 */ 184 0x0000, /* R92 */ 185 0x0000, /* R93 */ 186 0x0000, /* R94 - Analogue Lineout 0 */ 187 0x0000, /* R95 */ 188 0x0000, /* R96 */ 189 0x0000, /* R97 */ 190 0x0000, /* R98 - Charge Pump 0 */ 191 0x0000, /* R99 */ 192 0x0000, /* R100 */ 193 0x0000, /* R101 */ 194 0x0000, /* R102 */ 195 0x0000, /* R103 */ 196 0x0004, /* R104 - Class W 0 */ 197 0x0000, /* R105 */ 198 0x0000, /* R106 */ 199 0x0000, /* R107 */ 200 0x0000, /* R108 - Write Sequencer 0 */ 201 0x0000, /* R109 - Write Sequencer 1 */ 202 0x0000, /* R110 - Write Sequencer 2 */ 203 0x0000, /* R111 - Write Sequencer 3 */ 204 0x0000, /* R112 - Write Sequencer 4 */ 205 0x0000, /* R113 */ 206 0x0000, /* R114 */ 207 0x0000, /* R115 */ 208 0x0000, /* R116 - FLL Control 1 */ 209 0x0007, /* R117 - FLL Control 2 */ 210 0x0000, /* R118 - FLL Control 3 */ 211 0x2EE0, /* R119 - FLL Control 4 */ 212 0x0004, /* R120 - FLL Control 5 */ 213 0x0014, /* R121 - GPIO Control 1 */ 214 0x0010, /* R122 - GPIO Control 2 */ 215 0x0010, /* R123 - GPIO Control 3 */ 216 0x0000, /* R124 - GPIO Control 4 */ 217 0x0000, /* R125 */ 218 0x0000, /* R126 - Digital Pulls */ 219 0x0000, /* R127 - Interrupt Status */ 220 0xFFFF, /* R128 - Interrupt Status Mask */ 221 0x0000, /* R129 - Interrupt Polarity */ 222 0x0000, /* R130 - Interrupt Debounce */ 223 0x0000, /* R131 */ 224 0x0000, /* R132 */ 225 0x0000, /* R133 */ 226 0x0000, /* R134 - EQ1 */ 227 0x000C, /* R135 - EQ2 */ 228 0x000C, /* R136 - EQ3 */ 229 0x000C, /* R137 - EQ4 */ 230 0x000C, /* R138 - EQ5 */ 231 0x000C, /* R139 - EQ6 */ 232 0x0FCA, /* R140 - EQ7 */ 233 0x0400, /* R141 - EQ8 */ 234 0x00D8, /* R142 - EQ9 */ 235 0x1EB5, /* R143 - EQ10 */ 236 0xF145, /* R144 - EQ11 */ 237 0x0B75, /* R145 - EQ12 */ 238 0x01C5, /* R146 - EQ13 */ 239 0x1C58, /* R147 - EQ14 */ 240 0xF373, /* R148 - EQ15 */ 241 0x0A54, /* R149 - EQ16 */ 242 0x0558, /* R150 - EQ17 */ 243 0x168E, /* R151 - EQ18 */ 244 0xF829, /* R152 - EQ19 */ 245 0x07AD, /* R153 - EQ20 */ 246 0x1103, /* R154 - EQ21 */ 247 0x0564, /* R155 - EQ22 */ 248 0x0559, /* R156 - EQ23 */ 249 0x4000, /* R157 - EQ24 */ 250 0x0000, /* R158 */ 251 0x0000, /* R159 */ 252 0x0000, /* R160 */ 253 0x0000, /* R161 - Control Interface Test 1 */ 254 0x0000, /* R162 */ 255 0x0000, /* R163 */ 256 0x0000, /* R164 */ 257 0x0000, /* R165 */ 258 0x0000, /* R166 */ 259 0x0000, /* R167 */ 260 0x0000, /* R168 */ 261 0x0000, /* R169 */ 262 0x0000, /* R170 */ 263 0x0000, /* R171 */ 264 0x0000, /* R172 */ 265 0x0000, /* R173 */ 266 0x0000, /* R174 */ 267 0x0000, /* R175 */ 268 0x0000, /* R176 */ 269 0x0000, /* R177 */ 270 0x0000, /* R178 */ 271 0x0000, /* R179 */ 272 0x0000, /* R180 */ 273 0x0000, /* R181 */ 274 0x0000, /* R182 */ 275 0x0000, /* R183 */ 276 0x0000, /* R184 */ 277 0x0000, /* R185 */ 278 0x0000, /* R186 */ 279 0x0000, /* R187 */ 280 0x0000, /* R188 */ 281 0x0000, /* R189 */ 282 0x0000, /* R190 */ 283 0x0000, /* R191 */ 284 0x0000, /* R192 */ 285 0x0000, /* R193 */ 286 0x0000, /* R194 */ 287 0x0000, /* R195 */ 288 0x0000, /* R196 */ 289 0x0000, /* R197 */ 290 0x0000, /* R198 */ 291 0x0000, /* R199 */ 292 0x0000, /* R200 */ 293 0x0000, /* R201 */ 294 0x0000, /* R202 */ 295 0x0000, /* R203 */ 296 0x0000, /* R204 - Analogue Output Bias 0 */ 297 0x0000, /* R205 */ 298 0x0000, /* R206 */ 299 0x0000, /* R207 */ 300 0x0000, /* R208 */ 301 0x0000, /* R209 */ 302 0x0000, /* R210 */ 303 0x0000, /* R211 */ 304 0x0000, /* R212 */ 305 0x0000, /* R213 */ 306 0x0000, /* R214 */ 307 0x0000, /* R215 */ 308 0x0000, /* R216 */ 309 0x0000, /* R217 */ 310 0x0000, /* R218 */ 311 0x0000, /* R219 */ 312 0x0000, /* R220 */ 313 0x0000, /* R221 */ 314 0x0000, /* R222 */ 315 0x0000, /* R223 */ 316 0x0000, /* R224 */ 317 0x0000, /* R225 */ 318 0x0000, /* R226 */ 319 0x0000, /* R227 */ 320 0x0000, /* R228 */ 321 0x0000, /* R229 */ 322 0x0000, /* R230 */ 323 0x0000, /* R231 */ 324 0x0000, /* R232 */ 325 0x0000, /* R233 */ 326 0x0000, /* R234 */ 327 0x0000, /* R235 */ 328 0x0000, /* R236 */ 329 0x0000, /* R237 */ 330 0x0000, /* R238 */ 331 0x0000, /* R239 */ 332 0x0000, /* R240 */ 333 0x0000, /* R241 */ 334 0x0000, /* R242 */ 335 0x0000, /* R243 */ 336 0x0000, /* R244 */ 337 0x0000, /* R245 */ 338 0x0000, /* R246 */ 339 0x0000, /* R247 - FLL NCO Test 0 */ 340 0x0019, /* R248 - FLL NCO Test 1 */ 341 }; 342 343 static struct { 344 int readable; 345 int writable; 346 int vol; 347 } wm8904_access[] = { 348 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ 349 { 0x0000, 0x0000, 0 }, /* R1 - Revision */ 350 { 0x0000, 0x0000, 0 }, /* R2 */ 351 { 0x0000, 0x0000, 0 }, /* R3 */ 352 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ 353 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ 354 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ 355 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ 356 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ 357 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ 358 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ 359 { 0x0000, 0x0000, 0 }, /* R11 */ 360 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ 361 { 0x0000, 0x0000, 0 }, /* R13 */ 362 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ 363 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ 364 { 0x0000, 0x0000, 0 }, /* R16 */ 365 { 0x0000, 0x0000, 0 }, /* R17 */ 366 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ 367 { 0x0000, 0x0000, 0 }, /* R19 */ 368 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ 369 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ 370 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ 371 { 0x0000, 0x0000, 0 }, /* R23 */ 372 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ 373 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ 374 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ 375 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ 376 { 0x0000, 0x0000, 0 }, /* R28 */ 377 { 0x0000, 0x0000, 0 }, /* R29 */ 378 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ 379 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ 380 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ 381 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ 382 { 0x0000, 0x0000, 0 }, /* R34 */ 383 { 0x0000, 0x0000, 0 }, /* R35 */ 384 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ 385 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ 386 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ 387 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ 388 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ 389 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ 390 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ 391 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ 392 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ 393 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ 394 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ 395 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ 396 { 0x0000, 0x0000, 0 }, /* R48 */ 397 { 0x0000, 0x0000, 0 }, /* R49 */ 398 { 0x0000, 0x0000, 0 }, /* R50 */ 399 { 0x0000, 0x0000, 0 }, /* R51 */ 400 { 0x0000, 0x0000, 0 }, /* R52 */ 401 { 0x0000, 0x0000, 0 }, /* R53 */ 402 { 0x0000, 0x0000, 0 }, /* R54 */ 403 { 0x0000, 0x0000, 0 }, /* R55 */ 404 { 0x0000, 0x0000, 0 }, /* R56 */ 405 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ 406 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ 407 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ 408 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ 409 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ 410 { 0x0000, 0x0000, 0 }, /* R62 */ 411 { 0x0000, 0x0000, 0 }, /* R63 */ 412 { 0x0000, 0x0000, 0 }, /* R64 */ 413 { 0x0000, 0x0000, 0 }, /* R65 */ 414 { 0x0000, 0x0000, 0 }, /* R66 */ 415 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ 416 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ 417 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ 418 { 0x0000, 0x0000, 0 }, /* R70 */ 419 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ 420 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ 421 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ 422 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ 423 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ 424 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ 425 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ 426 { 0x0000, 0x0000, 0 }, /* R78 */ 427 { 0x0000, 0x0000, 0 }, /* R79 */ 428 { 0x0000, 0x0000, 0 }, /* R80 */ 429 { 0x0000, 0x0000, 0 }, /* R81 */ 430 { 0x0000, 0x0000, 0 }, /* R82 */ 431 { 0x0000, 0x0000, 0 }, /* R83 */ 432 { 0x0000, 0x0000, 0 }, /* R84 */ 433 { 0x0000, 0x0000, 0 }, /* R85 */ 434 { 0x0000, 0x0000, 0 }, /* R86 */ 435 { 0x0000, 0x0000, 0 }, /* R87 */ 436 { 0x0000, 0x0000, 0 }, /* R88 */ 437 { 0x0000, 0x0000, 0 }, /* R89 */ 438 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ 439 { 0x0000, 0x0000, 0 }, /* R91 */ 440 { 0x0000, 0x0000, 0 }, /* R92 */ 441 { 0x0000, 0x0000, 0 }, /* R93 */ 442 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ 443 { 0x0000, 0x0000, 0 }, /* R95 */ 444 { 0x0000, 0x0000, 0 }, /* R96 */ 445 { 0x0000, 0x0000, 0 }, /* R97 */ 446 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ 447 { 0x0000, 0x0000, 0 }, /* R99 */ 448 { 0x0000, 0x0000, 0 }, /* R100 */ 449 { 0x0000, 0x0000, 0 }, /* R101 */ 450 { 0x0000, 0x0000, 0 }, /* R102 */ 451 { 0x0000, 0x0000, 0 }, /* R103 */ 452 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ 453 { 0x0000, 0x0000, 0 }, /* R105 */ 454 { 0x0000, 0x0000, 0 }, /* R106 */ 455 { 0x0000, 0x0000, 0 }, /* R107 */ 456 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ 457 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ 458 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ 459 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ 460 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ 461 { 0x0000, 0x0000, 0 }, /* R113 */ 462 { 0x0000, 0x0000, 0 }, /* R114 */ 463 { 0x0000, 0x0000, 0 }, /* R115 */ 464 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ 465 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ 466 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ 467 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ 468 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ 469 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ 470 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ 471 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ 472 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ 473 { 0x0000, 0x0000, 0 }, /* R125 */ 474 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ 475 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ 476 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ 477 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ 478 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ 479 { 0x0000, 0x0000, 0 }, /* R131 */ 480 { 0x0000, 0x0000, 0 }, /* R132 */ 481 { 0x0000, 0x0000, 0 }, /* R133 */ 482 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ 483 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ 484 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ 485 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ 486 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ 487 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ 488 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ 489 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ 490 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ 491 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ 492 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ 493 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ 494 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ 495 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ 496 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ 497 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ 498 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ 499 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ 500 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ 501 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ 502 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ 503 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ 504 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ 505 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ 506 { 0x0000, 0x0000, 0 }, /* R158 */ 507 { 0x0000, 0x0000, 0 }, /* R159 */ 508 { 0x0000, 0x0000, 0 }, /* R160 */ 509 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ 510 { 0x0000, 0x0000, 0 }, /* R162 */ 511 { 0x0000, 0x0000, 0 }, /* R163 */ 512 { 0x0000, 0x0000, 0 }, /* R164 */ 513 { 0x0000, 0x0000, 0 }, /* R165 */ 514 { 0x0000, 0x0000, 0 }, /* R166 */ 515 { 0x0000, 0x0000, 0 }, /* R167 */ 516 { 0x0000, 0x0000, 0 }, /* R168 */ 517 { 0x0000, 0x0000, 0 }, /* R169 */ 518 { 0x0000, 0x0000, 0 }, /* R170 */ 519 { 0x0000, 0x0000, 0 }, /* R171 */ 520 { 0x0000, 0x0000, 0 }, /* R172 */ 521 { 0x0000, 0x0000, 0 }, /* R173 */ 522 { 0x0000, 0x0000, 0 }, /* R174 */ 523 { 0x0000, 0x0000, 0 }, /* R175 */ 524 { 0x0000, 0x0000, 0 }, /* R176 */ 525 { 0x0000, 0x0000, 0 }, /* R177 */ 526 { 0x0000, 0x0000, 0 }, /* R178 */ 527 { 0x0000, 0x0000, 0 }, /* R179 */ 528 { 0x0000, 0x0000, 0 }, /* R180 */ 529 { 0x0000, 0x0000, 0 }, /* R181 */ 530 { 0x0000, 0x0000, 0 }, /* R182 */ 531 { 0x0000, 0x0000, 0 }, /* R183 */ 532 { 0x0000, 0x0000, 0 }, /* R184 */ 533 { 0x0000, 0x0000, 0 }, /* R185 */ 534 { 0x0000, 0x0000, 0 }, /* R186 */ 535 { 0x0000, 0x0000, 0 }, /* R187 */ 536 { 0x0000, 0x0000, 0 }, /* R188 */ 537 { 0x0000, 0x0000, 0 }, /* R189 */ 538 { 0x0000, 0x0000, 0 }, /* R190 */ 539 { 0x0000, 0x0000, 0 }, /* R191 */ 540 { 0x0000, 0x0000, 0 }, /* R192 */ 541 { 0x0000, 0x0000, 0 }, /* R193 */ 542 { 0x0000, 0x0000, 0 }, /* R194 */ 543 { 0x0000, 0x0000, 0 }, /* R195 */ 544 { 0x0000, 0x0000, 0 }, /* R196 */ 545 { 0x0000, 0x0000, 0 }, /* R197 */ 546 { 0x0000, 0x0000, 0 }, /* R198 */ 547 { 0x0000, 0x0000, 0 }, /* R199 */ 548 { 0x0000, 0x0000, 0 }, /* R200 */ 549 { 0x0000, 0x0000, 0 }, /* R201 */ 550 { 0x0000, 0x0000, 0 }, /* R202 */ 551 { 0x0000, 0x0000, 0 }, /* R203 */ 552 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ 553 { 0x0000, 0x0000, 0 }, /* R205 */ 554 { 0x0000, 0x0000, 0 }, /* R206 */ 555 { 0x0000, 0x0000, 0 }, /* R207 */ 556 { 0x0000, 0x0000, 0 }, /* R208 */ 557 { 0x0000, 0x0000, 0 }, /* R209 */ 558 { 0x0000, 0x0000, 0 }, /* R210 */ 559 { 0x0000, 0x0000, 0 }, /* R211 */ 560 { 0x0000, 0x0000, 0 }, /* R212 */ 561 { 0x0000, 0x0000, 0 }, /* R213 */ 562 { 0x0000, 0x0000, 0 }, /* R214 */ 563 { 0x0000, 0x0000, 0 }, /* R215 */ 564 { 0x0000, 0x0000, 0 }, /* R216 */ 565 { 0x0000, 0x0000, 0 }, /* R217 */ 566 { 0x0000, 0x0000, 0 }, /* R218 */ 567 { 0x0000, 0x0000, 0 }, /* R219 */ 568 { 0x0000, 0x0000, 0 }, /* R220 */ 569 { 0x0000, 0x0000, 0 }, /* R221 */ 570 { 0x0000, 0x0000, 0 }, /* R222 */ 571 { 0x0000, 0x0000, 0 }, /* R223 */ 572 { 0x0000, 0x0000, 0 }, /* R224 */ 573 { 0x0000, 0x0000, 0 }, /* R225 */ 574 { 0x0000, 0x0000, 0 }, /* R226 */ 575 { 0x0000, 0x0000, 0 }, /* R227 */ 576 { 0x0000, 0x0000, 0 }, /* R228 */ 577 { 0x0000, 0x0000, 0 }, /* R229 */ 578 { 0x0000, 0x0000, 0 }, /* R230 */ 579 { 0x0000, 0x0000, 0 }, /* R231 */ 580 { 0x0000, 0x0000, 0 }, /* R232 */ 581 { 0x0000, 0x0000, 0 }, /* R233 */ 582 { 0x0000, 0x0000, 0 }, /* R234 */ 583 { 0x0000, 0x0000, 0 }, /* R235 */ 584 { 0x0000, 0x0000, 0 }, /* R236 */ 585 { 0x0000, 0x0000, 0 }, /* R237 */ 586 { 0x0000, 0x0000, 0 }, /* R238 */ 587 { 0x0000, 0x0000, 0 }, /* R239 */ 588 { 0x0000, 0x0000, 0 }, /* R240 */ 589 { 0x0000, 0x0000, 0 }, /* R241 */ 590 { 0x0000, 0x0000, 0 }, /* R242 */ 591 { 0x0000, 0x0000, 0 }, /* R243 */ 592 { 0x0000, 0x0000, 0 }, /* R244 */ 593 { 0x0000, 0x0000, 0 }, /* R245 */ 594 { 0x0000, 0x0000, 0 }, /* R246 */ 595 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ 596 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ 597 }; 598 599 static int wm8904_volatile_register(unsigned int reg) 600 { 601 return wm8904_access[reg].vol; 602 } 603 604 static int wm8904_reset(struct snd_soc_codec *codec) 605 { 606 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); 607 } 608 609 static int wm8904_configure_clocking(struct snd_soc_codec *codec) 610 { 611 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 612 unsigned int clock0, clock2, rate; 613 614 /* Gate the clock while we're updating to avoid misclocking */ 615 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 616 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 617 WM8904_SYSCLK_SRC, 0); 618 619 /* This should be done on init() for bypass paths */ 620 switch (wm8904->sysclk_src) { 621 case WM8904_CLK_MCLK: 622 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 623 624 clock2 &= ~WM8904_SYSCLK_SRC; 625 rate = wm8904->mclk_rate; 626 627 /* Ensure the FLL is stopped */ 628 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 629 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 630 break; 631 632 case WM8904_CLK_FLL: 633 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 634 wm8904->fll_fout); 635 636 clock2 |= WM8904_SYSCLK_SRC; 637 rate = wm8904->fll_fout; 638 break; 639 640 default: 641 dev_err(codec->dev, "System clock not configured\n"); 642 return -EINVAL; 643 } 644 645 /* SYSCLK shouldn't be over 13.5MHz */ 646 if (rate > 13500000) { 647 clock0 = WM8904_MCLK_DIV; 648 wm8904->sysclk_rate = rate / 2; 649 } else { 650 clock0 = 0; 651 wm8904->sysclk_rate = rate; 652 } 653 654 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 655 clock0); 656 657 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 658 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 659 660 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 661 662 return 0; 663 } 664 665 static void wm8904_set_drc(struct snd_soc_codec *codec) 666 { 667 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 668 struct wm8904_pdata *pdata = wm8904->pdata; 669 int save, i; 670 671 /* Save any enables; the configuration should clear them. */ 672 save = snd_soc_read(codec, WM8904_DRC_0); 673 674 for (i = 0; i < WM8904_DRC_REGS; i++) 675 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, 676 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 677 678 /* Reenable the DRC */ 679 snd_soc_update_bits(codec, WM8904_DRC_0, 680 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 681 } 682 683 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 684 struct snd_ctl_elem_value *ucontrol) 685 { 686 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 687 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 688 struct wm8904_pdata *pdata = wm8904->pdata; 689 int value = ucontrol->value.integer.value[0]; 690 691 if (value >= pdata->num_drc_cfgs) 692 return -EINVAL; 693 694 wm8904->drc_cfg = value; 695 696 wm8904_set_drc(codec); 697 698 return 0; 699 } 700 701 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 702 struct snd_ctl_elem_value *ucontrol) 703 { 704 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 705 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 706 707 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 708 709 return 0; 710 } 711 712 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) 713 { 714 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 715 struct wm8904_pdata *pdata = wm8904->pdata; 716 int best, best_val, save, i, cfg; 717 718 if (!pdata || !wm8904->num_retune_mobile_texts) 719 return; 720 721 /* Find the version of the currently selected configuration 722 * with the nearest sample rate. */ 723 cfg = wm8904->retune_mobile_cfg; 724 best = 0; 725 best_val = INT_MAX; 726 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 727 if (strcmp(pdata->retune_mobile_cfgs[i].name, 728 wm8904->retune_mobile_texts[cfg]) == 0 && 729 abs(pdata->retune_mobile_cfgs[i].rate 730 - wm8904->fs) < best_val) { 731 best = i; 732 best_val = abs(pdata->retune_mobile_cfgs[i].rate 733 - wm8904->fs); 734 } 735 } 736 737 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 738 pdata->retune_mobile_cfgs[best].name, 739 pdata->retune_mobile_cfgs[best].rate, 740 wm8904->fs); 741 742 /* The EQ will be disabled while reconfiguring it, remember the 743 * current configuration. 744 */ 745 save = snd_soc_read(codec, WM8904_EQ1); 746 747 for (i = 0; i < WM8904_EQ_REGS; i++) 748 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, 749 pdata->retune_mobile_cfgs[best].regs[i]); 750 751 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); 752 } 753 754 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 755 struct snd_ctl_elem_value *ucontrol) 756 { 757 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 758 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 759 struct wm8904_pdata *pdata = wm8904->pdata; 760 int value = ucontrol->value.integer.value[0]; 761 762 if (value >= pdata->num_retune_mobile_cfgs) 763 return -EINVAL; 764 765 wm8904->retune_mobile_cfg = value; 766 767 wm8904_set_retune_mobile(codec); 768 769 return 0; 770 } 771 772 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 773 struct snd_ctl_elem_value *ucontrol) 774 { 775 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 776 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 777 778 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 779 780 return 0; 781 } 782 783 static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 784 785 static int wm8904_set_deemph(struct snd_soc_codec *codec) 786 { 787 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 788 int val, i, best; 789 790 /* If we're using deemphasis select the nearest available sample 791 * rate. 792 */ 793 if (wm8904->deemph) { 794 best = 1; 795 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 796 if (abs(deemph_settings[i] - wm8904->fs) < 797 abs(deemph_settings[best] - wm8904->fs)) 798 best = i; 799 } 800 801 val = best << WM8904_DEEMPH_SHIFT; 802 } else { 803 val = 0; 804 } 805 806 dev_dbg(codec->dev, "Set deemphasis %d\n", val); 807 808 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 809 WM8904_DEEMPH_MASK, val); 810 } 811 812 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 813 struct snd_ctl_elem_value *ucontrol) 814 { 815 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 816 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 817 818 ucontrol->value.enumerated.item[0] = wm8904->deemph; 819 return 0; 820 } 821 822 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 823 struct snd_ctl_elem_value *ucontrol) 824 { 825 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 826 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 827 int deemph = ucontrol->value.enumerated.item[0]; 828 829 if (deemph > 1) 830 return -EINVAL; 831 832 wm8904->deemph = deemph; 833 834 return wm8904_set_deemph(codec); 835 } 836 837 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 838 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 839 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 840 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 841 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 842 843 static const char *input_mode_text[] = { 844 "Single-Ended", "Differential Line", "Differential Mic" 845 }; 846 847 static const struct soc_enum lin_mode = 848 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 849 850 static const struct soc_enum rin_mode = 851 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 852 853 static const char *hpf_mode_text[] = { 854 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 855 }; 856 857 static const struct soc_enum hpf_mode = 858 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 859 860 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 861 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 862 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 863 864 SOC_ENUM("Left Caputure Mode", lin_mode), 865 SOC_ENUM("Right Capture Mode", rin_mode), 866 867 /* No TLV since it depends on mode */ 868 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 869 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 870 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 871 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), 872 873 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 874 SOC_ENUM("High Pass Filter Mode", hpf_mode), 875 876 SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), 877 }; 878 879 static const char *drc_path_text[] = { 880 "ADC", "DAC" 881 }; 882 883 static const struct soc_enum drc_path = 884 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); 885 886 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 887 SOC_SINGLE_TLV("Digital Playback Boost Volume", 888 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 889 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 890 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 891 892 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 893 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 894 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 895 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 896 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 897 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 898 899 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 900 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 901 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 902 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 903 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 904 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 905 906 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 907 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 908 SOC_ENUM("DRC Path", drc_path), 909 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 910 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 911 wm8904_get_deemph, wm8904_put_deemph), 912 }; 913 914 static const struct snd_kcontrol_new wm8904_snd_controls[] = { 915 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 916 sidetone_tlv), 917 }; 918 919 static const struct snd_kcontrol_new wm8904_eq_controls[] = { 920 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 921 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 922 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 923 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 924 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 925 }; 926 927 static int cp_event(struct snd_soc_dapm_widget *w, 928 struct snd_kcontrol *kcontrol, int event) 929 { 930 BUG_ON(event != SND_SOC_DAPM_POST_PMU); 931 932 /* Maximum startup time */ 933 udelay(500); 934 935 return 0; 936 } 937 938 static int sysclk_event(struct snd_soc_dapm_widget *w, 939 struct snd_kcontrol *kcontrol, int event) 940 { 941 struct snd_soc_codec *codec = w->codec; 942 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 943 944 switch (event) { 945 case SND_SOC_DAPM_PRE_PMU: 946 /* If we're using the FLL then we only start it when 947 * required; we assume that the configuration has been 948 * done previously and all we need to do is kick it 949 * off. 950 */ 951 switch (wm8904->sysclk_src) { 952 case WM8904_CLK_FLL: 953 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 954 WM8904_FLL_OSC_ENA, 955 WM8904_FLL_OSC_ENA); 956 957 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 958 WM8904_FLL_ENA, 959 WM8904_FLL_ENA); 960 break; 961 962 default: 963 break; 964 } 965 break; 966 967 case SND_SOC_DAPM_POST_PMD: 968 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 969 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 970 break; 971 } 972 973 return 0; 974 } 975 976 static int out_pga_event(struct snd_soc_dapm_widget *w, 977 struct snd_kcontrol *kcontrol, int event) 978 { 979 struct snd_soc_codec *codec = w->codec; 980 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 981 int reg, val; 982 int dcs_mask; 983 int dcs_l, dcs_r; 984 int dcs_l_reg, dcs_r_reg; 985 int timeout; 986 int pwr_reg; 987 988 /* This code is shared between HP and LINEOUT; we do all our 989 * power management in stereo pairs to avoid latency issues so 990 * we reuse shift to identify which rather than strcmp() the 991 * name. */ 992 reg = w->shift; 993 994 switch (reg) { 995 case WM8904_ANALOGUE_HP_0: 996 pwr_reg = WM8904_POWER_MANAGEMENT_2; 997 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 998 dcs_r_reg = WM8904_DC_SERVO_8; 999 dcs_l_reg = WM8904_DC_SERVO_9; 1000 dcs_l = 0; 1001 dcs_r = 1; 1002 break; 1003 case WM8904_ANALOGUE_LINEOUT_0: 1004 pwr_reg = WM8904_POWER_MANAGEMENT_3; 1005 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 1006 dcs_r_reg = WM8904_DC_SERVO_6; 1007 dcs_l_reg = WM8904_DC_SERVO_7; 1008 dcs_l = 2; 1009 dcs_r = 3; 1010 break; 1011 default: 1012 BUG(); 1013 return -EINVAL; 1014 } 1015 1016 switch (event) { 1017 case SND_SOC_DAPM_PRE_PMU: 1018 /* Power on the PGAs */ 1019 snd_soc_update_bits(codec, pwr_reg, 1020 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1021 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 1022 1023 /* Power on the amplifier */ 1024 snd_soc_update_bits(codec, reg, 1025 WM8904_HPL_ENA | WM8904_HPR_ENA, 1026 WM8904_HPL_ENA | WM8904_HPR_ENA); 1027 1028 1029 /* Enable the first stage */ 1030 snd_soc_update_bits(codec, reg, 1031 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 1032 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 1033 1034 /* Power up the DC servo */ 1035 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1036 dcs_mask, dcs_mask); 1037 1038 /* Either calibrate the DC servo or restore cached state 1039 * if we have that. 1040 */ 1041 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 1042 dev_dbg(codec->dev, "Restoring DC servo state\n"); 1043 1044 snd_soc_write(codec, dcs_l_reg, 1045 wm8904->dcs_state[dcs_l]); 1046 snd_soc_write(codec, dcs_r_reg, 1047 wm8904->dcs_state[dcs_r]); 1048 1049 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); 1050 1051 timeout = 20; 1052 } else { 1053 dev_dbg(codec->dev, "Calibrating DC servo\n"); 1054 1055 snd_soc_write(codec, WM8904_DC_SERVO_1, 1056 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 1057 1058 timeout = 500; 1059 } 1060 1061 /* Wait for DC servo to complete */ 1062 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 1063 do { 1064 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); 1065 if ((val & dcs_mask) == dcs_mask) 1066 break; 1067 1068 msleep(1); 1069 } while (--timeout); 1070 1071 if ((val & dcs_mask) != dcs_mask) 1072 dev_warn(codec->dev, "DC servo timed out\n"); 1073 else 1074 dev_dbg(codec->dev, "DC servo ready\n"); 1075 1076 /* Enable the output stage */ 1077 snd_soc_update_bits(codec, reg, 1078 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1079 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 1080 break; 1081 1082 case SND_SOC_DAPM_POST_PMU: 1083 /* Unshort the output itself */ 1084 snd_soc_update_bits(codec, reg, 1085 WM8904_HPL_RMV_SHORT | 1086 WM8904_HPR_RMV_SHORT, 1087 WM8904_HPL_RMV_SHORT | 1088 WM8904_HPR_RMV_SHORT); 1089 1090 break; 1091 1092 case SND_SOC_DAPM_PRE_PMD: 1093 /* Short the output */ 1094 snd_soc_update_bits(codec, reg, 1095 WM8904_HPL_RMV_SHORT | 1096 WM8904_HPR_RMV_SHORT, 0); 1097 break; 1098 1099 case SND_SOC_DAPM_POST_PMD: 1100 /* Cache the DC servo configuration; this will be 1101 * invalidated if we change the configuration. */ 1102 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); 1103 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); 1104 1105 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1106 dcs_mask, 0); 1107 1108 /* Disable the amplifier input and output stages */ 1109 snd_soc_update_bits(codec, reg, 1110 WM8904_HPL_ENA | WM8904_HPR_ENA | 1111 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 1112 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1113 0); 1114 1115 /* PGAs too */ 1116 snd_soc_update_bits(codec, pwr_reg, 1117 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1118 0); 1119 break; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static const char *lin_text[] = { 1126 "IN1L", "IN2L", "IN3L" 1127 }; 1128 1129 static const struct soc_enum lin_enum = 1130 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); 1131 1132 static const struct snd_kcontrol_new lin_mux = 1133 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 1134 1135 static const struct soc_enum lin_inv_enum = 1136 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); 1137 1138 static const struct snd_kcontrol_new lin_inv_mux = 1139 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 1140 1141 static const char *rin_text[] = { 1142 "IN1R", "IN2R", "IN3R" 1143 }; 1144 1145 static const struct soc_enum rin_enum = 1146 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); 1147 1148 static const struct snd_kcontrol_new rin_mux = 1149 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 1150 1151 static const struct soc_enum rin_inv_enum = 1152 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); 1153 1154 static const struct snd_kcontrol_new rin_inv_mux = 1155 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 1156 1157 static const char *aif_text[] = { 1158 "Left", "Right" 1159 }; 1160 1161 static const struct soc_enum aifoutl_enum = 1162 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); 1163 1164 static const struct snd_kcontrol_new aifoutl_mux = 1165 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 1166 1167 static const struct soc_enum aifoutr_enum = 1168 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); 1169 1170 static const struct snd_kcontrol_new aifoutr_mux = 1171 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 1172 1173 static const struct soc_enum aifinl_enum = 1174 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); 1175 1176 static const struct snd_kcontrol_new aifinl_mux = 1177 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 1178 1179 static const struct soc_enum aifinr_enum = 1180 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); 1181 1182 static const struct snd_kcontrol_new aifinr_mux = 1183 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 1184 1185 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 1186 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 1187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1188 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 1189 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 1190 }; 1191 1192 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 1193 SND_SOC_DAPM_INPUT("IN1L"), 1194 SND_SOC_DAPM_INPUT("IN1R"), 1195 SND_SOC_DAPM_INPUT("IN2L"), 1196 SND_SOC_DAPM_INPUT("IN2R"), 1197 SND_SOC_DAPM_INPUT("IN3L"), 1198 SND_SOC_DAPM_INPUT("IN3R"), 1199 1200 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), 1201 1202 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 1203 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1204 &lin_inv_mux), 1205 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 1206 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1207 &rin_inv_mux), 1208 1209 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 1210 NULL, 0), 1211 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 1212 NULL, 0), 1213 1214 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 1215 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 1216 1217 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 1218 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 1219 1220 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 1221 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 1222 }; 1223 1224 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 1225 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 1226 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 1227 1228 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 1229 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 1230 1231 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 1232 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 1233 1234 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 1235 SND_SOC_DAPM_POST_PMU), 1236 1237 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1238 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1239 1240 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1241 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1242 1243 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 1244 0, NULL, 0, out_pga_event, 1245 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1246 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1247 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 1248 0, NULL, 0, out_pga_event, 1249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1250 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1251 1252 SND_SOC_DAPM_OUTPUT("HPOUTL"), 1253 SND_SOC_DAPM_OUTPUT("HPOUTR"), 1254 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 1255 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 1256 }; 1257 1258 static const char *out_mux_text[] = { 1259 "DAC", "Bypass" 1260 }; 1261 1262 static const struct soc_enum hpl_enum = 1263 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); 1264 1265 static const struct snd_kcontrol_new hpl_mux = 1266 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1267 1268 static const struct soc_enum hpr_enum = 1269 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); 1270 1271 static const struct snd_kcontrol_new hpr_mux = 1272 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1273 1274 static const struct soc_enum linel_enum = 1275 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); 1276 1277 static const struct snd_kcontrol_new linel_mux = 1278 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1279 1280 static const struct soc_enum liner_enum = 1281 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); 1282 1283 static const struct snd_kcontrol_new liner_mux = 1284 SOC_DAPM_ENUM("LINEL Mux", liner_enum); 1285 1286 static const char *sidetone_text[] = { 1287 "None", "Left", "Right" 1288 }; 1289 1290 static const struct soc_enum dacl_sidetone_enum = 1291 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); 1292 1293 static const struct snd_kcontrol_new dacl_sidetone_mux = 1294 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1295 1296 static const struct soc_enum dacr_sidetone_enum = 1297 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); 1298 1299 static const struct snd_kcontrol_new dacr_sidetone_mux = 1300 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1301 1302 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1303 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1304 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1305 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1306 1307 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1308 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1309 1310 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1311 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1312 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1313 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1314 }; 1315 1316 static const struct snd_soc_dapm_route core_intercon[] = { 1317 { "CLK_DSP", NULL, "SYSCLK" }, 1318 { "TOCLK", NULL, "SYSCLK" }, 1319 }; 1320 1321 static const struct snd_soc_dapm_route adc_intercon[] = { 1322 { "Left Capture Mux", "IN1L", "IN1L" }, 1323 { "Left Capture Mux", "IN2L", "IN2L" }, 1324 { "Left Capture Mux", "IN3L", "IN3L" }, 1325 1326 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1327 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1328 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1329 1330 { "Right Capture Mux", "IN1R", "IN1R" }, 1331 { "Right Capture Mux", "IN2R", "IN2R" }, 1332 { "Right Capture Mux", "IN3R", "IN3R" }, 1333 1334 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1335 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1336 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1337 1338 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1339 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1340 1341 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1342 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1343 1344 { "AIFOUTL", "Left", "ADCL" }, 1345 { "AIFOUTL", "Right", "ADCR" }, 1346 { "AIFOUTR", "Left", "ADCL" }, 1347 { "AIFOUTR", "Right", "ADCR" }, 1348 1349 { "ADCL", NULL, "CLK_DSP" }, 1350 { "ADCL", NULL, "Left Capture PGA" }, 1351 1352 { "ADCR", NULL, "CLK_DSP" }, 1353 { "ADCR", NULL, "Right Capture PGA" }, 1354 }; 1355 1356 static const struct snd_soc_dapm_route dac_intercon[] = { 1357 { "DACL", "Right", "AIFINR" }, 1358 { "DACL", "Left", "AIFINL" }, 1359 { "DACL", NULL, "CLK_DSP" }, 1360 1361 { "DACR", "Right", "AIFINR" }, 1362 { "DACR", "Left", "AIFINL" }, 1363 { "DACR", NULL, "CLK_DSP" }, 1364 1365 { "Charge pump", NULL, "SYSCLK" }, 1366 1367 { "Headphone Output", NULL, "HPL PGA" }, 1368 { "Headphone Output", NULL, "HPR PGA" }, 1369 { "Headphone Output", NULL, "Charge pump" }, 1370 { "Headphone Output", NULL, "TOCLK" }, 1371 1372 { "Line Output", NULL, "LINEL PGA" }, 1373 { "Line Output", NULL, "LINER PGA" }, 1374 { "Line Output", NULL, "Charge pump" }, 1375 { "Line Output", NULL, "TOCLK" }, 1376 1377 { "HPOUTL", NULL, "Headphone Output" }, 1378 { "HPOUTR", NULL, "Headphone Output" }, 1379 1380 { "LINEOUTL", NULL, "Line Output" }, 1381 { "LINEOUTR", NULL, "Line Output" }, 1382 }; 1383 1384 static const struct snd_soc_dapm_route wm8904_intercon[] = { 1385 { "Left Sidetone", "Left", "ADCL" }, 1386 { "Left Sidetone", "Right", "ADCR" }, 1387 { "DACL", NULL, "Left Sidetone" }, 1388 1389 { "Right Sidetone", "Left", "ADCL" }, 1390 { "Right Sidetone", "Right", "ADCR" }, 1391 { "DACR", NULL, "Right Sidetone" }, 1392 1393 { "Left Bypass", NULL, "Class G" }, 1394 { "Left Bypass", NULL, "Left Capture PGA" }, 1395 1396 { "Right Bypass", NULL, "Class G" }, 1397 { "Right Bypass", NULL, "Right Capture PGA" }, 1398 1399 { "HPL Mux", "DAC", "DACL" }, 1400 { "HPL Mux", "Bypass", "Left Bypass" }, 1401 1402 { "HPR Mux", "DAC", "DACR" }, 1403 { "HPR Mux", "Bypass", "Right Bypass" }, 1404 1405 { "LINEL Mux", "DAC", "DACL" }, 1406 { "LINEL Mux", "Bypass", "Left Bypass" }, 1407 1408 { "LINER Mux", "DAC", "DACR" }, 1409 { "LINER Mux", "Bypass", "Right Bypass" }, 1410 1411 { "HPL PGA", NULL, "HPL Mux" }, 1412 { "HPR PGA", NULL, "HPR Mux" }, 1413 1414 { "LINEL PGA", NULL, "LINEL Mux" }, 1415 { "LINER PGA", NULL, "LINER Mux" }, 1416 }; 1417 1418 static const struct snd_soc_dapm_route wm8912_intercon[] = { 1419 { "HPL PGA", NULL, "DACL" }, 1420 { "HPR PGA", NULL, "DACR" }, 1421 1422 { "LINEL PGA", NULL, "DACL" }, 1423 { "LINER PGA", NULL, "DACR" }, 1424 }; 1425 1426 static int wm8904_add_widgets(struct snd_soc_codec *codec) 1427 { 1428 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1429 struct snd_soc_dapm_context *dapm = &codec->dapm; 1430 1431 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, 1432 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1433 snd_soc_dapm_add_routes(dapm, core_intercon, 1434 ARRAY_SIZE(core_intercon)); 1435 1436 switch (wm8904->devtype) { 1437 case WM8904: 1438 snd_soc_add_controls(codec, wm8904_adc_snd_controls, 1439 ARRAY_SIZE(wm8904_adc_snd_controls)); 1440 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1441 ARRAY_SIZE(wm8904_dac_snd_controls)); 1442 snd_soc_add_controls(codec, wm8904_snd_controls, 1443 ARRAY_SIZE(wm8904_snd_controls)); 1444 1445 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, 1446 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1447 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1448 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1449 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, 1450 ARRAY_SIZE(wm8904_dapm_widgets)); 1451 1452 snd_soc_dapm_add_routes(dapm, core_intercon, 1453 ARRAY_SIZE(core_intercon)); 1454 snd_soc_dapm_add_routes(dapm, adc_intercon, 1455 ARRAY_SIZE(adc_intercon)); 1456 snd_soc_dapm_add_routes(dapm, dac_intercon, 1457 ARRAY_SIZE(dac_intercon)); 1458 snd_soc_dapm_add_routes(dapm, wm8904_intercon, 1459 ARRAY_SIZE(wm8904_intercon)); 1460 break; 1461 1462 case WM8912: 1463 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1464 ARRAY_SIZE(wm8904_dac_snd_controls)); 1465 1466 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1467 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1468 1469 snd_soc_dapm_add_routes(dapm, dac_intercon, 1470 ARRAY_SIZE(dac_intercon)); 1471 snd_soc_dapm_add_routes(dapm, wm8912_intercon, 1472 ARRAY_SIZE(wm8912_intercon)); 1473 break; 1474 } 1475 1476 snd_soc_dapm_new_widgets(dapm); 1477 return 0; 1478 } 1479 1480 static struct { 1481 int ratio; 1482 unsigned int clk_sys_rate; 1483 } clk_sys_rates[] = { 1484 { 64, 0 }, 1485 { 128, 1 }, 1486 { 192, 2 }, 1487 { 256, 3 }, 1488 { 384, 4 }, 1489 { 512, 5 }, 1490 { 786, 6 }, 1491 { 1024, 7 }, 1492 { 1408, 8 }, 1493 { 1536, 9 }, 1494 }; 1495 1496 static struct { 1497 int rate; 1498 int sample_rate; 1499 } sample_rates[] = { 1500 { 8000, 0 }, 1501 { 11025, 1 }, 1502 { 12000, 1 }, 1503 { 16000, 2 }, 1504 { 22050, 3 }, 1505 { 24000, 3 }, 1506 { 32000, 4 }, 1507 { 44100, 5 }, 1508 { 48000, 5 }, 1509 }; 1510 1511 static struct { 1512 int div; /* *10 due to .5s */ 1513 int bclk_div; 1514 } bclk_divs[] = { 1515 { 10, 0 }, 1516 { 15, 1 }, 1517 { 20, 2 }, 1518 { 30, 3 }, 1519 { 40, 4 }, 1520 { 50, 5 }, 1521 { 55, 6 }, 1522 { 60, 7 }, 1523 { 80, 8 }, 1524 { 100, 9 }, 1525 { 110, 10 }, 1526 { 120, 11 }, 1527 { 160, 12 }, 1528 { 200, 13 }, 1529 { 220, 14 }, 1530 { 240, 16 }, 1531 { 200, 17 }, 1532 { 320, 18 }, 1533 { 440, 19 }, 1534 { 480, 20 }, 1535 }; 1536 1537 1538 static int wm8904_hw_params(struct snd_pcm_substream *substream, 1539 struct snd_pcm_hw_params *params, 1540 struct snd_soc_dai *dai) 1541 { 1542 struct snd_soc_codec *codec = dai->codec; 1543 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1544 int ret, i, best, best_val, cur_val; 1545 unsigned int aif1 = 0; 1546 unsigned int aif2 = 0; 1547 unsigned int aif3 = 0; 1548 unsigned int clock1 = 0; 1549 unsigned int dac_digital1 = 0; 1550 1551 /* What BCLK do we need? */ 1552 wm8904->fs = params_rate(params); 1553 if (wm8904->tdm_slots) { 1554 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1555 wm8904->tdm_slots, wm8904->tdm_width); 1556 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1557 wm8904->tdm_width, 2, 1558 wm8904->tdm_slots); 1559 } else { 1560 wm8904->bclk = snd_soc_params_to_bclk(params); 1561 } 1562 1563 switch (params_format(params)) { 1564 case SNDRV_PCM_FORMAT_S16_LE: 1565 break; 1566 case SNDRV_PCM_FORMAT_S20_3LE: 1567 aif1 |= 0x40; 1568 break; 1569 case SNDRV_PCM_FORMAT_S24_LE: 1570 aif1 |= 0x80; 1571 break; 1572 case SNDRV_PCM_FORMAT_S32_LE: 1573 aif1 |= 0xc0; 1574 break; 1575 default: 1576 return -EINVAL; 1577 } 1578 1579 1580 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1581 1582 ret = wm8904_configure_clocking(codec); 1583 if (ret != 0) 1584 return ret; 1585 1586 /* Select nearest CLK_SYS_RATE */ 1587 best = 0; 1588 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1589 - wm8904->fs); 1590 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1591 cur_val = abs((wm8904->sysclk_rate / 1592 clk_sys_rates[i].ratio) - wm8904->fs); 1593 if (cur_val < best_val) { 1594 best = i; 1595 best_val = cur_val; 1596 } 1597 } 1598 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1599 clk_sys_rates[best].ratio); 1600 clock1 |= (clk_sys_rates[best].clk_sys_rate 1601 << WM8904_CLK_SYS_RATE_SHIFT); 1602 1603 /* SAMPLE_RATE */ 1604 best = 0; 1605 best_val = abs(wm8904->fs - sample_rates[0].rate); 1606 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1607 /* Closest match */ 1608 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1609 if (cur_val < best_val) { 1610 best = i; 1611 best_val = cur_val; 1612 } 1613 } 1614 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1615 sample_rates[best].rate); 1616 clock1 |= (sample_rates[best].sample_rate 1617 << WM8904_SAMPLE_RATE_SHIFT); 1618 1619 /* Enable sloping stopband filter for low sample rates */ 1620 if (wm8904->fs <= 24000) 1621 dac_digital1 |= WM8904_DAC_SB_FILT; 1622 1623 /* BCLK_DIV */ 1624 best = 0; 1625 best_val = INT_MAX; 1626 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1627 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1628 - wm8904->bclk; 1629 if (cur_val < 0) /* Table is sorted */ 1630 break; 1631 if (cur_val < best_val) { 1632 best = i; 1633 best_val = cur_val; 1634 } 1635 } 1636 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1637 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1638 bclk_divs[best].div, wm8904->bclk); 1639 aif2 |= bclk_divs[best].bclk_div; 1640 1641 /* LRCLK is a simple fraction of BCLK */ 1642 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1643 aif3 |= wm8904->bclk / wm8904->fs; 1644 1645 /* Apply the settings */ 1646 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 1647 WM8904_DAC_SB_FILT, dac_digital1); 1648 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1649 WM8904_AIF_WL_MASK, aif1); 1650 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, 1651 WM8904_BCLK_DIV_MASK, aif2); 1652 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1653 WM8904_LRCLK_RATE_MASK, aif3); 1654 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, 1655 WM8904_SAMPLE_RATE_MASK | 1656 WM8904_CLK_SYS_RATE_MASK, clock1); 1657 1658 /* Update filters for the new settings */ 1659 wm8904_set_retune_mobile(codec); 1660 wm8904_set_deemph(codec); 1661 1662 return 0; 1663 } 1664 1665 1666 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1667 unsigned int freq, int dir) 1668 { 1669 struct snd_soc_codec *codec = dai->codec; 1670 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); 1671 1672 switch (clk_id) { 1673 case WM8904_CLK_MCLK: 1674 priv->sysclk_src = clk_id; 1675 priv->mclk_rate = freq; 1676 break; 1677 1678 case WM8904_CLK_FLL: 1679 priv->sysclk_src = clk_id; 1680 break; 1681 1682 default: 1683 return -EINVAL; 1684 } 1685 1686 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1687 1688 wm8904_configure_clocking(codec); 1689 1690 return 0; 1691 } 1692 1693 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1694 { 1695 struct snd_soc_codec *codec = dai->codec; 1696 unsigned int aif1 = 0; 1697 unsigned int aif3 = 0; 1698 1699 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1700 case SND_SOC_DAIFMT_CBS_CFS: 1701 break; 1702 case SND_SOC_DAIFMT_CBS_CFM: 1703 aif3 |= WM8904_LRCLK_DIR; 1704 break; 1705 case SND_SOC_DAIFMT_CBM_CFS: 1706 aif1 |= WM8904_BCLK_DIR; 1707 break; 1708 case SND_SOC_DAIFMT_CBM_CFM: 1709 aif1 |= WM8904_BCLK_DIR; 1710 aif3 |= WM8904_LRCLK_DIR; 1711 break; 1712 default: 1713 return -EINVAL; 1714 } 1715 1716 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1717 case SND_SOC_DAIFMT_DSP_B: 1718 aif1 |= WM8904_AIF_LRCLK_INV; 1719 case SND_SOC_DAIFMT_DSP_A: 1720 aif1 |= 0x3; 1721 break; 1722 case SND_SOC_DAIFMT_I2S: 1723 aif1 |= 0x2; 1724 break; 1725 case SND_SOC_DAIFMT_RIGHT_J: 1726 break; 1727 case SND_SOC_DAIFMT_LEFT_J: 1728 aif1 |= 0x1; 1729 break; 1730 default: 1731 return -EINVAL; 1732 } 1733 1734 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1735 case SND_SOC_DAIFMT_DSP_A: 1736 case SND_SOC_DAIFMT_DSP_B: 1737 /* frame inversion not valid for DSP modes */ 1738 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1739 case SND_SOC_DAIFMT_NB_NF: 1740 break; 1741 case SND_SOC_DAIFMT_IB_NF: 1742 aif1 |= WM8904_AIF_BCLK_INV; 1743 break; 1744 default: 1745 return -EINVAL; 1746 } 1747 break; 1748 1749 case SND_SOC_DAIFMT_I2S: 1750 case SND_SOC_DAIFMT_RIGHT_J: 1751 case SND_SOC_DAIFMT_LEFT_J: 1752 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1753 case SND_SOC_DAIFMT_NB_NF: 1754 break; 1755 case SND_SOC_DAIFMT_IB_IF: 1756 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1757 break; 1758 case SND_SOC_DAIFMT_IB_NF: 1759 aif1 |= WM8904_AIF_BCLK_INV; 1760 break; 1761 case SND_SOC_DAIFMT_NB_IF: 1762 aif1 |= WM8904_AIF_LRCLK_INV; 1763 break; 1764 default: 1765 return -EINVAL; 1766 } 1767 break; 1768 default: 1769 return -EINVAL; 1770 } 1771 1772 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1773 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1774 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1775 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1776 WM8904_LRCLK_DIR, aif3); 1777 1778 return 0; 1779 } 1780 1781 1782 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1783 unsigned int rx_mask, int slots, int slot_width) 1784 { 1785 struct snd_soc_codec *codec = dai->codec; 1786 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1787 int aif1 = 0; 1788 1789 /* Don't need to validate anything if we're turning off TDM */ 1790 if (slots == 0) 1791 goto out; 1792 1793 /* Note that we allow configurations we can't handle ourselves - 1794 * for example, we can generate clocks for slots 2 and up even if 1795 * we can't use those slots ourselves. 1796 */ 1797 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1798 1799 switch (rx_mask) { 1800 case 3: 1801 break; 1802 case 0xc: 1803 aif1 |= WM8904_AIFADC_TDM_CHAN; 1804 break; 1805 default: 1806 return -EINVAL; 1807 } 1808 1809 1810 switch (tx_mask) { 1811 case 3: 1812 break; 1813 case 0xc: 1814 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1815 break; 1816 default: 1817 return -EINVAL; 1818 } 1819 1820 out: 1821 wm8904->tdm_width = slot_width; 1822 wm8904->tdm_slots = slots / 2; 1823 1824 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1825 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1826 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1827 1828 return 0; 1829 } 1830 1831 struct _fll_div { 1832 u16 fll_fratio; 1833 u16 fll_outdiv; 1834 u16 fll_clk_ref_div; 1835 u16 n; 1836 u16 k; 1837 }; 1838 1839 /* The size in bits of the FLL divide multiplied by 10 1840 * to allow rounding later */ 1841 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1842 1843 static struct { 1844 unsigned int min; 1845 unsigned int max; 1846 u16 fll_fratio; 1847 int ratio; 1848 } fll_fratios[] = { 1849 { 0, 64000, 4, 16 }, 1850 { 64000, 128000, 3, 8 }, 1851 { 128000, 256000, 2, 4 }, 1852 { 256000, 1000000, 1, 2 }, 1853 { 1000000, 13500000, 0, 1 }, 1854 }; 1855 1856 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1857 unsigned int Fout) 1858 { 1859 u64 Kpart; 1860 unsigned int K, Ndiv, Nmod, target; 1861 unsigned int div; 1862 int i; 1863 1864 /* Fref must be <=13.5MHz */ 1865 div = 1; 1866 fll_div->fll_clk_ref_div = 0; 1867 while ((Fref / div) > 13500000) { 1868 div *= 2; 1869 fll_div->fll_clk_ref_div++; 1870 1871 if (div > 8) { 1872 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1873 Fref); 1874 return -EINVAL; 1875 } 1876 } 1877 1878 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1879 1880 /* Apply the division for our remaining calculations */ 1881 Fref /= div; 1882 1883 /* Fvco should be 90-100MHz; don't check the upper bound */ 1884 div = 4; 1885 while (Fout * div < 90000000) { 1886 div++; 1887 if (div > 64) { 1888 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1889 Fout); 1890 return -EINVAL; 1891 } 1892 } 1893 target = Fout * div; 1894 fll_div->fll_outdiv = div - 1; 1895 1896 pr_debug("Fvco=%dHz\n", target); 1897 1898 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1899 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1900 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1901 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1902 target /= fll_fratios[i].ratio; 1903 break; 1904 } 1905 } 1906 if (i == ARRAY_SIZE(fll_fratios)) { 1907 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1908 return -EINVAL; 1909 } 1910 1911 /* Now, calculate N.K */ 1912 Ndiv = target / Fref; 1913 1914 fll_div->n = Ndiv; 1915 Nmod = target % Fref; 1916 pr_debug("Nmod=%d\n", Nmod); 1917 1918 /* Calculate fractional part - scale up so we can round. */ 1919 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1920 1921 do_div(Kpart, Fref); 1922 1923 K = Kpart & 0xFFFFFFFF; 1924 1925 if ((K % 10) >= 5) 1926 K += 5; 1927 1928 /* Move down to proper range now rounding is done */ 1929 fll_div->k = K / 10; 1930 1931 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1932 fll_div->n, fll_div->k, 1933 fll_div->fll_fratio, fll_div->fll_outdiv, 1934 fll_div->fll_clk_ref_div); 1935 1936 return 0; 1937 } 1938 1939 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1940 unsigned int Fref, unsigned int Fout) 1941 { 1942 struct snd_soc_codec *codec = dai->codec; 1943 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1944 struct _fll_div fll_div; 1945 int ret, val; 1946 int clock2, fll1; 1947 1948 /* Any change? */ 1949 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1950 Fout == wm8904->fll_fout) 1951 return 0; 1952 1953 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 1954 1955 if (Fout == 0) { 1956 dev_dbg(codec->dev, "FLL disabled\n"); 1957 1958 wm8904->fll_fref = 0; 1959 wm8904->fll_fout = 0; 1960 1961 /* Gate SYSCLK to avoid glitches */ 1962 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 1963 WM8904_CLK_SYS_ENA, 0); 1964 1965 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 1966 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1967 1968 goto out; 1969 } 1970 1971 /* Validate the FLL ID */ 1972 switch (source) { 1973 case WM8904_FLL_MCLK: 1974 case WM8904_FLL_LRCLK: 1975 case WM8904_FLL_BCLK: 1976 ret = fll_factors(&fll_div, Fref, Fout); 1977 if (ret != 0) 1978 return ret; 1979 break; 1980 1981 case WM8904_FLL_FREE_RUNNING: 1982 dev_dbg(codec->dev, "Using free running FLL\n"); 1983 /* Force 12MHz and output/4 for now */ 1984 Fout = 12000000; 1985 Fref = 12000000; 1986 1987 memset(&fll_div, 0, sizeof(fll_div)); 1988 fll_div.fll_outdiv = 3; 1989 break; 1990 1991 default: 1992 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 1993 return -EINVAL; 1994 } 1995 1996 /* Save current state then disable the FLL and SYSCLK to avoid 1997 * misclocking */ 1998 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); 1999 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2000 WM8904_CLK_SYS_ENA, 0); 2001 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2002 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 2003 2004 /* Unlock forced oscilator control to switch it on/off */ 2005 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2006 WM8904_USER_KEY, WM8904_USER_KEY); 2007 2008 if (fll_id == WM8904_FLL_FREE_RUNNING) { 2009 val = WM8904_FLL_FRC_NCO; 2010 } else { 2011 val = 0; 2012 } 2013 2014 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 2015 val); 2016 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2017 WM8904_USER_KEY, 0); 2018 2019 switch (fll_id) { 2020 case WM8904_FLL_MCLK: 2021 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2022 WM8904_FLL_CLK_REF_SRC_MASK, 0); 2023 break; 2024 2025 case WM8904_FLL_LRCLK: 2026 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2027 WM8904_FLL_CLK_REF_SRC_MASK, 1); 2028 break; 2029 2030 case WM8904_FLL_BCLK: 2031 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2032 WM8904_FLL_CLK_REF_SRC_MASK, 2); 2033 break; 2034 } 2035 2036 if (fll_div.k) 2037 val = WM8904_FLL_FRACN_ENA; 2038 else 2039 val = 0; 2040 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2041 WM8904_FLL_FRACN_ENA, val); 2042 2043 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, 2044 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 2045 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 2046 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 2047 2048 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); 2049 2050 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 2051 fll_div.n << WM8904_FLL_N_SHIFT); 2052 2053 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2054 WM8904_FLL_CLK_REF_DIV_MASK, 2055 fll_div.fll_clk_ref_div 2056 << WM8904_FLL_CLK_REF_DIV_SHIFT); 2057 2058 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2059 2060 wm8904->fll_fref = Fref; 2061 wm8904->fll_fout = Fout; 2062 wm8904->fll_src = source; 2063 2064 /* Enable the FLL if it was previously active */ 2065 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2066 WM8904_FLL_OSC_ENA, fll1); 2067 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2068 WM8904_FLL_ENA, fll1); 2069 2070 out: 2071 /* Reenable SYSCLK if it was previously active */ 2072 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2073 WM8904_CLK_SYS_ENA, clock2); 2074 2075 return 0; 2076 } 2077 2078 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 2079 { 2080 struct snd_soc_codec *codec = codec_dai->codec; 2081 int val; 2082 2083 if (mute) 2084 val = WM8904_DAC_MUTE; 2085 else 2086 val = 0; 2087 2088 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 2089 2090 return 0; 2091 } 2092 2093 static void wm8904_sync_cache(struct snd_soc_codec *codec) 2094 { 2095 u16 *reg_cache = codec->reg_cache; 2096 int i; 2097 2098 if (!codec->cache_sync) 2099 return; 2100 2101 codec->cache_only = 0; 2102 2103 /* Sync back cached values if they're different from the 2104 * hardware default. 2105 */ 2106 for (i = 1; i < codec->driver->reg_cache_size; i++) { 2107 if (!wm8904_access[i].writable) 2108 continue; 2109 2110 if (reg_cache[i] == wm8904_reg[i]) 2111 continue; 2112 2113 snd_soc_write(codec, i, reg_cache[i]); 2114 } 2115 2116 codec->cache_sync = 0; 2117 } 2118 2119 static int wm8904_set_bias_level(struct snd_soc_codec *codec, 2120 enum snd_soc_bias_level level) 2121 { 2122 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2123 int ret; 2124 2125 switch (level) { 2126 case SND_SOC_BIAS_ON: 2127 break; 2128 2129 case SND_SOC_BIAS_PREPARE: 2130 /* VMID resistance 2*50k */ 2131 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2132 WM8904_VMID_RES_MASK, 2133 0x1 << WM8904_VMID_RES_SHIFT); 2134 2135 /* Normal bias current */ 2136 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2137 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 2138 break; 2139 2140 case SND_SOC_BIAS_STANDBY: 2141 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2142 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2143 wm8904->supplies); 2144 if (ret != 0) { 2145 dev_err(codec->dev, 2146 "Failed to enable supplies: %d\n", 2147 ret); 2148 return ret; 2149 } 2150 2151 wm8904_sync_cache(codec); 2152 2153 /* Enable bias */ 2154 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2155 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 2156 2157 /* Enable VMID, VMID buffering, 2*5k resistance */ 2158 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2159 WM8904_VMID_ENA | 2160 WM8904_VMID_RES_MASK, 2161 WM8904_VMID_ENA | 2162 0x3 << WM8904_VMID_RES_SHIFT); 2163 2164 /* Let VMID ramp */ 2165 msleep(1); 2166 } 2167 2168 /* Maintain VMID with 2*250k */ 2169 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2170 WM8904_VMID_RES_MASK, 2171 0x2 << WM8904_VMID_RES_SHIFT); 2172 2173 /* Bias current *0.5 */ 2174 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2175 WM8904_ISEL_MASK, 0); 2176 break; 2177 2178 case SND_SOC_BIAS_OFF: 2179 /* Turn off VMID */ 2180 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2181 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 2182 2183 /* Stop bias generation */ 2184 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2185 WM8904_BIAS_ENA, 0); 2186 2187 #ifdef CONFIG_REGULATOR 2188 /* Post 2.6.34 we will be able to get a callback when 2189 * the regulators are disabled which we can use but 2190 * for now just assume that the power will be cut if 2191 * the regulator API is in use. 2192 */ 2193 codec->cache_sync = 1; 2194 #endif 2195 2196 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 2197 wm8904->supplies); 2198 break; 2199 } 2200 codec->dapm.bias_level = level; 2201 return 0; 2202 } 2203 2204 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 2205 2206 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2207 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2208 2209 static struct snd_soc_dai_ops wm8904_dai_ops = { 2210 .set_sysclk = wm8904_set_sysclk, 2211 .set_fmt = wm8904_set_fmt, 2212 .set_tdm_slot = wm8904_set_tdm_slot, 2213 .set_pll = wm8904_set_fll, 2214 .hw_params = wm8904_hw_params, 2215 .digital_mute = wm8904_digital_mute, 2216 }; 2217 2218 static struct snd_soc_dai_driver wm8904_dai = { 2219 .name = "wm8904-hifi", 2220 .playback = { 2221 .stream_name = "Playback", 2222 .channels_min = 2, 2223 .channels_max = 2, 2224 .rates = WM8904_RATES, 2225 .formats = WM8904_FORMATS, 2226 }, 2227 .capture = { 2228 .stream_name = "Capture", 2229 .channels_min = 2, 2230 .channels_max = 2, 2231 .rates = WM8904_RATES, 2232 .formats = WM8904_FORMATS, 2233 }, 2234 .ops = &wm8904_dai_ops, 2235 .symmetric_rates = 1, 2236 }; 2237 2238 #ifdef CONFIG_PM 2239 static int wm8904_suspend(struct snd_soc_codec *codec, pm_message_t state) 2240 { 2241 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2242 2243 return 0; 2244 } 2245 2246 static int wm8904_resume(struct snd_soc_codec *codec) 2247 { 2248 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2249 2250 return 0; 2251 } 2252 #else 2253 #define wm8904_suspend NULL 2254 #define wm8904_resume NULL 2255 #endif 2256 2257 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec) 2258 { 2259 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2260 struct wm8904_pdata *pdata = wm8904->pdata; 2261 struct snd_kcontrol_new control = 2262 SOC_ENUM_EXT("EQ Mode", 2263 wm8904->retune_mobile_enum, 2264 wm8904_get_retune_mobile_enum, 2265 wm8904_put_retune_mobile_enum); 2266 int ret, i, j; 2267 const char **t; 2268 2269 /* We need an array of texts for the enum API but the number 2270 * of texts is likely to be less than the number of 2271 * configurations due to the sample rate dependency of the 2272 * configurations. */ 2273 wm8904->num_retune_mobile_texts = 0; 2274 wm8904->retune_mobile_texts = NULL; 2275 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2276 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 2277 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2278 wm8904->retune_mobile_texts[j]) == 0) 2279 break; 2280 } 2281 2282 if (j != wm8904->num_retune_mobile_texts) 2283 continue; 2284 2285 /* Expand the array... */ 2286 t = krealloc(wm8904->retune_mobile_texts, 2287 sizeof(char *) * 2288 (wm8904->num_retune_mobile_texts + 1), 2289 GFP_KERNEL); 2290 if (t == NULL) 2291 continue; 2292 2293 /* ...store the new entry... */ 2294 t[wm8904->num_retune_mobile_texts] = 2295 pdata->retune_mobile_cfgs[i].name; 2296 2297 /* ...and remember the new version. */ 2298 wm8904->num_retune_mobile_texts++; 2299 wm8904->retune_mobile_texts = t; 2300 } 2301 2302 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2303 wm8904->num_retune_mobile_texts); 2304 2305 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; 2306 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2307 2308 ret = snd_soc_add_controls(codec, &control, 1); 2309 if (ret != 0) 2310 dev_err(codec->dev, 2311 "Failed to add ReTune Mobile control: %d\n", ret); 2312 } 2313 2314 static void wm8904_handle_pdata(struct snd_soc_codec *codec) 2315 { 2316 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2317 struct wm8904_pdata *pdata = wm8904->pdata; 2318 int ret, i; 2319 2320 if (!pdata) { 2321 snd_soc_add_controls(codec, wm8904_eq_controls, 2322 ARRAY_SIZE(wm8904_eq_controls)); 2323 return; 2324 } 2325 2326 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2327 2328 if (pdata->num_drc_cfgs) { 2329 struct snd_kcontrol_new control = 2330 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2331 wm8904_get_drc_enum, wm8904_put_drc_enum); 2332 2333 /* We need an array of texts for the enum API */ 2334 wm8904->drc_texts = kmalloc(sizeof(char *) 2335 * pdata->num_drc_cfgs, GFP_KERNEL); 2336 if (!wm8904->drc_texts) { 2337 dev_err(codec->dev, 2338 "Failed to allocate %d DRC config texts\n", 2339 pdata->num_drc_cfgs); 2340 return; 2341 } 2342 2343 for (i = 0; i < pdata->num_drc_cfgs; i++) 2344 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2345 2346 wm8904->drc_enum.max = pdata->num_drc_cfgs; 2347 wm8904->drc_enum.texts = wm8904->drc_texts; 2348 2349 ret = snd_soc_add_controls(codec, &control, 1); 2350 if (ret != 0) 2351 dev_err(codec->dev, 2352 "Failed to add DRC mode control: %d\n", ret); 2353 2354 wm8904_set_drc(codec); 2355 } 2356 2357 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2358 pdata->num_retune_mobile_cfgs); 2359 2360 if (pdata->num_retune_mobile_cfgs) 2361 wm8904_handle_retune_mobile_pdata(codec); 2362 else 2363 snd_soc_add_controls(codec, wm8904_eq_controls, 2364 ARRAY_SIZE(wm8904_eq_controls)); 2365 } 2366 2367 2368 static int wm8904_probe(struct snd_soc_codec *codec) 2369 { 2370 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2371 struct wm8904_pdata *pdata = wm8904->pdata; 2372 u16 *reg_cache = codec->reg_cache; 2373 int ret, i; 2374 2375 codec->cache_sync = 1; 2376 codec->dapm.idle_bias_off = 1; 2377 2378 switch (wm8904->devtype) { 2379 case WM8904: 2380 break; 2381 case WM8912: 2382 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2383 break; 2384 default: 2385 dev_err(codec->dev, "Unknown device type %d\n", 2386 wm8904->devtype); 2387 return -EINVAL; 2388 } 2389 2390 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 2391 if (ret != 0) { 2392 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2393 return ret; 2394 } 2395 2396 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2397 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2398 2399 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), 2400 wm8904->supplies); 2401 if (ret != 0) { 2402 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2403 return ret; 2404 } 2405 2406 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2407 wm8904->supplies); 2408 if (ret != 0) { 2409 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2410 goto err_get; 2411 } 2412 2413 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); 2414 if (ret < 0) { 2415 dev_err(codec->dev, "Failed to read ID register\n"); 2416 goto err_enable; 2417 } 2418 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { 2419 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); 2420 ret = -EINVAL; 2421 goto err_enable; 2422 } 2423 2424 ret = snd_soc_read(codec, WM8904_REVISION); 2425 if (ret < 0) { 2426 dev_err(codec->dev, "Failed to read device revision: %d\n", 2427 ret); 2428 goto err_enable; 2429 } 2430 dev_info(codec->dev, "revision %c\n", ret + 'A'); 2431 2432 ret = wm8904_reset(codec); 2433 if (ret < 0) { 2434 dev_err(codec->dev, "Failed to issue reset\n"); 2435 goto err_enable; 2436 } 2437 2438 /* Change some default settings - latch VU and enable ZC */ 2439 reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; 2440 reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; 2441 reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; 2442 reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; 2443 reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | 2444 WM8904_HPOUTLZC; 2445 reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | 2446 WM8904_HPOUTRZC; 2447 reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | 2448 WM8904_LINEOUTLZC; 2449 reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | 2450 WM8904_LINEOUTRZC; 2451 reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; 2452 2453 /* Apply configuration from the platform data. */ 2454 if (wm8904->pdata) { 2455 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2456 if (!pdata->gpio_cfg[i]) 2457 continue; 2458 2459 reg_cache[WM8904_GPIO_CONTROL_1 + i] 2460 = pdata->gpio_cfg[i] & 0xffff; 2461 } 2462 2463 /* Zero is the default value for these anyway */ 2464 for (i = 0; i < WM8904_MIC_REGS; i++) 2465 reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2466 = pdata->mic_cfg[i]; 2467 } 2468 2469 /* Set Class W by default - this will be managed by the Class 2470 * G widget at runtime where bypass paths are available. 2471 */ 2472 reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; 2473 2474 /* Use normal bias source */ 2475 reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; 2476 2477 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2478 2479 /* Bias level configuration will have done an extra enable */ 2480 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2481 2482 wm8904_handle_pdata(codec); 2483 2484 wm8904_add_widgets(codec); 2485 2486 return 0; 2487 2488 err_enable: 2489 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2490 err_get: 2491 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2492 return ret; 2493 } 2494 2495 static int wm8904_remove(struct snd_soc_codec *codec) 2496 { 2497 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2498 2499 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2500 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2501 kfree(wm8904->retune_mobile_texts); 2502 kfree(wm8904->drc_texts); 2503 2504 return 0; 2505 } 2506 2507 static struct snd_soc_codec_driver soc_codec_dev_wm8904 = { 2508 .probe = wm8904_probe, 2509 .remove = wm8904_remove, 2510 .suspend = wm8904_suspend, 2511 .resume = wm8904_resume, 2512 .set_bias_level = wm8904_set_bias_level, 2513 .reg_cache_size = ARRAY_SIZE(wm8904_reg), 2514 .reg_word_size = sizeof(u16), 2515 .reg_cache_default = wm8904_reg, 2516 .volatile_register = wm8904_volatile_register, 2517 }; 2518 2519 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2520 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, 2521 const struct i2c_device_id *id) 2522 { 2523 struct wm8904_priv *wm8904; 2524 int ret; 2525 2526 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); 2527 if (wm8904 == NULL) 2528 return -ENOMEM; 2529 2530 wm8904->devtype = id->driver_data; 2531 i2c_set_clientdata(i2c, wm8904); 2532 wm8904->control_data = i2c; 2533 wm8904->pdata = i2c->dev.platform_data; 2534 2535 ret = snd_soc_register_codec(&i2c->dev, 2536 &soc_codec_dev_wm8904, &wm8904_dai, 1); 2537 if (ret < 0) 2538 kfree(wm8904); 2539 return ret; 2540 } 2541 2542 static __devexit int wm8904_i2c_remove(struct i2c_client *client) 2543 { 2544 snd_soc_unregister_codec(&client->dev); 2545 kfree(i2c_get_clientdata(client)); 2546 return 0; 2547 } 2548 2549 static const struct i2c_device_id wm8904_i2c_id[] = { 2550 { "wm8904", WM8904 }, 2551 { "wm8912", WM8912 }, 2552 { } 2553 }; 2554 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2555 2556 static struct i2c_driver wm8904_i2c_driver = { 2557 .driver = { 2558 .name = "wm8904-codec", 2559 .owner = THIS_MODULE, 2560 }, 2561 .probe = wm8904_i2c_probe, 2562 .remove = __devexit_p(wm8904_i2c_remove), 2563 .id_table = wm8904_i2c_id, 2564 }; 2565 #endif 2566 2567 static int __init wm8904_modinit(void) 2568 { 2569 int ret = 0; 2570 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2571 ret = i2c_add_driver(&wm8904_i2c_driver); 2572 if (ret != 0) { 2573 printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n", 2574 ret); 2575 } 2576 #endif 2577 return ret; 2578 } 2579 module_init(wm8904_modinit); 2580 2581 static void __exit wm8904_exit(void) 2582 { 2583 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2584 i2c_del_driver(&wm8904_i2c_driver); 2585 #endif 2586 } 2587 module_exit(wm8904_exit); 2588 2589 MODULE_DESCRIPTION("ASoC WM8904 driver"); 2590 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2591 MODULE_LICENSE("GPL"); 2592