1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008-12 Wolfson Microelectronics 5 * Copyright 2011-2012 NVIDIA, Inc. 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: 14 * - TDM mode configuration. 15 * - Digital microphone support. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/init.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/gpio.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/regmap.h> 27 #include <linux/slab.h> 28 #include <linux/irq.h> 29 #include <sound/core.h> 30 #include <sound/jack.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/tlv.h> 34 #include <sound/soc.h> 35 #include <sound/initval.h> 36 #include <sound/wm8903.h> 37 #include <trace/events/asoc.h> 38 39 #include "wm8903.h" 40 41 /* Register defaults at reset */ 42 static const struct reg_default wm8903_reg_defaults[] = { 43 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 44 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 45 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 46 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 47 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 48 { 12, 0x0000 }, /* R12 - Power Management 0 */ 49 { 13, 0x0000 }, /* R13 - Power Management 1 */ 50 { 14, 0x0000 }, /* R14 - Power Management 2 */ 51 { 15, 0x0000 }, /* R15 - Power Management 3 */ 52 { 16, 0x0000 }, /* R16 - Power Management 4 */ 53 { 17, 0x0000 }, /* R17 - Power Management 5 */ 54 { 18, 0x0000 }, /* R18 - Power Management 6 */ 55 { 20, 0x0400 }, /* R20 - Clock Rates 0 */ 56 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */ 57 { 22, 0x0000 }, /* R22 - Clock Rates 2 */ 58 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 59 { 25, 0x0242 }, /* R25 - Audio Interface 1 */ 60 { 26, 0x0008 }, /* R26 - Audio Interface 2 */ 61 { 27, 0x0022 }, /* R27 - Audio Interface 3 */ 62 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 63 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 64 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 65 { 33, 0x0000 }, /* R33 - DAC Digital 1 */ 66 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 67 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 68 { 38, 0x0000 }, /* R38 - ADC Digital 0 */ 69 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */ 70 { 40, 0x09BF }, /* R40 - DRC 0 */ 71 { 41, 0x3241 }, /* R41 - DRC 1 */ 72 { 42, 0x0020 }, /* R42 - DRC 2 */ 73 { 43, 0x0000 }, /* R43 - DRC 3 */ 74 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 75 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 76 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 77 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 78 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */ 79 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */ 80 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */ 81 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */ 82 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */ 83 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */ 84 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 85 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 86 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 87 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 88 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */ 89 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */ 90 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */ 91 { 67, 0x0010 }, /* R67 - DC Servo 0 */ 92 { 69, 0x00A4 }, /* R69 - DC Servo 2 */ 93 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 94 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 95 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 96 { 104, 0x0000 }, /* R104 - Class W 0 */ 97 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 98 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 99 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 100 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 101 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 102 { 114, 0x0000 }, /* R114 - Control Interface */ 103 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */ 104 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */ 105 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */ 106 { 119, 0x0220 }, /* R119 - GPIO Control 4 */ 107 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */ 108 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */ 109 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */ 110 { 126, 0x0000 }, /* R126 - Interrupt Control */ 111 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */ 112 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */ 113 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */ 114 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */ 115 }; 116 117 struct wm8903_priv { 118 struct wm8903_platform_data *pdata; 119 struct device *dev; 120 struct snd_soc_codec *codec; 121 struct regmap *regmap; 122 123 int sysclk; 124 int irq; 125 126 int fs; 127 int deemph; 128 129 int dcs_pending; 130 int dcs_cache[4]; 131 132 /* Reference count */ 133 int class_w_users; 134 135 struct snd_soc_jack *mic_jack; 136 int mic_det; 137 int mic_short; 138 int mic_last_report; 139 int mic_delay; 140 141 #ifdef CONFIG_GPIOLIB 142 struct gpio_chip gpio_chip; 143 #endif 144 }; 145 146 static bool wm8903_readable_register(struct device *dev, unsigned int reg) 147 { 148 switch (reg) { 149 case WM8903_SW_RESET_AND_ID: 150 case WM8903_REVISION_NUMBER: 151 case WM8903_BIAS_CONTROL_0: 152 case WM8903_VMID_CONTROL_0: 153 case WM8903_MIC_BIAS_CONTROL_0: 154 case WM8903_ANALOGUE_DAC_0: 155 case WM8903_ANALOGUE_ADC_0: 156 case WM8903_POWER_MANAGEMENT_0: 157 case WM8903_POWER_MANAGEMENT_1: 158 case WM8903_POWER_MANAGEMENT_2: 159 case WM8903_POWER_MANAGEMENT_3: 160 case WM8903_POWER_MANAGEMENT_4: 161 case WM8903_POWER_MANAGEMENT_5: 162 case WM8903_POWER_MANAGEMENT_6: 163 case WM8903_CLOCK_RATES_0: 164 case WM8903_CLOCK_RATES_1: 165 case WM8903_CLOCK_RATES_2: 166 case WM8903_AUDIO_INTERFACE_0: 167 case WM8903_AUDIO_INTERFACE_1: 168 case WM8903_AUDIO_INTERFACE_2: 169 case WM8903_AUDIO_INTERFACE_3: 170 case WM8903_DAC_DIGITAL_VOLUME_LEFT: 171 case WM8903_DAC_DIGITAL_VOLUME_RIGHT: 172 case WM8903_DAC_DIGITAL_0: 173 case WM8903_DAC_DIGITAL_1: 174 case WM8903_ADC_DIGITAL_VOLUME_LEFT: 175 case WM8903_ADC_DIGITAL_VOLUME_RIGHT: 176 case WM8903_ADC_DIGITAL_0: 177 case WM8903_DIGITAL_MICROPHONE_0: 178 case WM8903_DRC_0: 179 case WM8903_DRC_1: 180 case WM8903_DRC_2: 181 case WM8903_DRC_3: 182 case WM8903_ANALOGUE_LEFT_INPUT_0: 183 case WM8903_ANALOGUE_RIGHT_INPUT_0: 184 case WM8903_ANALOGUE_LEFT_INPUT_1: 185 case WM8903_ANALOGUE_RIGHT_INPUT_1: 186 case WM8903_ANALOGUE_LEFT_MIX_0: 187 case WM8903_ANALOGUE_RIGHT_MIX_0: 188 case WM8903_ANALOGUE_SPK_MIX_LEFT_0: 189 case WM8903_ANALOGUE_SPK_MIX_LEFT_1: 190 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0: 191 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1: 192 case WM8903_ANALOGUE_OUT1_LEFT: 193 case WM8903_ANALOGUE_OUT1_RIGHT: 194 case WM8903_ANALOGUE_OUT2_LEFT: 195 case WM8903_ANALOGUE_OUT2_RIGHT: 196 case WM8903_ANALOGUE_OUT3_LEFT: 197 case WM8903_ANALOGUE_OUT3_RIGHT: 198 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0: 199 case WM8903_DC_SERVO_0: 200 case WM8903_DC_SERVO_2: 201 case WM8903_DC_SERVO_READBACK_1: 202 case WM8903_DC_SERVO_READBACK_2: 203 case WM8903_DC_SERVO_READBACK_3: 204 case WM8903_DC_SERVO_READBACK_4: 205 case WM8903_ANALOGUE_HP_0: 206 case WM8903_ANALOGUE_LINEOUT_0: 207 case WM8903_CHARGE_PUMP_0: 208 case WM8903_CLASS_W_0: 209 case WM8903_WRITE_SEQUENCER_0: 210 case WM8903_WRITE_SEQUENCER_1: 211 case WM8903_WRITE_SEQUENCER_2: 212 case WM8903_WRITE_SEQUENCER_3: 213 case WM8903_WRITE_SEQUENCER_4: 214 case WM8903_CONTROL_INTERFACE: 215 case WM8903_GPIO_CONTROL_1: 216 case WM8903_GPIO_CONTROL_2: 217 case WM8903_GPIO_CONTROL_3: 218 case WM8903_GPIO_CONTROL_4: 219 case WM8903_GPIO_CONTROL_5: 220 case WM8903_INTERRUPT_STATUS_1: 221 case WM8903_INTERRUPT_STATUS_1_MASK: 222 case WM8903_INTERRUPT_POLARITY_1: 223 case WM8903_INTERRUPT_CONTROL: 224 case WM8903_CLOCK_RATE_TEST_4: 225 case WM8903_ANALOGUE_OUTPUT_BIAS_0: 226 return true; 227 default: 228 return false; 229 } 230 } 231 232 static bool wm8903_volatile_register(struct device *dev, unsigned int reg) 233 { 234 switch (reg) { 235 case WM8903_SW_RESET_AND_ID: 236 case WM8903_REVISION_NUMBER: 237 case WM8903_INTERRUPT_STATUS_1: 238 case WM8903_WRITE_SEQUENCER_4: 239 case WM8903_DC_SERVO_READBACK_1: 240 case WM8903_DC_SERVO_READBACK_2: 241 case WM8903_DC_SERVO_READBACK_3: 242 case WM8903_DC_SERVO_READBACK_4: 243 return 1; 244 245 default: 246 return 0; 247 } 248 } 249 250 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 251 struct snd_kcontrol *kcontrol, int event) 252 { 253 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 254 mdelay(4); 255 256 return 0; 257 } 258 259 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 260 struct snd_kcontrol *kcontrol, int event) 261 { 262 struct snd_soc_codec *codec = w->codec; 263 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 264 265 switch (event) { 266 case SND_SOC_DAPM_POST_PMU: 267 wm8903->dcs_pending |= 1 << w->shift; 268 break; 269 case SND_SOC_DAPM_PRE_PMD: 270 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 271 1 << w->shift, 0); 272 break; 273 } 274 275 return 0; 276 } 277 278 #define WM8903_DCS_MODE_WRITE_STOP 0 279 #define WM8903_DCS_MODE_START_STOP 2 280 281 static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm, 282 enum snd_soc_dapm_type event, int subseq) 283 { 284 struct snd_soc_codec *codec = container_of(dapm, 285 struct snd_soc_codec, dapm); 286 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 287 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 288 int i, val; 289 290 /* Complete any pending DC servo starts */ 291 if (wm8903->dcs_pending) { 292 dev_dbg(codec->dev, "Starting DC servo for %x\n", 293 wm8903->dcs_pending); 294 295 /* If we've no cached values then we need to do startup */ 296 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 297 if (!(wm8903->dcs_pending & (1 << i))) 298 continue; 299 300 if (wm8903->dcs_cache[i]) { 301 dev_dbg(codec->dev, 302 "Restore DC servo %d value %x\n", 303 3 - i, wm8903->dcs_cache[i]); 304 305 snd_soc_write(codec, WM8903_DC_SERVO_4 + i, 306 wm8903->dcs_cache[i] & 0xff); 307 } else { 308 dev_dbg(codec->dev, 309 "Calibrate DC servo %d\n", 3 - i); 310 dcs_mode = WM8903_DCS_MODE_START_STOP; 311 } 312 } 313 314 /* Don't trust the cache for analogue */ 315 if (wm8903->class_w_users) 316 dcs_mode = WM8903_DCS_MODE_START_STOP; 317 318 snd_soc_update_bits(codec, WM8903_DC_SERVO_2, 319 WM8903_DCS_MODE_MASK, dcs_mode); 320 321 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 322 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 323 324 switch (dcs_mode) { 325 case WM8903_DCS_MODE_WRITE_STOP: 326 break; 327 328 case WM8903_DCS_MODE_START_STOP: 329 msleep(270); 330 331 /* Cache the measured offsets for digital */ 332 if (wm8903->class_w_users) 333 break; 334 335 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 336 if (!(wm8903->dcs_pending & (1 << i))) 337 continue; 338 339 val = snd_soc_read(codec, 340 WM8903_DC_SERVO_READBACK_1 + i); 341 dev_dbg(codec->dev, "DC servo %d: %x\n", 342 3 - i, val); 343 wm8903->dcs_cache[i] = val; 344 } 345 break; 346 347 default: 348 pr_warn("DCS mode %d delay not set\n", dcs_mode); 349 break; 350 } 351 352 wm8903->dcs_pending = 0; 353 } 354 } 355 356 /* 357 * When used with DAC outputs only the WM8903 charge pump supports 358 * operation in class W mode, providing very low power consumption 359 * when used with digital sources. Enable and disable this mode 360 * automatically depending on the mixer configuration. 361 * 362 * All the relevant controls are simple switches. 363 */ 364 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 365 struct snd_ctl_elem_value *ucontrol) 366 { 367 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 368 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 369 struct snd_soc_codec *codec = widget->codec; 370 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 371 u16 reg; 372 int ret; 373 374 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 375 376 /* Turn it off if we're about to enable bypass */ 377 if (ucontrol->value.integer.value[0]) { 378 if (wm8903->class_w_users == 0) { 379 dev_dbg(codec->dev, "Disabling Class W\n"); 380 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 381 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 382 } 383 wm8903->class_w_users++; 384 } 385 386 /* Implement the change */ 387 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 388 389 /* If we've just disabled the last bypass path turn Class W on */ 390 if (!ucontrol->value.integer.value[0]) { 391 if (wm8903->class_w_users == 1) { 392 dev_dbg(codec->dev, "Enabling Class W\n"); 393 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 394 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 395 } 396 wm8903->class_w_users--; 397 } 398 399 dev_dbg(codec->dev, "Bypass use count now %d\n", 400 wm8903->class_w_users); 401 402 return ret; 403 } 404 405 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 407 .info = snd_soc_info_volsw, \ 408 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 409 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 410 411 412 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 413 414 static int wm8903_set_deemph(struct snd_soc_codec *codec) 415 { 416 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 417 int val, i, best; 418 419 /* If we're using deemphasis select the nearest available sample 420 * rate. 421 */ 422 if (wm8903->deemph) { 423 best = 1; 424 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 425 if (abs(wm8903_deemph[i] - wm8903->fs) < 426 abs(wm8903_deemph[best] - wm8903->fs)) 427 best = i; 428 } 429 430 val = best << WM8903_DEEMPH_SHIFT; 431 } else { 432 best = 0; 433 val = 0; 434 } 435 436 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", 437 best, wm8903_deemph[best]); 438 439 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 440 WM8903_DEEMPH_MASK, val); 441 } 442 443 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 444 struct snd_ctl_elem_value *ucontrol) 445 { 446 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 447 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 448 449 ucontrol->value.enumerated.item[0] = wm8903->deemph; 450 451 return 0; 452 } 453 454 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 455 struct snd_ctl_elem_value *ucontrol) 456 { 457 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 458 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 459 int deemph = ucontrol->value.enumerated.item[0]; 460 int ret = 0; 461 462 if (deemph > 1) 463 return -EINVAL; 464 465 mutex_lock(&codec->mutex); 466 if (wm8903->deemph != deemph) { 467 wm8903->deemph = deemph; 468 469 wm8903_set_deemph(codec); 470 471 ret = 1; 472 } 473 mutex_unlock(&codec->mutex); 474 475 return ret; 476 } 477 478 /* ALSA can only do steps of .01dB */ 479 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 480 481 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 482 483 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 484 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 485 486 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 487 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 488 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 489 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 490 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 491 492 static const char *hpf_mode_text[] = { 493 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 494 }; 495 496 static const struct soc_enum hpf_mode = 497 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 498 499 static const char *osr_text[] = { 500 "Low power", "High performance" 501 }; 502 503 static const struct soc_enum adc_osr = 504 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text); 505 506 static const struct soc_enum dac_osr = 507 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text); 508 509 static const char *drc_slope_text[] = { 510 "1", "1/2", "1/4", "1/8", "1/16", "0" 511 }; 512 513 static const struct soc_enum drc_slope_r0 = 514 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 515 516 static const struct soc_enum drc_slope_r1 = 517 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 518 519 static const char *drc_attack_text[] = { 520 "instantaneous", 521 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 522 "46.4ms", "92.8ms", "185.6ms" 523 }; 524 525 static const struct soc_enum drc_attack = 526 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 527 528 static const char *drc_decay_text[] = { 529 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 530 "23.87s", "47.56s" 531 }; 532 533 static const struct soc_enum drc_decay = 534 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 535 536 static const char *drc_ff_delay_text[] = { 537 "5 samples", "9 samples" 538 }; 539 540 static const struct soc_enum drc_ff_delay = 541 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 542 543 static const char *drc_qr_decay_text[] = { 544 "0.725ms", "1.45ms", "5.8ms" 545 }; 546 547 static const struct soc_enum drc_qr_decay = 548 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 549 550 static const char *drc_smoothing_text[] = { 551 "Low", "Medium", "High" 552 }; 553 554 static const struct soc_enum drc_smoothing = 555 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 556 557 static const char *soft_mute_text[] = { 558 "Fast (fs/2)", "Slow (fs/32)" 559 }; 560 561 static const struct soc_enum soft_mute = 562 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 563 564 static const char *mute_mode_text[] = { 565 "Hard", "Soft" 566 }; 567 568 static const struct soc_enum mute_mode = 569 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 570 571 static const char *companding_text[] = { 572 "ulaw", "alaw" 573 }; 574 575 static const struct soc_enum dac_companding = 576 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 577 578 static const struct soc_enum adc_companding = 579 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 580 581 static const char *input_mode_text[] = { 582 "Single-Ended", "Differential Line", "Differential Mic" 583 }; 584 585 static const struct soc_enum linput_mode_enum = 586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 587 588 static const struct soc_enum rinput_mode_enum = 589 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 590 591 static const char *linput_mux_text[] = { 592 "IN1L", "IN2L", "IN3L" 593 }; 594 595 static const struct soc_enum linput_enum = 596 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 597 598 static const struct soc_enum linput_inv_enum = 599 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 600 601 static const char *rinput_mux_text[] = { 602 "IN1R", "IN2R", "IN3R" 603 }; 604 605 static const struct soc_enum rinput_enum = 606 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 607 608 static const struct soc_enum rinput_inv_enum = 609 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 610 611 612 static const char *sidetone_text[] = { 613 "None", "Left", "Right" 614 }; 615 616 static const struct soc_enum lsidetone_enum = 617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 618 619 static const struct soc_enum rsidetone_enum = 620 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 621 622 static const char *adcinput_text[] = { 623 "ADC", "DMIC" 624 }; 625 626 static const struct soc_enum adcinput_enum = 627 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text); 628 629 static const char *aif_text[] = { 630 "Left", "Right" 631 }; 632 633 static const struct soc_enum lcapture_enum = 634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text); 635 636 static const struct soc_enum rcapture_enum = 637 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text); 638 639 static const struct soc_enum lplay_enum = 640 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text); 641 642 static const struct soc_enum rplay_enum = 643 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text); 644 645 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 646 647 /* Input PGAs - No TLV since the scale depends on PGA mode */ 648 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 649 7, 1, 1), 650 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 651 0, 31, 0), 652 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 653 6, 1, 0), 654 655 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 656 7, 1, 1), 657 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 658 0, 31, 0), 659 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 660 6, 1, 0), 661 662 /* ADCs */ 663 SOC_ENUM("ADC OSR", adc_osr), 664 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 665 SOC_ENUM("HPF Mode", hpf_mode), 666 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 667 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 668 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 669 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 670 drc_tlv_thresh), 671 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 672 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 673 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 674 SOC_ENUM("DRC Attack Rate", drc_attack), 675 SOC_ENUM("DRC Decay Rate", drc_decay), 676 SOC_ENUM("DRC FF Delay", drc_ff_delay), 677 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 678 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 679 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 680 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 681 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 682 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 683 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 684 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 685 686 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 687 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 688 SOC_ENUM("ADC Companding Mode", adc_companding), 689 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 690 691 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 692 12, 0, digital_sidetone_tlv), 693 694 /* DAC */ 695 SOC_ENUM("DAC OSR", dac_osr), 696 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 697 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 698 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 699 SOC_ENUM("DAC Mute Mode", mute_mode), 700 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 701 SOC_ENUM("DAC Companding Mode", dac_companding), 702 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 703 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0, 704 dac_boost_tlv), 705 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 706 wm8903_get_deemph, wm8903_put_deemph), 707 708 /* Headphones */ 709 SOC_DOUBLE_R("Headphone Switch", 710 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 711 8, 1, 1), 712 SOC_DOUBLE_R("Headphone ZC Switch", 713 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 714 6, 1, 0), 715 SOC_DOUBLE_R_TLV("Headphone Volume", 716 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 717 0, 63, 0, out_tlv), 718 719 /* Line out */ 720 SOC_DOUBLE_R("Line Out Switch", 721 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 722 8, 1, 1), 723 SOC_DOUBLE_R("Line Out ZC Switch", 724 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 725 6, 1, 0), 726 SOC_DOUBLE_R_TLV("Line Out Volume", 727 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 728 0, 63, 0, out_tlv), 729 730 /* Speaker */ 731 SOC_DOUBLE_R("Speaker Switch", 732 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 733 SOC_DOUBLE_R("Speaker ZC Switch", 734 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 735 SOC_DOUBLE_R_TLV("Speaker Volume", 736 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 737 0, 63, 0, out_tlv), 738 }; 739 740 static const struct snd_kcontrol_new linput_mode_mux = 741 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 742 743 static const struct snd_kcontrol_new rinput_mode_mux = 744 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 745 746 static const struct snd_kcontrol_new linput_mux = 747 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 748 749 static const struct snd_kcontrol_new linput_inv_mux = 750 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 751 752 static const struct snd_kcontrol_new rinput_mux = 753 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 754 755 static const struct snd_kcontrol_new rinput_inv_mux = 756 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 757 758 static const struct snd_kcontrol_new lsidetone_mux = 759 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 760 761 static const struct snd_kcontrol_new rsidetone_mux = 762 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 763 764 static const struct snd_kcontrol_new adcinput_mux = 765 SOC_DAPM_ENUM("ADC Input", adcinput_enum); 766 767 static const struct snd_kcontrol_new lcapture_mux = 768 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 769 770 static const struct snd_kcontrol_new rcapture_mux = 771 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 772 773 static const struct snd_kcontrol_new lplay_mux = 774 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 775 776 static const struct snd_kcontrol_new rplay_mux = 777 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 778 779 static const struct snd_kcontrol_new left_output_mixer[] = { 780 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 781 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 782 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 783 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 784 }; 785 786 static const struct snd_kcontrol_new right_output_mixer[] = { 787 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 788 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 789 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 790 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 791 }; 792 793 static const struct snd_kcontrol_new left_speaker_mixer[] = { 794 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 795 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 796 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 797 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 798 0, 1, 0), 799 }; 800 801 static const struct snd_kcontrol_new right_speaker_mixer[] = { 802 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 803 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 804 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 805 1, 1, 0), 806 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 807 0, 1, 0), 808 }; 809 810 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 811 SND_SOC_DAPM_INPUT("IN1L"), 812 SND_SOC_DAPM_INPUT("IN1R"), 813 SND_SOC_DAPM_INPUT("IN2L"), 814 SND_SOC_DAPM_INPUT("IN2R"), 815 SND_SOC_DAPM_INPUT("IN3L"), 816 SND_SOC_DAPM_INPUT("IN3R"), 817 SND_SOC_DAPM_INPUT("DMICDAT"), 818 819 SND_SOC_DAPM_OUTPUT("HPOUTL"), 820 SND_SOC_DAPM_OUTPUT("HPOUTR"), 821 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 822 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 823 SND_SOC_DAPM_OUTPUT("LOP"), 824 SND_SOC_DAPM_OUTPUT("LON"), 825 SND_SOC_DAPM_OUTPUT("ROP"), 826 SND_SOC_DAPM_OUTPUT("RON"), 827 828 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 829 830 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 831 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 832 &linput_inv_mux), 833 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 834 835 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 836 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 837 &rinput_inv_mux), 838 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 839 840 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 841 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 842 843 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 844 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 845 846 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 847 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 848 849 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 850 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 851 852 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 853 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 854 855 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 856 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 857 858 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 859 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 860 861 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 862 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 863 864 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 865 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 866 867 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 868 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 869 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 870 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 871 872 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 873 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 874 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 875 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 876 877 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 878 1, 0, NULL, 0), 879 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 880 0, 0, NULL, 0), 881 882 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, 883 NULL, 0), 884 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, 885 NULL, 0), 886 887 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 888 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 889 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 890 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), 891 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 892 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 893 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 894 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), 895 896 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 897 NULL, 0), 898 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 899 NULL, 0), 900 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 901 NULL, 0), 902 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 903 NULL, 0), 904 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 905 NULL, 0), 906 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 907 NULL, 0), 908 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 909 NULL, 0), 910 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 911 NULL, 0), 912 913 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 914 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 915 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 916 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 917 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 918 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 919 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 920 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 921 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 922 923 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 924 NULL, 0), 925 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 926 NULL, 0), 927 928 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 929 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 930 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 931 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 932 }; 933 934 static const struct snd_soc_dapm_route wm8903_intercon[] = { 935 936 { "CLK_DSP", NULL, "CLK_SYS" }, 937 { "MICBIAS", NULL, "CLK_SYS" }, 938 { "HPL_DCS", NULL, "CLK_SYS" }, 939 { "HPR_DCS", NULL, "CLK_SYS" }, 940 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 941 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 942 943 { "Left Input Mux", "IN1L", "IN1L" }, 944 { "Left Input Mux", "IN2L", "IN2L" }, 945 { "Left Input Mux", "IN3L", "IN3L" }, 946 947 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 948 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 949 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 950 951 { "Right Input Mux", "IN1R", "IN1R" }, 952 { "Right Input Mux", "IN2R", "IN2R" }, 953 { "Right Input Mux", "IN3R", "IN3R" }, 954 955 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 956 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 957 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 958 959 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 960 { "Left Input Mode Mux", "Differential Line", 961 "Left Input Mux" }, 962 { "Left Input Mode Mux", "Differential Line", 963 "Left Input Inverting Mux" }, 964 { "Left Input Mode Mux", "Differential Mic", 965 "Left Input Mux" }, 966 { "Left Input Mode Mux", "Differential Mic", 967 "Left Input Inverting Mux" }, 968 969 { "Right Input Mode Mux", "Single-Ended", 970 "Right Input Inverting Mux" }, 971 { "Right Input Mode Mux", "Differential Line", 972 "Right Input Mux" }, 973 { "Right Input Mode Mux", "Differential Line", 974 "Right Input Inverting Mux" }, 975 { "Right Input Mode Mux", "Differential Mic", 976 "Right Input Mux" }, 977 { "Right Input Mode Mux", "Differential Mic", 978 "Right Input Inverting Mux" }, 979 980 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 981 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 982 983 { "Left ADC Input", "ADC", "Left Input PGA" }, 984 { "Left ADC Input", "DMIC", "DMICDAT" }, 985 { "Right ADC Input", "ADC", "Right Input PGA" }, 986 { "Right ADC Input", "DMIC", "DMICDAT" }, 987 988 { "Left Capture Mux", "Left", "ADCL" }, 989 { "Left Capture Mux", "Right", "ADCR" }, 990 991 { "Right Capture Mux", "Left", "ADCL" }, 992 { "Right Capture Mux", "Right", "ADCR" }, 993 994 { "AIFTXL", NULL, "Left Capture Mux" }, 995 { "AIFTXR", NULL, "Right Capture Mux" }, 996 997 { "ADCL", NULL, "Left ADC Input" }, 998 { "ADCL", NULL, "CLK_DSP" }, 999 { "ADCR", NULL, "Right ADC Input" }, 1000 { "ADCR", NULL, "CLK_DSP" }, 1001 1002 { "Left Playback Mux", "Left", "AIFRXL" }, 1003 { "Left Playback Mux", "Right", "AIFRXR" }, 1004 1005 { "Right Playback Mux", "Left", "AIFRXL" }, 1006 { "Right Playback Mux", "Right", "AIFRXR" }, 1007 1008 { "DACL Sidetone", "Left", "ADCL" }, 1009 { "DACL Sidetone", "Right", "ADCR" }, 1010 { "DACR Sidetone", "Left", "ADCL" }, 1011 { "DACR Sidetone", "Right", "ADCR" }, 1012 1013 { "DACL", NULL, "Left Playback Mux" }, 1014 { "DACL", NULL, "DACL Sidetone" }, 1015 { "DACL", NULL, "CLK_DSP" }, 1016 1017 { "DACR", NULL, "Right Playback Mux" }, 1018 { "DACR", NULL, "DACR Sidetone" }, 1019 { "DACR", NULL, "CLK_DSP" }, 1020 1021 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1022 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1023 { "Left Output Mixer", "DACL Switch", "DACL" }, 1024 { "Left Output Mixer", "DACR Switch", "DACR" }, 1025 1026 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1027 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1028 { "Right Output Mixer", "DACL Switch", "DACL" }, 1029 { "Right Output Mixer", "DACR Switch", "DACR" }, 1030 1031 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1032 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1033 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1034 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1035 1036 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1037 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1038 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1039 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1040 1041 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1042 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1043 1044 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1045 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1046 1047 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1048 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1049 1050 { "HPL_ENA", NULL, "Left Headphone Output PGA" }, 1051 { "HPR_ENA", NULL, "Right Headphone Output PGA" }, 1052 { "HPL_ENA_DLY", NULL, "HPL_ENA" }, 1053 { "HPR_ENA_DLY", NULL, "HPR_ENA" }, 1054 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, 1055 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, 1056 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, 1057 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, 1058 1059 { "HPL_DCS", NULL, "DCS Master" }, 1060 { "HPR_DCS", NULL, "DCS Master" }, 1061 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1062 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1063 1064 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1065 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1066 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1067 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1068 1069 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1070 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1071 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1072 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1073 1074 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1075 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1076 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1077 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1078 1079 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1080 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1081 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1082 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1083 1084 { "LOP", NULL, "Left Speaker PGA" }, 1085 { "LON", NULL, "Left Speaker PGA" }, 1086 1087 { "ROP", NULL, "Right Speaker PGA" }, 1088 { "RON", NULL, "Right Speaker PGA" }, 1089 1090 { "Charge Pump", NULL, "CLK_DSP" }, 1091 1092 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1093 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1094 { "Left Line Output PGA", NULL, "Charge Pump" }, 1095 { "Right Line Output PGA", NULL, "Charge Pump" }, 1096 }; 1097 1098 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1099 enum snd_soc_bias_level level) 1100 { 1101 switch (level) { 1102 case SND_SOC_BIAS_ON: 1103 break; 1104 1105 case SND_SOC_BIAS_PREPARE: 1106 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1107 WM8903_VMID_RES_MASK, 1108 WM8903_VMID_RES_50K); 1109 break; 1110 1111 case SND_SOC_BIAS_STANDBY: 1112 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1113 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1114 WM8903_POBCTRL | WM8903_ISEL_MASK | 1115 WM8903_STARTUP_BIAS_ENA | 1116 WM8903_BIAS_ENA, 1117 WM8903_POBCTRL | 1118 (2 << WM8903_ISEL_SHIFT) | 1119 WM8903_STARTUP_BIAS_ENA); 1120 1121 snd_soc_update_bits(codec, 1122 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1123 WM8903_SPK_DISCHARGE, 1124 WM8903_SPK_DISCHARGE); 1125 1126 msleep(33); 1127 1128 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1129 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1130 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1131 1132 snd_soc_update_bits(codec, 1133 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1134 WM8903_SPK_DISCHARGE, 0); 1135 1136 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1137 WM8903_VMID_TIE_ENA | 1138 WM8903_BUFIO_ENA | 1139 WM8903_VMID_IO_ENA | 1140 WM8903_VMID_SOFT_MASK | 1141 WM8903_VMID_RES_MASK | 1142 WM8903_VMID_BUF_ENA, 1143 WM8903_VMID_TIE_ENA | 1144 WM8903_BUFIO_ENA | 1145 WM8903_VMID_IO_ENA | 1146 (2 << WM8903_VMID_SOFT_SHIFT) | 1147 WM8903_VMID_RES_250K | 1148 WM8903_VMID_BUF_ENA); 1149 1150 msleep(129); 1151 1152 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1153 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1154 0); 1155 1156 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1157 WM8903_VMID_SOFT_MASK, 0); 1158 1159 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1160 WM8903_VMID_RES_MASK, 1161 WM8903_VMID_RES_50K); 1162 1163 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1164 WM8903_BIAS_ENA | WM8903_POBCTRL, 1165 WM8903_BIAS_ENA); 1166 1167 /* By default no bypass paths are enabled so 1168 * enable Class W support. 1169 */ 1170 dev_dbg(codec->dev, "Enabling Class W\n"); 1171 snd_soc_update_bits(codec, WM8903_CLASS_W_0, 1172 WM8903_CP_DYN_FREQ | 1173 WM8903_CP_DYN_V, 1174 WM8903_CP_DYN_FREQ | 1175 WM8903_CP_DYN_V); 1176 } 1177 1178 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1179 WM8903_VMID_RES_MASK, 1180 WM8903_VMID_RES_250K); 1181 break; 1182 1183 case SND_SOC_BIAS_OFF: 1184 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1185 WM8903_BIAS_ENA, 0); 1186 1187 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1188 WM8903_VMID_SOFT_MASK, 1189 2 << WM8903_VMID_SOFT_SHIFT); 1190 1191 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1192 WM8903_VMID_BUF_ENA, 0); 1193 1194 msleep(290); 1195 1196 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1197 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1198 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1199 WM8903_VMID_SOFT_MASK | 1200 WM8903_VMID_BUF_ENA, 0); 1201 1202 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1203 WM8903_STARTUP_BIAS_ENA, 0); 1204 break; 1205 } 1206 1207 codec->dapm.bias_level = level; 1208 1209 return 0; 1210 } 1211 1212 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1213 int clk_id, unsigned int freq, int dir) 1214 { 1215 struct snd_soc_codec *codec = codec_dai->codec; 1216 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1217 1218 wm8903->sysclk = freq; 1219 1220 return 0; 1221 } 1222 1223 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1224 unsigned int fmt) 1225 { 1226 struct snd_soc_codec *codec = codec_dai->codec; 1227 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1228 1229 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1230 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1231 1232 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1233 case SND_SOC_DAIFMT_CBS_CFS: 1234 break; 1235 case SND_SOC_DAIFMT_CBS_CFM: 1236 aif1 |= WM8903_LRCLK_DIR; 1237 break; 1238 case SND_SOC_DAIFMT_CBM_CFM: 1239 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1240 break; 1241 case SND_SOC_DAIFMT_CBM_CFS: 1242 aif1 |= WM8903_BCLK_DIR; 1243 break; 1244 default: 1245 return -EINVAL; 1246 } 1247 1248 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1249 case SND_SOC_DAIFMT_DSP_A: 1250 aif1 |= 0x3; 1251 break; 1252 case SND_SOC_DAIFMT_DSP_B: 1253 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1254 break; 1255 case SND_SOC_DAIFMT_I2S: 1256 aif1 |= 0x2; 1257 break; 1258 case SND_SOC_DAIFMT_RIGHT_J: 1259 aif1 |= 0x1; 1260 break; 1261 case SND_SOC_DAIFMT_LEFT_J: 1262 break; 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 /* Clock inversion */ 1268 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1269 case SND_SOC_DAIFMT_DSP_A: 1270 case SND_SOC_DAIFMT_DSP_B: 1271 /* frame inversion not valid for DSP modes */ 1272 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1273 case SND_SOC_DAIFMT_NB_NF: 1274 break; 1275 case SND_SOC_DAIFMT_IB_NF: 1276 aif1 |= WM8903_AIF_BCLK_INV; 1277 break; 1278 default: 1279 return -EINVAL; 1280 } 1281 break; 1282 case SND_SOC_DAIFMT_I2S: 1283 case SND_SOC_DAIFMT_RIGHT_J: 1284 case SND_SOC_DAIFMT_LEFT_J: 1285 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1286 case SND_SOC_DAIFMT_NB_NF: 1287 break; 1288 case SND_SOC_DAIFMT_IB_IF: 1289 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1290 break; 1291 case SND_SOC_DAIFMT_IB_NF: 1292 aif1 |= WM8903_AIF_BCLK_INV; 1293 break; 1294 case SND_SOC_DAIFMT_NB_IF: 1295 aif1 |= WM8903_AIF_LRCLK_INV; 1296 break; 1297 default: 1298 return -EINVAL; 1299 } 1300 break; 1301 default: 1302 return -EINVAL; 1303 } 1304 1305 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1306 1307 return 0; 1308 } 1309 1310 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1311 { 1312 struct snd_soc_codec *codec = codec_dai->codec; 1313 u16 reg; 1314 1315 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1316 1317 if (mute) 1318 reg |= WM8903_DAC_MUTE; 1319 else 1320 reg &= ~WM8903_DAC_MUTE; 1321 1322 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1323 1324 return 0; 1325 } 1326 1327 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1328 * for optimal performance so we list the lower rates first and match 1329 * on the last match we find. */ 1330 static struct { 1331 int div; 1332 int rate; 1333 int mode; 1334 int mclk_div; 1335 } clk_sys_ratios[] = { 1336 { 64, 0x0, 0x0, 1 }, 1337 { 68, 0x0, 0x1, 1 }, 1338 { 125, 0x0, 0x2, 1 }, 1339 { 128, 0x1, 0x0, 1 }, 1340 { 136, 0x1, 0x1, 1 }, 1341 { 192, 0x2, 0x0, 1 }, 1342 { 204, 0x2, 0x1, 1 }, 1343 1344 { 64, 0x0, 0x0, 2 }, 1345 { 68, 0x0, 0x1, 2 }, 1346 { 125, 0x0, 0x2, 2 }, 1347 { 128, 0x1, 0x0, 2 }, 1348 { 136, 0x1, 0x1, 2 }, 1349 { 192, 0x2, 0x0, 2 }, 1350 { 204, 0x2, 0x1, 2 }, 1351 1352 { 250, 0x2, 0x2, 1 }, 1353 { 256, 0x3, 0x0, 1 }, 1354 { 272, 0x3, 0x1, 1 }, 1355 { 384, 0x4, 0x0, 1 }, 1356 { 408, 0x4, 0x1, 1 }, 1357 { 375, 0x4, 0x2, 1 }, 1358 { 512, 0x5, 0x0, 1 }, 1359 { 544, 0x5, 0x1, 1 }, 1360 { 500, 0x5, 0x2, 1 }, 1361 { 768, 0x6, 0x0, 1 }, 1362 { 816, 0x6, 0x1, 1 }, 1363 { 750, 0x6, 0x2, 1 }, 1364 { 1024, 0x7, 0x0, 1 }, 1365 { 1088, 0x7, 0x1, 1 }, 1366 { 1000, 0x7, 0x2, 1 }, 1367 { 1408, 0x8, 0x0, 1 }, 1368 { 1496, 0x8, 0x1, 1 }, 1369 { 1536, 0x9, 0x0, 1 }, 1370 { 1632, 0x9, 0x1, 1 }, 1371 { 1500, 0x9, 0x2, 1 }, 1372 1373 { 250, 0x2, 0x2, 2 }, 1374 { 256, 0x3, 0x0, 2 }, 1375 { 272, 0x3, 0x1, 2 }, 1376 { 384, 0x4, 0x0, 2 }, 1377 { 408, 0x4, 0x1, 2 }, 1378 { 375, 0x4, 0x2, 2 }, 1379 { 512, 0x5, 0x0, 2 }, 1380 { 544, 0x5, 0x1, 2 }, 1381 { 500, 0x5, 0x2, 2 }, 1382 { 768, 0x6, 0x0, 2 }, 1383 { 816, 0x6, 0x1, 2 }, 1384 { 750, 0x6, 0x2, 2 }, 1385 { 1024, 0x7, 0x0, 2 }, 1386 { 1088, 0x7, 0x1, 2 }, 1387 { 1000, 0x7, 0x2, 2 }, 1388 { 1408, 0x8, 0x0, 2 }, 1389 { 1496, 0x8, 0x1, 2 }, 1390 { 1536, 0x9, 0x0, 2 }, 1391 { 1632, 0x9, 0x1, 2 }, 1392 { 1500, 0x9, 0x2, 2 }, 1393 }; 1394 1395 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1396 static struct { 1397 int ratio; 1398 int div; 1399 } bclk_divs[] = { 1400 { 10, 0 }, 1401 { 20, 2 }, 1402 { 30, 3 }, 1403 { 40, 4 }, 1404 { 50, 5 }, 1405 { 60, 7 }, 1406 { 80, 8 }, 1407 { 100, 9 }, 1408 { 120, 11 }, 1409 { 160, 12 }, 1410 { 200, 13 }, 1411 { 220, 14 }, 1412 { 240, 15 }, 1413 { 300, 17 }, 1414 { 320, 18 }, 1415 { 440, 19 }, 1416 { 480, 20 }, 1417 }; 1418 1419 /* Sample rates for DSP */ 1420 static struct { 1421 int rate; 1422 int value; 1423 } sample_rates[] = { 1424 { 8000, 0 }, 1425 { 11025, 1 }, 1426 { 12000, 2 }, 1427 { 16000, 3 }, 1428 { 22050, 4 }, 1429 { 24000, 5 }, 1430 { 32000, 6 }, 1431 { 44100, 7 }, 1432 { 48000, 8 }, 1433 { 88200, 9 }, 1434 { 96000, 10 }, 1435 { 0, 0 }, 1436 }; 1437 1438 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1439 struct snd_pcm_hw_params *params, 1440 struct snd_soc_dai *dai) 1441 { 1442 struct snd_soc_codec *codec = dai->codec; 1443 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1444 int fs = params_rate(params); 1445 int bclk; 1446 int bclk_div; 1447 int i; 1448 int dsp_config; 1449 int clk_config; 1450 int best_val; 1451 int cur_val; 1452 int clk_sys; 1453 1454 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1455 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1456 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1457 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1458 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1459 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1460 1461 /* Enable sloping stopband filter for low sample rates */ 1462 if (fs <= 24000) 1463 dac_digital1 |= WM8903_DAC_SB_FILT; 1464 else 1465 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1466 1467 /* Configure sample rate logic for DSP - choose nearest rate */ 1468 dsp_config = 0; 1469 best_val = abs(sample_rates[dsp_config].rate - fs); 1470 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1471 cur_val = abs(sample_rates[i].rate - fs); 1472 if (cur_val <= best_val) { 1473 dsp_config = i; 1474 best_val = cur_val; 1475 } 1476 } 1477 1478 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1479 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1480 clock1 |= sample_rates[dsp_config].value; 1481 1482 aif1 &= ~WM8903_AIF_WL_MASK; 1483 bclk = 2 * fs; 1484 switch (params_format(params)) { 1485 case SNDRV_PCM_FORMAT_S16_LE: 1486 bclk *= 16; 1487 break; 1488 case SNDRV_PCM_FORMAT_S20_3LE: 1489 bclk *= 20; 1490 aif1 |= 0x4; 1491 break; 1492 case SNDRV_PCM_FORMAT_S24_LE: 1493 bclk *= 24; 1494 aif1 |= 0x8; 1495 break; 1496 case SNDRV_PCM_FORMAT_S32_LE: 1497 bclk *= 32; 1498 aif1 |= 0xc; 1499 break; 1500 default: 1501 return -EINVAL; 1502 } 1503 1504 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1505 wm8903->sysclk, fs); 1506 1507 /* We may not have an MCLK which allows us to generate exactly 1508 * the clock we want, particularly with USB derived inputs, so 1509 * approximate. 1510 */ 1511 clk_config = 0; 1512 best_val = abs((wm8903->sysclk / 1513 (clk_sys_ratios[0].mclk_div * 1514 clk_sys_ratios[0].div)) - fs); 1515 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1516 cur_val = abs((wm8903->sysclk / 1517 (clk_sys_ratios[i].mclk_div * 1518 clk_sys_ratios[i].div)) - fs); 1519 1520 if (cur_val <= best_val) { 1521 clk_config = i; 1522 best_val = cur_val; 1523 } 1524 } 1525 1526 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1527 clock0 |= WM8903_MCLKDIV2; 1528 clk_sys = wm8903->sysclk / 2; 1529 } else { 1530 clock0 &= ~WM8903_MCLKDIV2; 1531 clk_sys = wm8903->sysclk; 1532 } 1533 1534 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1535 WM8903_CLK_SYS_MODE_MASK); 1536 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1537 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1538 1539 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1540 clk_sys_ratios[clk_config].rate, 1541 clk_sys_ratios[clk_config].mode, 1542 clk_sys_ratios[clk_config].div); 1543 1544 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1545 1546 /* We may not get quite the right frequency if using 1547 * approximate clocks so look for the closest match that is 1548 * higher than the target (we need to ensure that there enough 1549 * BCLKs to clock out the samples). 1550 */ 1551 bclk_div = 0; 1552 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1553 i = 1; 1554 while (i < ARRAY_SIZE(bclk_divs)) { 1555 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1556 if (cur_val < 0) /* BCLK table is sorted */ 1557 break; 1558 bclk_div = i; 1559 best_val = cur_val; 1560 i++; 1561 } 1562 1563 aif2 &= ~WM8903_BCLK_DIV_MASK; 1564 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1565 1566 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1567 bclk_divs[bclk_div].ratio / 10, bclk, 1568 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1569 1570 aif2 |= bclk_divs[bclk_div].div; 1571 aif3 |= bclk / fs; 1572 1573 wm8903->fs = params_rate(params); 1574 wm8903_set_deemph(codec); 1575 1576 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1577 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1578 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1579 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1580 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1581 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1582 1583 return 0; 1584 } 1585 1586 /** 1587 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1588 * 1589 * @codec: WM8903 codec 1590 * @jack: jack to report detection events on 1591 * @det: value to report for presence detection 1592 * @shrt: value to report for short detection 1593 * 1594 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1595 * being used to bring out signals to the processor then only platform 1596 * data configuration is needed for WM8903 and processor GPIOs should 1597 * be configured using snd_soc_jack_add_gpios() instead. 1598 * 1599 * The current threasholds for detection should be configured using 1600 * micdet_cfg in the platform data. Using this function will force on 1601 * the microphone bias for the device. 1602 */ 1603 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1604 int det, int shrt) 1605 { 1606 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1607 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1608 1609 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1610 det, shrt); 1611 1612 /* Store the configuration */ 1613 wm8903->mic_jack = jack; 1614 wm8903->mic_det = det; 1615 wm8903->mic_short = shrt; 1616 1617 /* Enable interrupts we've got a report configured for */ 1618 if (det) 1619 irq_mask &= ~WM8903_MICDET_EINT; 1620 if (shrt) 1621 irq_mask &= ~WM8903_MICSHRT_EINT; 1622 1623 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1624 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1625 irq_mask); 1626 1627 if (det || shrt) { 1628 /* Enable mic detection, this may not have been set through 1629 * platform data (eg, if the defaults are OK). */ 1630 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1631 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1632 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1633 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1634 } else { 1635 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1636 WM8903_MICDET_ENA, 0); 1637 } 1638 1639 return 0; 1640 } 1641 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1642 1643 static irqreturn_t wm8903_irq(int irq, void *data) 1644 { 1645 struct wm8903_priv *wm8903 = data; 1646 int mic_report, ret; 1647 unsigned int int_val, mask, int_pol; 1648 1649 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK, 1650 &mask); 1651 if (ret != 0) { 1652 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret); 1653 return IRQ_NONE; 1654 } 1655 1656 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val); 1657 if (ret != 0) { 1658 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret); 1659 return IRQ_NONE; 1660 } 1661 1662 int_val &= ~mask; 1663 1664 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1665 dev_warn(wm8903->dev, "Write sequencer done\n"); 1666 } 1667 1668 /* 1669 * The rest is microphone jack detection. We need to manually 1670 * invert the polarity of the interrupt after each event - to 1671 * simplify the code keep track of the last state we reported 1672 * and just invert the relevant bits in both the report and 1673 * the polarity register. 1674 */ 1675 mic_report = wm8903->mic_last_report; 1676 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1677 &int_pol); 1678 if (ret != 0) { 1679 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n", 1680 ret); 1681 return IRQ_HANDLED; 1682 } 1683 1684 #ifndef CONFIG_SND_SOC_WM8903_MODULE 1685 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1686 trace_snd_soc_jack_irq(dev_name(wm8903->dev)); 1687 #endif 1688 1689 if (int_val & WM8903_MICSHRT_EINT) { 1690 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol); 1691 1692 mic_report ^= wm8903->mic_short; 1693 int_pol ^= WM8903_MICSHRT_INV; 1694 } 1695 1696 if (int_val & WM8903_MICDET_EINT) { 1697 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol); 1698 1699 mic_report ^= wm8903->mic_det; 1700 int_pol ^= WM8903_MICDET_INV; 1701 1702 msleep(wm8903->mic_delay); 1703 } 1704 1705 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1706 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1707 1708 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1709 wm8903->mic_short | wm8903->mic_det); 1710 1711 wm8903->mic_last_report = mic_report; 1712 1713 return IRQ_HANDLED; 1714 } 1715 1716 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1717 SNDRV_PCM_RATE_11025 | \ 1718 SNDRV_PCM_RATE_16000 | \ 1719 SNDRV_PCM_RATE_22050 | \ 1720 SNDRV_PCM_RATE_32000 | \ 1721 SNDRV_PCM_RATE_44100 | \ 1722 SNDRV_PCM_RATE_48000 | \ 1723 SNDRV_PCM_RATE_88200 | \ 1724 SNDRV_PCM_RATE_96000) 1725 1726 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1727 SNDRV_PCM_RATE_11025 | \ 1728 SNDRV_PCM_RATE_16000 | \ 1729 SNDRV_PCM_RATE_22050 | \ 1730 SNDRV_PCM_RATE_32000 | \ 1731 SNDRV_PCM_RATE_44100 | \ 1732 SNDRV_PCM_RATE_48000) 1733 1734 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1735 SNDRV_PCM_FMTBIT_S20_3LE |\ 1736 SNDRV_PCM_FMTBIT_S24_LE) 1737 1738 static const struct snd_soc_dai_ops wm8903_dai_ops = { 1739 .hw_params = wm8903_hw_params, 1740 .digital_mute = wm8903_digital_mute, 1741 .set_fmt = wm8903_set_dai_fmt, 1742 .set_sysclk = wm8903_set_dai_sysclk, 1743 }; 1744 1745 static struct snd_soc_dai_driver wm8903_dai = { 1746 .name = "wm8903-hifi", 1747 .playback = { 1748 .stream_name = "Playback", 1749 .channels_min = 2, 1750 .channels_max = 2, 1751 .rates = WM8903_PLAYBACK_RATES, 1752 .formats = WM8903_FORMATS, 1753 }, 1754 .capture = { 1755 .stream_name = "Capture", 1756 .channels_min = 2, 1757 .channels_max = 2, 1758 .rates = WM8903_CAPTURE_RATES, 1759 .formats = WM8903_FORMATS, 1760 }, 1761 .ops = &wm8903_dai_ops, 1762 .symmetric_rates = 1, 1763 }; 1764 1765 static int wm8903_suspend(struct snd_soc_codec *codec) 1766 { 1767 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1768 1769 return 0; 1770 } 1771 1772 static int wm8903_resume(struct snd_soc_codec *codec) 1773 { 1774 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1775 1776 regcache_sync(wm8903->regmap); 1777 1778 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1779 1780 return 0; 1781 } 1782 1783 #ifdef CONFIG_GPIOLIB 1784 static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip) 1785 { 1786 return container_of(chip, struct wm8903_priv, gpio_chip); 1787 } 1788 1789 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1790 { 1791 if (offset >= WM8903_NUM_GPIO) 1792 return -EINVAL; 1793 1794 return 0; 1795 } 1796 1797 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1798 { 1799 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1800 unsigned int mask, val; 1801 int ret; 1802 1803 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1804 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1805 WM8903_GP1_DIR; 1806 1807 ret = regmap_update_bits(wm8903->regmap, 1808 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1809 if (ret < 0) 1810 return ret; 1811 1812 return 0; 1813 } 1814 1815 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1816 { 1817 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1818 unsigned int reg; 1819 1820 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®); 1821 1822 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT; 1823 } 1824 1825 static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1826 unsigned offset, int value) 1827 { 1828 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1829 unsigned int mask, val; 1830 int ret; 1831 1832 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1833 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1834 (value << WM8903_GP2_LVL_SHIFT); 1835 1836 ret = regmap_update_bits(wm8903->regmap, 1837 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1838 if (ret < 0) 1839 return ret; 1840 1841 return 0; 1842 } 1843 1844 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1845 { 1846 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1847 1848 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, 1849 WM8903_GP1_LVL_MASK, 1850 !!value << WM8903_GP1_LVL_SHIFT); 1851 } 1852 1853 static struct gpio_chip wm8903_template_chip = { 1854 .label = "wm8903", 1855 .owner = THIS_MODULE, 1856 .request = wm8903_gpio_request, 1857 .direction_input = wm8903_gpio_direction_in, 1858 .get = wm8903_gpio_get, 1859 .direction_output = wm8903_gpio_direction_out, 1860 .set = wm8903_gpio_set, 1861 .can_sleep = 1, 1862 }; 1863 1864 static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1865 { 1866 struct wm8903_platform_data *pdata = wm8903->pdata; 1867 int ret; 1868 1869 wm8903->gpio_chip = wm8903_template_chip; 1870 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1871 wm8903->gpio_chip.dev = wm8903->dev; 1872 1873 if (pdata->gpio_base) 1874 wm8903->gpio_chip.base = pdata->gpio_base; 1875 else 1876 wm8903->gpio_chip.base = -1; 1877 1878 ret = gpiochip_add(&wm8903->gpio_chip); 1879 if (ret != 0) 1880 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret); 1881 } 1882 1883 static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1884 { 1885 int ret; 1886 1887 ret = gpiochip_remove(&wm8903->gpio_chip); 1888 if (ret != 0) 1889 dev_err(wm8903->dev, "Failed to remove GPIOs: %d\n", ret); 1890 } 1891 #else 1892 static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1893 { 1894 } 1895 1896 static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1897 { 1898 } 1899 #endif 1900 1901 static int wm8903_probe(struct snd_soc_codec *codec) 1902 { 1903 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1904 int ret; 1905 1906 wm8903->codec = codec; 1907 codec->control_data = wm8903->regmap; 1908 1909 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); 1910 if (ret != 0) { 1911 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1912 return ret; 1913 } 1914 1915 /* power on device */ 1916 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1917 1918 return ret; 1919 } 1920 1921 /* power down chip */ 1922 static int wm8903_remove(struct snd_soc_codec *codec) 1923 { 1924 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1925 1926 return 0; 1927 } 1928 1929 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { 1930 .probe = wm8903_probe, 1931 .remove = wm8903_remove, 1932 .suspend = wm8903_suspend, 1933 .resume = wm8903_resume, 1934 .set_bias_level = wm8903_set_bias_level, 1935 .seq_notifier = wm8903_seq_notifier, 1936 .controls = wm8903_snd_controls, 1937 .num_controls = ARRAY_SIZE(wm8903_snd_controls), 1938 .dapm_widgets = wm8903_dapm_widgets, 1939 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets), 1940 .dapm_routes = wm8903_intercon, 1941 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon), 1942 }; 1943 1944 static const struct regmap_config wm8903_regmap = { 1945 .reg_bits = 8, 1946 .val_bits = 16, 1947 1948 .max_register = WM8903_MAX_REGISTER, 1949 .volatile_reg = wm8903_volatile_register, 1950 .readable_reg = wm8903_readable_register, 1951 1952 .cache_type = REGCACHE_RBTREE, 1953 .reg_defaults = wm8903_reg_defaults, 1954 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults), 1955 }; 1956 1957 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c, 1958 struct wm8903_platform_data *pdata) 1959 { 1960 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 1961 if (!irq_data) { 1962 dev_err(&i2c->dev, "Invalid IRQ: %d\n", 1963 i2c->irq); 1964 return -EINVAL; 1965 } 1966 1967 switch (irqd_get_trigger_type(irq_data)) { 1968 case IRQ_TYPE_NONE: 1969 default: 1970 /* 1971 * We assume the controller imposes no restrictions, 1972 * so we are able to select active-high 1973 */ 1974 /* Fall-through */ 1975 case IRQ_TYPE_LEVEL_HIGH: 1976 pdata->irq_active_low = false; 1977 break; 1978 case IRQ_TYPE_LEVEL_LOW: 1979 pdata->irq_active_low = true; 1980 break; 1981 } 1982 1983 return 0; 1984 } 1985 1986 static int wm8903_set_pdata_from_of(struct i2c_client *i2c, 1987 struct wm8903_platform_data *pdata) 1988 { 1989 const struct device_node *np = i2c->dev.of_node; 1990 u32 val32; 1991 int i; 1992 1993 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0) 1994 pdata->micdet_cfg = val32; 1995 1996 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0) 1997 pdata->micdet_delay = val32; 1998 1999 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg, 2000 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) { 2001 /* 2002 * In device tree: 0 means "write 0", 2003 * 0xffffffff means "don't touch". 2004 * 2005 * In platform data: 0 means "don't touch", 2006 * 0x8000 means "write 0". 2007 * 2008 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000. 2009 * 2010 * Convert from DT to pdata representation here, 2011 * so no other code needs to change. 2012 */ 2013 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2014 if (pdata->gpio_cfg[i] == 0) { 2015 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO; 2016 } else if (pdata->gpio_cfg[i] == 0xffffffff) { 2017 pdata->gpio_cfg[i] = 0; 2018 } else if (pdata->gpio_cfg[i] > 0x7fff) { 2019 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n", 2020 i, pdata->gpio_cfg[i]); 2021 return -EINVAL; 2022 } 2023 } 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int wm8903_i2c_probe(struct i2c_client *i2c, 2030 const struct i2c_device_id *id) 2031 { 2032 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 2033 struct wm8903_priv *wm8903; 2034 int trigger; 2035 bool mic_gpio = false; 2036 unsigned int val, irq_pol; 2037 int ret, i; 2038 2039 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv), 2040 GFP_KERNEL); 2041 if (wm8903 == NULL) 2042 return -ENOMEM; 2043 wm8903->dev = &i2c->dev; 2044 2045 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap); 2046 if (IS_ERR(wm8903->regmap)) { 2047 ret = PTR_ERR(wm8903->regmap); 2048 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2049 ret); 2050 return ret; 2051 } 2052 2053 i2c_set_clientdata(i2c, wm8903); 2054 2055 /* If no platform data was supplied, create storage for defaults */ 2056 if (pdata) { 2057 wm8903->pdata = pdata; 2058 } else { 2059 wm8903->pdata = devm_kzalloc(&i2c->dev, 2060 sizeof(struct wm8903_platform_data), 2061 GFP_KERNEL); 2062 if (wm8903->pdata == NULL) { 2063 dev_err(&i2c->dev, "Failed to allocate pdata\n"); 2064 return -ENOMEM; 2065 } 2066 2067 if (i2c->irq) { 2068 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata); 2069 if (ret != 0) 2070 return ret; 2071 } 2072 2073 if (i2c->dev.of_node) { 2074 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata); 2075 if (ret != 0) 2076 return ret; 2077 } 2078 } 2079 2080 pdata = wm8903->pdata; 2081 2082 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); 2083 if (ret != 0) { 2084 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 2085 goto err; 2086 } 2087 if (val != 0x8903) { 2088 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); 2089 ret = -ENODEV; 2090 goto err; 2091 } 2092 2093 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); 2094 if (ret != 0) { 2095 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret); 2096 goto err; 2097 } 2098 dev_info(&i2c->dev, "WM8903 revision %c\n", 2099 (val & WM8903_CHIP_REV_MASK) + 'A'); 2100 2101 /* Reset the device */ 2102 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903); 2103 2104 wm8903_init_gpio(wm8903); 2105 2106 /* Set up GPIO pin state, detect if any are MIC detect outputs */ 2107 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2108 if ((!pdata->gpio_cfg[i]) || 2109 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO)) 2110 continue; 2111 2112 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i, 2113 pdata->gpio_cfg[i] & 0x7fff); 2114 2115 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 2116 >> WM8903_GP1_FN_SHIFT; 2117 2118 switch (val) { 2119 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 2120 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 2121 mic_gpio = true; 2122 break; 2123 default: 2124 break; 2125 } 2126 } 2127 2128 /* Set up microphone detection */ 2129 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0, 2130 pdata->micdet_cfg); 2131 2132 /* Microphone detection needs the WSEQ clock */ 2133 if (pdata->micdet_cfg) 2134 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0, 2135 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 2136 2137 /* If microphone detection is enabled by pdata but 2138 * detected via IRQ then interrupts can be lost before 2139 * the machine driver has set up microphone detection 2140 * IRQs as the IRQs are clear on read. The detection 2141 * will be enabled when the machine driver configures. 2142 */ 2143 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 2144 2145 wm8903->mic_delay = pdata->micdet_delay; 2146 2147 if (i2c->irq) { 2148 if (pdata->irq_active_low) { 2149 trigger = IRQF_TRIGGER_LOW; 2150 irq_pol = WM8903_IRQ_POL; 2151 } else { 2152 trigger = IRQF_TRIGGER_HIGH; 2153 irq_pol = 0; 2154 } 2155 2156 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL, 2157 WM8903_IRQ_POL, irq_pol); 2158 2159 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq, 2160 trigger | IRQF_ONESHOT, 2161 "wm8903", wm8903); 2162 if (ret != 0) { 2163 dev_err(wm8903->dev, "Failed to request IRQ: %d\n", 2164 ret); 2165 return ret; 2166 } 2167 2168 /* Enable write sequencer interrupts */ 2169 regmap_update_bits(wm8903->regmap, 2170 WM8903_INTERRUPT_STATUS_1_MASK, 2171 WM8903_IM_WSEQ_BUSY_EINT, 0); 2172 } 2173 2174 /* Latch volume update bits */ 2175 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT, 2176 WM8903_ADCVU, WM8903_ADCVU); 2177 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT, 2178 WM8903_ADCVU, WM8903_ADCVU); 2179 2180 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT, 2181 WM8903_DACVU, WM8903_DACVU); 2182 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT, 2183 WM8903_DACVU, WM8903_DACVU); 2184 2185 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT, 2186 WM8903_HPOUTVU, WM8903_HPOUTVU); 2187 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT, 2188 WM8903_HPOUTVU, WM8903_HPOUTVU); 2189 2190 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT, 2191 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2192 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT, 2193 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2194 2195 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT, 2196 WM8903_SPKVU, WM8903_SPKVU); 2197 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT, 2198 WM8903_SPKVU, WM8903_SPKVU); 2199 2200 /* Enable DAC soft mute by default */ 2201 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1, 2202 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2203 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2204 2205 ret = snd_soc_register_codec(&i2c->dev, 2206 &soc_codec_dev_wm8903, &wm8903_dai, 1); 2207 if (ret != 0) 2208 goto err; 2209 2210 return 0; 2211 err: 2212 return ret; 2213 } 2214 2215 static int wm8903_i2c_remove(struct i2c_client *client) 2216 { 2217 struct wm8903_priv *wm8903 = i2c_get_clientdata(client); 2218 2219 if (client->irq) 2220 free_irq(client->irq, wm8903); 2221 wm8903_free_gpio(wm8903); 2222 snd_soc_unregister_codec(&client->dev); 2223 2224 return 0; 2225 } 2226 2227 static const struct of_device_id wm8903_of_match[] = { 2228 { .compatible = "wlf,wm8903", }, 2229 {}, 2230 }; 2231 MODULE_DEVICE_TABLE(of, wm8903_of_match); 2232 2233 static const struct i2c_device_id wm8903_i2c_id[] = { 2234 { "wm8903", 0 }, 2235 { } 2236 }; 2237 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2238 2239 static struct i2c_driver wm8903_i2c_driver = { 2240 .driver = { 2241 .name = "wm8903", 2242 .owner = THIS_MODULE, 2243 .of_match_table = wm8903_of_match, 2244 }, 2245 .probe = wm8903_i2c_probe, 2246 .remove = wm8903_i2c_remove, 2247 .id_table = wm8903_i2c_id, 2248 }; 2249 2250 module_i2c_driver(wm8903_i2c_driver); 2251 2252 MODULE_DESCRIPTION("ASoC WM8903 driver"); 2253 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2254 MODULE_LICENSE("GPL"); 2255