1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008-12 Wolfson Microelectronics 5 * Copyright 2011-2012 NVIDIA, Inc. 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: 14 * - TDM mode configuration. 15 * - Digital microphone support. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/init.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/slab.h> 29 #include <linux/irq.h> 30 #include <linux/mutex.h> 31 #include <sound/core.h> 32 #include <sound/jack.h> 33 #include <sound/pcm.h> 34 #include <sound/pcm_params.h> 35 #include <sound/tlv.h> 36 #include <sound/soc.h> 37 #include <sound/initval.h> 38 #include <sound/wm8903.h> 39 #include <trace/events/asoc.h> 40 41 #include "wm8903.h" 42 43 /* Register defaults at reset */ 44 static const struct reg_default wm8903_reg_defaults[] = { 45 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 46 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 47 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 48 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 49 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 50 { 12, 0x0000 }, /* R12 - Power Management 0 */ 51 { 13, 0x0000 }, /* R13 - Power Management 1 */ 52 { 14, 0x0000 }, /* R14 - Power Management 2 */ 53 { 15, 0x0000 }, /* R15 - Power Management 3 */ 54 { 16, 0x0000 }, /* R16 - Power Management 4 */ 55 { 17, 0x0000 }, /* R17 - Power Management 5 */ 56 { 18, 0x0000 }, /* R18 - Power Management 6 */ 57 { 20, 0x0400 }, /* R20 - Clock Rates 0 */ 58 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */ 59 { 22, 0x0000 }, /* R22 - Clock Rates 2 */ 60 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 61 { 25, 0x0242 }, /* R25 - Audio Interface 1 */ 62 { 26, 0x0008 }, /* R26 - Audio Interface 2 */ 63 { 27, 0x0022 }, /* R27 - Audio Interface 3 */ 64 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 65 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 66 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 67 { 33, 0x0000 }, /* R33 - DAC Digital 1 */ 68 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 69 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 70 { 38, 0x0000 }, /* R38 - ADC Digital 0 */ 71 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */ 72 { 40, 0x09BF }, /* R40 - DRC 0 */ 73 { 41, 0x3241 }, /* R41 - DRC 1 */ 74 { 42, 0x0020 }, /* R42 - DRC 2 */ 75 { 43, 0x0000 }, /* R43 - DRC 3 */ 76 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 77 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 78 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 79 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 80 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */ 81 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */ 82 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */ 83 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */ 84 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */ 85 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */ 86 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 87 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 88 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 89 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 90 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */ 91 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */ 92 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */ 93 { 67, 0x0010 }, /* R67 - DC Servo 0 */ 94 { 69, 0x00A4 }, /* R69 - DC Servo 2 */ 95 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 96 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 97 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 98 { 104, 0x0000 }, /* R104 - Class W 0 */ 99 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 100 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 101 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 102 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 103 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 104 { 114, 0x0000 }, /* R114 - Control Interface */ 105 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */ 106 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */ 107 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */ 108 { 119, 0x0220 }, /* R119 - GPIO Control 4 */ 109 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */ 110 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */ 111 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */ 112 { 126, 0x0000 }, /* R126 - Interrupt Control */ 113 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */ 114 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */ 115 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */ 116 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */ 117 }; 118 119 #define WM8903_NUM_SUPPLIES 4 120 static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = { 121 "AVDD", 122 "CPVDD", 123 "DBVDD", 124 "DCVDD", 125 }; 126 127 struct wm8903_priv { 128 struct wm8903_platform_data *pdata; 129 struct device *dev; 130 struct regmap *regmap; 131 struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES]; 132 133 int sysclk; 134 int irq; 135 136 struct mutex lock; 137 int fs; 138 int deemph; 139 140 int dcs_pending; 141 int dcs_cache[4]; 142 143 /* Reference count */ 144 int class_w_users; 145 146 struct snd_soc_jack *mic_jack; 147 int mic_det; 148 int mic_short; 149 int mic_last_report; 150 int mic_delay; 151 152 #ifdef CONFIG_GPIOLIB 153 struct gpio_chip gpio_chip; 154 #endif 155 }; 156 157 static bool wm8903_readable_register(struct device *dev, unsigned int reg) 158 { 159 switch (reg) { 160 case WM8903_SW_RESET_AND_ID: 161 case WM8903_REVISION_NUMBER: 162 case WM8903_BIAS_CONTROL_0: 163 case WM8903_VMID_CONTROL_0: 164 case WM8903_MIC_BIAS_CONTROL_0: 165 case WM8903_ANALOGUE_DAC_0: 166 case WM8903_ANALOGUE_ADC_0: 167 case WM8903_POWER_MANAGEMENT_0: 168 case WM8903_POWER_MANAGEMENT_1: 169 case WM8903_POWER_MANAGEMENT_2: 170 case WM8903_POWER_MANAGEMENT_3: 171 case WM8903_POWER_MANAGEMENT_4: 172 case WM8903_POWER_MANAGEMENT_5: 173 case WM8903_POWER_MANAGEMENT_6: 174 case WM8903_CLOCK_RATES_0: 175 case WM8903_CLOCK_RATES_1: 176 case WM8903_CLOCK_RATES_2: 177 case WM8903_AUDIO_INTERFACE_0: 178 case WM8903_AUDIO_INTERFACE_1: 179 case WM8903_AUDIO_INTERFACE_2: 180 case WM8903_AUDIO_INTERFACE_3: 181 case WM8903_DAC_DIGITAL_VOLUME_LEFT: 182 case WM8903_DAC_DIGITAL_VOLUME_RIGHT: 183 case WM8903_DAC_DIGITAL_0: 184 case WM8903_DAC_DIGITAL_1: 185 case WM8903_ADC_DIGITAL_VOLUME_LEFT: 186 case WM8903_ADC_DIGITAL_VOLUME_RIGHT: 187 case WM8903_ADC_DIGITAL_0: 188 case WM8903_DIGITAL_MICROPHONE_0: 189 case WM8903_DRC_0: 190 case WM8903_DRC_1: 191 case WM8903_DRC_2: 192 case WM8903_DRC_3: 193 case WM8903_ANALOGUE_LEFT_INPUT_0: 194 case WM8903_ANALOGUE_RIGHT_INPUT_0: 195 case WM8903_ANALOGUE_LEFT_INPUT_1: 196 case WM8903_ANALOGUE_RIGHT_INPUT_1: 197 case WM8903_ANALOGUE_LEFT_MIX_0: 198 case WM8903_ANALOGUE_RIGHT_MIX_0: 199 case WM8903_ANALOGUE_SPK_MIX_LEFT_0: 200 case WM8903_ANALOGUE_SPK_MIX_LEFT_1: 201 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0: 202 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1: 203 case WM8903_ANALOGUE_OUT1_LEFT: 204 case WM8903_ANALOGUE_OUT1_RIGHT: 205 case WM8903_ANALOGUE_OUT2_LEFT: 206 case WM8903_ANALOGUE_OUT2_RIGHT: 207 case WM8903_ANALOGUE_OUT3_LEFT: 208 case WM8903_ANALOGUE_OUT3_RIGHT: 209 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0: 210 case WM8903_DC_SERVO_0: 211 case WM8903_DC_SERVO_2: 212 case WM8903_DC_SERVO_READBACK_1: 213 case WM8903_DC_SERVO_READBACK_2: 214 case WM8903_DC_SERVO_READBACK_3: 215 case WM8903_DC_SERVO_READBACK_4: 216 case WM8903_ANALOGUE_HP_0: 217 case WM8903_ANALOGUE_LINEOUT_0: 218 case WM8903_CHARGE_PUMP_0: 219 case WM8903_CLASS_W_0: 220 case WM8903_WRITE_SEQUENCER_0: 221 case WM8903_WRITE_SEQUENCER_1: 222 case WM8903_WRITE_SEQUENCER_2: 223 case WM8903_WRITE_SEQUENCER_3: 224 case WM8903_WRITE_SEQUENCER_4: 225 case WM8903_CONTROL_INTERFACE: 226 case WM8903_GPIO_CONTROL_1: 227 case WM8903_GPIO_CONTROL_2: 228 case WM8903_GPIO_CONTROL_3: 229 case WM8903_GPIO_CONTROL_4: 230 case WM8903_GPIO_CONTROL_5: 231 case WM8903_INTERRUPT_STATUS_1: 232 case WM8903_INTERRUPT_STATUS_1_MASK: 233 case WM8903_INTERRUPT_POLARITY_1: 234 case WM8903_INTERRUPT_CONTROL: 235 case WM8903_CLOCK_RATE_TEST_4: 236 case WM8903_ANALOGUE_OUTPUT_BIAS_0: 237 return true; 238 default: 239 return false; 240 } 241 } 242 243 static bool wm8903_volatile_register(struct device *dev, unsigned int reg) 244 { 245 switch (reg) { 246 case WM8903_SW_RESET_AND_ID: 247 case WM8903_REVISION_NUMBER: 248 case WM8903_INTERRUPT_STATUS_1: 249 case WM8903_WRITE_SEQUENCER_4: 250 case WM8903_DC_SERVO_READBACK_1: 251 case WM8903_DC_SERVO_READBACK_2: 252 case WM8903_DC_SERVO_READBACK_3: 253 case WM8903_DC_SERVO_READBACK_4: 254 return 1; 255 256 default: 257 return 0; 258 } 259 } 260 261 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 262 struct snd_kcontrol *kcontrol, int event) 263 { 264 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 265 mdelay(4); 266 267 return 0; 268 } 269 270 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 271 struct snd_kcontrol *kcontrol, int event) 272 { 273 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 274 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 275 276 switch (event) { 277 case SND_SOC_DAPM_POST_PMU: 278 wm8903->dcs_pending |= 1 << w->shift; 279 break; 280 case SND_SOC_DAPM_PRE_PMD: 281 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0, 282 1 << w->shift, 0); 283 break; 284 } 285 286 return 0; 287 } 288 289 #define WM8903_DCS_MODE_WRITE_STOP 0 290 #define WM8903_DCS_MODE_START_STOP 2 291 292 static void wm8903_seq_notifier(struct snd_soc_component *component, 293 enum snd_soc_dapm_type event, int subseq) 294 { 295 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 296 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 297 int i, val; 298 299 /* Complete any pending DC servo starts */ 300 if (wm8903->dcs_pending) { 301 dev_dbg(component->dev, "Starting DC servo for %x\n", 302 wm8903->dcs_pending); 303 304 /* If we've no cached values then we need to do startup */ 305 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 306 if (!(wm8903->dcs_pending & (1 << i))) 307 continue; 308 309 if (wm8903->dcs_cache[i]) { 310 dev_dbg(component->dev, 311 "Restore DC servo %d value %x\n", 312 3 - i, wm8903->dcs_cache[i]); 313 314 snd_soc_component_write(component, WM8903_DC_SERVO_4 + i, 315 wm8903->dcs_cache[i] & 0xff); 316 } else { 317 dev_dbg(component->dev, 318 "Calibrate DC servo %d\n", 3 - i); 319 dcs_mode = WM8903_DCS_MODE_START_STOP; 320 } 321 } 322 323 /* Don't trust the cache for analogue */ 324 if (wm8903->class_w_users) 325 dcs_mode = WM8903_DCS_MODE_START_STOP; 326 327 snd_soc_component_update_bits(component, WM8903_DC_SERVO_2, 328 WM8903_DCS_MODE_MASK, dcs_mode); 329 330 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0, 331 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 332 333 switch (dcs_mode) { 334 case WM8903_DCS_MODE_WRITE_STOP: 335 break; 336 337 case WM8903_DCS_MODE_START_STOP: 338 msleep(270); 339 340 /* Cache the measured offsets for digital */ 341 if (wm8903->class_w_users) 342 break; 343 344 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 345 if (!(wm8903->dcs_pending & (1 << i))) 346 continue; 347 348 val = snd_soc_component_read32(component, 349 WM8903_DC_SERVO_READBACK_1 + i); 350 dev_dbg(component->dev, "DC servo %d: %x\n", 351 3 - i, val); 352 wm8903->dcs_cache[i] = val; 353 } 354 break; 355 356 default: 357 pr_warn("DCS mode %d delay not set\n", dcs_mode); 358 break; 359 } 360 361 wm8903->dcs_pending = 0; 362 } 363 } 364 365 /* 366 * When used with DAC outputs only the WM8903 charge pump supports 367 * operation in class W mode, providing very low power consumption 368 * when used with digital sources. Enable and disable this mode 369 * automatically depending on the mixer configuration. 370 * 371 * All the relevant controls are simple switches. 372 */ 373 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 374 struct snd_ctl_elem_value *ucontrol) 375 { 376 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 377 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 378 u16 reg; 379 int ret; 380 381 reg = snd_soc_component_read32(component, WM8903_CLASS_W_0); 382 383 /* Turn it off if we're about to enable bypass */ 384 if (ucontrol->value.integer.value[0]) { 385 if (wm8903->class_w_users == 0) { 386 dev_dbg(component->dev, "Disabling Class W\n"); 387 snd_soc_component_write(component, WM8903_CLASS_W_0, reg & 388 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 389 } 390 wm8903->class_w_users++; 391 } 392 393 /* Implement the change */ 394 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 395 396 /* If we've just disabled the last bypass path turn Class W on */ 397 if (!ucontrol->value.integer.value[0]) { 398 if (wm8903->class_w_users == 1) { 399 dev_dbg(component->dev, "Enabling Class W\n"); 400 snd_soc_component_write(component, WM8903_CLASS_W_0, reg | 401 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 402 } 403 wm8903->class_w_users--; 404 } 405 406 dev_dbg(component->dev, "Bypass use count now %d\n", 407 wm8903->class_w_users); 408 409 return ret; 410 } 411 412 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 413 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 414 snd_soc_dapm_get_volsw, wm8903_class_w_put) 415 416 417 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 418 419 static int wm8903_set_deemph(struct snd_soc_component *component) 420 { 421 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 422 int val, i, best; 423 424 /* If we're using deemphasis select the nearest available sample 425 * rate. 426 */ 427 if (wm8903->deemph) { 428 best = 1; 429 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 430 if (abs(wm8903_deemph[i] - wm8903->fs) < 431 abs(wm8903_deemph[best] - wm8903->fs)) 432 best = i; 433 } 434 435 val = best << WM8903_DEEMPH_SHIFT; 436 } else { 437 best = 0; 438 val = 0; 439 } 440 441 dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n", 442 best, wm8903_deemph[best]); 443 444 return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1, 445 WM8903_DEEMPH_MASK, val); 446 } 447 448 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 449 struct snd_ctl_elem_value *ucontrol) 450 { 451 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 452 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 453 454 ucontrol->value.integer.value[0] = wm8903->deemph; 455 456 return 0; 457 } 458 459 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 460 struct snd_ctl_elem_value *ucontrol) 461 { 462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 463 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 464 unsigned int deemph = ucontrol->value.integer.value[0]; 465 int ret = 0; 466 467 if (deemph > 1) 468 return -EINVAL; 469 470 mutex_lock(&wm8903->lock); 471 if (wm8903->deemph != deemph) { 472 wm8903->deemph = deemph; 473 474 wm8903_set_deemph(component); 475 476 ret = 1; 477 } 478 mutex_unlock(&wm8903->lock); 479 480 return ret; 481 } 482 483 /* ALSA can only do steps of .01dB */ 484 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 485 486 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 487 488 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 489 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 490 491 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 492 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 493 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 494 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 495 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 496 497 static const char *hpf_mode_text[] = { 498 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 499 }; 500 501 static SOC_ENUM_SINGLE_DECL(hpf_mode, 502 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text); 503 504 static const char *osr_text[] = { 505 "Low power", "High performance" 506 }; 507 508 static SOC_ENUM_SINGLE_DECL(adc_osr, 509 WM8903_ANALOGUE_ADC_0, 0, osr_text); 510 511 static SOC_ENUM_SINGLE_DECL(dac_osr, 512 WM8903_DAC_DIGITAL_1, 0, osr_text); 513 514 static const char *drc_slope_text[] = { 515 "1", "1/2", "1/4", "1/8", "1/16", "0" 516 }; 517 518 static SOC_ENUM_SINGLE_DECL(drc_slope_r0, 519 WM8903_DRC_2, 3, drc_slope_text); 520 521 static SOC_ENUM_SINGLE_DECL(drc_slope_r1, 522 WM8903_DRC_2, 0, drc_slope_text); 523 524 static const char *drc_attack_text[] = { 525 "instantaneous", 526 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 527 "46.4ms", "92.8ms", "185.6ms" 528 }; 529 530 static SOC_ENUM_SINGLE_DECL(drc_attack, 531 WM8903_DRC_1, 12, drc_attack_text); 532 533 static const char *drc_decay_text[] = { 534 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 535 "23.87s", "47.56s" 536 }; 537 538 static SOC_ENUM_SINGLE_DECL(drc_decay, 539 WM8903_DRC_1, 8, drc_decay_text); 540 541 static const char *drc_ff_delay_text[] = { 542 "5 samples", "9 samples" 543 }; 544 545 static SOC_ENUM_SINGLE_DECL(drc_ff_delay, 546 WM8903_DRC_0, 5, drc_ff_delay_text); 547 548 static const char *drc_qr_decay_text[] = { 549 "0.725ms", "1.45ms", "5.8ms" 550 }; 551 552 static SOC_ENUM_SINGLE_DECL(drc_qr_decay, 553 WM8903_DRC_1, 4, drc_qr_decay_text); 554 555 static const char *drc_smoothing_text[] = { 556 "Low", "Medium", "High" 557 }; 558 559 static SOC_ENUM_SINGLE_DECL(drc_smoothing, 560 WM8903_DRC_0, 11, drc_smoothing_text); 561 562 static const char *soft_mute_text[] = { 563 "Fast (fs/2)", "Slow (fs/32)" 564 }; 565 566 static SOC_ENUM_SINGLE_DECL(soft_mute, 567 WM8903_DAC_DIGITAL_1, 10, soft_mute_text); 568 569 static const char *mute_mode_text[] = { 570 "Hard", "Soft" 571 }; 572 573 static SOC_ENUM_SINGLE_DECL(mute_mode, 574 WM8903_DAC_DIGITAL_1, 9, mute_mode_text); 575 576 static const char *companding_text[] = { 577 "ulaw", "alaw" 578 }; 579 580 static SOC_ENUM_SINGLE_DECL(dac_companding, 581 WM8903_AUDIO_INTERFACE_0, 0, companding_text); 582 583 static SOC_ENUM_SINGLE_DECL(adc_companding, 584 WM8903_AUDIO_INTERFACE_0, 2, companding_text); 585 586 static const char *input_mode_text[] = { 587 "Single-Ended", "Differential Line", "Differential Mic" 588 }; 589 590 static SOC_ENUM_SINGLE_DECL(linput_mode_enum, 591 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text); 592 593 static SOC_ENUM_SINGLE_DECL(rinput_mode_enum, 594 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text); 595 596 static const char *linput_mux_text[] = { 597 "IN1L", "IN2L", "IN3L" 598 }; 599 600 static SOC_ENUM_SINGLE_DECL(linput_enum, 601 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text); 602 603 static SOC_ENUM_SINGLE_DECL(linput_inv_enum, 604 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text); 605 606 static const char *rinput_mux_text[] = { 607 "IN1R", "IN2R", "IN3R" 608 }; 609 610 static SOC_ENUM_SINGLE_DECL(rinput_enum, 611 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text); 612 613 static SOC_ENUM_SINGLE_DECL(rinput_inv_enum, 614 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text); 615 616 617 static const char *sidetone_text[] = { 618 "None", "Left", "Right" 619 }; 620 621 static SOC_ENUM_SINGLE_DECL(lsidetone_enum, 622 WM8903_DAC_DIGITAL_0, 2, sidetone_text); 623 624 static SOC_ENUM_SINGLE_DECL(rsidetone_enum, 625 WM8903_DAC_DIGITAL_0, 0, sidetone_text); 626 627 static const char *adcinput_text[] = { 628 "ADC", "DMIC" 629 }; 630 631 static SOC_ENUM_SINGLE_DECL(adcinput_enum, 632 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text); 633 634 static const char *aif_text[] = { 635 "Left", "Right" 636 }; 637 638 static SOC_ENUM_SINGLE_DECL(lcapture_enum, 639 WM8903_AUDIO_INTERFACE_0, 7, aif_text); 640 641 static SOC_ENUM_SINGLE_DECL(rcapture_enum, 642 WM8903_AUDIO_INTERFACE_0, 6, aif_text); 643 644 static SOC_ENUM_SINGLE_DECL(lplay_enum, 645 WM8903_AUDIO_INTERFACE_0, 5, aif_text); 646 647 static SOC_ENUM_SINGLE_DECL(rplay_enum, 648 WM8903_AUDIO_INTERFACE_0, 4, aif_text); 649 650 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 651 652 /* Input PGAs - No TLV since the scale depends on PGA mode */ 653 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 654 7, 1, 1), 655 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 656 0, 31, 0), 657 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 658 6, 1, 0), 659 660 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 661 7, 1, 1), 662 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 663 0, 31, 0), 664 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 665 6, 1, 0), 666 667 /* ADCs */ 668 SOC_ENUM("ADC OSR", adc_osr), 669 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 670 SOC_ENUM("HPF Mode", hpf_mode), 671 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 672 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 673 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 674 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 675 drc_tlv_thresh), 676 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 677 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 678 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 679 SOC_ENUM("DRC Attack Rate", drc_attack), 680 SOC_ENUM("DRC Decay Rate", drc_decay), 681 SOC_ENUM("DRC FF Delay", drc_ff_delay), 682 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 683 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 684 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 685 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 686 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 687 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 688 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 689 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 690 691 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 692 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 693 SOC_ENUM("ADC Companding Mode", adc_companding), 694 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 695 696 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 697 12, 0, digital_sidetone_tlv), 698 699 /* DAC */ 700 SOC_ENUM("DAC OSR", dac_osr), 701 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 702 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 703 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 704 SOC_ENUM("DAC Mute Mode", mute_mode), 705 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 706 SOC_ENUM("DAC Companding Mode", dac_companding), 707 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 708 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0, 709 dac_boost_tlv), 710 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 711 wm8903_get_deemph, wm8903_put_deemph), 712 713 /* Headphones */ 714 SOC_DOUBLE_R("Headphone Switch", 715 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 716 8, 1, 1), 717 SOC_DOUBLE_R("Headphone ZC Switch", 718 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 719 6, 1, 0), 720 SOC_DOUBLE_R_TLV("Headphone Volume", 721 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 722 0, 63, 0, out_tlv), 723 724 /* Line out */ 725 SOC_DOUBLE_R("Line Out Switch", 726 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 727 8, 1, 1), 728 SOC_DOUBLE_R("Line Out ZC Switch", 729 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 730 6, 1, 0), 731 SOC_DOUBLE_R_TLV("Line Out Volume", 732 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 733 0, 63, 0, out_tlv), 734 735 /* Speaker */ 736 SOC_DOUBLE_R("Speaker Switch", 737 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 738 SOC_DOUBLE_R("Speaker ZC Switch", 739 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 740 SOC_DOUBLE_R_TLV("Speaker Volume", 741 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 742 0, 63, 0, out_tlv), 743 }; 744 745 static const struct snd_kcontrol_new linput_mode_mux = 746 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 747 748 static const struct snd_kcontrol_new rinput_mode_mux = 749 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 750 751 static const struct snd_kcontrol_new linput_mux = 752 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 753 754 static const struct snd_kcontrol_new linput_inv_mux = 755 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 756 757 static const struct snd_kcontrol_new rinput_mux = 758 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 759 760 static const struct snd_kcontrol_new rinput_inv_mux = 761 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 762 763 static const struct snd_kcontrol_new lsidetone_mux = 764 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 765 766 static const struct snd_kcontrol_new rsidetone_mux = 767 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 768 769 static const struct snd_kcontrol_new adcinput_mux = 770 SOC_DAPM_ENUM("ADC Input", adcinput_enum); 771 772 static const struct snd_kcontrol_new lcapture_mux = 773 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 774 775 static const struct snd_kcontrol_new rcapture_mux = 776 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 777 778 static const struct snd_kcontrol_new lplay_mux = 779 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 780 781 static const struct snd_kcontrol_new rplay_mux = 782 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 783 784 static const struct snd_kcontrol_new left_output_mixer[] = { 785 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 786 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 787 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 788 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 789 }; 790 791 static const struct snd_kcontrol_new right_output_mixer[] = { 792 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 793 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 794 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 795 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 796 }; 797 798 static const struct snd_kcontrol_new left_speaker_mixer[] = { 799 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 800 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 801 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 802 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 803 0, 1, 0), 804 }; 805 806 static const struct snd_kcontrol_new right_speaker_mixer[] = { 807 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 808 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 809 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 810 1, 1, 0), 811 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 812 0, 1, 0), 813 }; 814 815 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 816 SND_SOC_DAPM_INPUT("IN1L"), 817 SND_SOC_DAPM_INPUT("IN1R"), 818 SND_SOC_DAPM_INPUT("IN2L"), 819 SND_SOC_DAPM_INPUT("IN2R"), 820 SND_SOC_DAPM_INPUT("IN3L"), 821 SND_SOC_DAPM_INPUT("IN3R"), 822 SND_SOC_DAPM_INPUT("DMICDAT"), 823 824 SND_SOC_DAPM_OUTPUT("HPOUTL"), 825 SND_SOC_DAPM_OUTPUT("HPOUTR"), 826 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 827 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 828 SND_SOC_DAPM_OUTPUT("LOP"), 829 SND_SOC_DAPM_OUTPUT("LON"), 830 SND_SOC_DAPM_OUTPUT("ROP"), 831 SND_SOC_DAPM_OUTPUT("RON"), 832 833 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 834 835 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 836 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 837 &linput_inv_mux), 838 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 839 840 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 841 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 842 &rinput_inv_mux), 843 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 844 845 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 846 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 847 848 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 849 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 850 851 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 852 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 853 854 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 855 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 856 857 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 858 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 859 860 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 861 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 862 863 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 864 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 865 866 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 867 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 868 869 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 870 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 871 872 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 873 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 874 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 875 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 876 877 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 878 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 879 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 880 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 881 882 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 883 1, 0, NULL, 0), 884 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 885 0, 0, NULL, 0), 886 887 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, 888 NULL, 0), 889 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, 890 NULL, 0), 891 892 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 893 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 894 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 895 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), 896 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 897 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 898 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 899 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), 900 901 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 902 NULL, 0), 903 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 904 NULL, 0), 905 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 906 NULL, 0), 907 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 908 NULL, 0), 909 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 910 NULL, 0), 911 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 912 NULL, 0), 913 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 914 NULL, 0), 915 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 916 NULL, 0), 917 918 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 919 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 920 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 921 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 922 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 923 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 924 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 925 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 926 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 927 928 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 929 NULL, 0), 930 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 931 NULL, 0), 932 933 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 934 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 935 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 936 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 937 }; 938 939 static const struct snd_soc_dapm_route wm8903_intercon[] = { 940 941 { "CLK_DSP", NULL, "CLK_SYS" }, 942 { "MICBIAS", NULL, "CLK_SYS" }, 943 { "HPL_DCS", NULL, "CLK_SYS" }, 944 { "HPR_DCS", NULL, "CLK_SYS" }, 945 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 946 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 947 948 { "Left Input Mux", "IN1L", "IN1L" }, 949 { "Left Input Mux", "IN2L", "IN2L" }, 950 { "Left Input Mux", "IN3L", "IN3L" }, 951 952 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 953 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 954 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 955 956 { "Right Input Mux", "IN1R", "IN1R" }, 957 { "Right Input Mux", "IN2R", "IN2R" }, 958 { "Right Input Mux", "IN3R", "IN3R" }, 959 960 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 961 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 962 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 963 964 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 965 { "Left Input Mode Mux", "Differential Line", 966 "Left Input Mux" }, 967 { "Left Input Mode Mux", "Differential Line", 968 "Left Input Inverting Mux" }, 969 { "Left Input Mode Mux", "Differential Mic", 970 "Left Input Mux" }, 971 { "Left Input Mode Mux", "Differential Mic", 972 "Left Input Inverting Mux" }, 973 974 { "Right Input Mode Mux", "Single-Ended", 975 "Right Input Inverting Mux" }, 976 { "Right Input Mode Mux", "Differential Line", 977 "Right Input Mux" }, 978 { "Right Input Mode Mux", "Differential Line", 979 "Right Input Inverting Mux" }, 980 { "Right Input Mode Mux", "Differential Mic", 981 "Right Input Mux" }, 982 { "Right Input Mode Mux", "Differential Mic", 983 "Right Input Inverting Mux" }, 984 985 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 986 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 987 988 { "Left ADC Input", "ADC", "Left Input PGA" }, 989 { "Left ADC Input", "DMIC", "DMICDAT" }, 990 { "Right ADC Input", "ADC", "Right Input PGA" }, 991 { "Right ADC Input", "DMIC", "DMICDAT" }, 992 993 { "Left Capture Mux", "Left", "ADCL" }, 994 { "Left Capture Mux", "Right", "ADCR" }, 995 996 { "Right Capture Mux", "Left", "ADCL" }, 997 { "Right Capture Mux", "Right", "ADCR" }, 998 999 { "AIFTXL", NULL, "Left Capture Mux" }, 1000 { "AIFTXR", NULL, "Right Capture Mux" }, 1001 1002 { "ADCL", NULL, "Left ADC Input" }, 1003 { "ADCL", NULL, "CLK_DSP" }, 1004 { "ADCR", NULL, "Right ADC Input" }, 1005 { "ADCR", NULL, "CLK_DSP" }, 1006 1007 { "Left Playback Mux", "Left", "AIFRXL" }, 1008 { "Left Playback Mux", "Right", "AIFRXR" }, 1009 1010 { "Right Playback Mux", "Left", "AIFRXL" }, 1011 { "Right Playback Mux", "Right", "AIFRXR" }, 1012 1013 { "DACL Sidetone", "Left", "ADCL" }, 1014 { "DACL Sidetone", "Right", "ADCR" }, 1015 { "DACR Sidetone", "Left", "ADCL" }, 1016 { "DACR Sidetone", "Right", "ADCR" }, 1017 1018 { "DACL", NULL, "Left Playback Mux" }, 1019 { "DACL", NULL, "DACL Sidetone" }, 1020 { "DACL", NULL, "CLK_DSP" }, 1021 1022 { "DACR", NULL, "Right Playback Mux" }, 1023 { "DACR", NULL, "DACR Sidetone" }, 1024 { "DACR", NULL, "CLK_DSP" }, 1025 1026 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1027 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1028 { "Left Output Mixer", "DACL Switch", "DACL" }, 1029 { "Left Output Mixer", "DACR Switch", "DACR" }, 1030 1031 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1032 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1033 { "Right Output Mixer", "DACL Switch", "DACL" }, 1034 { "Right Output Mixer", "DACR Switch", "DACR" }, 1035 1036 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1037 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1038 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1039 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1040 1041 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1042 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1043 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1044 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1045 1046 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1047 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1048 1049 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1050 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1051 1052 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1053 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1054 1055 { "HPL_ENA", NULL, "Left Headphone Output PGA" }, 1056 { "HPR_ENA", NULL, "Right Headphone Output PGA" }, 1057 { "HPL_ENA_DLY", NULL, "HPL_ENA" }, 1058 { "HPR_ENA_DLY", NULL, "HPR_ENA" }, 1059 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, 1060 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, 1061 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, 1062 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, 1063 1064 { "HPL_DCS", NULL, "DCS Master" }, 1065 { "HPR_DCS", NULL, "DCS Master" }, 1066 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1067 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1068 1069 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1070 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1071 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1072 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1073 1074 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1075 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1076 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1077 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1078 1079 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1080 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1081 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1082 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1083 1084 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1085 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1086 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1087 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1088 1089 { "LOP", NULL, "Left Speaker PGA" }, 1090 { "LON", NULL, "Left Speaker PGA" }, 1091 1092 { "ROP", NULL, "Right Speaker PGA" }, 1093 { "RON", NULL, "Right Speaker PGA" }, 1094 1095 { "Charge Pump", NULL, "CLK_DSP" }, 1096 1097 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1098 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1099 { "Left Line Output PGA", NULL, "Charge Pump" }, 1100 { "Right Line Output PGA", NULL, "Charge Pump" }, 1101 }; 1102 1103 static int wm8903_set_bias_level(struct snd_soc_component *component, 1104 enum snd_soc_bias_level level) 1105 { 1106 switch (level) { 1107 case SND_SOC_BIAS_ON: 1108 break; 1109 1110 case SND_SOC_BIAS_PREPARE: 1111 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1112 WM8903_VMID_RES_MASK, 1113 WM8903_VMID_RES_50K); 1114 break; 1115 1116 case SND_SOC_BIAS_STANDBY: 1117 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1118 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1119 WM8903_POBCTRL | WM8903_ISEL_MASK | 1120 WM8903_STARTUP_BIAS_ENA | 1121 WM8903_BIAS_ENA, 1122 WM8903_POBCTRL | 1123 (2 << WM8903_ISEL_SHIFT) | 1124 WM8903_STARTUP_BIAS_ENA); 1125 1126 snd_soc_component_update_bits(component, 1127 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1128 WM8903_SPK_DISCHARGE, 1129 WM8903_SPK_DISCHARGE); 1130 1131 msleep(33); 1132 1133 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5, 1134 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1135 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1136 1137 snd_soc_component_update_bits(component, 1138 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1139 WM8903_SPK_DISCHARGE, 0); 1140 1141 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1142 WM8903_VMID_TIE_ENA | 1143 WM8903_BUFIO_ENA | 1144 WM8903_VMID_IO_ENA | 1145 WM8903_VMID_SOFT_MASK | 1146 WM8903_VMID_RES_MASK | 1147 WM8903_VMID_BUF_ENA, 1148 WM8903_VMID_TIE_ENA | 1149 WM8903_BUFIO_ENA | 1150 WM8903_VMID_IO_ENA | 1151 (2 << WM8903_VMID_SOFT_SHIFT) | 1152 WM8903_VMID_RES_250K | 1153 WM8903_VMID_BUF_ENA); 1154 1155 msleep(129); 1156 1157 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5, 1158 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1159 0); 1160 1161 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1162 WM8903_VMID_SOFT_MASK, 0); 1163 1164 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1165 WM8903_VMID_RES_MASK, 1166 WM8903_VMID_RES_50K); 1167 1168 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1169 WM8903_BIAS_ENA | WM8903_POBCTRL, 1170 WM8903_BIAS_ENA); 1171 1172 /* By default no bypass paths are enabled so 1173 * enable Class W support. 1174 */ 1175 dev_dbg(component->dev, "Enabling Class W\n"); 1176 snd_soc_component_update_bits(component, WM8903_CLASS_W_0, 1177 WM8903_CP_DYN_FREQ | 1178 WM8903_CP_DYN_V, 1179 WM8903_CP_DYN_FREQ | 1180 WM8903_CP_DYN_V); 1181 } 1182 1183 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1184 WM8903_VMID_RES_MASK, 1185 WM8903_VMID_RES_250K); 1186 break; 1187 1188 case SND_SOC_BIAS_OFF: 1189 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1190 WM8903_BIAS_ENA, 0); 1191 1192 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1193 WM8903_VMID_SOFT_MASK, 1194 2 << WM8903_VMID_SOFT_SHIFT); 1195 1196 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1197 WM8903_VMID_BUF_ENA, 0); 1198 1199 msleep(290); 1200 1201 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0, 1202 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1203 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1204 WM8903_VMID_SOFT_MASK | 1205 WM8903_VMID_BUF_ENA, 0); 1206 1207 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0, 1208 WM8903_STARTUP_BIAS_ENA, 0); 1209 break; 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1216 int clk_id, unsigned int freq, int dir) 1217 { 1218 struct snd_soc_component *component = codec_dai->component; 1219 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1220 1221 wm8903->sysclk = freq; 1222 1223 return 0; 1224 } 1225 1226 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1227 unsigned int fmt) 1228 { 1229 struct snd_soc_component *component = codec_dai->component; 1230 u16 aif1 = snd_soc_component_read32(component, WM8903_AUDIO_INTERFACE_1); 1231 1232 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1233 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1234 1235 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1236 case SND_SOC_DAIFMT_CBS_CFS: 1237 break; 1238 case SND_SOC_DAIFMT_CBS_CFM: 1239 aif1 |= WM8903_LRCLK_DIR; 1240 break; 1241 case SND_SOC_DAIFMT_CBM_CFM: 1242 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1243 break; 1244 case SND_SOC_DAIFMT_CBM_CFS: 1245 aif1 |= WM8903_BCLK_DIR; 1246 break; 1247 default: 1248 return -EINVAL; 1249 } 1250 1251 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1252 case SND_SOC_DAIFMT_DSP_A: 1253 aif1 |= 0x3; 1254 break; 1255 case SND_SOC_DAIFMT_DSP_B: 1256 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1257 break; 1258 case SND_SOC_DAIFMT_I2S: 1259 aif1 |= 0x2; 1260 break; 1261 case SND_SOC_DAIFMT_RIGHT_J: 1262 aif1 |= 0x1; 1263 break; 1264 case SND_SOC_DAIFMT_LEFT_J: 1265 break; 1266 default: 1267 return -EINVAL; 1268 } 1269 1270 /* Clock inversion */ 1271 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1272 case SND_SOC_DAIFMT_DSP_A: 1273 case SND_SOC_DAIFMT_DSP_B: 1274 /* frame inversion not valid for DSP modes */ 1275 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1276 case SND_SOC_DAIFMT_NB_NF: 1277 break; 1278 case SND_SOC_DAIFMT_IB_NF: 1279 aif1 |= WM8903_AIF_BCLK_INV; 1280 break; 1281 default: 1282 return -EINVAL; 1283 } 1284 break; 1285 case SND_SOC_DAIFMT_I2S: 1286 case SND_SOC_DAIFMT_RIGHT_J: 1287 case SND_SOC_DAIFMT_LEFT_J: 1288 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1289 case SND_SOC_DAIFMT_NB_NF: 1290 break; 1291 case SND_SOC_DAIFMT_IB_IF: 1292 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1293 break; 1294 case SND_SOC_DAIFMT_IB_NF: 1295 aif1 |= WM8903_AIF_BCLK_INV; 1296 break; 1297 case SND_SOC_DAIFMT_NB_IF: 1298 aif1 |= WM8903_AIF_LRCLK_INV; 1299 break; 1300 default: 1301 return -EINVAL; 1302 } 1303 break; 1304 default: 1305 return -EINVAL; 1306 } 1307 1308 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1); 1309 1310 return 0; 1311 } 1312 1313 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1314 { 1315 struct snd_soc_component *component = codec_dai->component; 1316 u16 reg; 1317 1318 reg = snd_soc_component_read32(component, WM8903_DAC_DIGITAL_1); 1319 1320 if (mute) 1321 reg |= WM8903_DAC_MUTE; 1322 else 1323 reg &= ~WM8903_DAC_MUTE; 1324 1325 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg); 1326 1327 return 0; 1328 } 1329 1330 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1331 * for optimal performance so we list the lower rates first and match 1332 * on the last match we find. */ 1333 static struct { 1334 int div; 1335 int rate; 1336 int mode; 1337 int mclk_div; 1338 } clk_sys_ratios[] = { 1339 { 64, 0x0, 0x0, 1 }, 1340 { 68, 0x0, 0x1, 1 }, 1341 { 125, 0x0, 0x2, 1 }, 1342 { 128, 0x1, 0x0, 1 }, 1343 { 136, 0x1, 0x1, 1 }, 1344 { 192, 0x2, 0x0, 1 }, 1345 { 204, 0x2, 0x1, 1 }, 1346 1347 { 64, 0x0, 0x0, 2 }, 1348 { 68, 0x0, 0x1, 2 }, 1349 { 125, 0x0, 0x2, 2 }, 1350 { 128, 0x1, 0x0, 2 }, 1351 { 136, 0x1, 0x1, 2 }, 1352 { 192, 0x2, 0x0, 2 }, 1353 { 204, 0x2, 0x1, 2 }, 1354 1355 { 250, 0x2, 0x2, 1 }, 1356 { 256, 0x3, 0x0, 1 }, 1357 { 272, 0x3, 0x1, 1 }, 1358 { 384, 0x4, 0x0, 1 }, 1359 { 408, 0x4, 0x1, 1 }, 1360 { 375, 0x4, 0x2, 1 }, 1361 { 512, 0x5, 0x0, 1 }, 1362 { 544, 0x5, 0x1, 1 }, 1363 { 500, 0x5, 0x2, 1 }, 1364 { 768, 0x6, 0x0, 1 }, 1365 { 816, 0x6, 0x1, 1 }, 1366 { 750, 0x6, 0x2, 1 }, 1367 { 1024, 0x7, 0x0, 1 }, 1368 { 1088, 0x7, 0x1, 1 }, 1369 { 1000, 0x7, 0x2, 1 }, 1370 { 1408, 0x8, 0x0, 1 }, 1371 { 1496, 0x8, 0x1, 1 }, 1372 { 1536, 0x9, 0x0, 1 }, 1373 { 1632, 0x9, 0x1, 1 }, 1374 { 1500, 0x9, 0x2, 1 }, 1375 1376 { 250, 0x2, 0x2, 2 }, 1377 { 256, 0x3, 0x0, 2 }, 1378 { 272, 0x3, 0x1, 2 }, 1379 { 384, 0x4, 0x0, 2 }, 1380 { 408, 0x4, 0x1, 2 }, 1381 { 375, 0x4, 0x2, 2 }, 1382 { 512, 0x5, 0x0, 2 }, 1383 { 544, 0x5, 0x1, 2 }, 1384 { 500, 0x5, 0x2, 2 }, 1385 { 768, 0x6, 0x0, 2 }, 1386 { 816, 0x6, 0x1, 2 }, 1387 { 750, 0x6, 0x2, 2 }, 1388 { 1024, 0x7, 0x0, 2 }, 1389 { 1088, 0x7, 0x1, 2 }, 1390 { 1000, 0x7, 0x2, 2 }, 1391 { 1408, 0x8, 0x0, 2 }, 1392 { 1496, 0x8, 0x1, 2 }, 1393 { 1536, 0x9, 0x0, 2 }, 1394 { 1632, 0x9, 0x1, 2 }, 1395 { 1500, 0x9, 0x2, 2 }, 1396 }; 1397 1398 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1399 static struct { 1400 int ratio; 1401 int div; 1402 } bclk_divs[] = { 1403 { 10, 0 }, 1404 { 20, 2 }, 1405 { 30, 3 }, 1406 { 40, 4 }, 1407 { 50, 5 }, 1408 { 60, 7 }, 1409 { 80, 8 }, 1410 { 100, 9 }, 1411 { 120, 11 }, 1412 { 160, 12 }, 1413 { 200, 13 }, 1414 { 220, 14 }, 1415 { 240, 15 }, 1416 { 300, 17 }, 1417 { 320, 18 }, 1418 { 440, 19 }, 1419 { 480, 20 }, 1420 }; 1421 1422 /* Sample rates for DSP */ 1423 static struct { 1424 int rate; 1425 int value; 1426 } sample_rates[] = { 1427 { 8000, 0 }, 1428 { 11025, 1 }, 1429 { 12000, 2 }, 1430 { 16000, 3 }, 1431 { 22050, 4 }, 1432 { 24000, 5 }, 1433 { 32000, 6 }, 1434 { 44100, 7 }, 1435 { 48000, 8 }, 1436 { 88200, 9 }, 1437 { 96000, 10 }, 1438 { 0, 0 }, 1439 }; 1440 1441 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1442 struct snd_pcm_hw_params *params, 1443 struct snd_soc_dai *dai) 1444 { 1445 struct snd_soc_component *component = dai->component; 1446 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1447 int fs = params_rate(params); 1448 int bclk; 1449 int bclk_div; 1450 int i; 1451 int dsp_config; 1452 int clk_config; 1453 int best_val; 1454 int cur_val; 1455 int clk_sys; 1456 1457 u16 aif1 = snd_soc_component_read32(component, WM8903_AUDIO_INTERFACE_1); 1458 u16 aif2 = snd_soc_component_read32(component, WM8903_AUDIO_INTERFACE_2); 1459 u16 aif3 = snd_soc_component_read32(component, WM8903_AUDIO_INTERFACE_3); 1460 u16 clock0 = snd_soc_component_read32(component, WM8903_CLOCK_RATES_0); 1461 u16 clock1 = snd_soc_component_read32(component, WM8903_CLOCK_RATES_1); 1462 u16 dac_digital1 = snd_soc_component_read32(component, WM8903_DAC_DIGITAL_1); 1463 1464 /* Enable sloping stopband filter for low sample rates */ 1465 if (fs <= 24000) 1466 dac_digital1 |= WM8903_DAC_SB_FILT; 1467 else 1468 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1469 1470 /* Configure sample rate logic for DSP - choose nearest rate */ 1471 dsp_config = 0; 1472 best_val = abs(sample_rates[dsp_config].rate - fs); 1473 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1474 cur_val = abs(sample_rates[i].rate - fs); 1475 if (cur_val <= best_val) { 1476 dsp_config = i; 1477 best_val = cur_val; 1478 } 1479 } 1480 1481 dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1482 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1483 clock1 |= sample_rates[dsp_config].value; 1484 1485 aif1 &= ~WM8903_AIF_WL_MASK; 1486 bclk = 2 * fs; 1487 switch (params_width(params)) { 1488 case 16: 1489 bclk *= 16; 1490 break; 1491 case 20: 1492 bclk *= 20; 1493 aif1 |= 0x4; 1494 break; 1495 case 24: 1496 bclk *= 24; 1497 aif1 |= 0x8; 1498 break; 1499 case 32: 1500 bclk *= 32; 1501 aif1 |= 0xc; 1502 break; 1503 default: 1504 return -EINVAL; 1505 } 1506 1507 dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1508 wm8903->sysclk, fs); 1509 1510 /* We may not have an MCLK which allows us to generate exactly 1511 * the clock we want, particularly with USB derived inputs, so 1512 * approximate. 1513 */ 1514 clk_config = 0; 1515 best_val = abs((wm8903->sysclk / 1516 (clk_sys_ratios[0].mclk_div * 1517 clk_sys_ratios[0].div)) - fs); 1518 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1519 cur_val = abs((wm8903->sysclk / 1520 (clk_sys_ratios[i].mclk_div * 1521 clk_sys_ratios[i].div)) - fs); 1522 1523 if (cur_val <= best_val) { 1524 clk_config = i; 1525 best_val = cur_val; 1526 } 1527 } 1528 1529 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1530 clock0 |= WM8903_MCLKDIV2; 1531 clk_sys = wm8903->sysclk / 2; 1532 } else { 1533 clock0 &= ~WM8903_MCLKDIV2; 1534 clk_sys = wm8903->sysclk; 1535 } 1536 1537 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1538 WM8903_CLK_SYS_MODE_MASK); 1539 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1540 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1541 1542 dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1543 clk_sys_ratios[clk_config].rate, 1544 clk_sys_ratios[clk_config].mode, 1545 clk_sys_ratios[clk_config].div); 1546 1547 dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1548 1549 /* We may not get quite the right frequency if using 1550 * approximate clocks so look for the closest match that is 1551 * higher than the target (we need to ensure that there enough 1552 * BCLKs to clock out the samples). 1553 */ 1554 bclk_div = 0; 1555 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1556 i = 1; 1557 while (i < ARRAY_SIZE(bclk_divs)) { 1558 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1559 if (cur_val < 0) /* BCLK table is sorted */ 1560 break; 1561 bclk_div = i; 1562 best_val = cur_val; 1563 i++; 1564 } 1565 1566 aif2 &= ~WM8903_BCLK_DIV_MASK; 1567 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1568 1569 dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1570 bclk_divs[bclk_div].ratio / 10, bclk, 1571 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1572 1573 aif2 |= bclk_divs[bclk_div].div; 1574 aif3 |= bclk / fs; 1575 1576 wm8903->fs = params_rate(params); 1577 wm8903_set_deemph(component); 1578 1579 snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0); 1580 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1); 1581 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1); 1582 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2); 1583 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3); 1584 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1); 1585 1586 return 0; 1587 } 1588 1589 /** 1590 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1591 * 1592 * @component: WM8903 component 1593 * @jack: jack to report detection events on 1594 * @det: value to report for presence detection 1595 * @shrt: value to report for short detection 1596 * 1597 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1598 * being used to bring out signals to the processor then only platform 1599 * data configuration is needed for WM8903 and processor GPIOs should 1600 * be configured using snd_soc_jack_add_gpios() instead. 1601 * 1602 * The current threasholds for detection should be configured using 1603 * micdet_cfg in the platform data. Using this function will force on 1604 * the microphone bias for the device. 1605 */ 1606 int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 1607 int det, int shrt) 1608 { 1609 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1610 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1611 1612 dev_dbg(component->dev, "Enabling microphone detection: %x %x\n", 1613 det, shrt); 1614 1615 /* Store the configuration */ 1616 wm8903->mic_jack = jack; 1617 wm8903->mic_det = det; 1618 wm8903->mic_short = shrt; 1619 1620 /* Enable interrupts we've got a report configured for */ 1621 if (det) 1622 irq_mask &= ~WM8903_MICDET_EINT; 1623 if (shrt) 1624 irq_mask &= ~WM8903_MICSHRT_EINT; 1625 1626 snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK, 1627 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1628 irq_mask); 1629 1630 if (det || shrt) { 1631 /* Enable mic detection, this may not have been set through 1632 * platform data (eg, if the defaults are OK). */ 1633 snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0, 1634 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1635 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0, 1636 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1637 } else { 1638 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0, 1639 WM8903_MICDET_ENA, 0); 1640 } 1641 1642 return 0; 1643 } 1644 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1645 1646 static irqreturn_t wm8903_irq(int irq, void *data) 1647 { 1648 struct wm8903_priv *wm8903 = data; 1649 int mic_report, ret; 1650 unsigned int int_val, mask, int_pol; 1651 1652 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK, 1653 &mask); 1654 if (ret != 0) { 1655 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret); 1656 return IRQ_NONE; 1657 } 1658 1659 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val); 1660 if (ret != 0) { 1661 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret); 1662 return IRQ_NONE; 1663 } 1664 1665 int_val &= ~mask; 1666 1667 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1668 dev_warn(wm8903->dev, "Write sequencer done\n"); 1669 } 1670 1671 /* 1672 * The rest is microphone jack detection. We need to manually 1673 * invert the polarity of the interrupt after each event - to 1674 * simplify the code keep track of the last state we reported 1675 * and just invert the relevant bits in both the report and 1676 * the polarity register. 1677 */ 1678 mic_report = wm8903->mic_last_report; 1679 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1680 &int_pol); 1681 if (ret != 0) { 1682 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n", 1683 ret); 1684 return IRQ_HANDLED; 1685 } 1686 1687 #ifndef CONFIG_SND_SOC_WM8903_MODULE 1688 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1689 trace_snd_soc_jack_irq(dev_name(wm8903->dev)); 1690 #endif 1691 1692 if (int_val & WM8903_MICSHRT_EINT) { 1693 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol); 1694 1695 mic_report ^= wm8903->mic_short; 1696 int_pol ^= WM8903_MICSHRT_INV; 1697 } 1698 1699 if (int_val & WM8903_MICDET_EINT) { 1700 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol); 1701 1702 mic_report ^= wm8903->mic_det; 1703 int_pol ^= WM8903_MICDET_INV; 1704 1705 msleep(wm8903->mic_delay); 1706 } 1707 1708 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1709 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1710 1711 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1712 wm8903->mic_short | wm8903->mic_det); 1713 1714 wm8903->mic_last_report = mic_report; 1715 1716 return IRQ_HANDLED; 1717 } 1718 1719 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1720 SNDRV_PCM_RATE_11025 | \ 1721 SNDRV_PCM_RATE_16000 | \ 1722 SNDRV_PCM_RATE_22050 | \ 1723 SNDRV_PCM_RATE_32000 | \ 1724 SNDRV_PCM_RATE_44100 | \ 1725 SNDRV_PCM_RATE_48000 | \ 1726 SNDRV_PCM_RATE_88200 | \ 1727 SNDRV_PCM_RATE_96000) 1728 1729 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1730 SNDRV_PCM_RATE_11025 | \ 1731 SNDRV_PCM_RATE_16000 | \ 1732 SNDRV_PCM_RATE_22050 | \ 1733 SNDRV_PCM_RATE_32000 | \ 1734 SNDRV_PCM_RATE_44100 | \ 1735 SNDRV_PCM_RATE_48000) 1736 1737 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1738 SNDRV_PCM_FMTBIT_S20_3LE |\ 1739 SNDRV_PCM_FMTBIT_S24_LE) 1740 1741 static const struct snd_soc_dai_ops wm8903_dai_ops = { 1742 .hw_params = wm8903_hw_params, 1743 .digital_mute = wm8903_digital_mute, 1744 .set_fmt = wm8903_set_dai_fmt, 1745 .set_sysclk = wm8903_set_dai_sysclk, 1746 }; 1747 1748 static struct snd_soc_dai_driver wm8903_dai = { 1749 .name = "wm8903-hifi", 1750 .playback = { 1751 .stream_name = "Playback", 1752 .channels_min = 2, 1753 .channels_max = 2, 1754 .rates = WM8903_PLAYBACK_RATES, 1755 .formats = WM8903_FORMATS, 1756 }, 1757 .capture = { 1758 .stream_name = "Capture", 1759 .channels_min = 2, 1760 .channels_max = 2, 1761 .rates = WM8903_CAPTURE_RATES, 1762 .formats = WM8903_FORMATS, 1763 }, 1764 .ops = &wm8903_dai_ops, 1765 .symmetric_rates = 1, 1766 }; 1767 1768 static int wm8903_resume(struct snd_soc_component *component) 1769 { 1770 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component); 1771 1772 regcache_sync(wm8903->regmap); 1773 1774 return 0; 1775 } 1776 1777 #ifdef CONFIG_GPIOLIB 1778 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1779 { 1780 if (offset >= WM8903_NUM_GPIO) 1781 return -EINVAL; 1782 1783 return 0; 1784 } 1785 1786 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1787 { 1788 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1789 unsigned int mask, val; 1790 int ret; 1791 1792 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1793 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1794 WM8903_GP1_DIR; 1795 1796 ret = regmap_update_bits(wm8903->regmap, 1797 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1798 if (ret < 0) 1799 return ret; 1800 1801 return 0; 1802 } 1803 1804 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1805 { 1806 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1807 unsigned int reg; 1808 1809 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®); 1810 1811 return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT); 1812 } 1813 1814 static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1815 unsigned offset, int value) 1816 { 1817 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1818 unsigned int mask, val; 1819 int ret; 1820 1821 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1822 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1823 (value << WM8903_GP2_LVL_SHIFT); 1824 1825 ret = regmap_update_bits(wm8903->regmap, 1826 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1827 if (ret < 0) 1828 return ret; 1829 1830 return 0; 1831 } 1832 1833 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1834 { 1835 struct wm8903_priv *wm8903 = gpiochip_get_data(chip); 1836 1837 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, 1838 WM8903_GP1_LVL_MASK, 1839 !!value << WM8903_GP1_LVL_SHIFT); 1840 } 1841 1842 static const struct gpio_chip wm8903_template_chip = { 1843 .label = "wm8903", 1844 .owner = THIS_MODULE, 1845 .request = wm8903_gpio_request, 1846 .direction_input = wm8903_gpio_direction_in, 1847 .get = wm8903_gpio_get, 1848 .direction_output = wm8903_gpio_direction_out, 1849 .set = wm8903_gpio_set, 1850 .can_sleep = 1, 1851 }; 1852 1853 static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1854 { 1855 struct wm8903_platform_data *pdata = wm8903->pdata; 1856 int ret; 1857 1858 wm8903->gpio_chip = wm8903_template_chip; 1859 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1860 wm8903->gpio_chip.parent = wm8903->dev; 1861 1862 if (pdata->gpio_base) 1863 wm8903->gpio_chip.base = pdata->gpio_base; 1864 else 1865 wm8903->gpio_chip.base = -1; 1866 1867 ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903); 1868 if (ret != 0) 1869 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret); 1870 } 1871 1872 static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1873 { 1874 gpiochip_remove(&wm8903->gpio_chip); 1875 } 1876 #else 1877 static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1878 { 1879 } 1880 1881 static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1882 { 1883 } 1884 #endif 1885 1886 static const struct snd_soc_component_driver soc_component_dev_wm8903 = { 1887 .resume = wm8903_resume, 1888 .set_bias_level = wm8903_set_bias_level, 1889 .seq_notifier = wm8903_seq_notifier, 1890 .controls = wm8903_snd_controls, 1891 .num_controls = ARRAY_SIZE(wm8903_snd_controls), 1892 .dapm_widgets = wm8903_dapm_widgets, 1893 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets), 1894 .dapm_routes = wm8903_intercon, 1895 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon), 1896 .suspend_bias_off = 1, 1897 .idle_bias_on = 1, 1898 .use_pmdown_time = 1, 1899 .endianness = 1, 1900 .non_legacy_dai_naming = 1, 1901 }; 1902 1903 static const struct regmap_config wm8903_regmap = { 1904 .reg_bits = 8, 1905 .val_bits = 16, 1906 1907 .max_register = WM8903_MAX_REGISTER, 1908 .volatile_reg = wm8903_volatile_register, 1909 .readable_reg = wm8903_readable_register, 1910 1911 .cache_type = REGCACHE_RBTREE, 1912 .reg_defaults = wm8903_reg_defaults, 1913 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults), 1914 }; 1915 1916 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c, 1917 struct wm8903_platform_data *pdata) 1918 { 1919 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 1920 if (!irq_data) { 1921 dev_err(&i2c->dev, "Invalid IRQ: %d\n", 1922 i2c->irq); 1923 return -EINVAL; 1924 } 1925 1926 switch (irqd_get_trigger_type(irq_data)) { 1927 case IRQ_TYPE_NONE: 1928 default: 1929 /* 1930 * We assume the controller imposes no restrictions, 1931 * so we are able to select active-high 1932 */ 1933 /* Fall-through */ 1934 case IRQ_TYPE_LEVEL_HIGH: 1935 pdata->irq_active_low = false; 1936 break; 1937 case IRQ_TYPE_LEVEL_LOW: 1938 pdata->irq_active_low = true; 1939 break; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static int wm8903_set_pdata_from_of(struct i2c_client *i2c, 1946 struct wm8903_platform_data *pdata) 1947 { 1948 const struct device_node *np = i2c->dev.of_node; 1949 u32 val32; 1950 int i; 1951 1952 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0) 1953 pdata->micdet_cfg = val32; 1954 1955 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0) 1956 pdata->micdet_delay = val32; 1957 1958 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg, 1959 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) { 1960 /* 1961 * In device tree: 0 means "write 0", 1962 * 0xffffffff means "don't touch". 1963 * 1964 * In platform data: 0 means "don't touch", 1965 * 0x8000 means "write 0". 1966 * 1967 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000. 1968 * 1969 * Convert from DT to pdata representation here, 1970 * so no other code needs to change. 1971 */ 1972 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1973 if (pdata->gpio_cfg[i] == 0) { 1974 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO; 1975 } else if (pdata->gpio_cfg[i] == 0xffffffff) { 1976 pdata->gpio_cfg[i] = 0; 1977 } else if (pdata->gpio_cfg[i] > 0x7fff) { 1978 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n", 1979 i, pdata->gpio_cfg[i]); 1980 return -EINVAL; 1981 } 1982 } 1983 } 1984 1985 return 0; 1986 } 1987 1988 static int wm8903_i2c_probe(struct i2c_client *i2c, 1989 const struct i2c_device_id *id) 1990 { 1991 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 1992 struct wm8903_priv *wm8903; 1993 int trigger; 1994 bool mic_gpio = false; 1995 unsigned int val, irq_pol; 1996 int ret, i; 1997 1998 wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL); 1999 if (wm8903 == NULL) 2000 return -ENOMEM; 2001 2002 mutex_init(&wm8903->lock); 2003 wm8903->dev = &i2c->dev; 2004 2005 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap); 2006 if (IS_ERR(wm8903->regmap)) { 2007 ret = PTR_ERR(wm8903->regmap); 2008 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2009 ret); 2010 return ret; 2011 } 2012 2013 i2c_set_clientdata(i2c, wm8903); 2014 2015 /* If no platform data was supplied, create storage for defaults */ 2016 if (pdata) { 2017 wm8903->pdata = pdata; 2018 } else { 2019 wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata), 2020 GFP_KERNEL); 2021 if (!wm8903->pdata) 2022 return -ENOMEM; 2023 2024 if (i2c->irq) { 2025 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata); 2026 if (ret != 0) 2027 return ret; 2028 } 2029 2030 if (i2c->dev.of_node) { 2031 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata); 2032 if (ret != 0) 2033 return ret; 2034 } 2035 } 2036 2037 pdata = wm8903->pdata; 2038 2039 for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++) 2040 wm8903->supplies[i].supply = wm8903_supply_names[i]; 2041 2042 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies), 2043 wm8903->supplies); 2044 if (ret != 0) { 2045 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2046 return ret; 2047 } 2048 2049 ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies), 2050 wm8903->supplies); 2051 if (ret != 0) { 2052 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2053 return ret; 2054 } 2055 2056 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); 2057 if (ret != 0) { 2058 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 2059 goto err; 2060 } 2061 if (val != 0x8903) { 2062 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); 2063 ret = -ENODEV; 2064 goto err; 2065 } 2066 2067 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); 2068 if (ret != 0) { 2069 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret); 2070 goto err; 2071 } 2072 dev_info(&i2c->dev, "WM8903 revision %c\n", 2073 (val & WM8903_CHIP_REV_MASK) + 'A'); 2074 2075 /* Reset the device */ 2076 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903); 2077 2078 wm8903_init_gpio(wm8903); 2079 2080 /* Set up GPIO pin state, detect if any are MIC detect outputs */ 2081 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2082 if ((!pdata->gpio_cfg[i]) || 2083 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO)) 2084 continue; 2085 2086 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i, 2087 pdata->gpio_cfg[i] & 0x7fff); 2088 2089 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 2090 >> WM8903_GP1_FN_SHIFT; 2091 2092 switch (val) { 2093 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 2094 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 2095 mic_gpio = true; 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 2102 /* Set up microphone detection */ 2103 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0, 2104 pdata->micdet_cfg); 2105 2106 /* Microphone detection needs the WSEQ clock */ 2107 if (pdata->micdet_cfg) 2108 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0, 2109 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 2110 2111 /* If microphone detection is enabled by pdata but 2112 * detected via IRQ then interrupts can be lost before 2113 * the machine driver has set up microphone detection 2114 * IRQs as the IRQs are clear on read. The detection 2115 * will be enabled when the machine driver configures. 2116 */ 2117 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 2118 2119 wm8903->mic_delay = pdata->micdet_delay; 2120 2121 if (i2c->irq) { 2122 if (pdata->irq_active_low) { 2123 trigger = IRQF_TRIGGER_LOW; 2124 irq_pol = WM8903_IRQ_POL; 2125 } else { 2126 trigger = IRQF_TRIGGER_HIGH; 2127 irq_pol = 0; 2128 } 2129 2130 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL, 2131 WM8903_IRQ_POL, irq_pol); 2132 2133 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq, 2134 trigger | IRQF_ONESHOT, 2135 "wm8903", wm8903); 2136 if (ret != 0) { 2137 dev_err(wm8903->dev, "Failed to request IRQ: %d\n", 2138 ret); 2139 return ret; 2140 } 2141 2142 /* Enable write sequencer interrupts */ 2143 regmap_update_bits(wm8903->regmap, 2144 WM8903_INTERRUPT_STATUS_1_MASK, 2145 WM8903_IM_WSEQ_BUSY_EINT, 0); 2146 } 2147 2148 /* Latch volume update bits */ 2149 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT, 2150 WM8903_ADCVU, WM8903_ADCVU); 2151 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT, 2152 WM8903_ADCVU, WM8903_ADCVU); 2153 2154 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT, 2155 WM8903_DACVU, WM8903_DACVU); 2156 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT, 2157 WM8903_DACVU, WM8903_DACVU); 2158 2159 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT, 2160 WM8903_HPOUTVU, WM8903_HPOUTVU); 2161 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT, 2162 WM8903_HPOUTVU, WM8903_HPOUTVU); 2163 2164 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT, 2165 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2166 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT, 2167 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2168 2169 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT, 2170 WM8903_SPKVU, WM8903_SPKVU); 2171 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT, 2172 WM8903_SPKVU, WM8903_SPKVU); 2173 2174 /* Enable DAC soft mute by default */ 2175 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1, 2176 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2177 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2178 2179 ret = devm_snd_soc_register_component(&i2c->dev, 2180 &soc_component_dev_wm8903, &wm8903_dai, 1); 2181 if (ret != 0) 2182 goto err; 2183 2184 return 0; 2185 err: 2186 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies), 2187 wm8903->supplies); 2188 return ret; 2189 } 2190 2191 static int wm8903_i2c_remove(struct i2c_client *client) 2192 { 2193 struct wm8903_priv *wm8903 = i2c_get_clientdata(client); 2194 2195 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies), 2196 wm8903->supplies); 2197 if (client->irq) 2198 free_irq(client->irq, wm8903); 2199 wm8903_free_gpio(wm8903); 2200 2201 return 0; 2202 } 2203 2204 static const struct of_device_id wm8903_of_match[] = { 2205 { .compatible = "wlf,wm8903", }, 2206 {}, 2207 }; 2208 MODULE_DEVICE_TABLE(of, wm8903_of_match); 2209 2210 static const struct i2c_device_id wm8903_i2c_id[] = { 2211 { "wm8903", 0 }, 2212 { } 2213 }; 2214 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2215 2216 static struct i2c_driver wm8903_i2c_driver = { 2217 .driver = { 2218 .name = "wm8903", 2219 .of_match_table = wm8903_of_match, 2220 }, 2221 .probe = wm8903_i2c_probe, 2222 .remove = wm8903_i2c_remove, 2223 .id_table = wm8903_i2c_id, 2224 }; 2225 2226 module_i2c_driver(wm8903_i2c_driver); 2227 2228 MODULE_DESCRIPTION("ASoC WM8903 driver"); 2229 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2230 MODULE_LICENSE("GPL"); 2231