1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: 13 * - TDM mode configuration. 14 * - Digital microphone support. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/moduleparam.h> 19 #include <linux/init.h> 20 #include <linux/completion.h> 21 #include <linux/delay.h> 22 #include <linux/pm.h> 23 #include <linux/i2c.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/tlv.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/wm8903.h> 35 36 #include "wm8903.h" 37 38 /* Register defaults at reset */ 39 static u16 wm8903_reg_defaults[] = { 40 0x8903, /* R0 - SW Reset and ID */ 41 0x0000, /* R1 - Revision Number */ 42 0x0000, /* R2 */ 43 0x0000, /* R3 */ 44 0x0018, /* R4 - Bias Control 0 */ 45 0x0000, /* R5 - VMID Control 0 */ 46 0x0000, /* R6 - Mic Bias Control 0 */ 47 0x0000, /* R7 */ 48 0x0001, /* R8 - Analogue DAC 0 */ 49 0x0000, /* R9 */ 50 0x0001, /* R10 - Analogue ADC 0 */ 51 0x0000, /* R11 */ 52 0x0000, /* R12 - Power Management 0 */ 53 0x0000, /* R13 - Power Management 1 */ 54 0x0000, /* R14 - Power Management 2 */ 55 0x0000, /* R15 - Power Management 3 */ 56 0x0000, /* R16 - Power Management 4 */ 57 0x0000, /* R17 - Power Management 5 */ 58 0x0000, /* R18 - Power Management 6 */ 59 0x0000, /* R19 */ 60 0x0400, /* R20 - Clock Rates 0 */ 61 0x0D07, /* R21 - Clock Rates 1 */ 62 0x0000, /* R22 - Clock Rates 2 */ 63 0x0000, /* R23 */ 64 0x0050, /* R24 - Audio Interface 0 */ 65 0x0242, /* R25 - Audio Interface 1 */ 66 0x0008, /* R26 - Audio Interface 2 */ 67 0x0022, /* R27 - Audio Interface 3 */ 68 0x0000, /* R28 */ 69 0x0000, /* R29 */ 70 0x00C0, /* R30 - DAC Digital Volume Left */ 71 0x00C0, /* R31 - DAC Digital Volume Right */ 72 0x0000, /* R32 - DAC Digital 0 */ 73 0x0000, /* R33 - DAC Digital 1 */ 74 0x0000, /* R34 */ 75 0x0000, /* R35 */ 76 0x00C0, /* R36 - ADC Digital Volume Left */ 77 0x00C0, /* R37 - ADC Digital Volume Right */ 78 0x0000, /* R38 - ADC Digital 0 */ 79 0x0073, /* R39 - Digital Microphone 0 */ 80 0x09BF, /* R40 - DRC 0 */ 81 0x3241, /* R41 - DRC 1 */ 82 0x0020, /* R42 - DRC 2 */ 83 0x0000, /* R43 - DRC 3 */ 84 0x0085, /* R44 - Analogue Left Input 0 */ 85 0x0085, /* R45 - Analogue Right Input 0 */ 86 0x0044, /* R46 - Analogue Left Input 1 */ 87 0x0044, /* R47 - Analogue Right Input 1 */ 88 0x0000, /* R48 */ 89 0x0000, /* R49 */ 90 0x0008, /* R50 - Analogue Left Mix 0 */ 91 0x0004, /* R51 - Analogue Right Mix 0 */ 92 0x0000, /* R52 - Analogue Spk Mix Left 0 */ 93 0x0000, /* R53 - Analogue Spk Mix Left 1 */ 94 0x0000, /* R54 - Analogue Spk Mix Right 0 */ 95 0x0000, /* R55 - Analogue Spk Mix Right 1 */ 96 0x0000, /* R56 */ 97 0x002D, /* R57 - Analogue OUT1 Left */ 98 0x002D, /* R58 - Analogue OUT1 Right */ 99 0x0039, /* R59 - Analogue OUT2 Left */ 100 0x0039, /* R60 - Analogue OUT2 Right */ 101 0x0100, /* R61 */ 102 0x0139, /* R62 - Analogue OUT3 Left */ 103 0x0139, /* R63 - Analogue OUT3 Right */ 104 0x0000, /* R64 */ 105 0x0000, /* R65 - Analogue SPK Output Control 0 */ 106 0x0000, /* R66 */ 107 0x0010, /* R67 - DC Servo 0 */ 108 0x0100, /* R68 */ 109 0x00A4, /* R69 - DC Servo 2 */ 110 0x0807, /* R70 */ 111 0x0000, /* R71 */ 112 0x0000, /* R72 */ 113 0x0000, /* R73 */ 114 0x0000, /* R74 */ 115 0x0000, /* R75 */ 116 0x0000, /* R76 */ 117 0x0000, /* R77 */ 118 0x0000, /* R78 */ 119 0x000E, /* R79 */ 120 0x0000, /* R80 */ 121 0x0000, /* R81 */ 122 0x0000, /* R82 */ 123 0x0000, /* R83 */ 124 0x0000, /* R84 */ 125 0x0000, /* R85 */ 126 0x0000, /* R86 */ 127 0x0006, /* R87 */ 128 0x0000, /* R88 */ 129 0x0000, /* R89 */ 130 0x0000, /* R90 - Analogue HP 0 */ 131 0x0060, /* R91 */ 132 0x0000, /* R92 */ 133 0x0000, /* R93 */ 134 0x0000, /* R94 - Analogue Lineout 0 */ 135 0x0060, /* R95 */ 136 0x0000, /* R96 */ 137 0x0000, /* R97 */ 138 0x0000, /* R98 - Charge Pump 0 */ 139 0x1F25, /* R99 */ 140 0x2B19, /* R100 */ 141 0x01C0, /* R101 */ 142 0x01EF, /* R102 */ 143 0x2B00, /* R103 */ 144 0x0000, /* R104 - Class W 0 */ 145 0x01C0, /* R105 */ 146 0x1C10, /* R106 */ 147 0x0000, /* R107 */ 148 0x0000, /* R108 - Write Sequencer 0 */ 149 0x0000, /* R109 - Write Sequencer 1 */ 150 0x0000, /* R110 - Write Sequencer 2 */ 151 0x0000, /* R111 - Write Sequencer 3 */ 152 0x0000, /* R112 - Write Sequencer 4 */ 153 0x0000, /* R113 */ 154 0x0000, /* R114 - Control Interface */ 155 0x0000, /* R115 */ 156 0x00A8, /* R116 - GPIO Control 1 */ 157 0x00A8, /* R117 - GPIO Control 2 */ 158 0x00A8, /* R118 - GPIO Control 3 */ 159 0x0220, /* R119 - GPIO Control 4 */ 160 0x01A0, /* R120 - GPIO Control 5 */ 161 0x0000, /* R121 - Interrupt Status 1 */ 162 0xFFFF, /* R122 - Interrupt Status 1 Mask */ 163 0x0000, /* R123 - Interrupt Polarity 1 */ 164 0x0000, /* R124 */ 165 0x0003, /* R125 */ 166 0x0000, /* R126 - Interrupt Control */ 167 0x0000, /* R127 */ 168 0x0005, /* R128 */ 169 0x0000, /* R129 - Control Interface Test 1 */ 170 0x0000, /* R130 */ 171 0x0000, /* R131 */ 172 0x0000, /* R132 */ 173 0x0000, /* R133 */ 174 0x0000, /* R134 */ 175 0x03FF, /* R135 */ 176 0x0007, /* R136 */ 177 0x0040, /* R137 */ 178 0x0000, /* R138 */ 179 0x0000, /* R139 */ 180 0x0000, /* R140 */ 181 0x0000, /* R141 */ 182 0x0000, /* R142 */ 183 0x0000, /* R143 */ 184 0x0000, /* R144 */ 185 0x0000, /* R145 */ 186 0x0000, /* R146 */ 187 0x0000, /* R147 */ 188 0x4000, /* R148 */ 189 0x6810, /* R149 - Charge Pump Test 1 */ 190 0x0004, /* R150 */ 191 0x0000, /* R151 */ 192 0x0000, /* R152 */ 193 0x0000, /* R153 */ 194 0x0000, /* R154 */ 195 0x0000, /* R155 */ 196 0x0000, /* R156 */ 197 0x0000, /* R157 */ 198 0x0000, /* R158 */ 199 0x0000, /* R159 */ 200 0x0000, /* R160 */ 201 0x0000, /* R161 */ 202 0x0000, /* R162 */ 203 0x0000, /* R163 */ 204 0x0028, /* R164 - Clock Rate Test 4 */ 205 0x0004, /* R165 */ 206 0x0000, /* R166 */ 207 0x0060, /* R167 */ 208 0x0000, /* R168 */ 209 0x0000, /* R169 */ 210 0x0000, /* R170 */ 211 0x0000, /* R171 */ 212 0x0000, /* R172 - Analogue Output Bias 0 */ 213 }; 214 215 struct wm8903_priv { 216 217 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; 218 219 int sysclk; 220 int irq; 221 222 /* Reference counts */ 223 int class_w_users; 224 int playback_active; 225 int capture_active; 226 227 struct completion wseq; 228 229 struct snd_soc_jack *mic_jack; 230 int mic_det; 231 int mic_short; 232 int mic_last_report; 233 int mic_delay; 234 235 struct snd_pcm_substream *master_substream; 236 struct snd_pcm_substream *slave_substream; 237 }; 238 239 static int wm8903_volatile_register(unsigned int reg) 240 { 241 switch (reg) { 242 case WM8903_SW_RESET_AND_ID: 243 case WM8903_REVISION_NUMBER: 244 case WM8903_INTERRUPT_STATUS_1: 245 case WM8903_WRITE_SEQUENCER_4: 246 return 1; 247 248 default: 249 return 0; 250 } 251 } 252 253 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) 254 { 255 u16 reg[5]; 256 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 257 258 BUG_ON(start > 48); 259 260 /* Enable the sequencer if it's not already on */ 261 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0); 262 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 263 reg[0] | WM8903_WSEQ_ENA); 264 265 dev_dbg(codec->dev, "Starting sequence at %d\n", start); 266 267 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3, 268 start | WM8903_WSEQ_START); 269 270 /* Wait for it to complete. If we have the interrupt wired up then 271 * that will break us out of the poll early. 272 */ 273 do { 274 wait_for_completion_timeout(&wm8903->wseq, 275 msecs_to_jiffies(10)); 276 277 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4); 278 } while (reg[4] & WM8903_WSEQ_BUSY); 279 280 dev_dbg(codec->dev, "Sequence complete\n"); 281 282 /* Disable the sequencer again if we enabled it */ 283 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); 284 285 return 0; 286 } 287 288 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache) 289 { 290 int i; 291 292 /* There really ought to be something better we can do here :/ */ 293 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 294 cache[i] = codec->hw_read(codec, i); 295 } 296 297 static void wm8903_reset(struct snd_soc_codec *codec) 298 { 299 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); 300 memcpy(codec->reg_cache, wm8903_reg_defaults, 301 sizeof(wm8903_reg_defaults)); 302 } 303 304 #define WM8903_OUTPUT_SHORT 0x8 305 #define WM8903_OUTPUT_OUT 0x4 306 #define WM8903_OUTPUT_INT 0x2 307 #define WM8903_OUTPUT_IN 0x1 308 309 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 310 struct snd_kcontrol *kcontrol, int event) 311 { 312 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 313 mdelay(4); 314 315 return 0; 316 } 317 318 /* 319 * Event for headphone and line out amplifier power changes. Special 320 * power up/down sequences are required in order to maximise pop/click 321 * performance. 322 */ 323 static int wm8903_output_event(struct snd_soc_dapm_widget *w, 324 struct snd_kcontrol *kcontrol, int event) 325 { 326 struct snd_soc_codec *codec = w->codec; 327 u16 val; 328 u16 reg; 329 u16 dcs_reg; 330 u16 dcs_bit; 331 int shift; 332 333 switch (w->reg) { 334 case WM8903_POWER_MANAGEMENT_2: 335 reg = WM8903_ANALOGUE_HP_0; 336 dcs_bit = 0 + w->shift; 337 break; 338 case WM8903_POWER_MANAGEMENT_3: 339 reg = WM8903_ANALOGUE_LINEOUT_0; 340 dcs_bit = 2 + w->shift; 341 break; 342 default: 343 BUG(); 344 return -EINVAL; /* Spurious warning from some compilers */ 345 } 346 347 switch (w->shift) { 348 case 0: 349 shift = 0; 350 break; 351 case 1: 352 shift = 4; 353 break; 354 default: 355 BUG(); 356 return -EINVAL; /* Spurious warning from some compilers */ 357 } 358 359 if (event & SND_SOC_DAPM_PRE_PMU) { 360 val = snd_soc_read(codec, reg); 361 362 /* Short the output */ 363 val &= ~(WM8903_OUTPUT_SHORT << shift); 364 snd_soc_write(codec, reg, val); 365 } 366 367 if (event & SND_SOC_DAPM_POST_PMU) { 368 val = snd_soc_read(codec, reg); 369 370 val |= (WM8903_OUTPUT_IN << shift); 371 snd_soc_write(codec, reg, val); 372 373 val |= (WM8903_OUTPUT_INT << shift); 374 snd_soc_write(codec, reg, val); 375 376 /* Turn on the output ENA_OUTP */ 377 val |= (WM8903_OUTPUT_OUT << shift); 378 snd_soc_write(codec, reg, val); 379 380 /* Enable the DC servo */ 381 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 382 dcs_reg |= dcs_bit; 383 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 384 385 /* Remove the short */ 386 val |= (WM8903_OUTPUT_SHORT << shift); 387 snd_soc_write(codec, reg, val); 388 } 389 390 if (event & SND_SOC_DAPM_PRE_PMD) { 391 val = snd_soc_read(codec, reg); 392 393 /* Short the output */ 394 val &= ~(WM8903_OUTPUT_SHORT << shift); 395 snd_soc_write(codec, reg, val); 396 397 /* Disable the DC servo */ 398 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 399 dcs_reg &= ~dcs_bit; 400 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 401 402 /* Then disable the intermediate and output stages */ 403 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 404 WM8903_OUTPUT_IN) << shift); 405 snd_soc_write(codec, reg, val); 406 } 407 408 return 0; 409 } 410 411 /* 412 * When used with DAC outputs only the WM8903 charge pump supports 413 * operation in class W mode, providing very low power consumption 414 * when used with digital sources. Enable and disable this mode 415 * automatically depending on the mixer configuration. 416 * 417 * All the relevant controls are simple switches. 418 */ 419 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 420 struct snd_ctl_elem_value *ucontrol) 421 { 422 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 423 struct snd_soc_codec *codec = widget->codec; 424 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 425 u16 reg; 426 int ret; 427 428 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 429 430 /* Turn it off if we're about to enable bypass */ 431 if (ucontrol->value.integer.value[0]) { 432 if (wm8903->class_w_users == 0) { 433 dev_dbg(codec->dev, "Disabling Class W\n"); 434 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 435 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 436 } 437 wm8903->class_w_users++; 438 } 439 440 /* Implement the change */ 441 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 442 443 /* If we've just disabled the last bypass path turn Class W on */ 444 if (!ucontrol->value.integer.value[0]) { 445 if (wm8903->class_w_users == 1) { 446 dev_dbg(codec->dev, "Enabling Class W\n"); 447 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 448 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 449 } 450 wm8903->class_w_users--; 451 } 452 453 dev_dbg(codec->dev, "Bypass use count now %d\n", 454 wm8903->class_w_users); 455 456 return ret; 457 } 458 459 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 460 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 461 .info = snd_soc_info_volsw, \ 462 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 463 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 464 465 466 /* ALSA can only do steps of .01dB */ 467 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 468 469 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 470 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 471 472 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 473 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 474 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 475 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 476 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 477 478 static const char *drc_slope_text[] = { 479 "1", "1/2", "1/4", "1/8", "1/16", "0" 480 }; 481 482 static const struct soc_enum drc_slope_r0 = 483 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 484 485 static const struct soc_enum drc_slope_r1 = 486 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 487 488 static const char *drc_attack_text[] = { 489 "instantaneous", 490 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 491 "46.4ms", "92.8ms", "185.6ms" 492 }; 493 494 static const struct soc_enum drc_attack = 495 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 496 497 static const char *drc_decay_text[] = { 498 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 499 "23.87s", "47.56s" 500 }; 501 502 static const struct soc_enum drc_decay = 503 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 504 505 static const char *drc_ff_delay_text[] = { 506 "5 samples", "9 samples" 507 }; 508 509 static const struct soc_enum drc_ff_delay = 510 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 511 512 static const char *drc_qr_decay_text[] = { 513 "0.725ms", "1.45ms", "5.8ms" 514 }; 515 516 static const struct soc_enum drc_qr_decay = 517 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 518 519 static const char *drc_smoothing_text[] = { 520 "Low", "Medium", "High" 521 }; 522 523 static const struct soc_enum drc_smoothing = 524 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 525 526 static const char *soft_mute_text[] = { 527 "Fast (fs/2)", "Slow (fs/32)" 528 }; 529 530 static const struct soc_enum soft_mute = 531 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 532 533 static const char *mute_mode_text[] = { 534 "Hard", "Soft" 535 }; 536 537 static const struct soc_enum mute_mode = 538 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 539 540 static const char *dac_deemphasis_text[] = { 541 "Disabled", "32kHz", "44.1kHz", "48kHz" 542 }; 543 544 static const struct soc_enum dac_deemphasis = 545 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); 546 547 static const char *companding_text[] = { 548 "ulaw", "alaw" 549 }; 550 551 static const struct soc_enum dac_companding = 552 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 553 554 static const struct soc_enum adc_companding = 555 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 556 557 static const char *input_mode_text[] = { 558 "Single-Ended", "Differential Line", "Differential Mic" 559 }; 560 561 static const struct soc_enum linput_mode_enum = 562 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 563 564 static const struct soc_enum rinput_mode_enum = 565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 566 567 static const char *linput_mux_text[] = { 568 "IN1L", "IN2L", "IN3L" 569 }; 570 571 static const struct soc_enum linput_enum = 572 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 573 574 static const struct soc_enum linput_inv_enum = 575 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 576 577 static const char *rinput_mux_text[] = { 578 "IN1R", "IN2R", "IN3R" 579 }; 580 581 static const struct soc_enum rinput_enum = 582 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 583 584 static const struct soc_enum rinput_inv_enum = 585 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 586 587 588 static const char *sidetone_text[] = { 589 "None", "Left", "Right" 590 }; 591 592 static const struct soc_enum lsidetone_enum = 593 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 594 595 static const struct soc_enum rsidetone_enum = 596 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 597 598 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 599 600 /* Input PGAs - No TLV since the scale depends on PGA mode */ 601 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 602 7, 1, 1), 603 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 604 0, 31, 0), 605 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 606 6, 1, 0), 607 608 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 609 7, 1, 1), 610 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 611 0, 31, 0), 612 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 613 6, 1, 0), 614 615 /* ADCs */ 616 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 617 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 618 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 619 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 620 drc_tlv_thresh), 621 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 622 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 623 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 624 SOC_ENUM("DRC Attack Rate", drc_attack), 625 SOC_ENUM("DRC Decay Rate", drc_decay), 626 SOC_ENUM("DRC FF Delay", drc_ff_delay), 627 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 628 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 629 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 630 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 631 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 632 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 633 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 634 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 635 636 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 637 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 638 SOC_ENUM("ADC Companding Mode", adc_companding), 639 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 640 641 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 642 12, 0, digital_sidetone_tlv), 643 644 /* DAC */ 645 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 646 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 647 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 648 SOC_ENUM("DAC Mute Mode", mute_mode), 649 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 650 SOC_ENUM("DAC De-emphasis", dac_deemphasis), 651 SOC_ENUM("DAC Companding Mode", dac_companding), 652 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 653 654 /* Headphones */ 655 SOC_DOUBLE_R("Headphone Switch", 656 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 657 8, 1, 1), 658 SOC_DOUBLE_R("Headphone ZC Switch", 659 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 660 6, 1, 0), 661 SOC_DOUBLE_R_TLV("Headphone Volume", 662 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 663 0, 63, 0, out_tlv), 664 665 /* Line out */ 666 SOC_DOUBLE_R("Line Out Switch", 667 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 668 8, 1, 1), 669 SOC_DOUBLE_R("Line Out ZC Switch", 670 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 671 6, 1, 0), 672 SOC_DOUBLE_R_TLV("Line Out Volume", 673 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 674 0, 63, 0, out_tlv), 675 676 /* Speaker */ 677 SOC_DOUBLE_R("Speaker Switch", 678 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 679 SOC_DOUBLE_R("Speaker ZC Switch", 680 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 681 SOC_DOUBLE_R_TLV("Speaker Volume", 682 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 683 0, 63, 0, out_tlv), 684 }; 685 686 static const struct snd_kcontrol_new linput_mode_mux = 687 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 688 689 static const struct snd_kcontrol_new rinput_mode_mux = 690 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 691 692 static const struct snd_kcontrol_new linput_mux = 693 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 694 695 static const struct snd_kcontrol_new linput_inv_mux = 696 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 697 698 static const struct snd_kcontrol_new rinput_mux = 699 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 700 701 static const struct snd_kcontrol_new rinput_inv_mux = 702 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 703 704 static const struct snd_kcontrol_new lsidetone_mux = 705 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 706 707 static const struct snd_kcontrol_new rsidetone_mux = 708 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 709 710 static const struct snd_kcontrol_new left_output_mixer[] = { 711 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 712 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 713 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 714 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 715 }; 716 717 static const struct snd_kcontrol_new right_output_mixer[] = { 718 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 719 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 720 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 721 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 722 }; 723 724 static const struct snd_kcontrol_new left_speaker_mixer[] = { 725 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 726 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 727 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 728 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 729 0, 1, 0), 730 }; 731 732 static const struct snd_kcontrol_new right_speaker_mixer[] = { 733 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 734 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 735 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 736 1, 1, 0), 737 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 738 0, 1, 0), 739 }; 740 741 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 742 SND_SOC_DAPM_INPUT("IN1L"), 743 SND_SOC_DAPM_INPUT("IN1R"), 744 SND_SOC_DAPM_INPUT("IN2L"), 745 SND_SOC_DAPM_INPUT("IN2R"), 746 SND_SOC_DAPM_INPUT("IN3L"), 747 SND_SOC_DAPM_INPUT("IN3R"), 748 749 SND_SOC_DAPM_OUTPUT("HPOUTL"), 750 SND_SOC_DAPM_OUTPUT("HPOUTR"), 751 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 752 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 753 SND_SOC_DAPM_OUTPUT("LOP"), 754 SND_SOC_DAPM_OUTPUT("LON"), 755 SND_SOC_DAPM_OUTPUT("ROP"), 756 SND_SOC_DAPM_OUTPUT("RON"), 757 758 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), 759 760 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 761 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 762 &linput_inv_mux), 763 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 764 765 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 766 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 767 &rinput_inv_mux), 768 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 769 770 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 771 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 772 773 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), 774 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), 775 776 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 777 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 778 779 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), 780 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), 781 782 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 783 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 784 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 785 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 786 787 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 788 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 789 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 790 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 791 792 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 793 1, 0, NULL, 0, wm8903_output_event, 794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 795 SND_SOC_DAPM_PRE_PMD), 796 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 797 0, 0, NULL, 0, wm8903_output_event, 798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 799 SND_SOC_DAPM_PRE_PMD), 800 801 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, 802 NULL, 0, wm8903_output_event, 803 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 804 SND_SOC_DAPM_PRE_PMD), 805 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, 806 NULL, 0, wm8903_output_event, 807 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 808 SND_SOC_DAPM_PRE_PMD), 809 810 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 811 NULL, 0), 812 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 813 NULL, 0), 814 815 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 816 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 817 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 818 }; 819 820 static const struct snd_soc_dapm_route intercon[] = { 821 822 { "Left Input Mux", "IN1L", "IN1L" }, 823 { "Left Input Mux", "IN2L", "IN2L" }, 824 { "Left Input Mux", "IN3L", "IN3L" }, 825 826 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 827 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 828 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 829 830 { "Right Input Mux", "IN1R", "IN1R" }, 831 { "Right Input Mux", "IN2R", "IN2R" }, 832 { "Right Input Mux", "IN3R", "IN3R" }, 833 834 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 835 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 836 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 837 838 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 839 { "Left Input Mode Mux", "Differential Line", 840 "Left Input Mux" }, 841 { "Left Input Mode Mux", "Differential Line", 842 "Left Input Inverting Mux" }, 843 { "Left Input Mode Mux", "Differential Mic", 844 "Left Input Mux" }, 845 { "Left Input Mode Mux", "Differential Mic", 846 "Left Input Inverting Mux" }, 847 848 { "Right Input Mode Mux", "Single-Ended", 849 "Right Input Inverting Mux" }, 850 { "Right Input Mode Mux", "Differential Line", 851 "Right Input Mux" }, 852 { "Right Input Mode Mux", "Differential Line", 853 "Right Input Inverting Mux" }, 854 { "Right Input Mode Mux", "Differential Mic", 855 "Right Input Mux" }, 856 { "Right Input Mode Mux", "Differential Mic", 857 "Right Input Inverting Mux" }, 858 859 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 860 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 861 862 { "ADCL", NULL, "Left Input PGA" }, 863 { "ADCL", NULL, "CLK_DSP" }, 864 { "ADCR", NULL, "Right Input PGA" }, 865 { "ADCR", NULL, "CLK_DSP" }, 866 867 { "DACL Sidetone", "Left", "ADCL" }, 868 { "DACL Sidetone", "Right", "ADCR" }, 869 { "DACR Sidetone", "Left", "ADCL" }, 870 { "DACR Sidetone", "Right", "ADCR" }, 871 872 { "DACL", NULL, "DACL Sidetone" }, 873 { "DACL", NULL, "CLK_DSP" }, 874 { "DACR", NULL, "DACR Sidetone" }, 875 { "DACR", NULL, "CLK_DSP" }, 876 877 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 878 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 879 { "Left Output Mixer", "DACL Switch", "DACL" }, 880 { "Left Output Mixer", "DACR Switch", "DACR" }, 881 882 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 883 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 884 { "Right Output Mixer", "DACL Switch", "DACL" }, 885 { "Right Output Mixer", "DACR Switch", "DACR" }, 886 887 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 888 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 889 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 890 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 891 892 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 893 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 894 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 895 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 896 897 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 898 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 899 900 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 901 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 902 903 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 904 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 905 906 { "HPOUTL", NULL, "Left Headphone Output PGA" }, 907 { "HPOUTR", NULL, "Right Headphone Output PGA" }, 908 909 { "LINEOUTL", NULL, "Left Line Output PGA" }, 910 { "LINEOUTR", NULL, "Right Line Output PGA" }, 911 912 { "LOP", NULL, "Left Speaker PGA" }, 913 { "LON", NULL, "Left Speaker PGA" }, 914 915 { "ROP", NULL, "Right Speaker PGA" }, 916 { "RON", NULL, "Right Speaker PGA" }, 917 918 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 919 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 920 { "Left Line Output PGA", NULL, "Charge Pump" }, 921 { "Right Line Output PGA", NULL, "Charge Pump" }, 922 }; 923 924 static int wm8903_add_widgets(struct snd_soc_codec *codec) 925 { 926 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, 927 ARRAY_SIZE(wm8903_dapm_widgets)); 928 929 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 930 931 return 0; 932 } 933 934 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 935 enum snd_soc_bias_level level) 936 { 937 u16 reg, reg2; 938 939 switch (level) { 940 case SND_SOC_BIAS_ON: 941 case SND_SOC_BIAS_PREPARE: 942 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 943 reg &= ~(WM8903_VMID_RES_MASK); 944 reg |= WM8903_VMID_RES_50K; 945 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 946 break; 947 948 case SND_SOC_BIAS_STANDBY: 949 if (codec->bias_level == SND_SOC_BIAS_OFF) { 950 snd_soc_write(codec, WM8903_CLOCK_RATES_2, 951 WM8903_CLK_SYS_ENA); 952 953 /* Change DC servo dither level in startup sequence */ 954 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); 955 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); 956 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); 957 958 wm8903_run_sequence(codec, 0); 959 wm8903_sync_reg_cache(codec, codec->reg_cache); 960 961 /* Enable low impedence charge pump output */ 962 reg = snd_soc_read(codec, 963 WM8903_CONTROL_INTERFACE_TEST_1); 964 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 965 reg | WM8903_TEST_KEY); 966 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); 967 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, 968 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); 969 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 970 reg); 971 972 /* By default no bypass paths are enabled so 973 * enable Class W support. 974 */ 975 dev_dbg(codec->dev, "Enabling Class W\n"); 976 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 977 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 978 } 979 980 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 981 reg &= ~(WM8903_VMID_RES_MASK); 982 reg |= WM8903_VMID_RES_250K; 983 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 984 break; 985 986 case SND_SOC_BIAS_OFF: 987 wm8903_run_sequence(codec, 32); 988 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2); 989 reg &= ~WM8903_CLK_SYS_ENA; 990 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg); 991 break; 992 } 993 994 codec->bias_level = level; 995 996 return 0; 997 } 998 999 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1000 int clk_id, unsigned int freq, int dir) 1001 { 1002 struct snd_soc_codec *codec = codec_dai->codec; 1003 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1004 1005 wm8903->sysclk = freq; 1006 1007 return 0; 1008 } 1009 1010 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1011 unsigned int fmt) 1012 { 1013 struct snd_soc_codec *codec = codec_dai->codec; 1014 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1015 1016 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1017 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1018 1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1020 case SND_SOC_DAIFMT_CBS_CFS: 1021 break; 1022 case SND_SOC_DAIFMT_CBS_CFM: 1023 aif1 |= WM8903_LRCLK_DIR; 1024 break; 1025 case SND_SOC_DAIFMT_CBM_CFM: 1026 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1027 break; 1028 case SND_SOC_DAIFMT_CBM_CFS: 1029 aif1 |= WM8903_BCLK_DIR; 1030 break; 1031 default: 1032 return -EINVAL; 1033 } 1034 1035 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1036 case SND_SOC_DAIFMT_DSP_A: 1037 aif1 |= 0x3; 1038 break; 1039 case SND_SOC_DAIFMT_DSP_B: 1040 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1041 break; 1042 case SND_SOC_DAIFMT_I2S: 1043 aif1 |= 0x2; 1044 break; 1045 case SND_SOC_DAIFMT_RIGHT_J: 1046 aif1 |= 0x1; 1047 break; 1048 case SND_SOC_DAIFMT_LEFT_J: 1049 break; 1050 default: 1051 return -EINVAL; 1052 } 1053 1054 /* Clock inversion */ 1055 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1056 case SND_SOC_DAIFMT_DSP_A: 1057 case SND_SOC_DAIFMT_DSP_B: 1058 /* frame inversion not valid for DSP modes */ 1059 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1060 case SND_SOC_DAIFMT_NB_NF: 1061 break; 1062 case SND_SOC_DAIFMT_IB_NF: 1063 aif1 |= WM8903_AIF_BCLK_INV; 1064 break; 1065 default: 1066 return -EINVAL; 1067 } 1068 break; 1069 case SND_SOC_DAIFMT_I2S: 1070 case SND_SOC_DAIFMT_RIGHT_J: 1071 case SND_SOC_DAIFMT_LEFT_J: 1072 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1073 case SND_SOC_DAIFMT_NB_NF: 1074 break; 1075 case SND_SOC_DAIFMT_IB_IF: 1076 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1077 break; 1078 case SND_SOC_DAIFMT_IB_NF: 1079 aif1 |= WM8903_AIF_BCLK_INV; 1080 break; 1081 case SND_SOC_DAIFMT_NB_IF: 1082 aif1 |= WM8903_AIF_LRCLK_INV; 1083 break; 1084 default: 1085 return -EINVAL; 1086 } 1087 break; 1088 default: 1089 return -EINVAL; 1090 } 1091 1092 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1093 1094 return 0; 1095 } 1096 1097 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1098 { 1099 struct snd_soc_codec *codec = codec_dai->codec; 1100 u16 reg; 1101 1102 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1103 1104 if (mute) 1105 reg |= WM8903_DAC_MUTE; 1106 else 1107 reg &= ~WM8903_DAC_MUTE; 1108 1109 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1110 1111 return 0; 1112 } 1113 1114 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1115 * for optimal performance so we list the lower rates first and match 1116 * on the last match we find. */ 1117 static struct { 1118 int div; 1119 int rate; 1120 int mode; 1121 int mclk_div; 1122 } clk_sys_ratios[] = { 1123 { 64, 0x0, 0x0, 1 }, 1124 { 68, 0x0, 0x1, 1 }, 1125 { 125, 0x0, 0x2, 1 }, 1126 { 128, 0x1, 0x0, 1 }, 1127 { 136, 0x1, 0x1, 1 }, 1128 { 192, 0x2, 0x0, 1 }, 1129 { 204, 0x2, 0x1, 1 }, 1130 1131 { 64, 0x0, 0x0, 2 }, 1132 { 68, 0x0, 0x1, 2 }, 1133 { 125, 0x0, 0x2, 2 }, 1134 { 128, 0x1, 0x0, 2 }, 1135 { 136, 0x1, 0x1, 2 }, 1136 { 192, 0x2, 0x0, 2 }, 1137 { 204, 0x2, 0x1, 2 }, 1138 1139 { 250, 0x2, 0x2, 1 }, 1140 { 256, 0x3, 0x0, 1 }, 1141 { 272, 0x3, 0x1, 1 }, 1142 { 384, 0x4, 0x0, 1 }, 1143 { 408, 0x4, 0x1, 1 }, 1144 { 375, 0x4, 0x2, 1 }, 1145 { 512, 0x5, 0x0, 1 }, 1146 { 544, 0x5, 0x1, 1 }, 1147 { 500, 0x5, 0x2, 1 }, 1148 { 768, 0x6, 0x0, 1 }, 1149 { 816, 0x6, 0x1, 1 }, 1150 { 750, 0x6, 0x2, 1 }, 1151 { 1024, 0x7, 0x0, 1 }, 1152 { 1088, 0x7, 0x1, 1 }, 1153 { 1000, 0x7, 0x2, 1 }, 1154 { 1408, 0x8, 0x0, 1 }, 1155 { 1496, 0x8, 0x1, 1 }, 1156 { 1536, 0x9, 0x0, 1 }, 1157 { 1632, 0x9, 0x1, 1 }, 1158 { 1500, 0x9, 0x2, 1 }, 1159 1160 { 250, 0x2, 0x2, 2 }, 1161 { 256, 0x3, 0x0, 2 }, 1162 { 272, 0x3, 0x1, 2 }, 1163 { 384, 0x4, 0x0, 2 }, 1164 { 408, 0x4, 0x1, 2 }, 1165 { 375, 0x4, 0x2, 2 }, 1166 { 512, 0x5, 0x0, 2 }, 1167 { 544, 0x5, 0x1, 2 }, 1168 { 500, 0x5, 0x2, 2 }, 1169 { 768, 0x6, 0x0, 2 }, 1170 { 816, 0x6, 0x1, 2 }, 1171 { 750, 0x6, 0x2, 2 }, 1172 { 1024, 0x7, 0x0, 2 }, 1173 { 1088, 0x7, 0x1, 2 }, 1174 { 1000, 0x7, 0x2, 2 }, 1175 { 1408, 0x8, 0x0, 2 }, 1176 { 1496, 0x8, 0x1, 2 }, 1177 { 1536, 0x9, 0x0, 2 }, 1178 { 1632, 0x9, 0x1, 2 }, 1179 { 1500, 0x9, 0x2, 2 }, 1180 }; 1181 1182 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1183 static struct { 1184 int ratio; 1185 int div; 1186 } bclk_divs[] = { 1187 { 10, 0 }, 1188 { 20, 2 }, 1189 { 30, 3 }, 1190 { 40, 4 }, 1191 { 50, 5 }, 1192 { 60, 7 }, 1193 { 80, 8 }, 1194 { 100, 9 }, 1195 { 120, 11 }, 1196 { 160, 12 }, 1197 { 200, 13 }, 1198 { 220, 14 }, 1199 { 240, 15 }, 1200 { 300, 17 }, 1201 { 320, 18 }, 1202 { 440, 19 }, 1203 { 480, 20 }, 1204 }; 1205 1206 /* Sample rates for DSP */ 1207 static struct { 1208 int rate; 1209 int value; 1210 } sample_rates[] = { 1211 { 8000, 0 }, 1212 { 11025, 1 }, 1213 { 12000, 2 }, 1214 { 16000, 3 }, 1215 { 22050, 4 }, 1216 { 24000, 5 }, 1217 { 32000, 6 }, 1218 { 44100, 7 }, 1219 { 48000, 8 }, 1220 { 88200, 9 }, 1221 { 96000, 10 }, 1222 { 0, 0 }, 1223 }; 1224 1225 static int wm8903_startup(struct snd_pcm_substream *substream, 1226 struct snd_soc_dai *dai) 1227 { 1228 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1229 struct snd_soc_codec *codec = rtd->codec; 1230 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1231 struct snd_pcm_runtime *master_runtime; 1232 1233 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1234 wm8903->playback_active++; 1235 else 1236 wm8903->capture_active++; 1237 1238 /* The DAI has shared clocks so if we already have a playback or 1239 * capture going then constrain this substream to match it. 1240 */ 1241 if (wm8903->master_substream) { 1242 master_runtime = wm8903->master_substream->runtime; 1243 1244 dev_dbg(codec->dev, "Constraining to %d bits\n", 1245 master_runtime->sample_bits); 1246 1247 snd_pcm_hw_constraint_minmax(substream->runtime, 1248 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1249 master_runtime->sample_bits, 1250 master_runtime->sample_bits); 1251 1252 wm8903->slave_substream = substream; 1253 } else 1254 wm8903->master_substream = substream; 1255 1256 return 0; 1257 } 1258 1259 static void wm8903_shutdown(struct snd_pcm_substream *substream, 1260 struct snd_soc_dai *dai) 1261 { 1262 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1263 struct snd_soc_codec *codec = rtd->codec; 1264 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1265 1266 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1267 wm8903->playback_active--; 1268 else 1269 wm8903->capture_active--; 1270 1271 if (wm8903->master_substream == substream) 1272 wm8903->master_substream = wm8903->slave_substream; 1273 1274 wm8903->slave_substream = NULL; 1275 } 1276 1277 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1278 struct snd_pcm_hw_params *params, 1279 struct snd_soc_dai *dai) 1280 { 1281 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1282 struct snd_soc_codec *codec =rtd->codec; 1283 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1284 int fs = params_rate(params); 1285 int bclk; 1286 int bclk_div; 1287 int i; 1288 int dsp_config; 1289 int clk_config; 1290 int best_val; 1291 int cur_val; 1292 int clk_sys; 1293 1294 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1295 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1296 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1297 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1298 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1299 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1300 1301 if (substream == wm8903->slave_substream) { 1302 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n"); 1303 return 0; 1304 } 1305 1306 /* Enable sloping stopband filter for low sample rates */ 1307 if (fs <= 24000) 1308 dac_digital1 |= WM8903_DAC_SB_FILT; 1309 else 1310 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1311 1312 /* Configure sample rate logic for DSP - choose nearest rate */ 1313 dsp_config = 0; 1314 best_val = abs(sample_rates[dsp_config].rate - fs); 1315 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1316 cur_val = abs(sample_rates[i].rate - fs); 1317 if (cur_val <= best_val) { 1318 dsp_config = i; 1319 best_val = cur_val; 1320 } 1321 } 1322 1323 /* Constraints should stop us hitting this but let's make sure */ 1324 if (wm8903->capture_active) 1325 switch (sample_rates[dsp_config].rate) { 1326 case 88200: 1327 case 96000: 1328 dev_err(codec->dev, "%dHz unsupported by ADC\n", 1329 fs); 1330 return -EINVAL; 1331 1332 default: 1333 break; 1334 } 1335 1336 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1337 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1338 clock1 |= sample_rates[dsp_config].value; 1339 1340 aif1 &= ~WM8903_AIF_WL_MASK; 1341 bclk = 2 * fs; 1342 switch (params_format(params)) { 1343 case SNDRV_PCM_FORMAT_S16_LE: 1344 bclk *= 16; 1345 break; 1346 case SNDRV_PCM_FORMAT_S20_3LE: 1347 bclk *= 20; 1348 aif1 |= 0x4; 1349 break; 1350 case SNDRV_PCM_FORMAT_S24_LE: 1351 bclk *= 24; 1352 aif1 |= 0x8; 1353 break; 1354 case SNDRV_PCM_FORMAT_S32_LE: 1355 bclk *= 32; 1356 aif1 |= 0xc; 1357 break; 1358 default: 1359 return -EINVAL; 1360 } 1361 1362 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1363 wm8903->sysclk, fs); 1364 1365 /* We may not have an MCLK which allows us to generate exactly 1366 * the clock we want, particularly with USB derived inputs, so 1367 * approximate. 1368 */ 1369 clk_config = 0; 1370 best_val = abs((wm8903->sysclk / 1371 (clk_sys_ratios[0].mclk_div * 1372 clk_sys_ratios[0].div)) - fs); 1373 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1374 cur_val = abs((wm8903->sysclk / 1375 (clk_sys_ratios[i].mclk_div * 1376 clk_sys_ratios[i].div)) - fs); 1377 1378 if (cur_val <= best_val) { 1379 clk_config = i; 1380 best_val = cur_val; 1381 } 1382 } 1383 1384 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1385 clock0 |= WM8903_MCLKDIV2; 1386 clk_sys = wm8903->sysclk / 2; 1387 } else { 1388 clock0 &= ~WM8903_MCLKDIV2; 1389 clk_sys = wm8903->sysclk; 1390 } 1391 1392 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1393 WM8903_CLK_SYS_MODE_MASK); 1394 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1395 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1396 1397 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1398 clk_sys_ratios[clk_config].rate, 1399 clk_sys_ratios[clk_config].mode, 1400 clk_sys_ratios[clk_config].div); 1401 1402 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1403 1404 /* We may not get quite the right frequency if using 1405 * approximate clocks so look for the closest match that is 1406 * higher than the target (we need to ensure that there enough 1407 * BCLKs to clock out the samples). 1408 */ 1409 bclk_div = 0; 1410 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1411 i = 1; 1412 while (i < ARRAY_SIZE(bclk_divs)) { 1413 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1414 if (cur_val < 0) /* BCLK table is sorted */ 1415 break; 1416 bclk_div = i; 1417 best_val = cur_val; 1418 i++; 1419 } 1420 1421 aif2 &= ~WM8903_BCLK_DIV_MASK; 1422 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1423 1424 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1425 bclk_divs[bclk_div].ratio / 10, bclk, 1426 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1427 1428 aif2 |= bclk_divs[bclk_div].div; 1429 aif3 |= bclk / fs; 1430 1431 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1432 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1434 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1435 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1436 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1437 1438 return 0; 1439 } 1440 1441 /** 1442 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1443 * 1444 * @codec: WM8903 codec 1445 * @jack: jack to report detection events on 1446 * @det: value to report for presence detection 1447 * @shrt: value to report for short detection 1448 * 1449 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1450 * being used to bring out signals to the processor then only platform 1451 * data configuration is needed for WM8903 and processor GPIOs should 1452 * be configured using snd_soc_jack_add_gpios() instead. 1453 * 1454 * The current threasholds for detection should be configured using 1455 * micdet_cfg in the platform data. Using this function will force on 1456 * the microphone bias for the device. 1457 */ 1458 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1459 int det, int shrt) 1460 { 1461 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1462 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1463 1464 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1465 det, shrt); 1466 1467 /* Store the configuration */ 1468 wm8903->mic_jack = jack; 1469 wm8903->mic_det = det; 1470 wm8903->mic_short = shrt; 1471 1472 /* Enable interrupts we've got a report configured for */ 1473 if (det) 1474 irq_mask &= ~WM8903_MICDET_EINT; 1475 if (shrt) 1476 irq_mask &= ~WM8903_MICSHRT_EINT; 1477 1478 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1479 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1480 irq_mask); 1481 1482 if (det && shrt) { 1483 /* Enable mic detection, this may not have been set through 1484 * platform data (eg, if the defaults are OK). */ 1485 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1486 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1487 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1488 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1489 } else { 1490 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1491 WM8903_MICDET_ENA, 0); 1492 } 1493 1494 return 0; 1495 } 1496 EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1497 1498 static irqreturn_t wm8903_irq(int irq, void *data) 1499 { 1500 struct snd_soc_codec *codec = data; 1501 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1502 int mic_report; 1503 int int_pol; 1504 int int_val = 0; 1505 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); 1506 1507 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; 1508 1509 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1510 dev_dbg(codec->dev, "Write sequencer done\n"); 1511 complete(&wm8903->wseq); 1512 } 1513 1514 /* 1515 * The rest is microphone jack detection. We need to manually 1516 * invert the polarity of the interrupt after each event - to 1517 * simplify the code keep track of the last state we reported 1518 * and just invert the relevant bits in both the report and 1519 * the polarity register. 1520 */ 1521 mic_report = wm8903->mic_last_report; 1522 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1523 1524 if (int_val & WM8903_MICSHRT_EINT) { 1525 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1526 1527 mic_report ^= wm8903->mic_short; 1528 int_pol ^= WM8903_MICSHRT_INV; 1529 } 1530 1531 if (int_val & WM8903_MICDET_EINT) { 1532 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); 1533 1534 mic_report ^= wm8903->mic_det; 1535 int_pol ^= WM8903_MICDET_INV; 1536 1537 msleep(wm8903->mic_delay); 1538 } 1539 1540 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, 1541 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1542 1543 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1544 wm8903->mic_short | wm8903->mic_det); 1545 1546 wm8903->mic_last_report = mic_report; 1547 1548 return IRQ_HANDLED; 1549 } 1550 1551 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1552 SNDRV_PCM_RATE_11025 | \ 1553 SNDRV_PCM_RATE_16000 | \ 1554 SNDRV_PCM_RATE_22050 | \ 1555 SNDRV_PCM_RATE_32000 | \ 1556 SNDRV_PCM_RATE_44100 | \ 1557 SNDRV_PCM_RATE_48000 | \ 1558 SNDRV_PCM_RATE_88200 | \ 1559 SNDRV_PCM_RATE_96000) 1560 1561 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1562 SNDRV_PCM_RATE_11025 | \ 1563 SNDRV_PCM_RATE_16000 | \ 1564 SNDRV_PCM_RATE_22050 | \ 1565 SNDRV_PCM_RATE_32000 | \ 1566 SNDRV_PCM_RATE_44100 | \ 1567 SNDRV_PCM_RATE_48000) 1568 1569 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1570 SNDRV_PCM_FMTBIT_S20_3LE |\ 1571 SNDRV_PCM_FMTBIT_S24_LE) 1572 1573 static struct snd_soc_dai_ops wm8903_dai_ops = { 1574 .startup = wm8903_startup, 1575 .shutdown = wm8903_shutdown, 1576 .hw_params = wm8903_hw_params, 1577 .digital_mute = wm8903_digital_mute, 1578 .set_fmt = wm8903_set_dai_fmt, 1579 .set_sysclk = wm8903_set_dai_sysclk, 1580 }; 1581 1582 static struct snd_soc_dai_driver wm8903_dai = { 1583 .name = "wm8903-hifi", 1584 .playback = { 1585 .stream_name = "Playback", 1586 .channels_min = 2, 1587 .channels_max = 2, 1588 .rates = WM8903_PLAYBACK_RATES, 1589 .formats = WM8903_FORMATS, 1590 }, 1591 .capture = { 1592 .stream_name = "Capture", 1593 .channels_min = 2, 1594 .channels_max = 2, 1595 .rates = WM8903_CAPTURE_RATES, 1596 .formats = WM8903_FORMATS, 1597 }, 1598 .ops = &wm8903_dai_ops, 1599 .symmetric_rates = 1, 1600 }; 1601 1602 static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state) 1603 { 1604 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1605 1606 return 0; 1607 } 1608 1609 static int wm8903_resume(struct snd_soc_codec *codec) 1610 { 1611 int i; 1612 u16 *reg_cache = codec->reg_cache; 1613 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults), 1614 GFP_KERNEL); 1615 1616 /* Bring the codec back up to standby first to minimise pop/clicks */ 1617 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1618 1619 /* Sync back everything else */ 1620 if (tmp_cache) { 1621 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1622 if (tmp_cache[i] != reg_cache[i]) 1623 snd_soc_write(codec, i, tmp_cache[i]); 1624 kfree(tmp_cache); 1625 } else { 1626 dev_err(codec->dev, "Failed to allocate temporary cache\n"); 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int wm8903_probe(struct snd_soc_codec *codec) 1633 { 1634 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); 1635 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1636 int ret, i; 1637 int trigger, irq_pol; 1638 u16 val; 1639 1640 init_completion(&wm8903->wseq); 1641 1642 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1643 if (ret != 0) { 1644 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1645 return ret; 1646 } 1647 1648 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); 1649 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1650 dev_err(codec->dev, 1651 "Device with ID register %x is not a WM8903\n", val); 1652 return -ENODEV; 1653 } 1654 1655 val = snd_soc_read(codec, WM8903_REVISION_NUMBER); 1656 dev_info(codec->dev, "WM8903 revision %d\n", 1657 val & WM8903_CHIP_REV_MASK); 1658 1659 wm8903_reset(codec); 1660 1661 /* Set up GPIOs and microphone detection */ 1662 if (pdata) { 1663 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1664 if (!pdata->gpio_cfg[i]) 1665 continue; 1666 1667 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, 1668 pdata->gpio_cfg[i] & 0xffff); 1669 } 1670 1671 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, 1672 pdata->micdet_cfg); 1673 1674 /* Microphone detection needs the WSEQ clock */ 1675 if (pdata->micdet_cfg) 1676 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1677 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1678 1679 wm8903->mic_delay = pdata->micdet_delay; 1680 } 1681 1682 if (wm8903->irq) { 1683 if (pdata && pdata->irq_active_low) { 1684 trigger = IRQF_TRIGGER_LOW; 1685 irq_pol = WM8903_IRQ_POL; 1686 } else { 1687 trigger = IRQF_TRIGGER_HIGH; 1688 irq_pol = 0; 1689 } 1690 1691 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, 1692 WM8903_IRQ_POL, irq_pol); 1693 1694 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq, 1695 trigger | IRQF_ONESHOT, 1696 "wm8903", codec); 1697 if (ret != 0) { 1698 dev_err(codec->dev, "Failed to request IRQ: %d\n", 1699 ret); 1700 return ret; 1701 } 1702 1703 /* Enable write sequencer interrupts */ 1704 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1705 WM8903_IM_WSEQ_BUSY_EINT, 0); 1706 } 1707 1708 /* power on device */ 1709 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1710 1711 /* Latch volume update bits */ 1712 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1713 val |= WM8903_ADCVU; 1714 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1715 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1716 1717 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1718 val |= WM8903_DACVU; 1719 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1720 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1721 1722 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1723 val |= WM8903_HPOUTVU; 1724 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1725 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1726 1727 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1728 val |= WM8903_LINEOUTVU; 1729 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1730 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1731 1732 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1733 val |= WM8903_SPKVU; 1734 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1735 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1736 1737 /* Enable DAC soft mute by default */ 1738 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1739 val |= WM8903_DAC_MUTEMODE; 1740 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val); 1741 1742 snd_soc_add_controls(codec, wm8903_snd_controls, 1743 ARRAY_SIZE(wm8903_snd_controls)); 1744 wm8903_add_widgets(codec); 1745 1746 return ret; 1747 } 1748 1749 /* power down chip */ 1750 static int wm8903_remove(struct snd_soc_codec *codec) 1751 { 1752 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1753 return 0; 1754 } 1755 1756 static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { 1757 .probe = wm8903_probe, 1758 .remove = wm8903_remove, 1759 .suspend = wm8903_suspend, 1760 .resume = wm8903_resume, 1761 .set_bias_level = wm8903_set_bias_level, 1762 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults), 1763 .reg_word_size = sizeof(u16), 1764 .reg_cache_default = wm8903_reg_defaults, 1765 .volatile_register = wm8903_volatile_register, 1766 }; 1767 1768 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1769 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, 1770 const struct i2c_device_id *id) 1771 { 1772 struct wm8903_priv *wm8903; 1773 int ret; 1774 1775 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); 1776 if (wm8903 == NULL) 1777 return -ENOMEM; 1778 1779 i2c_set_clientdata(i2c, wm8903); 1780 wm8903->irq = i2c->irq; 1781 1782 ret = snd_soc_register_codec(&i2c->dev, 1783 &soc_codec_dev_wm8903, &wm8903_dai, 1); 1784 if (ret < 0) 1785 kfree(wm8903); 1786 return ret; 1787 } 1788 1789 static __devexit int wm8903_i2c_remove(struct i2c_client *client) 1790 { 1791 snd_soc_unregister_codec(&client->dev); 1792 kfree(i2c_get_clientdata(client)); 1793 return 0; 1794 } 1795 1796 static const struct i2c_device_id wm8903_i2c_id[] = { 1797 { "wm8903", 0 }, 1798 { } 1799 }; 1800 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 1801 1802 static struct i2c_driver wm8903_i2c_driver = { 1803 .driver = { 1804 .name = "wm8903-codec", 1805 .owner = THIS_MODULE, 1806 }, 1807 .probe = wm8903_i2c_probe, 1808 .remove = __devexit_p(wm8903_i2c_remove), 1809 .id_table = wm8903_i2c_id, 1810 }; 1811 #endif 1812 1813 static int __init wm8903_modinit(void) 1814 { 1815 int ret = 0; 1816 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1817 ret = i2c_add_driver(&wm8903_i2c_driver); 1818 if (ret != 0) { 1819 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n", 1820 ret); 1821 } 1822 #endif 1823 return ret; 1824 } 1825 module_init(wm8903_modinit); 1826 1827 static void __exit wm8903_exit(void) 1828 { 1829 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1830 i2c_del_driver(&wm8903_i2c_driver); 1831 #endif 1832 } 1833 module_exit(wm8903_exit); 1834 1835 MODULE_DESCRIPTION("ASoC WM8903 driver"); 1836 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 1837 MODULE_LICENSE("GPL"); 1838