1 /* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: 13 * - TDM mode configuration. 14 * - Mic detect. 15 * - Digital microphone support. 16 * - Interrupt support (mic detect and sequencer). 17 */ 18 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/pm.h> 24 #include <linux/i2c.h> 25 #include <linux/platform_device.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/tlv.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 34 #include "wm8903.h" 35 36 /* Register defaults at reset */ 37 static u16 wm8903_reg_defaults[] = { 38 0x8903, /* R0 - SW Reset and ID */ 39 0x0000, /* R1 - Revision Number */ 40 0x0000, /* R2 */ 41 0x0000, /* R3 */ 42 0x0018, /* R4 - Bias Control 0 */ 43 0x0000, /* R5 - VMID Control 0 */ 44 0x0000, /* R6 - Mic Bias Control 0 */ 45 0x0000, /* R7 */ 46 0x0001, /* R8 - Analogue DAC 0 */ 47 0x0000, /* R9 */ 48 0x0001, /* R10 - Analogue ADC 0 */ 49 0x0000, /* R11 */ 50 0x0000, /* R12 - Power Management 0 */ 51 0x0000, /* R13 - Power Management 1 */ 52 0x0000, /* R14 - Power Management 2 */ 53 0x0000, /* R15 - Power Management 3 */ 54 0x0000, /* R16 - Power Management 4 */ 55 0x0000, /* R17 - Power Management 5 */ 56 0x0000, /* R18 - Power Management 6 */ 57 0x0000, /* R19 */ 58 0x0400, /* R20 - Clock Rates 0 */ 59 0x0D07, /* R21 - Clock Rates 1 */ 60 0x0000, /* R22 - Clock Rates 2 */ 61 0x0000, /* R23 */ 62 0x0050, /* R24 - Audio Interface 0 */ 63 0x0242, /* R25 - Audio Interface 1 */ 64 0x0008, /* R26 - Audio Interface 2 */ 65 0x0022, /* R27 - Audio Interface 3 */ 66 0x0000, /* R28 */ 67 0x0000, /* R29 */ 68 0x00C0, /* R30 - DAC Digital Volume Left */ 69 0x00C0, /* R31 - DAC Digital Volume Right */ 70 0x0000, /* R32 - DAC Digital 0 */ 71 0x0000, /* R33 - DAC Digital 1 */ 72 0x0000, /* R34 */ 73 0x0000, /* R35 */ 74 0x00C0, /* R36 - ADC Digital Volume Left */ 75 0x00C0, /* R37 - ADC Digital Volume Right */ 76 0x0000, /* R38 - ADC Digital 0 */ 77 0x0073, /* R39 - Digital Microphone 0 */ 78 0x09BF, /* R40 - DRC 0 */ 79 0x3241, /* R41 - DRC 1 */ 80 0x0020, /* R42 - DRC 2 */ 81 0x0000, /* R43 - DRC 3 */ 82 0x0085, /* R44 - Analogue Left Input 0 */ 83 0x0085, /* R45 - Analogue Right Input 0 */ 84 0x0044, /* R46 - Analogue Left Input 1 */ 85 0x0044, /* R47 - Analogue Right Input 1 */ 86 0x0000, /* R48 */ 87 0x0000, /* R49 */ 88 0x0008, /* R50 - Analogue Left Mix 0 */ 89 0x0004, /* R51 - Analogue Right Mix 0 */ 90 0x0000, /* R52 - Analogue Spk Mix Left 0 */ 91 0x0000, /* R53 - Analogue Spk Mix Left 1 */ 92 0x0000, /* R54 - Analogue Spk Mix Right 0 */ 93 0x0000, /* R55 - Analogue Spk Mix Right 1 */ 94 0x0000, /* R56 */ 95 0x002D, /* R57 - Analogue OUT1 Left */ 96 0x002D, /* R58 - Analogue OUT1 Right */ 97 0x0039, /* R59 - Analogue OUT2 Left */ 98 0x0039, /* R60 - Analogue OUT2 Right */ 99 0x0100, /* R61 */ 100 0x0139, /* R62 - Analogue OUT3 Left */ 101 0x0139, /* R63 - Analogue OUT3 Right */ 102 0x0000, /* R64 */ 103 0x0000, /* R65 - Analogue SPK Output Control 0 */ 104 0x0000, /* R66 */ 105 0x0010, /* R67 - DC Servo 0 */ 106 0x0100, /* R68 */ 107 0x00A4, /* R69 - DC Servo 2 */ 108 0x0807, /* R70 */ 109 0x0000, /* R71 */ 110 0x0000, /* R72 */ 111 0x0000, /* R73 */ 112 0x0000, /* R74 */ 113 0x0000, /* R75 */ 114 0x0000, /* R76 */ 115 0x0000, /* R77 */ 116 0x0000, /* R78 */ 117 0x000E, /* R79 */ 118 0x0000, /* R80 */ 119 0x0000, /* R81 */ 120 0x0000, /* R82 */ 121 0x0000, /* R83 */ 122 0x0000, /* R84 */ 123 0x0000, /* R85 */ 124 0x0000, /* R86 */ 125 0x0006, /* R87 */ 126 0x0000, /* R88 */ 127 0x0000, /* R89 */ 128 0x0000, /* R90 - Analogue HP 0 */ 129 0x0060, /* R91 */ 130 0x0000, /* R92 */ 131 0x0000, /* R93 */ 132 0x0000, /* R94 - Analogue Lineout 0 */ 133 0x0060, /* R95 */ 134 0x0000, /* R96 */ 135 0x0000, /* R97 */ 136 0x0000, /* R98 - Charge Pump 0 */ 137 0x1F25, /* R99 */ 138 0x2B19, /* R100 */ 139 0x01C0, /* R101 */ 140 0x01EF, /* R102 */ 141 0x2B00, /* R103 */ 142 0x0000, /* R104 - Class W 0 */ 143 0x01C0, /* R105 */ 144 0x1C10, /* R106 */ 145 0x0000, /* R107 */ 146 0x0000, /* R108 - Write Sequencer 0 */ 147 0x0000, /* R109 - Write Sequencer 1 */ 148 0x0000, /* R110 - Write Sequencer 2 */ 149 0x0000, /* R111 - Write Sequencer 3 */ 150 0x0000, /* R112 - Write Sequencer 4 */ 151 0x0000, /* R113 */ 152 0x0000, /* R114 - Control Interface */ 153 0x0000, /* R115 */ 154 0x00A8, /* R116 - GPIO Control 1 */ 155 0x00A8, /* R117 - GPIO Control 2 */ 156 0x00A8, /* R118 - GPIO Control 3 */ 157 0x0220, /* R119 - GPIO Control 4 */ 158 0x01A0, /* R120 - GPIO Control 5 */ 159 0x0000, /* R121 - Interrupt Status 1 */ 160 0xFFFF, /* R122 - Interrupt Status 1 Mask */ 161 0x0000, /* R123 - Interrupt Polarity 1 */ 162 0x0000, /* R124 */ 163 0x0003, /* R125 */ 164 0x0000, /* R126 - Interrupt Control */ 165 0x0000, /* R127 */ 166 0x0005, /* R128 */ 167 0x0000, /* R129 - Control Interface Test 1 */ 168 0x0000, /* R130 */ 169 0x0000, /* R131 */ 170 0x0000, /* R132 */ 171 0x0000, /* R133 */ 172 0x0000, /* R134 */ 173 0x03FF, /* R135 */ 174 0x0007, /* R136 */ 175 0x0040, /* R137 */ 176 0x0000, /* R138 */ 177 0x0000, /* R139 */ 178 0x0000, /* R140 */ 179 0x0000, /* R141 */ 180 0x0000, /* R142 */ 181 0x0000, /* R143 */ 182 0x0000, /* R144 */ 183 0x0000, /* R145 */ 184 0x0000, /* R146 */ 185 0x0000, /* R147 */ 186 0x4000, /* R148 */ 187 0x6810, /* R149 - Charge Pump Test 1 */ 188 0x0004, /* R150 */ 189 0x0000, /* R151 */ 190 0x0000, /* R152 */ 191 0x0000, /* R153 */ 192 0x0000, /* R154 */ 193 0x0000, /* R155 */ 194 0x0000, /* R156 */ 195 0x0000, /* R157 */ 196 0x0000, /* R158 */ 197 0x0000, /* R159 */ 198 0x0000, /* R160 */ 199 0x0000, /* R161 */ 200 0x0000, /* R162 */ 201 0x0000, /* R163 */ 202 0x0028, /* R164 - Clock Rate Test 4 */ 203 0x0004, /* R165 */ 204 0x0000, /* R166 */ 205 0x0060, /* R167 */ 206 0x0000, /* R168 */ 207 0x0000, /* R169 */ 208 0x0000, /* R170 */ 209 0x0000, /* R171 */ 210 0x0000, /* R172 - Analogue Output Bias 0 */ 211 }; 212 213 struct wm8903_priv { 214 struct snd_soc_codec codec; 215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; 216 217 int sysclk; 218 219 /* Reference counts */ 220 int class_w_users; 221 int playback_active; 222 int capture_active; 223 224 struct snd_pcm_substream *master_substream; 225 struct snd_pcm_substream *slave_substream; 226 }; 227 228 static int wm8903_volatile_register(unsigned int reg) 229 { 230 switch (reg) { 231 case WM8903_SW_RESET_AND_ID: 232 case WM8903_REVISION_NUMBER: 233 case WM8903_INTERRUPT_STATUS_1: 234 case WM8903_WRITE_SEQUENCER_4: 235 return 1; 236 237 default: 238 return 0; 239 } 240 } 241 242 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) 243 { 244 u16 reg[5]; 245 struct i2c_client *i2c = codec->control_data; 246 247 BUG_ON(start > 48); 248 249 /* Enable the sequencer */ 250 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0); 251 reg[0] |= WM8903_WSEQ_ENA; 252 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); 253 254 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start); 255 256 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3, 257 start | WM8903_WSEQ_START); 258 259 /* Wait for it to complete. If we have the interrupt wired up then 260 * we could block waiting for an interrupt, though polling may still 261 * be desirable for diagnostic purposes. 262 */ 263 do { 264 msleep(10); 265 266 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4); 267 } while (reg[4] & WM8903_WSEQ_BUSY); 268 269 dev_dbg(&i2c->dev, "Sequence complete\n"); 270 271 /* Disable the sequencer again */ 272 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 273 reg[0] & ~WM8903_WSEQ_ENA); 274 275 return 0; 276 } 277 278 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache) 279 { 280 int i; 281 282 /* There really ought to be something better we can do here :/ */ 283 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 284 cache[i] = codec->hw_read(codec, i); 285 } 286 287 static void wm8903_reset(struct snd_soc_codec *codec) 288 { 289 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); 290 memcpy(codec->reg_cache, wm8903_reg_defaults, 291 sizeof(wm8903_reg_defaults)); 292 } 293 294 #define WM8903_OUTPUT_SHORT 0x8 295 #define WM8903_OUTPUT_OUT 0x4 296 #define WM8903_OUTPUT_INT 0x2 297 #define WM8903_OUTPUT_IN 0x1 298 299 static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 300 struct snd_kcontrol *kcontrol, int event) 301 { 302 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 303 mdelay(4); 304 305 return 0; 306 } 307 308 /* 309 * Event for headphone and line out amplifier power changes. Special 310 * power up/down sequences are required in order to maximise pop/click 311 * performance. 312 */ 313 static int wm8903_output_event(struct snd_soc_dapm_widget *w, 314 struct snd_kcontrol *kcontrol, int event) 315 { 316 struct snd_soc_codec *codec = w->codec; 317 u16 val; 318 u16 reg; 319 u16 dcs_reg; 320 u16 dcs_bit; 321 int shift; 322 323 switch (w->reg) { 324 case WM8903_POWER_MANAGEMENT_2: 325 reg = WM8903_ANALOGUE_HP_0; 326 dcs_bit = 0 + w->shift; 327 break; 328 case WM8903_POWER_MANAGEMENT_3: 329 reg = WM8903_ANALOGUE_LINEOUT_0; 330 dcs_bit = 2 + w->shift; 331 break; 332 default: 333 BUG(); 334 return -EINVAL; /* Spurious warning from some compilers */ 335 } 336 337 switch (w->shift) { 338 case 0: 339 shift = 0; 340 break; 341 case 1: 342 shift = 4; 343 break; 344 default: 345 BUG(); 346 return -EINVAL; /* Spurious warning from some compilers */ 347 } 348 349 if (event & SND_SOC_DAPM_PRE_PMU) { 350 val = snd_soc_read(codec, reg); 351 352 /* Short the output */ 353 val &= ~(WM8903_OUTPUT_SHORT << shift); 354 snd_soc_write(codec, reg, val); 355 } 356 357 if (event & SND_SOC_DAPM_POST_PMU) { 358 val = snd_soc_read(codec, reg); 359 360 val |= (WM8903_OUTPUT_IN << shift); 361 snd_soc_write(codec, reg, val); 362 363 val |= (WM8903_OUTPUT_INT << shift); 364 snd_soc_write(codec, reg, val); 365 366 /* Turn on the output ENA_OUTP */ 367 val |= (WM8903_OUTPUT_OUT << shift); 368 snd_soc_write(codec, reg, val); 369 370 /* Enable the DC servo */ 371 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 372 dcs_reg |= dcs_bit; 373 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 374 375 /* Remove the short */ 376 val |= (WM8903_OUTPUT_SHORT << shift); 377 snd_soc_write(codec, reg, val); 378 } 379 380 if (event & SND_SOC_DAPM_PRE_PMD) { 381 val = snd_soc_read(codec, reg); 382 383 /* Short the output */ 384 val &= ~(WM8903_OUTPUT_SHORT << shift); 385 snd_soc_write(codec, reg, val); 386 387 /* Disable the DC servo */ 388 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); 389 dcs_reg &= ~dcs_bit; 390 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); 391 392 /* Then disable the intermediate and output stages */ 393 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 394 WM8903_OUTPUT_IN) << shift); 395 snd_soc_write(codec, reg, val); 396 } 397 398 return 0; 399 } 400 401 /* 402 * When used with DAC outputs only the WM8903 charge pump supports 403 * operation in class W mode, providing very low power consumption 404 * when used with digital sources. Enable and disable this mode 405 * automatically depending on the mixer configuration. 406 * 407 * All the relevant controls are simple switches. 408 */ 409 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 410 struct snd_ctl_elem_value *ucontrol) 411 { 412 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 413 struct snd_soc_codec *codec = widget->codec; 414 struct wm8903_priv *wm8903 = codec->private_data; 415 struct i2c_client *i2c = codec->control_data; 416 u16 reg; 417 int ret; 418 419 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 420 421 /* Turn it off if we're about to enable bypass */ 422 if (ucontrol->value.integer.value[0]) { 423 if (wm8903->class_w_users == 0) { 424 dev_dbg(&i2c->dev, "Disabling Class W\n"); 425 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 426 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 427 } 428 wm8903->class_w_users++; 429 } 430 431 /* Implement the change */ 432 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 433 434 /* If we've just disabled the last bypass path turn Class W on */ 435 if (!ucontrol->value.integer.value[0]) { 436 if (wm8903->class_w_users == 1) { 437 dev_dbg(&i2c->dev, "Enabling Class W\n"); 438 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 439 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 440 } 441 wm8903->class_w_users--; 442 } 443 444 dev_dbg(&i2c->dev, "Bypass use count now %d\n", 445 wm8903->class_w_users); 446 447 return ret; 448 } 449 450 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 451 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 452 .info = snd_soc_info_volsw, \ 453 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ 454 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 455 456 457 /* ALSA can only do steps of .01dB */ 458 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 459 460 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 461 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 462 463 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 464 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 465 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 466 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 467 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 468 469 static const char *drc_slope_text[] = { 470 "1", "1/2", "1/4", "1/8", "1/16", "0" 471 }; 472 473 static const struct soc_enum drc_slope_r0 = 474 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); 475 476 static const struct soc_enum drc_slope_r1 = 477 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); 478 479 static const char *drc_attack_text[] = { 480 "instantaneous", 481 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 482 "46.4ms", "92.8ms", "185.6ms" 483 }; 484 485 static const struct soc_enum drc_attack = 486 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); 487 488 static const char *drc_decay_text[] = { 489 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 490 "23.87s", "47.56s" 491 }; 492 493 static const struct soc_enum drc_decay = 494 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); 495 496 static const char *drc_ff_delay_text[] = { 497 "5 samples", "9 samples" 498 }; 499 500 static const struct soc_enum drc_ff_delay = 501 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); 502 503 static const char *drc_qr_decay_text[] = { 504 "0.725ms", "1.45ms", "5.8ms" 505 }; 506 507 static const struct soc_enum drc_qr_decay = 508 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); 509 510 static const char *drc_smoothing_text[] = { 511 "Low", "Medium", "High" 512 }; 513 514 static const struct soc_enum drc_smoothing = 515 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); 516 517 static const char *soft_mute_text[] = { 518 "Fast (fs/2)", "Slow (fs/32)" 519 }; 520 521 static const struct soc_enum soft_mute = 522 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); 523 524 static const char *mute_mode_text[] = { 525 "Hard", "Soft" 526 }; 527 528 static const struct soc_enum mute_mode = 529 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 530 531 static const char *dac_deemphasis_text[] = { 532 "Disabled", "32kHz", "44.1kHz", "48kHz" 533 }; 534 535 static const struct soc_enum dac_deemphasis = 536 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); 537 538 static const char *companding_text[] = { 539 "ulaw", "alaw" 540 }; 541 542 static const struct soc_enum dac_companding = 543 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); 544 545 static const struct soc_enum adc_companding = 546 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); 547 548 static const char *input_mode_text[] = { 549 "Single-Ended", "Differential Line", "Differential Mic" 550 }; 551 552 static const struct soc_enum linput_mode_enum = 553 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 554 555 static const struct soc_enum rinput_mode_enum = 556 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 557 558 static const char *linput_mux_text[] = { 559 "IN1L", "IN2L", "IN3L" 560 }; 561 562 static const struct soc_enum linput_enum = 563 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); 564 565 static const struct soc_enum linput_inv_enum = 566 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); 567 568 static const char *rinput_mux_text[] = { 569 "IN1R", "IN2R", "IN3R" 570 }; 571 572 static const struct soc_enum rinput_enum = 573 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); 574 575 static const struct soc_enum rinput_inv_enum = 576 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 577 578 579 static const char *sidetone_text[] = { 580 "None", "Left", "Right" 581 }; 582 583 static const struct soc_enum lsidetone_enum = 584 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); 585 586 static const struct soc_enum rsidetone_enum = 587 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); 588 589 static const struct snd_kcontrol_new wm8903_snd_controls[] = { 590 591 /* Input PGAs - No TLV since the scale depends on PGA mode */ 592 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 593 7, 1, 1), 594 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 595 0, 31, 0), 596 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 597 6, 1, 0), 598 599 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 600 7, 1, 1), 601 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 602 0, 31, 0), 603 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 604 6, 1, 0), 605 606 /* ADCs */ 607 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 608 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 609 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 610 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 611 drc_tlv_thresh), 612 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 613 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 614 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 615 SOC_ENUM("DRC Attack Rate", drc_attack), 616 SOC_ENUM("DRC Decay Rate", drc_decay), 617 SOC_ENUM("DRC FF Delay", drc_ff_delay), 618 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 619 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 620 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 621 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 622 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 623 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 624 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 625 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 626 627 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 628 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 629 SOC_ENUM("ADC Companding Mode", adc_companding), 630 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 631 632 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 633 12, 0, digital_sidetone_tlv), 634 635 /* DAC */ 636 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 637 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 638 SOC_ENUM("DAC Soft Mute Rate", soft_mute), 639 SOC_ENUM("DAC Mute Mode", mute_mode), 640 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 641 SOC_ENUM("DAC De-emphasis", dac_deemphasis), 642 SOC_ENUM("DAC Companding Mode", dac_companding), 643 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 644 645 /* Headphones */ 646 SOC_DOUBLE_R("Headphone Switch", 647 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 648 8, 1, 1), 649 SOC_DOUBLE_R("Headphone ZC Switch", 650 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 651 6, 1, 0), 652 SOC_DOUBLE_R_TLV("Headphone Volume", 653 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 654 0, 63, 0, out_tlv), 655 656 /* Line out */ 657 SOC_DOUBLE_R("Line Out Switch", 658 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 659 8, 1, 1), 660 SOC_DOUBLE_R("Line Out ZC Switch", 661 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 662 6, 1, 0), 663 SOC_DOUBLE_R_TLV("Line Out Volume", 664 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 665 0, 63, 0, out_tlv), 666 667 /* Speaker */ 668 SOC_DOUBLE_R("Speaker Switch", 669 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 670 SOC_DOUBLE_R("Speaker ZC Switch", 671 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 672 SOC_DOUBLE_R_TLV("Speaker Volume", 673 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 674 0, 63, 0, out_tlv), 675 }; 676 677 static const struct snd_kcontrol_new linput_mode_mux = 678 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 679 680 static const struct snd_kcontrol_new rinput_mode_mux = 681 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 682 683 static const struct snd_kcontrol_new linput_mux = 684 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 685 686 static const struct snd_kcontrol_new linput_inv_mux = 687 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 688 689 static const struct snd_kcontrol_new rinput_mux = 690 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 691 692 static const struct snd_kcontrol_new rinput_inv_mux = 693 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 694 695 static const struct snd_kcontrol_new lsidetone_mux = 696 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 697 698 static const struct snd_kcontrol_new rsidetone_mux = 699 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 700 701 static const struct snd_kcontrol_new left_output_mixer[] = { 702 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 703 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 704 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 705 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 706 }; 707 708 static const struct snd_kcontrol_new right_output_mixer[] = { 709 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 710 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 711 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 712 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 713 }; 714 715 static const struct snd_kcontrol_new left_speaker_mixer[] = { 716 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 717 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 718 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 719 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 720 0, 1, 0), 721 }; 722 723 static const struct snd_kcontrol_new right_speaker_mixer[] = { 724 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 725 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 726 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 727 1, 1, 0), 728 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 729 0, 1, 0), 730 }; 731 732 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 733 SND_SOC_DAPM_INPUT("IN1L"), 734 SND_SOC_DAPM_INPUT("IN1R"), 735 SND_SOC_DAPM_INPUT("IN2L"), 736 SND_SOC_DAPM_INPUT("IN2R"), 737 SND_SOC_DAPM_INPUT("IN3L"), 738 SND_SOC_DAPM_INPUT("IN3R"), 739 740 SND_SOC_DAPM_OUTPUT("HPOUTL"), 741 SND_SOC_DAPM_OUTPUT("HPOUTR"), 742 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 743 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 744 SND_SOC_DAPM_OUTPUT("LOP"), 745 SND_SOC_DAPM_OUTPUT("LON"), 746 SND_SOC_DAPM_OUTPUT("ROP"), 747 SND_SOC_DAPM_OUTPUT("RON"), 748 749 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), 750 751 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 752 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 753 &linput_inv_mux), 754 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 755 756 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 757 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 758 &rinput_inv_mux), 759 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 760 761 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 762 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 763 764 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), 765 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), 766 767 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 768 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 769 770 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), 771 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), 772 773 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 774 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 775 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 776 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 777 778 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 779 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 780 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 781 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 782 783 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 784 1, 0, NULL, 0, wm8903_output_event, 785 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 786 SND_SOC_DAPM_PRE_PMD), 787 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 788 0, 0, NULL, 0, wm8903_output_event, 789 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 790 SND_SOC_DAPM_PRE_PMD), 791 792 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, 793 NULL, 0, wm8903_output_event, 794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 795 SND_SOC_DAPM_PRE_PMD), 796 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, 797 NULL, 0, wm8903_output_event, 798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 799 SND_SOC_DAPM_PRE_PMD), 800 801 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 802 NULL, 0), 803 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 804 NULL, 0), 805 806 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 807 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 808 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 809 }; 810 811 static const struct snd_soc_dapm_route intercon[] = { 812 813 { "Left Input Mux", "IN1L", "IN1L" }, 814 { "Left Input Mux", "IN2L", "IN2L" }, 815 { "Left Input Mux", "IN3L", "IN3L" }, 816 817 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 818 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 819 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 820 821 { "Right Input Mux", "IN1R", "IN1R" }, 822 { "Right Input Mux", "IN2R", "IN2R" }, 823 { "Right Input Mux", "IN3R", "IN3R" }, 824 825 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 826 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 827 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 828 829 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 830 { "Left Input Mode Mux", "Differential Line", 831 "Left Input Mux" }, 832 { "Left Input Mode Mux", "Differential Line", 833 "Left Input Inverting Mux" }, 834 { "Left Input Mode Mux", "Differential Mic", 835 "Left Input Mux" }, 836 { "Left Input Mode Mux", "Differential Mic", 837 "Left Input Inverting Mux" }, 838 839 { "Right Input Mode Mux", "Single-Ended", 840 "Right Input Inverting Mux" }, 841 { "Right Input Mode Mux", "Differential Line", 842 "Right Input Mux" }, 843 { "Right Input Mode Mux", "Differential Line", 844 "Right Input Inverting Mux" }, 845 { "Right Input Mode Mux", "Differential Mic", 846 "Right Input Mux" }, 847 { "Right Input Mode Mux", "Differential Mic", 848 "Right Input Inverting Mux" }, 849 850 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 851 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 852 853 { "ADCL", NULL, "Left Input PGA" }, 854 { "ADCL", NULL, "CLK_DSP" }, 855 { "ADCR", NULL, "Right Input PGA" }, 856 { "ADCR", NULL, "CLK_DSP" }, 857 858 { "DACL Sidetone", "Left", "ADCL" }, 859 { "DACL Sidetone", "Right", "ADCR" }, 860 { "DACR Sidetone", "Left", "ADCL" }, 861 { "DACR Sidetone", "Right", "ADCR" }, 862 863 { "DACL", NULL, "DACL Sidetone" }, 864 { "DACL", NULL, "CLK_DSP" }, 865 { "DACR", NULL, "DACR Sidetone" }, 866 { "DACR", NULL, "CLK_DSP" }, 867 868 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 869 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 870 { "Left Output Mixer", "DACL Switch", "DACL" }, 871 { "Left Output Mixer", "DACR Switch", "DACR" }, 872 873 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 874 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 875 { "Right Output Mixer", "DACL Switch", "DACL" }, 876 { "Right Output Mixer", "DACR Switch", "DACR" }, 877 878 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 879 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 880 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 881 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 882 883 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 884 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 885 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 886 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 887 888 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 889 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 890 891 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 892 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 893 894 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 895 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 896 897 { "HPOUTL", NULL, "Left Headphone Output PGA" }, 898 { "HPOUTR", NULL, "Right Headphone Output PGA" }, 899 900 { "LINEOUTL", NULL, "Left Line Output PGA" }, 901 { "LINEOUTR", NULL, "Right Line Output PGA" }, 902 903 { "LOP", NULL, "Left Speaker PGA" }, 904 { "LON", NULL, "Left Speaker PGA" }, 905 906 { "ROP", NULL, "Right Speaker PGA" }, 907 { "RON", NULL, "Right Speaker PGA" }, 908 909 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 910 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 911 { "Left Line Output PGA", NULL, "Charge Pump" }, 912 { "Right Line Output PGA", NULL, "Charge Pump" }, 913 }; 914 915 static int wm8903_add_widgets(struct snd_soc_codec *codec) 916 { 917 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, 918 ARRAY_SIZE(wm8903_dapm_widgets)); 919 920 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 921 922 return 0; 923 } 924 925 static int wm8903_set_bias_level(struct snd_soc_codec *codec, 926 enum snd_soc_bias_level level) 927 { 928 struct i2c_client *i2c = codec->control_data; 929 u16 reg, reg2; 930 931 switch (level) { 932 case SND_SOC_BIAS_ON: 933 case SND_SOC_BIAS_PREPARE: 934 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 935 reg &= ~(WM8903_VMID_RES_MASK); 936 reg |= WM8903_VMID_RES_50K; 937 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 938 break; 939 940 case SND_SOC_BIAS_STANDBY: 941 if (codec->bias_level == SND_SOC_BIAS_OFF) { 942 snd_soc_write(codec, WM8903_CLOCK_RATES_2, 943 WM8903_CLK_SYS_ENA); 944 945 /* Change DC servo dither level in startup sequence */ 946 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); 947 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); 948 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); 949 950 wm8903_run_sequence(codec, 0); 951 wm8903_sync_reg_cache(codec, codec->reg_cache); 952 953 /* Enable low impedence charge pump output */ 954 reg = snd_soc_read(codec, 955 WM8903_CONTROL_INTERFACE_TEST_1); 956 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 957 reg | WM8903_TEST_KEY); 958 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); 959 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, 960 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); 961 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 962 reg); 963 964 /* By default no bypass paths are enabled so 965 * enable Class W support. 966 */ 967 dev_dbg(&i2c->dev, "Enabling Class W\n"); 968 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 969 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 970 } 971 972 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 973 reg &= ~(WM8903_VMID_RES_MASK); 974 reg |= WM8903_VMID_RES_250K; 975 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); 976 break; 977 978 case SND_SOC_BIAS_OFF: 979 wm8903_run_sequence(codec, 32); 980 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2); 981 reg &= ~WM8903_CLK_SYS_ENA; 982 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg); 983 break; 984 } 985 986 codec->bias_level = level; 987 988 return 0; 989 } 990 991 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 992 int clk_id, unsigned int freq, int dir) 993 { 994 struct snd_soc_codec *codec = codec_dai->codec; 995 struct wm8903_priv *wm8903 = codec->private_data; 996 997 wm8903->sysclk = freq; 998 999 return 0; 1000 } 1001 1002 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1003 unsigned int fmt) 1004 { 1005 struct snd_soc_codec *codec = codec_dai->codec; 1006 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1007 1008 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1009 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1010 1011 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1012 case SND_SOC_DAIFMT_CBS_CFS: 1013 break; 1014 case SND_SOC_DAIFMT_CBS_CFM: 1015 aif1 |= WM8903_LRCLK_DIR; 1016 break; 1017 case SND_SOC_DAIFMT_CBM_CFM: 1018 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1019 break; 1020 case SND_SOC_DAIFMT_CBM_CFS: 1021 aif1 |= WM8903_BCLK_DIR; 1022 break; 1023 default: 1024 return -EINVAL; 1025 } 1026 1027 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1028 case SND_SOC_DAIFMT_DSP_A: 1029 aif1 |= 0x3; 1030 break; 1031 case SND_SOC_DAIFMT_DSP_B: 1032 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1033 break; 1034 case SND_SOC_DAIFMT_I2S: 1035 aif1 |= 0x2; 1036 break; 1037 case SND_SOC_DAIFMT_RIGHT_J: 1038 aif1 |= 0x1; 1039 break; 1040 case SND_SOC_DAIFMT_LEFT_J: 1041 break; 1042 default: 1043 return -EINVAL; 1044 } 1045 1046 /* Clock inversion */ 1047 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1048 case SND_SOC_DAIFMT_DSP_A: 1049 case SND_SOC_DAIFMT_DSP_B: 1050 /* frame inversion not valid for DSP modes */ 1051 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1052 case SND_SOC_DAIFMT_NB_NF: 1053 break; 1054 case SND_SOC_DAIFMT_IB_NF: 1055 aif1 |= WM8903_AIF_BCLK_INV; 1056 break; 1057 default: 1058 return -EINVAL; 1059 } 1060 break; 1061 case SND_SOC_DAIFMT_I2S: 1062 case SND_SOC_DAIFMT_RIGHT_J: 1063 case SND_SOC_DAIFMT_LEFT_J: 1064 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1065 case SND_SOC_DAIFMT_NB_NF: 1066 break; 1067 case SND_SOC_DAIFMT_IB_IF: 1068 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1069 break; 1070 case SND_SOC_DAIFMT_IB_NF: 1071 aif1 |= WM8903_AIF_BCLK_INV; 1072 break; 1073 case SND_SOC_DAIFMT_NB_IF: 1074 aif1 |= WM8903_AIF_LRCLK_INV; 1075 break; 1076 default: 1077 return -EINVAL; 1078 } 1079 break; 1080 default: 1081 return -EINVAL; 1082 } 1083 1084 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1085 1086 return 0; 1087 } 1088 1089 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1090 { 1091 struct snd_soc_codec *codec = codec_dai->codec; 1092 u16 reg; 1093 1094 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1095 1096 if (mute) 1097 reg |= WM8903_DAC_MUTE; 1098 else 1099 reg &= ~WM8903_DAC_MUTE; 1100 1101 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1102 1103 return 0; 1104 } 1105 1106 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1107 * for optimal performance so we list the lower rates first and match 1108 * on the last match we find. */ 1109 static struct { 1110 int div; 1111 int rate; 1112 int mode; 1113 int mclk_div; 1114 } clk_sys_ratios[] = { 1115 { 64, 0x0, 0x0, 1 }, 1116 { 68, 0x0, 0x1, 1 }, 1117 { 125, 0x0, 0x2, 1 }, 1118 { 128, 0x1, 0x0, 1 }, 1119 { 136, 0x1, 0x1, 1 }, 1120 { 192, 0x2, 0x0, 1 }, 1121 { 204, 0x2, 0x1, 1 }, 1122 1123 { 64, 0x0, 0x0, 2 }, 1124 { 68, 0x0, 0x1, 2 }, 1125 { 125, 0x0, 0x2, 2 }, 1126 { 128, 0x1, 0x0, 2 }, 1127 { 136, 0x1, 0x1, 2 }, 1128 { 192, 0x2, 0x0, 2 }, 1129 { 204, 0x2, 0x1, 2 }, 1130 1131 { 250, 0x2, 0x2, 1 }, 1132 { 256, 0x3, 0x0, 1 }, 1133 { 272, 0x3, 0x1, 1 }, 1134 { 384, 0x4, 0x0, 1 }, 1135 { 408, 0x4, 0x1, 1 }, 1136 { 375, 0x4, 0x2, 1 }, 1137 { 512, 0x5, 0x0, 1 }, 1138 { 544, 0x5, 0x1, 1 }, 1139 { 500, 0x5, 0x2, 1 }, 1140 { 768, 0x6, 0x0, 1 }, 1141 { 816, 0x6, 0x1, 1 }, 1142 { 750, 0x6, 0x2, 1 }, 1143 { 1024, 0x7, 0x0, 1 }, 1144 { 1088, 0x7, 0x1, 1 }, 1145 { 1000, 0x7, 0x2, 1 }, 1146 { 1408, 0x8, 0x0, 1 }, 1147 { 1496, 0x8, 0x1, 1 }, 1148 { 1536, 0x9, 0x0, 1 }, 1149 { 1632, 0x9, 0x1, 1 }, 1150 { 1500, 0x9, 0x2, 1 }, 1151 1152 { 250, 0x2, 0x2, 2 }, 1153 { 256, 0x3, 0x0, 2 }, 1154 { 272, 0x3, 0x1, 2 }, 1155 { 384, 0x4, 0x0, 2 }, 1156 { 408, 0x4, 0x1, 2 }, 1157 { 375, 0x4, 0x2, 2 }, 1158 { 512, 0x5, 0x0, 2 }, 1159 { 544, 0x5, 0x1, 2 }, 1160 { 500, 0x5, 0x2, 2 }, 1161 { 768, 0x6, 0x0, 2 }, 1162 { 816, 0x6, 0x1, 2 }, 1163 { 750, 0x6, 0x2, 2 }, 1164 { 1024, 0x7, 0x0, 2 }, 1165 { 1088, 0x7, 0x1, 2 }, 1166 { 1000, 0x7, 0x2, 2 }, 1167 { 1408, 0x8, 0x0, 2 }, 1168 { 1496, 0x8, 0x1, 2 }, 1169 { 1536, 0x9, 0x0, 2 }, 1170 { 1632, 0x9, 0x1, 2 }, 1171 { 1500, 0x9, 0x2, 2 }, 1172 }; 1173 1174 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1175 static struct { 1176 int ratio; 1177 int div; 1178 } bclk_divs[] = { 1179 { 10, 0 }, 1180 { 20, 2 }, 1181 { 30, 3 }, 1182 { 40, 4 }, 1183 { 50, 5 }, 1184 { 60, 7 }, 1185 { 80, 8 }, 1186 { 100, 9 }, 1187 { 120, 11 }, 1188 { 160, 12 }, 1189 { 200, 13 }, 1190 { 220, 14 }, 1191 { 240, 15 }, 1192 { 300, 17 }, 1193 { 320, 18 }, 1194 { 440, 19 }, 1195 { 480, 20 }, 1196 }; 1197 1198 /* Sample rates for DSP */ 1199 static struct { 1200 int rate; 1201 int value; 1202 } sample_rates[] = { 1203 { 8000, 0 }, 1204 { 11025, 1 }, 1205 { 12000, 2 }, 1206 { 16000, 3 }, 1207 { 22050, 4 }, 1208 { 24000, 5 }, 1209 { 32000, 6 }, 1210 { 44100, 7 }, 1211 { 48000, 8 }, 1212 { 88200, 9 }, 1213 { 96000, 10 }, 1214 { 0, 0 }, 1215 }; 1216 1217 static int wm8903_startup(struct snd_pcm_substream *substream, 1218 struct snd_soc_dai *dai) 1219 { 1220 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1221 struct snd_soc_device *socdev = rtd->socdev; 1222 struct snd_soc_codec *codec = socdev->card->codec; 1223 struct wm8903_priv *wm8903 = codec->private_data; 1224 struct i2c_client *i2c = codec->control_data; 1225 struct snd_pcm_runtime *master_runtime; 1226 1227 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1228 wm8903->playback_active++; 1229 else 1230 wm8903->capture_active++; 1231 1232 /* The DAI has shared clocks so if we already have a playback or 1233 * capture going then constrain this substream to match it. 1234 */ 1235 if (wm8903->master_substream) { 1236 master_runtime = wm8903->master_substream->runtime; 1237 1238 dev_dbg(&i2c->dev, "Constraining to %d bits\n", 1239 master_runtime->sample_bits); 1240 1241 snd_pcm_hw_constraint_minmax(substream->runtime, 1242 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1243 master_runtime->sample_bits, 1244 master_runtime->sample_bits); 1245 1246 wm8903->slave_substream = substream; 1247 } else 1248 wm8903->master_substream = substream; 1249 1250 return 0; 1251 } 1252 1253 static void wm8903_shutdown(struct snd_pcm_substream *substream, 1254 struct snd_soc_dai *dai) 1255 { 1256 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1257 struct snd_soc_device *socdev = rtd->socdev; 1258 struct snd_soc_codec *codec = socdev->card->codec; 1259 struct wm8903_priv *wm8903 = codec->private_data; 1260 1261 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1262 wm8903->playback_active--; 1263 else 1264 wm8903->capture_active--; 1265 1266 if (wm8903->master_substream == substream) 1267 wm8903->master_substream = wm8903->slave_substream; 1268 1269 wm8903->slave_substream = NULL; 1270 } 1271 1272 static int wm8903_hw_params(struct snd_pcm_substream *substream, 1273 struct snd_pcm_hw_params *params, 1274 struct snd_soc_dai *dai) 1275 { 1276 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1277 struct snd_soc_device *socdev = rtd->socdev; 1278 struct snd_soc_codec *codec = socdev->card->codec; 1279 struct wm8903_priv *wm8903 = codec->private_data; 1280 struct i2c_client *i2c = codec->control_data; 1281 int fs = params_rate(params); 1282 int bclk; 1283 int bclk_div; 1284 int i; 1285 int dsp_config; 1286 int clk_config; 1287 int best_val; 1288 int cur_val; 1289 int clk_sys; 1290 1291 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1292 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1293 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1294 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1295 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1296 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1297 1298 if (substream == wm8903->slave_substream) { 1299 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n"); 1300 return 0; 1301 } 1302 1303 /* Enable sloping stopband filter for low sample rates */ 1304 if (fs <= 24000) 1305 dac_digital1 |= WM8903_DAC_SB_FILT; 1306 else 1307 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1308 1309 /* Configure sample rate logic for DSP - choose nearest rate */ 1310 dsp_config = 0; 1311 best_val = abs(sample_rates[dsp_config].rate - fs); 1312 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1313 cur_val = abs(sample_rates[i].rate - fs); 1314 if (cur_val <= best_val) { 1315 dsp_config = i; 1316 best_val = cur_val; 1317 } 1318 } 1319 1320 /* Constraints should stop us hitting this but let's make sure */ 1321 if (wm8903->capture_active) 1322 switch (sample_rates[dsp_config].rate) { 1323 case 88200: 1324 case 96000: 1325 dev_err(&i2c->dev, "%dHz unsupported by ADC\n", 1326 fs); 1327 return -EINVAL; 1328 1329 default: 1330 break; 1331 } 1332 1333 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1334 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1335 clock1 |= sample_rates[dsp_config].value; 1336 1337 aif1 &= ~WM8903_AIF_WL_MASK; 1338 bclk = 2 * fs; 1339 switch (params_format(params)) { 1340 case SNDRV_PCM_FORMAT_S16_LE: 1341 bclk *= 16; 1342 break; 1343 case SNDRV_PCM_FORMAT_S20_3LE: 1344 bclk *= 20; 1345 aif1 |= 0x4; 1346 break; 1347 case SNDRV_PCM_FORMAT_S24_LE: 1348 bclk *= 24; 1349 aif1 |= 0x8; 1350 break; 1351 case SNDRV_PCM_FORMAT_S32_LE: 1352 bclk *= 32; 1353 aif1 |= 0xc; 1354 break; 1355 default: 1356 return -EINVAL; 1357 } 1358 1359 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1360 wm8903->sysclk, fs); 1361 1362 /* We may not have an MCLK which allows us to generate exactly 1363 * the clock we want, particularly with USB derived inputs, so 1364 * approximate. 1365 */ 1366 clk_config = 0; 1367 best_val = abs((wm8903->sysclk / 1368 (clk_sys_ratios[0].mclk_div * 1369 clk_sys_ratios[0].div)) - fs); 1370 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1371 cur_val = abs((wm8903->sysclk / 1372 (clk_sys_ratios[i].mclk_div * 1373 clk_sys_ratios[i].div)) - fs); 1374 1375 if (cur_val <= best_val) { 1376 clk_config = i; 1377 best_val = cur_val; 1378 } 1379 } 1380 1381 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1382 clock0 |= WM8903_MCLKDIV2; 1383 clk_sys = wm8903->sysclk / 2; 1384 } else { 1385 clock0 &= ~WM8903_MCLKDIV2; 1386 clk_sys = wm8903->sysclk; 1387 } 1388 1389 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1390 WM8903_CLK_SYS_MODE_MASK); 1391 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1392 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1393 1394 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1395 clk_sys_ratios[clk_config].rate, 1396 clk_sys_ratios[clk_config].mode, 1397 clk_sys_ratios[clk_config].div); 1398 1399 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1400 1401 /* We may not get quite the right frequency if using 1402 * approximate clocks so look for the closest match that is 1403 * higher than the target (we need to ensure that there enough 1404 * BCLKs to clock out the samples). 1405 */ 1406 bclk_div = 0; 1407 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1408 i = 1; 1409 while (i < ARRAY_SIZE(bclk_divs)) { 1410 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1411 if (cur_val < 0) /* BCLK table is sorted */ 1412 break; 1413 bclk_div = i; 1414 best_val = cur_val; 1415 i++; 1416 } 1417 1418 aif2 &= ~WM8903_BCLK_DIV_MASK; 1419 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1420 1421 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1422 bclk_divs[bclk_div].ratio / 10, bclk, 1423 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1424 1425 aif2 |= bclk_divs[bclk_div].div; 1426 aif3 |= bclk / fs; 1427 1428 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1429 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1430 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1431 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1432 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1433 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1434 1435 return 0; 1436 } 1437 1438 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1439 SNDRV_PCM_RATE_11025 | \ 1440 SNDRV_PCM_RATE_16000 | \ 1441 SNDRV_PCM_RATE_22050 | \ 1442 SNDRV_PCM_RATE_32000 | \ 1443 SNDRV_PCM_RATE_44100 | \ 1444 SNDRV_PCM_RATE_48000 | \ 1445 SNDRV_PCM_RATE_88200 | \ 1446 SNDRV_PCM_RATE_96000) 1447 1448 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1449 SNDRV_PCM_RATE_11025 | \ 1450 SNDRV_PCM_RATE_16000 | \ 1451 SNDRV_PCM_RATE_22050 | \ 1452 SNDRV_PCM_RATE_32000 | \ 1453 SNDRV_PCM_RATE_44100 | \ 1454 SNDRV_PCM_RATE_48000) 1455 1456 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1457 SNDRV_PCM_FMTBIT_S20_3LE |\ 1458 SNDRV_PCM_FMTBIT_S24_LE) 1459 1460 static struct snd_soc_dai_ops wm8903_dai_ops = { 1461 .startup = wm8903_startup, 1462 .shutdown = wm8903_shutdown, 1463 .hw_params = wm8903_hw_params, 1464 .digital_mute = wm8903_digital_mute, 1465 .set_fmt = wm8903_set_dai_fmt, 1466 .set_sysclk = wm8903_set_dai_sysclk, 1467 }; 1468 1469 struct snd_soc_dai wm8903_dai = { 1470 .name = "WM8903", 1471 .playback = { 1472 .stream_name = "Playback", 1473 .channels_min = 2, 1474 .channels_max = 2, 1475 .rates = WM8903_PLAYBACK_RATES, 1476 .formats = WM8903_FORMATS, 1477 }, 1478 .capture = { 1479 .stream_name = "Capture", 1480 .channels_min = 2, 1481 .channels_max = 2, 1482 .rates = WM8903_CAPTURE_RATES, 1483 .formats = WM8903_FORMATS, 1484 }, 1485 .ops = &wm8903_dai_ops, 1486 .symmetric_rates = 1, 1487 }; 1488 EXPORT_SYMBOL_GPL(wm8903_dai); 1489 1490 static int wm8903_suspend(struct platform_device *pdev, pm_message_t state) 1491 { 1492 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1493 struct snd_soc_codec *codec = socdev->card->codec; 1494 1495 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1496 1497 return 0; 1498 } 1499 1500 static int wm8903_resume(struct platform_device *pdev) 1501 { 1502 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1503 struct snd_soc_codec *codec = socdev->card->codec; 1504 struct i2c_client *i2c = codec->control_data; 1505 int i; 1506 u16 *reg_cache = codec->reg_cache; 1507 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults), 1508 GFP_KERNEL); 1509 1510 /* Bring the codec back up to standby first to minimise pop/clicks */ 1511 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1512 wm8903_set_bias_level(codec, codec->suspend_bias_level); 1513 1514 /* Sync back everything else */ 1515 if (tmp_cache) { 1516 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1517 if (tmp_cache[i] != reg_cache[i]) 1518 snd_soc_write(codec, i, tmp_cache[i]); 1519 } else { 1520 dev_err(&i2c->dev, "Failed to allocate temporary cache\n"); 1521 } 1522 1523 return 0; 1524 } 1525 1526 static struct snd_soc_codec *wm8903_codec; 1527 1528 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, 1529 const struct i2c_device_id *id) 1530 { 1531 struct wm8903_priv *wm8903; 1532 struct snd_soc_codec *codec; 1533 int ret; 1534 u16 val; 1535 1536 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); 1537 if (wm8903 == NULL) 1538 return -ENOMEM; 1539 1540 codec = &wm8903->codec; 1541 1542 mutex_init(&codec->mutex); 1543 INIT_LIST_HEAD(&codec->dapm_widgets); 1544 INIT_LIST_HEAD(&codec->dapm_paths); 1545 1546 codec->dev = &i2c->dev; 1547 codec->name = "WM8903"; 1548 codec->owner = THIS_MODULE; 1549 codec->bias_level = SND_SOC_BIAS_OFF; 1550 codec->set_bias_level = wm8903_set_bias_level; 1551 codec->dai = &wm8903_dai; 1552 codec->num_dai = 1; 1553 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache); 1554 codec->reg_cache = &wm8903->reg_cache[0]; 1555 codec->private_data = wm8903; 1556 codec->volatile_register = wm8903_volatile_register; 1557 1558 i2c_set_clientdata(i2c, codec); 1559 codec->control_data = i2c; 1560 1561 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1562 if (ret != 0) { 1563 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret); 1564 goto err; 1565 } 1566 1567 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); 1568 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1569 dev_err(&i2c->dev, 1570 "Device with ID register %x is not a WM8903\n", val); 1571 return -ENODEV; 1572 } 1573 1574 val = snd_soc_read(codec, WM8903_REVISION_NUMBER); 1575 dev_info(&i2c->dev, "WM8903 revision %d\n", 1576 val & WM8903_CHIP_REV_MASK); 1577 1578 wm8903_reset(codec); 1579 1580 /* power on device */ 1581 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1582 1583 /* Latch volume update bits */ 1584 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1585 val |= WM8903_ADCVU; 1586 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1587 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1588 1589 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1590 val |= WM8903_DACVU; 1591 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1592 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1593 1594 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1595 val |= WM8903_HPOUTVU; 1596 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1597 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1598 1599 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1600 val |= WM8903_LINEOUTVU; 1601 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1602 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1603 1604 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1605 val |= WM8903_SPKVU; 1606 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1607 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1608 1609 /* Enable DAC soft mute by default */ 1610 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1611 val |= WM8903_DAC_MUTEMODE; 1612 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val); 1613 1614 wm8903_dai.dev = &i2c->dev; 1615 wm8903_codec = codec; 1616 1617 ret = snd_soc_register_codec(codec); 1618 if (ret != 0) { 1619 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1620 goto err; 1621 } 1622 1623 ret = snd_soc_register_dai(&wm8903_dai); 1624 if (ret != 0) { 1625 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret); 1626 goto err_codec; 1627 } 1628 1629 return ret; 1630 1631 err_codec: 1632 snd_soc_unregister_codec(codec); 1633 err: 1634 wm8903_codec = NULL; 1635 kfree(wm8903); 1636 return ret; 1637 } 1638 1639 static __devexit int wm8903_i2c_remove(struct i2c_client *client) 1640 { 1641 struct snd_soc_codec *codec = i2c_get_clientdata(client); 1642 1643 snd_soc_unregister_dai(&wm8903_dai); 1644 snd_soc_unregister_codec(codec); 1645 1646 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1647 1648 kfree(codec->private_data); 1649 1650 wm8903_codec = NULL; 1651 wm8903_dai.dev = NULL; 1652 1653 return 0; 1654 } 1655 1656 /* i2c codec control layer */ 1657 static const struct i2c_device_id wm8903_i2c_id[] = { 1658 { "wm8903", 0 }, 1659 { } 1660 }; 1661 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 1662 1663 static struct i2c_driver wm8903_i2c_driver = { 1664 .driver = { 1665 .name = "WM8903", 1666 .owner = THIS_MODULE, 1667 }, 1668 .probe = wm8903_i2c_probe, 1669 .remove = __devexit_p(wm8903_i2c_remove), 1670 .id_table = wm8903_i2c_id, 1671 }; 1672 1673 static int wm8903_probe(struct platform_device *pdev) 1674 { 1675 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1676 int ret = 0; 1677 1678 if (!wm8903_codec) { 1679 dev_err(&pdev->dev, "I2C device not yet probed\n"); 1680 goto err; 1681 } 1682 1683 socdev->card->codec = wm8903_codec; 1684 1685 /* register pcms */ 1686 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1687 if (ret < 0) { 1688 dev_err(&pdev->dev, "failed to create pcms\n"); 1689 goto err; 1690 } 1691 1692 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls, 1693 ARRAY_SIZE(wm8903_snd_controls)); 1694 wm8903_add_widgets(socdev->card->codec); 1695 1696 return ret; 1697 1698 err: 1699 return ret; 1700 } 1701 1702 /* power down chip */ 1703 static int wm8903_remove(struct platform_device *pdev) 1704 { 1705 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1706 struct snd_soc_codec *codec = socdev->card->codec; 1707 1708 if (codec->control_data) 1709 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 1710 1711 snd_soc_free_pcms(socdev); 1712 snd_soc_dapm_free(socdev); 1713 1714 return 0; 1715 } 1716 1717 struct snd_soc_codec_device soc_codec_dev_wm8903 = { 1718 .probe = wm8903_probe, 1719 .remove = wm8903_remove, 1720 .suspend = wm8903_suspend, 1721 .resume = wm8903_resume, 1722 }; 1723 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903); 1724 1725 static int __init wm8903_modinit(void) 1726 { 1727 return i2c_add_driver(&wm8903_i2c_driver); 1728 } 1729 module_init(wm8903_modinit); 1730 1731 static void __exit wm8903_exit(void) 1732 { 1733 i2c_del_driver(&wm8903_i2c_driver); 1734 } 1735 module_exit(wm8903_exit); 1736 1737 MODULE_DESCRIPTION("ASoC WM8903 driver"); 1738 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 1739 MODULE_LICENSE("GPL"); 1740