1 /* 2 * wm8900.c -- WM8900 ALSA Soc Audio driver 3 * 4 * Copyright 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * TODO: 13 * - Tristating. 14 * - TDM. 15 * - Jack detect. 16 * - FLL source configuration, currently only MCLK is supported. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/pm.h> 25 #include <linux/i2c.h> 26 #include <linux/platform_device.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 35 #include "wm8900.h" 36 37 /* WM8900 register space */ 38 #define WM8900_REG_RESET 0x0 39 #define WM8900_REG_ID 0x0 40 #define WM8900_REG_POWER1 0x1 41 #define WM8900_REG_POWER2 0x2 42 #define WM8900_REG_POWER3 0x3 43 #define WM8900_REG_AUDIO1 0x4 44 #define WM8900_REG_AUDIO2 0x5 45 #define WM8900_REG_CLOCKING1 0x6 46 #define WM8900_REG_CLOCKING2 0x7 47 #define WM8900_REG_AUDIO3 0x8 48 #define WM8900_REG_AUDIO4 0x9 49 #define WM8900_REG_DACCTRL 0xa 50 #define WM8900_REG_LDAC_DV 0xb 51 #define WM8900_REG_RDAC_DV 0xc 52 #define WM8900_REG_SIDETONE 0xd 53 #define WM8900_REG_ADCCTRL 0xe 54 #define WM8900_REG_LADC_DV 0xf 55 #define WM8900_REG_RADC_DV 0x10 56 #define WM8900_REG_GPIO 0x12 57 #define WM8900_REG_INCTL 0x15 58 #define WM8900_REG_LINVOL 0x16 59 #define WM8900_REG_RINVOL 0x17 60 #define WM8900_REG_INBOOSTMIX1 0x18 61 #define WM8900_REG_INBOOSTMIX2 0x19 62 #define WM8900_REG_ADCPATH 0x1a 63 #define WM8900_REG_AUXBOOST 0x1b 64 #define WM8900_REG_ADDCTL 0x1e 65 #define WM8900_REG_FLLCTL1 0x24 66 #define WM8900_REG_FLLCTL2 0x25 67 #define WM8900_REG_FLLCTL3 0x26 68 #define WM8900_REG_FLLCTL4 0x27 69 #define WM8900_REG_FLLCTL5 0x28 70 #define WM8900_REG_FLLCTL6 0x29 71 #define WM8900_REG_LOUTMIXCTL1 0x2c 72 #define WM8900_REG_ROUTMIXCTL1 0x2d 73 #define WM8900_REG_BYPASS1 0x2e 74 #define WM8900_REG_BYPASS2 0x2f 75 #define WM8900_REG_AUXOUT_CTL 0x30 76 #define WM8900_REG_LOUT1CTL 0x33 77 #define WM8900_REG_ROUT1CTL 0x34 78 #define WM8900_REG_LOUT2CTL 0x35 79 #define WM8900_REG_ROUT2CTL 0x36 80 #define WM8900_REG_HPCTL1 0x3a 81 #define WM8900_REG_OUTBIASCTL 0x73 82 83 #define WM8900_MAXREG 0x80 84 85 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80 86 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40 87 #define WM8900_REG_ADDCTL_VMID_DIS 0x20 88 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10 89 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04 90 #define WM8900_REG_ADDCTL_TEMP_SD 0x02 91 92 #define WM8900_REG_GPIO_TEMP_ENA 0x2 93 94 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100 95 #define WM8900_REG_POWER1_BIAS_ENA 0x0008 96 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004 97 #define WM8900_REG_POWER1_FLL_ENA 0x0040 98 99 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000 100 #define WM8900_REG_POWER2_ADCL_ENA 0x0002 101 #define WM8900_REG_POWER2_ADCR_ENA 0x0001 102 103 #define WM8900_REG_POWER3_DACL_ENA 0x0002 104 #define WM8900_REG_POWER3_DACR_ENA 0x0001 105 106 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018 107 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080 108 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100 109 110 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1 111 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100 112 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e) 113 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000) 114 115 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0 116 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c 117 118 #define WM8900_REG_DACCTRL_MUTE 0x004 119 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400 120 121 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800 122 123 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800 124 125 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100 126 127 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100 128 129 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80 130 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40 131 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20 132 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10 133 #define WM8900_REG_HPCTL1_HP_SHORT 0x08 134 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04 135 136 #define WM8900_LRC_MASK 0xfc00 137 138 struct snd_soc_codec_device soc_codec_dev_wm8900; 139 140 struct wm8900_priv { 141 u32 fll_in; /* FLL input frequency */ 142 u32 fll_out; /* FLL output frequency */ 143 }; 144 145 /* 146 * wm8900 register cache. We can't read the entire register space and we 147 * have slow control buses so we cache the registers. 148 */ 149 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = { 150 0x8900, 0x0000, 151 0xc000, 0x0000, 152 0x4050, 0x4000, 153 0x0008, 0x0000, 154 0x0040, 0x0040, 155 0x1004, 0x00c0, 156 0x00c0, 0x0000, 157 0x0100, 0x00c0, 158 0x00c0, 0x0000, 159 0xb001, 0x0000, 160 0x0000, 0x0044, 161 0x004c, 0x004c, 162 0x0044, 0x0044, 163 0x0000, 0x0044, 164 0x0000, 0x0000, 165 0x0002, 0x0000, 166 0x0000, 0x0000, 167 0x0000, 0x0000, 168 0x0008, 0x0000, 169 0x0000, 0x0008, 170 0x0097, 0x0100, 171 0x0000, 0x0000, 172 0x0050, 0x0050, 173 0x0055, 0x0055, 174 0x0055, 0x0000, 175 0x0000, 0x0079, 176 0x0079, 0x0079, 177 0x0079, 0x0000, 178 /* Remaining registers all zero */ 179 }; 180 181 /* 182 * read wm8900 register cache 183 */ 184 static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec, 185 unsigned int reg) 186 { 187 u16 *cache = codec->reg_cache; 188 189 BUG_ON(reg >= WM8900_MAXREG); 190 191 if (reg == WM8900_REG_ID) 192 return 0; 193 194 return cache[reg]; 195 } 196 197 /* 198 * write wm8900 register cache 199 */ 200 static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec, 201 u16 reg, unsigned int value) 202 { 203 u16 *cache = codec->reg_cache; 204 205 BUG_ON(reg >= WM8900_MAXREG); 206 207 cache[reg] = value; 208 } 209 210 /* 211 * write to the WM8900 register space 212 */ 213 static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg, 214 unsigned int value) 215 { 216 u8 data[3]; 217 218 if (value == wm8900_read_reg_cache(codec, reg)) 219 return 0; 220 221 /* data is 222 * D15..D9 WM8900 register offset 223 * D8...D0 register data 224 */ 225 data[0] = reg; 226 data[1] = value >> 8; 227 data[2] = value & 0x00ff; 228 229 wm8900_write_reg_cache(codec, reg, value); 230 if (codec->hw_write(codec->control_data, data, 3) == 3) 231 return 0; 232 else 233 return -EIO; 234 } 235 236 /* 237 * Read from the wm8900. 238 */ 239 static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg) 240 { 241 struct i2c_msg xfer[2]; 242 u16 data; 243 int ret; 244 struct i2c_client *client = codec->control_data; 245 246 BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1); 247 248 /* Write register */ 249 xfer[0].addr = client->addr; 250 xfer[0].flags = 0; 251 xfer[0].len = 1; 252 xfer[0].buf = ® 253 254 /* Read data */ 255 xfer[1].addr = client->addr; 256 xfer[1].flags = I2C_M_RD; 257 xfer[1].len = 2; 258 xfer[1].buf = (u8 *)&data; 259 260 ret = i2c_transfer(client->adapter, xfer, 2); 261 if (ret != 2) { 262 printk(KERN_CRIT "i2c_transfer returned %d\n", ret); 263 return 0; 264 } 265 266 return (data >> 8) | ((data & 0xff) << 8); 267 } 268 269 /* 270 * Read from the WM8900 register space. Most registers can't be read 271 * and are therefore supplied from cache. 272 */ 273 static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg) 274 { 275 switch (reg) { 276 case WM8900_REG_ID: 277 return wm8900_chip_read(codec, reg); 278 default: 279 return wm8900_read_reg_cache(codec, reg); 280 } 281 } 282 283 static void wm8900_reset(struct snd_soc_codec *codec) 284 { 285 wm8900_write(codec, WM8900_REG_RESET, 0); 286 287 memcpy(codec->reg_cache, wm8900_reg_defaults, 288 sizeof(codec->reg_cache)); 289 } 290 291 static int wm8900_hp_event(struct snd_soc_dapm_widget *w, 292 struct snd_kcontrol *kcontrol, int event) 293 { 294 struct snd_soc_codec *codec = w->codec; 295 u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1); 296 297 switch (event) { 298 case SND_SOC_DAPM_PRE_PMU: 299 /* Clamp headphone outputs */ 300 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | 301 WM8900_REG_HPCTL1_HP_CLAMP_OP; 302 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 303 break; 304 305 case SND_SOC_DAPM_POST_PMU: 306 /* Enable the input stage */ 307 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP; 308 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | 309 WM8900_REG_HPCTL1_HP_SHORT2 | 310 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 311 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 312 313 msleep(400); 314 315 /* Enable the output stage */ 316 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; 317 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 318 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 319 320 /* Remove the shorts */ 321 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; 322 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 323 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; 324 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 325 break; 326 327 case SND_SOC_DAPM_PRE_PMD: 328 /* Short the output */ 329 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; 330 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 331 332 /* Disable the output stage */ 333 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 334 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 335 336 /* Clamp the outputs and power down input */ 337 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | 338 WM8900_REG_HPCTL1_HP_CLAMP_OP; 339 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 340 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 341 break; 342 343 case SND_SOC_DAPM_POST_PMD: 344 /* Disable everything */ 345 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 346 break; 347 348 default: 349 BUG(); 350 } 351 352 return 0; 353 } 354 355 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0); 356 357 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0); 358 359 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0); 360 361 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0); 362 363 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 364 365 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); 366 367 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0); 368 369 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); 370 371 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" }; 372 373 static const struct soc_enum mic_bias_level = 374 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt); 375 376 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" }; 377 378 static const struct soc_enum dac_mute_rate = 379 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt); 380 381 static const char *dac_deemphasis_txt[] = { 382 "Disabled", "32kHz", "44.1kHz", "48kHz" 383 }; 384 385 static const struct soc_enum dac_deemphasis = 386 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt); 387 388 static const char *adc_hpf_cut_txt[] = { 389 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3" 390 }; 391 392 static const struct soc_enum adc_hpf_cut = 393 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt); 394 395 static const char *lr_txt[] = { 396 "Left", "Right" 397 }; 398 399 static const struct soc_enum aifl_src = 400 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt); 401 402 static const struct soc_enum aifr_src = 403 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt); 404 405 static const struct soc_enum dacl_src = 406 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt); 407 408 static const struct soc_enum dacr_src = 409 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt); 410 411 static const char *sidetone_txt[] = { 412 "Disabled", "Left ADC", "Right ADC" 413 }; 414 415 static const struct soc_enum dacl_sidetone = 416 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt); 417 418 static const struct soc_enum dacr_sidetone = 419 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt); 420 421 static const struct snd_kcontrol_new wm8900_snd_controls[] = { 422 SOC_ENUM("Mic Bias Level", mic_bias_level), 423 424 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0, 425 in_pga_tlv), 426 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1), 427 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0), 428 429 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0, 430 in_pga_tlv), 431 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1), 432 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0), 433 434 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1), 435 SOC_ENUM("DAC Mute Rate", dac_mute_rate), 436 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0), 437 SOC_ENUM("DAC Deemphasis", dac_deemphasis), 438 SOC_SINGLE("DAC Sloping Stopband Filter Switch", WM8900_REG_DACCTRL, 8, 1, 0), 439 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL, 440 12, 1, 0), 441 442 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0), 443 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut), 444 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0), 445 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0, 446 adc_svol_tlv), 447 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0, 448 adc_svol_tlv), 449 SOC_ENUM("Left Digital Audio Source", aifl_src), 450 SOC_ENUM("Right Digital Audio Source", aifr_src), 451 452 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0, 453 dac_boost_tlv), 454 SOC_ENUM("Left DAC Source", dacl_src), 455 SOC_ENUM("Right DAC Source", dacr_src), 456 SOC_ENUM("Left DAC Sidetone", dacl_sidetone), 457 SOC_ENUM("Right DAC Sidetone", dacr_sidetone), 458 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0), 459 460 SOC_DOUBLE_R_TLV("Digital Playback Volume", 461 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV, 462 1, 96, 0, dac_tlv), 463 SOC_DOUBLE_R_TLV("Digital Capture Volume", 464 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv), 465 466 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0, 467 out_mix_tlv), 468 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0, 469 out_mix_tlv), 470 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0, 471 out_mix_tlv), 472 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0, 473 out_mix_tlv), 474 475 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0, 476 out_mix_tlv), 477 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0, 478 out_mix_tlv), 479 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0, 480 out_mix_tlv), 481 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0, 482 out_mix_tlv), 483 484 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0, 485 in_boost_tlv), 486 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0, 487 in_boost_tlv), 488 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0, 489 in_boost_tlv), 490 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0, 491 in_boost_tlv), 492 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0, 493 in_boost_tlv), 494 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0, 495 in_boost_tlv), 496 497 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 498 0, 63, 0, out_pga_tlv), 499 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 500 6, 1, 1), 501 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, 502 7, 1, 0), 503 504 SOC_DOUBLE_R_TLV("LINEOUT2 Volume", 505 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 506 0, 63, 0, out_pga_tlv), 507 SOC_DOUBLE_R("LINEOUT2 Switch", 508 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1), 509 SOC_DOUBLE_R("LINEOUT2 ZC Switch", 510 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0), 511 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1, 512 0, 1, 1), 513 514 }; 515 516 /* add non dapm controls */ 517 static int wm8900_add_controls(struct snd_soc_codec *codec) 518 { 519 int err, i; 520 521 for (i = 0; i < ARRAY_SIZE(wm8900_snd_controls); i++) { 522 err = snd_ctl_add(codec->card, 523 snd_soc_cnew(&wm8900_snd_controls[i], 524 codec, NULL)); 525 if (err < 0) 526 return err; 527 } 528 529 return 0; 530 } 531 532 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control = 533 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0); 534 535 static const struct snd_kcontrol_new wm8900_dapm_routput2_control = 536 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0); 537 538 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = { 539 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0), 540 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0), 541 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0), 542 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0), 543 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0), 544 }; 545 546 static const struct snd_kcontrol_new wm8900_routmix_controls[] = { 547 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0), 548 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0), 549 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0), 550 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0), 551 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0), 552 }; 553 554 static const struct snd_kcontrol_new wm8900_linmix_controls[] = { 555 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1), 556 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1), 557 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1), 558 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0), 559 }; 560 561 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = { 562 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1), 563 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1), 564 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1), 565 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0), 566 }; 567 568 static const struct snd_kcontrol_new wm8900_linpga_controls[] = { 569 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0), 570 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0), 571 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0), 572 }; 573 574 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = { 575 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0), 576 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0), 577 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0), 578 }; 579 580 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" }; 581 582 static const struct soc_enum wm8900_lineout2_lp_mux = 583 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux); 584 585 static const struct snd_kcontrol_new wm8900_lineout2_lp = 586 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux); 587 588 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = { 589 590 /* Externally visible pins */ 591 SND_SOC_DAPM_OUTPUT("LINEOUT1L"), 592 SND_SOC_DAPM_OUTPUT("LINEOUT1R"), 593 SND_SOC_DAPM_OUTPUT("LINEOUT2L"), 594 SND_SOC_DAPM_OUTPUT("LINEOUT2R"), 595 SND_SOC_DAPM_OUTPUT("HP_L"), 596 SND_SOC_DAPM_OUTPUT("HP_R"), 597 598 SND_SOC_DAPM_INPUT("RINPUT1"), 599 SND_SOC_DAPM_INPUT("LINPUT1"), 600 SND_SOC_DAPM_INPUT("RINPUT2"), 601 SND_SOC_DAPM_INPUT("LINPUT2"), 602 SND_SOC_DAPM_INPUT("RINPUT3"), 603 SND_SOC_DAPM_INPUT("LINPUT3"), 604 SND_SOC_DAPM_INPUT("AUX"), 605 606 SND_SOC_DAPM_VMID("VMID"), 607 608 /* Input */ 609 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0, 610 wm8900_linpga_controls, 611 ARRAY_SIZE(wm8900_linpga_controls)), 612 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0, 613 wm8900_rinpga_controls, 614 ARRAY_SIZE(wm8900_rinpga_controls)), 615 616 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0, 617 wm8900_linmix_controls, 618 ARRAY_SIZE(wm8900_linmix_controls)), 619 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0, 620 wm8900_rinmix_controls, 621 ARRAY_SIZE(wm8900_rinmix_controls)), 622 623 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0), 624 625 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0), 626 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0), 627 628 /* Output */ 629 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0), 630 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0), 631 632 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0, 633 wm8900_hp_event, 634 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 635 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 636 637 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0), 638 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0), 639 640 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp), 641 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0), 642 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0), 643 644 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0, 645 wm8900_loutmix_controls, 646 ARRAY_SIZE(wm8900_loutmix_controls)), 647 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0, 648 wm8900_routmix_controls, 649 ARRAY_SIZE(wm8900_routmix_controls)), 650 }; 651 652 /* Target, Path, Source */ 653 static const struct snd_soc_dapm_route audio_map[] = { 654 /* Inputs */ 655 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"}, 656 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"}, 657 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"}, 658 659 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"}, 660 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"}, 661 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"}, 662 663 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"}, 664 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"}, 665 {"Left Input Mixer", "AUX Switch", "AUX"}, 666 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"}, 667 668 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"}, 669 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"}, 670 {"Right Input Mixer", "AUX Switch", "AUX"}, 671 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"}, 672 673 {"ADCL", NULL, "Left Input Mixer"}, 674 {"ADCR", NULL, "Right Input Mixer"}, 675 676 /* Outputs */ 677 {"LINEOUT1L", NULL, "LINEOUT1L PGA"}, 678 {"LINEOUT1L PGA", NULL, "Left Output Mixer"}, 679 {"LINEOUT1R", NULL, "LINEOUT1R PGA"}, 680 {"LINEOUT1R PGA", NULL, "Right Output Mixer"}, 681 682 {"LINEOUT2L PGA", NULL, "Left Output Mixer"}, 683 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"}, 684 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"}, 685 {"LINEOUT2L", NULL, "LINEOUT2 LP"}, 686 687 {"LINEOUT2R PGA", NULL, "Right Output Mixer"}, 688 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"}, 689 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"}, 690 {"LINEOUT2R", NULL, "LINEOUT2 LP"}, 691 692 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"}, 693 {"Left Output Mixer", "AUX Bypass Switch", "AUX"}, 694 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, 695 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, 696 {"Left Output Mixer", "DACL Switch", "DACL"}, 697 698 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"}, 699 {"Right Output Mixer", "AUX Bypass Switch", "AUX"}, 700 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"}, 701 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"}, 702 {"Right Output Mixer", "DACR Switch", "DACR"}, 703 704 /* Note that the headphone output stage needs to be connected 705 * externally to LINEOUT2 via DC blocking capacitors. Other 706 * configurations are not supported. 707 * 708 * Note also that left and right headphone paths are treated as a 709 * mono path. 710 */ 711 {"Headphone Amplifier", NULL, "LINEOUT2 LP"}, 712 {"Headphone Amplifier", NULL, "LINEOUT2 LP"}, 713 {"HP_L", NULL, "Headphone Amplifier"}, 714 {"HP_R", NULL, "Headphone Amplifier"}, 715 }; 716 717 static int wm8900_add_widgets(struct snd_soc_codec *codec) 718 { 719 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets, 720 ARRAY_SIZE(wm8900_dapm_widgets)); 721 722 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 723 724 snd_soc_dapm_new_widgets(codec); 725 726 return 0; 727 } 728 729 static int wm8900_hw_params(struct snd_pcm_substream *substream, 730 struct snd_pcm_hw_params *params) 731 { 732 struct snd_soc_pcm_runtime *rtd = substream->private_data; 733 struct snd_soc_device *socdev = rtd->socdev; 734 struct snd_soc_codec *codec = socdev->codec; 735 u16 reg; 736 737 reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60; 738 739 switch (params_format(params)) { 740 case SNDRV_PCM_FORMAT_S16_LE: 741 break; 742 case SNDRV_PCM_FORMAT_S20_3LE: 743 reg |= 0x20; 744 break; 745 case SNDRV_PCM_FORMAT_S24_LE: 746 reg |= 0x40; 747 break; 748 case SNDRV_PCM_FORMAT_S32_LE: 749 reg |= 0x60; 750 break; 751 default: 752 return -EINVAL; 753 } 754 755 wm8900_write(codec, WM8900_REG_AUDIO1, reg); 756 757 return 0; 758 } 759 760 /* FLL divisors */ 761 struct _fll_div { 762 u16 fll_ratio; 763 u16 fllclk_div; 764 u16 fll_slow_lock_ref; 765 u16 n; 766 u16 k; 767 }; 768 769 /* The size in bits of the FLL divide multiplied by 10 770 * to allow rounding later */ 771 #define FIXED_FLL_SIZE ((1 << 16) * 10) 772 773 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 774 unsigned int Fout) 775 { 776 u64 Kpart; 777 unsigned int K, Ndiv, Nmod, target; 778 unsigned int div; 779 780 BUG_ON(!Fout); 781 782 /* The FLL must run at 90-100MHz which is then scaled down to 783 * the output value by FLLCLK_DIV. */ 784 target = Fout; 785 div = 1; 786 while (target < 90000000) { 787 div *= 2; 788 target *= 2; 789 } 790 791 if (target > 100000000) 792 printk(KERN_WARNING "wm8900: FLL rate %d out of range, Fref=%d" 793 " Fout=%d\n", target, Fref, Fout); 794 if (div > 32) { 795 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, " 796 "Fref=%d, Fout=%d, target=%d\n", 797 div, Fref, Fout, target); 798 return -EINVAL; 799 } 800 801 fll_div->fllclk_div = div >> 2; 802 803 if (Fref < 48000) 804 fll_div->fll_slow_lock_ref = 1; 805 else 806 fll_div->fll_slow_lock_ref = 0; 807 808 Ndiv = target / Fref; 809 810 if (Fref < 1000000) 811 fll_div->fll_ratio = 8; 812 else 813 fll_div->fll_ratio = 1; 814 815 fll_div->n = Ndiv / fll_div->fll_ratio; 816 Nmod = (target / fll_div->fll_ratio) % Fref; 817 818 /* Calculate fractional part - scale up so we can round. */ 819 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 820 821 do_div(Kpart, Fref); 822 823 K = Kpart & 0xFFFFFFFF; 824 825 if ((K % 10) >= 5) 826 K += 5; 827 828 /* Move down to proper range now rounding is done */ 829 fll_div->k = K / 10; 830 831 BUG_ON(target != Fout * (fll_div->fllclk_div << 2)); 832 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n); 833 834 return 0; 835 } 836 837 static int wm8900_set_fll(struct snd_soc_codec *codec, 838 int fll_id, unsigned int freq_in, unsigned int freq_out) 839 { 840 struct wm8900_priv *wm8900 = codec->private_data; 841 struct _fll_div fll_div; 842 unsigned int reg; 843 844 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) 845 return 0; 846 847 /* The digital side should be disabled during any change. */ 848 reg = wm8900_read(codec, WM8900_REG_POWER1); 849 wm8900_write(codec, WM8900_REG_POWER1, 850 reg & (~WM8900_REG_POWER1_FLL_ENA)); 851 852 /* Disable the FLL? */ 853 if (!freq_in || !freq_out) { 854 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 855 wm8900_write(codec, WM8900_REG_CLOCKING1, 856 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC)); 857 858 reg = wm8900_read(codec, WM8900_REG_FLLCTL1); 859 wm8900_write(codec, WM8900_REG_FLLCTL1, 860 reg & (~WM8900_REG_FLLCTL1_OSC_ENA)); 861 862 wm8900->fll_in = freq_in; 863 wm8900->fll_out = freq_out; 864 865 return 0; 866 } 867 868 if (fll_factors(&fll_div, freq_in, freq_out) != 0) 869 goto reenable; 870 871 wm8900->fll_in = freq_in; 872 wm8900->fll_out = freq_out; 873 874 /* The osclilator *MUST* be enabled before we enable the 875 * digital circuit. */ 876 wm8900_write(codec, WM8900_REG_FLLCTL1, 877 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); 878 879 wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); 880 wm8900_write(codec, WM8900_REG_FLLCTL5, 881 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); 882 883 if (fll_div.k) { 884 wm8900_write(codec, WM8900_REG_FLLCTL2, 885 (fll_div.k >> 8) | 0x100); 886 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); 887 } else 888 wm8900_write(codec, WM8900_REG_FLLCTL2, 0); 889 890 if (fll_div.fll_slow_lock_ref) 891 wm8900_write(codec, WM8900_REG_FLLCTL6, 892 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); 893 else 894 wm8900_write(codec, WM8900_REG_FLLCTL6, 0); 895 896 reg = wm8900_read(codec, WM8900_REG_POWER1); 897 wm8900_write(codec, WM8900_REG_POWER1, 898 reg | WM8900_REG_POWER1_FLL_ENA); 899 900 reenable: 901 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 902 wm8900_write(codec, WM8900_REG_CLOCKING1, 903 reg | WM8900_REG_CLOCKING1_MCLK_SRC); 904 905 return 0; 906 } 907 908 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, 909 int pll_id, unsigned int freq_in, unsigned int freq_out) 910 { 911 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out); 912 } 913 914 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 915 int div_id, int div) 916 { 917 struct snd_soc_codec *codec = codec_dai->codec; 918 unsigned int reg; 919 920 switch (div_id) { 921 case WM8900_BCLK_DIV: 922 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 923 wm8900_write(codec, WM8900_REG_CLOCKING1, 924 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); 925 break; 926 case WM8900_OPCLK_DIV: 927 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 928 wm8900_write(codec, WM8900_REG_CLOCKING1, 929 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); 930 break; 931 case WM8900_DAC_LRCLK: 932 reg = wm8900_read(codec, WM8900_REG_AUDIO4); 933 wm8900_write(codec, WM8900_REG_AUDIO4, 934 div | (reg & WM8900_LRC_MASK)); 935 break; 936 case WM8900_ADC_LRCLK: 937 reg = wm8900_read(codec, WM8900_REG_AUDIO3); 938 wm8900_write(codec, WM8900_REG_AUDIO3, 939 div | (reg & WM8900_LRC_MASK)); 940 break; 941 case WM8900_DAC_CLKDIV: 942 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 943 wm8900_write(codec, WM8900_REG_CLOCKING2, 944 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV)); 945 break; 946 case WM8900_ADC_CLKDIV: 947 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 948 wm8900_write(codec, WM8900_REG_CLOCKING2, 949 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV)); 950 break; 951 case WM8900_LRCLK_MODE: 952 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 953 wm8900_write(codec, WM8900_REG_DACCTRL, 954 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE)); 955 break; 956 default: 957 return -EINVAL; 958 } 959 960 return 0; 961 } 962 963 964 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, 965 unsigned int fmt) 966 { 967 struct snd_soc_codec *codec = codec_dai->codec; 968 unsigned int clocking1, aif1, aif3, aif4; 969 970 clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1); 971 aif1 = wm8900_read(codec, WM8900_REG_AUDIO1); 972 aif3 = wm8900_read(codec, WM8900_REG_AUDIO3); 973 aif4 = wm8900_read(codec, WM8900_REG_AUDIO4); 974 975 /* set master/slave audio interface */ 976 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 977 case SND_SOC_DAIFMT_CBS_CFS: 978 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; 979 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; 980 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; 981 break; 982 case SND_SOC_DAIFMT_CBS_CFM: 983 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; 984 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; 985 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; 986 break; 987 case SND_SOC_DAIFMT_CBM_CFM: 988 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; 989 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; 990 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; 991 break; 992 case SND_SOC_DAIFMT_CBM_CFS: 993 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; 994 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; 995 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; 996 break; 997 default: 998 return -EINVAL; 999 } 1000 1001 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1002 case SND_SOC_DAIFMT_DSP_A: 1003 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; 1004 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 1005 break; 1006 case SND_SOC_DAIFMT_DSP_B: 1007 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; 1008 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 1009 break; 1010 case SND_SOC_DAIFMT_I2S: 1011 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 1012 aif1 |= 0x10; 1013 break; 1014 case SND_SOC_DAIFMT_RIGHT_J: 1015 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 1016 break; 1017 case SND_SOC_DAIFMT_LEFT_J: 1018 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; 1019 aif1 |= 0x8; 1020 break; 1021 default: 1022 return -EINVAL; 1023 } 1024 1025 /* Clock inversion */ 1026 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1027 case SND_SOC_DAIFMT_DSP_A: 1028 case SND_SOC_DAIFMT_DSP_B: 1029 /* frame inversion not valid for DSP modes */ 1030 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1031 case SND_SOC_DAIFMT_NB_NF: 1032 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 1033 break; 1034 case SND_SOC_DAIFMT_IB_NF: 1035 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 1036 break; 1037 default: 1038 return -EINVAL; 1039 } 1040 break; 1041 case SND_SOC_DAIFMT_I2S: 1042 case SND_SOC_DAIFMT_RIGHT_J: 1043 case SND_SOC_DAIFMT_LEFT_J: 1044 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1045 case SND_SOC_DAIFMT_NB_NF: 1046 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 1047 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 1048 break; 1049 case SND_SOC_DAIFMT_IB_IF: 1050 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 1051 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 1052 break; 1053 case SND_SOC_DAIFMT_IB_NF: 1054 aif1 |= WM8900_REG_AUDIO1_BCLK_INV; 1055 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; 1056 break; 1057 case SND_SOC_DAIFMT_NB_IF: 1058 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; 1059 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; 1060 break; 1061 default: 1062 return -EINVAL; 1063 } 1064 break; 1065 default: 1066 return -EINVAL; 1067 } 1068 1069 wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1); 1070 wm8900_write(codec, WM8900_REG_AUDIO1, aif1); 1071 wm8900_write(codec, WM8900_REG_AUDIO3, aif3); 1072 wm8900_write(codec, WM8900_REG_AUDIO4, aif4); 1073 1074 return 0; 1075 } 1076 1077 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1078 { 1079 struct snd_soc_codec *codec = codec_dai->codec; 1080 u16 reg; 1081 1082 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 1083 1084 if (mute) 1085 reg |= WM8900_REG_DACCTRL_MUTE; 1086 else 1087 reg &= ~WM8900_REG_DACCTRL_MUTE; 1088 1089 wm8900_write(codec, WM8900_REG_DACCTRL, reg); 1090 1091 return 0; 1092 } 1093 1094 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1095 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 1096 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1097 1098 #define WM8900_PCM_FORMATS \ 1099 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ 1100 SNDRV_PCM_FORMAT_S24_LE) 1101 1102 struct snd_soc_dai wm8900_dai = { 1103 .name = "WM8900 HiFi", 1104 .playback = { 1105 .stream_name = "HiFi Playback", 1106 .channels_min = 1, 1107 .channels_max = 2, 1108 .rates = WM8900_RATES, 1109 .formats = WM8900_PCM_FORMATS, 1110 }, 1111 .capture = { 1112 .stream_name = "HiFi Capture", 1113 .channels_min = 1, 1114 .channels_max = 2, 1115 .rates = WM8900_RATES, 1116 .formats = WM8900_PCM_FORMATS, 1117 }, 1118 .ops = { 1119 .hw_params = wm8900_hw_params, 1120 }, 1121 .dai_ops = { 1122 .set_clkdiv = wm8900_set_dai_clkdiv, 1123 .set_pll = wm8900_set_dai_pll, 1124 .set_fmt = wm8900_set_dai_fmt, 1125 .digital_mute = wm8900_digital_mute, 1126 }, 1127 }; 1128 EXPORT_SYMBOL_GPL(wm8900_dai); 1129 1130 static int wm8900_set_bias_level(struct snd_soc_codec *codec, 1131 enum snd_soc_bias_level level) 1132 { 1133 u16 reg; 1134 1135 switch (level) { 1136 case SND_SOC_BIAS_ON: 1137 /* Enable thermal shutdown */ 1138 reg = wm8900_read(codec, WM8900_REG_GPIO); 1139 wm8900_write(codec, WM8900_REG_GPIO, 1140 reg | WM8900_REG_GPIO_TEMP_ENA); 1141 reg = wm8900_read(codec, WM8900_REG_ADDCTL); 1142 wm8900_write(codec, WM8900_REG_ADDCTL, 1143 reg | WM8900_REG_ADDCTL_TEMP_SD); 1144 break; 1145 1146 case SND_SOC_BIAS_PREPARE: 1147 break; 1148 1149 case SND_SOC_BIAS_STANDBY: 1150 /* Charge capacitors if initial power up */ 1151 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1152 /* STARTUP_BIAS_ENA on */ 1153 wm8900_write(codec, WM8900_REG_POWER1, 1154 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1155 1156 /* Startup bias mode */ 1157 wm8900_write(codec, WM8900_REG_ADDCTL, 1158 WM8900_REG_ADDCTL_BIAS_SRC | 1159 WM8900_REG_ADDCTL_VMID_SOFTST); 1160 1161 /* VMID 2x50k */ 1162 wm8900_write(codec, WM8900_REG_POWER1, 1163 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); 1164 1165 /* Allow capacitors to charge */ 1166 schedule_timeout_interruptible(msecs_to_jiffies(400)); 1167 1168 /* Enable bias */ 1169 wm8900_write(codec, WM8900_REG_POWER1, 1170 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 1171 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1172 1173 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1174 1175 wm8900_write(codec, WM8900_REG_POWER1, 1176 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1177 } 1178 1179 reg = wm8900_read(codec, WM8900_REG_POWER1); 1180 wm8900_write(codec, WM8900_REG_POWER1, 1181 (reg & WM8900_REG_POWER1_FLL_ENA) | 1182 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1183 wm8900_write(codec, WM8900_REG_POWER2, 1184 WM8900_REG_POWER2_SYSCLK_ENA); 1185 wm8900_write(codec, WM8900_REG_POWER3, 0); 1186 break; 1187 1188 case SND_SOC_BIAS_OFF: 1189 /* Startup bias enable */ 1190 reg = wm8900_read(codec, WM8900_REG_POWER1); 1191 wm8900_write(codec, WM8900_REG_POWER1, 1192 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1193 wm8900_write(codec, WM8900_REG_ADDCTL, 1194 WM8900_REG_ADDCTL_BIAS_SRC | 1195 WM8900_REG_ADDCTL_VMID_SOFTST); 1196 1197 /* Discharge caps */ 1198 wm8900_write(codec, WM8900_REG_POWER1, 1199 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1200 schedule_timeout_interruptible(msecs_to_jiffies(500)); 1201 1202 /* Remove clamp */ 1203 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 1204 1205 /* Power down */ 1206 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1207 wm8900_write(codec, WM8900_REG_POWER1, 0); 1208 wm8900_write(codec, WM8900_REG_POWER2, 0); 1209 wm8900_write(codec, WM8900_REG_POWER3, 0); 1210 1211 /* Need to let things settle before stopping the clock 1212 * to ensure that restart works, see "Stopping the 1213 * master clock" in the datasheet. */ 1214 schedule_timeout_interruptible(msecs_to_jiffies(1)); 1215 wm8900_write(codec, WM8900_REG_POWER2, 1216 WM8900_REG_POWER2_SYSCLK_ENA); 1217 break; 1218 } 1219 codec->bias_level = level; 1220 return 0; 1221 } 1222 1223 static int wm8900_suspend(struct platform_device *pdev, pm_message_t state) 1224 { 1225 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1226 struct snd_soc_codec *codec = socdev->codec; 1227 struct wm8900_priv *wm8900 = codec->private_data; 1228 int fll_out = wm8900->fll_out; 1229 int fll_in = wm8900->fll_in; 1230 int ret; 1231 1232 /* Stop the FLL in an orderly fashion */ 1233 ret = wm8900_set_fll(codec, 0, 0, 0); 1234 if (ret != 0) { 1235 dev_err(&pdev->dev, "Failed to stop FLL\n"); 1236 return ret; 1237 } 1238 1239 wm8900->fll_out = fll_out; 1240 wm8900->fll_in = fll_in; 1241 1242 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF); 1243 1244 return 0; 1245 } 1246 1247 static int wm8900_resume(struct platform_device *pdev) 1248 { 1249 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1250 struct snd_soc_codec *codec = socdev->codec; 1251 struct wm8900_priv *wm8900 = codec->private_data; 1252 u16 *cache; 1253 int i, ret; 1254 1255 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults), 1256 GFP_KERNEL); 1257 1258 wm8900_reset(codec); 1259 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1260 1261 /* Restart the FLL? */ 1262 if (wm8900->fll_out) { 1263 int fll_out = wm8900->fll_out; 1264 int fll_in = wm8900->fll_in; 1265 1266 wm8900->fll_in = 0; 1267 wm8900->fll_out = 0; 1268 1269 ret = wm8900_set_fll(codec, 0, fll_in, fll_out); 1270 if (ret != 0) { 1271 dev_err(&pdev->dev, "Failed to restart FLL\n"); 1272 return ret; 1273 } 1274 } 1275 1276 if (cache) { 1277 for (i = 0; i < WM8900_MAXREG; i++) 1278 wm8900_write(codec, i, cache[i]); 1279 kfree(cache); 1280 } else 1281 dev_err(&pdev->dev, "Unable to allocate register cache\n"); 1282 1283 return 0; 1284 } 1285 1286 /* 1287 * initialise the WM8900 driver 1288 * register the mixer and dsp interfaces with the kernel 1289 */ 1290 static int wm8900_init(struct snd_soc_device *socdev) 1291 { 1292 struct snd_soc_codec *codec = socdev->codec; 1293 int ret = 0; 1294 unsigned int reg; 1295 struct i2c_client *i2c_client = socdev->codec->control_data; 1296 1297 codec->name = "WM8900"; 1298 codec->owner = THIS_MODULE; 1299 codec->read = wm8900_read; 1300 codec->write = wm8900_write; 1301 codec->dai = &wm8900_dai; 1302 codec->num_dai = 1; 1303 codec->reg_cache_size = WM8900_MAXREG; 1304 codec->reg_cache = kmemdup(wm8900_reg_defaults, 1305 sizeof(wm8900_reg_defaults), GFP_KERNEL); 1306 1307 if (codec->reg_cache == NULL) 1308 return -ENOMEM; 1309 1310 reg = wm8900_read(codec, WM8900_REG_ID); 1311 if (reg != 0x8900) { 1312 dev_err(&i2c_client->dev, "Device is not a WM8900 - ID %x\n", 1313 reg); 1314 return -ENODEV; 1315 } 1316 1317 codec->private_data = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL); 1318 if (codec->private_data == NULL) { 1319 ret = -ENOMEM; 1320 goto priv_err; 1321 } 1322 1323 /* Read back from the chip */ 1324 reg = wm8900_chip_read(codec, WM8900_REG_POWER1); 1325 reg = (reg >> 12) & 0xf; 1326 dev_info(&i2c_client->dev, "WM8900 revision %d\n", reg); 1327 1328 wm8900_reset(codec); 1329 1330 /* Latch the volume update bits */ 1331 wm8900_write(codec, WM8900_REG_LINVOL, 1332 wm8900_read(codec, WM8900_REG_LINVOL) | 0x100); 1333 wm8900_write(codec, WM8900_REG_RINVOL, 1334 wm8900_read(codec, WM8900_REG_RINVOL) | 0x100); 1335 wm8900_write(codec, WM8900_REG_LOUT1CTL, 1336 wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100); 1337 wm8900_write(codec, WM8900_REG_ROUT1CTL, 1338 wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100); 1339 wm8900_write(codec, WM8900_REG_LOUT2CTL, 1340 wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100); 1341 wm8900_write(codec, WM8900_REG_ROUT2CTL, 1342 wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100); 1343 wm8900_write(codec, WM8900_REG_LDAC_DV, 1344 wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100); 1345 wm8900_write(codec, WM8900_REG_RDAC_DV, 1346 wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100); 1347 wm8900_write(codec, WM8900_REG_LADC_DV, 1348 wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100); 1349 wm8900_write(codec, WM8900_REG_RADC_DV, 1350 wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100); 1351 1352 /* Set the DAC and mixer output bias */ 1353 wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81); 1354 1355 /* Register pcms */ 1356 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1357 if (ret < 0) { 1358 dev_err(&i2c_client->dev, "Failed to register new PCMs\n"); 1359 goto pcm_err; 1360 } 1361 1362 /* Turn the chip on */ 1363 codec->bias_level = SND_SOC_BIAS_OFF; 1364 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1365 1366 wm8900_add_controls(codec); 1367 wm8900_add_widgets(codec); 1368 1369 ret = snd_soc_register_card(socdev); 1370 if (ret < 0) { 1371 dev_err(&i2c_client->dev, "Failed to register card\n"); 1372 goto card_err; 1373 } 1374 return ret; 1375 1376 card_err: 1377 snd_soc_free_pcms(socdev); 1378 snd_soc_dapm_free(socdev); 1379 pcm_err: 1380 kfree(codec->reg_cache); 1381 priv_err: 1382 kfree(codec->private_data); 1383 return ret; 1384 } 1385 1386 static struct snd_soc_device *wm8900_socdev; 1387 1388 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1389 1390 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; 1391 1392 /* Magic definition of all other variables and things */ 1393 I2C_CLIENT_INSMOD; 1394 1395 static struct i2c_driver wm8900_i2c_driver; 1396 static struct i2c_client client_template; 1397 1398 /* If the i2c layer weren't so broken, we could pass this kind of data 1399 around */ 1400 static int wm8900_codec_probe(struct i2c_adapter *adap, int addr, int kind) 1401 { 1402 struct snd_soc_device *socdev = wm8900_socdev; 1403 struct wm8900_setup_data *setup = socdev->codec_data; 1404 struct snd_soc_codec *codec = socdev->codec; 1405 struct i2c_client *i2c; 1406 int ret; 1407 1408 if (addr != setup->i2c_address) 1409 return -ENODEV; 1410 1411 dev_err(&adap->dev, "Probe on %x\n", addr); 1412 1413 client_template.adapter = adap; 1414 client_template.addr = addr; 1415 1416 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); 1417 if (i2c == NULL) { 1418 kfree(codec); 1419 return -ENOMEM; 1420 } 1421 i2c_set_clientdata(i2c, codec); 1422 codec->control_data = i2c; 1423 1424 ret = i2c_attach_client(i2c); 1425 if (ret < 0) { 1426 dev_err(&adap->dev, 1427 "failed to attach codec at addr %x\n", addr); 1428 goto err; 1429 } 1430 1431 ret = wm8900_init(socdev); 1432 if (ret < 0) { 1433 dev_err(&adap->dev, "failed to initialise WM8900\n"); 1434 goto err; 1435 } 1436 return ret; 1437 1438 err: 1439 kfree(codec); 1440 kfree(i2c); 1441 return ret; 1442 } 1443 1444 static int wm8900_i2c_detach(struct i2c_client *client) 1445 { 1446 struct snd_soc_codec *codec = i2c_get_clientdata(client); 1447 i2c_detach_client(client); 1448 kfree(codec->reg_cache); 1449 kfree(client); 1450 return 0; 1451 } 1452 1453 static int wm8900_i2c_attach(struct i2c_adapter *adap) 1454 { 1455 return i2c_probe(adap, &addr_data, wm8900_codec_probe); 1456 } 1457 1458 /* corgi i2c codec control layer */ 1459 static struct i2c_driver wm8900_i2c_driver = { 1460 .driver = { 1461 .name = "WM8900 I2C codec", 1462 .owner = THIS_MODULE, 1463 }, 1464 .attach_adapter = wm8900_i2c_attach, 1465 .detach_client = wm8900_i2c_detach, 1466 .command = NULL, 1467 }; 1468 1469 static struct i2c_client client_template = { 1470 .name = "WM8900", 1471 .driver = &wm8900_i2c_driver, 1472 }; 1473 #endif 1474 1475 static int wm8900_probe(struct platform_device *pdev) 1476 { 1477 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1478 struct wm8900_setup_data *setup; 1479 struct snd_soc_codec *codec; 1480 int ret = 0; 1481 1482 dev_info(&pdev->dev, "WM8900 Audio Codec\n"); 1483 1484 setup = socdev->codec_data; 1485 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 1486 if (codec == NULL) 1487 return -ENOMEM; 1488 1489 mutex_init(&codec->mutex); 1490 INIT_LIST_HEAD(&codec->dapm_widgets); 1491 INIT_LIST_HEAD(&codec->dapm_paths); 1492 1493 socdev->codec = codec; 1494 1495 codec->set_bias_level = wm8900_set_bias_level; 1496 1497 wm8900_socdev = socdev; 1498 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1499 if (setup->i2c_address) { 1500 normal_i2c[0] = setup->i2c_address; 1501 codec->hw_write = (hw_write_t)i2c_master_send; 1502 ret = i2c_add_driver(&wm8900_i2c_driver); 1503 if (ret != 0) 1504 printk(KERN_ERR "can't add i2c driver"); 1505 } 1506 #else 1507 #error Non-I2C interfaces not yet supported 1508 #endif 1509 return ret; 1510 } 1511 1512 /* power down chip */ 1513 static int wm8900_remove(struct platform_device *pdev) 1514 { 1515 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1516 struct snd_soc_codec *codec = socdev->codec; 1517 1518 if (codec->control_data) 1519 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF); 1520 1521 snd_soc_free_pcms(socdev); 1522 snd_soc_dapm_free(socdev); 1523 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1524 i2c_del_driver(&wm8900_i2c_driver); 1525 #endif 1526 kfree(codec); 1527 1528 return 0; 1529 } 1530 1531 struct snd_soc_codec_device soc_codec_dev_wm8900 = { 1532 .probe = wm8900_probe, 1533 .remove = wm8900_remove, 1534 .suspend = wm8900_suspend, 1535 .resume = wm8900_resume, 1536 }; 1537 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900); 1538 1539 MODULE_DESCRIPTION("ASoC WM8900 driver"); 1540 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>"); 1541 MODULE_LICENSE("GPL"); 1542