1 /* 2 * wm8350.c -- WM8350 ALSA SoC audio driver 3 * 4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/platform_device.h> 20 #include <linux/mfd/wm8350/audio.h> 21 #include <linux/mfd/wm8350/core.h> 22 #include <linux/regulator/consumer.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <trace/events/asoc.h> 30 31 #include "wm8350.h" 32 33 #define WM8350_OUTn_0dB 0x39 34 35 #define WM8350_RAMP_NONE 0 36 #define WM8350_RAMP_UP 1 37 #define WM8350_RAMP_DOWN 2 38 39 /* We only include the analogue supplies here; the digital supplies 40 * need to be available well before this driver can be probed. 41 */ 42 static const char *supply_names[] = { 43 "AVDD", 44 "HPVDD", 45 }; 46 47 struct wm8350_output { 48 u16 active; 49 u16 left_vol; 50 u16 right_vol; 51 u16 ramp; 52 u16 mute; 53 }; 54 55 struct wm8350_jack_data { 56 struct snd_soc_jack *jack; 57 struct delayed_work work; 58 int report; 59 int short_report; 60 }; 61 62 struct wm8350_data { 63 struct wm8350 *wm8350; 64 struct wm8350_output out1; 65 struct wm8350_output out2; 66 struct wm8350_jack_data hpl; 67 struct wm8350_jack_data hpr; 68 struct wm8350_jack_data mic; 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 70 int fll_freq_out; 71 int fll_freq_in; 72 }; 73 74 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec, 75 unsigned int reg) 76 { 77 struct wm8350 *wm8350 = codec->control_data; 78 return wm8350->reg_cache[reg]; 79 } 80 81 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, 82 unsigned int reg) 83 { 84 struct wm8350 *wm8350 = codec->control_data; 85 return wm8350_reg_read(wm8350, reg); 86 } 87 88 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg, 89 unsigned int value) 90 { 91 struct wm8350 *wm8350 = codec->control_data; 92 return wm8350_reg_write(wm8350, reg, value); 93 } 94 95 /* 96 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. 97 */ 98 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) 99 { 100 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 101 struct wm8350_output *out1 = &wm8350_data->out1; 102 struct wm8350 *wm8350 = codec->control_data; 103 int left_complete = 0, right_complete = 0; 104 u16 reg, val; 105 106 /* left channel */ 107 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); 108 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 109 110 if (out1->ramp == WM8350_RAMP_UP) { 111 /* ramp step up */ 112 if (val < out1->left_vol) { 113 val++; 114 reg &= ~WM8350_OUT1L_VOL_MASK; 115 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 116 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 117 } else 118 left_complete = 1; 119 } else if (out1->ramp == WM8350_RAMP_DOWN) { 120 /* ramp step down */ 121 if (val > 0) { 122 val--; 123 reg &= ~WM8350_OUT1L_VOL_MASK; 124 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 125 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 126 } else 127 left_complete = 1; 128 } else 129 return 1; 130 131 /* right channel */ 132 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); 133 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 134 if (out1->ramp == WM8350_RAMP_UP) { 135 /* ramp step up */ 136 if (val < out1->right_vol) { 137 val++; 138 reg &= ~WM8350_OUT1R_VOL_MASK; 139 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 140 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 141 } else 142 right_complete = 1; 143 } else if (out1->ramp == WM8350_RAMP_DOWN) { 144 /* ramp step down */ 145 if (val > 0) { 146 val--; 147 reg &= ~WM8350_OUT1R_VOL_MASK; 148 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 149 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 150 } else 151 right_complete = 1; 152 } 153 154 /* only hit the update bit if either volume has changed this step */ 155 if (!left_complete || !right_complete) 156 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); 157 158 return left_complete & right_complete; 159 } 160 161 /* 162 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. 163 */ 164 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) 165 { 166 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 167 struct wm8350_output *out2 = &wm8350_data->out2; 168 struct wm8350 *wm8350 = codec->control_data; 169 int left_complete = 0, right_complete = 0; 170 u16 reg, val; 171 172 /* left channel */ 173 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); 174 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 175 if (out2->ramp == WM8350_RAMP_UP) { 176 /* ramp step up */ 177 if (val < out2->left_vol) { 178 val++; 179 reg &= ~WM8350_OUT2L_VOL_MASK; 180 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 181 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 182 } else 183 left_complete = 1; 184 } else if (out2->ramp == WM8350_RAMP_DOWN) { 185 /* ramp step down */ 186 if (val > 0) { 187 val--; 188 reg &= ~WM8350_OUT2L_VOL_MASK; 189 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 190 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 191 } else 192 left_complete = 1; 193 } else 194 return 1; 195 196 /* right channel */ 197 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); 198 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 199 if (out2->ramp == WM8350_RAMP_UP) { 200 /* ramp step up */ 201 if (val < out2->right_vol) { 202 val++; 203 reg &= ~WM8350_OUT2R_VOL_MASK; 204 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 205 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 206 } else 207 right_complete = 1; 208 } else if (out2->ramp == WM8350_RAMP_DOWN) { 209 /* ramp step down */ 210 if (val > 0) { 211 val--; 212 reg &= ~WM8350_OUT2R_VOL_MASK; 213 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 214 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 215 } else 216 right_complete = 1; 217 } 218 219 /* only hit the update bit if either volume has changed this step */ 220 if (!left_complete || !right_complete) 221 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); 222 223 return left_complete & right_complete; 224 } 225 226 /* 227 * This work ramps both output PGAs at stream start/stop time to 228 * minimise pop associated with DAPM power switching. 229 * It's best to enable Zero Cross when ramping occurs to minimise any 230 * zipper noises. 231 */ 232 static void wm8350_pga_work(struct work_struct *work) 233 { 234 struct snd_soc_dapm_context *dapm = 235 container_of(work, struct snd_soc_dapm_context, delayed_work.work); 236 struct snd_soc_codec *codec = dapm->codec; 237 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 238 struct wm8350_output *out1 = &wm8350_data->out1, 239 *out2 = &wm8350_data->out2; 240 int i, out1_complete, out2_complete; 241 242 /* do we need to ramp at all ? */ 243 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) 244 return; 245 246 /* PGA volumes have 6 bits of resolution to ramp */ 247 for (i = 0; i <= 63; i++) { 248 out1_complete = 1, out2_complete = 1; 249 if (out1->ramp != WM8350_RAMP_NONE) 250 out1_complete = wm8350_out1_ramp_step(codec); 251 if (out2->ramp != WM8350_RAMP_NONE) 252 out2_complete = wm8350_out2_ramp_step(codec); 253 254 /* ramp finished ? */ 255 if (out1_complete && out2_complete) 256 break; 257 258 /* we need to delay longer on the up ramp */ 259 if (out1->ramp == WM8350_RAMP_UP || 260 out2->ramp == WM8350_RAMP_UP) { 261 /* delay is longer over 0dB as increases are larger */ 262 if (i >= WM8350_OUTn_0dB) 263 schedule_timeout_interruptible(msecs_to_jiffies 264 (2)); 265 else 266 schedule_timeout_interruptible(msecs_to_jiffies 267 (1)); 268 } else 269 udelay(50); /* doesn't matter if we delay longer */ 270 } 271 272 out1->ramp = WM8350_RAMP_NONE; 273 out2->ramp = WM8350_RAMP_NONE; 274 } 275 276 /* 277 * WM8350 Controls 278 */ 279 280 static int pga_event(struct snd_soc_dapm_widget *w, 281 struct snd_kcontrol *kcontrol, int event) 282 { 283 struct snd_soc_codec *codec = w->codec; 284 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 285 struct wm8350_output *out; 286 287 switch (w->shift) { 288 case 0: 289 case 1: 290 out = &wm8350_data->out1; 291 break; 292 case 2: 293 case 3: 294 out = &wm8350_data->out2; 295 break; 296 297 default: 298 BUG(); 299 return -1; 300 } 301 302 switch (event) { 303 case SND_SOC_DAPM_POST_PMU: 304 out->ramp = WM8350_RAMP_UP; 305 out->active = 1; 306 307 if (!delayed_work_pending(&codec->dapm.delayed_work)) 308 schedule_delayed_work(&codec->dapm.delayed_work, 309 msecs_to_jiffies(1)); 310 break; 311 312 case SND_SOC_DAPM_PRE_PMD: 313 out->ramp = WM8350_RAMP_DOWN; 314 out->active = 0; 315 316 if (!delayed_work_pending(&codec->dapm.delayed_work)) 317 schedule_delayed_work(&codec->dapm.delayed_work, 318 msecs_to_jiffies(1)); 319 break; 320 } 321 322 return 0; 323 } 324 325 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, 326 struct snd_ctl_elem_value *ucontrol) 327 { 328 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 329 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 330 struct wm8350_output *out = NULL; 331 struct soc_mixer_control *mc = 332 (struct soc_mixer_control *)kcontrol->private_value; 333 int ret; 334 unsigned int reg = mc->reg; 335 u16 val; 336 337 /* For OUT1 and OUT2 we shadow the values and only actually write 338 * them out when active in order to ensure the amplifier comes on 339 * as quietly as possible. */ 340 switch (reg) { 341 case WM8350_LOUT1_VOLUME: 342 out = &wm8350_priv->out1; 343 break; 344 case WM8350_LOUT2_VOLUME: 345 out = &wm8350_priv->out2; 346 break; 347 default: 348 break; 349 } 350 351 if (out) { 352 out->left_vol = ucontrol->value.integer.value[0]; 353 out->right_vol = ucontrol->value.integer.value[1]; 354 if (!out->active) 355 return 1; 356 } 357 358 ret = snd_soc_put_volsw(kcontrol, ucontrol); 359 if (ret < 0) 360 return ret; 361 362 /* now hit the volume update bits (always bit 8) */ 363 val = wm8350_codec_read(codec, reg); 364 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU); 365 return 1; 366 } 367 368 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, 369 struct snd_ctl_elem_value *ucontrol) 370 { 371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 372 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 373 struct wm8350_output *out1 = &wm8350_priv->out1; 374 struct wm8350_output *out2 = &wm8350_priv->out2; 375 struct soc_mixer_control *mc = 376 (struct soc_mixer_control *)kcontrol->private_value; 377 unsigned int reg = mc->reg; 378 379 /* If these are cached registers use the cache */ 380 switch (reg) { 381 case WM8350_LOUT1_VOLUME: 382 ucontrol->value.integer.value[0] = out1->left_vol; 383 ucontrol->value.integer.value[1] = out1->right_vol; 384 return 0; 385 386 case WM8350_LOUT2_VOLUME: 387 ucontrol->value.integer.value[0] = out2->left_vol; 388 ucontrol->value.integer.value[1] = out2->right_vol; 389 return 0; 390 391 default: 392 break; 393 } 394 395 return snd_soc_get_volsw(kcontrol, ucontrol); 396 } 397 398 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; 399 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; 400 static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; 401 static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; 402 static const char *wm8350_adcfilter[] = { "None", "High Pass" }; 403 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; 404 static const char *wm8350_lr[] = { "Left", "Right" }; 405 406 static const struct soc_enum wm8350_enum[] = { 407 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), 408 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), 409 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), 410 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), 411 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), 412 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), 413 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), 414 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), 415 }; 416 417 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0); 418 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0); 419 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); 420 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); 421 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); 422 423 static const unsigned int capture_sd_tlv[] = { 424 TLV_DB_RANGE_HEAD(2), 425 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), 426 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), 427 }; 428 429 static const struct snd_kcontrol_new wm8350_snd_controls[] = { 430 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), 431 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), 432 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume", 433 WM8350_DAC_DIGITAL_VOLUME_L, 434 WM8350_DAC_DIGITAL_VOLUME_R, 435 0, 255, 0, wm8350_get_volsw_2r, 436 wm8350_put_volsw_2r_vu, dac_pcm_tlv), 437 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), 438 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), 439 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]), 440 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]), 441 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]), 442 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume", 443 WM8350_ADC_DIGITAL_VOLUME_L, 444 WM8350_ADC_DIGITAL_VOLUME_R, 445 0, 255, 0, wm8350_get_volsw_2r, 446 wm8350_put_volsw_2r_vu, adc_pcm_tlv), 447 SOC_DOUBLE_TLV("Capture Sidetone Volume", 448 WM8350_ADC_DIVIDER, 449 8, 4, 15, 1, capture_sd_tlv), 450 SOC_DOUBLE_R_EXT_TLV("Capture Volume", 451 WM8350_LEFT_INPUT_VOLUME, 452 WM8350_RIGHT_INPUT_VOLUME, 453 2, 63, 0, wm8350_get_volsw_2r, 454 wm8350_put_volsw_2r_vu, pre_amp_tlv), 455 SOC_DOUBLE_R("Capture ZC Switch", 456 WM8350_LEFT_INPUT_VOLUME, 457 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), 458 SOC_SINGLE_TLV("Left Input Left Sidetone Volume", 459 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), 460 SOC_SINGLE_TLV("Left Input Right Sidetone Volume", 461 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 462 5, 7, 0, out_mix_tlv), 463 SOC_SINGLE_TLV("Left Input Bypass Volume", 464 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 465 9, 7, 0, out_mix_tlv), 466 SOC_SINGLE_TLV("Right Input Left Sidetone Volume", 467 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 468 1, 7, 0, out_mix_tlv), 469 SOC_SINGLE_TLV("Right Input Right Sidetone Volume", 470 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 471 5, 7, 0, out_mix_tlv), 472 SOC_SINGLE_TLV("Right Input Bypass Volume", 473 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 474 13, 7, 0, out_mix_tlv), 475 SOC_SINGLE("Left Input Mixer +20dB Switch", 476 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), 477 SOC_SINGLE("Right Input Mixer +20dB Switch", 478 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), 479 SOC_SINGLE_TLV("Out4 Capture Volume", 480 WM8350_INPUT_MIXER_VOLUME, 481 1, 7, 0, out_mix_tlv), 482 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume", 483 WM8350_LOUT1_VOLUME, 484 WM8350_ROUT1_VOLUME, 485 2, 63, 0, wm8350_get_volsw_2r, 486 wm8350_put_volsw_2r_vu, out_pga_tlv), 487 SOC_DOUBLE_R("Out1 Playback ZC Switch", 488 WM8350_LOUT1_VOLUME, 489 WM8350_ROUT1_VOLUME, 13, 1, 0), 490 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume", 491 WM8350_LOUT2_VOLUME, 492 WM8350_ROUT2_VOLUME, 493 2, 63, 0, wm8350_get_volsw_2r, 494 wm8350_put_volsw_2r_vu, out_pga_tlv), 495 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, 496 WM8350_ROUT2_VOLUME, 13, 1, 0), 497 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), 498 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, 499 5, 7, 0, out_mix_tlv), 500 501 SOC_DOUBLE_R("Out1 Playback Switch", 502 WM8350_LOUT1_VOLUME, 503 WM8350_ROUT1_VOLUME, 504 14, 1, 1), 505 SOC_DOUBLE_R("Out2 Playback Switch", 506 WM8350_LOUT2_VOLUME, 507 WM8350_ROUT2_VOLUME, 508 14, 1, 1), 509 }; 510 511 /* 512 * DAPM Controls 513 */ 514 515 /* Left Playback Mixer */ 516 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { 517 SOC_DAPM_SINGLE("Playback Switch", 518 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), 519 SOC_DAPM_SINGLE("Left Bypass Switch", 520 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), 521 SOC_DAPM_SINGLE("Right Playback Switch", 522 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), 523 SOC_DAPM_SINGLE("Left Sidetone Switch", 524 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), 525 SOC_DAPM_SINGLE("Right Sidetone Switch", 526 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), 527 }; 528 529 /* Right Playback Mixer */ 530 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { 531 SOC_DAPM_SINGLE("Playback Switch", 532 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), 533 SOC_DAPM_SINGLE("Right Bypass Switch", 534 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), 535 SOC_DAPM_SINGLE("Left Playback Switch", 536 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), 537 SOC_DAPM_SINGLE("Left Sidetone Switch", 538 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), 539 SOC_DAPM_SINGLE("Right Sidetone Switch", 540 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), 541 }; 542 543 /* Out4 Mixer */ 544 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { 545 SOC_DAPM_SINGLE("Right Playback Switch", 546 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), 547 SOC_DAPM_SINGLE("Left Playback Switch", 548 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), 549 SOC_DAPM_SINGLE("Right Capture Switch", 550 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), 551 SOC_DAPM_SINGLE("Out3 Playback Switch", 552 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), 553 SOC_DAPM_SINGLE("Right Mixer Switch", 554 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), 555 SOC_DAPM_SINGLE("Left Mixer Switch", 556 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), 557 }; 558 559 /* Out3 Mixer */ 560 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { 561 SOC_DAPM_SINGLE("Left Playback Switch", 562 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), 563 SOC_DAPM_SINGLE("Left Capture Switch", 564 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), 565 SOC_DAPM_SINGLE("Out4 Playback Switch", 566 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), 567 SOC_DAPM_SINGLE("Left Mixer Switch", 568 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), 569 }; 570 571 /* Left Input Mixer */ 572 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { 573 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 574 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), 575 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 576 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), 577 SOC_DAPM_SINGLE("PGA Capture Switch", 578 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1), 579 }; 580 581 /* Right Input Mixer */ 582 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { 583 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 584 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), 585 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 586 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), 587 SOC_DAPM_SINGLE("PGA Capture Switch", 588 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1), 589 }; 590 591 /* Left Mic Mixer */ 592 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { 593 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), 594 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), 595 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), 596 }; 597 598 /* Right Mic Mixer */ 599 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { 600 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), 601 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), 602 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), 603 }; 604 605 /* Beep Switch */ 606 static const struct snd_kcontrol_new wm8350_beep_switch_controls = 607 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); 608 609 /* Out4 Capture Mux */ 610 static const struct snd_kcontrol_new wm8350_out4_capture_controls = 611 SOC_DAPM_ENUM("Route", wm8350_enum[7]); 612 613 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { 614 615 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), 616 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), 617 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, 618 0, pga_event, 619 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 620 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, 621 pga_event, 622 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 623 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, 624 0, pga_event, 625 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 626 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, 627 pga_event, 628 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 629 630 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, 631 7, 0, &wm8350_right_capt_mixer_controls[0], 632 ARRAY_SIZE(wm8350_right_capt_mixer_controls)), 633 634 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, 635 6, 0, &wm8350_left_capt_mixer_controls[0], 636 ARRAY_SIZE(wm8350_left_capt_mixer_controls)), 637 638 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, 639 &wm8350_out4_mixer_controls[0], 640 ARRAY_SIZE(wm8350_out4_mixer_controls)), 641 642 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, 643 &wm8350_out3_mixer_controls[0], 644 ARRAY_SIZE(wm8350_out3_mixer_controls)), 645 646 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, 647 &wm8350_right_play_mixer_controls[0], 648 ARRAY_SIZE(wm8350_right_play_mixer_controls)), 649 650 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, 651 &wm8350_left_play_mixer_controls[0], 652 ARRAY_SIZE(wm8350_left_play_mixer_controls)), 653 654 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, 655 &wm8350_left_mic_mixer_controls[0], 656 ARRAY_SIZE(wm8350_left_mic_mixer_controls)), 657 658 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, 659 &wm8350_right_mic_mixer_controls[0], 660 ARRAY_SIZE(wm8350_right_mic_mixer_controls)), 661 662 /* virtual mixer for Beep and Out2R */ 663 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 664 665 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, 666 &wm8350_beep_switch_controls), 667 668 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 669 WM8350_POWER_MGMT_4, 3, 0), 670 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", 671 WM8350_POWER_MGMT_4, 2, 0), 672 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", 673 WM8350_POWER_MGMT_4, 5, 0), 674 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 675 WM8350_POWER_MGMT_4, 4, 0), 676 677 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), 678 679 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, 680 &wm8350_out4_capture_controls), 681 682 SND_SOC_DAPM_OUTPUT("OUT1R"), 683 SND_SOC_DAPM_OUTPUT("OUT1L"), 684 SND_SOC_DAPM_OUTPUT("OUT2R"), 685 SND_SOC_DAPM_OUTPUT("OUT2L"), 686 SND_SOC_DAPM_OUTPUT("OUT3"), 687 SND_SOC_DAPM_OUTPUT("OUT4"), 688 689 SND_SOC_DAPM_INPUT("IN1RN"), 690 SND_SOC_DAPM_INPUT("IN1RP"), 691 SND_SOC_DAPM_INPUT("IN2R"), 692 SND_SOC_DAPM_INPUT("IN1LP"), 693 SND_SOC_DAPM_INPUT("IN1LN"), 694 SND_SOC_DAPM_INPUT("IN2L"), 695 SND_SOC_DAPM_INPUT("IN3R"), 696 SND_SOC_DAPM_INPUT("IN3L"), 697 }; 698 699 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = { 700 701 /* left playback mixer */ 702 {"Left Playback Mixer", "Playback Switch", "Left DAC"}, 703 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, 704 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, 705 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 706 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 707 708 /* right playback mixer */ 709 {"Right Playback Mixer", "Playback Switch", "Right DAC"}, 710 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, 711 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, 712 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 713 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 714 715 /* out4 playback mixer */ 716 {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, 717 {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, 718 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, 719 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, 720 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, 721 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 722 {"OUT4", NULL, "Out4 Mixer"}, 723 724 /* out3 playback mixer */ 725 {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, 726 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, 727 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 728 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, 729 {"OUT3", NULL, "Out3 Mixer"}, 730 731 /* out2 */ 732 {"Right Out2 PGA", NULL, "Right Playback Mixer"}, 733 {"Left Out2 PGA", NULL, "Left Playback Mixer"}, 734 {"OUT2L", NULL, "Left Out2 PGA"}, 735 {"OUT2R", NULL, "Right Out2 PGA"}, 736 737 /* out1 */ 738 {"Right Out1 PGA", NULL, "Right Playback Mixer"}, 739 {"Left Out1 PGA", NULL, "Left Playback Mixer"}, 740 {"OUT1L", NULL, "Left Out1 PGA"}, 741 {"OUT1R", NULL, "Right Out1 PGA"}, 742 743 /* ADCs */ 744 {"Left ADC", NULL, "Left Capture Mixer"}, 745 {"Right ADC", NULL, "Right Capture Mixer"}, 746 747 /* Left capture mixer */ 748 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, 749 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, 750 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, 751 {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, 752 753 /* Right capture mixer */ 754 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, 755 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, 756 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, 757 {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, 758 759 /* L3 Inputs */ 760 {"IN3L PGA", NULL, "IN3L"}, 761 {"IN3R PGA", NULL, "IN3R"}, 762 763 /* Left Mic mixer */ 764 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, 765 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, 766 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, 767 768 /* Right Mic mixer */ 769 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, 770 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, 771 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, 772 773 /* out 4 capture */ 774 {"Out4 Capture Channel", NULL, "Out4 Mixer"}, 775 776 /* Beep */ 777 {"Beep", NULL, "IN3R PGA"}, 778 }; 779 780 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, 781 int clk_id, unsigned int freq, int dir) 782 { 783 struct snd_soc_codec *codec = codec_dai->codec; 784 struct wm8350 *wm8350 = codec->control_data; 785 u16 fll_4; 786 787 switch (clk_id) { 788 case WM8350_MCLK_SEL_MCLK: 789 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, 790 WM8350_MCLK_SEL); 791 break; 792 case WM8350_MCLK_SEL_PLL_MCLK: 793 case WM8350_MCLK_SEL_PLL_DAC: 794 case WM8350_MCLK_SEL_PLL_ADC: 795 case WM8350_MCLK_SEL_PLL_32K: 796 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, 797 WM8350_MCLK_SEL); 798 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 799 ~WM8350_FLL_CLK_SRC_MASK; 800 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); 801 break; 802 } 803 804 /* MCLK direction */ 805 if (dir == SND_SOC_CLOCK_OUT) 806 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, 807 WM8350_MCLK_DIR); 808 else 809 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, 810 WM8350_MCLK_DIR); 811 812 return 0; 813 } 814 815 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) 816 { 817 struct snd_soc_codec *codec = codec_dai->codec; 818 u16 val; 819 820 switch (div_id) { 821 case WM8350_ADC_CLKDIV: 822 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) & 823 ~WM8350_ADC_CLKDIV_MASK; 824 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div); 825 break; 826 case WM8350_DAC_CLKDIV: 827 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) & 828 ~WM8350_DAC_CLKDIV_MASK; 829 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); 830 break; 831 case WM8350_BCLK_CLKDIV: 832 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 833 ~WM8350_BCLK_DIV_MASK; 834 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 835 break; 836 case WM8350_OPCLK_CLKDIV: 837 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 838 ~WM8350_OPCLK_DIV_MASK; 839 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 840 break; 841 case WM8350_SYS_CLKDIV: 842 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 843 ~WM8350_MCLK_DIV_MASK; 844 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 845 break; 846 case WM8350_DACLR_CLKDIV: 847 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 848 ~WM8350_DACLRC_RATE_MASK; 849 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div); 850 break; 851 case WM8350_ADCLR_CLKDIV: 852 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 853 ~WM8350_ADCLRC_RATE_MASK; 854 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div); 855 break; 856 default: 857 return -EINVAL; 858 } 859 860 return 0; 861 } 862 863 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 864 { 865 struct snd_soc_codec *codec = codec_dai->codec; 866 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 867 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); 868 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) & 869 ~WM8350_BCLK_MSTR; 870 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 871 ~WM8350_DACLRC_ENA; 872 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 873 ~WM8350_ADCLRC_ENA; 874 875 /* set master/slave audio interface */ 876 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 877 case SND_SOC_DAIFMT_CBM_CFM: 878 master |= WM8350_BCLK_MSTR; 879 dac_lrc |= WM8350_DACLRC_ENA; 880 adc_lrc |= WM8350_ADCLRC_ENA; 881 break; 882 case SND_SOC_DAIFMT_CBS_CFS: 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 /* interface format */ 889 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 890 case SND_SOC_DAIFMT_I2S: 891 iface |= 0x2 << 8; 892 break; 893 case SND_SOC_DAIFMT_RIGHT_J: 894 break; 895 case SND_SOC_DAIFMT_LEFT_J: 896 iface |= 0x1 << 8; 897 break; 898 case SND_SOC_DAIFMT_DSP_A: 899 iface |= 0x3 << 8; 900 break; 901 case SND_SOC_DAIFMT_DSP_B: 902 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV; 903 break; 904 default: 905 return -EINVAL; 906 } 907 908 /* clock inversion */ 909 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 910 case SND_SOC_DAIFMT_NB_NF: 911 break; 912 case SND_SOC_DAIFMT_IB_IF: 913 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; 914 break; 915 case SND_SOC_DAIFMT_IB_NF: 916 iface |= WM8350_AIF_BCLK_INV; 917 break; 918 case SND_SOC_DAIFMT_NB_IF: 919 iface |= WM8350_AIF_LRCLK_INV; 920 break; 921 default: 922 return -EINVAL; 923 } 924 925 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 926 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master); 927 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc); 928 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc); 929 return 0; 930 } 931 932 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream, 933 int cmd, struct snd_soc_dai *codec_dai) 934 { 935 struct snd_soc_codec *codec = codec_dai->codec; 936 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) & 937 WM8350_BCLK_MSTR; 938 int enabled = 0; 939 940 /* Check that the DACs or ADCs are enabled since they are 941 * required for LRC in master mode. The DACs or ADCs need a 942 * valid audio path i.e. pin -> ADC or DAC -> pin before 943 * the LRC will be enabled in master mode. */ 944 if (!master || cmd != SNDRV_PCM_TRIGGER_START) 945 return 0; 946 947 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 948 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & 949 (WM8350_ADCR_ENA | WM8350_ADCL_ENA); 950 } else { 951 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & 952 (WM8350_DACR_ENA | WM8350_DACL_ENA); 953 } 954 955 if (!enabled) { 956 dev_err(codec->dev, 957 "%s: invalid audio path - no clocks available\n", 958 __func__); 959 return -EINVAL; 960 } 961 return 0; 962 } 963 964 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, 965 struct snd_pcm_hw_params *params, 966 struct snd_soc_dai *codec_dai) 967 { 968 struct snd_soc_codec *codec = codec_dai->codec; 969 struct wm8350 *wm8350 = codec->control_data; 970 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 971 ~WM8350_AIF_WL_MASK; 972 973 /* bit size */ 974 switch (params_format(params)) { 975 case SNDRV_PCM_FORMAT_S16_LE: 976 break; 977 case SNDRV_PCM_FORMAT_S20_3LE: 978 iface |= 0x1 << 10; 979 break; 980 case SNDRV_PCM_FORMAT_S24_LE: 981 iface |= 0x2 << 10; 982 break; 983 case SNDRV_PCM_FORMAT_S32_LE: 984 iface |= 0x3 << 10; 985 break; 986 } 987 988 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 989 990 /* The sloping stopband filter is recommended for use with 991 * lower sample rates to improve performance. 992 */ 993 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 994 if (params_rate(params) < 24000) 995 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 996 WM8350_DAC_SB_FILT); 997 else 998 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 999 WM8350_DAC_SB_FILT); 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int wm8350_mute(struct snd_soc_dai *dai, int mute) 1006 { 1007 struct snd_soc_codec *codec = dai->codec; 1008 struct wm8350 *wm8350 = codec->control_data; 1009 1010 if (mute) 1011 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1012 else 1013 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1014 return 0; 1015 } 1016 1017 /* FLL divisors */ 1018 struct _fll_div { 1019 int div; /* FLL_OUTDIV */ 1020 int n; 1021 int k; 1022 int ratio; /* FLL_FRATIO */ 1023 }; 1024 1025 /* The size in bits of the fll divide multiplied by 10 1026 * to allow rounding later */ 1027 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1028 1029 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, 1030 unsigned int output) 1031 { 1032 u64 Kpart; 1033 unsigned int t1, t2, K, Nmod; 1034 1035 if (output >= 2815250 && output <= 3125000) 1036 fll_div->div = 0x4; 1037 else if (output >= 5625000 && output <= 6250000) 1038 fll_div->div = 0x3; 1039 else if (output >= 11250000 && output <= 12500000) 1040 fll_div->div = 0x2; 1041 else if (output >= 22500000 && output <= 25000000) 1042 fll_div->div = 0x1; 1043 else { 1044 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); 1045 return -EINVAL; 1046 } 1047 1048 if (input > 48000) 1049 fll_div->ratio = 1; 1050 else 1051 fll_div->ratio = 8; 1052 1053 t1 = output * (1 << (fll_div->div + 1)); 1054 t2 = input * fll_div->ratio; 1055 1056 fll_div->n = t1 / t2; 1057 Nmod = t1 % t2; 1058 1059 if (Nmod) { 1060 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1061 do_div(Kpart, t2); 1062 K = Kpart & 0xFFFFFFFF; 1063 1064 /* Check if we need to round */ 1065 if ((K % 10) >= 5) 1066 K += 5; 1067 1068 /* Move down to proper range now rounding is done */ 1069 K /= 10; 1070 fll_div->k = K; 1071 } else 1072 fll_div->k = 0; 1073 1074 return 0; 1075 } 1076 1077 static int wm8350_set_fll(struct snd_soc_dai *codec_dai, 1078 int pll_id, int source, unsigned int freq_in, 1079 unsigned int freq_out) 1080 { 1081 struct snd_soc_codec *codec = codec_dai->codec; 1082 struct wm8350 *wm8350 = codec->control_data; 1083 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1084 struct _fll_div fll_div; 1085 int ret = 0; 1086 u16 fll_1, fll_4; 1087 1088 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out) 1089 return 0; 1090 1091 /* power down FLL - we need to do this for reconfiguration */ 1092 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1093 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); 1094 1095 if (freq_out == 0 || freq_in == 0) 1096 return ret; 1097 1098 ret = fll_factors(&fll_div, freq_in, freq_out); 1099 if (ret < 0) 1100 return ret; 1101 dev_dbg(wm8350->dev, 1102 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", 1103 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, 1104 fll_div.ratio); 1105 1106 /* set up N.K & dividers */ 1107 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & 1108 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); 1109 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, 1110 fll_1 | (fll_div.div << 8) | 0x50); 1111 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, 1112 (fll_div.ratio << 11) | (fll_div. 1113 n & WM8350_FLL_N_MASK)); 1114 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); 1115 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 1116 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); 1117 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, 1118 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | 1119 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); 1120 1121 /* power FLL on */ 1122 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); 1123 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); 1124 1125 priv->fll_freq_out = freq_out; 1126 priv->fll_freq_in = freq_in; 1127 1128 return 0; 1129 } 1130 1131 static int wm8350_set_bias_level(struct snd_soc_codec *codec, 1132 enum snd_soc_bias_level level) 1133 { 1134 struct wm8350 *wm8350 = codec->control_data; 1135 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1136 struct wm8350_audio_platform_data *platform = 1137 wm8350->codec.platform_data; 1138 u16 pm1; 1139 int ret; 1140 1141 switch (level) { 1142 case SND_SOC_BIAS_ON: 1143 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1144 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1145 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1146 pm1 | WM8350_VMID_50K | 1147 platform->codec_current_on << 14); 1148 break; 1149 1150 case SND_SOC_BIAS_PREPARE: 1151 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); 1152 pm1 &= ~WM8350_VMID_MASK; 1153 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1154 pm1 | WM8350_VMID_50K); 1155 break; 1156 1157 case SND_SOC_BIAS_STANDBY: 1158 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1159 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), 1160 priv->supplies); 1161 if (ret != 0) 1162 return ret; 1163 1164 /* Enable the system clock */ 1165 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, 1166 WM8350_SYSCLK_ENA); 1167 1168 /* mute DAC & outputs */ 1169 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, 1170 WM8350_DAC_MUTE_ENA); 1171 1172 /* discharge cap memory */ 1173 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1174 platform->dis_out1 | 1175 (platform->dis_out2 << 2) | 1176 (platform->dis_out3 << 4) | 1177 (platform->dis_out4 << 6)); 1178 1179 /* wait for discharge */ 1180 schedule_timeout_interruptible(msecs_to_jiffies 1181 (platform-> 1182 cap_discharge_msecs)); 1183 1184 /* enable antipop */ 1185 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1186 (platform->vmid_s_curve << 8)); 1187 1188 /* ramp up vmid */ 1189 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1190 (platform-> 1191 codec_current_charge << 14) | 1192 WM8350_VMID_5K | WM8350_VMIDEN | 1193 WM8350_VBUFEN); 1194 1195 /* wait for vmid */ 1196 schedule_timeout_interruptible(msecs_to_jiffies 1197 (platform-> 1198 vmid_charge_msecs)); 1199 1200 /* turn on vmid 300k */ 1201 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1202 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1203 pm1 |= WM8350_VMID_300K | 1204 (platform->codec_current_standby << 14); 1205 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1206 pm1); 1207 1208 1209 /* enable analogue bias */ 1210 pm1 |= WM8350_BIASEN; 1211 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1212 1213 /* disable antipop */ 1214 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1215 1216 } else { 1217 /* turn on vmid 300k and reduce current */ 1218 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1219 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1220 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1221 pm1 | WM8350_VMID_300K | 1222 (platform-> 1223 codec_current_standby << 14)); 1224 1225 } 1226 break; 1227 1228 case SND_SOC_BIAS_OFF: 1229 1230 /* mute DAC & enable outputs */ 1231 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1232 1233 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, 1234 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | 1235 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); 1236 1237 /* enable anti pop S curve */ 1238 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1239 (platform->vmid_s_curve << 8)); 1240 1241 /* turn off vmid */ 1242 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1243 ~WM8350_VMIDEN; 1244 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1245 1246 /* wait */ 1247 schedule_timeout_interruptible(msecs_to_jiffies 1248 (platform-> 1249 vmid_discharge_msecs)); 1250 1251 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1252 (platform->vmid_s_curve << 8) | 1253 platform->dis_out1 | 1254 (platform->dis_out2 << 2) | 1255 (platform->dis_out3 << 4) | 1256 (platform->dis_out4 << 6)); 1257 1258 /* turn off VBuf and drain */ 1259 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1260 ~(WM8350_VBUFEN | WM8350_VMID_MASK); 1261 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1262 pm1 | WM8350_OUTPUT_DRAIN_EN); 1263 1264 /* wait */ 1265 schedule_timeout_interruptible(msecs_to_jiffies 1266 (platform->drain_msecs)); 1267 1268 pm1 &= ~WM8350_BIASEN; 1269 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1270 1271 /* disable anti-pop */ 1272 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1273 1274 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, 1275 WM8350_OUT1L_ENA); 1276 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, 1277 WM8350_OUT1R_ENA); 1278 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, 1279 WM8350_OUT2L_ENA); 1280 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, 1281 WM8350_OUT2R_ENA); 1282 1283 /* disable clock gen */ 1284 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1285 WM8350_SYSCLK_ENA); 1286 1287 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 1288 priv->supplies); 1289 break; 1290 } 1291 codec->dapm.bias_level = level; 1292 return 0; 1293 } 1294 1295 static int wm8350_suspend(struct snd_soc_codec *codec) 1296 { 1297 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1298 return 0; 1299 } 1300 1301 static int wm8350_resume(struct snd_soc_codec *codec) 1302 { 1303 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1304 1305 return 0; 1306 } 1307 1308 static void wm8350_hp_work(struct wm8350_data *priv, 1309 struct wm8350_jack_data *jack, 1310 u16 mask) 1311 { 1312 struct wm8350 *wm8350 = priv->wm8350; 1313 u16 reg; 1314 int report; 1315 1316 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1317 if (reg & mask) 1318 report = jack->report; 1319 else 1320 report = 0; 1321 1322 snd_soc_jack_report(jack->jack, report, jack->report); 1323 1324 } 1325 1326 static void wm8350_hpl_work(struct work_struct *work) 1327 { 1328 struct wm8350_data *priv = 1329 container_of(work, struct wm8350_data, hpl.work.work); 1330 1331 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL); 1332 } 1333 1334 static void wm8350_hpr_work(struct work_struct *work) 1335 { 1336 struct wm8350_data *priv = 1337 container_of(work, struct wm8350_data, hpr.work.work); 1338 1339 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); 1340 } 1341 1342 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1343 { 1344 struct wm8350_data *priv = data; 1345 struct wm8350 *wm8350 = priv->wm8350; 1346 struct wm8350_jack_data *jack = NULL; 1347 1348 switch (irq - wm8350->irq_base) { 1349 case WM8350_IRQ_CODEC_JCK_DET_L: 1350 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1351 trace_snd_soc_jack_irq("WM8350 HPL"); 1352 #endif 1353 jack = &priv->hpl; 1354 break; 1355 1356 case WM8350_IRQ_CODEC_JCK_DET_R: 1357 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1358 trace_snd_soc_jack_irq("WM8350 HPR"); 1359 #endif 1360 jack = &priv->hpr; 1361 break; 1362 1363 default: 1364 BUG(); 1365 } 1366 1367 if (device_may_wakeup(wm8350->dev)) 1368 pm_wakeup_event(wm8350->dev, 250); 1369 1370 schedule_delayed_work(&jack->work, 200); 1371 1372 return IRQ_HANDLED; 1373 } 1374 1375 /** 1376 * wm8350_hp_jack_detect - Enable headphone jack detection. 1377 * 1378 * @codec: WM8350 codec 1379 * @which: left or right jack detect signal 1380 * @jack: jack to report detection events on 1381 * @report: value to report 1382 * 1383 * Enables the headphone jack detection of the WM8350. If no report 1384 * is specified then detection is disabled. 1385 */ 1386 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, 1387 struct snd_soc_jack *jack, int report) 1388 { 1389 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1390 struct wm8350 *wm8350 = codec->control_data; 1391 int irq; 1392 int ena; 1393 1394 switch (which) { 1395 case WM8350_JDL: 1396 priv->hpl.jack = jack; 1397 priv->hpl.report = report; 1398 irq = WM8350_IRQ_CODEC_JCK_DET_L; 1399 ena = WM8350_JDL_ENA; 1400 break; 1401 1402 case WM8350_JDR: 1403 priv->hpr.jack = jack; 1404 priv->hpr.report = report; 1405 irq = WM8350_IRQ_CODEC_JCK_DET_R; 1406 ena = WM8350_JDR_ENA; 1407 break; 1408 1409 default: 1410 return -EINVAL; 1411 } 1412 1413 if (report) { 1414 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1415 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); 1416 } else { 1417 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena); 1418 } 1419 1420 /* Sync status */ 1421 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv); 1422 1423 return 0; 1424 } 1425 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); 1426 1427 static irqreturn_t wm8350_mic_handler(int irq, void *data) 1428 { 1429 struct wm8350_data *priv = data; 1430 struct wm8350 *wm8350 = priv->wm8350; 1431 u16 reg; 1432 int report = 0; 1433 1434 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1435 trace_snd_soc_jack_irq("WM8350 mic"); 1436 #endif 1437 1438 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1439 if (reg & WM8350_JACK_MICSCD_LVL) 1440 report |= priv->mic.short_report; 1441 if (reg & WM8350_JACK_MICSD_LVL) 1442 report |= priv->mic.report; 1443 1444 snd_soc_jack_report(priv->mic.jack, report, 1445 priv->mic.report | priv->mic.short_report); 1446 1447 return IRQ_HANDLED; 1448 } 1449 1450 /** 1451 * wm8350_mic_jack_detect - Enable microphone jack detection. 1452 * 1453 * @codec: WM8350 codec 1454 * @jack: jack to report detection events on 1455 * @detect_report: value to report when presence detected 1456 * @short_report: value to report when microphone short detected 1457 * 1458 * Enables the microphone jack detection of the WM8350. If both reports 1459 * are specified as zero then detection is disabled. 1460 */ 1461 int wm8350_mic_jack_detect(struct snd_soc_codec *codec, 1462 struct snd_soc_jack *jack, 1463 int detect_report, int short_report) 1464 { 1465 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1466 struct wm8350 *wm8350 = codec->control_data; 1467 1468 priv->mic.jack = jack; 1469 priv->mic.report = detect_report; 1470 priv->mic.short_report = short_report; 1471 1472 if (detect_report || short_report) { 1473 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1474 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1, 1475 WM8350_MIC_DET_ENA); 1476 } else { 1477 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1, 1478 WM8350_MIC_DET_ENA); 1479 } 1480 1481 return 0; 1482 } 1483 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect); 1484 1485 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) 1486 1487 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1488 SNDRV_PCM_FMTBIT_S20_3LE |\ 1489 SNDRV_PCM_FMTBIT_S24_LE) 1490 1491 static const struct snd_soc_dai_ops wm8350_dai_ops = { 1492 .hw_params = wm8350_pcm_hw_params, 1493 .digital_mute = wm8350_mute, 1494 .trigger = wm8350_pcm_trigger, 1495 .set_fmt = wm8350_set_dai_fmt, 1496 .set_sysclk = wm8350_set_dai_sysclk, 1497 .set_pll = wm8350_set_fll, 1498 .set_clkdiv = wm8350_set_clkdiv, 1499 }; 1500 1501 static struct snd_soc_dai_driver wm8350_dai = { 1502 .name = "wm8350-hifi", 1503 .playback = { 1504 .stream_name = "Playback", 1505 .channels_min = 1, 1506 .channels_max = 2, 1507 .rates = WM8350_RATES, 1508 .formats = WM8350_FORMATS, 1509 }, 1510 .capture = { 1511 .stream_name = "Capture", 1512 .channels_min = 1, 1513 .channels_max = 2, 1514 .rates = WM8350_RATES, 1515 .formats = WM8350_FORMATS, 1516 }, 1517 .ops = &wm8350_dai_ops, 1518 }; 1519 1520 static int wm8350_codec_probe(struct snd_soc_codec *codec) 1521 { 1522 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1523 struct wm8350_data *priv; 1524 struct wm8350_output *out1; 1525 struct wm8350_output *out2; 1526 int ret, i; 1527 1528 if (wm8350->codec.platform_data == NULL) { 1529 dev_err(codec->dev, "No audio platform data supplied\n"); 1530 return -EINVAL; 1531 } 1532 1533 priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data), 1534 GFP_KERNEL); 1535 if (priv == NULL) 1536 return -ENOMEM; 1537 snd_soc_codec_set_drvdata(codec, priv); 1538 1539 priv->wm8350 = wm8350; 1540 1541 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1542 priv->supplies[i].supply = supply_names[i]; 1543 1544 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), 1545 priv->supplies); 1546 if (ret != 0) 1547 return ret; 1548 1549 codec->control_data = wm8350; 1550 1551 /* Put the codec into reset if it wasn't already */ 1552 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1553 1554 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); 1555 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work); 1556 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work); 1557 1558 /* Enable the codec */ 1559 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1560 1561 /* Enable robust clocking mode in ADC */ 1562 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7); 1563 wm8350_codec_write(codec, 0xde, 0x13); 1564 wm8350_codec_write(codec, WM8350_SECURITY, 0); 1565 1566 /* read OUT1 & OUT2 volumes */ 1567 out1 = &priv->out1; 1568 out2 = &priv->out2; 1569 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & 1570 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1571 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & 1572 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1573 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & 1574 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1575 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & 1576 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1577 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); 1578 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); 1579 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); 1580 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); 1581 1582 /* Latch VU bits & mute */ 1583 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, 1584 WM8350_OUT1_VU | WM8350_OUT1L_MUTE); 1585 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, 1586 WM8350_OUT2_VU | WM8350_OUT2L_MUTE); 1587 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, 1588 WM8350_OUT1_VU | WM8350_OUT1R_MUTE); 1589 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, 1590 WM8350_OUT2_VU | WM8350_OUT2R_MUTE); 1591 1592 /* Make sure AIF tristating is disabled by default */ 1593 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI); 1594 1595 /* Make sure we've got a sane companding setup too */ 1596 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP, 1597 WM8350_DAC_COMP | WM8350_LOOPBACK); 1598 1599 /* Make sure jack detect is disabled to start off with */ 1600 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1601 WM8350_JDL_ENA | WM8350_JDR_ENA); 1602 1603 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, 1604 wm8350_hp_jack_handler, 0, "Left jack detect", 1605 priv); 1606 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, 1607 wm8350_hp_jack_handler, 0, "Right jack detect", 1608 priv); 1609 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, 1610 wm8350_mic_handler, 0, "Microphone short", priv); 1611 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD, 1612 wm8350_mic_handler, 0, "Microphone detect", priv); 1613 1614 1615 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1616 1617 return 0; 1618 } 1619 1620 static int wm8350_codec_remove(struct snd_soc_codec *codec) 1621 { 1622 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1623 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1624 1625 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1626 WM8350_JDL_ENA | WM8350_JDR_ENA); 1627 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1628 1629 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv); 1630 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv); 1631 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv); 1632 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv); 1633 1634 priv->hpl.jack = NULL; 1635 priv->hpr.jack = NULL; 1636 priv->mic.jack = NULL; 1637 1638 cancel_delayed_work_sync(&priv->hpl.work); 1639 cancel_delayed_work_sync(&priv->hpr.work); 1640 1641 /* if there was any work waiting then we run it now and 1642 * wait for its completion */ 1643 flush_delayed_work_sync(&codec->dapm.delayed_work); 1644 1645 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1646 1647 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1648 1649 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); 1650 1651 return 0; 1652 } 1653 1654 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = { 1655 .probe = wm8350_codec_probe, 1656 .remove = wm8350_codec_remove, 1657 .suspend = wm8350_suspend, 1658 .resume = wm8350_resume, 1659 .read = wm8350_codec_read, 1660 .write = wm8350_codec_write, 1661 .set_bias_level = wm8350_set_bias_level, 1662 1663 .controls = wm8350_snd_controls, 1664 .num_controls = ARRAY_SIZE(wm8350_snd_controls), 1665 .dapm_widgets = wm8350_dapm_widgets, 1666 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets), 1667 .dapm_routes = wm8350_dapm_routes, 1668 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes), 1669 }; 1670 1671 static int __devinit wm8350_probe(struct platform_device *pdev) 1672 { 1673 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350, 1674 &wm8350_dai, 1); 1675 } 1676 1677 static int __devexit wm8350_remove(struct platform_device *pdev) 1678 { 1679 snd_soc_unregister_codec(&pdev->dev); 1680 return 0; 1681 } 1682 1683 static struct platform_driver wm8350_codec_driver = { 1684 .driver = { 1685 .name = "wm8350-codec", 1686 .owner = THIS_MODULE, 1687 }, 1688 .probe = wm8350_probe, 1689 .remove = __devexit_p(wm8350_remove), 1690 }; 1691 1692 module_platform_driver(wm8350_codec_driver); 1693 1694 MODULE_DESCRIPTION("ASoC WM8350 driver"); 1695 MODULE_AUTHOR("Liam Girdwood"); 1696 MODULE_LICENSE("GPL"); 1697 MODULE_ALIAS("platform:wm8350-codec"); 1698