1 /* 2 * wm8350.c -- WM8350 ALSA SoC audio driver 3 * 4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/platform_device.h> 19 #include <linux/mfd/wm8350/audio.h> 20 #include <linux/mfd/wm8350/core.h> 21 #include <linux/regulator/consumer.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "wm8350.h" 31 32 #define WM8350_OUTn_0dB 0x39 33 34 #define WM8350_RAMP_NONE 0 35 #define WM8350_RAMP_UP 1 36 #define WM8350_RAMP_DOWN 2 37 38 /* We only include the analogue supplies here; the digital supplies 39 * need to be available well before this driver can be probed. 40 */ 41 static const char *supply_names[] = { 42 "AVDD", 43 "HPVDD", 44 }; 45 46 struct wm8350_output { 47 u16 active; 48 u16 left_vol; 49 u16 right_vol; 50 u16 ramp; 51 u16 mute; 52 }; 53 54 struct wm8350_jack_data { 55 struct snd_soc_jack *jack; 56 int report; 57 }; 58 59 struct wm8350_data { 60 struct snd_soc_codec codec; 61 struct wm8350_output out1; 62 struct wm8350_output out2; 63 struct wm8350_jack_data hpl; 64 struct wm8350_jack_data hpr; 65 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 66 int fll_freq_out; 67 int fll_freq_in; 68 }; 69 70 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec, 71 unsigned int reg) 72 { 73 struct wm8350 *wm8350 = codec->control_data; 74 return wm8350->reg_cache[reg]; 75 } 76 77 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, 78 unsigned int reg) 79 { 80 struct wm8350 *wm8350 = codec->control_data; 81 return wm8350_reg_read(wm8350, reg); 82 } 83 84 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg, 85 unsigned int value) 86 { 87 struct wm8350 *wm8350 = codec->control_data; 88 return wm8350_reg_write(wm8350, reg, value); 89 } 90 91 /* 92 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. 93 */ 94 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) 95 { 96 struct wm8350_data *wm8350_data = codec->private_data; 97 struct wm8350_output *out1 = &wm8350_data->out1; 98 struct wm8350 *wm8350 = codec->control_data; 99 int left_complete = 0, right_complete = 0; 100 u16 reg, val; 101 102 /* left channel */ 103 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); 104 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 105 106 if (out1->ramp == WM8350_RAMP_UP) { 107 /* ramp step up */ 108 if (val < out1->left_vol) { 109 val++; 110 reg &= ~WM8350_OUT1L_VOL_MASK; 111 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 112 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 113 } else 114 left_complete = 1; 115 } else if (out1->ramp == WM8350_RAMP_DOWN) { 116 /* ramp step down */ 117 if (val > 0) { 118 val--; 119 reg &= ~WM8350_OUT1L_VOL_MASK; 120 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 121 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 122 } else 123 left_complete = 1; 124 } else 125 return 1; 126 127 /* right channel */ 128 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); 129 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 130 if (out1->ramp == WM8350_RAMP_UP) { 131 /* ramp step up */ 132 if (val < out1->right_vol) { 133 val++; 134 reg &= ~WM8350_OUT1R_VOL_MASK; 135 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 136 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 137 } else 138 right_complete = 1; 139 } else if (out1->ramp == WM8350_RAMP_DOWN) { 140 /* ramp step down */ 141 if (val > 0) { 142 val--; 143 reg &= ~WM8350_OUT1R_VOL_MASK; 144 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 145 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 146 } else 147 right_complete = 1; 148 } 149 150 /* only hit the update bit if either volume has changed this step */ 151 if (!left_complete || !right_complete) 152 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); 153 154 return left_complete & right_complete; 155 } 156 157 /* 158 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. 159 */ 160 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) 161 { 162 struct wm8350_data *wm8350_data = codec->private_data; 163 struct wm8350_output *out2 = &wm8350_data->out2; 164 struct wm8350 *wm8350 = codec->control_data; 165 int left_complete = 0, right_complete = 0; 166 u16 reg, val; 167 168 /* left channel */ 169 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); 170 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 171 if (out2->ramp == WM8350_RAMP_UP) { 172 /* ramp step up */ 173 if (val < out2->left_vol) { 174 val++; 175 reg &= ~WM8350_OUT2L_VOL_MASK; 176 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 177 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 178 } else 179 left_complete = 1; 180 } else if (out2->ramp == WM8350_RAMP_DOWN) { 181 /* ramp step down */ 182 if (val > 0) { 183 val--; 184 reg &= ~WM8350_OUT2L_VOL_MASK; 185 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 186 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 187 } else 188 left_complete = 1; 189 } else 190 return 1; 191 192 /* right channel */ 193 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); 194 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 195 if (out2->ramp == WM8350_RAMP_UP) { 196 /* ramp step up */ 197 if (val < out2->right_vol) { 198 val++; 199 reg &= ~WM8350_OUT2R_VOL_MASK; 200 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 201 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 202 } else 203 right_complete = 1; 204 } else if (out2->ramp == WM8350_RAMP_DOWN) { 205 /* ramp step down */ 206 if (val > 0) { 207 val--; 208 reg &= ~WM8350_OUT2R_VOL_MASK; 209 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 210 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 211 } else 212 right_complete = 1; 213 } 214 215 /* only hit the update bit if either volume has changed this step */ 216 if (!left_complete || !right_complete) 217 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); 218 219 return left_complete & right_complete; 220 } 221 222 /* 223 * This work ramps both output PGAs at stream start/stop time to 224 * minimise pop associated with DAPM power switching. 225 * It's best to enable Zero Cross when ramping occurs to minimise any 226 * zipper noises. 227 */ 228 static void wm8350_pga_work(struct work_struct *work) 229 { 230 struct snd_soc_codec *codec = 231 container_of(work, struct snd_soc_codec, delayed_work.work); 232 struct wm8350_data *wm8350_data = codec->private_data; 233 struct wm8350_output *out1 = &wm8350_data->out1, 234 *out2 = &wm8350_data->out2; 235 int i, out1_complete, out2_complete; 236 237 /* do we need to ramp at all ? */ 238 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) 239 return; 240 241 /* PGA volumes have 6 bits of resolution to ramp */ 242 for (i = 0; i <= 63; i++) { 243 out1_complete = 1, out2_complete = 1; 244 if (out1->ramp != WM8350_RAMP_NONE) 245 out1_complete = wm8350_out1_ramp_step(codec); 246 if (out2->ramp != WM8350_RAMP_NONE) 247 out2_complete = wm8350_out2_ramp_step(codec); 248 249 /* ramp finished ? */ 250 if (out1_complete && out2_complete) 251 break; 252 253 /* we need to delay longer on the up ramp */ 254 if (out1->ramp == WM8350_RAMP_UP || 255 out2->ramp == WM8350_RAMP_UP) { 256 /* delay is longer over 0dB as increases are larger */ 257 if (i >= WM8350_OUTn_0dB) 258 schedule_timeout_interruptible(msecs_to_jiffies 259 (2)); 260 else 261 schedule_timeout_interruptible(msecs_to_jiffies 262 (1)); 263 } else 264 udelay(50); /* doesn't matter if we delay longer */ 265 } 266 267 out1->ramp = WM8350_RAMP_NONE; 268 out2->ramp = WM8350_RAMP_NONE; 269 } 270 271 /* 272 * WM8350 Controls 273 */ 274 275 static int pga_event(struct snd_soc_dapm_widget *w, 276 struct snd_kcontrol *kcontrol, int event) 277 { 278 struct snd_soc_codec *codec = w->codec; 279 struct wm8350_data *wm8350_data = codec->private_data; 280 struct wm8350_output *out; 281 282 switch (w->shift) { 283 case 0: 284 case 1: 285 out = &wm8350_data->out1; 286 break; 287 case 2: 288 case 3: 289 out = &wm8350_data->out2; 290 break; 291 292 default: 293 BUG(); 294 return -1; 295 } 296 297 switch (event) { 298 case SND_SOC_DAPM_POST_PMU: 299 out->ramp = WM8350_RAMP_UP; 300 out->active = 1; 301 302 if (!delayed_work_pending(&codec->delayed_work)) 303 schedule_delayed_work(&codec->delayed_work, 304 msecs_to_jiffies(1)); 305 break; 306 307 case SND_SOC_DAPM_PRE_PMD: 308 out->ramp = WM8350_RAMP_DOWN; 309 out->active = 0; 310 311 if (!delayed_work_pending(&codec->delayed_work)) 312 schedule_delayed_work(&codec->delayed_work, 313 msecs_to_jiffies(1)); 314 break; 315 } 316 317 return 0; 318 } 319 320 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, 321 struct snd_ctl_elem_value *ucontrol) 322 { 323 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 324 struct wm8350_data *wm8350_priv = codec->private_data; 325 struct wm8350_output *out = NULL; 326 struct soc_mixer_control *mc = 327 (struct soc_mixer_control *)kcontrol->private_value; 328 int ret; 329 unsigned int reg = mc->reg; 330 u16 val; 331 332 /* For OUT1 and OUT2 we shadow the values and only actually write 333 * them out when active in order to ensure the amplifier comes on 334 * as quietly as possible. */ 335 switch (reg) { 336 case WM8350_LOUT1_VOLUME: 337 out = &wm8350_priv->out1; 338 break; 339 case WM8350_LOUT2_VOLUME: 340 out = &wm8350_priv->out2; 341 break; 342 default: 343 break; 344 } 345 346 if (out) { 347 out->left_vol = ucontrol->value.integer.value[0]; 348 out->right_vol = ucontrol->value.integer.value[1]; 349 if (!out->active) 350 return 1; 351 } 352 353 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); 354 if (ret < 0) 355 return ret; 356 357 /* now hit the volume update bits (always bit 8) */ 358 val = wm8350_codec_read(codec, reg); 359 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU); 360 return 1; 361 } 362 363 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, 364 struct snd_ctl_elem_value *ucontrol) 365 { 366 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 367 struct wm8350_data *wm8350_priv = codec->private_data; 368 struct wm8350_output *out1 = &wm8350_priv->out1; 369 struct wm8350_output *out2 = &wm8350_priv->out2; 370 struct soc_mixer_control *mc = 371 (struct soc_mixer_control *)kcontrol->private_value; 372 unsigned int reg = mc->reg; 373 374 /* If these are cached registers use the cache */ 375 switch (reg) { 376 case WM8350_LOUT1_VOLUME: 377 ucontrol->value.integer.value[0] = out1->left_vol; 378 ucontrol->value.integer.value[1] = out1->right_vol; 379 return 0; 380 381 case WM8350_LOUT2_VOLUME: 382 ucontrol->value.integer.value[0] = out2->left_vol; 383 ucontrol->value.integer.value[1] = out2->right_vol; 384 return 0; 385 386 default: 387 break; 388 } 389 390 return snd_soc_get_volsw_2r(kcontrol, ucontrol); 391 } 392 393 /* double control with volume update */ 394 #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \ 395 xinvert, tlv_array) \ 396 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 397 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 398 SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 399 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 400 .tlv.p = (tlv_array), \ 401 .info = snd_soc_info_volsw_2r, \ 402 .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \ 403 .private_value = (unsigned long)&(struct soc_mixer_control) \ 404 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ 405 .rshift = xshift, .max = xmax, .invert = xinvert}, } 406 407 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; 408 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; 409 static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; 410 static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; 411 static const char *wm8350_adcfilter[] = { "None", "High Pass" }; 412 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; 413 static const char *wm8350_lr[] = { "Left", "Right" }; 414 415 static const struct soc_enum wm8350_enum[] = { 416 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), 417 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), 418 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), 419 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), 420 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), 421 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), 422 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), 423 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), 424 }; 425 426 static DECLARE_TLV_DB_LINEAR(pre_amp_tlv, -1200, 3525); 427 static DECLARE_TLV_DB_LINEAR(out_pga_tlv, -5700, 600); 428 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); 429 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); 430 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); 431 432 static const unsigned int capture_sd_tlv[] = { 433 TLV_DB_RANGE_HEAD(2), 434 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), 435 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), 436 }; 437 438 static const struct snd_kcontrol_new wm8350_snd_controls[] = { 439 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), 440 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), 441 SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume", 442 WM8350_DAC_DIGITAL_VOLUME_L, 443 WM8350_DAC_DIGITAL_VOLUME_R, 444 0, 255, 0, dac_pcm_tlv), 445 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), 446 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), 447 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]), 448 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]), 449 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]), 450 SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume", 451 WM8350_ADC_DIGITAL_VOLUME_L, 452 WM8350_ADC_DIGITAL_VOLUME_R, 453 0, 255, 0, adc_pcm_tlv), 454 SOC_DOUBLE_TLV("Capture Sidetone Volume", 455 WM8350_ADC_DIVIDER, 456 8, 4, 15, 1, capture_sd_tlv), 457 SOC_WM8350_DOUBLE_R_TLV("Capture Volume", 458 WM8350_LEFT_INPUT_VOLUME, 459 WM8350_RIGHT_INPUT_VOLUME, 460 2, 63, 0, pre_amp_tlv), 461 SOC_DOUBLE_R("Capture ZC Switch", 462 WM8350_LEFT_INPUT_VOLUME, 463 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), 464 SOC_SINGLE_TLV("Left Input Left Sidetone Volume", 465 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), 466 SOC_SINGLE_TLV("Left Input Right Sidetone Volume", 467 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 468 5, 7, 0, out_mix_tlv), 469 SOC_SINGLE_TLV("Left Input Bypass Volume", 470 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 471 9, 7, 0, out_mix_tlv), 472 SOC_SINGLE_TLV("Right Input Left Sidetone Volume", 473 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 474 1, 7, 0, out_mix_tlv), 475 SOC_SINGLE_TLV("Right Input Right Sidetone Volume", 476 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 477 5, 7, 0, out_mix_tlv), 478 SOC_SINGLE_TLV("Right Input Bypass Volume", 479 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 480 13, 7, 0, out_mix_tlv), 481 SOC_SINGLE("Left Input Mixer +20dB Switch", 482 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), 483 SOC_SINGLE("Right Input Mixer +20dB Switch", 484 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), 485 SOC_SINGLE_TLV("Out4 Capture Volume", 486 WM8350_INPUT_MIXER_VOLUME, 487 1, 7, 0, out_mix_tlv), 488 SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume", 489 WM8350_LOUT1_VOLUME, 490 WM8350_ROUT1_VOLUME, 491 2, 63, 0, out_pga_tlv), 492 SOC_DOUBLE_R("Out1 Playback ZC Switch", 493 WM8350_LOUT1_VOLUME, 494 WM8350_ROUT1_VOLUME, 13, 1, 0), 495 SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume", 496 WM8350_LOUT2_VOLUME, 497 WM8350_ROUT2_VOLUME, 498 2, 63, 0, out_pga_tlv), 499 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, 500 WM8350_ROUT2_VOLUME, 13, 1, 0), 501 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), 502 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, 503 5, 7, 0, out_mix_tlv), 504 505 SOC_DOUBLE_R("Out1 Playback Switch", 506 WM8350_LOUT1_VOLUME, 507 WM8350_ROUT1_VOLUME, 508 14, 1, 1), 509 SOC_DOUBLE_R("Out2 Playback Switch", 510 WM8350_LOUT2_VOLUME, 511 WM8350_ROUT2_VOLUME, 512 14, 1, 1), 513 }; 514 515 /* 516 * DAPM Controls 517 */ 518 519 /* Left Playback Mixer */ 520 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { 521 SOC_DAPM_SINGLE("Playback Switch", 522 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), 523 SOC_DAPM_SINGLE("Left Bypass Switch", 524 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), 525 SOC_DAPM_SINGLE("Right Playback Switch", 526 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), 527 SOC_DAPM_SINGLE("Left Sidetone Switch", 528 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), 529 SOC_DAPM_SINGLE("Right Sidetone Switch", 530 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), 531 }; 532 533 /* Right Playback Mixer */ 534 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { 535 SOC_DAPM_SINGLE("Playback Switch", 536 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), 537 SOC_DAPM_SINGLE("Right Bypass Switch", 538 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), 539 SOC_DAPM_SINGLE("Left Playback Switch", 540 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), 541 SOC_DAPM_SINGLE("Left Sidetone Switch", 542 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), 543 SOC_DAPM_SINGLE("Right Sidetone Switch", 544 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), 545 }; 546 547 /* Out4 Mixer */ 548 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { 549 SOC_DAPM_SINGLE("Right Playback Switch", 550 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), 551 SOC_DAPM_SINGLE("Left Playback Switch", 552 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), 553 SOC_DAPM_SINGLE("Right Capture Switch", 554 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), 555 SOC_DAPM_SINGLE("Out3 Playback Switch", 556 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), 557 SOC_DAPM_SINGLE("Right Mixer Switch", 558 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), 559 SOC_DAPM_SINGLE("Left Mixer Switch", 560 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), 561 }; 562 563 /* Out3 Mixer */ 564 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { 565 SOC_DAPM_SINGLE("Left Playback Switch", 566 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), 567 SOC_DAPM_SINGLE("Left Capture Switch", 568 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), 569 SOC_DAPM_SINGLE("Out4 Playback Switch", 570 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), 571 SOC_DAPM_SINGLE("Left Mixer Switch", 572 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), 573 }; 574 575 /* Left Input Mixer */ 576 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { 577 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 578 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), 579 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 580 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), 581 SOC_DAPM_SINGLE("PGA Capture Switch", 582 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1), 583 }; 584 585 /* Right Input Mixer */ 586 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { 587 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 588 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), 589 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 590 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), 591 SOC_DAPM_SINGLE("PGA Capture Switch", 592 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1), 593 }; 594 595 /* Left Mic Mixer */ 596 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { 597 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), 598 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), 599 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), 600 }; 601 602 /* Right Mic Mixer */ 603 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { 604 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), 605 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), 606 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), 607 }; 608 609 /* Beep Switch */ 610 static const struct snd_kcontrol_new wm8350_beep_switch_controls = 611 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); 612 613 /* Out4 Capture Mux */ 614 static const struct snd_kcontrol_new wm8350_out4_capture_controls = 615 SOC_DAPM_ENUM("Route", wm8350_enum[7]); 616 617 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { 618 619 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), 620 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), 621 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, 622 0, pga_event, 623 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 624 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, 625 pga_event, 626 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 627 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, 628 0, pga_event, 629 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 630 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, 631 pga_event, 632 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 633 634 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, 635 7, 0, &wm8350_right_capt_mixer_controls[0], 636 ARRAY_SIZE(wm8350_right_capt_mixer_controls)), 637 638 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, 639 6, 0, &wm8350_left_capt_mixer_controls[0], 640 ARRAY_SIZE(wm8350_left_capt_mixer_controls)), 641 642 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, 643 &wm8350_out4_mixer_controls[0], 644 ARRAY_SIZE(wm8350_out4_mixer_controls)), 645 646 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, 647 &wm8350_out3_mixer_controls[0], 648 ARRAY_SIZE(wm8350_out3_mixer_controls)), 649 650 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, 651 &wm8350_right_play_mixer_controls[0], 652 ARRAY_SIZE(wm8350_right_play_mixer_controls)), 653 654 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, 655 &wm8350_left_play_mixer_controls[0], 656 ARRAY_SIZE(wm8350_left_play_mixer_controls)), 657 658 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, 659 &wm8350_left_mic_mixer_controls[0], 660 ARRAY_SIZE(wm8350_left_mic_mixer_controls)), 661 662 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, 663 &wm8350_right_mic_mixer_controls[0], 664 ARRAY_SIZE(wm8350_right_mic_mixer_controls)), 665 666 /* virtual mixer for Beep and Out2R */ 667 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 668 669 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, 670 &wm8350_beep_switch_controls), 671 672 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 673 WM8350_POWER_MGMT_4, 3, 0), 674 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", 675 WM8350_POWER_MGMT_4, 2, 0), 676 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", 677 WM8350_POWER_MGMT_4, 5, 0), 678 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 679 WM8350_POWER_MGMT_4, 4, 0), 680 681 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), 682 683 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, 684 &wm8350_out4_capture_controls), 685 686 SND_SOC_DAPM_OUTPUT("OUT1R"), 687 SND_SOC_DAPM_OUTPUT("OUT1L"), 688 SND_SOC_DAPM_OUTPUT("OUT2R"), 689 SND_SOC_DAPM_OUTPUT("OUT2L"), 690 SND_SOC_DAPM_OUTPUT("OUT3"), 691 SND_SOC_DAPM_OUTPUT("OUT4"), 692 693 SND_SOC_DAPM_INPUT("IN1RN"), 694 SND_SOC_DAPM_INPUT("IN1RP"), 695 SND_SOC_DAPM_INPUT("IN2R"), 696 SND_SOC_DAPM_INPUT("IN1LP"), 697 SND_SOC_DAPM_INPUT("IN1LN"), 698 SND_SOC_DAPM_INPUT("IN2L"), 699 SND_SOC_DAPM_INPUT("IN3R"), 700 SND_SOC_DAPM_INPUT("IN3L"), 701 }; 702 703 static const struct snd_soc_dapm_route audio_map[] = { 704 705 /* left playback mixer */ 706 {"Left Playback Mixer", "Playback Switch", "Left DAC"}, 707 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, 708 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, 709 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 710 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 711 712 /* right playback mixer */ 713 {"Right Playback Mixer", "Playback Switch", "Right DAC"}, 714 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, 715 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, 716 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 717 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 718 719 /* out4 playback mixer */ 720 {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, 721 {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, 722 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, 723 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, 724 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, 725 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 726 {"OUT4", NULL, "Out4 Mixer"}, 727 728 /* out3 playback mixer */ 729 {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, 730 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, 731 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 732 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, 733 {"OUT3", NULL, "Out3 Mixer"}, 734 735 /* out2 */ 736 {"Right Out2 PGA", NULL, "Right Playback Mixer"}, 737 {"Left Out2 PGA", NULL, "Left Playback Mixer"}, 738 {"OUT2L", NULL, "Left Out2 PGA"}, 739 {"OUT2R", NULL, "Right Out2 PGA"}, 740 741 /* out1 */ 742 {"Right Out1 PGA", NULL, "Right Playback Mixer"}, 743 {"Left Out1 PGA", NULL, "Left Playback Mixer"}, 744 {"OUT1L", NULL, "Left Out1 PGA"}, 745 {"OUT1R", NULL, "Right Out1 PGA"}, 746 747 /* ADCs */ 748 {"Left ADC", NULL, "Left Capture Mixer"}, 749 {"Right ADC", NULL, "Right Capture Mixer"}, 750 751 /* Left capture mixer */ 752 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, 753 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, 754 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, 755 {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, 756 757 /* Right capture mixer */ 758 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, 759 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, 760 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, 761 {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, 762 763 /* L3 Inputs */ 764 {"IN3L PGA", NULL, "IN3L"}, 765 {"IN3R PGA", NULL, "IN3R"}, 766 767 /* Left Mic mixer */ 768 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, 769 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, 770 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, 771 772 /* Right Mic mixer */ 773 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, 774 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, 775 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, 776 777 /* out 4 capture */ 778 {"Out4 Capture Channel", NULL, "Out4 Mixer"}, 779 780 /* Beep */ 781 {"Beep", NULL, "IN3R PGA"}, 782 }; 783 784 static int wm8350_add_widgets(struct snd_soc_codec *codec) 785 { 786 int ret; 787 788 ret = snd_soc_dapm_new_controls(codec, 789 wm8350_dapm_widgets, 790 ARRAY_SIZE(wm8350_dapm_widgets)); 791 if (ret != 0) { 792 dev_err(codec->dev, "dapm control register failed\n"); 793 return ret; 794 } 795 796 /* set up audio paths */ 797 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 798 if (ret != 0) { 799 dev_err(codec->dev, "DAPM route register failed\n"); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, 807 int clk_id, unsigned int freq, int dir) 808 { 809 struct snd_soc_codec *codec = codec_dai->codec; 810 struct wm8350 *wm8350 = codec->control_data; 811 u16 fll_4; 812 813 switch (clk_id) { 814 case WM8350_MCLK_SEL_MCLK: 815 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, 816 WM8350_MCLK_SEL); 817 break; 818 case WM8350_MCLK_SEL_PLL_MCLK: 819 case WM8350_MCLK_SEL_PLL_DAC: 820 case WM8350_MCLK_SEL_PLL_ADC: 821 case WM8350_MCLK_SEL_PLL_32K: 822 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, 823 WM8350_MCLK_SEL); 824 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 825 ~WM8350_FLL_CLK_SRC_MASK; 826 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); 827 break; 828 } 829 830 /* MCLK direction */ 831 if (dir == WM8350_MCLK_DIR_OUT) 832 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, 833 WM8350_MCLK_DIR); 834 else 835 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, 836 WM8350_MCLK_DIR); 837 838 return 0; 839 } 840 841 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) 842 { 843 struct snd_soc_codec *codec = codec_dai->codec; 844 u16 val; 845 846 switch (div_id) { 847 case WM8350_ADC_CLKDIV: 848 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) & 849 ~WM8350_ADC_CLKDIV_MASK; 850 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div); 851 break; 852 case WM8350_DAC_CLKDIV: 853 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) & 854 ~WM8350_DAC_CLKDIV_MASK; 855 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); 856 break; 857 case WM8350_BCLK_CLKDIV: 858 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 859 ~WM8350_BCLK_DIV_MASK; 860 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 861 break; 862 case WM8350_OPCLK_CLKDIV: 863 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 864 ~WM8350_OPCLK_DIV_MASK; 865 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 866 break; 867 case WM8350_SYS_CLKDIV: 868 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 869 ~WM8350_MCLK_DIV_MASK; 870 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 871 break; 872 case WM8350_DACLR_CLKDIV: 873 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 874 ~WM8350_DACLRC_RATE_MASK; 875 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div); 876 break; 877 case WM8350_ADCLR_CLKDIV: 878 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 879 ~WM8350_ADCLRC_RATE_MASK; 880 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div); 881 break; 882 default: 883 return -EINVAL; 884 } 885 886 return 0; 887 } 888 889 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 890 { 891 struct snd_soc_codec *codec = codec_dai->codec; 892 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 893 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); 894 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) & 895 ~WM8350_BCLK_MSTR; 896 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 897 ~WM8350_DACLRC_ENA; 898 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 899 ~WM8350_ADCLRC_ENA; 900 901 /* set master/slave audio interface */ 902 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 903 case SND_SOC_DAIFMT_CBM_CFM: 904 master |= WM8350_BCLK_MSTR; 905 dac_lrc |= WM8350_DACLRC_ENA; 906 adc_lrc |= WM8350_ADCLRC_ENA; 907 break; 908 case SND_SOC_DAIFMT_CBS_CFS: 909 break; 910 default: 911 return -EINVAL; 912 } 913 914 /* interface format */ 915 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 916 case SND_SOC_DAIFMT_I2S: 917 iface |= 0x2 << 8; 918 break; 919 case SND_SOC_DAIFMT_RIGHT_J: 920 break; 921 case SND_SOC_DAIFMT_LEFT_J: 922 iface |= 0x1 << 8; 923 break; 924 case SND_SOC_DAIFMT_DSP_A: 925 iface |= 0x3 << 8; 926 break; 927 case SND_SOC_DAIFMT_DSP_B: 928 iface |= 0x3 << 8; /* lg not sure which mode */ 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 /* clock inversion */ 935 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 936 case SND_SOC_DAIFMT_NB_NF: 937 break; 938 case SND_SOC_DAIFMT_IB_IF: 939 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; 940 break; 941 case SND_SOC_DAIFMT_IB_NF: 942 iface |= WM8350_AIF_BCLK_INV; 943 break; 944 case SND_SOC_DAIFMT_NB_IF: 945 iface |= WM8350_AIF_LRCLK_INV; 946 break; 947 default: 948 return -EINVAL; 949 } 950 951 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 952 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master); 953 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc); 954 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc); 955 return 0; 956 } 957 958 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream, 959 int cmd, struct snd_soc_dai *codec_dai) 960 { 961 struct snd_soc_codec *codec = codec_dai->codec; 962 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) & 963 WM8350_BCLK_MSTR; 964 int enabled = 0; 965 966 /* Check that the DACs or ADCs are enabled since they are 967 * required for LRC in master mode. The DACs or ADCs need a 968 * valid audio path i.e. pin -> ADC or DAC -> pin before 969 * the LRC will be enabled in master mode. */ 970 if (!master || cmd != SNDRV_PCM_TRIGGER_START) 971 return 0; 972 973 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 974 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & 975 (WM8350_ADCR_ENA | WM8350_ADCL_ENA); 976 } else { 977 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & 978 (WM8350_DACR_ENA | WM8350_DACL_ENA); 979 } 980 981 if (!enabled) { 982 dev_err(codec->dev, 983 "%s: invalid audio path - no clocks available\n", 984 __func__); 985 return -EINVAL; 986 } 987 return 0; 988 } 989 990 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, 991 struct snd_pcm_hw_params *params, 992 struct snd_soc_dai *codec_dai) 993 { 994 struct snd_soc_codec *codec = codec_dai->codec; 995 struct wm8350 *wm8350 = codec->control_data; 996 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 997 ~WM8350_AIF_WL_MASK; 998 999 /* bit size */ 1000 switch (params_format(params)) { 1001 case SNDRV_PCM_FORMAT_S16_LE: 1002 break; 1003 case SNDRV_PCM_FORMAT_S20_3LE: 1004 iface |= 0x1 << 10; 1005 break; 1006 case SNDRV_PCM_FORMAT_S24_LE: 1007 iface |= 0x2 << 10; 1008 break; 1009 case SNDRV_PCM_FORMAT_S32_LE: 1010 iface |= 0x3 << 10; 1011 break; 1012 } 1013 1014 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 1015 1016 /* The sloping stopband filter is recommended for use with 1017 * lower sample rates to improve performance. 1018 */ 1019 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1020 if (params_rate(params) < 24000) 1021 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 1022 WM8350_DAC_SB_FILT); 1023 else 1024 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 1025 WM8350_DAC_SB_FILT); 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int wm8350_mute(struct snd_soc_dai *dai, int mute) 1032 { 1033 struct snd_soc_codec *codec = dai->codec; 1034 struct wm8350 *wm8350 = codec->control_data; 1035 1036 if (mute) 1037 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1038 else 1039 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1040 return 0; 1041 } 1042 1043 /* FLL divisors */ 1044 struct _fll_div { 1045 int div; /* FLL_OUTDIV */ 1046 int n; 1047 int k; 1048 int ratio; /* FLL_FRATIO */ 1049 }; 1050 1051 /* The size in bits of the fll divide multiplied by 10 1052 * to allow rounding later */ 1053 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1054 1055 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, 1056 unsigned int output) 1057 { 1058 u64 Kpart; 1059 unsigned int t1, t2, K, Nmod; 1060 1061 if (output >= 2815250 && output <= 3125000) 1062 fll_div->div = 0x4; 1063 else if (output >= 5625000 && output <= 6250000) 1064 fll_div->div = 0x3; 1065 else if (output >= 11250000 && output <= 12500000) 1066 fll_div->div = 0x2; 1067 else if (output >= 22500000 && output <= 25000000) 1068 fll_div->div = 0x1; 1069 else { 1070 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); 1071 return -EINVAL; 1072 } 1073 1074 if (input > 48000) 1075 fll_div->ratio = 1; 1076 else 1077 fll_div->ratio = 8; 1078 1079 t1 = output * (1 << (fll_div->div + 1)); 1080 t2 = input * fll_div->ratio; 1081 1082 fll_div->n = t1 / t2; 1083 Nmod = t1 % t2; 1084 1085 if (Nmod) { 1086 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1087 do_div(Kpart, t2); 1088 K = Kpart & 0xFFFFFFFF; 1089 1090 /* Check if we need to round */ 1091 if ((K % 10) >= 5) 1092 K += 5; 1093 1094 /* Move down to proper range now rounding is done */ 1095 K /= 10; 1096 fll_div->k = K; 1097 } else 1098 fll_div->k = 0; 1099 1100 return 0; 1101 } 1102 1103 static int wm8350_set_fll(struct snd_soc_dai *codec_dai, 1104 int pll_id, int source, unsigned int freq_in, 1105 unsigned int freq_out) 1106 { 1107 struct snd_soc_codec *codec = codec_dai->codec; 1108 struct wm8350 *wm8350 = codec->control_data; 1109 struct wm8350_data *priv = codec->private_data; 1110 struct _fll_div fll_div; 1111 int ret = 0; 1112 u16 fll_1, fll_4; 1113 1114 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out) 1115 return 0; 1116 1117 /* power down FLL - we need to do this for reconfiguration */ 1118 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1119 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); 1120 1121 if (freq_out == 0 || freq_in == 0) 1122 return ret; 1123 1124 ret = fll_factors(&fll_div, freq_in, freq_out); 1125 if (ret < 0) 1126 return ret; 1127 dev_dbg(wm8350->dev, 1128 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", 1129 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, 1130 fll_div.ratio); 1131 1132 /* set up N.K & dividers */ 1133 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & 1134 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); 1135 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, 1136 fll_1 | (fll_div.div << 8) | 0x50); 1137 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, 1138 (fll_div.ratio << 11) | (fll_div. 1139 n & WM8350_FLL_N_MASK)); 1140 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); 1141 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 1142 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); 1143 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, 1144 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | 1145 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); 1146 1147 /* power FLL on */ 1148 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); 1149 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); 1150 1151 priv->fll_freq_out = freq_out; 1152 priv->fll_freq_in = freq_in; 1153 1154 return 0; 1155 } 1156 1157 static int wm8350_set_bias_level(struct snd_soc_codec *codec, 1158 enum snd_soc_bias_level level) 1159 { 1160 struct wm8350 *wm8350 = codec->control_data; 1161 struct wm8350_data *priv = codec->private_data; 1162 struct wm8350_audio_platform_data *platform = 1163 wm8350->codec.platform_data; 1164 u16 pm1; 1165 int ret; 1166 1167 switch (level) { 1168 case SND_SOC_BIAS_ON: 1169 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1170 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1171 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1172 pm1 | WM8350_VMID_50K | 1173 platform->codec_current_on << 14); 1174 break; 1175 1176 case SND_SOC_BIAS_PREPARE: 1177 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); 1178 pm1 &= ~WM8350_VMID_MASK; 1179 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1180 pm1 | WM8350_VMID_50K); 1181 break; 1182 1183 case SND_SOC_BIAS_STANDBY: 1184 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1185 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), 1186 priv->supplies); 1187 if (ret != 0) 1188 return ret; 1189 1190 /* Enable the system clock */ 1191 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, 1192 WM8350_SYSCLK_ENA); 1193 1194 /* mute DAC & outputs */ 1195 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, 1196 WM8350_DAC_MUTE_ENA); 1197 1198 /* discharge cap memory */ 1199 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1200 platform->dis_out1 | 1201 (platform->dis_out2 << 2) | 1202 (platform->dis_out3 << 4) | 1203 (platform->dis_out4 << 6)); 1204 1205 /* wait for discharge */ 1206 schedule_timeout_interruptible(msecs_to_jiffies 1207 (platform-> 1208 cap_discharge_msecs)); 1209 1210 /* enable antipop */ 1211 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1212 (platform->vmid_s_curve << 8)); 1213 1214 /* ramp up vmid */ 1215 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1216 (platform-> 1217 codec_current_charge << 14) | 1218 WM8350_VMID_5K | WM8350_VMIDEN | 1219 WM8350_VBUFEN); 1220 1221 /* wait for vmid */ 1222 schedule_timeout_interruptible(msecs_to_jiffies 1223 (platform-> 1224 vmid_charge_msecs)); 1225 1226 /* turn on vmid 300k */ 1227 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1228 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1229 pm1 |= WM8350_VMID_300K | 1230 (platform->codec_current_standby << 14); 1231 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1232 pm1); 1233 1234 1235 /* enable analogue bias */ 1236 pm1 |= WM8350_BIASEN; 1237 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1238 1239 /* disable antipop */ 1240 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1241 1242 } else { 1243 /* turn on vmid 300k and reduce current */ 1244 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1245 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1246 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1247 pm1 | WM8350_VMID_300K | 1248 (platform-> 1249 codec_current_standby << 14)); 1250 1251 } 1252 break; 1253 1254 case SND_SOC_BIAS_OFF: 1255 1256 /* mute DAC & enable outputs */ 1257 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1258 1259 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, 1260 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | 1261 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); 1262 1263 /* enable anti pop S curve */ 1264 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1265 (platform->vmid_s_curve << 8)); 1266 1267 /* turn off vmid */ 1268 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1269 ~WM8350_VMIDEN; 1270 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1271 1272 /* wait */ 1273 schedule_timeout_interruptible(msecs_to_jiffies 1274 (platform-> 1275 vmid_discharge_msecs)); 1276 1277 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1278 (platform->vmid_s_curve << 8) | 1279 platform->dis_out1 | 1280 (platform->dis_out2 << 2) | 1281 (platform->dis_out3 << 4) | 1282 (platform->dis_out4 << 6)); 1283 1284 /* turn off VBuf and drain */ 1285 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1286 ~(WM8350_VBUFEN | WM8350_VMID_MASK); 1287 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1288 pm1 | WM8350_OUTPUT_DRAIN_EN); 1289 1290 /* wait */ 1291 schedule_timeout_interruptible(msecs_to_jiffies 1292 (platform->drain_msecs)); 1293 1294 pm1 &= ~WM8350_BIASEN; 1295 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1296 1297 /* disable anti-pop */ 1298 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1299 1300 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, 1301 WM8350_OUT1L_ENA); 1302 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, 1303 WM8350_OUT1R_ENA); 1304 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, 1305 WM8350_OUT2L_ENA); 1306 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, 1307 WM8350_OUT2R_ENA); 1308 1309 /* disable clock gen */ 1310 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1311 WM8350_SYSCLK_ENA); 1312 1313 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 1314 priv->supplies); 1315 break; 1316 } 1317 codec->bias_level = level; 1318 return 0; 1319 } 1320 1321 static int wm8350_suspend(struct platform_device *pdev, pm_message_t state) 1322 { 1323 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1324 struct snd_soc_codec *codec = socdev->card->codec; 1325 1326 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1327 return 0; 1328 } 1329 1330 static int wm8350_resume(struct platform_device *pdev) 1331 { 1332 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1333 struct snd_soc_codec *codec = socdev->card->codec; 1334 1335 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1336 1337 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) 1338 wm8350_set_bias_level(codec, SND_SOC_BIAS_ON); 1339 1340 return 0; 1341 } 1342 1343 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1344 { 1345 struct wm8350_data *priv = data; 1346 struct wm8350 *wm8350 = priv->codec.control_data; 1347 u16 reg; 1348 int report; 1349 int mask; 1350 struct wm8350_jack_data *jack = NULL; 1351 1352 switch (irq) { 1353 case WM8350_IRQ_CODEC_JCK_DET_L: 1354 jack = &priv->hpl; 1355 mask = WM8350_JACK_L_LVL; 1356 break; 1357 1358 case WM8350_IRQ_CODEC_JCK_DET_R: 1359 jack = &priv->hpr; 1360 mask = WM8350_JACK_R_LVL; 1361 break; 1362 1363 default: 1364 BUG(); 1365 } 1366 1367 if (!jack->jack) { 1368 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); 1369 return IRQ_NONE; 1370 } 1371 1372 /* Debounce */ 1373 msleep(200); 1374 1375 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1376 if (reg & mask) 1377 report = jack->report; 1378 else 1379 report = 0; 1380 1381 snd_soc_jack_report(jack->jack, report, jack->report); 1382 1383 return IRQ_HANDLED; 1384 } 1385 1386 /** 1387 * wm8350_hp_jack_detect - Enable headphone jack detection. 1388 * 1389 * @codec: WM8350 codec 1390 * @which: left or right jack detect signal 1391 * @jack: jack to report detection events on 1392 * @report: value to report 1393 * 1394 * Enables the headphone jack detection of the WM8350. 1395 */ 1396 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, 1397 struct snd_soc_jack *jack, int report) 1398 { 1399 struct wm8350_data *priv = codec->private_data; 1400 struct wm8350 *wm8350 = codec->control_data; 1401 int irq; 1402 int ena; 1403 1404 switch (which) { 1405 case WM8350_JDL: 1406 priv->hpl.jack = jack; 1407 priv->hpl.report = report; 1408 irq = WM8350_IRQ_CODEC_JCK_DET_L; 1409 ena = WM8350_JDL_ENA; 1410 break; 1411 1412 case WM8350_JDR: 1413 priv->hpr.jack = jack; 1414 priv->hpr.report = report; 1415 irq = WM8350_IRQ_CODEC_JCK_DET_R; 1416 ena = WM8350_JDR_ENA; 1417 break; 1418 1419 default: 1420 return -EINVAL; 1421 } 1422 1423 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1424 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); 1425 1426 /* Sync status */ 1427 wm8350_hp_jack_handler(irq, priv); 1428 1429 return 0; 1430 } 1431 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); 1432 1433 static struct snd_soc_codec *wm8350_codec; 1434 1435 static int wm8350_probe(struct platform_device *pdev) 1436 { 1437 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1438 struct snd_soc_codec *codec; 1439 struct wm8350 *wm8350; 1440 struct wm8350_data *priv; 1441 int ret; 1442 struct wm8350_output *out1; 1443 struct wm8350_output *out2; 1444 1445 BUG_ON(!wm8350_codec); 1446 1447 socdev->card->codec = wm8350_codec; 1448 codec = socdev->card->codec; 1449 wm8350 = codec->control_data; 1450 priv = codec->private_data; 1451 1452 /* Enable the codec */ 1453 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1454 1455 /* Enable robust clocking mode in ADC */ 1456 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7); 1457 wm8350_codec_write(codec, 0xde, 0x13); 1458 wm8350_codec_write(codec, WM8350_SECURITY, 0); 1459 1460 /* read OUT1 & OUT2 volumes */ 1461 out1 = &priv->out1; 1462 out2 = &priv->out2; 1463 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & 1464 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1465 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & 1466 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1467 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & 1468 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1469 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & 1470 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1471 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); 1472 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); 1473 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); 1474 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); 1475 1476 /* Latch VU bits & mute */ 1477 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, 1478 WM8350_OUT1_VU | WM8350_OUT1L_MUTE); 1479 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, 1480 WM8350_OUT2_VU | WM8350_OUT2L_MUTE); 1481 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, 1482 WM8350_OUT1_VU | WM8350_OUT1R_MUTE); 1483 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, 1484 WM8350_OUT2_VU | WM8350_OUT2R_MUTE); 1485 1486 /* Make sure jack detect is disabled to start off with */ 1487 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1488 WM8350_JDL_ENA | WM8350_JDR_ENA); 1489 1490 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, 1491 wm8350_hp_jack_handler, 0, "Left jack detect", 1492 priv); 1493 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, 1494 wm8350_hp_jack_handler, 0, "Right jack detect", 1495 priv); 1496 1497 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1498 if (ret < 0) { 1499 dev_err(&pdev->dev, "failed to create pcms\n"); 1500 return ret; 1501 } 1502 1503 snd_soc_add_controls(codec, wm8350_snd_controls, 1504 ARRAY_SIZE(wm8350_snd_controls)); 1505 wm8350_add_widgets(codec); 1506 1507 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1508 1509 return 0; 1510 } 1511 1512 static int wm8350_remove(struct platform_device *pdev) 1513 { 1514 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1515 struct snd_soc_codec *codec = socdev->card->codec; 1516 struct wm8350 *wm8350 = codec->control_data; 1517 struct wm8350_data *priv = codec->private_data; 1518 int ret; 1519 1520 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1521 WM8350_JDL_ENA | WM8350_JDR_ENA); 1522 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1523 1524 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); 1525 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); 1526 1527 priv->hpl.jack = NULL; 1528 priv->hpr.jack = NULL; 1529 1530 /* cancel any work waiting to be queued. */ 1531 ret = cancel_delayed_work(&codec->delayed_work); 1532 1533 /* if there was any work waiting then we run it now and 1534 * wait for its completion */ 1535 if (ret) { 1536 schedule_delayed_work(&codec->delayed_work, 0); 1537 flush_scheduled_work(); 1538 } 1539 1540 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1541 1542 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1543 1544 return 0; 1545 } 1546 1547 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) 1548 1549 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1550 SNDRV_PCM_FMTBIT_S20_3LE |\ 1551 SNDRV_PCM_FMTBIT_S24_LE) 1552 1553 static struct snd_soc_dai_ops wm8350_dai_ops = { 1554 .hw_params = wm8350_pcm_hw_params, 1555 .digital_mute = wm8350_mute, 1556 .trigger = wm8350_pcm_trigger, 1557 .set_fmt = wm8350_set_dai_fmt, 1558 .set_sysclk = wm8350_set_dai_sysclk, 1559 .set_pll = wm8350_set_fll, 1560 .set_clkdiv = wm8350_set_clkdiv, 1561 }; 1562 1563 struct snd_soc_dai wm8350_dai = { 1564 .name = "WM8350", 1565 .playback = { 1566 .stream_name = "Playback", 1567 .channels_min = 1, 1568 .channels_max = 2, 1569 .rates = WM8350_RATES, 1570 .formats = WM8350_FORMATS, 1571 }, 1572 .capture = { 1573 .stream_name = "Capture", 1574 .channels_min = 1, 1575 .channels_max = 2, 1576 .rates = WM8350_RATES, 1577 .formats = WM8350_FORMATS, 1578 }, 1579 .ops = &wm8350_dai_ops, 1580 }; 1581 EXPORT_SYMBOL_GPL(wm8350_dai); 1582 1583 struct snd_soc_codec_device soc_codec_dev_wm8350 = { 1584 .probe = wm8350_probe, 1585 .remove = wm8350_remove, 1586 .suspend = wm8350_suspend, 1587 .resume = wm8350_resume, 1588 }; 1589 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350); 1590 1591 static __devinit int wm8350_codec_probe(struct platform_device *pdev) 1592 { 1593 struct wm8350 *wm8350 = platform_get_drvdata(pdev); 1594 struct wm8350_data *priv; 1595 struct snd_soc_codec *codec; 1596 int ret, i; 1597 1598 if (wm8350->codec.platform_data == NULL) { 1599 dev_err(&pdev->dev, "No audio platform data supplied\n"); 1600 return -EINVAL; 1601 } 1602 1603 priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL); 1604 if (priv == NULL) 1605 return -ENOMEM; 1606 1607 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1608 priv->supplies[i].supply = supply_names[i]; 1609 1610 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), 1611 priv->supplies); 1612 if (ret != 0) 1613 goto err_priv; 1614 1615 codec = &priv->codec; 1616 wm8350->codec.codec = codec; 1617 1618 wm8350_dai.dev = &pdev->dev; 1619 1620 mutex_init(&codec->mutex); 1621 INIT_LIST_HEAD(&codec->dapm_widgets); 1622 INIT_LIST_HEAD(&codec->dapm_paths); 1623 codec->dev = &pdev->dev; 1624 codec->name = "WM8350"; 1625 codec->owner = THIS_MODULE; 1626 codec->read = wm8350_codec_read; 1627 codec->write = wm8350_codec_write; 1628 codec->bias_level = SND_SOC_BIAS_OFF; 1629 codec->set_bias_level = wm8350_set_bias_level; 1630 codec->dai = &wm8350_dai; 1631 codec->num_dai = 1; 1632 codec->reg_cache_size = WM8350_MAX_REGISTER; 1633 codec->private_data = priv; 1634 codec->control_data = wm8350; 1635 1636 /* Put the codec into reset if it wasn't already */ 1637 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1638 1639 INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work); 1640 ret = snd_soc_register_codec(codec); 1641 if (ret != 0) 1642 goto err_supply; 1643 1644 wm8350_codec = codec; 1645 1646 ret = snd_soc_register_dai(&wm8350_dai); 1647 if (ret != 0) 1648 goto err_codec; 1649 return 0; 1650 1651 err_codec: 1652 snd_soc_unregister_codec(codec); 1653 err_supply: 1654 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); 1655 err_priv: 1656 kfree(priv); 1657 wm8350_codec = NULL; 1658 return ret; 1659 } 1660 1661 static int __devexit wm8350_codec_remove(struct platform_device *pdev) 1662 { 1663 struct wm8350 *wm8350 = platform_get_drvdata(pdev); 1664 struct snd_soc_codec *codec = wm8350->codec.codec; 1665 struct wm8350_data *priv = codec->private_data; 1666 1667 snd_soc_unregister_dai(&wm8350_dai); 1668 snd_soc_unregister_codec(codec); 1669 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); 1670 kfree(priv); 1671 wm8350_codec = NULL; 1672 return 0; 1673 } 1674 1675 static struct platform_driver wm8350_codec_driver = { 1676 .driver = { 1677 .name = "wm8350-codec", 1678 .owner = THIS_MODULE, 1679 }, 1680 .probe = wm8350_codec_probe, 1681 .remove = __devexit_p(wm8350_codec_remove), 1682 }; 1683 1684 static __init int wm8350_init(void) 1685 { 1686 return platform_driver_register(&wm8350_codec_driver); 1687 } 1688 module_init(wm8350_init); 1689 1690 static __exit void wm8350_exit(void) 1691 { 1692 platform_driver_unregister(&wm8350_codec_driver); 1693 } 1694 module_exit(wm8350_exit); 1695 1696 MODULE_DESCRIPTION("ASoC WM8350 driver"); 1697 MODULE_AUTHOR("Liam Girdwood"); 1698 MODULE_LICENSE("GPL"); 1699 MODULE_ALIAS("platform:wm8350-codec"); 1700