1 /* 2 * wm5100.h -- WM5100 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef WM5100_ASOC_H 15 #define WM5100_ASOC_H 16 17 #include <sound/soc.h> 18 19 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); 20 21 #define WM5100_CLK_AIF1 1 22 #define WM5100_CLK_AIF2 2 23 #define WM5100_CLK_AIF3 3 24 #define WM5100_CLK_SYSCLK 4 25 #define WM5100_CLK_ASYNCCLK 5 26 #define WM5100_CLK_32KHZ 6 27 #define WM5100_CLK_OPCLK 7 28 29 #define WM5100_CLKSRC_MCLK1 0 30 #define WM5100_CLKSRC_MCLK2 1 31 #define WM5100_CLKSRC_SYSCLK 2 32 #define WM5100_CLKSRC_FLL1 4 33 #define WM5100_CLKSRC_FLL2 5 34 #define WM5100_CLKSRC_AIF1BCLK 8 35 #define WM5100_CLKSRC_AIF2BCLK 9 36 #define WM5100_CLKSRC_AIF3BCLK 10 37 #define WM5100_CLKSRC_ASYNCCLK 0x100 38 39 #define WM5100_FLL1 1 40 #define WM5100_FLL2 2 41 42 #define WM5100_FLL_SRC_MCLK1 0x0 43 #define WM5100_FLL_SRC_MCLK2 0x1 44 #define WM5100_FLL_SRC_FLL1 0x4 45 #define WM5100_FLL_SRC_FLL2 0x5 46 #define WM5100_FLL_SRC_AIF1BCLK 0x8 47 #define WM5100_FLL_SRC_AIF2BCLK 0x9 48 #define WM5100_FLL_SRC_AIF3BCLK 0xa 49 50 /* 51 * Register values. 52 */ 53 #define WM5100_SOFTWARE_RESET 0x00 54 #define WM5100_DEVICE_REVISION 0x01 55 #define WM5100_CTRL_IF_1 0x10 56 #define WM5100_TONE_GENERATOR_1 0x20 57 #define WM5100_PWM_DRIVE_1 0x30 58 #define WM5100_PWM_DRIVE_2 0x31 59 #define WM5100_PWM_DRIVE_3 0x32 60 #define WM5100_CLOCKING_1 0x100 61 #define WM5100_CLOCKING_3 0x101 62 #define WM5100_CLOCKING_4 0x102 63 #define WM5100_CLOCKING_5 0x103 64 #define WM5100_CLOCKING_6 0x104 65 #define WM5100_CLOCKING_7 0x107 66 #define WM5100_CLOCKING_8 0x108 67 #define WM5100_ASRC_ENABLE 0x120 68 #define WM5100_ASRC_STATUS 0x121 69 #define WM5100_ASRC_RATE1 0x122 70 #define WM5100_ISRC_1_CTRL_1 0x141 71 #define WM5100_ISRC_1_CTRL_2 0x142 72 #define WM5100_ISRC_2_CTRL1 0x143 73 #define WM5100_ISRC_2_CTRL_2 0x144 74 #define WM5100_FLL1_CONTROL_1 0x182 75 #define WM5100_FLL1_CONTROL_2 0x183 76 #define WM5100_FLL1_CONTROL_3 0x184 77 #define WM5100_FLL1_CONTROL_5 0x186 78 #define WM5100_FLL1_CONTROL_6 0x187 79 #define WM5100_FLL1_EFS_1 0x188 80 #define WM5100_FLL2_CONTROL_1 0x1A2 81 #define WM5100_FLL2_CONTROL_2 0x1A3 82 #define WM5100_FLL2_CONTROL_3 0x1A4 83 #define WM5100_FLL2_CONTROL_5 0x1A6 84 #define WM5100_FLL2_CONTROL_6 0x1A7 85 #define WM5100_FLL2_EFS_1 0x1A8 86 #define WM5100_MIC_CHARGE_PUMP_1 0x200 87 #define WM5100_MIC_CHARGE_PUMP_2 0x201 88 #define WM5100_HP_CHARGE_PUMP_1 0x202 89 #define WM5100_LDO1_CONTROL 0x211 90 #define WM5100_MIC_BIAS_CTRL_1 0x215 91 #define WM5100_MIC_BIAS_CTRL_2 0x216 92 #define WM5100_MIC_BIAS_CTRL_3 0x217 93 #define WM5100_ACCESSORY_DETECT_MODE_1 0x280 94 #define WM5100_HEADPHONE_DETECT_1 0x288 95 #define WM5100_HEADPHONE_DETECT_2 0x289 96 #define WM5100_MIC_DETECT_1 0x290 97 #define WM5100_MIC_DETECT_2 0x291 98 #define WM5100_MIC_DETECT_3 0x292 99 #define WM5100_MISC_CONTROL 0x2BB 100 #define WM5100_INPUT_ENABLES 0x301 101 #define WM5100_INPUT_ENABLES_STATUS 0x302 102 #define WM5100_IN1L_CONTROL 0x310 103 #define WM5100_IN1R_CONTROL 0x311 104 #define WM5100_IN2L_CONTROL 0x312 105 #define WM5100_IN2R_CONTROL 0x313 106 #define WM5100_IN3L_CONTROL 0x314 107 #define WM5100_IN3R_CONTROL 0x315 108 #define WM5100_IN4L_CONTROL 0x316 109 #define WM5100_IN4R_CONTROL 0x317 110 #define WM5100_RXANC_SRC 0x318 111 #define WM5100_INPUT_VOLUME_RAMP 0x319 112 #define WM5100_ADC_DIGITAL_VOLUME_1L 0x320 113 #define WM5100_ADC_DIGITAL_VOLUME_1R 0x321 114 #define WM5100_ADC_DIGITAL_VOLUME_2L 0x322 115 #define WM5100_ADC_DIGITAL_VOLUME_2R 0x323 116 #define WM5100_ADC_DIGITAL_VOLUME_3L 0x324 117 #define WM5100_ADC_DIGITAL_VOLUME_3R 0x325 118 #define WM5100_ADC_DIGITAL_VOLUME_4L 0x326 119 #define WM5100_ADC_DIGITAL_VOLUME_4R 0x327 120 #define WM5100_OUTPUT_ENABLES_2 0x401 121 #define WM5100_OUTPUT_STATUS_1 0x402 122 #define WM5100_OUTPUT_STATUS_2 0x403 123 #define WM5100_CHANNEL_ENABLES_1 0x408 124 #define WM5100_OUT_VOLUME_1L 0x410 125 #define WM5100_OUT_VOLUME_1R 0x411 126 #define WM5100_DAC_VOLUME_LIMIT_1L 0x412 127 #define WM5100_DAC_VOLUME_LIMIT_1R 0x413 128 #define WM5100_OUT_VOLUME_2L 0x414 129 #define WM5100_OUT_VOLUME_2R 0x415 130 #define WM5100_DAC_VOLUME_LIMIT_2L 0x416 131 #define WM5100_DAC_VOLUME_LIMIT_2R 0x417 132 #define WM5100_OUT_VOLUME_3L 0x418 133 #define WM5100_OUT_VOLUME_3R 0x419 134 #define WM5100_DAC_VOLUME_LIMIT_3L 0x41A 135 #define WM5100_DAC_VOLUME_LIMIT_3R 0x41B 136 #define WM5100_OUT_VOLUME_4L 0x41C 137 #define WM5100_OUT_VOLUME_4R 0x41D 138 #define WM5100_DAC_VOLUME_LIMIT_5L 0x41E 139 #define WM5100_DAC_VOLUME_LIMIT_5R 0x41F 140 #define WM5100_DAC_VOLUME_LIMIT_6L 0x420 141 #define WM5100_DAC_VOLUME_LIMIT_6R 0x421 142 #define WM5100_DAC_AEC_CONTROL_1 0x440 143 #define WM5100_OUTPUT_VOLUME_RAMP 0x441 144 #define WM5100_DAC_DIGITAL_VOLUME_1L 0x480 145 #define WM5100_DAC_DIGITAL_VOLUME_1R 0x481 146 #define WM5100_DAC_DIGITAL_VOLUME_2L 0x482 147 #define WM5100_DAC_DIGITAL_VOLUME_2R 0x483 148 #define WM5100_DAC_DIGITAL_VOLUME_3L 0x484 149 #define WM5100_DAC_DIGITAL_VOLUME_3R 0x485 150 #define WM5100_DAC_DIGITAL_VOLUME_4L 0x486 151 #define WM5100_DAC_DIGITAL_VOLUME_4R 0x487 152 #define WM5100_DAC_DIGITAL_VOLUME_5L 0x488 153 #define WM5100_DAC_DIGITAL_VOLUME_5R 0x489 154 #define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A 155 #define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B 156 #define WM5100_PDM_SPK1_CTRL_1 0x4C0 157 #define WM5100_PDM_SPK1_CTRL_2 0x4C1 158 #define WM5100_PDM_SPK2_CTRL_1 0x4C2 159 #define WM5100_PDM_SPK2_CTRL_2 0x4C3 160 #define WM5100_AUDIO_IF_1_1 0x500 161 #define WM5100_AUDIO_IF_1_2 0x501 162 #define WM5100_AUDIO_IF_1_3 0x502 163 #define WM5100_AUDIO_IF_1_4 0x503 164 #define WM5100_AUDIO_IF_1_5 0x504 165 #define WM5100_AUDIO_IF_1_6 0x505 166 #define WM5100_AUDIO_IF_1_7 0x506 167 #define WM5100_AUDIO_IF_1_8 0x507 168 #define WM5100_AUDIO_IF_1_9 0x508 169 #define WM5100_AUDIO_IF_1_10 0x509 170 #define WM5100_AUDIO_IF_1_11 0x50A 171 #define WM5100_AUDIO_IF_1_12 0x50B 172 #define WM5100_AUDIO_IF_1_13 0x50C 173 #define WM5100_AUDIO_IF_1_14 0x50D 174 #define WM5100_AUDIO_IF_1_15 0x50E 175 #define WM5100_AUDIO_IF_1_16 0x50F 176 #define WM5100_AUDIO_IF_1_17 0x510 177 #define WM5100_AUDIO_IF_1_18 0x511 178 #define WM5100_AUDIO_IF_1_19 0x512 179 #define WM5100_AUDIO_IF_1_20 0x513 180 #define WM5100_AUDIO_IF_1_21 0x514 181 #define WM5100_AUDIO_IF_1_22 0x515 182 #define WM5100_AUDIO_IF_1_23 0x516 183 #define WM5100_AUDIO_IF_1_24 0x517 184 #define WM5100_AUDIO_IF_1_25 0x518 185 #define WM5100_AUDIO_IF_1_26 0x519 186 #define WM5100_AUDIO_IF_1_27 0x51A 187 #define WM5100_AUDIO_IF_2_1 0x540 188 #define WM5100_AUDIO_IF_2_2 0x541 189 #define WM5100_AUDIO_IF_2_3 0x542 190 #define WM5100_AUDIO_IF_2_4 0x543 191 #define WM5100_AUDIO_IF_2_5 0x544 192 #define WM5100_AUDIO_IF_2_6 0x545 193 #define WM5100_AUDIO_IF_2_7 0x546 194 #define WM5100_AUDIO_IF_2_8 0x547 195 #define WM5100_AUDIO_IF_2_9 0x548 196 #define WM5100_AUDIO_IF_2_10 0x549 197 #define WM5100_AUDIO_IF_2_11 0x54A 198 #define WM5100_AUDIO_IF_2_18 0x551 199 #define WM5100_AUDIO_IF_2_19 0x552 200 #define WM5100_AUDIO_IF_2_26 0x559 201 #define WM5100_AUDIO_IF_2_27 0x55A 202 #define WM5100_AUDIO_IF_3_1 0x580 203 #define WM5100_AUDIO_IF_3_2 0x581 204 #define WM5100_AUDIO_IF_3_3 0x582 205 #define WM5100_AUDIO_IF_3_4 0x583 206 #define WM5100_AUDIO_IF_3_5 0x584 207 #define WM5100_AUDIO_IF_3_6 0x585 208 #define WM5100_AUDIO_IF_3_7 0x586 209 #define WM5100_AUDIO_IF_3_8 0x587 210 #define WM5100_AUDIO_IF_3_9 0x588 211 #define WM5100_AUDIO_IF_3_10 0x589 212 #define WM5100_AUDIO_IF_3_11 0x58A 213 #define WM5100_AUDIO_IF_3_18 0x591 214 #define WM5100_AUDIO_IF_3_19 0x592 215 #define WM5100_AUDIO_IF_3_26 0x599 216 #define WM5100_AUDIO_IF_3_27 0x59A 217 #define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640 218 #define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641 219 #define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642 220 #define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643 221 #define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644 222 #define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645 223 #define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646 224 #define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647 225 #define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648 226 #define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649 227 #define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A 228 #define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B 229 #define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C 230 #define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D 231 #define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E 232 #define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F 233 #define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680 234 #define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681 235 #define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682 236 #define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683 237 #define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684 238 #define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685 239 #define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686 240 #define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687 241 #define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688 242 #define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689 243 #define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A 244 #define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B 245 #define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C 246 #define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D 247 #define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E 248 #define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F 249 #define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690 250 #define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691 251 #define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692 252 #define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693 253 #define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694 254 #define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695 255 #define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696 256 #define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697 257 #define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698 258 #define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699 259 #define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A 260 #define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B 261 #define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C 262 #define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D 263 #define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E 264 #define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F 265 #define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0 266 #define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1 267 #define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2 268 #define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3 269 #define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4 270 #define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5 271 #define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6 272 #define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7 273 #define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8 274 #define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9 275 #define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA 276 #define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB 277 #define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC 278 #define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD 279 #define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE 280 #define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF 281 #define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0 282 #define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1 283 #define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2 284 #define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3 285 #define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4 286 #define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5 287 #define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6 288 #define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7 289 #define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8 290 #define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9 291 #define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA 292 #define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB 293 #define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC 294 #define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD 295 #define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE 296 #define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF 297 #define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0 298 #define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1 299 #define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2 300 #define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3 301 #define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4 302 #define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5 303 #define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6 304 #define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7 305 #define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8 306 #define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9 307 #define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA 308 #define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB 309 #define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC 310 #define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD 311 #define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE 312 #define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF 313 #define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0 314 #define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1 315 #define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2 316 #define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3 317 #define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4 318 #define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5 319 #define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6 320 #define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7 321 #define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8 322 #define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9 323 #define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA 324 #define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB 325 #define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC 326 #define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD 327 #define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE 328 #define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF 329 #define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700 330 #define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701 331 #define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702 332 #define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703 333 #define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704 334 #define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705 335 #define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706 336 #define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707 337 #define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708 338 #define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709 339 #define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A 340 #define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B 341 #define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C 342 #define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D 343 #define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E 344 #define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F 345 #define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710 346 #define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711 347 #define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712 348 #define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713 349 #define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714 350 #define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715 351 #define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716 352 #define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717 353 #define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718 354 #define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719 355 #define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A 356 #define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B 357 #define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C 358 #define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D 359 #define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E 360 #define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F 361 #define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720 362 #define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721 363 #define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722 364 #define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723 365 #define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724 366 #define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725 367 #define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726 368 #define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727 369 #define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728 370 #define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729 371 #define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A 372 #define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B 373 #define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C 374 #define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D 375 #define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E 376 #define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F 377 #define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730 378 #define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731 379 #define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732 380 #define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733 381 #define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734 382 #define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735 383 #define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736 384 #define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737 385 #define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738 386 #define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739 387 #define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A 388 #define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B 389 #define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C 390 #define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D 391 #define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E 392 #define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F 393 #define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740 394 #define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741 395 #define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742 396 #define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743 397 #define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744 398 #define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745 399 #define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746 400 #define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747 401 #define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748 402 #define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749 403 #define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A 404 #define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B 405 #define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C 406 #define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D 407 #define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E 408 #define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F 409 #define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780 410 #define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781 411 #define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782 412 #define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783 413 #define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784 414 #define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785 415 #define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786 416 #define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787 417 #define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788 418 #define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789 419 #define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A 420 #define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B 421 #define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C 422 #define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 423 #define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 424 #define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 425 #define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880 426 #define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881 427 #define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882 428 #define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883 429 #define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884 430 #define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885 431 #define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886 432 #define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887 433 #define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888 434 #define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889 435 #define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A 436 #define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B 437 #define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C 438 #define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D 439 #define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E 440 #define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F 441 #define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890 442 #define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891 443 #define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892 444 #define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893 445 #define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894 446 #define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895 447 #define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896 448 #define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897 449 #define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898 450 #define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899 451 #define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A 452 #define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B 453 #define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C 454 #define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D 455 #define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E 456 #define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F 457 #define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0 458 #define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1 459 #define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2 460 #define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3 461 #define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4 462 #define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5 463 #define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6 464 #define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7 465 #define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8 466 #define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9 467 #define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA 468 #define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB 469 #define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC 470 #define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD 471 #define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE 472 #define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF 473 #define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900 474 #define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901 475 #define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902 476 #define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903 477 #define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904 478 #define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905 479 #define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906 480 #define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907 481 #define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908 482 #define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909 483 #define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A 484 #define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B 485 #define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C 486 #define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D 487 #define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E 488 #define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F 489 #define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910 490 #define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911 491 #define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912 492 #define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913 493 #define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914 494 #define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915 495 #define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916 496 #define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917 497 #define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918 498 #define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919 499 #define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A 500 #define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B 501 #define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C 502 #define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D 503 #define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E 504 #define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F 505 #define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940 506 #define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941 507 #define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942 508 #define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943 509 #define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944 510 #define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945 511 #define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946 512 #define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947 513 #define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948 514 #define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949 515 #define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A 516 #define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B 517 #define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C 518 #define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D 519 #define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E 520 #define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F 521 #define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950 522 #define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958 523 #define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960 524 #define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968 525 #define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970 526 #define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978 527 #define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980 528 #define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981 529 #define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982 530 #define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983 531 #define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984 532 #define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985 533 #define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986 534 #define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987 535 #define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988 536 #define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989 537 #define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A 538 #define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B 539 #define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C 540 #define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D 541 #define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E 542 #define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F 543 #define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990 544 #define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998 545 #define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0 546 #define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8 547 #define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0 548 #define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8 549 #define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0 550 #define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1 551 #define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2 552 #define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3 553 #define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4 554 #define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5 555 #define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6 556 #define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7 557 #define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8 558 #define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9 559 #define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA 560 #define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB 561 #define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC 562 #define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD 563 #define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE 564 #define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF 565 #define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0 566 #define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8 567 #define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0 568 #define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8 569 #define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0 570 #define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8 571 #define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80 572 #define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88 573 #define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90 574 #define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98 575 #define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 576 #define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 577 #define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 578 #define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18 579 #define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20 580 #define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28 581 #define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 582 #define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 583 #define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 584 #define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 585 #define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 586 #define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 587 #define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 588 #define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 589 #define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70 590 #define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78 591 #define WM5100_GPIO_CTRL_1 0xC00 592 #define WM5100_GPIO_CTRL_2 0xC01 593 #define WM5100_GPIO_CTRL_3 0xC02 594 #define WM5100_GPIO_CTRL_4 0xC03 595 #define WM5100_GPIO_CTRL_5 0xC04 596 #define WM5100_GPIO_CTRL_6 0xC05 597 #define WM5100_MISC_PAD_CTRL_1 0xC23 598 #define WM5100_MISC_PAD_CTRL_2 0xC24 599 #define WM5100_MISC_PAD_CTRL_3 0xC25 600 #define WM5100_MISC_PAD_CTRL_4 0xC26 601 #define WM5100_MISC_PAD_CTRL_5 0xC27 602 #define WM5100_MISC_GPIO_1 0xC28 603 #define WM5100_INTERRUPT_STATUS_1 0xD00 604 #define WM5100_INTERRUPT_STATUS_2 0xD01 605 #define WM5100_INTERRUPT_STATUS_3 0xD02 606 #define WM5100_INTERRUPT_STATUS_4 0xD03 607 #define WM5100_INTERRUPT_RAW_STATUS_2 0xD04 608 #define WM5100_INTERRUPT_RAW_STATUS_3 0xD05 609 #define WM5100_INTERRUPT_RAW_STATUS_4 0xD06 610 #define WM5100_INTERRUPT_STATUS_1_MASK 0xD07 611 #define WM5100_INTERRUPT_STATUS_2_MASK 0xD08 612 #define WM5100_INTERRUPT_STATUS_3_MASK 0xD09 613 #define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A 614 #define WM5100_INTERRUPT_CONTROL 0xD1F 615 #define WM5100_IRQ_DEBOUNCE_1 0xD20 616 #define WM5100_IRQ_DEBOUNCE_2 0xD21 617 #define WM5100_FX_CTRL 0xE00 618 #define WM5100_EQ1_1 0xE10 619 #define WM5100_EQ1_2 0xE11 620 #define WM5100_EQ1_3 0xE12 621 #define WM5100_EQ1_4 0xE13 622 #define WM5100_EQ1_5 0xE14 623 #define WM5100_EQ1_6 0xE15 624 #define WM5100_EQ1_7 0xE16 625 #define WM5100_EQ1_8 0xE17 626 #define WM5100_EQ1_9 0xE18 627 #define WM5100_EQ1_10 0xE19 628 #define WM5100_EQ1_11 0xE1A 629 #define WM5100_EQ1_12 0xE1B 630 #define WM5100_EQ1_13 0xE1C 631 #define WM5100_EQ1_14 0xE1D 632 #define WM5100_EQ1_15 0xE1E 633 #define WM5100_EQ1_16 0xE1F 634 #define WM5100_EQ1_17 0xE20 635 #define WM5100_EQ1_18 0xE21 636 #define WM5100_EQ1_19 0xE22 637 #define WM5100_EQ1_20 0xE23 638 #define WM5100_EQ2_1 0xE26 639 #define WM5100_EQ2_2 0xE27 640 #define WM5100_EQ2_3 0xE28 641 #define WM5100_EQ2_4 0xE29 642 #define WM5100_EQ2_5 0xE2A 643 #define WM5100_EQ2_6 0xE2B 644 #define WM5100_EQ2_7 0xE2C 645 #define WM5100_EQ2_8 0xE2D 646 #define WM5100_EQ2_9 0xE2E 647 #define WM5100_EQ2_10 0xE2F 648 #define WM5100_EQ2_11 0xE30 649 #define WM5100_EQ2_12 0xE31 650 #define WM5100_EQ2_13 0xE32 651 #define WM5100_EQ2_14 0xE33 652 #define WM5100_EQ2_15 0xE34 653 #define WM5100_EQ2_16 0xE35 654 #define WM5100_EQ2_17 0xE36 655 #define WM5100_EQ2_18 0xE37 656 #define WM5100_EQ2_19 0xE38 657 #define WM5100_EQ2_20 0xE39 658 #define WM5100_EQ3_1 0xE3C 659 #define WM5100_EQ3_2 0xE3D 660 #define WM5100_EQ3_3 0xE3E 661 #define WM5100_EQ3_4 0xE3F 662 #define WM5100_EQ3_5 0xE40 663 #define WM5100_EQ3_6 0xE41 664 #define WM5100_EQ3_7 0xE42 665 #define WM5100_EQ3_8 0xE43 666 #define WM5100_EQ3_9 0xE44 667 #define WM5100_EQ3_10 0xE45 668 #define WM5100_EQ3_11 0xE46 669 #define WM5100_EQ3_12 0xE47 670 #define WM5100_EQ3_13 0xE48 671 #define WM5100_EQ3_14 0xE49 672 #define WM5100_EQ3_15 0xE4A 673 #define WM5100_EQ3_16 0xE4B 674 #define WM5100_EQ3_17 0xE4C 675 #define WM5100_EQ3_18 0xE4D 676 #define WM5100_EQ3_19 0xE4E 677 #define WM5100_EQ3_20 0xE4F 678 #define WM5100_EQ4_1 0xE52 679 #define WM5100_EQ4_2 0xE53 680 #define WM5100_EQ4_3 0xE54 681 #define WM5100_EQ4_4 0xE55 682 #define WM5100_EQ4_5 0xE56 683 #define WM5100_EQ4_6 0xE57 684 #define WM5100_EQ4_7 0xE58 685 #define WM5100_EQ4_8 0xE59 686 #define WM5100_EQ4_9 0xE5A 687 #define WM5100_EQ4_10 0xE5B 688 #define WM5100_EQ4_11 0xE5C 689 #define WM5100_EQ4_12 0xE5D 690 #define WM5100_EQ4_13 0xE5E 691 #define WM5100_EQ4_14 0xE5F 692 #define WM5100_EQ4_15 0xE60 693 #define WM5100_EQ4_16 0xE61 694 #define WM5100_EQ4_17 0xE62 695 #define WM5100_EQ4_18 0xE63 696 #define WM5100_EQ4_19 0xE64 697 #define WM5100_EQ4_20 0xE65 698 #define WM5100_DRC1_CTRL1 0xE80 699 #define WM5100_DRC1_CTRL2 0xE81 700 #define WM5100_DRC1_CTRL3 0xE82 701 #define WM5100_DRC1_CTRL4 0xE83 702 #define WM5100_DRC1_CTRL5 0xE84 703 #define WM5100_HPLPF1_1 0xEC0 704 #define WM5100_HPLPF1_2 0xEC1 705 #define WM5100_HPLPF2_1 0xEC4 706 #define WM5100_HPLPF2_2 0xEC5 707 #define WM5100_HPLPF3_1 0xEC8 708 #define WM5100_HPLPF3_2 0xEC9 709 #define WM5100_HPLPF4_1 0xECC 710 #define WM5100_HPLPF4_2 0xECD 711 #define WM5100_DSP1_DM_0 0x4000 712 #define WM5100_DSP1_DM_1 0x4001 713 #define WM5100_DSP1_DM_2 0x4002 714 #define WM5100_DSP1_DM_3 0x4003 715 #define WM5100_DSP1_DM_508 0x41FC 716 #define WM5100_DSP1_DM_509 0x41FD 717 #define WM5100_DSP1_DM_510 0x41FE 718 #define WM5100_DSP1_DM_511 0x41FF 719 #define WM5100_DSP1_PM_0 0x4800 720 #define WM5100_DSP1_PM_1 0x4801 721 #define WM5100_DSP1_PM_2 0x4802 722 #define WM5100_DSP1_PM_3 0x4803 723 #define WM5100_DSP1_PM_4 0x4804 724 #define WM5100_DSP1_PM_5 0x4805 725 #define WM5100_DSP1_PM_1530 0x4DFA 726 #define WM5100_DSP1_PM_1531 0x4DFB 727 #define WM5100_DSP1_PM_1532 0x4DFC 728 #define WM5100_DSP1_PM_1533 0x4DFD 729 #define WM5100_DSP1_PM_1534 0x4DFE 730 #define WM5100_DSP1_PM_1535 0x4DFF 731 #define WM5100_DSP1_ZM_0 0x5000 732 #define WM5100_DSP1_ZM_1 0x5001 733 #define WM5100_DSP1_ZM_2 0x5002 734 #define WM5100_DSP1_ZM_3 0x5003 735 #define WM5100_DSP1_ZM_2044 0x57FC 736 #define WM5100_DSP1_ZM_2045 0x57FD 737 #define WM5100_DSP1_ZM_2046 0x57FE 738 #define WM5100_DSP1_ZM_2047 0x57FF 739 #define WM5100_DSP2_DM_0 0x6000 740 #define WM5100_DSP2_DM_1 0x6001 741 #define WM5100_DSP2_DM_2 0x6002 742 #define WM5100_DSP2_DM_3 0x6003 743 #define WM5100_DSP2_DM_508 0x61FC 744 #define WM5100_DSP2_DM_509 0x61FD 745 #define WM5100_DSP2_DM_510 0x61FE 746 #define WM5100_DSP2_DM_511 0x61FF 747 #define WM5100_DSP2_PM_0 0x6800 748 #define WM5100_DSP2_PM_1 0x6801 749 #define WM5100_DSP2_PM_2 0x6802 750 #define WM5100_DSP2_PM_3 0x6803 751 #define WM5100_DSP2_PM_4 0x6804 752 #define WM5100_DSP2_PM_5 0x6805 753 #define WM5100_DSP2_PM_1530 0x6DFA 754 #define WM5100_DSP2_PM_1531 0x6DFB 755 #define WM5100_DSP2_PM_1532 0x6DFC 756 #define WM5100_DSP2_PM_1533 0x6DFD 757 #define WM5100_DSP2_PM_1534 0x6DFE 758 #define WM5100_DSP2_PM_1535 0x6DFF 759 #define WM5100_DSP2_ZM_0 0x7000 760 #define WM5100_DSP2_ZM_1 0x7001 761 #define WM5100_DSP2_ZM_2 0x7002 762 #define WM5100_DSP2_ZM_3 0x7003 763 #define WM5100_DSP2_ZM_2044 0x77FC 764 #define WM5100_DSP2_ZM_2045 0x77FD 765 #define WM5100_DSP2_ZM_2046 0x77FE 766 #define WM5100_DSP2_ZM_2047 0x77FF 767 #define WM5100_DSP3_DM_0 0x8000 768 #define WM5100_DSP3_DM_1 0x8001 769 #define WM5100_DSP3_DM_2 0x8002 770 #define WM5100_DSP3_DM_3 0x8003 771 #define WM5100_DSP3_DM_508 0x81FC 772 #define WM5100_DSP3_DM_509 0x81FD 773 #define WM5100_DSP3_DM_510 0x81FE 774 #define WM5100_DSP3_DM_511 0x81FF 775 #define WM5100_DSP3_PM_0 0x8800 776 #define WM5100_DSP3_PM_1 0x8801 777 #define WM5100_DSP3_PM_2 0x8802 778 #define WM5100_DSP3_PM_3 0x8803 779 #define WM5100_DSP3_PM_4 0x8804 780 #define WM5100_DSP3_PM_5 0x8805 781 #define WM5100_DSP3_PM_1530 0x8DFA 782 #define WM5100_DSP3_PM_1531 0x8DFB 783 #define WM5100_DSP3_PM_1532 0x8DFC 784 #define WM5100_DSP3_PM_1533 0x8DFD 785 #define WM5100_DSP3_PM_1534 0x8DFE 786 #define WM5100_DSP3_PM_1535 0x8DFF 787 #define WM5100_DSP3_ZM_0 0x9000 788 #define WM5100_DSP3_ZM_1 0x9001 789 #define WM5100_DSP3_ZM_2 0x9002 790 #define WM5100_DSP3_ZM_3 0x9003 791 #define WM5100_DSP3_ZM_2044 0x97FC 792 #define WM5100_DSP3_ZM_2045 0x97FD 793 #define WM5100_DSP3_ZM_2046 0x97FE 794 #define WM5100_DSP3_ZM_2047 0x97FF 795 796 #define WM5100_REGISTER_COUNT 1435 797 #define WM5100_MAX_REGISTER 0x97FF 798 799 /* 800 * Field Definitions. 801 */ 802 803 /* 804 * R0 (0x00) - software reset 805 */ 806 #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 807 #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 808 #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 809 810 /* 811 * R1 (0x01) - Device Revision 812 */ 813 #define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 814 #define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 815 #define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 816 817 /* 818 * R16 (0x10) - Ctrl IF 1 819 */ 820 #define WM5100_AUTO_INC 0x0001 /* AUTO_INC */ 821 #define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 822 #define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */ 823 #define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */ 824 825 /* 826 * R32 (0x20) - Tone Generator 1 827 */ 828 #define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */ 829 #define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */ 830 #define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */ 831 #define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */ 832 #define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */ 833 #define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */ 834 #define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */ 835 #define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */ 836 #define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */ 837 #define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */ 838 #define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */ 839 #define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */ 840 #define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */ 841 #define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */ 842 843 /* 844 * R48 (0x30) - PWM Drive 1 845 */ 846 #define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */ 847 #define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */ 848 #define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */ 849 #define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */ 850 #define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */ 851 #define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */ 852 #define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */ 853 #define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */ 854 #define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */ 855 #define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */ 856 #define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */ 857 #define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */ 858 #define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */ 859 #define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */ 860 #define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */ 861 #define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */ 862 #define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */ 863 #define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */ 864 #define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */ 865 #define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */ 866 #define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */ 867 #define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */ 868 869 /* 870 * R49 (0x31) - PWM Drive 2 871 */ 872 #define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */ 873 #define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */ 874 #define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */ 875 876 /* 877 * R50 (0x32) - PWM Drive 3 878 */ 879 #define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */ 880 #define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */ 881 #define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */ 882 883 /* 884 * R256 (0x100) - Clocking 1 885 */ 886 #define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */ 887 #define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */ 888 #define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */ 889 890 /* 891 * R257 (0x101) - Clocking 3 892 */ 893 #define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 894 #define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 895 #define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 896 #define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 897 #define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 898 #define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 899 #define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 900 #define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 901 #define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 902 #define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 903 904 /* 905 * R258 (0x102) - Clocking 4 906 */ 907 #define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 908 #define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 909 #define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 910 911 /* 912 * R259 (0x103) - Clocking 5 913 */ 914 #define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */ 915 #define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */ 916 #define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */ 917 918 /* 919 * R260 (0x104) - Clocking 6 920 */ 921 #define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */ 922 #define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */ 923 #define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */ 924 925 /* 926 * R263 (0x107) - Clocking 7 927 */ 928 #define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */ 929 #define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */ 930 #define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */ 931 #define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */ 932 #define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */ 933 #define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */ 934 #define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */ 935 #define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */ 936 #define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */ 937 #define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */ 938 939 /* 940 * R264 (0x108) - Clocking 8 941 */ 942 #define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ 943 #define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ 944 #define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ 945 946 /* 947 * R288 (0x120) - ASRC_ENABLE 948 */ 949 #define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */ 950 #define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ 951 #define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */ 952 #define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */ 953 #define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */ 954 #define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ 955 #define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */ 956 #define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */ 957 #define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */ 958 #define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ 959 #define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */ 960 #define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */ 961 #define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */ 962 #define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ 963 #define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */ 964 #define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */ 965 966 /* 967 * R289 (0x121) - ASRC_STATUS 968 */ 969 #define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */ 970 #define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */ 971 #define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */ 972 #define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */ 973 #define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */ 974 #define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */ 975 #define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */ 976 #define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */ 977 #define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */ 978 #define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */ 979 #define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */ 980 #define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */ 981 #define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */ 982 #define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */ 983 #define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */ 984 #define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */ 985 986 /* 987 * R290 (0x122) - ASRC_RATE1 988 */ 989 #define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */ 990 #define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */ 991 #define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */ 992 993 /* 994 * R321 (0x141) - ISRC 1 CTRL 1 995 */ 996 #define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */ 997 #define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */ 998 #define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */ 999 #define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */ 1000 #define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */ 1001 #define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */ 1002 #define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */ 1003 #define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */ 1004 #define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */ 1005 #define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */ 1006 #define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */ 1007 #define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */ 1008 #define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */ 1009 1010 /* 1011 * R322 (0x142) - ISRC 1 CTRL 2 1012 */ 1013 #define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */ 1014 #define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */ 1015 #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */ 1016 #define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */ 1017 #define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */ 1018 #define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */ 1019 #define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */ 1020 #define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */ 1021 #define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */ 1022 #define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */ 1023 #define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */ 1024 #define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */ 1025 #define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */ 1026 #define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */ 1027 #define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */ 1028 #define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */ 1029 #define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */ 1030 #define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */ 1031 #define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */ 1032 #define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */ 1033 #define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */ 1034 #define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */ 1035 #define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */ 1036 #define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */ 1037 #define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */ 1038 #define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */ 1039 #define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */ 1040 #define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */ 1041 #define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */ 1042 #define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */ 1043 #define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */ 1044 #define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */ 1045 #define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */ 1046 #define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */ 1047 #define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */ 1048 #define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */ 1049 1050 /* 1051 * R323 (0x143) - ISRC 2 CTRL1 1052 */ 1053 #define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */ 1054 #define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */ 1055 #define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */ 1056 #define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */ 1057 #define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */ 1058 #define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */ 1059 #define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */ 1060 #define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */ 1061 #define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */ 1062 #define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */ 1063 #define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */ 1064 #define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */ 1065 #define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */ 1066 1067 /* 1068 * R324 (0x144) - ISRC 2 CTRL 2 1069 */ 1070 #define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */ 1071 #define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */ 1072 #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */ 1073 #define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */ 1074 #define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */ 1075 #define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */ 1076 #define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */ 1077 #define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */ 1078 #define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */ 1079 #define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */ 1080 #define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */ 1081 #define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */ 1082 #define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */ 1083 #define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */ 1084 #define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */ 1085 #define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */ 1086 #define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */ 1087 #define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */ 1088 #define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */ 1089 #define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */ 1090 #define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */ 1091 #define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */ 1092 #define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */ 1093 #define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */ 1094 #define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */ 1095 #define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */ 1096 #define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */ 1097 #define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */ 1098 #define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */ 1099 #define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */ 1100 #define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */ 1101 #define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */ 1102 #define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */ 1103 #define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */ 1104 #define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */ 1105 #define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */ 1106 1107 /* 1108 * R386 (0x182) - FLL1 Control 1 1109 */ 1110 #define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */ 1111 #define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1112 #define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1113 #define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1114 1115 /* 1116 * R387 (0x183) - FLL1 Control 2 1117 */ 1118 #define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1119 #define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1120 #define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1121 #define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1122 #define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1123 #define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1124 1125 /* 1126 * R388 (0x184) - FLL1 Control 3 1127 */ 1128 #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */ 1129 #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */ 1130 #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */ 1131 1132 /* 1133 * R390 (0x186) - FLL1 Control 5 1134 */ 1135 #define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */ 1136 #define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */ 1137 #define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */ 1138 1139 /* 1140 * R391 (0x187) - FLL1 Control 6 1141 */ 1142 #define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */ 1143 #define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */ 1144 #define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */ 1145 #define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */ 1146 #define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */ 1147 #define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */ 1148 1149 /* 1150 * R392 (0x188) - FLL1 EFS 1 1151 */ 1152 #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 1153 #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 1154 #define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 1155 1156 /* 1157 * R418 (0x1A2) - FLL2 Control 1 1158 */ 1159 #define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */ 1160 #define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1161 #define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1162 #define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1163 1164 /* 1165 * R419 (0x1A3) - FLL2 Control 2 1166 */ 1167 #define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1168 #define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1169 #define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1170 #define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1171 #define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1172 #define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1173 1174 /* 1175 * R420 (0x1A4) - FLL2 Control 3 1176 */ 1177 #define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */ 1178 #define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */ 1179 #define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */ 1180 1181 /* 1182 * R422 (0x1A6) - FLL2 Control 5 1183 */ 1184 #define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */ 1185 #define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */ 1186 #define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */ 1187 1188 /* 1189 * R423 (0x1A7) - FLL2 Control 6 1190 */ 1191 #define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */ 1192 #define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */ 1193 #define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */ 1194 #define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */ 1195 #define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */ 1196 #define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */ 1197 1198 /* 1199 * R424 (0x1A8) - FLL2 EFS 1 1200 */ 1201 #define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 1202 #define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 1203 #define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 1204 1205 /* 1206 * R512 (0x200) - Mic Charge Pump 1 1207 */ 1208 #define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */ 1209 #define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */ 1210 #define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */ 1211 #define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */ 1212 #define WM5100_CP2_ENA 0x0001 /* CP2_ENA */ 1213 #define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */ 1214 #define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */ 1215 #define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */ 1216 1217 /* 1218 * R513 (0x201) - Mic Charge Pump 2 1219 */ 1220 #define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */ 1221 #define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */ 1222 #define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */ 1223 1224 /* 1225 * R514 (0x202) - HP Charge Pump 1 1226 */ 1227 #define WM5100_CP1_ENA 0x0001 /* CP1_ENA */ 1228 #define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */ 1229 #define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */ 1230 #define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */ 1231 1232 /* 1233 * R529 (0x211) - LDO1 Control 1234 */ 1235 #define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */ 1236 #define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */ 1237 #define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */ 1238 #define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */ 1239 1240 /* 1241 * R533 (0x215) - Mic Bias Ctrl 1 1242 */ 1243 #define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 1244 #define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 1245 #define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 1246 #define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1247 #define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */ 1248 #define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1249 #define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1250 #define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1251 #define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 1252 #define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 1253 #define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 1254 #define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */ 1255 #define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */ 1256 #define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */ 1257 #define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */ 1258 #define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */ 1259 #define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 1260 #define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 1261 #define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 1262 1263 /* 1264 * R534 (0x216) - Mic Bias Ctrl 2 1265 */ 1266 #define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 1267 #define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 1268 #define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 1269 #define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1270 #define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */ 1271 #define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1272 #define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1273 #define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1274 #define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 1275 #define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 1276 #define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 1277 #define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */ 1278 #define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */ 1279 #define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */ 1280 #define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */ 1281 #define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */ 1282 #define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 1283 #define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 1284 #define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 1285 1286 /* 1287 * R535 (0x217) - Mic Bias Ctrl 3 1288 */ 1289 #define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */ 1290 #define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */ 1291 #define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */ 1292 #define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */ 1293 #define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */ 1294 #define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */ 1295 #define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */ 1296 #define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */ 1297 #define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */ 1298 #define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */ 1299 #define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */ 1300 #define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */ 1301 #define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */ 1302 #define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */ 1303 #define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */ 1304 #define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */ 1305 #define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */ 1306 #define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ 1307 #define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ 1308 1309 /* 1310 * R640 (0x280) - Accessory Detect Mode 1 1311 */ 1312 #define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */ 1313 #define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */ 1314 #define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */ 1315 #define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */ 1316 #define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ 1317 #define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ 1318 #define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ 1319 #define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ 1320 #define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ 1321 #define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ 1322 1323 /* 1324 * R648 (0x288) - Headphone Detect 1 1325 */ 1326 #define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1327 #define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1328 #define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1329 #define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1330 #define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1331 #define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1332 #define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1333 #define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1334 #define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1335 #define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1336 #define WM5100_HP_POLL 0x0001 /* HP_POLL */ 1337 #define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */ 1338 #define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */ 1339 #define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */ 1340 1341 /* 1342 * R649 (0x289) - Headphone Detect 2 1343 */ 1344 #define WM5100_HP_DONE 0x0080 /* HP_DONE */ 1345 #define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */ 1346 #define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */ 1347 #define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */ 1348 #define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1349 #define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1350 #define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1351 1352 /* 1353 * R656 (0x290) - Mic Detect 1 1354 */ 1355 #define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1356 #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1357 #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1358 #define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */ 1359 #define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */ 1360 #define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */ 1361 #define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */ 1362 #define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */ 1363 #define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */ 1364 #define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */ 1365 #define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */ 1366 #define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */ 1367 #define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */ 1368 #define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */ 1369 1370 /* 1371 * R657 (0x291) - Mic Detect 2 1372 */ 1373 #define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */ 1374 #define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */ 1375 #define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */ 1376 1377 /* 1378 * R658 (0x292) - Mic Detect 3 1379 */ 1380 #define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */ 1381 #define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */ 1382 #define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */ 1383 #define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */ 1384 #define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */ 1385 #define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */ 1386 #define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */ 1387 #define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */ 1388 #define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */ 1389 #define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */ 1390 #define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */ 1391 1392 /* 1393 * R699 (0x2BB) - Misc Control 1394 */ 1395 #define WM5100_HPCOM_SRC 0x200 /* HPCOM_SRC */ 1396 #define WM5100_HPCOM_SRC_SHIFT 9 /* HPCOM_SRC */ 1397 1398 /* 1399 * R769 (0x301) - Input Enables 1400 */ 1401 #define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */ 1402 #define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ 1403 #define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ 1404 #define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */ 1405 #define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */ 1406 #define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */ 1407 #define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */ 1408 #define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */ 1409 #define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */ 1410 #define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 1411 #define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 1412 #define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 1413 #define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */ 1414 #define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 1415 #define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 1416 #define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 1417 #define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */ 1418 #define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 1419 #define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 1420 #define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 1421 #define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */ 1422 #define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 1423 #define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 1424 #define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 1425 #define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */ 1426 #define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 1427 #define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 1428 #define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 1429 #define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */ 1430 #define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 1431 #define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 1432 #define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 1433 1434 /* 1435 * R770 (0x302) - Input Enables Status 1436 */ 1437 #define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */ 1438 #define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */ 1439 #define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */ 1440 #define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */ 1441 #define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */ 1442 #define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */ 1443 #define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */ 1444 #define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */ 1445 #define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */ 1446 #define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */ 1447 #define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */ 1448 #define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */ 1449 #define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */ 1450 #define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */ 1451 #define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */ 1452 #define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */ 1453 #define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */ 1454 #define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */ 1455 #define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */ 1456 #define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */ 1457 #define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */ 1458 #define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */ 1459 #define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */ 1460 #define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */ 1461 #define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */ 1462 #define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */ 1463 #define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */ 1464 #define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */ 1465 #define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */ 1466 #define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */ 1467 #define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */ 1468 #define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */ 1469 1470 /* 1471 * R784 (0x310) - IN1L Control 1472 */ 1473 #define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */ 1474 #define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */ 1475 #define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */ 1476 #define WM5100_IN1_OSR 0x2000 /* IN1_OSR */ 1477 #define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 1478 #define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */ 1479 #define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */ 1480 #define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 1481 #define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 1482 #define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 1483 #define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 1484 #define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 1485 #define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 1486 #define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 1487 #define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 1488 #define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 1489 1490 /* 1491 * R785 (0x311) - IN1R Control 1492 */ 1493 #define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 1494 #define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 1495 #define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 1496 1497 /* 1498 * R786 (0x312) - IN2L Control 1499 */ 1500 #define WM5100_IN2_OSR 0x2000 /* IN2_OSR */ 1501 #define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 1502 #define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */ 1503 #define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */ 1504 #define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 1505 #define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 1506 #define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 1507 #define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 1508 #define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 1509 #define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 1510 #define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 1511 #define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 1512 #define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 1513 1514 /* 1515 * R787 (0x313) - IN2R Control 1516 */ 1517 #define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 1518 #define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 1519 #define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 1520 1521 /* 1522 * R788 (0x314) - IN3L Control 1523 */ 1524 #define WM5100_IN3_OSR 0x2000 /* IN3_OSR */ 1525 #define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 1526 #define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */ 1527 #define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */ 1528 #define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 1529 #define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 1530 #define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 1531 #define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 1532 #define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 1533 #define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 1534 #define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 1535 #define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 1536 #define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 1537 1538 /* 1539 * R789 (0x315) - IN3R Control 1540 */ 1541 #define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 1542 #define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 1543 #define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 1544 1545 /* 1546 * R790 (0x316) - IN4L Control 1547 */ 1548 #define WM5100_IN4_OSR 0x2000 /* IN4_OSR */ 1549 #define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */ 1550 #define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */ 1551 #define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */ 1552 #define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */ 1553 #define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */ 1554 #define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */ 1555 #define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */ 1556 #define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */ 1557 #define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */ 1558 #define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */ 1559 #define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */ 1560 #define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */ 1561 1562 /* 1563 * R791 (0x317) - IN4R Control 1564 */ 1565 #define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */ 1566 #define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */ 1567 #define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */ 1568 1569 /* 1570 * R792 (0x318) - RXANC_SRC 1571 */ 1572 #define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 1573 #define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 1574 #define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 1575 1576 /* 1577 * R793 (0x319) - Input Volume Ramp 1578 */ 1579 #define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 1580 #define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 1581 #define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 1582 #define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 1583 #define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 1584 #define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 1585 1586 /* 1587 * R800 (0x320) - ADC Digital Volume 1L 1588 */ 1589 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1590 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1591 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1592 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1593 #define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 1594 #define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 1595 #define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 1596 #define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1597 #define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */ 1598 #define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */ 1599 #define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */ 1600 1601 /* 1602 * R801 (0x321) - ADC Digital Volume 1R 1603 */ 1604 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1605 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1606 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1607 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1608 #define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 1609 #define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 1610 #define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 1611 #define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1612 #define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */ 1613 #define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */ 1614 #define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */ 1615 1616 /* 1617 * R802 (0x322) - ADC Digital Volume 2L 1618 */ 1619 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1620 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1621 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1622 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1623 #define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 1624 #define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 1625 #define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 1626 #define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1627 #define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */ 1628 #define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */ 1629 #define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */ 1630 1631 /* 1632 * R803 (0x323) - ADC Digital Volume 2R 1633 */ 1634 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1635 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1636 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1637 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1638 #define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 1639 #define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 1640 #define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 1641 #define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1642 #define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */ 1643 #define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */ 1644 #define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */ 1645 1646 /* 1647 * R804 (0x324) - ADC Digital Volume 3L 1648 */ 1649 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1650 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1651 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1652 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1653 #define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 1654 #define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 1655 #define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 1656 #define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 1657 #define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */ 1658 #define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */ 1659 #define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */ 1660 1661 /* 1662 * R805 (0x325) - ADC Digital Volume 3R 1663 */ 1664 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1665 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1666 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1667 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1668 #define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 1669 #define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 1670 #define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 1671 #define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 1672 #define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */ 1673 #define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */ 1674 #define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */ 1675 1676 /* 1677 * R806 (0x326) - ADC Digital Volume 4L 1678 */ 1679 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1680 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1681 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1682 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1683 #define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */ 1684 #define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */ 1685 #define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */ 1686 #define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */ 1687 #define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */ 1688 #define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */ 1689 #define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */ 1690 1691 /* 1692 * R807 (0x327) - ADC Digital Volume 4R 1693 */ 1694 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1695 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1696 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1697 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1698 #define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */ 1699 #define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */ 1700 #define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */ 1701 #define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */ 1702 #define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */ 1703 #define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */ 1704 #define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */ 1705 1706 /* 1707 * R1025 (0x401) - Output Enables 2 1708 */ 1709 #define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */ 1710 #define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ 1711 #define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ 1712 #define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */ 1713 #define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */ 1714 #define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */ 1715 #define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */ 1716 #define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */ 1717 #define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */ 1718 #define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */ 1719 #define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */ 1720 #define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */ 1721 #define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */ 1722 #define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */ 1723 #define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */ 1724 #define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */ 1725 #define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */ 1726 #define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */ 1727 #define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */ 1728 #define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */ 1729 #define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */ 1730 #define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */ 1731 #define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */ 1732 #define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */ 1733 1734 /* 1735 * R1026 (0x402) - Output Status 1 1736 */ 1737 #define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */ 1738 #define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */ 1739 #define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */ 1740 #define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */ 1741 #define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */ 1742 #define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */ 1743 #define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */ 1744 #define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */ 1745 #define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */ 1746 #define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */ 1747 #define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */ 1748 #define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */ 1749 #define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */ 1750 #define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */ 1751 #define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */ 1752 #define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */ 1753 #define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */ 1754 #define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */ 1755 #define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */ 1756 #define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */ 1757 #define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */ 1758 #define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */ 1759 #define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */ 1760 #define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */ 1761 1762 /* 1763 * R1027 (0x403) - Output Status 2 1764 */ 1765 #define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */ 1766 #define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */ 1767 #define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */ 1768 #define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */ 1769 #define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */ 1770 #define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */ 1771 #define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */ 1772 #define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */ 1773 #define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */ 1774 #define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */ 1775 #define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */ 1776 #define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */ 1777 #define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */ 1778 #define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */ 1779 #define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */ 1780 #define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */ 1781 #define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */ 1782 #define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */ 1783 #define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */ 1784 #define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */ 1785 #define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */ 1786 #define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */ 1787 #define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */ 1788 #define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */ 1789 1790 /* 1791 * R1032 (0x408) - Channel Enables 1 1792 */ 1793 #define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */ 1794 #define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */ 1795 #define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */ 1796 #define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */ 1797 #define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */ 1798 #define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */ 1799 #define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */ 1800 #define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */ 1801 #define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */ 1802 #define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */ 1803 #define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */ 1804 #define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */ 1805 #define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */ 1806 #define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */ 1807 #define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */ 1808 #define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */ 1809 #define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */ 1810 #define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */ 1811 #define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */ 1812 #define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ 1813 #define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */ 1814 #define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ 1815 #define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ 1816 #define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ 1817 1818 /* 1819 * R1040 (0x410) - Out Volume 1L 1820 */ 1821 #define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */ 1822 #define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */ 1823 #define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */ 1824 #define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */ 1825 #define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 1826 #define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 1827 #define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 1828 #define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */ 1829 #define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */ 1830 #define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */ 1831 #define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */ 1832 #define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1833 #define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1834 #define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1835 #define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1836 #define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1837 #define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1838 #define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1839 1840 /* 1841 * R1041 (0x411) - Out Volume 1R 1842 */ 1843 #define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1844 #define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1845 #define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1846 #define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1847 #define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1848 #define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1849 #define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1850 1851 /* 1852 * R1042 (0x412) - DAC Volume Limit 1L 1853 */ 1854 #define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */ 1855 #define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ 1856 #define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ 1857 1858 /* 1859 * R1043 (0x413) - DAC Volume Limit 1R 1860 */ 1861 #define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */ 1862 #define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */ 1863 #define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */ 1864 1865 /* 1866 * R1044 (0x414) - Out Volume 2L 1867 */ 1868 #define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */ 1869 #define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1870 #define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1871 #define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1872 #define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */ 1873 #define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */ 1874 #define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */ 1875 #define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */ 1876 #define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1877 #define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1878 #define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1879 #define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1880 #define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */ 1881 #define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */ 1882 #define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */ 1883 1884 /* 1885 * R1045 (0x415) - Out Volume 2R 1886 */ 1887 #define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1888 #define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1889 #define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1890 #define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1891 #define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */ 1892 #define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */ 1893 #define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */ 1894 1895 /* 1896 * R1046 (0x416) - DAC Volume Limit 2L 1897 */ 1898 #define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */ 1899 #define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ 1900 #define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ 1901 1902 /* 1903 * R1047 (0x417) - DAC Volume Limit 2R 1904 */ 1905 #define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */ 1906 #define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */ 1907 #define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */ 1908 1909 /* 1910 * R1048 (0x418) - Out Volume 3L 1911 */ 1912 #define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */ 1913 #define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */ 1914 #define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */ 1915 #define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */ 1916 #define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */ 1917 #define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */ 1918 #define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */ 1919 #define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */ 1920 #define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */ 1921 #define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */ 1922 #define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */ 1923 #define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */ 1924 #define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */ 1925 #define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */ 1926 #define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */ 1927 1928 /* 1929 * R1049 (0x419) - Out Volume 3R 1930 */ 1931 #define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */ 1932 #define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */ 1933 #define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */ 1934 #define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */ 1935 #define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */ 1936 #define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */ 1937 #define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */ 1938 1939 /* 1940 * R1050 (0x41A) - DAC Volume Limit 3L 1941 */ 1942 #define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */ 1943 #define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */ 1944 #define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */ 1945 1946 /* 1947 * R1051 (0x41B) - DAC Volume Limit 3R 1948 */ 1949 #define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */ 1950 #define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */ 1951 #define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */ 1952 1953 /* 1954 * R1052 (0x41C) - Out Volume 4L 1955 */ 1956 #define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */ 1957 #define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */ 1958 #define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */ 1959 #define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */ 1960 #define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */ 1961 #define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */ 1962 #define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */ 1963 #define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */ 1964 #define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */ 1965 #define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */ 1966 #define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */ 1967 1968 /* 1969 * R1053 (0x41D) - Out Volume 4R 1970 */ 1971 #define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */ 1972 #define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */ 1973 #define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */ 1974 #define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */ 1975 #define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */ 1976 #define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */ 1977 #define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */ 1978 1979 /* 1980 * R1054 (0x41E) - DAC Volume Limit 5L 1981 */ 1982 #define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */ 1983 #define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */ 1984 #define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */ 1985 #define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */ 1986 #define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */ 1987 #define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */ 1988 #define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */ 1989 #define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */ 1990 #define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */ 1991 #define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */ 1992 #define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */ 1993 1994 /* 1995 * R1055 (0x41F) - DAC Volume Limit 5R 1996 */ 1997 #define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */ 1998 #define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */ 1999 #define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */ 2000 #define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */ 2001 #define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */ 2002 #define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */ 2003 #define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */ 2004 2005 /* 2006 * R1056 (0x420) - DAC Volume Limit 6L 2007 */ 2008 #define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */ 2009 #define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */ 2010 #define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */ 2011 #define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */ 2012 #define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */ 2013 #define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */ 2014 #define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */ 2015 #define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */ 2016 #define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */ 2017 #define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */ 2018 #define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */ 2019 2020 /* 2021 * R1057 (0x421) - DAC Volume Limit 6R 2022 */ 2023 #define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */ 2024 #define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */ 2025 #define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */ 2026 #define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */ 2027 #define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */ 2028 #define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */ 2029 #define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */ 2030 2031 /* 2032 * R1088 (0x440) - DAC AEC Control 1 2033 */ 2034 #define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 2035 #define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */ 2036 #define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */ 2037 #define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */ 2038 #define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */ 2039 #define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */ 2040 #define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */ 2041 #define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */ 2042 #define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */ 2043 #define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */ 2044 #define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 2045 2046 /* 2047 * R1089 (0x441) - Output Volume Ramp 2048 */ 2049 #define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 2050 #define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 2051 #define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 2052 #define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 2053 #define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 2054 #define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 2055 2056 /* 2057 * R1152 (0x480) - DAC Digital Volume 1L 2058 */ 2059 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2060 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2061 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2062 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2063 #define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 2064 #define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 2065 #define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 2066 #define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 2067 #define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 2068 #define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 2069 #define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 2070 2071 /* 2072 * R1153 (0x481) - DAC Digital Volume 1R 2073 */ 2074 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2075 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2076 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2077 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2078 #define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 2079 #define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 2080 #define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 2081 #define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 2082 #define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 2083 #define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 2084 #define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 2085 2086 /* 2087 * R1154 (0x482) - DAC Digital Volume 2L 2088 */ 2089 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2090 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2091 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2092 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2093 #define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 2094 #define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 2095 #define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 2096 #define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 2097 #define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 2098 #define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 2099 #define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 2100 2101 /* 2102 * R1155 (0x483) - DAC Digital Volume 2R 2103 */ 2104 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2105 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2106 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2107 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2108 #define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 2109 #define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 2110 #define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 2111 #define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 2112 #define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 2113 #define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 2114 #define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 2115 2116 /* 2117 * R1156 (0x484) - DAC Digital Volume 3L 2118 */ 2119 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2120 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2121 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2122 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2123 #define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */ 2124 #define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */ 2125 #define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */ 2126 #define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */ 2127 #define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */ 2128 #define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */ 2129 #define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */ 2130 2131 /* 2132 * R1157 (0x485) - DAC Digital Volume 3R 2133 */ 2134 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2135 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2136 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2137 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2138 #define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */ 2139 #define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */ 2140 #define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */ 2141 #define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */ 2142 #define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */ 2143 #define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */ 2144 #define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */ 2145 2146 /* 2147 * R1158 (0x486) - DAC Digital Volume 4L 2148 */ 2149 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2150 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2151 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2152 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2153 #define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */ 2154 #define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */ 2155 #define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */ 2156 #define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */ 2157 #define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */ 2158 #define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */ 2159 #define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */ 2160 2161 /* 2162 * R1159 (0x487) - DAC Digital Volume 4R 2163 */ 2164 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2165 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2166 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2167 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2168 #define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */ 2169 #define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */ 2170 #define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */ 2171 #define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */ 2172 #define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */ 2173 #define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */ 2174 #define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */ 2175 2176 /* 2177 * R1160 (0x488) - DAC Digital Volume 5L 2178 */ 2179 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2180 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2181 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2182 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2183 #define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */ 2184 #define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */ 2185 #define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */ 2186 #define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */ 2187 #define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */ 2188 #define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */ 2189 #define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */ 2190 2191 /* 2192 * R1161 (0x489) - DAC Digital Volume 5R 2193 */ 2194 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2195 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2196 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2197 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2198 #define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */ 2199 #define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */ 2200 #define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */ 2201 #define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */ 2202 #define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */ 2203 #define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */ 2204 #define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */ 2205 2206 /* 2207 * R1162 (0x48A) - DAC Digital Volume 6L 2208 */ 2209 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2210 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2211 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2212 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2213 #define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */ 2214 #define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */ 2215 #define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */ 2216 #define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */ 2217 #define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */ 2218 #define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */ 2219 #define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */ 2220 2221 /* 2222 * R1163 (0x48B) - DAC Digital Volume 6R 2223 */ 2224 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2225 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2226 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2227 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2228 #define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */ 2229 #define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */ 2230 #define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */ 2231 #define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */ 2232 #define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */ 2233 #define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */ 2234 #define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */ 2235 2236 /* 2237 * R1216 (0x4C0) - PDM SPK1 CTRL 1 2238 */ 2239 #define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 2240 #define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 2241 #define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 2242 #define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 2243 #define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 2244 #define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 2245 #define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 2246 #define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 2247 #define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 2248 #define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 2249 #define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 2250 #define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 2251 #define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 2252 #define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 2253 #define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 2254 2255 /* 2256 * R1217 (0x4C1) - PDM SPK1 CTRL 2 2257 */ 2258 #define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */ 2259 #define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 2260 #define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 2261 #define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 2262 2263 /* 2264 * R1218 (0x4C2) - PDM SPK2 CTRL 1 2265 */ 2266 #define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */ 2267 #define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */ 2268 #define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */ 2269 #define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 2270 #define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */ 2271 #define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */ 2272 #define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */ 2273 #define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 2274 #define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */ 2275 #define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */ 2276 #define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */ 2277 #define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */ 2278 #define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 2279 #define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 2280 #define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 2281 2282 /* 2283 * R1219 (0x4C3) - PDM SPK2 CTRL 2 2284 */ 2285 #define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */ 2286 #define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */ 2287 #define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ 2288 #define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ 2289 2290 /* 2291 * R1280 (0x500) - Audio IF 1_1 2292 */ 2293 #define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */ 2294 #define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */ 2295 #define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */ 2296 #define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2297 #define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */ 2298 #define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */ 2299 #define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */ 2300 #define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 2301 #define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */ 2302 #define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */ 2303 #define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */ 2304 #define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 2305 #define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */ 2306 #define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */ 2307 #define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */ 2308 2309 /* 2310 * R1281 (0x501) - Audio IF 1_2 2311 */ 2312 #define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 2313 #define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 2314 #define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 2315 #define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 2316 #define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 2317 #define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 2318 #define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 2319 #define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 2320 #define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 2321 #define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 2322 #define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 2323 #define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 2324 #define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 2325 #define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 2326 #define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 2327 #define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 2328 #define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 2329 #define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 2330 #define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 2331 #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 2332 2333 /* 2334 * R1282 (0x502) - Audio IF 1_3 2335 */ 2336 #define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 2337 #define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 2338 #define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 2339 #define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 2340 #define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 2341 #define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 2342 #define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 2343 #define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 2344 #define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 2345 #define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 2346 #define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 2347 #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 2348 2349 /* 2350 * R1283 (0x503) - Audio IF 1_4 2351 */ 2352 #define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */ 2353 #define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 2354 #define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 2355 #define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2356 #define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */ 2357 #define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */ 2358 #define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */ 2359 2360 /* 2361 * R1284 (0x504) - Audio IF 1_5 2362 */ 2363 #define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 2364 #define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 2365 #define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 2366 2367 /* 2368 * R1285 (0x505) - Audio IF 1_6 2369 */ 2370 #define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */ 2371 #define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */ 2372 #define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */ 2373 2374 /* 2375 * R1286 (0x506) - Audio IF 1_7 2376 */ 2377 #define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */ 2378 #define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */ 2379 #define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */ 2380 2381 /* 2382 * R1287 (0x507) - Audio IF 1_8 2383 */ 2384 #define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 2385 #define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 2386 #define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 2387 #define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 2388 #define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 2389 #define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 2390 2391 /* 2392 * R1288 (0x508) - Audio IF 1_9 2393 */ 2394 #define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 2395 #define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 2396 #define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 2397 #define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 2398 #define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 2399 #define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 2400 2401 /* 2402 * R1289 (0x509) - Audio IF 1_10 2403 */ 2404 #define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 2405 #define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 2406 #define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 2407 2408 /* 2409 * R1290 (0x50A) - Audio IF 1_11 2410 */ 2411 #define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 2412 #define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 2413 #define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 2414 2415 /* 2416 * R1291 (0x50B) - Audio IF 1_12 2417 */ 2418 #define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 2419 #define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 2420 #define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 2421 2422 /* 2423 * R1292 (0x50C) - Audio IF 1_13 2424 */ 2425 #define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 2426 #define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 2427 #define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 2428 2429 /* 2430 * R1293 (0x50D) - Audio IF 1_14 2431 */ 2432 #define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 2433 #define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 2434 #define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 2435 2436 /* 2437 * R1294 (0x50E) - Audio IF 1_15 2438 */ 2439 #define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 2440 #define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 2441 #define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 2442 2443 /* 2444 * R1295 (0x50F) - Audio IF 1_16 2445 */ 2446 #define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */ 2447 #define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */ 2448 #define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */ 2449 2450 /* 2451 * R1296 (0x510) - Audio IF 1_17 2452 */ 2453 #define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */ 2454 #define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */ 2455 #define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */ 2456 2457 /* 2458 * R1297 (0x511) - Audio IF 1_18 2459 */ 2460 #define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 2461 #define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 2462 #define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 2463 2464 /* 2465 * R1298 (0x512) - Audio IF 1_19 2466 */ 2467 #define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 2468 #define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 2469 #define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 2470 2471 /* 2472 * R1299 (0x513) - Audio IF 1_20 2473 */ 2474 #define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 2475 #define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 2476 #define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 2477 2478 /* 2479 * R1300 (0x514) - Audio IF 1_21 2480 */ 2481 #define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 2482 #define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 2483 #define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 2484 2485 /* 2486 * R1301 (0x515) - Audio IF 1_22 2487 */ 2488 #define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 2489 #define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 2490 #define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 2491 2492 /* 2493 * R1302 (0x516) - Audio IF 1_23 2494 */ 2495 #define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 2496 #define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 2497 #define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 2498 2499 /* 2500 * R1303 (0x517) - Audio IF 1_24 2501 */ 2502 #define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */ 2503 #define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */ 2504 #define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */ 2505 2506 /* 2507 * R1304 (0x518) - Audio IF 1_25 2508 */ 2509 #define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */ 2510 #define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */ 2511 #define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */ 2512 2513 /* 2514 * R1305 (0x519) - Audio IF 1_26 2515 */ 2516 #define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */ 2517 #define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */ 2518 #define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */ 2519 #define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */ 2520 #define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */ 2521 #define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */ 2522 #define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */ 2523 #define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */ 2524 #define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 2525 #define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 2526 #define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 2527 #define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 2528 #define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 2529 #define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 2530 #define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 2531 #define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 2532 #define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 2533 #define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 2534 #define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 2535 #define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 2536 #define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 2537 #define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 2538 #define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 2539 #define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 2540 #define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 2541 #define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 2542 #define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 2543 #define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 2544 #define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 2545 #define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 2546 #define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 2547 #define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 2548 2549 /* 2550 * R1306 (0x51A) - Audio IF 1_27 2551 */ 2552 #define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */ 2553 #define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */ 2554 #define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */ 2555 #define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */ 2556 #define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */ 2557 #define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */ 2558 #define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */ 2559 #define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */ 2560 #define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */ 2561 #define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */ 2562 #define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */ 2563 #define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 2564 #define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */ 2565 #define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */ 2566 #define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */ 2567 #define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 2568 #define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */ 2569 #define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */ 2570 #define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */ 2571 #define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 2572 #define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */ 2573 #define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */ 2574 #define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */ 2575 #define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 2576 #define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */ 2577 #define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */ 2578 #define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */ 2579 #define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 2580 #define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */ 2581 #define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */ 2582 #define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */ 2583 #define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 2584 2585 /* 2586 * R1344 (0x540) - Audio IF 2_1 2587 */ 2588 #define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */ 2589 #define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */ 2590 #define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */ 2591 #define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2592 #define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */ 2593 #define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */ 2594 #define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */ 2595 #define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2596 #define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */ 2597 #define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */ 2598 #define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */ 2599 #define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2600 #define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */ 2601 #define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */ 2602 #define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */ 2603 2604 /* 2605 * R1345 (0x541) - Audio IF 2_2 2606 */ 2607 #define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */ 2608 #define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */ 2609 #define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */ 2610 #define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2611 #define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */ 2612 #define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */ 2613 #define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */ 2614 #define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */ 2615 #define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2616 #define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2617 #define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2618 #define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2619 #define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2620 #define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2621 #define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2622 #define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2623 #define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2624 #define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2625 #define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2626 #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2627 2628 /* 2629 * R1346 (0x542) - Audio IF 2_3 2630 */ 2631 #define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2632 #define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2633 #define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2634 #define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2635 #define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2636 #define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2637 #define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2638 #define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2639 #define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2640 #define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2641 #define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2642 #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2643 2644 /* 2645 * R1347 (0x543) - Audio IF 2_4 2646 */ 2647 #define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */ 2648 #define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */ 2649 #define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */ 2650 #define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2651 #define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */ 2652 #define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */ 2653 #define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */ 2654 2655 /* 2656 * R1348 (0x544) - Audio IF 2_5 2657 */ 2658 #define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */ 2659 #define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */ 2660 #define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */ 2661 2662 /* 2663 * R1349 (0x545) - Audio IF 2_6 2664 */ 2665 #define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */ 2666 #define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */ 2667 #define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */ 2668 2669 /* 2670 * R1350 (0x546) - Audio IF 2_7 2671 */ 2672 #define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */ 2673 #define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */ 2674 #define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */ 2675 2676 /* 2677 * R1351 (0x547) - Audio IF 2_8 2678 */ 2679 #define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */ 2680 #define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */ 2681 #define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */ 2682 #define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2683 #define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2684 #define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2685 2686 /* 2687 * R1352 (0x548) - Audio IF 2_9 2688 */ 2689 #define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */ 2690 #define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */ 2691 #define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */ 2692 #define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2693 #define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2694 #define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2695 2696 /* 2697 * R1353 (0x549) - Audio IF 2_10 2698 */ 2699 #define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */ 2700 #define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */ 2701 #define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */ 2702 2703 /* 2704 * R1354 (0x54A) - Audio IF 2_11 2705 */ 2706 #define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */ 2707 #define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ 2708 #define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ 2709 2710 /* 2711 * R1361 (0x551) - Audio IF 2_18 2712 */ 2713 #define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ 2714 #define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */ 2715 #define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */ 2716 2717 /* 2718 * R1362 (0x552) - Audio IF 2_19 2719 */ 2720 #define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */ 2721 #define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ 2722 #define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ 2723 2724 /* 2725 * R1369 (0x559) - Audio IF 2_26 2726 */ 2727 #define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ 2728 #define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ 2729 #define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ 2730 #define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */ 2731 #define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */ 2732 #define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */ 2733 #define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */ 2734 #define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */ 2735 2736 /* 2737 * R1370 (0x55A) - Audio IF 2_27 2738 */ 2739 #define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ 2740 #define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ 2741 #define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ 2742 #define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */ 2743 #define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */ 2744 #define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */ 2745 #define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */ 2746 #define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */ 2747 2748 /* 2749 * R1408 (0x580) - Audio IF 3_1 2750 */ 2751 #define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */ 2752 #define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */ 2753 #define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */ 2754 #define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */ 2755 #define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */ 2756 #define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */ 2757 #define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */ 2758 #define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */ 2759 #define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */ 2760 #define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */ 2761 #define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */ 2762 #define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */ 2763 #define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */ 2764 #define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */ 2765 #define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */ 2766 2767 /* 2768 * R1409 (0x581) - Audio IF 3_2 2769 */ 2770 #define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */ 2771 #define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */ 2772 #define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */ 2773 #define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */ 2774 #define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */ 2775 #define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */ 2776 #define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */ 2777 #define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */ 2778 #define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */ 2779 #define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */ 2780 #define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */ 2781 #define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */ 2782 #define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */ 2783 #define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */ 2784 #define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */ 2785 #define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */ 2786 #define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */ 2787 #define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */ 2788 #define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */ 2789 #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */ 2790 2791 /* 2792 * R1410 (0x582) - Audio IF 3_3 2793 */ 2794 #define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */ 2795 #define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */ 2796 #define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */ 2797 #define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */ 2798 #define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */ 2799 #define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */ 2800 #define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */ 2801 #define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */ 2802 #define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */ 2803 #define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */ 2804 #define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */ 2805 #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */ 2806 2807 /* 2808 * R1411 (0x583) - Audio IF 3_4 2809 */ 2810 #define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */ 2811 #define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */ 2812 #define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */ 2813 #define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 2814 #define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */ 2815 #define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */ 2816 #define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */ 2817 2818 /* 2819 * R1412 (0x584) - Audio IF 3_5 2820 */ 2821 #define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */ 2822 #define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */ 2823 #define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */ 2824 2825 /* 2826 * R1413 (0x585) - Audio IF 3_6 2827 */ 2828 #define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */ 2829 #define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */ 2830 #define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */ 2831 2832 /* 2833 * R1414 (0x586) - Audio IF 3_7 2834 */ 2835 #define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */ 2836 #define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */ 2837 #define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */ 2838 2839 /* 2840 * R1415 (0x587) - Audio IF 3_8 2841 */ 2842 #define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */ 2843 #define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */ 2844 #define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */ 2845 #define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */ 2846 #define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */ 2847 #define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */ 2848 2849 /* 2850 * R1416 (0x588) - Audio IF 3_9 2851 */ 2852 #define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */ 2853 #define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */ 2854 #define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */ 2855 #define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */ 2856 #define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */ 2857 #define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */ 2858 2859 /* 2860 * R1417 (0x589) - Audio IF 3_10 2861 */ 2862 #define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */ 2863 #define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */ 2864 #define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */ 2865 2866 /* 2867 * R1418 (0x58A) - Audio IF 3_11 2868 */ 2869 #define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */ 2870 #define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */ 2871 #define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */ 2872 2873 /* 2874 * R1425 (0x591) - Audio IF 3_18 2875 */ 2876 #define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */ 2877 #define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */ 2878 #define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */ 2879 2880 /* 2881 * R1426 (0x592) - Audio IF 3_19 2882 */ 2883 #define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */ 2884 #define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */ 2885 #define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */ 2886 2887 /* 2888 * R1433 (0x599) - Audio IF 3_26 2889 */ 2890 #define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */ 2891 #define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */ 2892 #define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */ 2893 #define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */ 2894 #define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */ 2895 #define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */ 2896 #define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */ 2897 #define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */ 2898 2899 /* 2900 * R1434 (0x59A) - Audio IF 3_27 2901 */ 2902 #define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */ 2903 #define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */ 2904 #define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */ 2905 #define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */ 2906 #define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */ 2907 #define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */ 2908 #define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */ 2909 #define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */ 2910 2911 #define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */ 2912 #define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */ 2913 #define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */ 2914 2915 /* 2916 * R3072 (0xC00) - GPIO CTRL 1 2917 */ 2918 #define WM5100_GP1_DIR 0x8000 /* GP1_DIR */ 2919 #define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 2920 #define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */ 2921 #define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */ 2922 #define WM5100_GP1_PU 0x4000 /* GP1_PU */ 2923 #define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */ 2924 #define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */ 2925 #define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */ 2926 #define WM5100_GP1_PD 0x2000 /* GP1_PD */ 2927 #define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */ 2928 #define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */ 2929 #define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */ 2930 #define WM5100_GP1_POL 0x0400 /* GP1_POL */ 2931 #define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */ 2932 #define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */ 2933 #define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */ 2934 #define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 2935 #define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 2936 #define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 2937 #define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 2938 #define WM5100_GP1_DB 0x0100 /* GP1_DB */ 2939 #define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */ 2940 #define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */ 2941 #define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */ 2942 #define WM5100_GP1_LVL 0x0040 /* GP1_LVL */ 2943 #define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 2944 #define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */ 2945 #define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */ 2946 #define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 2947 #define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 2948 #define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 2949 2950 /* 2951 * R3073 (0xC01) - GPIO CTRL 2 2952 */ 2953 #define WM5100_GP2_DIR 0x8000 /* GP2_DIR */ 2954 #define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 2955 #define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */ 2956 #define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */ 2957 #define WM5100_GP2_PU 0x4000 /* GP2_PU */ 2958 #define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */ 2959 #define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */ 2960 #define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */ 2961 #define WM5100_GP2_PD 0x2000 /* GP2_PD */ 2962 #define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */ 2963 #define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */ 2964 #define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */ 2965 #define WM5100_GP2_POL 0x0400 /* GP2_POL */ 2966 #define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */ 2967 #define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */ 2968 #define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */ 2969 #define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 2970 #define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 2971 #define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 2972 #define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 2973 #define WM5100_GP2_DB 0x0100 /* GP2_DB */ 2974 #define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */ 2975 #define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */ 2976 #define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */ 2977 #define WM5100_GP2_LVL 0x0040 /* GP2_LVL */ 2978 #define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 2979 #define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */ 2980 #define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */ 2981 #define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 2982 #define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 2983 #define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 2984 2985 /* 2986 * R3074 (0xC02) - GPIO CTRL 3 2987 */ 2988 #define WM5100_GP3_DIR 0x8000 /* GP3_DIR */ 2989 #define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 2990 #define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */ 2991 #define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */ 2992 #define WM5100_GP3_PU 0x4000 /* GP3_PU */ 2993 #define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */ 2994 #define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */ 2995 #define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */ 2996 #define WM5100_GP3_PD 0x2000 /* GP3_PD */ 2997 #define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */ 2998 #define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */ 2999 #define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */ 3000 #define WM5100_GP3_POL 0x0400 /* GP3_POL */ 3001 #define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */ 3002 #define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */ 3003 #define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */ 3004 #define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3005 #define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3006 #define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3007 #define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3008 #define WM5100_GP3_DB 0x0100 /* GP3_DB */ 3009 #define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */ 3010 #define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */ 3011 #define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */ 3012 #define WM5100_GP3_LVL 0x0040 /* GP3_LVL */ 3013 #define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3014 #define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3015 #define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3016 #define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 3017 #define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 3018 #define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 3019 3020 /* 3021 * R3075 (0xC03) - GPIO CTRL 4 3022 */ 3023 #define WM5100_GP4_DIR 0x8000 /* GP4_DIR */ 3024 #define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3025 #define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3026 #define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3027 #define WM5100_GP4_PU 0x4000 /* GP4_PU */ 3028 #define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */ 3029 #define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */ 3030 #define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */ 3031 #define WM5100_GP4_PD 0x2000 /* GP4_PD */ 3032 #define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */ 3033 #define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */ 3034 #define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */ 3035 #define WM5100_GP4_POL 0x0400 /* GP4_POL */ 3036 #define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */ 3037 #define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */ 3038 #define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */ 3039 #define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3040 #define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3041 #define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3042 #define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3043 #define WM5100_GP4_DB 0x0100 /* GP4_DB */ 3044 #define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */ 3045 #define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */ 3046 #define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */ 3047 #define WM5100_GP4_LVL 0x0040 /* GP4_LVL */ 3048 #define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3049 #define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3050 #define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3051 #define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 3052 #define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 3053 #define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 3054 3055 /* 3056 * R3076 (0xC04) - GPIO CTRL 5 3057 */ 3058 #define WM5100_GP5_DIR 0x8000 /* GP5_DIR */ 3059 #define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3060 #define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3061 #define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3062 #define WM5100_GP5_PU 0x4000 /* GP5_PU */ 3063 #define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */ 3064 #define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */ 3065 #define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */ 3066 #define WM5100_GP5_PD 0x2000 /* GP5_PD */ 3067 #define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */ 3068 #define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */ 3069 #define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */ 3070 #define WM5100_GP5_POL 0x0400 /* GP5_POL */ 3071 #define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */ 3072 #define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */ 3073 #define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */ 3074 #define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3075 #define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3076 #define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3077 #define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3078 #define WM5100_GP5_DB 0x0100 /* GP5_DB */ 3079 #define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */ 3080 #define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */ 3081 #define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */ 3082 #define WM5100_GP5_LVL 0x0040 /* GP5_LVL */ 3083 #define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3084 #define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3085 #define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3086 #define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */ 3087 #define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */ 3088 #define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */ 3089 3090 /* 3091 * R3077 (0xC05) - GPIO CTRL 6 3092 */ 3093 #define WM5100_GP6_DIR 0x8000 /* GP6_DIR */ 3094 #define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3095 #define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3096 #define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3097 #define WM5100_GP6_PU 0x4000 /* GP6_PU */ 3098 #define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */ 3099 #define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */ 3100 #define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */ 3101 #define WM5100_GP6_PD 0x2000 /* GP6_PD */ 3102 #define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */ 3103 #define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */ 3104 #define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */ 3105 #define WM5100_GP6_POL 0x0400 /* GP6_POL */ 3106 #define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */ 3107 #define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */ 3108 #define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */ 3109 #define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3110 #define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3111 #define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3112 #define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3113 #define WM5100_GP6_DB 0x0100 /* GP6_DB */ 3114 #define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */ 3115 #define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */ 3116 #define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */ 3117 #define WM5100_GP6_LVL 0x0040 /* GP6_LVL */ 3118 #define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3119 #define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3120 #define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3121 #define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */ 3122 #define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */ 3123 #define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */ 3124 3125 /* 3126 * R3107 (0xC23) - Misc Pad Ctrl 1 3127 */ 3128 #define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 3129 #define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 3130 #define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 3131 #define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3132 #define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */ 3133 #define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 3134 #define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 3135 #define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3136 #define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */ 3137 #define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 3138 #define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 3139 #define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3140 #define WM5100_RESET_PU 0x0002 /* RESET_PU */ 3141 #define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */ 3142 #define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */ 3143 #define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */ 3144 #define WM5100_ADDR_PD 0x0001 /* ADDR_PD */ 3145 #define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 3146 #define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */ 3147 #define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3148 3149 /* 3150 * R3108 (0xC24) - Misc Pad Ctrl 2 3151 */ 3152 #define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */ 3153 #define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */ 3154 #define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */ 3155 #define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */ 3156 #define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */ 3157 #define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */ 3158 #define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */ 3159 #define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3160 #define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */ 3161 #define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */ 3162 #define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */ 3163 #define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3164 #define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */ 3165 #define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */ 3166 #define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */ 3167 #define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3168 3169 /* 3170 * R3109 (0xC25) - Misc Pad Ctrl 3 3171 */ 3172 #define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */ 3173 #define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */ 3174 #define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */ 3175 #define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */ 3176 #define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */ 3177 #define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */ 3178 #define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */ 3179 #define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */ 3180 #define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */ 3181 #define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */ 3182 #define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */ 3183 #define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */ 3184 #define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */ 3185 #define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */ 3186 #define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */ 3187 #define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */ 3188 #define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */ 3189 #define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */ 3190 #define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */ 3191 #define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */ 3192 #define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */ 3193 #define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */ 3194 #define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */ 3195 #define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */ 3196 3197 /* 3198 * R3110 (0xC26) - Misc Pad Ctrl 4 3199 */ 3200 #define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */ 3201 #define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */ 3202 #define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */ 3203 #define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */ 3204 #define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */ 3205 #define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */ 3206 #define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */ 3207 #define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */ 3208 #define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */ 3209 #define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */ 3210 #define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */ 3211 #define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */ 3212 #define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */ 3213 #define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */ 3214 #define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */ 3215 #define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */ 3216 #define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */ 3217 #define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */ 3218 #define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */ 3219 #define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */ 3220 #define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */ 3221 #define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */ 3222 #define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */ 3223 #define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */ 3224 3225 /* 3226 * R3111 (0xC27) - Misc Pad Ctrl 5 3227 */ 3228 #define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */ 3229 #define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */ 3230 #define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */ 3231 #define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */ 3232 #define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */ 3233 #define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */ 3234 #define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */ 3235 #define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */ 3236 #define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */ 3237 #define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */ 3238 #define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */ 3239 #define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */ 3240 #define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */ 3241 #define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */ 3242 #define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */ 3243 #define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */ 3244 #define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */ 3245 #define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */ 3246 #define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */ 3247 #define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */ 3248 #define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */ 3249 #define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */ 3250 #define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */ 3251 #define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */ 3252 3253 /* 3254 * R3112 (0xC28) - Misc GPIO 1 3255 */ 3256 #define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */ 3257 #define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */ 3258 #define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */ 3259 3260 /* 3261 * R3328 (0xD00) - Interrupt Status 1 3262 */ 3263 #define WM5100_GP6_EINT 0x0020 /* GP6_EINT */ 3264 #define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3265 #define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3266 #define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3267 #define WM5100_GP5_EINT 0x0010 /* GP5_EINT */ 3268 #define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3269 #define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3270 #define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3271 #define WM5100_GP4_EINT 0x0008 /* GP4_EINT */ 3272 #define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3273 #define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3274 #define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3275 #define WM5100_GP3_EINT 0x0004 /* GP3_EINT */ 3276 #define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3277 #define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3278 #define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3279 #define WM5100_GP2_EINT 0x0002 /* GP2_EINT */ 3280 #define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3281 #define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3282 #define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3283 #define WM5100_GP1_EINT 0x0001 /* GP1_EINT */ 3284 #define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3285 #define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3286 #define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3287 3288 /* 3289 * R3329 (0xD01) - Interrupt Status 2 3290 */ 3291 #define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */ 3292 #define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */ 3293 #define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */ 3294 #define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */ 3295 #define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */ 3296 #define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */ 3297 #define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */ 3298 #define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */ 3299 #define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */ 3300 #define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */ 3301 #define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */ 3302 #define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */ 3303 #define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */ 3304 #define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */ 3305 #define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */ 3306 #define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 3307 #define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */ 3308 #define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */ 3309 #define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */ 3310 #define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 3311 #define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */ 3312 #define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */ 3313 #define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */ 3314 #define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 3315 3316 /* 3317 * R3330 (0xD02) - Interrupt Status 3 3318 */ 3319 #define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3320 #define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3321 #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */ 3322 #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */ 3323 #define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */ 3324 #define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */ 3325 #define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */ 3326 #define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */ 3327 #define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */ 3328 #define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */ 3329 #define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */ 3330 #define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */ 3331 #define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */ 3332 #define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */ 3333 #define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */ 3334 #define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */ 3335 #define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */ 3336 #define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */ 3337 #define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */ 3338 #define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */ 3339 #define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */ 3340 #define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */ 3341 #define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */ 3342 #define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */ 3343 #define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */ 3344 #define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */ 3345 #define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */ 3346 #define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */ 3347 #define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3348 #define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3349 #define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3350 #define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3351 #define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3352 #define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3353 #define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3354 #define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3355 #define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */ 3356 #define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */ 3357 #define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */ 3358 #define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */ 3359 #define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3360 #define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3361 #define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */ 3362 #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */ 3363 3364 /* 3365 * R3331 (0xD03) - Interrupt Status 4 3366 */ 3367 #define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */ 3368 #define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */ 3369 #define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */ 3370 #define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */ 3371 #define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */ 3372 #define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */ 3373 #define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */ 3374 #define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */ 3375 #define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */ 3376 #define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */ 3377 #define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */ 3378 #define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */ 3379 #define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */ 3380 #define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */ 3381 #define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */ 3382 #define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */ 3383 #define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3384 #define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3385 #define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */ 3386 #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */ 3387 #define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3388 #define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3389 #define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */ 3390 #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */ 3391 #define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */ 3392 #define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */ 3393 #define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */ 3394 #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */ 3395 #define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3396 #define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3397 #define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */ 3398 #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */ 3399 #define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3400 #define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3401 #define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */ 3402 #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */ 3403 #define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3404 #define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3405 #define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */ 3406 #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */ 3407 #define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3408 #define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3409 #define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */ 3410 #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */ 3411 #define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3412 #define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3413 #define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */ 3414 #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */ 3415 #define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3416 #define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3417 #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */ 3418 #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */ 3419 #define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3420 #define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3421 #define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */ 3422 #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */ 3423 3424 /* 3425 * R3332 (0xD04) - Interrupt Raw Status 2 3426 */ 3427 #define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */ 3428 #define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */ 3429 #define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */ 3430 #define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */ 3431 #define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */ 3432 #define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */ 3433 #define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */ 3434 #define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */ 3435 #define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */ 3436 #define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */ 3437 #define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */ 3438 #define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */ 3439 #define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */ 3440 #define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */ 3441 #define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */ 3442 #define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */ 3443 #define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */ 3444 #define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */ 3445 #define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */ 3446 #define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */ 3447 #define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */ 3448 #define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */ 3449 #define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */ 3450 #define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */ 3451 3452 /* 3453 * R3333 (0xD05) - Interrupt Raw Status 3 3454 */ 3455 #define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3456 #define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3457 #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */ 3458 #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */ 3459 #define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ 3460 #define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ 3461 #define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ 3462 #define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ 3463 #define WM5100_HPDET_STS 0x2000 /* HPDET_STS */ 3464 #define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */ 3465 #define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */ 3466 #define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */ 3467 #define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */ 3468 #define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */ 3469 #define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */ 3470 #define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */ 3471 #define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */ 3472 #define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */ 3473 #define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */ 3474 #define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */ 3475 #define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */ 3476 #define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */ 3477 #define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */ 3478 #define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */ 3479 #define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 3480 #define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 3481 #define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 3482 #define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 3483 #define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 3484 #define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 3485 #define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 3486 #define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 3487 #define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */ 3488 #define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */ 3489 #define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */ 3490 #define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */ 3491 #define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3492 #define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3493 #define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */ 3494 #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */ 3495 3496 /* 3497 * R3334 (0xD06) - Interrupt Raw Status 4 3498 */ 3499 #define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */ 3500 #define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */ 3501 #define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */ 3502 #define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */ 3503 #define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */ 3504 #define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */ 3505 #define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */ 3506 #define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */ 3507 #define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */ 3508 #define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */ 3509 #define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */ 3510 #define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */ 3511 #define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */ 3512 #define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */ 3513 #define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */ 3514 #define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */ 3515 #define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3516 #define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3517 #define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */ 3518 #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */ 3519 #define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3520 #define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3521 #define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */ 3522 #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */ 3523 #define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */ 3524 #define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */ 3525 #define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */ 3526 #define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */ 3527 #define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3528 #define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3529 #define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */ 3530 #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */ 3531 #define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3532 #define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3533 #define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */ 3534 #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */ 3535 #define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3536 #define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3537 #define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */ 3538 #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ 3539 #define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3540 #define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3541 #define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */ 3542 #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */ 3543 #define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */ 3544 #define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */ 3545 #define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */ 3546 #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */ 3547 #define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */ 3548 #define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */ 3549 #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */ 3550 #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */ 3551 #define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3552 #define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3553 #define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ 3554 #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ 3555 3556 /* 3557 * R3335 (0xD07) - Interrupt Status 1 Mask 3558 */ 3559 #define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 3560 #define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 3561 #define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 3562 #define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 3563 #define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3564 #define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3565 #define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3566 #define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3567 #define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3568 #define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3569 #define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3570 #define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3571 #define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3572 #define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3573 #define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3574 #define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3575 #define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3576 #define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3577 #define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3578 #define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3579 #define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3580 #define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3581 #define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3582 #define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3583 3584 /* 3585 * R3336 (0xD08) - Interrupt Status 2 Mask 3586 */ 3587 #define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */ 3588 #define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */ 3589 #define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */ 3590 #define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */ 3591 #define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */ 3592 #define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */ 3593 #define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */ 3594 #define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */ 3595 #define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */ 3596 #define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */ 3597 #define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */ 3598 #define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */ 3599 #define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */ 3600 #define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */ 3601 #define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */ 3602 #define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 3603 #define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */ 3604 #define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */ 3605 #define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */ 3606 #define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 3607 #define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */ 3608 #define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */ 3609 #define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */ 3610 #define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 3611 3612 /* 3613 * R3337 (0xD09) - Interrupt Status 3 Mask 3614 */ 3615 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3616 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3617 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3618 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3619 #define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3620 #define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3621 #define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */ 3622 #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */ 3623 #define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */ 3624 #define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */ 3625 #define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */ 3626 #define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */ 3627 #define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */ 3628 #define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */ 3629 #define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */ 3630 #define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */ 3631 #define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */ 3632 #define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */ 3633 #define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */ 3634 #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */ 3635 #define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */ 3636 #define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */ 3637 #define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */ 3638 #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */ 3639 #define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */ 3640 #define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */ 3641 #define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */ 3642 #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */ 3643 #define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 3644 #define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 3645 #define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 3646 #define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 3647 #define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 3648 #define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 3649 #define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 3650 #define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 3651 #define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */ 3652 #define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */ 3653 #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */ 3654 #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */ 3655 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3656 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3657 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3658 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3659 3660 /* 3661 * R3338 (0xD0A) - Interrupt Status 4 Mask 3662 */ 3663 #define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */ 3664 #define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */ 3665 #define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */ 3666 #define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */ 3667 #define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */ 3668 #define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */ 3669 #define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */ 3670 #define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */ 3671 #define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */ 3672 #define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */ 3673 #define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */ 3674 #define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */ 3675 #define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */ 3676 #define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */ 3677 #define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */ 3678 #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */ 3679 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3680 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3681 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3682 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3683 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3684 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3685 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3686 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3687 #define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3688 #define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3689 #define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */ 3690 #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */ 3691 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3692 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3693 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */ 3694 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */ 3695 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3696 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3697 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */ 3698 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */ 3699 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3700 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3701 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */ 3702 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */ 3703 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3704 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3705 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */ 3706 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */ 3707 #define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3708 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3709 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */ 3710 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */ 3711 #define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3712 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3713 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3714 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3715 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3716 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3717 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */ 3718 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */ 3719 3720 /* 3721 * R3359 (0xD1F) - Interrupt Control 3722 */ 3723 #define WM5100_IM_IRQ 0x0001 /* IM_IRQ */ 3724 #define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3725 #define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3726 #define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3727 3728 /* 3729 * R3360 (0xD20) - IRQ Debounce 1 3730 */ 3731 #define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3732 #define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3733 #define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */ 3734 #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */ 3735 #define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */ 3736 #define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */ 3737 #define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */ 3738 #define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */ 3739 #define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */ 3740 #define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */ 3741 #define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */ 3742 #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */ 3743 #define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */ 3744 #define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */ 3745 #define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */ 3746 #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */ 3747 #define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3748 #define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3749 #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */ 3750 #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */ 3751 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3752 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3753 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3754 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3755 3756 /* 3757 * R3361 (0xD21) - IRQ Debounce 2 3758 */ 3759 #define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */ 3760 #define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */ 3761 #define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */ 3762 #define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */ 3763 3764 /* 3765 * R3584 (0xE00) - FX_Ctrl 3766 */ 3767 #define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */ 3768 #define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */ 3769 #define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */ 3770 #define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */ 3771 #define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */ 3772 #define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */ 3773 3774 /* 3775 * R3600 (0xE10) - EQ1_1 3776 */ 3777 #define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */ 3778 #define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */ 3779 #define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */ 3780 #define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */ 3781 #define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */ 3782 #define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */ 3783 #define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */ 3784 #define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */ 3785 #define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */ 3786 #define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */ 3787 #define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */ 3788 #define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */ 3789 #define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */ 3790 3791 /* 3792 * R3601 (0xE11) - EQ1_2 3793 */ 3794 #define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */ 3795 #define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */ 3796 #define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */ 3797 #define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */ 3798 #define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */ 3799 #define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */ 3800 3801 /* 3802 * R3602 (0xE12) - EQ1_3 3803 */ 3804 #define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */ 3805 #define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */ 3806 #define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */ 3807 3808 /* 3809 * R3603 (0xE13) - EQ1_4 3810 */ 3811 #define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */ 3812 #define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */ 3813 #define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */ 3814 3815 /* 3816 * R3604 (0xE14) - EQ1_5 3817 */ 3818 #define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */ 3819 #define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */ 3820 #define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */ 3821 3822 /* 3823 * R3605 (0xE15) - EQ1_6 3824 */ 3825 #define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */ 3826 #define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */ 3827 #define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */ 3828 3829 /* 3830 * R3606 (0xE16) - EQ1_7 3831 */ 3832 #define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */ 3833 #define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */ 3834 #define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */ 3835 3836 /* 3837 * R3607 (0xE17) - EQ1_8 3838 */ 3839 #define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */ 3840 #define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */ 3841 #define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */ 3842 3843 /* 3844 * R3608 (0xE18) - EQ1_9 3845 */ 3846 #define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */ 3847 #define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */ 3848 #define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */ 3849 3850 /* 3851 * R3609 (0xE19) - EQ1_10 3852 */ 3853 #define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */ 3854 #define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */ 3855 #define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */ 3856 3857 /* 3858 * R3610 (0xE1A) - EQ1_11 3859 */ 3860 #define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */ 3861 #define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */ 3862 #define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */ 3863 3864 /* 3865 * R3611 (0xE1B) - EQ1_12 3866 */ 3867 #define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */ 3868 #define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */ 3869 #define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */ 3870 3871 /* 3872 * R3612 (0xE1C) - EQ1_13 3873 */ 3874 #define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */ 3875 #define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */ 3876 #define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */ 3877 3878 /* 3879 * R3613 (0xE1D) - EQ1_14 3880 */ 3881 #define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */ 3882 #define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */ 3883 #define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */ 3884 3885 /* 3886 * R3614 (0xE1E) - EQ1_15 3887 */ 3888 #define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */ 3889 #define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */ 3890 #define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */ 3891 3892 /* 3893 * R3615 (0xE1F) - EQ1_16 3894 */ 3895 #define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */ 3896 #define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */ 3897 #define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */ 3898 3899 /* 3900 * R3616 (0xE20) - EQ1_17 3901 */ 3902 #define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */ 3903 #define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */ 3904 #define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */ 3905 3906 /* 3907 * R3617 (0xE21) - EQ1_18 3908 */ 3909 #define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */ 3910 #define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */ 3911 #define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */ 3912 3913 /* 3914 * R3618 (0xE22) - EQ1_19 3915 */ 3916 #define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */ 3917 #define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */ 3918 #define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */ 3919 3920 /* 3921 * R3619 (0xE23) - EQ1_20 3922 */ 3923 #define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */ 3924 #define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */ 3925 #define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */ 3926 3927 /* 3928 * R3622 (0xE26) - EQ2_1 3929 */ 3930 #define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */ 3931 #define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */ 3932 #define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */ 3933 #define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */ 3934 #define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */ 3935 #define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */ 3936 #define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */ 3937 #define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */ 3938 #define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */ 3939 #define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */ 3940 #define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */ 3941 #define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */ 3942 #define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */ 3943 3944 /* 3945 * R3623 (0xE27) - EQ2_2 3946 */ 3947 #define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */ 3948 #define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */ 3949 #define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */ 3950 #define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */ 3951 #define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */ 3952 #define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */ 3953 3954 /* 3955 * R3624 (0xE28) - EQ2_3 3956 */ 3957 #define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */ 3958 #define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */ 3959 #define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */ 3960 3961 /* 3962 * R3625 (0xE29) - EQ2_4 3963 */ 3964 #define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */ 3965 #define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */ 3966 #define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */ 3967 3968 /* 3969 * R3626 (0xE2A) - EQ2_5 3970 */ 3971 #define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */ 3972 #define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */ 3973 #define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */ 3974 3975 /* 3976 * R3627 (0xE2B) - EQ2_6 3977 */ 3978 #define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */ 3979 #define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */ 3980 #define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */ 3981 3982 /* 3983 * R3628 (0xE2C) - EQ2_7 3984 */ 3985 #define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */ 3986 #define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */ 3987 #define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */ 3988 3989 /* 3990 * R3629 (0xE2D) - EQ2_8 3991 */ 3992 #define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */ 3993 #define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */ 3994 #define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */ 3995 3996 /* 3997 * R3630 (0xE2E) - EQ2_9 3998 */ 3999 #define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */ 4000 #define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */ 4001 #define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */ 4002 4003 /* 4004 * R3631 (0xE2F) - EQ2_10 4005 */ 4006 #define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */ 4007 #define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */ 4008 #define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */ 4009 4010 /* 4011 * R3632 (0xE30) - EQ2_11 4012 */ 4013 #define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */ 4014 #define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */ 4015 #define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */ 4016 4017 /* 4018 * R3633 (0xE31) - EQ2_12 4019 */ 4020 #define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */ 4021 #define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */ 4022 #define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */ 4023 4024 /* 4025 * R3634 (0xE32) - EQ2_13 4026 */ 4027 #define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */ 4028 #define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */ 4029 #define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */ 4030 4031 /* 4032 * R3635 (0xE33) - EQ2_14 4033 */ 4034 #define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */ 4035 #define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */ 4036 #define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */ 4037 4038 /* 4039 * R3636 (0xE34) - EQ2_15 4040 */ 4041 #define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */ 4042 #define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */ 4043 #define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */ 4044 4045 /* 4046 * R3637 (0xE35) - EQ2_16 4047 */ 4048 #define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */ 4049 #define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */ 4050 #define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */ 4051 4052 /* 4053 * R3638 (0xE36) - EQ2_17 4054 */ 4055 #define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */ 4056 #define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */ 4057 #define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */ 4058 4059 /* 4060 * R3639 (0xE37) - EQ2_18 4061 */ 4062 #define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */ 4063 #define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */ 4064 #define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */ 4065 4066 /* 4067 * R3640 (0xE38) - EQ2_19 4068 */ 4069 #define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */ 4070 #define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */ 4071 #define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */ 4072 4073 /* 4074 * R3641 (0xE39) - EQ2_20 4075 */ 4076 #define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */ 4077 #define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */ 4078 #define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */ 4079 4080 /* 4081 * R3644 (0xE3C) - EQ3_1 4082 */ 4083 #define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */ 4084 #define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */ 4085 #define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */ 4086 #define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */ 4087 #define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */ 4088 #define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */ 4089 #define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */ 4090 #define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */ 4091 #define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */ 4092 #define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */ 4093 #define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */ 4094 #define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */ 4095 #define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */ 4096 4097 /* 4098 * R3645 (0xE3D) - EQ3_2 4099 */ 4100 #define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */ 4101 #define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */ 4102 #define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */ 4103 #define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */ 4104 #define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */ 4105 #define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */ 4106 4107 /* 4108 * R3646 (0xE3E) - EQ3_3 4109 */ 4110 #define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */ 4111 #define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */ 4112 #define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */ 4113 4114 /* 4115 * R3647 (0xE3F) - EQ3_4 4116 */ 4117 #define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */ 4118 #define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */ 4119 #define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */ 4120 4121 /* 4122 * R3648 (0xE40) - EQ3_5 4123 */ 4124 #define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */ 4125 #define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */ 4126 #define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */ 4127 4128 /* 4129 * R3649 (0xE41) - EQ3_6 4130 */ 4131 #define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */ 4132 #define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */ 4133 #define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */ 4134 4135 /* 4136 * R3650 (0xE42) - EQ3_7 4137 */ 4138 #define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */ 4139 #define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */ 4140 #define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */ 4141 4142 /* 4143 * R3651 (0xE43) - EQ3_8 4144 */ 4145 #define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */ 4146 #define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */ 4147 #define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */ 4148 4149 /* 4150 * R3652 (0xE44) - EQ3_9 4151 */ 4152 #define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */ 4153 #define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */ 4154 #define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */ 4155 4156 /* 4157 * R3653 (0xE45) - EQ3_10 4158 */ 4159 #define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */ 4160 #define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */ 4161 #define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */ 4162 4163 /* 4164 * R3654 (0xE46) - EQ3_11 4165 */ 4166 #define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */ 4167 #define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */ 4168 #define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */ 4169 4170 /* 4171 * R3655 (0xE47) - EQ3_12 4172 */ 4173 #define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */ 4174 #define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */ 4175 #define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */ 4176 4177 /* 4178 * R3656 (0xE48) - EQ3_13 4179 */ 4180 #define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */ 4181 #define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */ 4182 #define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */ 4183 4184 /* 4185 * R3657 (0xE49) - EQ3_14 4186 */ 4187 #define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */ 4188 #define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */ 4189 #define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */ 4190 4191 /* 4192 * R3658 (0xE4A) - EQ3_15 4193 */ 4194 #define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */ 4195 #define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */ 4196 #define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */ 4197 4198 /* 4199 * R3659 (0xE4B) - EQ3_16 4200 */ 4201 #define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */ 4202 #define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */ 4203 #define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */ 4204 4205 /* 4206 * R3660 (0xE4C) - EQ3_17 4207 */ 4208 #define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */ 4209 #define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */ 4210 #define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */ 4211 4212 /* 4213 * R3661 (0xE4D) - EQ3_18 4214 */ 4215 #define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */ 4216 #define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */ 4217 #define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */ 4218 4219 /* 4220 * R3662 (0xE4E) - EQ3_19 4221 */ 4222 #define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */ 4223 #define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */ 4224 #define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */ 4225 4226 /* 4227 * R3663 (0xE4F) - EQ3_20 4228 */ 4229 #define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */ 4230 #define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */ 4231 #define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */ 4232 4233 /* 4234 * R3666 (0xE52) - EQ4_1 4235 */ 4236 #define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */ 4237 #define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */ 4238 #define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */ 4239 #define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */ 4240 #define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */ 4241 #define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */ 4242 #define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */ 4243 #define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */ 4244 #define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */ 4245 #define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */ 4246 #define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */ 4247 #define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */ 4248 #define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */ 4249 4250 /* 4251 * R3667 (0xE53) - EQ4_2 4252 */ 4253 #define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */ 4254 #define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */ 4255 #define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */ 4256 #define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */ 4257 #define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */ 4258 #define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */ 4259 4260 /* 4261 * R3668 (0xE54) - EQ4_3 4262 */ 4263 #define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */ 4264 #define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */ 4265 #define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */ 4266 4267 /* 4268 * R3669 (0xE55) - EQ4_4 4269 */ 4270 #define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */ 4271 #define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */ 4272 #define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */ 4273 4274 /* 4275 * R3670 (0xE56) - EQ4_5 4276 */ 4277 #define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */ 4278 #define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */ 4279 #define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */ 4280 4281 /* 4282 * R3671 (0xE57) - EQ4_6 4283 */ 4284 #define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */ 4285 #define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */ 4286 #define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */ 4287 4288 /* 4289 * R3672 (0xE58) - EQ4_7 4290 */ 4291 #define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */ 4292 #define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */ 4293 #define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */ 4294 4295 /* 4296 * R3673 (0xE59) - EQ4_8 4297 */ 4298 #define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */ 4299 #define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */ 4300 #define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */ 4301 4302 /* 4303 * R3674 (0xE5A) - EQ4_9 4304 */ 4305 #define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */ 4306 #define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */ 4307 #define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */ 4308 4309 /* 4310 * R3675 (0xE5B) - EQ4_10 4311 */ 4312 #define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */ 4313 #define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */ 4314 #define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */ 4315 4316 /* 4317 * R3676 (0xE5C) - EQ4_11 4318 */ 4319 #define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */ 4320 #define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */ 4321 #define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */ 4322 4323 /* 4324 * R3677 (0xE5D) - EQ4_12 4325 */ 4326 #define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */ 4327 #define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */ 4328 #define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */ 4329 4330 /* 4331 * R3678 (0xE5E) - EQ4_13 4332 */ 4333 #define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */ 4334 #define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */ 4335 #define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */ 4336 4337 /* 4338 * R3679 (0xE5F) - EQ4_14 4339 */ 4340 #define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */ 4341 #define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */ 4342 #define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */ 4343 4344 /* 4345 * R3680 (0xE60) - EQ4_15 4346 */ 4347 #define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */ 4348 #define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */ 4349 #define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */ 4350 4351 /* 4352 * R3681 (0xE61) - EQ4_16 4353 */ 4354 #define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */ 4355 #define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */ 4356 #define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */ 4357 4358 /* 4359 * R3682 (0xE62) - EQ4_17 4360 */ 4361 #define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */ 4362 #define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */ 4363 #define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */ 4364 4365 /* 4366 * R3683 (0xE63) - EQ4_18 4367 */ 4368 #define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */ 4369 #define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */ 4370 #define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */ 4371 4372 /* 4373 * R3684 (0xE64) - EQ4_19 4374 */ 4375 #define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */ 4376 #define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */ 4377 #define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */ 4378 4379 /* 4380 * R3685 (0xE65) - EQ4_20 4381 */ 4382 #define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */ 4383 #define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */ 4384 #define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */ 4385 4386 /* 4387 * R3712 (0xE80) - DRC1 ctrl1 4388 */ 4389 #define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */ 4390 #define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */ 4391 #define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */ 4392 #define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */ 4393 #define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */ 4394 #define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */ 4395 #define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */ 4396 #define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */ 4397 #define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */ 4398 #define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ 4399 #define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */ 4400 #define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */ 4401 #define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */ 4402 #define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ 4403 #define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */ 4404 #define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */ 4405 #define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */ 4406 #define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ 4407 #define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */ 4408 #define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */ 4409 #define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */ 4410 #define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ 4411 #define WM5100_DRC_QR 0x0010 /* DRC_QR */ 4412 #define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */ 4413 #define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */ 4414 #define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */ 4415 #define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */ 4416 #define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */ 4417 #define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */ 4418 #define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 4419 #define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */ 4420 #define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */ 4421 #define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */ 4422 #define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */ 4423 #define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */ 4424 #define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */ 4425 #define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */ 4426 #define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */ 4427 4428 /* 4429 * R3713 (0xE81) - DRC1 ctrl2 4430 */ 4431 #define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ 4432 #define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ 4433 #define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ 4434 #define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ 4435 #define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ 4436 #define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ 4437 #define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ 4438 #define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ 4439 #define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ 4440 #define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 4441 #define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 4442 #define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 4443 4444 /* 4445 * R3714 (0xE82) - DRC1 ctrl3 4446 */ 4447 #define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ 4448 #define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ 4449 #define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ 4450 #define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */ 4451 #define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */ 4452 #define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */ 4453 #define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */ 4454 #define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */ 4455 #define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */ 4456 #define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */ 4457 #define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */ 4458 #define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */ 4459 #define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 4460 #define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 4461 #define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 4462 #define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 4463 #define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 4464 #define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 4465 4466 /* 4467 * R3715 (0xE83) - DRC1 ctrl4 4468 */ 4469 #define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 4470 #define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 4471 #define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 4472 #define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 4473 #define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 4474 #define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 4475 4476 /* 4477 * R3716 (0xE84) - DRC1 ctrl5 4478 */ 4479 #define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ 4480 #define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ 4481 #define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ 4482 #define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ 4483 #define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ 4484 #define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ 4485 4486 /* 4487 * R3776 (0xEC0) - HPLPF1_1 4488 */ 4489 #define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 4490 #define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 4491 #define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 4492 #define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 4493 #define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 4494 #define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 4495 #define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 4496 #define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 4497 4498 /* 4499 * R3777 (0xEC1) - HPLPF1_2 4500 */ 4501 #define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 4502 #define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 4503 #define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 4504 4505 /* 4506 * R3780 (0xEC4) - HPLPF2_1 4507 */ 4508 #define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 4509 #define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 4510 #define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 4511 #define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 4512 #define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 4513 #define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 4514 #define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 4515 #define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 4516 4517 /* 4518 * R3781 (0xEC5) - HPLPF2_2 4519 */ 4520 #define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 4521 #define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 4522 #define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 4523 4524 /* 4525 * R3784 (0xEC8) - HPLPF3_1 4526 */ 4527 #define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */ 4528 #define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */ 4529 #define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */ 4530 #define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */ 4531 #define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */ 4532 #define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */ 4533 #define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */ 4534 #define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */ 4535 4536 /* 4537 * R3785 (0xEC9) - HPLPF3_2 4538 */ 4539 #define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */ 4540 #define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */ 4541 #define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */ 4542 4543 /* 4544 * R3788 (0xECC) - HPLPF4_1 4545 */ 4546 #define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */ 4547 #define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */ 4548 #define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */ 4549 #define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */ 4550 #define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */ 4551 #define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */ 4552 #define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */ 4553 #define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */ 4554 4555 /* 4556 * R3789 (0xECD) - HPLPF4_2 4557 */ 4558 #define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */ 4559 #define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ 4560 #define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 4561 4562 /* 4563 * R16384 (0x4000) - DSP1 DM 0 4564 */ 4565 #define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */ 4566 #define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */ 4567 #define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */ 4568 4569 /* 4570 * R16385 (0x4001) - DSP1 DM 1 4571 */ 4572 #define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */ 4573 #define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */ 4574 #define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */ 4575 4576 /* 4577 * R16386 (0x4002) - DSP1 DM 2 4578 */ 4579 #define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */ 4580 #define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */ 4581 #define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */ 4582 4583 /* 4584 * R16387 (0x4003) - DSP1 DM 3 4585 */ 4586 #define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */ 4587 #define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */ 4588 #define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */ 4589 4590 /* 4591 * R16892 (0x41FC) - DSP1 DM 508 4592 */ 4593 #define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */ 4594 #define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */ 4595 #define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */ 4596 4597 /* 4598 * R16893 (0x41FD) - DSP1 DM 509 4599 */ 4600 #define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */ 4601 #define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */ 4602 #define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */ 4603 4604 /* 4605 * R16894 (0x41FE) - DSP1 DM 510 4606 */ 4607 #define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */ 4608 #define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */ 4609 #define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */ 4610 4611 /* 4612 * R16895 (0x41FF) - DSP1 DM 511 4613 */ 4614 #define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */ 4615 #define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */ 4616 #define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */ 4617 4618 /* 4619 * R18432 (0x4800) - DSP1 PM 0 4620 */ 4621 #define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */ 4622 #define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */ 4623 #define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */ 4624 4625 /* 4626 * R18433 (0x4801) - DSP1 PM 1 4627 */ 4628 #define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4629 #define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4630 #define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4631 4632 /* 4633 * R18434 (0x4802) - DSP1 PM 2 4634 */ 4635 #define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4636 #define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4637 #define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4638 4639 /* 4640 * R18435 (0x4803) - DSP1 PM 3 4641 */ 4642 #define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */ 4643 #define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */ 4644 #define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */ 4645 4646 /* 4647 * R18436 (0x4804) - DSP1 PM 4 4648 */ 4649 #define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4650 #define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4651 #define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4652 4653 /* 4654 * R18437 (0x4805) - DSP1 PM 5 4655 */ 4656 #define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4657 #define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4658 #define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4659 4660 /* 4661 * R19962 (0x4DFA) - DSP1 PM 1530 4662 */ 4663 #define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */ 4664 #define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */ 4665 #define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */ 4666 4667 /* 4668 * R19963 (0x4DFB) - DSP1 PM 1531 4669 */ 4670 #define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4671 #define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4672 #define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4673 4674 /* 4675 * R19964 (0x4DFC) - DSP1 PM 1532 4676 */ 4677 #define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4678 #define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4679 #define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4680 4681 /* 4682 * R19965 (0x4DFD) - DSP1 PM 1533 4683 */ 4684 #define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */ 4685 #define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */ 4686 #define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */ 4687 4688 /* 4689 * R19966 (0x4DFE) - DSP1 PM 1534 4690 */ 4691 #define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4692 #define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4693 #define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4694 4695 /* 4696 * R19967 (0x4DFF) - DSP1 PM 1535 4697 */ 4698 #define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4699 #define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4700 #define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4701 4702 /* 4703 * R20480 (0x5000) - DSP1 ZM 0 4704 */ 4705 #define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */ 4706 #define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */ 4707 #define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */ 4708 4709 /* 4710 * R20481 (0x5001) - DSP1 ZM 1 4711 */ 4712 #define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */ 4713 #define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */ 4714 #define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */ 4715 4716 /* 4717 * R20482 (0x5002) - DSP1 ZM 2 4718 */ 4719 #define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */ 4720 #define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */ 4721 #define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */ 4722 4723 /* 4724 * R20483 (0x5003) - DSP1 ZM 3 4725 */ 4726 #define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */ 4727 #define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */ 4728 #define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */ 4729 4730 /* 4731 * R22524 (0x57FC) - DSP1 ZM 2044 4732 */ 4733 #define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */ 4734 #define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */ 4735 #define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */ 4736 4737 /* 4738 * R22525 (0x57FD) - DSP1 ZM 2045 4739 */ 4740 #define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */ 4741 #define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */ 4742 #define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */ 4743 4744 /* 4745 * R22526 (0x57FE) - DSP1 ZM 2046 4746 */ 4747 #define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */ 4748 #define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */ 4749 #define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */ 4750 4751 /* 4752 * R22527 (0x57FF) - DSP1 ZM 2047 4753 */ 4754 #define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */ 4755 #define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */ 4756 #define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */ 4757 4758 /* 4759 * R24576 (0x6000) - DSP2 DM 0 4760 */ 4761 #define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */ 4762 #define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */ 4763 #define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */ 4764 4765 /* 4766 * R24577 (0x6001) - DSP2 DM 1 4767 */ 4768 #define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */ 4769 #define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */ 4770 #define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */ 4771 4772 /* 4773 * R24578 (0x6002) - DSP2 DM 2 4774 */ 4775 #define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */ 4776 #define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */ 4777 #define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */ 4778 4779 /* 4780 * R24579 (0x6003) - DSP2 DM 3 4781 */ 4782 #define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */ 4783 #define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */ 4784 #define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */ 4785 4786 /* 4787 * R25084 (0x61FC) - DSP2 DM 508 4788 */ 4789 #define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */ 4790 #define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */ 4791 #define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */ 4792 4793 /* 4794 * R25085 (0x61FD) - DSP2 DM 509 4795 */ 4796 #define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */ 4797 #define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */ 4798 #define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */ 4799 4800 /* 4801 * R25086 (0x61FE) - DSP2 DM 510 4802 */ 4803 #define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */ 4804 #define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */ 4805 #define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */ 4806 4807 /* 4808 * R25087 (0x61FF) - DSP2 DM 511 4809 */ 4810 #define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */ 4811 #define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */ 4812 #define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */ 4813 4814 /* 4815 * R26624 (0x6800) - DSP2 PM 0 4816 */ 4817 #define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */ 4818 #define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */ 4819 #define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */ 4820 4821 /* 4822 * R26625 (0x6801) - DSP2 PM 1 4823 */ 4824 #define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4825 #define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4826 #define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4827 4828 /* 4829 * R26626 (0x6802) - DSP2 PM 2 4830 */ 4831 #define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4832 #define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4833 #define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4834 4835 /* 4836 * R26627 (0x6803) - DSP2 PM 3 4837 */ 4838 #define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */ 4839 #define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */ 4840 #define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */ 4841 4842 /* 4843 * R26628 (0x6804) - DSP2 PM 4 4844 */ 4845 #define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 4846 #define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 4847 #define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 4848 4849 /* 4850 * R26629 (0x6805) - DSP2 PM 5 4851 */ 4852 #define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 4853 #define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 4854 #define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 4855 4856 /* 4857 * R28154 (0x6DFA) - DSP2 PM 1530 4858 */ 4859 #define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */ 4860 #define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */ 4861 #define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */ 4862 4863 /* 4864 * R28155 (0x6DFB) - DSP2 PM 1531 4865 */ 4866 #define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 4867 #define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 4868 #define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 4869 4870 /* 4871 * R28156 (0x6DFC) - DSP2 PM 1532 4872 */ 4873 #define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 4874 #define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 4875 #define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 4876 4877 /* 4878 * R28157 (0x6DFD) - DSP2 PM 1533 4879 */ 4880 #define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */ 4881 #define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */ 4882 #define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */ 4883 4884 /* 4885 * R28158 (0x6DFE) - DSP2 PM 1534 4886 */ 4887 #define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 4888 #define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */ 4889 #define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */ 4890 4891 /* 4892 * R28159 (0x6DFF) - DSP2 PM 1535 4893 */ 4894 #define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 4895 #define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */ 4896 #define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */ 4897 4898 /* 4899 * R28672 (0x7000) - DSP2 ZM 0 4900 */ 4901 #define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */ 4902 #define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */ 4903 #define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */ 4904 4905 /* 4906 * R28673 (0x7001) - DSP2 ZM 1 4907 */ 4908 #define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */ 4909 #define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */ 4910 #define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */ 4911 4912 /* 4913 * R28674 (0x7002) - DSP2 ZM 2 4914 */ 4915 #define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */ 4916 #define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */ 4917 #define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */ 4918 4919 /* 4920 * R28675 (0x7003) - DSP2 ZM 3 4921 */ 4922 #define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */ 4923 #define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */ 4924 #define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */ 4925 4926 /* 4927 * R30716 (0x77FC) - DSP2 ZM 2044 4928 */ 4929 #define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */ 4930 #define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */ 4931 #define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */ 4932 4933 /* 4934 * R30717 (0x77FD) - DSP2 ZM 2045 4935 */ 4936 #define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */ 4937 #define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */ 4938 #define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */ 4939 4940 /* 4941 * R30718 (0x77FE) - DSP2 ZM 2046 4942 */ 4943 #define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */ 4944 #define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */ 4945 #define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */ 4946 4947 /* 4948 * R30719 (0x77FF) - DSP2 ZM 2047 4949 */ 4950 #define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */ 4951 #define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */ 4952 #define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */ 4953 4954 /* 4955 * R32768 (0x8000) - DSP3 DM 0 4956 */ 4957 #define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */ 4958 #define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */ 4959 #define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */ 4960 4961 /* 4962 * R32769 (0x8001) - DSP3 DM 1 4963 */ 4964 #define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */ 4965 #define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */ 4966 #define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */ 4967 4968 /* 4969 * R32770 (0x8002) - DSP3 DM 2 4970 */ 4971 #define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */ 4972 #define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */ 4973 #define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */ 4974 4975 /* 4976 * R32771 (0x8003) - DSP3 DM 3 4977 */ 4978 #define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */ 4979 #define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */ 4980 #define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */ 4981 4982 /* 4983 * R33276 (0x81FC) - DSP3 DM 508 4984 */ 4985 #define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */ 4986 #define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */ 4987 #define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */ 4988 4989 /* 4990 * R33277 (0x81FD) - DSP3 DM 509 4991 */ 4992 #define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */ 4993 #define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */ 4994 #define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */ 4995 4996 /* 4997 * R33278 (0x81FE) - DSP3 DM 510 4998 */ 4999 #define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */ 5000 #define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */ 5001 #define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */ 5002 5003 /* 5004 * R33279 (0x81FF) - DSP3 DM 511 5005 */ 5006 #define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */ 5007 #define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */ 5008 #define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */ 5009 5010 /* 5011 * R34816 (0x8800) - DSP3 PM 0 5012 */ 5013 #define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */ 5014 #define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */ 5015 #define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */ 5016 5017 /* 5018 * R34817 (0x8801) - DSP3 PM 1 5019 */ 5020 #define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5021 #define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5022 #define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5023 5024 /* 5025 * R34818 (0x8802) - DSP3 PM 2 5026 */ 5027 #define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5028 #define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5029 #define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5030 5031 /* 5032 * R34819 (0x8803) - DSP3 PM 3 5033 */ 5034 #define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */ 5035 #define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */ 5036 #define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */ 5037 5038 /* 5039 * R34820 (0x8804) - DSP3 PM 4 5040 */ 5041 #define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5042 #define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5043 #define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5044 5045 /* 5046 * R34821 (0x8805) - DSP3 PM 5 5047 */ 5048 #define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5049 #define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5050 #define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5051 5052 /* 5053 * R36346 (0x8DFA) - DSP3 PM 1530 5054 */ 5055 #define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */ 5056 #define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */ 5057 #define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */ 5058 5059 /* 5060 * R36347 (0x8DFB) - DSP3 PM 1531 5061 */ 5062 #define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5063 #define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5064 #define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5065 5066 /* 5067 * R36348 (0x8DFC) - DSP3 PM 1532 5068 */ 5069 #define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5070 #define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5071 #define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5072 5073 /* 5074 * R36349 (0x8DFD) - DSP3 PM 1533 5075 */ 5076 #define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */ 5077 #define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */ 5078 #define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */ 5079 5080 /* 5081 * R36350 (0x8DFE) - DSP3 PM 1534 5082 */ 5083 #define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5084 #define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5085 #define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5086 5087 /* 5088 * R36351 (0x8DFF) - DSP3 PM 1535 5089 */ 5090 #define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5091 #define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5092 #define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5093 5094 /* 5095 * R36864 (0x9000) - DSP3 ZM 0 5096 */ 5097 #define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */ 5098 #define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */ 5099 #define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */ 5100 5101 /* 5102 * R36865 (0x9001) - DSP3 ZM 1 5103 */ 5104 #define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */ 5105 #define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */ 5106 #define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */ 5107 5108 /* 5109 * R36866 (0x9002) - DSP3 ZM 2 5110 */ 5111 #define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */ 5112 #define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */ 5113 #define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */ 5114 5115 /* 5116 * R36867 (0x9003) - DSP3 ZM 3 5117 */ 5118 #define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */ 5119 #define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */ 5120 #define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */ 5121 5122 /* 5123 * R38908 (0x97FC) - DSP3 ZM 2044 5124 */ 5125 #define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */ 5126 #define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */ 5127 #define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */ 5128 5129 /* 5130 * R38909 (0x97FD) - DSP3 ZM 2045 5131 */ 5132 #define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */ 5133 #define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */ 5134 #define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */ 5135 5136 /* 5137 * R38910 (0x97FE) - DSP3 ZM 2046 5138 */ 5139 #define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */ 5140 #define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */ 5141 #define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */ 5142 5143 /* 5144 * R38911 (0x97FF) - DSP3 ZM 2047 5145 */ 5146 #define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */ 5147 #define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */ 5148 #define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */ 5149 5150 int wm5100_readable_register(struct snd_soc_codec *codec, unsigned int reg); 5151 int wm5100_volatile_register(struct snd_soc_codec *codec, unsigned int reg); 5152 5153 extern u16 wm5100_reg_defaults[WM5100_MAX_REGISTER + 1]; 5154 5155 #endif 5156