xref: /openbmc/linux/sound/soc/codecs/wm5100.c (revision e23feb16)
1 /*
2  * wm5100.c  --  WM5100 ALSA SoC Audio driver
3  *
4  * Copyright 2011-2 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/gcd.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/regulator/fixed.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/wm5100.h>
33 
34 #include "wm5100.h"
35 
36 #define WM5100_NUM_CORE_SUPPLIES 2
37 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
38 	"DBVDD1",
39 	"LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
40 };
41 
42 #define WM5100_AIFS     3
43 #define WM5100_SYNC_SRS 3
44 
45 struct wm5100_fll {
46 	int fref;
47 	int fout;
48 	int src;
49 	struct completion lock;
50 };
51 
52 /* codec private data */
53 struct wm5100_priv {
54 	struct device *dev;
55 	struct regmap *regmap;
56 	struct snd_soc_codec *codec;
57 
58 	struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
59 
60 	int rev;
61 
62 	int sysclk;
63 	int asyncclk;
64 
65 	bool aif_async[WM5100_AIFS];
66 	bool aif_symmetric[WM5100_AIFS];
67 	int sr_ref[WM5100_SYNC_SRS];
68 
69 	bool out_ena[2];
70 
71 	struct snd_soc_jack *jack;
72 	bool jack_detecting;
73 	bool jack_mic;
74 	int jack_mode;
75 	int jack_flips;
76 
77 	struct wm5100_fll fll[2];
78 
79 	struct wm5100_pdata pdata;
80 
81 #ifdef CONFIG_GPIOLIB
82 	struct gpio_chip gpio_chip;
83 #endif
84 };
85 
86 static int wm5100_sr_code[] = {
87 	0,
88 	12000,
89 	24000,
90 	48000,
91 	96000,
92 	192000,
93 	384000,
94 	768000,
95 	0,
96 	11025,
97 	22050,
98 	44100,
99 	88200,
100 	176400,
101 	352800,
102 	705600,
103 	4000,
104 	8000,
105 	16000,
106 	32000,
107 	64000,
108 	128000,
109 	256000,
110 	512000,
111 };
112 
113 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
114 	WM5100_CLOCKING_4,
115 	WM5100_CLOCKING_5,
116 	WM5100_CLOCKING_6,
117 };
118 
119 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
120 {
121 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
122 	int sr_code, sr_free, i;
123 
124 	for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
125 		if (wm5100_sr_code[i] == rate)
126 			break;
127 	if (i == ARRAY_SIZE(wm5100_sr_code)) {
128 		dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
129 		return -EINVAL;
130 	}
131 	sr_code = i;
132 
133 	if ((wm5100->sysclk % rate) == 0) {
134 		/* Is this rate already in use? */
135 		sr_free = -1;
136 		for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
137 			if (!wm5100->sr_ref[i] && sr_free == -1) {
138 				sr_free = i;
139 				continue;
140 			}
141 			if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
142 			     WM5100_SAMPLE_RATE_1_MASK) == sr_code)
143 				break;
144 		}
145 
146 		if (i < ARRAY_SIZE(wm5100_sr_regs)) {
147 			wm5100->sr_ref[i]++;
148 			dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
149 				rate, i, wm5100->sr_ref[i]);
150 			return i;
151 		}
152 
153 		if (sr_free == -1) {
154 			dev_err(codec->dev, "All SR slots already in use\n");
155 			return -EBUSY;
156 		}
157 
158 		dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
159 			sr_free, rate);
160 		wm5100->sr_ref[sr_free]++;
161 		snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
162 				    WM5100_SAMPLE_RATE_1_MASK,
163 				    sr_code);
164 
165 		return sr_free;
166 
167 	} else {
168 		dev_err(codec->dev,
169 			"SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
170 			rate, wm5100->sysclk, wm5100->asyncclk);
171 		return -EINVAL;
172 	}
173 }
174 
175 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
176 {
177 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
178 	int i, sr_code;
179 
180 	for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
181 		if (wm5100_sr_code[i] == rate)
182 			break;
183 	if (i == ARRAY_SIZE(wm5100_sr_code)) {
184 		dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
185 		return;
186 	}
187 	sr_code = wm5100_sr_code[i];
188 
189 	for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
190 		if (!wm5100->sr_ref[i])
191 			continue;
192 
193 		if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
194 		     WM5100_SAMPLE_RATE_1_MASK) == sr_code)
195 			break;
196 	}
197 	if (i < ARRAY_SIZE(wm5100_sr_regs)) {
198 		wm5100->sr_ref[i]--;
199 		dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
200 			rate, wm5100->sr_ref[i]);
201 	} else {
202 		dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
203 			 rate);
204 	}
205 }
206 
207 static int wm5100_reset(struct wm5100_priv *wm5100)
208 {
209 	if (wm5100->pdata.reset) {
210 		gpio_set_value_cansleep(wm5100->pdata.reset, 0);
211 		gpio_set_value_cansleep(wm5100->pdata.reset, 1);
212 
213 		return 0;
214 	} else {
215 		return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
216 	}
217 }
218 
219 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
220 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
221 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
222 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
223 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
224 
225 static const char *wm5100_mixer_texts[] = {
226 	"None",
227 	"Tone Generator 1",
228 	"Tone Generator 2",
229 	"AEC loopback",
230 	"IN1L",
231 	"IN1R",
232 	"IN2L",
233 	"IN2R",
234 	"IN3L",
235 	"IN3R",
236 	"IN4L",
237 	"IN4R",
238 	"AIF1RX1",
239 	"AIF1RX2",
240 	"AIF1RX3",
241 	"AIF1RX4",
242 	"AIF1RX5",
243 	"AIF1RX6",
244 	"AIF1RX7",
245 	"AIF1RX8",
246 	"AIF2RX1",
247 	"AIF2RX2",
248 	"AIF3RX1",
249 	"AIF3RX2",
250 	"EQ1",
251 	"EQ2",
252 	"EQ3",
253 	"EQ4",
254 	"DRC1L",
255 	"DRC1R",
256 	"LHPF1",
257 	"LHPF2",
258 	"LHPF3",
259 	"LHPF4",
260 	"DSP1.1",
261 	"DSP1.2",
262 	"DSP1.3",
263 	"DSP1.4",
264 	"DSP1.5",
265 	"DSP1.6",
266 	"DSP2.1",
267 	"DSP2.2",
268 	"DSP2.3",
269 	"DSP2.4",
270 	"DSP2.5",
271 	"DSP2.6",
272 	"DSP3.1",
273 	"DSP3.2",
274 	"DSP3.3",
275 	"DSP3.4",
276 	"DSP3.5",
277 	"DSP3.6",
278 	"ASRC1L",
279 	"ASRC1R",
280 	"ASRC2L",
281 	"ASRC2R",
282 	"ISRC1INT1",
283 	"ISRC1INT2",
284 	"ISRC1INT3",
285 	"ISRC1INT4",
286 	"ISRC2INT1",
287 	"ISRC2INT2",
288 	"ISRC2INT3",
289 	"ISRC2INT4",
290 	"ISRC1DEC1",
291 	"ISRC1DEC2",
292 	"ISRC1DEC3",
293 	"ISRC1DEC4",
294 	"ISRC2DEC1",
295 	"ISRC2DEC2",
296 	"ISRC2DEC3",
297 	"ISRC2DEC4",
298 };
299 
300 static int wm5100_mixer_values[] = {
301 	0x00,
302 	0x04,   /* Tone */
303 	0x05,
304 	0x08,   /* AEC */
305 	0x10,   /* Input */
306 	0x11,
307 	0x12,
308 	0x13,
309 	0x14,
310 	0x15,
311 	0x16,
312 	0x17,
313 	0x20,   /* AIF */
314 	0x21,
315 	0x22,
316 	0x23,
317 	0x24,
318 	0x25,
319 	0x26,
320 	0x27,
321 	0x28,
322 	0x29,
323 	0x30,   /* AIF3 - check */
324 	0x31,
325 	0x50,   /* EQ */
326 	0x51,
327 	0x52,
328 	0x53,
329 	0x54,
330 	0x58,   /* DRC */
331 	0x59,
332 	0x60,   /* LHPF1 */
333 	0x61,   /* LHPF2 */
334 	0x62,   /* LHPF3 */
335 	0x63,   /* LHPF4 */
336 	0x68,   /* DSP1 */
337 	0x69,
338 	0x6a,
339 	0x6b,
340 	0x6c,
341 	0x6d,
342 	0x70,   /* DSP2 */
343 	0x71,
344 	0x72,
345 	0x73,
346 	0x74,
347 	0x75,
348 	0x78,   /* DSP3 */
349 	0x79,
350 	0x7a,
351 	0x7b,
352 	0x7c,
353 	0x7d,
354 	0x90,   /* ASRC1 */
355 	0x91,
356 	0x92,   /* ASRC2 */
357 	0x93,
358 	0xa0,   /* ISRC1DEC1 */
359 	0xa1,
360 	0xa2,
361 	0xa3,
362 	0xa4,   /* ISRC1INT1 */
363 	0xa5,
364 	0xa6,
365 	0xa7,
366 	0xa8,   /* ISRC2DEC1 */
367 	0xa9,
368 	0xaa,
369 	0xab,
370 	0xac,   /* ISRC2INT1 */
371 	0xad,
372 	0xae,
373 	0xaf,
374 };
375 
376 #define WM5100_MIXER_CONTROLS(name, base) \
377 	SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
378 		       WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
379 	SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
380 		       WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381 	SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
382 		       WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383 	SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
384 		       WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
385 
386 #define WM5100_MUX_ENUM_DECL(name, reg) \
387 	SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, 			\
388 				   wm5100_mixer_texts, wm5100_mixer_values)
389 
390 #define WM5100_MUX_CTL_DECL(name) \
391 	const struct snd_kcontrol_new name##_mux =	\
392 		SOC_DAPM_VALUE_ENUM("Route", name##_enum)
393 
394 #define WM5100_MIXER_ENUMS(name, base_reg) \
395 	static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg);	     \
396 	static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2);  \
397 	static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4);  \
398 	static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6);  \
399 	static WM5100_MUX_CTL_DECL(name##_in1); \
400 	static WM5100_MUX_CTL_DECL(name##_in2); \
401 	static WM5100_MUX_CTL_DECL(name##_in3); \
402 	static WM5100_MUX_CTL_DECL(name##_in4)
403 
404 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
405 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
406 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
407 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
408 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
409 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
410 
411 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
412 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
413 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
414 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
415 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
416 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
417 
418 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
419 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
420 
421 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
422 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
423 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
424 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
425 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
426 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
427 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
428 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
429 
430 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
431 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
432 
433 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
434 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
435 
436 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
437 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
438 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
439 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
440 
441 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
442 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
443 
444 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
445 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
446 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
447 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
448 
449 #define WM5100_MUX(name, ctrl) \
450 	SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
451 
452 #define WM5100_MIXER_WIDGETS(name, name_str)	\
453 	WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
454 	WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
455 	WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
456 	WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
457 	SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
458 
459 #define WM5100_MIXER_INPUT_ROUTES(name)	\
460 	{ name, "Tone Generator 1", "Tone Generator 1" }, \
461         { name, "Tone Generator 2", "Tone Generator 2" }, \
462         { name, "IN1L", "IN1L PGA" }, \
463         { name, "IN1R", "IN1R PGA" }, \
464         { name, "IN2L", "IN2L PGA" }, \
465         { name, "IN2R", "IN2R PGA" }, \
466         { name, "IN3L", "IN3L PGA" }, \
467         { name, "IN3R", "IN3R PGA" }, \
468         { name, "IN4L", "IN4L PGA" }, \
469         { name, "IN4R", "IN4R PGA" }, \
470         { name, "AIF1RX1", "AIF1RX1" }, \
471         { name, "AIF1RX2", "AIF1RX2" }, \
472         { name, "AIF1RX3", "AIF1RX3" }, \
473         { name, "AIF1RX4", "AIF1RX4" }, \
474         { name, "AIF1RX5", "AIF1RX5" }, \
475         { name, "AIF1RX6", "AIF1RX6" }, \
476         { name, "AIF1RX7", "AIF1RX7" }, \
477         { name, "AIF1RX8", "AIF1RX8" }, \
478         { name, "AIF2RX1", "AIF2RX1" }, \
479         { name, "AIF2RX2", "AIF2RX2" }, \
480         { name, "AIF3RX1", "AIF3RX1" }, \
481         { name, "AIF3RX2", "AIF3RX2" }, \
482         { name, "EQ1", "EQ1" }, \
483         { name, "EQ2", "EQ2" }, \
484         { name, "EQ3", "EQ3" }, \
485         { name, "EQ4", "EQ4" }, \
486         { name, "DRC1L", "DRC1L" }, \
487         { name, "DRC1R", "DRC1R" }, \
488         { name, "LHPF1", "LHPF1" }, \
489         { name, "LHPF2", "LHPF2" }, \
490         { name, "LHPF3", "LHPF3" }, \
491         { name, "LHPF4", "LHPF4" }
492 
493 #define WM5100_MIXER_ROUTES(widget, name) \
494 	{ widget, NULL, name " Mixer" },         \
495 	{ name " Mixer", NULL, name " Input 1" }, \
496 	{ name " Mixer", NULL, name " Input 2" }, \
497 	{ name " Mixer", NULL, name " Input 3" }, \
498 	{ name " Mixer", NULL, name " Input 4" }, \
499 	WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
500 	WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
501 	WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
502 	WM5100_MIXER_INPUT_ROUTES(name " Input 4")
503 
504 static const char *wm5100_lhpf_mode_text[] = {
505 	"Low-pass", "High-pass"
506 };
507 
508 static const struct soc_enum wm5100_lhpf1_mode =
509 	SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
510 			wm5100_lhpf_mode_text);
511 
512 static const struct soc_enum wm5100_lhpf2_mode =
513 	SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
514 			wm5100_lhpf_mode_text);
515 
516 static const struct soc_enum wm5100_lhpf3_mode =
517 	SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
518 			wm5100_lhpf_mode_text);
519 
520 static const struct soc_enum wm5100_lhpf4_mode =
521 	SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
522 			wm5100_lhpf_mode_text);
523 
524 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
525 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
526 	   WM5100_IN1_OSR_SHIFT, 1, 0),
527 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
528 	   WM5100_IN2_OSR_SHIFT, 1, 0),
529 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
530 	   WM5100_IN3_OSR_SHIFT, 1, 0),
531 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
532 	   WM5100_IN4_OSR_SHIFT, 1, 0),
533 
534 /* Only applicable for analogue inputs */
535 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
536 		 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
537 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
538 		 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
540 		 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
542 		 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
543 
544 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
545 		 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
546 		 0, digital_tlv),
547 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
548 		 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
549 		 0, digital_tlv),
550 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
551 		 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
552 		 0, digital_tlv),
553 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
554 		 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
555 		 0, digital_tlv),
556 
557 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
558 	     WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
559 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
560 	     WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
561 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
562 	     WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
563 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
564 	     WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
565 
566 SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
567 SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
568 SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
569 SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
570 
571 SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
572 		   WM5100_DRCL_ENA | WM5100_DRCR_ENA),
573 
574 SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1),
575 SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1),
576 SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1),
577 SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1),
578 
579 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
580 	   WM5100_OUT1_OSR_SHIFT, 1, 0),
581 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
582 	   WM5100_OUT2_OSR_SHIFT, 1, 0),
583 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
584 	   WM5100_OUT3_OSR_SHIFT, 1, 0),
585 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
586 	   WM5100_OUT4_OSR_SHIFT, 1, 0),
587 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
588 	   WM5100_OUT5_OSR_SHIFT, 1, 0),
589 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
590 	   WM5100_OUT6_OSR_SHIFT, 1, 0),
591 
592 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
593 		 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
594 		 digital_tlv),
595 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
596 		 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
597 		 digital_tlv),
598 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
599 		 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
600 		 digital_tlv),
601 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
602 		 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
603 		 digital_tlv),
604 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
605 		 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
606 		 digital_tlv),
607 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
608 		 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
609 		 digital_tlv),
610 
611 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
612 	     WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
613 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
614 	     WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
615 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
616 	     WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
617 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
618 	     WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
619 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
620 	     WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
621 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
622 	     WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
623 
624 /* FIXME: Only valid from -12dB to 0dB (52-64) */
625 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
626 		 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
627 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
628 		 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
629 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
630 		 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
631 
632 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
633 	   WM5100_SPK1R_MUTE_SHIFT, 1, 1),
634 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
635 	   WM5100_SPK2R_MUTE_SHIFT, 1, 1),
636 
637 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
638 	       24, 0, eq_tlv),
639 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
640 	       24, 0, eq_tlv),
641 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
642 	       24, 0, eq_tlv),
643 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
644 	       24, 0, eq_tlv),
645 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
646 	       24, 0, eq_tlv),
647 
648 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
649 	       24, 0, eq_tlv),
650 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
651 	       24, 0, eq_tlv),
652 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
653 	       24, 0, eq_tlv),
654 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
655 	       24, 0, eq_tlv),
656 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
657 	       24, 0, eq_tlv),
658 
659 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
660 	       24, 0, eq_tlv),
661 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
662 	       24, 0, eq_tlv),
663 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
664 	       24, 0, eq_tlv),
665 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
666 	       24, 0, eq_tlv),
667 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
668 	       24, 0, eq_tlv),
669 
670 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
671 	       24, 0, eq_tlv),
672 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
673 	       24, 0, eq_tlv),
674 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
675 	       24, 0, eq_tlv),
676 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
677 	       24, 0, eq_tlv),
678 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
679 	       24, 0, eq_tlv),
680 
681 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
682 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
683 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
684 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
685 
686 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
687 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
688 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
689 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
690 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
691 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
692 
693 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
694 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
695 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
696 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
697 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
698 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
699 
700 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
701 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
702 
703 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
704 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
705 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
706 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
707 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
708 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
709 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
710 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
711 
712 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
713 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
714 
715 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
716 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
717 
718 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
719 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
720 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
721 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
722 
723 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
724 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
725 SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
726 		   WM5100_DRCL_ENA | WM5100_DRCR_ENA),
727 
728 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
729 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
730 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
731 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
732 };
733 
734 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
735 				enum snd_soc_dapm_type event, int subseq)
736 {
737 	struct snd_soc_codec *codec = container_of(dapm,
738 						   struct snd_soc_codec, dapm);
739 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
740 	u16 val, expect, i;
741 
742 	/* Wait for the outputs to flag themselves as enabled */
743 	if (wm5100->out_ena[0]) {
744 		expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
745 		for (i = 0; i < 200; i++) {
746 			val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
747 			if (val == expect) {
748 				wm5100->out_ena[0] = false;
749 				break;
750 			}
751 		}
752 		if (i == 200) {
753 			dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
754 				expect);
755 		}
756 	}
757 
758 	if (wm5100->out_ena[1]) {
759 		expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
760 		for (i = 0; i < 200; i++) {
761 			val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
762 			if (val == expect) {
763 				wm5100->out_ena[1] = false;
764 				break;
765 			}
766 		}
767 		if (i == 200) {
768 			dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
769 				expect);
770 		}
771 	}
772 }
773 
774 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
775 			 struct snd_kcontrol *kcontrol,
776 			 int event)
777 {
778 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
779 
780 	switch (w->reg) {
781 	case WM5100_CHANNEL_ENABLES_1:
782 		wm5100->out_ena[0] = true;
783 		break;
784 	case WM5100_OUTPUT_ENABLES_2:
785 		wm5100->out_ena[0] = true;
786 		break;
787 	default:
788 		break;
789 	}
790 
791 	return 0;
792 }
793 
794 static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
795 {
796 	if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
797 		dev_crit(wm5100->dev, "Speaker shutdown warning\n");
798 	if (val & WM5100_SPK_SHUTDOWN_EINT)
799 		dev_crit(wm5100->dev, "Speaker shutdown\n");
800 	if (val & WM5100_CLKGEN_ERR_EINT)
801 		dev_crit(wm5100->dev, "SYSCLK underclocked\n");
802 	if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
803 		dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
804 }
805 
806 static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
807 {
808 	if (val & WM5100_AIF3_ERR_EINT)
809 		dev_err(wm5100->dev, "AIF3 configuration error\n");
810 	if (val & WM5100_AIF2_ERR_EINT)
811 		dev_err(wm5100->dev, "AIF2 configuration error\n");
812 	if (val & WM5100_AIF1_ERR_EINT)
813 		dev_err(wm5100->dev, "AIF1 configuration error\n");
814 	if (val & WM5100_CTRLIF_ERR_EINT)
815 		dev_err(wm5100->dev, "Control interface error\n");
816 	if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
817 		dev_err(wm5100->dev, "ISRC2 underclocked\n");
818 	if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
819 		dev_err(wm5100->dev, "ISRC1 underclocked\n");
820 	if (val & WM5100_FX_UNDERCLOCKED_EINT)
821 		dev_err(wm5100->dev, "FX underclocked\n");
822 	if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
823 		dev_err(wm5100->dev, "AIF3 underclocked\n");
824 	if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
825 		dev_err(wm5100->dev, "AIF2 underclocked\n");
826 	if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
827 		dev_err(wm5100->dev, "AIF1 underclocked\n");
828 	if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
829 		dev_err(wm5100->dev, "ASRC underclocked\n");
830 	if (val & WM5100_DAC_UNDERCLOCKED_EINT)
831 		dev_err(wm5100->dev, "DAC underclocked\n");
832 	if (val & WM5100_ADC_UNDERCLOCKED_EINT)
833 		dev_err(wm5100->dev, "ADC underclocked\n");
834 	if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
835 		dev_err(wm5100->dev, "Mixer underclocked\n");
836 }
837 
838 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
839 			  struct snd_kcontrol *kcontrol,
840 			  int event)
841 {
842 	struct snd_soc_codec *codec = w->codec;
843 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
844 	int ret;
845 
846 	ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
847 	ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
848 		WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
849 		WM5100_CLKGEN_ERR_ASYNC_STS;
850 	wm5100_log_status3(wm5100, ret);
851 
852 	ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
853 	wm5100_log_status4(wm5100, ret);
854 
855 	return 0;
856 }
857 
858 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
859 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
860 		    NULL, 0),
861 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
862 		    0, NULL, 0),
863 
864 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
865 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
866 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
867 
868 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
869 		    NULL, 0),
870 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
871 		    NULL, 0),
872 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
873 		    WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
874 
875 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
876 		    0, NULL, 0),
877 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
878 		    0, NULL, 0),
879 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
880 		    0, NULL, 0),
881 
882 SND_SOC_DAPM_INPUT("IN1L"),
883 SND_SOC_DAPM_INPUT("IN1R"),
884 SND_SOC_DAPM_INPUT("IN2L"),
885 SND_SOC_DAPM_INPUT("IN2R"),
886 SND_SOC_DAPM_INPUT("IN3L"),
887 SND_SOC_DAPM_INPUT("IN3R"),
888 SND_SOC_DAPM_INPUT("IN4L"),
889 SND_SOC_DAPM_INPUT("IN4R"),
890 SND_SOC_DAPM_SIGGEN("TONE"),
891 
892 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
893 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
894 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
895 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
896 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
897 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
898 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
899 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
900 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
901 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
902 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
903 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
904 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
905 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
906 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
907 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
908 
909 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
910 		 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
911 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
912 		 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
913 
914 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
915 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
916 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
917 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
918 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
919 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
920 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
921 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
922 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
923 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
924 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
925 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
926 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
927 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
928 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
929 		    WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
930 
931 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
932 		    WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
933 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
934 		    WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
935 
936 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
937 		    WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
938 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
939 		    WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
940 
941 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
942 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
943 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
944 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
945 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
946 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
947 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
948 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
949 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
950 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
951 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
952 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
953 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
954 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
955 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
956 		    WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
957 
958 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
959 		    WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
960 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
961 		    WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
962 
963 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
964 		    WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
965 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
966 		    WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
967 
968 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
969 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
970 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
971 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
972 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
973 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
974 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
975 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
976 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
977 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
978 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
979 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
980 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
981 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
982 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
983 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
984 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
985 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
986 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
987 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
988 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
989 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
990 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
991 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
992 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
993 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
994 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
995 		   NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
996 
997 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
998 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
999 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1001 
1002 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1003 		 NULL, 0),
1004 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1005 		 NULL, 0),
1006 
1007 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1008 		 NULL, 0),
1009 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1010 		 NULL, 0),
1011 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1012 		 NULL, 0),
1013 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1014 		 NULL, 0),
1015 
1016 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1017 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1018 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1019 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1020 
1021 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1022 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1023 
1024 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1025 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1026 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1027 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1028 
1029 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1030 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1031 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1032 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1033 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1034 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1035 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1036 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1037 
1038 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1039 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1040 
1041 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1042 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1043 
1044 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1045 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1046 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1047 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1048 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1049 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1050 
1051 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1052 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1053 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1054 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1055 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1056 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1057 
1058 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1059 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1060 
1061 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1062 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1063 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1067 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1068 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1069 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1070 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1071 SND_SOC_DAPM_OUTPUT("PWM1"),
1072 SND_SOC_DAPM_OUTPUT("PWM2"),
1073 };
1074 
1075 /* We register a _POST event if we don't have IRQ support so we can
1076  * look at the error status from the CODEC - if we've got the IRQ
1077  * hooked up then we will get prompted to look by an interrupt.
1078  */
1079 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1080 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1081 };
1082 
1083 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1084 	{ "CP1", NULL, "CPVDD" },
1085 	{ "CP2 Active", NULL, "CPVDD" },
1086 
1087 	{ "IN1L", NULL, "SYSCLK" },
1088 	{ "IN1R", NULL, "SYSCLK" },
1089 	{ "IN2L", NULL, "SYSCLK" },
1090 	{ "IN2R", NULL, "SYSCLK" },
1091 	{ "IN3L", NULL, "SYSCLK" },
1092 	{ "IN3R", NULL, "SYSCLK" },
1093 	{ "IN4L", NULL, "SYSCLK" },
1094 	{ "IN4R", NULL, "SYSCLK" },
1095 
1096 	{ "OUT1L", NULL, "SYSCLK" },
1097 	{ "OUT1R", NULL, "SYSCLK" },
1098 	{ "OUT2L", NULL, "SYSCLK" },
1099 	{ "OUT2R", NULL, "SYSCLK" },
1100 	{ "OUT3L", NULL, "SYSCLK" },
1101 	{ "OUT3R", NULL, "SYSCLK" },
1102 	{ "OUT4L", NULL, "SYSCLK" },
1103 	{ "OUT4R", NULL, "SYSCLK" },
1104 	{ "OUT5L", NULL, "SYSCLK" },
1105 	{ "OUT5R", NULL, "SYSCLK" },
1106 	{ "OUT6L", NULL, "SYSCLK" },
1107 	{ "OUT6R", NULL, "SYSCLK" },
1108 
1109 	{ "AIF1RX1", NULL, "SYSCLK" },
1110 	{ "AIF1RX2", NULL, "SYSCLK" },
1111 	{ "AIF1RX3", NULL, "SYSCLK" },
1112 	{ "AIF1RX4", NULL, "SYSCLK" },
1113 	{ "AIF1RX5", NULL, "SYSCLK" },
1114 	{ "AIF1RX6", NULL, "SYSCLK" },
1115 	{ "AIF1RX7", NULL, "SYSCLK" },
1116 	{ "AIF1RX8", NULL, "SYSCLK" },
1117 
1118 	{ "AIF2RX1", NULL, "SYSCLK" },
1119 	{ "AIF2RX1", NULL, "DBVDD2" },
1120 	{ "AIF2RX2", NULL, "SYSCLK" },
1121 	{ "AIF2RX2", NULL, "DBVDD2" },
1122 
1123 	{ "AIF3RX1", NULL, "SYSCLK" },
1124 	{ "AIF3RX1", NULL, "DBVDD3" },
1125 	{ "AIF3RX2", NULL, "SYSCLK" },
1126 	{ "AIF3RX2", NULL, "DBVDD3" },
1127 
1128 	{ "AIF1TX1", NULL, "SYSCLK" },
1129 	{ "AIF1TX2", NULL, "SYSCLK" },
1130 	{ "AIF1TX3", NULL, "SYSCLK" },
1131 	{ "AIF1TX4", NULL, "SYSCLK" },
1132 	{ "AIF1TX5", NULL, "SYSCLK" },
1133 	{ "AIF1TX6", NULL, "SYSCLK" },
1134 	{ "AIF1TX7", NULL, "SYSCLK" },
1135 	{ "AIF1TX8", NULL, "SYSCLK" },
1136 
1137 	{ "AIF2TX1", NULL, "SYSCLK" },
1138 	{ "AIF2TX1", NULL, "DBVDD2" },
1139 	{ "AIF2TX2", NULL, "SYSCLK" },
1140 	{ "AIF2TX2", NULL, "DBVDD2" },
1141 
1142 	{ "AIF3TX1", NULL, "SYSCLK" },
1143 	{ "AIF3TX1", NULL, "DBVDD3" },
1144 	{ "AIF3TX2", NULL, "SYSCLK" },
1145 	{ "AIF3TX2", NULL, "DBVDD3" },
1146 
1147 	{ "MICBIAS1", NULL, "CP2" },
1148 	{ "MICBIAS2", NULL, "CP2" },
1149 	{ "MICBIAS3", NULL, "CP2" },
1150 
1151 	{ "IN1L PGA", NULL, "CP2" },
1152 	{ "IN1R PGA", NULL, "CP2" },
1153 	{ "IN2L PGA", NULL, "CP2" },
1154 	{ "IN2R PGA", NULL, "CP2" },
1155 	{ "IN3L PGA", NULL, "CP2" },
1156 	{ "IN3R PGA", NULL, "CP2" },
1157 	{ "IN4L PGA", NULL, "CP2" },
1158 	{ "IN4R PGA", NULL, "CP2" },
1159 
1160 	{ "IN1L PGA", NULL, "CP2 Active" },
1161 	{ "IN1R PGA", NULL, "CP2 Active" },
1162 	{ "IN2L PGA", NULL, "CP2 Active" },
1163 	{ "IN2R PGA", NULL, "CP2 Active" },
1164 	{ "IN3L PGA", NULL, "CP2 Active" },
1165 	{ "IN3R PGA", NULL, "CP2 Active" },
1166 	{ "IN4L PGA", NULL, "CP2 Active" },
1167 	{ "IN4R PGA", NULL, "CP2 Active" },
1168 
1169 	{ "OUT1L", NULL, "CP1" },
1170 	{ "OUT1R", NULL, "CP1" },
1171 	{ "OUT2L", NULL, "CP1" },
1172 	{ "OUT2R", NULL, "CP1" },
1173 	{ "OUT3L", NULL, "CP1" },
1174 	{ "OUT3R", NULL, "CP1" },
1175 
1176 	{ "Tone Generator 1", NULL, "TONE" },
1177 	{ "Tone Generator 2", NULL, "TONE" },
1178 
1179 	{ "IN1L PGA", NULL, "IN1L" },
1180 	{ "IN1R PGA", NULL, "IN1R" },
1181 	{ "IN2L PGA", NULL, "IN2L" },
1182 	{ "IN2R PGA", NULL, "IN2R" },
1183 	{ "IN3L PGA", NULL, "IN3L" },
1184 	{ "IN3R PGA", NULL, "IN3R" },
1185 	{ "IN4L PGA", NULL, "IN4L" },
1186 	{ "IN4R PGA", NULL, "IN4R" },
1187 
1188 	WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1189 	WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1190 	WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1191 	WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1192 	WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1193 	WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1194 
1195 	WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1196 	WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1197 	WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1198 	WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1199 	WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1200 	WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1201 
1202 	WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1203 	WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1204 
1205 	WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1206 	WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1207 	WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1208 	WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1209 	WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1210 	WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1211 	WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1212 	WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1213 
1214 	WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1215 	WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1216 
1217 	WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1218 	WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1219 
1220 	WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1221 	WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1222 	WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1223 	WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1224 
1225 	WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1226 	WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1227 
1228 	WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1229 	WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1230 	WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1231 	WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1232 
1233 	{ "HPOUT1L", NULL, "OUT1L" },
1234 	{ "HPOUT1R", NULL, "OUT1R" },
1235 	{ "HPOUT2L", NULL, "OUT2L" },
1236 	{ "HPOUT2R", NULL, "OUT2R" },
1237 	{ "HPOUT3L", NULL, "OUT3L" },
1238 	{ "HPOUT3R", NULL, "OUT3R" },
1239 	{ "SPKOUTL", NULL, "OUT4L" },
1240 	{ "SPKOUTR", NULL, "OUT4R" },
1241 	{ "SPKDAT1", NULL, "OUT5L" },
1242 	{ "SPKDAT1", NULL, "OUT5R" },
1243 	{ "SPKDAT2", NULL, "OUT6L" },
1244 	{ "SPKDAT2", NULL, "OUT6R" },
1245 	{ "PWM1", NULL, "PWM1 Driver" },
1246 	{ "PWM2", NULL, "PWM2 Driver" },
1247 };
1248 
1249 static const struct reg_default wm5100_reva_patches[] = {
1250 	{ WM5100_AUDIO_IF_1_10, 0 },
1251 	{ WM5100_AUDIO_IF_1_11, 1 },
1252 	{ WM5100_AUDIO_IF_1_12, 2 },
1253 	{ WM5100_AUDIO_IF_1_13, 3 },
1254 	{ WM5100_AUDIO_IF_1_14, 4 },
1255 	{ WM5100_AUDIO_IF_1_15, 5 },
1256 	{ WM5100_AUDIO_IF_1_16, 6 },
1257 	{ WM5100_AUDIO_IF_1_17, 7 },
1258 
1259 	{ WM5100_AUDIO_IF_1_18, 0 },
1260 	{ WM5100_AUDIO_IF_1_19, 1 },
1261 	{ WM5100_AUDIO_IF_1_20, 2 },
1262 	{ WM5100_AUDIO_IF_1_21, 3 },
1263 	{ WM5100_AUDIO_IF_1_22, 4 },
1264 	{ WM5100_AUDIO_IF_1_23, 5 },
1265 	{ WM5100_AUDIO_IF_1_24, 6 },
1266 	{ WM5100_AUDIO_IF_1_25, 7 },
1267 
1268 	{ WM5100_AUDIO_IF_2_10, 0 },
1269 	{ WM5100_AUDIO_IF_2_11, 1 },
1270 
1271 	{ WM5100_AUDIO_IF_2_18, 0 },
1272 	{ WM5100_AUDIO_IF_2_19, 1 },
1273 
1274 	{ WM5100_AUDIO_IF_3_10, 0 },
1275 	{ WM5100_AUDIO_IF_3_11, 1 },
1276 
1277 	{ WM5100_AUDIO_IF_3_18, 0 },
1278 	{ WM5100_AUDIO_IF_3_19, 1 },
1279 };
1280 
1281 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1282 {
1283 	struct snd_soc_codec *codec = dai->codec;
1284 	int lrclk, bclk, mask, base;
1285 
1286 	base = dai->driver->base;
1287 
1288 	lrclk = 0;
1289 	bclk = 0;
1290 
1291 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1292 	case SND_SOC_DAIFMT_DSP_A:
1293 		mask = 0;
1294 		break;
1295 	case SND_SOC_DAIFMT_I2S:
1296 		mask = 2;
1297 		break;
1298 	default:
1299 		dev_err(codec->dev, "Unsupported DAI format %d\n",
1300 			fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1301 		return -EINVAL;
1302 	}
1303 
1304 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1305 	case SND_SOC_DAIFMT_CBS_CFS:
1306 		break;
1307 	case SND_SOC_DAIFMT_CBS_CFM:
1308 		lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1309 		break;
1310 	case SND_SOC_DAIFMT_CBM_CFS:
1311 		bclk |= WM5100_AIF1_BCLK_MSTR;
1312 		break;
1313 	case SND_SOC_DAIFMT_CBM_CFM:
1314 		lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1315 		bclk |= WM5100_AIF1_BCLK_MSTR;
1316 		break;
1317 	default:
1318 		dev_err(codec->dev, "Unsupported master mode %d\n",
1319 			fmt & SND_SOC_DAIFMT_MASTER_MASK);
1320 		return -EINVAL;
1321 	}
1322 
1323 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1324 	case SND_SOC_DAIFMT_NB_NF:
1325 		break;
1326 	case SND_SOC_DAIFMT_IB_IF:
1327 		bclk |= WM5100_AIF1_BCLK_INV;
1328 		lrclk |= WM5100_AIF1TX_LRCLK_INV;
1329 		break;
1330 	case SND_SOC_DAIFMT_IB_NF:
1331 		bclk |= WM5100_AIF1_BCLK_INV;
1332 		break;
1333 	case SND_SOC_DAIFMT_NB_IF:
1334 		lrclk |= WM5100_AIF1TX_LRCLK_INV;
1335 		break;
1336 	default:
1337 		return -EINVAL;
1338 	}
1339 
1340 	snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1341 			    WM5100_AIF1_BCLK_INV, bclk);
1342 	snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1343 			    WM5100_AIF1TX_LRCLK_INV, lrclk);
1344 	snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1345 			    WM5100_AIF1TX_LRCLK_INV, lrclk);
1346 	snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1347 
1348 	return 0;
1349 }
1350 
1351 #define WM5100_NUM_BCLK_RATES 19
1352 
1353 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1354 	32000,
1355 	48000,
1356 	64000,
1357 	96000,
1358 	128000,
1359 	192000,
1360 	256000,
1361 	384000,
1362 	512000,
1363 	768000,
1364 	1024000,
1365 	1536000,
1366 	2048000,
1367 	3072000,
1368 	4096000,
1369 	6144000,
1370 	8192000,
1371 	12288000,
1372 	24576000,
1373 };
1374 
1375 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1376 	29400,
1377 	44100,
1378 	58800,
1379 	88200,
1380 	117600,
1381 	176400,
1382 	235200,
1383 	352800,
1384 	470400,
1385 	705600,
1386 	940800,
1387 	1411200,
1388 	1881600,
1389 	2882400,
1390 	3763200,
1391 	5644800,
1392 	7526400,
1393 	11289600,
1394 	22579600,
1395 };
1396 
1397 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1398 			    struct snd_pcm_hw_params *params,
1399 			    struct snd_soc_dai *dai)
1400 {
1401 	struct snd_soc_codec *codec = dai->codec;
1402 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1403 	bool async = wm5100->aif_async[dai->id];
1404 	int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1405 	int *bclk_rates;
1406 
1407 	base = dai->driver->base;
1408 
1409 	/* Data sizes if not using TDM */
1410 	wl = snd_pcm_format_width(params_format(params));
1411 	if (wl < 0)
1412 		return wl;
1413 	fl = snd_soc_params_to_frame_size(params);
1414 	if (fl < 0)
1415 		return fl;
1416 
1417 	dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1418 		wl, fl);
1419 
1420 	/* Target BCLK rate */
1421 	bclk = snd_soc_params_to_bclk(params);
1422 	if (bclk < 0)
1423 		return bclk;
1424 
1425 	/* Root for BCLK depends on SYS/ASYNCCLK */
1426 	if (!async) {
1427 		aif_rate = wm5100->sysclk;
1428 		sr = wm5100_alloc_sr(codec, params_rate(params));
1429 		if (sr < 0)
1430 			return sr;
1431 	} else {
1432 		/* If we're in ASYNCCLK set the ASYNC sample rate */
1433 		aif_rate = wm5100->asyncclk;
1434 		sr = 3;
1435 
1436 		for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1437 			if (params_rate(params) == wm5100_sr_code[i])
1438 				break;
1439 		if (i == ARRAY_SIZE(wm5100_sr_code)) {
1440 			dev_err(codec->dev, "Invalid rate %dHzn",
1441 				params_rate(params));
1442 			return -EINVAL;
1443 		}
1444 
1445 		/* TODO: We should really check for symmetry */
1446 		snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1447 				    WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1448 	}
1449 
1450 	if (!aif_rate) {
1451 		dev_err(codec->dev, "%s has no rate set\n",
1452 			async ? "ASYNCCLK" : "SYSCLK");
1453 		return -EINVAL;
1454 	}
1455 
1456 	dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1457 		bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1458 
1459 	if (aif_rate % 4000)
1460 		bclk_rates = wm5100_bclk_rates_cd;
1461 	else
1462 		bclk_rates = wm5100_bclk_rates_dat;
1463 
1464 	for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1465 		if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1466 			break;
1467 	if (i == WM5100_NUM_BCLK_RATES) {
1468 		dev_err(codec->dev,
1469 			"No valid BCLK for %dHz found from %dHz %s\n",
1470 			bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1471 		return -EINVAL;
1472 	}
1473 
1474 	bclk = i;
1475 	dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1476 	snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1477 
1478 	lrclk = bclk_rates[bclk] / params_rate(params);
1479 	dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1480 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1481 	    wm5100->aif_symmetric[dai->id])
1482 		snd_soc_update_bits(codec, base + 7,
1483 				    WM5100_AIF1RX_BCPF_MASK, lrclk);
1484 	else
1485 		snd_soc_update_bits(codec, base + 6,
1486 				    WM5100_AIF1TX_BCPF_MASK, lrclk);
1487 
1488 	i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1489 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1490 		snd_soc_update_bits(codec, base + 9,
1491 				    WM5100_AIF1RX_WL_MASK |
1492 				    WM5100_AIF1RX_SLOT_LEN_MASK, i);
1493 	else
1494 		snd_soc_update_bits(codec, base + 8,
1495 				    WM5100_AIF1TX_WL_MASK |
1496 				    WM5100_AIF1TX_SLOT_LEN_MASK, i);
1497 
1498 	snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1499 
1500 	return 0;
1501 }
1502 
1503 static const struct snd_soc_dai_ops wm5100_dai_ops = {
1504 	.set_fmt = wm5100_set_fmt,
1505 	.hw_params = wm5100_hw_params,
1506 };
1507 
1508 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1509 			     int source, unsigned int freq, int dir)
1510 {
1511 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1512 	int *rate_store;
1513 	int fval, audio_rate, ret, reg;
1514 
1515 	switch (clk_id) {
1516 	case WM5100_CLK_SYSCLK:
1517 		reg = WM5100_CLOCKING_3;
1518 		rate_store = &wm5100->sysclk;
1519 		break;
1520 	case WM5100_CLK_ASYNCCLK:
1521 		reg = WM5100_CLOCKING_7;
1522 		rate_store = &wm5100->asyncclk;
1523 		break;
1524 	case WM5100_CLK_32KHZ:
1525 		/* The 32kHz clock is slightly different to the others */
1526 		switch (source) {
1527 		case WM5100_CLKSRC_MCLK1:
1528 		case WM5100_CLKSRC_MCLK2:
1529 		case WM5100_CLKSRC_SYSCLK:
1530 			snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1531 					    WM5100_CLK_32K_SRC_MASK,
1532 					    source);
1533 			break;
1534 		default:
1535 			return -EINVAL;
1536 		}
1537 		return 0;
1538 
1539 	case WM5100_CLK_AIF1:
1540 	case WM5100_CLK_AIF2:
1541 	case WM5100_CLK_AIF3:
1542 		/* Not real clocks, record which clock domain they're in */
1543 		switch (source) {
1544 		case WM5100_CLKSRC_SYSCLK:
1545 			wm5100->aif_async[clk_id - 1] = false;
1546 			break;
1547 		case WM5100_CLKSRC_ASYNCCLK:
1548 			wm5100->aif_async[clk_id - 1] = true;
1549 			break;
1550 		default:
1551 			dev_err(codec->dev, "Invalid source %d\n", source);
1552 			return -EINVAL;
1553 		}
1554 		return 0;
1555 
1556 	case WM5100_CLK_OPCLK:
1557 		switch (freq) {
1558 		case 5644800:
1559 		case 6144000:
1560 			snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1561 					    WM5100_OPCLK_SEL_MASK, 0);
1562 			break;
1563 		case 11289600:
1564 		case 12288000:
1565 			snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1566 					    WM5100_OPCLK_SEL_MASK, 0);
1567 			break;
1568 		case 22579200:
1569 		case 24576000:
1570 			snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1571 					    WM5100_OPCLK_SEL_MASK, 0);
1572 			break;
1573 		default:
1574 			dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1575 				freq);
1576 			return -EINVAL;
1577 		}
1578 		return 0;
1579 
1580 	default:
1581 		dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1582 		return -EINVAL;
1583 	}
1584 
1585 	switch (source) {
1586 	case WM5100_CLKSRC_SYSCLK:
1587 	case WM5100_CLKSRC_ASYNCCLK:
1588 		dev_err(codec->dev, "Invalid source %d\n", source);
1589 		return -EINVAL;
1590 	}
1591 
1592 	switch (freq) {
1593 	case 5644800:
1594 	case 6144000:
1595 		fval = 0;
1596 		break;
1597 	case 11289600:
1598 	case 12288000:
1599 		fval = 1;
1600 		break;
1601 	case 22579200:
1602 	case 24576000:
1603 		fval = 2;
1604 		break;
1605 	default:
1606 		dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1607 		return -EINVAL;
1608 	}
1609 
1610 	switch (freq) {
1611 	case 5644800:
1612 	case 11289600:
1613 	case 22579200:
1614 		audio_rate = 44100;
1615 		break;
1616 
1617 	case 6144000:
1618 	case 12288000:
1619 	case 24576000:
1620 		audio_rate = 48000;
1621 		break;
1622 
1623 	default:
1624 		BUG();
1625 		audio_rate = 0;
1626 		break;
1627 	}
1628 
1629 	/* TODO: Check if MCLKs are in use and enable/disable pulls to
1630 	 * match.
1631 	 */
1632 
1633 	snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1634 			    WM5100_SYSCLK_SRC_MASK,
1635 			    fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1636 
1637 	/* If this is SYSCLK then configure the clock rate for the
1638 	 * internal audio functions to the natural sample rate for
1639 	 * this clock rate.
1640 	 */
1641 	if (clk_id == WM5100_CLK_SYSCLK) {
1642 		dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1643 			audio_rate);
1644 		if (0 && *rate_store)
1645 			wm5100_free_sr(codec, audio_rate);
1646 		ret = wm5100_alloc_sr(codec, audio_rate);
1647 		if (ret != 0)
1648 			dev_warn(codec->dev, "Primary audio slot is %d\n",
1649 				 ret);
1650 	}
1651 
1652 	*rate_store = freq;
1653 
1654 	return 0;
1655 }
1656 
1657 struct _fll_div {
1658 	u16 fll_fratio;
1659 	u16 fll_outdiv;
1660 	u16 fll_refclk_div;
1661 	u16 n;
1662 	u16 theta;
1663 	u16 lambda;
1664 };
1665 
1666 static struct {
1667 	unsigned int min;
1668 	unsigned int max;
1669 	u16 fll_fratio;
1670 	int ratio;
1671 } fll_fratios[] = {
1672 	{       0,    64000, 4, 16 },
1673 	{   64000,   128000, 3,  8 },
1674 	{  128000,   256000, 2,  4 },
1675 	{  256000,  1000000, 1,  2 },
1676 	{ 1000000, 13500000, 0,  1 },
1677 };
1678 
1679 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1680 		       unsigned int Fout)
1681 {
1682 	unsigned int target;
1683 	unsigned int div;
1684 	unsigned int fratio, gcd_fll;
1685 	int i;
1686 
1687 	/* Fref must be <=13.5MHz */
1688 	div = 1;
1689 	fll_div->fll_refclk_div = 0;
1690 	while ((Fref / div) > 13500000) {
1691 		div *= 2;
1692 		fll_div->fll_refclk_div++;
1693 
1694 		if (div > 8) {
1695 			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1696 			       Fref);
1697 			return -EINVAL;
1698 		}
1699 	}
1700 
1701 	pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1702 
1703 	/* Apply the division for our remaining calculations */
1704 	Fref /= div;
1705 
1706 	/* Fvco should be 90-100MHz; don't check the upper bound */
1707 	div = 2;
1708 	while (Fout * div < 90000000) {
1709 		div++;
1710 		if (div > 64) {
1711 			pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1712 			       Fout);
1713 			return -EINVAL;
1714 		}
1715 	}
1716 	target = Fout * div;
1717 	fll_div->fll_outdiv = div - 1;
1718 
1719 	pr_debug("FLL Fvco=%dHz\n", target);
1720 
1721 	/* Find an appropraite FLL_FRATIO and factor it out of the target */
1722 	for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1723 		if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1724 			fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1725 			fratio = fll_fratios[i].ratio;
1726 			break;
1727 		}
1728 	}
1729 	if (i == ARRAY_SIZE(fll_fratios)) {
1730 		pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1731 		return -EINVAL;
1732 	}
1733 
1734 	fll_div->n = target / (fratio * Fref);
1735 
1736 	if (target % Fref == 0) {
1737 		fll_div->theta = 0;
1738 		fll_div->lambda = 0;
1739 	} else {
1740 		gcd_fll = gcd(target, fratio * Fref);
1741 
1742 		fll_div->theta = (target - (fll_div->n * fratio * Fref))
1743 			/ gcd_fll;
1744 		fll_div->lambda = (fratio * Fref) / gcd_fll;
1745 	}
1746 
1747 	pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1748 		 fll_div->n, fll_div->theta, fll_div->lambda);
1749 	pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1750 		 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1751 		 fll_div->fll_refclk_div);
1752 
1753 	return 0;
1754 }
1755 
1756 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1757 			  unsigned int Fref, unsigned int Fout)
1758 {
1759 	struct i2c_client *i2c = to_i2c_client(codec->dev);
1760 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1761 	struct _fll_div factors;
1762 	struct wm5100_fll *fll;
1763 	int ret, base, lock, i, timeout;
1764 
1765 	switch (fll_id) {
1766 	case WM5100_FLL1:
1767 		fll = &wm5100->fll[0];
1768 		base = WM5100_FLL1_CONTROL_1 - 1;
1769 		lock = WM5100_FLL1_LOCK_STS;
1770 		break;
1771 	case WM5100_FLL2:
1772 		fll = &wm5100->fll[1];
1773 		base = WM5100_FLL2_CONTROL_2 - 1;
1774 		lock = WM5100_FLL2_LOCK_STS;
1775 		break;
1776 	default:
1777 		dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1778 		return -EINVAL;
1779 	}
1780 
1781 	if (!Fout) {
1782 		dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1783 		if (fll->fout)
1784 			pm_runtime_put(codec->dev);
1785 		fll->fout = 0;
1786 		snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1787 		return 0;
1788 	}
1789 
1790 	switch (source) {
1791 	case WM5100_FLL_SRC_MCLK1:
1792 	case WM5100_FLL_SRC_MCLK2:
1793 	case WM5100_FLL_SRC_FLL1:
1794 	case WM5100_FLL_SRC_FLL2:
1795 	case WM5100_FLL_SRC_AIF1BCLK:
1796 	case WM5100_FLL_SRC_AIF2BCLK:
1797 	case WM5100_FLL_SRC_AIF3BCLK:
1798 		break;
1799 	default:
1800 		dev_err(codec->dev, "Invalid FLL source %d\n", source);
1801 		return -EINVAL;
1802 	}
1803 
1804 	ret = fll_factors(&factors, Fref, Fout);
1805 	if (ret < 0)
1806 		return ret;
1807 
1808 	/* Disable the FLL while we reconfigure */
1809 	snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1810 
1811 	snd_soc_update_bits(codec, base + 2,
1812 			    WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1813 			    (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1814 			    factors.fll_fratio);
1815 	snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1816 			    factors.theta);
1817 	snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1818 	snd_soc_update_bits(codec, base + 6,
1819 			    WM5100_FLL1_REFCLK_DIV_MASK |
1820 			    WM5100_FLL1_REFCLK_SRC_MASK,
1821 			    (factors.fll_refclk_div
1822 			     << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1823 	snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1824 			    factors.lambda);
1825 
1826 	/* Clear any pending completions */
1827 	try_wait_for_completion(&fll->lock);
1828 
1829 	pm_runtime_get_sync(codec->dev);
1830 
1831 	snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1832 
1833 	if (i2c->irq)
1834 		timeout = 2;
1835 	else
1836 		timeout = 50;
1837 
1838 	snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1839 			    WM5100_SYSCLK_ENA);
1840 
1841 	/* Poll for the lock; will use interrupt when we can test */
1842 	for (i = 0; i < timeout; i++) {
1843 		if (i2c->irq) {
1844 			ret = wait_for_completion_timeout(&fll->lock,
1845 							  msecs_to_jiffies(25));
1846 			if (ret > 0)
1847 				break;
1848 		} else {
1849 			msleep(1);
1850 		}
1851 
1852 		ret = snd_soc_read(codec,
1853 				   WM5100_INTERRUPT_RAW_STATUS_3);
1854 		if (ret < 0) {
1855 			dev_err(codec->dev,
1856 				"Failed to read FLL status: %d\n",
1857 				ret);
1858 			continue;
1859 		}
1860 		if (ret & lock)
1861 			break;
1862 	}
1863 	if (i == timeout) {
1864 		dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1865 		pm_runtime_put(codec->dev);
1866 		return -ETIMEDOUT;
1867 	}
1868 
1869 	fll->src = source;
1870 	fll->fref = Fref;
1871 	fll->fout = Fout;
1872 
1873 	dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1874 		Fref, Fout);
1875 
1876 	return 0;
1877 }
1878 
1879 /* Actually go much higher */
1880 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1881 
1882 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1883 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1884 
1885 static struct snd_soc_dai_driver wm5100_dai[] = {
1886 	{
1887 		.name = "wm5100-aif1",
1888 		.base = WM5100_AUDIO_IF_1_1 - 1,
1889 		.playback = {
1890 			.stream_name = "AIF1 Playback",
1891 			.channels_min = 2,
1892 			.channels_max = 2,
1893 			.rates = WM5100_RATES,
1894 			.formats = WM5100_FORMATS,
1895 		},
1896 		.capture = {
1897 			 .stream_name = "AIF1 Capture",
1898 			 .channels_min = 2,
1899 			 .channels_max = 2,
1900 			 .rates = WM5100_RATES,
1901 			 .formats = WM5100_FORMATS,
1902 		 },
1903 		.ops = &wm5100_dai_ops,
1904 	},
1905 	{
1906 		.name = "wm5100-aif2",
1907 		.id = 1,
1908 		.base = WM5100_AUDIO_IF_2_1 - 1,
1909 		.playback = {
1910 			.stream_name = "AIF2 Playback",
1911 			.channels_min = 2,
1912 			.channels_max = 2,
1913 			.rates = WM5100_RATES,
1914 			.formats = WM5100_FORMATS,
1915 		},
1916 		.capture = {
1917 			 .stream_name = "AIF2 Capture",
1918 			 .channels_min = 2,
1919 			 .channels_max = 2,
1920 			 .rates = WM5100_RATES,
1921 			 .formats = WM5100_FORMATS,
1922 		 },
1923 		.ops = &wm5100_dai_ops,
1924 	},
1925 	{
1926 		.name = "wm5100-aif3",
1927 		.id = 2,
1928 		.base = WM5100_AUDIO_IF_3_1 - 1,
1929 		.playback = {
1930 			.stream_name = "AIF3 Playback",
1931 			.channels_min = 2,
1932 			.channels_max = 2,
1933 			.rates = WM5100_RATES,
1934 			.formats = WM5100_FORMATS,
1935 		},
1936 		.capture = {
1937 			 .stream_name = "AIF3 Capture",
1938 			 .channels_min = 2,
1939 			 .channels_max = 2,
1940 			 .rates = WM5100_RATES,
1941 			 .formats = WM5100_FORMATS,
1942 		 },
1943 		.ops = &wm5100_dai_ops,
1944 	},
1945 };
1946 
1947 static int wm5100_dig_vu[] = {
1948 	WM5100_ADC_DIGITAL_VOLUME_1L,
1949 	WM5100_ADC_DIGITAL_VOLUME_1R,
1950 	WM5100_ADC_DIGITAL_VOLUME_2L,
1951 	WM5100_ADC_DIGITAL_VOLUME_2R,
1952 	WM5100_ADC_DIGITAL_VOLUME_3L,
1953 	WM5100_ADC_DIGITAL_VOLUME_3R,
1954 	WM5100_ADC_DIGITAL_VOLUME_4L,
1955 	WM5100_ADC_DIGITAL_VOLUME_4R,
1956 
1957 	WM5100_DAC_DIGITAL_VOLUME_1L,
1958 	WM5100_DAC_DIGITAL_VOLUME_1R,
1959 	WM5100_DAC_DIGITAL_VOLUME_2L,
1960 	WM5100_DAC_DIGITAL_VOLUME_2R,
1961 	WM5100_DAC_DIGITAL_VOLUME_3L,
1962 	WM5100_DAC_DIGITAL_VOLUME_3R,
1963 	WM5100_DAC_DIGITAL_VOLUME_4L,
1964 	WM5100_DAC_DIGITAL_VOLUME_4R,
1965 	WM5100_DAC_DIGITAL_VOLUME_5L,
1966 	WM5100_DAC_DIGITAL_VOLUME_5R,
1967 	WM5100_DAC_DIGITAL_VOLUME_6L,
1968 	WM5100_DAC_DIGITAL_VOLUME_6R,
1969 };
1970 
1971 static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
1972 {
1973 	struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1974 
1975 	BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
1976 
1977 	gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
1978 	regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1979 			   WM5100_ACCDET_BIAS_SRC_MASK |
1980 			   WM5100_ACCDET_SRC,
1981 			   (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1982 			   mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1983 	regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1984 			   WM5100_HPCOM_SRC,
1985 			   mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
1986 
1987 	wm5100->jack_mode = the_mode;
1988 
1989 	dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
1990 		wm5100->jack_mode);
1991 }
1992 
1993 static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1994 {
1995 	dev_dbg(wm5100->dev, "Headphone detected\n");
1996 	wm5100->jack_detecting = false;
1997 	snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
1998 			    SND_JACK_HEADPHONE);
1999 
2000 	/* Increase the detection rate a bit for responsiveness. */
2001 	regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2002 			   WM5100_ACCDET_RATE_MASK,
2003 			   7 << WM5100_ACCDET_RATE_SHIFT);
2004 }
2005 
2006 static void wm5100_micd_irq(struct wm5100_priv *wm5100)
2007 {
2008 	unsigned int val;
2009 	int ret;
2010 
2011 	ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2012 	if (ret != 0) {
2013 		dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2014 			ret);
2015 		return;
2016 	}
2017 
2018 	dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
2019 
2020 	if (!(val & WM5100_ACCDET_VALID)) {
2021 		dev_warn(wm5100->dev, "Microphone detection state invalid\n");
2022 		return;
2023 	}
2024 
2025 	/* No accessory, reset everything and report removal */
2026 	if (!(val & WM5100_ACCDET_STS)) {
2027 		dev_dbg(wm5100->dev, "Jack removal detected\n");
2028 		wm5100->jack_mic = false;
2029 		wm5100->jack_detecting = true;
2030 		wm5100->jack_flips = 0;
2031 		snd_soc_jack_report(wm5100->jack, 0,
2032 				    SND_JACK_LINEOUT | SND_JACK_HEADSET |
2033 				    SND_JACK_BTN_0);
2034 
2035 		regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2036 				   WM5100_ACCDET_RATE_MASK,
2037 				   WM5100_ACCDET_RATE_MASK);
2038 		return;
2039 	}
2040 
2041 	/* If the measurement is very high we've got a microphone,
2042 	 * either we just detected one or if we already reported then
2043 	 * we've got a button release event.
2044 	 */
2045 	if (val & 0x400) {
2046 		if (wm5100->jack_detecting) {
2047 			dev_dbg(wm5100->dev, "Microphone detected\n");
2048 			wm5100->jack_mic = true;
2049 			wm5100->jack_detecting = false;
2050 			snd_soc_jack_report(wm5100->jack,
2051 					    SND_JACK_HEADSET,
2052 					    SND_JACK_HEADSET | SND_JACK_BTN_0);
2053 
2054 			/* Increase poll rate to give better responsiveness
2055 			 * for buttons */
2056 			regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2057 					   WM5100_ACCDET_RATE_MASK,
2058 					   5 << WM5100_ACCDET_RATE_SHIFT);
2059 		} else {
2060 			dev_dbg(wm5100->dev, "Mic button up\n");
2061 			snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2062 		}
2063 
2064 		return;
2065 	}
2066 
2067 	/* If we detected a lower impedence during initial startup
2068 	 * then we probably have the wrong polarity, flip it.  Don't
2069 	 * do this for the lowest impedences to speed up detection of
2070 	 * plain headphones and give up if neither polarity looks
2071 	 * sensible.
2072 	 */
2073 	if (wm5100->jack_detecting && (val & 0x3f8)) {
2074 		wm5100->jack_flips++;
2075 
2076 		if (wm5100->jack_flips > 1)
2077 			wm5100_report_headphone(wm5100);
2078 		else
2079 			wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
2080 
2081 		return;
2082 	}
2083 
2084 	/* Don't distinguish between buttons, just report any low
2085 	 * impedence as BTN_0.
2086 	 */
2087 	if (val & 0x3fc) {
2088 		if (wm5100->jack_mic) {
2089 			dev_dbg(wm5100->dev, "Mic button detected\n");
2090 			snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2091 					    SND_JACK_BTN_0);
2092 		} else if (wm5100->jack_detecting) {
2093 			wm5100_report_headphone(wm5100);
2094 		}
2095 	}
2096 }
2097 
2098 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2099 {
2100 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2101 
2102 	if (jack) {
2103 		wm5100->jack = jack;
2104 		wm5100->jack_detecting = true;
2105 		wm5100->jack_flips = 0;
2106 
2107 		wm5100_set_detect_mode(wm5100, 0);
2108 
2109 		/* Slowest detection rate, gives debounce for initial
2110 		 * detection */
2111 		snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2112 				    WM5100_ACCDET_BIAS_STARTTIME_MASK |
2113 				    WM5100_ACCDET_RATE_MASK,
2114 				    (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2115 				    WM5100_ACCDET_RATE_MASK);
2116 
2117 		/* We need the charge pump to power MICBIAS */
2118 		snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2119 		snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2120 		snd_soc_dapm_sync(&codec->dapm);
2121 
2122 		/* We start off just enabling microphone detection - even a
2123 		 * plain headphone will trigger detection.
2124 		 */
2125 		snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2126 				    WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2127 
2128 		snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2129 				    WM5100_IM_ACCDET_EINT, 0);
2130 	} else {
2131 		snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2132 				    WM5100_IM_HPDET_EINT |
2133 				    WM5100_IM_ACCDET_EINT,
2134 				    WM5100_IM_HPDET_EINT |
2135 				    WM5100_IM_ACCDET_EINT);
2136 		snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2137 				    WM5100_ACCDET_ENA, 0);
2138 		wm5100->jack = NULL;
2139 	}
2140 
2141 	return 0;
2142 }
2143 
2144 static irqreturn_t wm5100_irq(int irq, void *data)
2145 {
2146 	struct wm5100_priv *wm5100 = data;
2147 	irqreturn_t status = IRQ_NONE;
2148 	unsigned int irq_val, mask_val;
2149 	int ret;
2150 
2151 	ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2152 	if (ret < 0) {
2153 		dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2154 			ret);
2155 		irq_val = 0;
2156 	}
2157 
2158 	ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2159 			  &mask_val);
2160 	if (ret < 0) {
2161 		dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2162 			ret);
2163 		mask_val = 0xffff;
2164 	}
2165 
2166 	irq_val &= ~mask_val;
2167 
2168 	regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
2169 
2170 	if (irq_val)
2171 		status = IRQ_HANDLED;
2172 
2173 	wm5100_log_status3(wm5100, irq_val);
2174 
2175 	if (irq_val & WM5100_FLL1_LOCK_EINT) {
2176 		dev_dbg(wm5100->dev, "FLL1 locked\n");
2177 		complete(&wm5100->fll[0].lock);
2178 	}
2179 	if (irq_val & WM5100_FLL2_LOCK_EINT) {
2180 		dev_dbg(wm5100->dev, "FLL2 locked\n");
2181 		complete(&wm5100->fll[1].lock);
2182 	}
2183 
2184 	if (irq_val & WM5100_ACCDET_EINT)
2185 		wm5100_micd_irq(wm5100);
2186 
2187 	ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2188 	if (ret < 0) {
2189 		dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2190 			ret);
2191 		irq_val = 0;
2192 	}
2193 
2194 	ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2195 			  &mask_val);
2196 	if (ret < 0) {
2197 		dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2198 			ret);
2199 		mask_val = 0xffff;
2200 	}
2201 
2202 	irq_val &= ~mask_val;
2203 
2204 	if (irq_val)
2205 		status = IRQ_HANDLED;
2206 
2207 	regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
2208 
2209 	wm5100_log_status4(wm5100, irq_val);
2210 
2211 	return status;
2212 }
2213 
2214 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2215 {
2216 	irqreturn_t ret = IRQ_NONE;
2217 	irqreturn_t val;
2218 
2219 	do {
2220 		val = wm5100_irq(irq, data);
2221 		if (val != IRQ_NONE)
2222 			ret = val;
2223 	} while (val != IRQ_NONE);
2224 
2225 	return ret;
2226 }
2227 
2228 #ifdef CONFIG_GPIOLIB
2229 static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2230 {
2231 	return container_of(chip, struct wm5100_priv, gpio_chip);
2232 }
2233 
2234 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2235 {
2236 	struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2237 
2238 	regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2239 			   WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2240 }
2241 
2242 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2243 				     unsigned offset, int value)
2244 {
2245 	struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2246 	int val, ret;
2247 
2248 	val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2249 
2250 	ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2251 				 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2252 				 WM5100_GP1_LVL, val);
2253 	if (ret < 0)
2254 		return ret;
2255 	else
2256 		return 0;
2257 }
2258 
2259 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2260 {
2261 	struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2262 	unsigned int reg;
2263 	int ret;
2264 
2265 	ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
2266 	if (ret < 0)
2267 		return ret;
2268 
2269 	return (reg & WM5100_GP1_LVL) != 0;
2270 }
2271 
2272 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2273 {
2274 	struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2275 
2276 	return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2277 				  WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2278 				  (1 << WM5100_GP1_FN_SHIFT) |
2279 				  (1 << WM5100_GP1_DIR_SHIFT));
2280 }
2281 
2282 static struct gpio_chip wm5100_template_chip = {
2283 	.label			= "wm5100",
2284 	.owner			= THIS_MODULE,
2285 	.direction_output	= wm5100_gpio_direction_out,
2286 	.set			= wm5100_gpio_set,
2287 	.direction_input	= wm5100_gpio_direction_in,
2288 	.get			= wm5100_gpio_get,
2289 	.can_sleep		= 1,
2290 };
2291 
2292 static void wm5100_init_gpio(struct i2c_client *i2c)
2293 {
2294 	struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2295 	int ret;
2296 
2297 	wm5100->gpio_chip = wm5100_template_chip;
2298 	wm5100->gpio_chip.ngpio = 6;
2299 	wm5100->gpio_chip.dev = &i2c->dev;
2300 
2301 	if (wm5100->pdata.gpio_base)
2302 		wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2303 	else
2304 		wm5100->gpio_chip.base = -1;
2305 
2306 	ret = gpiochip_add(&wm5100->gpio_chip);
2307 	if (ret != 0)
2308 		dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
2309 }
2310 
2311 static void wm5100_free_gpio(struct i2c_client *i2c)
2312 {
2313 	struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2314 	int ret;
2315 
2316 	ret = gpiochip_remove(&wm5100->gpio_chip);
2317 	if (ret != 0)
2318 		dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
2319 }
2320 #else
2321 static void wm5100_init_gpio(struct i2c_client *i2c)
2322 {
2323 }
2324 
2325 static void wm5100_free_gpio(struct i2c_client *i2c)
2326 {
2327 }
2328 #endif
2329 
2330 static int wm5100_probe(struct snd_soc_codec *codec)
2331 {
2332 	struct i2c_client *i2c = to_i2c_client(codec->dev);
2333 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2334 	int ret, i;
2335 
2336 	wm5100->codec = codec;
2337 	codec->control_data = wm5100->regmap;
2338 
2339 	ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2340 	if (ret != 0) {
2341 		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2342 		return ret;
2343 	}
2344 
2345 	for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2346 		snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2347 				    WM5100_OUT_VU);
2348 
2349 	/* Don't debounce interrupts to support use of SYSCLK only */
2350 	snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2351 	snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2352 
2353 	/* TODO: check if we're symmetric */
2354 
2355 	if (i2c->irq)
2356 		snd_soc_dapm_new_controls(&codec->dapm,
2357 					  wm5100_dapm_widgets_noirq,
2358 					  ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2359 
2360 	if (wm5100->pdata.hp_pol) {
2361 		ret = gpio_request_one(wm5100->pdata.hp_pol,
2362 				       GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2363 		if (ret < 0) {
2364 			dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2365 				wm5100->pdata.hp_pol, ret);
2366 			goto err_gpio;
2367 		}
2368 	}
2369 
2370 	return 0;
2371 
2372 err_gpio:
2373 
2374 	return ret;
2375 }
2376 
2377 static int wm5100_remove(struct snd_soc_codec *codec)
2378 {
2379 	struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2380 
2381 	if (wm5100->pdata.hp_pol) {
2382 		gpio_free(wm5100->pdata.hp_pol);
2383 	}
2384 
2385 	return 0;
2386 }
2387 
2388 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2389 	.probe =	wm5100_probe,
2390 	.remove =	wm5100_remove,
2391 
2392 	.set_sysclk = wm5100_set_sysclk,
2393 	.set_pll = wm5100_set_fll,
2394 	.idle_bias_off = 1,
2395 
2396 	.seq_notifier = wm5100_seq_notifier,
2397 	.controls = wm5100_snd_controls,
2398 	.num_controls = ARRAY_SIZE(wm5100_snd_controls),
2399 	.dapm_widgets = wm5100_dapm_widgets,
2400 	.num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2401 	.dapm_routes = wm5100_dapm_routes,
2402 	.num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2403 };
2404 
2405 static const struct regmap_config wm5100_regmap = {
2406 	.reg_bits = 16,
2407 	.val_bits = 16,
2408 
2409 	.max_register = WM5100_MAX_REGISTER,
2410 	.reg_defaults = wm5100_reg_defaults,
2411 	.num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2412 	.volatile_reg = wm5100_volatile_register,
2413 	.readable_reg = wm5100_readable_register,
2414 	.cache_type = REGCACHE_RBTREE,
2415 };
2416 
2417 static const unsigned int wm5100_mic_ctrl_reg[] = {
2418 	WM5100_IN1L_CONTROL,
2419 	WM5100_IN2L_CONTROL,
2420 	WM5100_IN3L_CONTROL,
2421 	WM5100_IN4L_CONTROL,
2422 };
2423 
2424 static int wm5100_i2c_probe(struct i2c_client *i2c,
2425 			    const struct i2c_device_id *id)
2426 {
2427 	struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2428 	struct wm5100_priv *wm5100;
2429 	unsigned int reg;
2430 	int ret, i, irq_flags;
2431 
2432 	wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2433 			      GFP_KERNEL);
2434 	if (wm5100 == NULL)
2435 		return -ENOMEM;
2436 
2437 	wm5100->dev = &i2c->dev;
2438 
2439 	wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
2440 	if (IS_ERR(wm5100->regmap)) {
2441 		ret = PTR_ERR(wm5100->regmap);
2442 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2443 			ret);
2444 		goto err;
2445 	}
2446 
2447 	for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2448 		init_completion(&wm5100->fll[i].lock);
2449 
2450 	if (pdata)
2451 		wm5100->pdata = *pdata;
2452 
2453 	i2c_set_clientdata(i2c, wm5100);
2454 
2455 	for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2456 		wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2457 
2458 	ret = devm_regulator_bulk_get(&i2c->dev,
2459 				      ARRAY_SIZE(wm5100->core_supplies),
2460 				      wm5100->core_supplies);
2461 	if (ret != 0) {
2462 		dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2463 			ret);
2464 		goto err;
2465 	}
2466 
2467 	ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2468 				    wm5100->core_supplies);
2469 	if (ret != 0) {
2470 		dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2471 			ret);
2472 		goto err;
2473 	}
2474 
2475 	if (wm5100->pdata.ldo_ena) {
2476 		ret = gpio_request_one(wm5100->pdata.ldo_ena,
2477 				       GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2478 		if (ret < 0) {
2479 			dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2480 				wm5100->pdata.ldo_ena, ret);
2481 			goto err_enable;
2482 		}
2483 		msleep(2);
2484 	}
2485 
2486 	if (wm5100->pdata.reset) {
2487 		ret = gpio_request_one(wm5100->pdata.reset,
2488 				       GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2489 		if (ret < 0) {
2490 			dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2491 				wm5100->pdata.reset, ret);
2492 			goto err_ldo;
2493 		}
2494 	}
2495 
2496 	ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2497 	if (ret < 0) {
2498 		dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2499 		goto err_reset;
2500 	}
2501 	switch (reg) {
2502 	case 0x8997:
2503 	case 0x5100:
2504 		break;
2505 
2506 	default:
2507 		dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2508 		ret = -EINVAL;
2509 		goto err_reset;
2510 	}
2511 
2512 	ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2513 	if (ret < 0) {
2514 		dev_err(&i2c->dev, "Failed to read revision register\n");
2515 		goto err_reset;
2516 	}
2517 	wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2518 
2519 	dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2520 
2521 	ret = wm5100_reset(wm5100);
2522 	if (ret < 0) {
2523 		dev_err(&i2c->dev, "Failed to issue reset\n");
2524 		goto err_reset;
2525 	}
2526 
2527 	switch (wm5100->rev) {
2528 	case 0:
2529 		ret = regmap_register_patch(wm5100->regmap,
2530 					    wm5100_reva_patches,
2531 					    ARRAY_SIZE(wm5100_reva_patches));
2532 		if (ret != 0) {
2533 			dev_err(&i2c->dev, "Failed to register patches: %d\n",
2534 				ret);
2535 			goto err_reset;
2536 		}
2537 		break;
2538 	default:
2539 		break;
2540 	}
2541 
2542 
2543 	wm5100_init_gpio(i2c);
2544 
2545 	for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2546 		if (!wm5100->pdata.gpio_defaults[i])
2547 			continue;
2548 
2549 		regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2550 			     wm5100->pdata.gpio_defaults[i]);
2551 	}
2552 
2553 	for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2554 		regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
2555 				   WM5100_IN1_MODE_MASK |
2556 				   WM5100_IN1_DMIC_SUP_MASK,
2557 				   (wm5100->pdata.in_mode[i] <<
2558 				    WM5100_IN1_MODE_SHIFT) |
2559 				   (wm5100->pdata.dmic_sup[i] <<
2560 				    WM5100_IN1_DMIC_SUP_SHIFT));
2561 	}
2562 
2563 	if (i2c->irq) {
2564 		if (wm5100->pdata.irq_flags)
2565 			irq_flags = wm5100->pdata.irq_flags;
2566 		else
2567 			irq_flags = IRQF_TRIGGER_LOW;
2568 
2569 		irq_flags |= IRQF_ONESHOT;
2570 
2571 		if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2572 			ret = request_threaded_irq(i2c->irq, NULL,
2573 						   wm5100_edge_irq, irq_flags,
2574 						   "wm5100", wm5100);
2575 		else
2576 			ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2577 						   irq_flags, "wm5100",
2578 						   wm5100);
2579 
2580 		if (ret != 0) {
2581 			dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2582 				i2c->irq, ret);
2583 		} else {
2584 			/* Enable default interrupts */
2585 			regmap_update_bits(wm5100->regmap,
2586 					   WM5100_INTERRUPT_STATUS_3_MASK,
2587 					   WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2588 					   WM5100_IM_SPK_SHUTDOWN_EINT |
2589 					   WM5100_IM_ASRC2_LOCK_EINT |
2590 					   WM5100_IM_ASRC1_LOCK_EINT |
2591 					   WM5100_IM_FLL2_LOCK_EINT |
2592 					   WM5100_IM_FLL1_LOCK_EINT |
2593 					   WM5100_CLKGEN_ERR_EINT |
2594 					   WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2595 
2596 			regmap_update_bits(wm5100->regmap,
2597 					   WM5100_INTERRUPT_STATUS_4_MASK,
2598 					   WM5100_AIF3_ERR_EINT |
2599 					   WM5100_AIF2_ERR_EINT |
2600 					   WM5100_AIF1_ERR_EINT |
2601 					   WM5100_CTRLIF_ERR_EINT |
2602 					   WM5100_ISRC2_UNDERCLOCKED_EINT |
2603 					   WM5100_ISRC1_UNDERCLOCKED_EINT |
2604 					   WM5100_FX_UNDERCLOCKED_EINT |
2605 					   WM5100_AIF3_UNDERCLOCKED_EINT |
2606 					   WM5100_AIF2_UNDERCLOCKED_EINT |
2607 					   WM5100_AIF1_UNDERCLOCKED_EINT |
2608 					   WM5100_ASRC_UNDERCLOCKED_EINT |
2609 					   WM5100_DAC_UNDERCLOCKED_EINT |
2610 					   WM5100_ADC_UNDERCLOCKED_EINT |
2611 					   WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2612 		}
2613 	}
2614 
2615 	pm_runtime_set_active(&i2c->dev);
2616 	pm_runtime_enable(&i2c->dev);
2617 	pm_request_idle(&i2c->dev);
2618 
2619 	ret = snd_soc_register_codec(&i2c->dev,
2620 				     &soc_codec_dev_wm5100, wm5100_dai,
2621 				     ARRAY_SIZE(wm5100_dai));
2622 	if (ret < 0) {
2623 		dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2624 		goto err_reset;
2625 	}
2626 
2627 	return ret;
2628 
2629 err_reset:
2630 	if (i2c->irq)
2631 		free_irq(i2c->irq, wm5100);
2632 	wm5100_free_gpio(i2c);
2633 	if (wm5100->pdata.reset) {
2634 		gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2635 		gpio_free(wm5100->pdata.reset);
2636 	}
2637 err_ldo:
2638 	if (wm5100->pdata.ldo_ena) {
2639 		gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2640 		gpio_free(wm5100->pdata.ldo_ena);
2641 	}
2642 err_enable:
2643 	regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2644 			       wm5100->core_supplies);
2645 err:
2646 	return ret;
2647 }
2648 
2649 static int wm5100_i2c_remove(struct i2c_client *i2c)
2650 {
2651 	struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2652 
2653 	snd_soc_unregister_codec(&i2c->dev);
2654 	if (i2c->irq)
2655 		free_irq(i2c->irq, wm5100);
2656 	wm5100_free_gpio(i2c);
2657 	if (wm5100->pdata.reset) {
2658 		gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2659 		gpio_free(wm5100->pdata.reset);
2660 	}
2661 	if (wm5100->pdata.ldo_ena) {
2662 		gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2663 		gpio_free(wm5100->pdata.ldo_ena);
2664 	}
2665 
2666 	return 0;
2667 }
2668 
2669 #ifdef CONFIG_PM_RUNTIME
2670 static int wm5100_runtime_suspend(struct device *dev)
2671 {
2672 	struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2673 
2674 	regcache_cache_only(wm5100->regmap, true);
2675 	regcache_mark_dirty(wm5100->regmap);
2676 	if (wm5100->pdata.ldo_ena)
2677 		gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2678 	regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2679 			       wm5100->core_supplies);
2680 
2681 	return 0;
2682 }
2683 
2684 static int wm5100_runtime_resume(struct device *dev)
2685 {
2686 	struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2687 	int ret;
2688 
2689 	ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2690 				    wm5100->core_supplies);
2691 	if (ret != 0) {
2692 		dev_err(dev, "Failed to enable supplies: %d\n",
2693 			ret);
2694 		return ret;
2695 	}
2696 
2697 	if (wm5100->pdata.ldo_ena) {
2698 		gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2699 		msleep(2);
2700 	}
2701 
2702 	regcache_cache_only(wm5100->regmap, false);
2703 	regcache_sync(wm5100->regmap);
2704 
2705 	return 0;
2706 }
2707 #endif
2708 
2709 static struct dev_pm_ops wm5100_pm = {
2710 	SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2711 			   NULL)
2712 };
2713 
2714 static const struct i2c_device_id wm5100_i2c_id[] = {
2715 	{ "wm5100", 0 },
2716 	{ }
2717 };
2718 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2719 
2720 static struct i2c_driver wm5100_i2c_driver = {
2721 	.driver = {
2722 		.name = "wm5100",
2723 		.owner = THIS_MODULE,
2724 		.pm = &wm5100_pm,
2725 	},
2726 	.probe =    wm5100_i2c_probe,
2727 	.remove =   wm5100_i2c_remove,
2728 	.id_table = wm5100_i2c_id,
2729 };
2730 
2731 module_i2c_driver(wm5100_i2c_driver);
2732 
2733 MODULE_DESCRIPTION("ASoC WM5100 driver");
2734 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2735 MODULE_LICENSE("GPL");
2736