1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * wm2200.h - WM2200 audio codec interface 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 */ 8 9 #ifndef _WM2200_H 10 #define _WM2200_H 11 12 #define WM2200_CLK_SYSCLK 1 13 14 #define WM2200_CLKSRC_MCLK1 0 15 #define WM2200_CLKSRC_MCLK2 1 16 #define WM2200_CLKSRC_FLL 4 17 #define WM2200_CLKSRC_BCLK1 8 18 19 #define WM2200_FLL_SRC_MCLK1 0 20 #define WM2200_FLL_SRC_MCLK2 1 21 #define WM2200_FLL_SRC_BCLK 2 22 23 /* 24 * Register values. 25 */ 26 #define WM2200_SOFTWARE_RESET 0x00 27 #define WM2200_DEVICE_REVISION 0x01 28 #define WM2200_TONE_GENERATOR_1 0x0B 29 #define WM2200_CLOCKING_3 0x102 30 #define WM2200_CLOCKING_4 0x103 31 #define WM2200_FLL_CONTROL_1 0x111 32 #define WM2200_FLL_CONTROL_2 0x112 33 #define WM2200_FLL_CONTROL_3 0x113 34 #define WM2200_FLL_CONTROL_4 0x114 35 #define WM2200_FLL_CONTROL_6 0x116 36 #define WM2200_FLL_CONTROL_7 0x117 37 #define WM2200_FLL_EFS_1 0x119 38 #define WM2200_FLL_EFS_2 0x11A 39 #define WM2200_MIC_CHARGE_PUMP_1 0x200 40 #define WM2200_MIC_CHARGE_PUMP_2 0x201 41 #define WM2200_DM_CHARGE_PUMP_1 0x202 42 #define WM2200_MIC_BIAS_CTRL_1 0x20C 43 #define WM2200_MIC_BIAS_CTRL_2 0x20D 44 #define WM2200_EAR_PIECE_CTRL_1 0x20F 45 #define WM2200_EAR_PIECE_CTRL_2 0x210 46 #define WM2200_INPUT_ENABLES 0x301 47 #define WM2200_IN1L_CONTROL 0x302 48 #define WM2200_IN1R_CONTROL 0x303 49 #define WM2200_IN2L_CONTROL 0x304 50 #define WM2200_IN2R_CONTROL 0x305 51 #define WM2200_IN3L_CONTROL 0x306 52 #define WM2200_IN3R_CONTROL 0x307 53 #define WM2200_RXANC_SRC 0x30A 54 #define WM2200_INPUT_VOLUME_RAMP 0x30B 55 #define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C 56 #define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D 57 #define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E 58 #define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F 59 #define WM2200_ADC_DIGITAL_VOLUME_3L 0x310 60 #define WM2200_ADC_DIGITAL_VOLUME_3R 0x311 61 #define WM2200_OUTPUT_ENABLES 0x400 62 #define WM2200_DAC_VOLUME_LIMIT_1L 0x401 63 #define WM2200_DAC_VOLUME_LIMIT_1R 0x402 64 #define WM2200_DAC_VOLUME_LIMIT_2L 0x403 65 #define WM2200_DAC_VOLUME_LIMIT_2R 0x404 66 #define WM2200_DAC_AEC_CONTROL_1 0x409 67 #define WM2200_OUTPUT_VOLUME_RAMP 0x40A 68 #define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B 69 #define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C 70 #define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D 71 #define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E 72 #define WM2200_PDM_1 0x417 73 #define WM2200_PDM_2 0x418 74 #define WM2200_AUDIO_IF_1_1 0x500 75 #define WM2200_AUDIO_IF_1_2 0x501 76 #define WM2200_AUDIO_IF_1_3 0x502 77 #define WM2200_AUDIO_IF_1_4 0x503 78 #define WM2200_AUDIO_IF_1_5 0x504 79 #define WM2200_AUDIO_IF_1_6 0x505 80 #define WM2200_AUDIO_IF_1_7 0x506 81 #define WM2200_AUDIO_IF_1_8 0x507 82 #define WM2200_AUDIO_IF_1_9 0x508 83 #define WM2200_AUDIO_IF_1_10 0x509 84 #define WM2200_AUDIO_IF_1_11 0x50A 85 #define WM2200_AUDIO_IF_1_12 0x50B 86 #define WM2200_AUDIO_IF_1_13 0x50C 87 #define WM2200_AUDIO_IF_1_14 0x50D 88 #define WM2200_AUDIO_IF_1_15 0x50E 89 #define WM2200_AUDIO_IF_1_16 0x50F 90 #define WM2200_AUDIO_IF_1_17 0x510 91 #define WM2200_AUDIO_IF_1_18 0x511 92 #define WM2200_AUDIO_IF_1_19 0x512 93 #define WM2200_AUDIO_IF_1_20 0x513 94 #define WM2200_AUDIO_IF_1_21 0x514 95 #define WM2200_AUDIO_IF_1_22 0x515 96 #define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600 97 #define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601 98 #define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602 99 #define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603 100 #define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604 101 #define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605 102 #define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606 103 #define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607 104 #define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608 105 #define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609 106 #define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A 107 #define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B 108 #define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C 109 #define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D 110 #define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E 111 #define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F 112 #define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610 113 #define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611 114 #define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612 115 #define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613 116 #define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614 117 #define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615 118 #define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616 119 #define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617 120 #define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618 121 #define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619 122 #define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A 123 #define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B 124 #define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C 125 #define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D 126 #define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E 127 #define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F 128 #define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620 129 #define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621 130 #define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622 131 #define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623 132 #define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624 133 #define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625 134 #define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626 135 #define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627 136 #define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628 137 #define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629 138 #define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A 139 #define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B 140 #define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C 141 #define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D 142 #define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E 143 #define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F 144 #define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630 145 #define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631 146 #define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632 147 #define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633 148 #define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634 149 #define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635 150 #define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636 151 #define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637 152 #define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638 153 #define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639 154 #define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A 155 #define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B 156 #define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C 157 #define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D 158 #define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E 159 #define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F 160 #define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640 161 #define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641 162 #define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642 163 #define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643 164 #define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644 165 #define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645 166 #define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646 167 #define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647 168 #define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648 169 #define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649 170 #define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A 171 #define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B 172 #define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C 173 #define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D 174 #define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E 175 #define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F 176 #define WM2200_EQLMIX_INPUT_1_SOURCE 0x650 177 #define WM2200_EQLMIX_INPUT_1_VOLUME 0x651 178 #define WM2200_EQLMIX_INPUT_2_SOURCE 0x652 179 #define WM2200_EQLMIX_INPUT_2_VOLUME 0x653 180 #define WM2200_EQLMIX_INPUT_3_SOURCE 0x654 181 #define WM2200_EQLMIX_INPUT_3_VOLUME 0x655 182 #define WM2200_EQLMIX_INPUT_4_SOURCE 0x656 183 #define WM2200_EQLMIX_INPUT_4_VOLUME 0x657 184 #define WM2200_EQRMIX_INPUT_1_SOURCE 0x658 185 #define WM2200_EQRMIX_INPUT_1_VOLUME 0x659 186 #define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A 187 #define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B 188 #define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C 189 #define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D 190 #define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E 191 #define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F 192 #define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660 193 #define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661 194 #define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662 195 #define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663 196 #define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664 197 #define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665 198 #define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666 199 #define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667 200 #define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668 201 #define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669 202 #define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A 203 #define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B 204 #define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C 205 #define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D 206 #define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E 207 #define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F 208 #define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670 209 #define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671 210 #define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672 211 #define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673 212 #define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674 213 #define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675 214 #define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676 215 #define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677 216 #define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678 217 #define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679 218 #define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A 219 #define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B 220 #define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C 221 #define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D 222 #define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E 223 #define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F 224 #define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680 225 #define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681 226 #define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682 227 #define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683 228 #define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684 229 #define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685 230 #define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686 231 #define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687 232 #define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688 233 #define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689 234 #define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A 235 #define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B 236 #define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C 237 #define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D 238 #define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E 239 #define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F 240 #define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690 241 #define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691 242 #define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692 243 #define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693 244 #define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694 245 #define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695 246 #define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696 247 #define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697 248 #define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698 249 #define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699 250 #define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A 251 #define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B 252 #define WM2200_GPIO_CTRL_1 0x700 253 #define WM2200_GPIO_CTRL_2 0x701 254 #define WM2200_GPIO_CTRL_3 0x702 255 #define WM2200_GPIO_CTRL_4 0x703 256 #define WM2200_ADPS1_IRQ0 0x707 257 #define WM2200_ADPS1_IRQ1 0x708 258 #define WM2200_MISC_PAD_CTRL_1 0x709 259 #define WM2200_INTERRUPT_STATUS_1 0x800 260 #define WM2200_INTERRUPT_STATUS_1_MASK 0x801 261 #define WM2200_INTERRUPT_STATUS_2 0x802 262 #define WM2200_INTERRUPT_RAW_STATUS_2 0x803 263 #define WM2200_INTERRUPT_STATUS_2_MASK 0x804 264 #define WM2200_INTERRUPT_CONTROL 0x808 265 #define WM2200_EQL_1 0x900 266 #define WM2200_EQL_2 0x901 267 #define WM2200_EQL_3 0x902 268 #define WM2200_EQL_4 0x903 269 #define WM2200_EQL_5 0x904 270 #define WM2200_EQL_6 0x905 271 #define WM2200_EQL_7 0x906 272 #define WM2200_EQL_8 0x907 273 #define WM2200_EQL_9 0x908 274 #define WM2200_EQL_10 0x909 275 #define WM2200_EQL_11 0x90A 276 #define WM2200_EQL_12 0x90B 277 #define WM2200_EQL_13 0x90C 278 #define WM2200_EQL_14 0x90D 279 #define WM2200_EQL_15 0x90E 280 #define WM2200_EQL_16 0x90F 281 #define WM2200_EQL_17 0x910 282 #define WM2200_EQL_18 0x911 283 #define WM2200_EQL_19 0x912 284 #define WM2200_EQL_20 0x913 285 #define WM2200_EQR_1 0x916 286 #define WM2200_EQR_2 0x917 287 #define WM2200_EQR_3 0x918 288 #define WM2200_EQR_4 0x919 289 #define WM2200_EQR_5 0x91A 290 #define WM2200_EQR_6 0x91B 291 #define WM2200_EQR_7 0x91C 292 #define WM2200_EQR_8 0x91D 293 #define WM2200_EQR_9 0x91E 294 #define WM2200_EQR_10 0x91F 295 #define WM2200_EQR_11 0x920 296 #define WM2200_EQR_12 0x921 297 #define WM2200_EQR_13 0x922 298 #define WM2200_EQR_14 0x923 299 #define WM2200_EQR_15 0x924 300 #define WM2200_EQR_16 0x925 301 #define WM2200_EQR_17 0x926 302 #define WM2200_EQR_18 0x927 303 #define WM2200_EQR_19 0x928 304 #define WM2200_EQR_20 0x929 305 #define WM2200_HPLPF1_1 0x93E 306 #define WM2200_HPLPF1_2 0x93F 307 #define WM2200_HPLPF2_1 0x942 308 #define WM2200_HPLPF2_2 0x943 309 #define WM2200_DSP1_CONTROL_1 0xA00 310 #define WM2200_DSP1_CONTROL_2 0xA02 311 #define WM2200_DSP1_CONTROL_3 0xA03 312 #define WM2200_DSP1_CONTROL_4 0xA04 313 #define WM2200_DSP1_CONTROL_5 0xA06 314 #define WM2200_DSP1_CONTROL_6 0xA07 315 #define WM2200_DSP1_CONTROL_7 0xA08 316 #define WM2200_DSP1_CONTROL_8 0xA09 317 #define WM2200_DSP1_CONTROL_9 0xA0A 318 #define WM2200_DSP1_CONTROL_10 0xA0B 319 #define WM2200_DSP1_CONTROL_11 0xA0C 320 #define WM2200_DSP1_CONTROL_12 0xA0D 321 #define WM2200_DSP1_CONTROL_13 0xA0F 322 #define WM2200_DSP1_CONTROL_14 0xA10 323 #define WM2200_DSP1_CONTROL_15 0xA11 324 #define WM2200_DSP1_CONTROL_16 0xA12 325 #define WM2200_DSP1_CONTROL_17 0xA13 326 #define WM2200_DSP1_CONTROL_18 0xA14 327 #define WM2200_DSP1_CONTROL_19 0xA16 328 #define WM2200_DSP1_CONTROL_20 0xA17 329 #define WM2200_DSP1_CONTROL_21 0xA18 330 #define WM2200_DSP1_CONTROL_22 0xA1A 331 #define WM2200_DSP1_CONTROL_23 0xA1B 332 #define WM2200_DSP1_CONTROL_24 0xA1C 333 #define WM2200_DSP1_CONTROL_25 0xA1E 334 #define WM2200_DSP1_CONTROL_26 0xA20 335 #define WM2200_DSP1_CONTROL_27 0xA21 336 #define WM2200_DSP1_CONTROL_28 0xA22 337 #define WM2200_DSP1_CONTROL_29 0xA23 338 #define WM2200_DSP1_CONTROL_30 0xA24 339 #define WM2200_DSP1_CONTROL_31 0xA26 340 #define WM2200_DSP2_CONTROL_1 0xB00 341 #define WM2200_DSP2_CONTROL_2 0xB02 342 #define WM2200_DSP2_CONTROL_3 0xB03 343 #define WM2200_DSP2_CONTROL_4 0xB04 344 #define WM2200_DSP2_CONTROL_5 0xB06 345 #define WM2200_DSP2_CONTROL_6 0xB07 346 #define WM2200_DSP2_CONTROL_7 0xB08 347 #define WM2200_DSP2_CONTROL_8 0xB09 348 #define WM2200_DSP2_CONTROL_9 0xB0A 349 #define WM2200_DSP2_CONTROL_10 0xB0B 350 #define WM2200_DSP2_CONTROL_11 0xB0C 351 #define WM2200_DSP2_CONTROL_12 0xB0D 352 #define WM2200_DSP2_CONTROL_13 0xB0F 353 #define WM2200_DSP2_CONTROL_14 0xB10 354 #define WM2200_DSP2_CONTROL_15 0xB11 355 #define WM2200_DSP2_CONTROL_16 0xB12 356 #define WM2200_DSP2_CONTROL_17 0xB13 357 #define WM2200_DSP2_CONTROL_18 0xB14 358 #define WM2200_DSP2_CONTROL_19 0xB16 359 #define WM2200_DSP2_CONTROL_20 0xB17 360 #define WM2200_DSP2_CONTROL_21 0xB18 361 #define WM2200_DSP2_CONTROL_22 0xB1A 362 #define WM2200_DSP2_CONTROL_23 0xB1B 363 #define WM2200_DSP2_CONTROL_24 0xB1C 364 #define WM2200_DSP2_CONTROL_25 0xB1E 365 #define WM2200_DSP2_CONTROL_26 0xB20 366 #define WM2200_DSP2_CONTROL_27 0xB21 367 #define WM2200_DSP2_CONTROL_28 0xB22 368 #define WM2200_DSP2_CONTROL_29 0xB23 369 #define WM2200_DSP2_CONTROL_30 0xB24 370 #define WM2200_DSP2_CONTROL_31 0xB26 371 #define WM2200_ANC_CTRL1 0xD00 372 #define WM2200_ANC_CTRL2 0xD01 373 #define WM2200_ANC_CTRL3 0xD02 374 #define WM2200_ANC_CTRL7 0xD08 375 #define WM2200_ANC_CTRL8 0xD09 376 #define WM2200_ANC_CTRL9 0xD0A 377 #define WM2200_ANC_CTRL10 0xD0B 378 #define WM2200_ANC_CTRL11 0xD0C 379 #define WM2200_ANC_CTRL12 0xD0D 380 #define WM2200_ANC_CTRL13 0xD0E 381 #define WM2200_ANC_CTRL14 0xD0F 382 #define WM2200_ANC_CTRL15 0xD10 383 #define WM2200_ANC_CTRL16 0xD11 384 #define WM2200_ANC_CTRL17 0xD12 385 #define WM2200_ANC_CTRL18 0xD15 386 #define WM2200_ANC_CTRL19 0xD16 387 #define WM2200_ANC_CTRL20 0xD17 388 #define WM2200_ANC_CTRL21 0xD18 389 #define WM2200_ANC_CTRL22 0xD19 390 #define WM2200_ANC_CTRL23 0xD1A 391 #define WM2200_ANC_CTRL24 0xD1B 392 #define WM2200_ANC_CTRL25 0xD1C 393 #define WM2200_ANC_CTRL26 0xD1D 394 #define WM2200_ANC_CTRL27 0xD1E 395 #define WM2200_ANC_CTRL28 0xD1F 396 #define WM2200_ANC_CTRL29 0xD20 397 #define WM2200_ANC_CTRL30 0xD21 398 #define WM2200_ANC_CTRL31 0xD23 399 #define WM2200_ANC_CTRL32 0xD24 400 #define WM2200_ANC_CTRL33 0xD25 401 #define WM2200_ANC_CTRL34 0xD27 402 #define WM2200_ANC_CTRL35 0xD28 403 #define WM2200_ANC_CTRL36 0xD29 404 #define WM2200_ANC_CTRL37 0xD2A 405 #define WM2200_ANC_CTRL38 0xD2B 406 #define WM2200_ANC_CTRL39 0xD2C 407 #define WM2200_ANC_CTRL40 0xD2D 408 #define WM2200_ANC_CTRL41 0xD2E 409 #define WM2200_ANC_CTRL42 0xD2F 410 #define WM2200_ANC_CTRL43 0xD30 411 #define WM2200_ANC_CTRL44 0xD31 412 #define WM2200_ANC_CTRL45 0xD32 413 #define WM2200_ANC_CTRL46 0xD33 414 #define WM2200_ANC_CTRL47 0xD34 415 #define WM2200_ANC_CTRL48 0xD35 416 #define WM2200_ANC_CTRL49 0xD36 417 #define WM2200_ANC_CTRL50 0xD37 418 #define WM2200_ANC_CTRL51 0xD38 419 #define WM2200_ANC_CTRL52 0xD39 420 #define WM2200_ANC_CTRL53 0xD3A 421 #define WM2200_ANC_CTRL54 0xD3B 422 #define WM2200_ANC_CTRL55 0xD3C 423 #define WM2200_ANC_CTRL56 0xD3D 424 #define WM2200_ANC_CTRL57 0xD3E 425 #define WM2200_ANC_CTRL58 0xD3F 426 #define WM2200_ANC_CTRL59 0xD40 427 #define WM2200_ANC_CTRL60 0xD41 428 #define WM2200_ANC_CTRL61 0xD42 429 #define WM2200_ANC_CTRL62 0xD43 430 #define WM2200_ANC_CTRL63 0xD44 431 #define WM2200_ANC_CTRL64 0xD45 432 #define WM2200_ANC_CTRL65 0xD46 433 #define WM2200_ANC_CTRL66 0xD47 434 #define WM2200_ANC_CTRL67 0xD48 435 #define WM2200_ANC_CTRL68 0xD49 436 #define WM2200_ANC_CTRL69 0xD4A 437 #define WM2200_ANC_CTRL70 0xD4B 438 #define WM2200_ANC_CTRL71 0xD4C 439 #define WM2200_ANC_CTRL72 0xD4D 440 #define WM2200_ANC_CTRL73 0xD4E 441 #define WM2200_ANC_CTRL74 0xD4F 442 #define WM2200_ANC_CTRL75 0xD50 443 #define WM2200_ANC_CTRL76 0xD51 444 #define WM2200_ANC_CTRL77 0xD52 445 #define WM2200_ANC_CTRL78 0xD53 446 #define WM2200_ANC_CTRL79 0xD54 447 #define WM2200_ANC_CTRL80 0xD55 448 #define WM2200_ANC_CTRL81 0xD56 449 #define WM2200_ANC_CTRL82 0xD57 450 #define WM2200_ANC_CTRL83 0xD58 451 #define WM2200_ANC_CTRL84 0xD5B 452 #define WM2200_ANC_CTRL85 0xD5C 453 #define WM2200_ANC_CTRL86 0xD5F 454 #define WM2200_ANC_CTRL87 0xD60 455 #define WM2200_ANC_CTRL88 0xD61 456 #define WM2200_ANC_CTRL89 0xD62 457 #define WM2200_ANC_CTRL90 0xD63 458 #define WM2200_ANC_CTRL91 0xD64 459 #define WM2200_ANC_CTRL92 0xD65 460 #define WM2200_ANC_CTRL93 0xD66 461 #define WM2200_ANC_CTRL94 0xD67 462 #define WM2200_ANC_CTRL95 0xD68 463 #define WM2200_ANC_CTRL96 0xD69 464 #define WM2200_DSP1_DM_0 0x3000 465 #define WM2200_DSP1_DM_1 0x3001 466 #define WM2200_DSP1_DM_2 0x3002 467 #define WM2200_DSP1_DM_3 0x3003 468 #define WM2200_DSP1_DM_2044 0x37FC 469 #define WM2200_DSP1_DM_2045 0x37FD 470 #define WM2200_DSP1_DM_2046 0x37FE 471 #define WM2200_DSP1_DM_2047 0x37FF 472 #define WM2200_DSP1_PM_0 0x3800 473 #define WM2200_DSP1_PM_1 0x3801 474 #define WM2200_DSP1_PM_2 0x3802 475 #define WM2200_DSP1_PM_3 0x3803 476 #define WM2200_DSP1_PM_4 0x3804 477 #define WM2200_DSP1_PM_5 0x3805 478 #define WM2200_DSP1_PM_762 0x3AFA 479 #define WM2200_DSP1_PM_763 0x3AFB 480 #define WM2200_DSP1_PM_764 0x3AFC 481 #define WM2200_DSP1_PM_765 0x3AFD 482 #define WM2200_DSP1_PM_766 0x3AFE 483 #define WM2200_DSP1_PM_767 0x3AFF 484 #define WM2200_DSP1_ZM_0 0x3C00 485 #define WM2200_DSP1_ZM_1 0x3C01 486 #define WM2200_DSP1_ZM_2 0x3C02 487 #define WM2200_DSP1_ZM_3 0x3C03 488 #define WM2200_DSP1_ZM_1020 0x3FFC 489 #define WM2200_DSP1_ZM_1021 0x3FFD 490 #define WM2200_DSP1_ZM_1022 0x3FFE 491 #define WM2200_DSP1_ZM_1023 0x3FFF 492 #define WM2200_DSP2_DM_0 0x4000 493 #define WM2200_DSP2_DM_1 0x4001 494 #define WM2200_DSP2_DM_2 0x4002 495 #define WM2200_DSP2_DM_3 0x4003 496 #define WM2200_DSP2_DM_2044 0x47FC 497 #define WM2200_DSP2_DM_2045 0x47FD 498 #define WM2200_DSP2_DM_2046 0x47FE 499 #define WM2200_DSP2_DM_2047 0x47FF 500 #define WM2200_DSP2_PM_0 0x4800 501 #define WM2200_DSP2_PM_1 0x4801 502 #define WM2200_DSP2_PM_2 0x4802 503 #define WM2200_DSP2_PM_3 0x4803 504 #define WM2200_DSP2_PM_4 0x4804 505 #define WM2200_DSP2_PM_5 0x4805 506 #define WM2200_DSP2_PM_762 0x4AFA 507 #define WM2200_DSP2_PM_763 0x4AFB 508 #define WM2200_DSP2_PM_764 0x4AFC 509 #define WM2200_DSP2_PM_765 0x4AFD 510 #define WM2200_DSP2_PM_766 0x4AFE 511 #define WM2200_DSP2_PM_767 0x4AFF 512 #define WM2200_DSP2_ZM_0 0x4C00 513 #define WM2200_DSP2_ZM_1 0x4C01 514 #define WM2200_DSP2_ZM_2 0x4C02 515 #define WM2200_DSP2_ZM_3 0x4C03 516 #define WM2200_DSP2_ZM_1020 0x4FFC 517 #define WM2200_DSP2_ZM_1021 0x4FFD 518 #define WM2200_DSP2_ZM_1022 0x4FFE 519 #define WM2200_DSP2_ZM_1023 0x4FFF 520 521 #define WM2200_REGISTER_COUNT 494 522 #define WM2200_MAX_REGISTER 0x4FFF 523 524 /* 525 * Field Definitions. 526 */ 527 528 /* 529 * R0 (0x00) - software reset 530 */ 531 #define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */ 532 #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */ 533 #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */ 534 535 /* 536 * R1 (0x01) - Device Revision 537 */ 538 #define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 539 #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 540 #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 541 542 /* 543 * R11 (0x0B) - Tone Generator 1 544 */ 545 #define WM2200_TONE_ENA 0x0001 /* TONE_ENA */ 546 #define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */ 547 #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */ 548 #define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */ 549 550 /* 551 * R258 (0x102) - Clocking 3 552 */ 553 #define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 554 #define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 555 #define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 556 #define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 557 #define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 558 #define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 559 #define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 560 #define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 561 #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 562 #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 563 564 /* 565 * R259 (0x103) - Clocking 4 566 */ 567 #define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 568 #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 569 #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 570 571 /* 572 * R273 (0x111) - FLL Control 1 573 */ 574 #define WM2200_FLL_ENA 0x0001 /* FLL_ENA */ 575 #define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 576 #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */ 577 #define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */ 578 579 /* 580 * R274 (0x112) - FLL Control 2 581 */ 582 #define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 583 #define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 584 #define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 585 #define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 586 #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 587 #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 588 589 /* 590 * R275 (0x113) - FLL Control 3 591 */ 592 #define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */ 593 #define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */ 594 #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */ 595 #define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ 596 597 /* 598 * R276 (0x114) - FLL Control 4 599 */ 600 #define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ 601 #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ 602 #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ 603 604 /* 605 * R278 (0x116) - FLL Control 6 606 */ 607 #define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */ 608 #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ 609 #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ 610 611 /* 612 * R279 (0x117) - FLL Control 7 613 */ 614 #define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */ 615 #define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */ 616 #define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */ 617 #define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ 618 #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ 619 #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ 620 621 /* 622 * R281 (0x119) - FLL EFS 1 623 */ 624 #define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ 625 #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ 626 #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ 627 628 /* 629 * R282 (0x11A) - FLL EFS 2 630 */ 631 #define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ 632 #define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ 633 #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ 634 #define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ 635 636 /* 637 * R512 (0x200) - Mic Charge Pump 1 638 */ 639 #define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */ 640 #define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */ 641 #define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */ 642 #define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */ 643 #define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */ 644 #define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */ 645 #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */ 646 #define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */ 647 648 /* 649 * R513 (0x201) - Mic Charge Pump 2 650 */ 651 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 652 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 653 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 654 655 /* 656 * R514 (0x202) - DM Charge Pump 1 657 */ 658 #define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */ 659 #define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */ 660 #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */ 661 #define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */ 662 663 /* 664 * R524 (0x20C) - Mic Bias Ctrl 1 665 */ 666 #define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 667 #define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 668 #define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 669 #define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 670 #define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */ 671 #define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 672 #define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 673 #define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 674 #define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 675 #define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 676 #define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 677 #define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */ 678 #define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */ 679 #define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */ 680 #define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 681 #define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */ 682 #define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 683 #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 684 #define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 685 686 /* 687 * R525 (0x20D) - Mic Bias Ctrl 2 688 */ 689 #define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 690 #define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 691 #define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 692 #define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 693 #define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */ 694 #define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 695 #define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 696 #define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 697 #define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 698 #define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 699 #define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 700 #define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */ 701 #define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */ 702 #define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */ 703 #define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 704 #define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */ 705 #define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 706 #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 707 #define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 708 709 /* 710 * R527 (0x20F) - Ear Piece Ctrl 1 711 */ 712 #define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */ 713 #define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */ 714 #define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */ 715 #define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */ 716 #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */ 717 #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */ 718 #define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */ 719 #define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */ 720 #define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */ 721 #define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */ 722 #define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */ 723 #define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */ 724 #define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */ 725 #define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */ 726 #define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */ 727 #define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */ 728 #define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */ 729 #define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */ 730 #define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */ 731 #define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */ 732 #define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */ 733 #define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */ 734 #define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */ 735 #define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */ 736 737 /* 738 * R528 (0x210) - Ear Piece Ctrl 2 739 */ 740 #define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */ 741 #define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */ 742 #define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */ 743 #define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */ 744 #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */ 745 #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */ 746 #define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */ 747 #define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */ 748 #define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */ 749 #define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */ 750 #define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */ 751 #define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */ 752 #define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */ 753 #define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */ 754 #define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */ 755 #define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */ 756 #define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */ 757 #define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */ 758 #define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */ 759 #define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */ 760 #define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */ 761 #define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */ 762 #define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */ 763 #define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */ 764 765 /* 766 * R769 (0x301) - Input Enables 767 */ 768 #define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */ 769 #define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 770 #define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 771 #define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 772 #define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */ 773 #define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 774 #define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 775 #define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 776 #define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */ 777 #define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 778 #define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 779 #define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 780 #define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */ 781 #define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 782 #define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 783 #define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 784 #define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */ 785 #define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 786 #define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 787 #define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 788 #define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */ 789 #define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 790 #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 791 #define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 792 793 /* 794 * R770 (0x302) - IN1L Control 795 */ 796 #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */ 797 #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 798 #define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */ 799 #define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */ 800 #define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 801 #define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 802 #define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 803 #define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 804 #define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 805 #define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 806 #define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 807 #define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 808 #define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 809 810 /* 811 * R771 (0x303) - IN1R Control 812 */ 813 #define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 814 #define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 815 #define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 816 817 /* 818 * R772 (0x304) - IN2L Control 819 */ 820 #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */ 821 #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 822 #define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */ 823 #define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */ 824 #define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 825 #define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 826 #define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 827 #define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 828 #define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 829 #define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 830 #define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 831 #define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 832 #define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 833 834 /* 835 * R773 (0x305) - IN2R Control 836 */ 837 #define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 838 #define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 839 #define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 840 841 /* 842 * R774 (0x306) - IN3L Control 843 */ 844 #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */ 845 #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 846 #define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */ 847 #define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */ 848 #define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 849 #define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 850 #define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 851 #define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 852 #define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 853 #define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 854 #define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 855 #define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 856 #define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 857 858 /* 859 * R775 (0x307) - IN3R Control 860 */ 861 #define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 862 #define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 863 #define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 864 865 /* 866 * R778 (0x30A) - RXANC_SRC 867 */ 868 #define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 869 #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 870 #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 871 872 /* 873 * R779 (0x30B) - Input Volume Ramp 874 */ 875 #define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 876 #define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 877 #define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 878 #define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 879 #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 880 #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 881 882 /* 883 * R780 (0x30C) - ADC Digital Volume 1L 884 */ 885 #define WM2200_IN_VU 0x0200 /* IN_VU */ 886 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 887 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 888 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 889 #define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 890 #define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 891 #define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 892 #define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 893 #define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */ 894 #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */ 895 #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */ 896 897 /* 898 * R781 (0x30D) - ADC Digital Volume 1R 899 */ 900 #define WM2200_IN_VU 0x0200 /* IN_VU */ 901 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 902 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 903 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 904 #define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 905 #define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 906 #define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 907 #define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 908 #define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */ 909 #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */ 910 #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */ 911 912 /* 913 * R782 (0x30E) - ADC Digital Volume 2L 914 */ 915 #define WM2200_IN_VU 0x0200 /* IN_VU */ 916 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 917 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 918 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 919 #define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 920 #define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 921 #define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 922 #define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 923 #define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */ 924 #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */ 925 #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */ 926 927 /* 928 * R783 (0x30F) - ADC Digital Volume 2R 929 */ 930 #define WM2200_IN_VU 0x0200 /* IN_VU */ 931 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 932 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 933 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 934 #define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 935 #define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 936 #define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 937 #define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 938 #define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */ 939 #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */ 940 #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */ 941 942 /* 943 * R784 (0x310) - ADC Digital Volume 3L 944 */ 945 #define WM2200_IN_VU 0x0200 /* IN_VU */ 946 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 947 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 948 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 949 #define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 950 #define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 951 #define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 952 #define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 953 #define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */ 954 #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */ 955 #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */ 956 957 /* 958 * R785 (0x311) - ADC Digital Volume 3R 959 */ 960 #define WM2200_IN_VU 0x0200 /* IN_VU */ 961 #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 962 #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 963 #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 964 #define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 965 #define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 966 #define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 967 #define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 968 #define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */ 969 #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */ 970 #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */ 971 972 /* 973 * R1024 (0x400) - Output Enables 974 */ 975 #define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */ 976 #define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */ 977 #define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */ 978 #define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */ 979 #define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */ 980 #define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */ 981 #define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */ 982 #define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */ 983 #define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */ 984 #define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */ 985 #define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */ 986 #define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */ 987 #define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */ 988 #define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */ 989 #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */ 990 #define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */ 991 992 /* 993 * R1025 (0x401) - DAC Volume Limit 1L 994 */ 995 #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */ 996 #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 997 #define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 998 #define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 999 #define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1000 #define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1001 #define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1002 #define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1003 #define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1004 #define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1005 #define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1006 1007 /* 1008 * R1026 (0x402) - DAC Volume Limit 1R 1009 */ 1010 #define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1011 #define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1012 #define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1013 #define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1014 #define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1015 #define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1016 #define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1017 1018 /* 1019 * R1027 (0x403) - DAC Volume Limit 2L 1020 */ 1021 #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */ 1022 #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1023 #define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1024 #define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1025 #define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1026 #define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1027 #define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1028 #define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1029 1030 /* 1031 * R1028 (0x404) - DAC Volume Limit 2R 1032 */ 1033 #define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1034 #define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1035 #define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1036 #define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1037 1038 /* 1039 * R1033 (0x409) - DAC AEC Control 1 1040 */ 1041 #define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */ 1042 #define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */ 1043 #define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */ 1044 #define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 1045 #define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */ 1046 #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */ 1047 #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */ 1048 1049 /* 1050 * R1034 (0x40A) - Output Volume Ramp 1051 */ 1052 #define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 1053 #define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 1054 #define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 1055 #define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 1056 #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 1057 #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 1058 1059 /* 1060 * R1035 (0x40B) - DAC Digital Volume 1L 1061 */ 1062 #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1063 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1064 #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1065 #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1066 #define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 1067 #define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 1068 #define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 1069 #define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 1070 #define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 1071 #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 1072 #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 1073 1074 /* 1075 * R1036 (0x40C) - DAC Digital Volume 1R 1076 */ 1077 #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1078 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1079 #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1080 #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1081 #define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 1082 #define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 1083 #define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 1084 #define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 1085 #define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 1086 #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 1087 #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 1088 1089 /* 1090 * R1037 (0x40D) - DAC Digital Volume 2L 1091 */ 1092 #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1093 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1094 #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1095 #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1096 #define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 1097 #define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 1098 #define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 1099 #define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 1100 #define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 1101 #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 1102 #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 1103 1104 /* 1105 * R1038 (0x40E) - DAC Digital Volume 2R 1106 */ 1107 #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1108 #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1109 #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1110 #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1111 #define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 1112 #define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 1113 #define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 1114 #define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 1115 #define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 1116 #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 1117 #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 1118 1119 /* 1120 * R1047 (0x417) - PDM 1 1121 */ 1122 #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 1123 #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 1124 #define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 1125 #define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 1126 #define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 1127 #define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 1128 #define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 1129 #define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 1130 #define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 1131 #define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 1132 #define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 1133 #define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 1134 #define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */ 1135 #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */ 1136 #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */ 1137 1138 /* 1139 * R1048 (0x418) - PDM 2 1140 */ 1141 #define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */ 1142 #define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 1143 #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 1144 #define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 1145 1146 /* 1147 * R1280 (0x500) - Audio IF 1_1 1148 */ 1149 #define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */ 1150 #define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */ 1151 #define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */ 1152 #define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1153 #define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */ 1154 #define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */ 1155 #define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */ 1156 #define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 1157 #define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */ 1158 #define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */ 1159 #define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */ 1160 #define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 1161 #define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ 1162 #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ 1163 #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ 1164 1165 /* 1166 * R1281 (0x501) - Audio IF 1_2 1167 */ 1168 #define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 1169 #define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 1170 #define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 1171 #define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 1172 #define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 1173 #define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 1174 #define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 1175 #define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 1176 #define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 1177 #define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 1178 #define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 1179 #define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 1180 #define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 1181 #define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 1182 #define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 1183 #define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 1184 #define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 1185 #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 1186 #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 1187 #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 1188 1189 /* 1190 * R1282 (0x502) - Audio IF 1_3 1191 */ 1192 #define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 1193 #define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 1194 #define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 1195 #define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 1196 #define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 1197 #define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 1198 #define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 1199 #define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 1200 #define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 1201 #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 1202 #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 1203 #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 1204 1205 /* 1206 * R1283 (0x503) - Audio IF 1_4 1207 */ 1208 #define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */ 1209 #define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 1210 #define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 1211 #define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1212 1213 /* 1214 * R1284 (0x504) - Audio IF 1_5 1215 */ 1216 #define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 1217 #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 1218 #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 1219 1220 /* 1221 * R1285 (0x505) - Audio IF 1_6 1222 */ 1223 #define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */ 1224 #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */ 1225 #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */ 1226 1227 /* 1228 * R1286 (0x506) - Audio IF 1_7 1229 */ 1230 #define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */ 1231 #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */ 1232 #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */ 1233 1234 /* 1235 * R1287 (0x507) - Audio IF 1_8 1236 */ 1237 #define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 1238 #define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 1239 #define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 1240 #define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 1241 #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 1242 #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 1243 1244 /* 1245 * R1288 (0x508) - Audio IF 1_9 1246 */ 1247 #define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 1248 #define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 1249 #define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 1250 #define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 1251 #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 1252 #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 1253 1254 /* 1255 * R1289 (0x509) - Audio IF 1_10 1256 */ 1257 #define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 1258 #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 1259 #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 1260 1261 /* 1262 * R1290 (0x50A) - Audio IF 1_11 1263 */ 1264 #define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 1265 #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 1266 #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 1267 1268 /* 1269 * R1291 (0x50B) - Audio IF 1_12 1270 */ 1271 #define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 1272 #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 1273 #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 1274 1275 /* 1276 * R1292 (0x50C) - Audio IF 1_13 1277 */ 1278 #define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 1279 #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 1280 #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 1281 1282 /* 1283 * R1293 (0x50D) - Audio IF 1_14 1284 */ 1285 #define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 1286 #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 1287 #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 1288 1289 /* 1290 * R1294 (0x50E) - Audio IF 1_15 1291 */ 1292 #define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 1293 #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 1294 #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 1295 1296 /* 1297 * R1295 (0x50F) - Audio IF 1_16 1298 */ 1299 #define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 1300 #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 1301 #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 1302 1303 /* 1304 * R1296 (0x510) - Audio IF 1_17 1305 */ 1306 #define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 1307 #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 1308 #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 1309 1310 /* 1311 * R1297 (0x511) - Audio IF 1_18 1312 */ 1313 #define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 1314 #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 1315 #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 1316 1317 /* 1318 * R1298 (0x512) - Audio IF 1_19 1319 */ 1320 #define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 1321 #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 1322 #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 1323 1324 /* 1325 * R1299 (0x513) - Audio IF 1_20 1326 */ 1327 #define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 1328 #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 1329 #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 1330 1331 /* 1332 * R1300 (0x514) - Audio IF 1_21 1333 */ 1334 #define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 1335 #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 1336 #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 1337 1338 /* 1339 * R1301 (0x515) - Audio IF 1_22 1340 */ 1341 #define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */ 1342 #define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */ 1343 #define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */ 1344 #define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 1345 #define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */ 1346 #define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */ 1347 #define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */ 1348 #define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 1349 #define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */ 1350 #define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */ 1351 #define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */ 1352 #define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 1353 #define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */ 1354 #define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */ 1355 #define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */ 1356 #define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 1357 #define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */ 1358 #define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */ 1359 #define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */ 1360 #define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 1361 #define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */ 1362 #define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */ 1363 #define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */ 1364 #define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 1365 #define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 1366 #define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 1367 #define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 1368 #define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 1369 #define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 1370 #define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 1371 #define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 1372 #define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 1373 #define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 1374 #define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 1375 #define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 1376 #define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 1377 #define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 1378 #define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 1379 #define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 1380 #define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 1381 #define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 1382 #define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 1383 #define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 1384 #define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 1385 #define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 1386 #define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 1387 #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 1388 #define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 1389 1390 /* 1391 * R1536 (0x600) - OUT1LMIX Input 1 Source 1392 */ 1393 #define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */ 1394 #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */ 1395 #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */ 1396 1397 /* 1398 * R1537 (0x601) - OUT1LMIX Input 1 Volume 1399 */ 1400 #define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */ 1401 #define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */ 1402 #define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */ 1403 1404 /* 1405 * R1538 (0x602) - OUT1LMIX Input 2 Source 1406 */ 1407 #define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */ 1408 #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */ 1409 #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */ 1410 1411 /* 1412 * R1539 (0x603) - OUT1LMIX Input 2 Volume 1413 */ 1414 #define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */ 1415 #define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */ 1416 #define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */ 1417 1418 /* 1419 * R1540 (0x604) - OUT1LMIX Input 3 Source 1420 */ 1421 #define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */ 1422 #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */ 1423 #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */ 1424 1425 /* 1426 * R1541 (0x605) - OUT1LMIX Input 3 Volume 1427 */ 1428 #define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */ 1429 #define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */ 1430 #define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */ 1431 1432 /* 1433 * R1542 (0x606) - OUT1LMIX Input 4 Source 1434 */ 1435 #define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */ 1436 #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */ 1437 #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */ 1438 1439 /* 1440 * R1543 (0x607) - OUT1LMIX Input 4 Volume 1441 */ 1442 #define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */ 1443 #define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */ 1444 #define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */ 1445 1446 /* 1447 * R1544 (0x608) - OUT1RMIX Input 1 Source 1448 */ 1449 #define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */ 1450 #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */ 1451 #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */ 1452 1453 /* 1454 * R1545 (0x609) - OUT1RMIX Input 1 Volume 1455 */ 1456 #define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */ 1457 #define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */ 1458 #define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */ 1459 1460 /* 1461 * R1546 (0x60A) - OUT1RMIX Input 2 Source 1462 */ 1463 #define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */ 1464 #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */ 1465 #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */ 1466 1467 /* 1468 * R1547 (0x60B) - OUT1RMIX Input 2 Volume 1469 */ 1470 #define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */ 1471 #define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */ 1472 #define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */ 1473 1474 /* 1475 * R1548 (0x60C) - OUT1RMIX Input 3 Source 1476 */ 1477 #define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */ 1478 #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */ 1479 #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */ 1480 1481 /* 1482 * R1549 (0x60D) - OUT1RMIX Input 3 Volume 1483 */ 1484 #define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */ 1485 #define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */ 1486 #define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */ 1487 1488 /* 1489 * R1550 (0x60E) - OUT1RMIX Input 4 Source 1490 */ 1491 #define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */ 1492 #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */ 1493 #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */ 1494 1495 /* 1496 * R1551 (0x60F) - OUT1RMIX Input 4 Volume 1497 */ 1498 #define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */ 1499 #define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */ 1500 #define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */ 1501 1502 /* 1503 * R1552 (0x610) - OUT2LMIX Input 1 Source 1504 */ 1505 #define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */ 1506 #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */ 1507 #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */ 1508 1509 /* 1510 * R1553 (0x611) - OUT2LMIX Input 1 Volume 1511 */ 1512 #define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */ 1513 #define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */ 1514 #define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */ 1515 1516 /* 1517 * R1554 (0x612) - OUT2LMIX Input 2 Source 1518 */ 1519 #define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */ 1520 #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */ 1521 #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */ 1522 1523 /* 1524 * R1555 (0x613) - OUT2LMIX Input 2 Volume 1525 */ 1526 #define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */ 1527 #define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */ 1528 #define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */ 1529 1530 /* 1531 * R1556 (0x614) - OUT2LMIX Input 3 Source 1532 */ 1533 #define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */ 1534 #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */ 1535 #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */ 1536 1537 /* 1538 * R1557 (0x615) - OUT2LMIX Input 3 Volume 1539 */ 1540 #define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */ 1541 #define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */ 1542 #define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */ 1543 1544 /* 1545 * R1558 (0x616) - OUT2LMIX Input 4 Source 1546 */ 1547 #define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */ 1548 #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */ 1549 #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */ 1550 1551 /* 1552 * R1559 (0x617) - OUT2LMIX Input 4 Volume 1553 */ 1554 #define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */ 1555 #define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */ 1556 #define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */ 1557 1558 /* 1559 * R1560 (0x618) - OUT2RMIX Input 1 Source 1560 */ 1561 #define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */ 1562 #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */ 1563 #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */ 1564 1565 /* 1566 * R1561 (0x619) - OUT2RMIX Input 1 Volume 1567 */ 1568 #define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */ 1569 #define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */ 1570 #define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */ 1571 1572 /* 1573 * R1562 (0x61A) - OUT2RMIX Input 2 Source 1574 */ 1575 #define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */ 1576 #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */ 1577 #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */ 1578 1579 /* 1580 * R1563 (0x61B) - OUT2RMIX Input 2 Volume 1581 */ 1582 #define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */ 1583 #define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */ 1584 #define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */ 1585 1586 /* 1587 * R1564 (0x61C) - OUT2RMIX Input 3 Source 1588 */ 1589 #define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */ 1590 #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */ 1591 #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */ 1592 1593 /* 1594 * R1565 (0x61D) - OUT2RMIX Input 3 Volume 1595 */ 1596 #define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */ 1597 #define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */ 1598 #define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */ 1599 1600 /* 1601 * R1566 (0x61E) - OUT2RMIX Input 4 Source 1602 */ 1603 #define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */ 1604 #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */ 1605 #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */ 1606 1607 /* 1608 * R1567 (0x61F) - OUT2RMIX Input 4 Volume 1609 */ 1610 #define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */ 1611 #define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */ 1612 #define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */ 1613 1614 /* 1615 * R1568 (0x620) - AIF1TX1MIX Input 1 Source 1616 */ 1617 #define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */ 1618 #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */ 1619 #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */ 1620 1621 /* 1622 * R1569 (0x621) - AIF1TX1MIX Input 1 Volume 1623 */ 1624 #define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */ 1625 #define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */ 1626 #define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */ 1627 1628 /* 1629 * R1570 (0x622) - AIF1TX1MIX Input 2 Source 1630 */ 1631 #define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */ 1632 #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */ 1633 #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */ 1634 1635 /* 1636 * R1571 (0x623) - AIF1TX1MIX Input 2 Volume 1637 */ 1638 #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */ 1639 #define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */ 1640 #define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */ 1641 1642 /* 1643 * R1572 (0x624) - AIF1TX1MIX Input 3 Source 1644 */ 1645 #define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */ 1646 #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */ 1647 #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */ 1648 1649 /* 1650 * R1573 (0x625) - AIF1TX1MIX Input 3 Volume 1651 */ 1652 #define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */ 1653 #define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */ 1654 #define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */ 1655 1656 /* 1657 * R1574 (0x626) - AIF1TX1MIX Input 4 Source 1658 */ 1659 #define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */ 1660 #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */ 1661 #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */ 1662 1663 /* 1664 * R1575 (0x627) - AIF1TX1MIX Input 4 Volume 1665 */ 1666 #define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */ 1667 #define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */ 1668 #define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */ 1669 1670 /* 1671 * R1576 (0x628) - AIF1TX2MIX Input 1 Source 1672 */ 1673 #define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */ 1674 #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */ 1675 #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */ 1676 1677 /* 1678 * R1577 (0x629) - AIF1TX2MIX Input 1 Volume 1679 */ 1680 #define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */ 1681 #define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */ 1682 #define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */ 1683 1684 /* 1685 * R1578 (0x62A) - AIF1TX2MIX Input 2 Source 1686 */ 1687 #define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */ 1688 #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */ 1689 #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */ 1690 1691 /* 1692 * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume 1693 */ 1694 #define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */ 1695 #define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */ 1696 #define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */ 1697 1698 /* 1699 * R1580 (0x62C) - AIF1TX2MIX Input 3 Source 1700 */ 1701 #define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */ 1702 #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */ 1703 #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */ 1704 1705 /* 1706 * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume 1707 */ 1708 #define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */ 1709 #define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */ 1710 #define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */ 1711 1712 /* 1713 * R1582 (0x62E) - AIF1TX2MIX Input 4 Source 1714 */ 1715 #define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */ 1716 #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */ 1717 #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */ 1718 1719 /* 1720 * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume 1721 */ 1722 #define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */ 1723 #define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */ 1724 #define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */ 1725 1726 /* 1727 * R1584 (0x630) - AIF1TX3MIX Input 1 Source 1728 */ 1729 #define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */ 1730 #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */ 1731 #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */ 1732 1733 /* 1734 * R1585 (0x631) - AIF1TX3MIX Input 1 Volume 1735 */ 1736 #define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */ 1737 #define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */ 1738 #define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */ 1739 1740 /* 1741 * R1586 (0x632) - AIF1TX3MIX Input 2 Source 1742 */ 1743 #define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */ 1744 #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */ 1745 #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */ 1746 1747 /* 1748 * R1587 (0x633) - AIF1TX3MIX Input 2 Volume 1749 */ 1750 #define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */ 1751 #define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */ 1752 #define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */ 1753 1754 /* 1755 * R1588 (0x634) - AIF1TX3MIX Input 3 Source 1756 */ 1757 #define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */ 1758 #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */ 1759 #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */ 1760 1761 /* 1762 * R1589 (0x635) - AIF1TX3MIX Input 3 Volume 1763 */ 1764 #define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */ 1765 #define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */ 1766 #define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */ 1767 1768 /* 1769 * R1590 (0x636) - AIF1TX3MIX Input 4 Source 1770 */ 1771 #define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */ 1772 #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */ 1773 #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */ 1774 1775 /* 1776 * R1591 (0x637) - AIF1TX3MIX Input 4 Volume 1777 */ 1778 #define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */ 1779 #define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */ 1780 #define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */ 1781 1782 /* 1783 * R1592 (0x638) - AIF1TX4MIX Input 1 Source 1784 */ 1785 #define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */ 1786 #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */ 1787 #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */ 1788 1789 /* 1790 * R1593 (0x639) - AIF1TX4MIX Input 1 Volume 1791 */ 1792 #define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */ 1793 #define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */ 1794 #define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */ 1795 1796 /* 1797 * R1594 (0x63A) - AIF1TX4MIX Input 2 Source 1798 */ 1799 #define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */ 1800 #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */ 1801 #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */ 1802 1803 /* 1804 * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume 1805 */ 1806 #define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */ 1807 #define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */ 1808 #define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */ 1809 1810 /* 1811 * R1596 (0x63C) - AIF1TX4MIX Input 3 Source 1812 */ 1813 #define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */ 1814 #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */ 1815 #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */ 1816 1817 /* 1818 * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume 1819 */ 1820 #define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */ 1821 #define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */ 1822 #define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */ 1823 1824 /* 1825 * R1598 (0x63E) - AIF1TX4MIX Input 4 Source 1826 */ 1827 #define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */ 1828 #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */ 1829 #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */ 1830 1831 /* 1832 * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume 1833 */ 1834 #define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */ 1835 #define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */ 1836 #define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */ 1837 1838 /* 1839 * R1600 (0x640) - AIF1TX5MIX Input 1 Source 1840 */ 1841 #define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */ 1842 #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */ 1843 #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */ 1844 1845 /* 1846 * R1601 (0x641) - AIF1TX5MIX Input 1 Volume 1847 */ 1848 #define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */ 1849 #define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */ 1850 #define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */ 1851 1852 /* 1853 * R1602 (0x642) - AIF1TX5MIX Input 2 Source 1854 */ 1855 #define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */ 1856 #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */ 1857 #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */ 1858 1859 /* 1860 * R1603 (0x643) - AIF1TX5MIX Input 2 Volume 1861 */ 1862 #define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */ 1863 #define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */ 1864 #define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */ 1865 1866 /* 1867 * R1604 (0x644) - AIF1TX5MIX Input 3 Source 1868 */ 1869 #define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */ 1870 #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */ 1871 #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */ 1872 1873 /* 1874 * R1605 (0x645) - AIF1TX5MIX Input 3 Volume 1875 */ 1876 #define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */ 1877 #define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */ 1878 #define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */ 1879 1880 /* 1881 * R1606 (0x646) - AIF1TX5MIX Input 4 Source 1882 */ 1883 #define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */ 1884 #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */ 1885 #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */ 1886 1887 /* 1888 * R1607 (0x647) - AIF1TX5MIX Input 4 Volume 1889 */ 1890 #define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */ 1891 #define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */ 1892 #define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */ 1893 1894 /* 1895 * R1608 (0x648) - AIF1TX6MIX Input 1 Source 1896 */ 1897 #define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */ 1898 #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */ 1899 #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */ 1900 1901 /* 1902 * R1609 (0x649) - AIF1TX6MIX Input 1 Volume 1903 */ 1904 #define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */ 1905 #define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */ 1906 #define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */ 1907 1908 /* 1909 * R1610 (0x64A) - AIF1TX6MIX Input 2 Source 1910 */ 1911 #define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */ 1912 #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */ 1913 #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */ 1914 1915 /* 1916 * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume 1917 */ 1918 #define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */ 1919 #define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */ 1920 #define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */ 1921 1922 /* 1923 * R1612 (0x64C) - AIF1TX6MIX Input 3 Source 1924 */ 1925 #define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */ 1926 #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */ 1927 #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */ 1928 1929 /* 1930 * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume 1931 */ 1932 #define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */ 1933 #define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */ 1934 #define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */ 1935 1936 /* 1937 * R1614 (0x64E) - AIF1TX6MIX Input 4 Source 1938 */ 1939 #define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */ 1940 #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */ 1941 #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */ 1942 1943 /* 1944 * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume 1945 */ 1946 #define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */ 1947 #define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */ 1948 #define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */ 1949 1950 /* 1951 * R1616 (0x650) - EQLMIX Input 1 Source 1952 */ 1953 #define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */ 1954 #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */ 1955 #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */ 1956 1957 /* 1958 * R1617 (0x651) - EQLMIX Input 1 Volume 1959 */ 1960 #define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */ 1961 #define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */ 1962 #define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */ 1963 1964 /* 1965 * R1618 (0x652) - EQLMIX Input 2 Source 1966 */ 1967 #define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */ 1968 #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */ 1969 #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */ 1970 1971 /* 1972 * R1619 (0x653) - EQLMIX Input 2 Volume 1973 */ 1974 #define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */ 1975 #define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */ 1976 #define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */ 1977 1978 /* 1979 * R1620 (0x654) - EQLMIX Input 3 Source 1980 */ 1981 #define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */ 1982 #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */ 1983 #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */ 1984 1985 /* 1986 * R1621 (0x655) - EQLMIX Input 3 Volume 1987 */ 1988 #define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */ 1989 #define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */ 1990 #define WM2200_EQLMIX_VOL3_WIDTH 7 /* EQLMIX_VOL3 - [7:1] */ 1991 1992 /* 1993 * R1622 (0x656) - EQLMIX Input 4 Source 1994 */ 1995 #define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */ 1996 #define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */ 1997 #define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */ 1998 1999 /* 2000 * R1623 (0x657) - EQLMIX Input 4 Volume 2001 */ 2002 #define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */ 2003 #define WM2200_EQLMIX_VOL4_SHIFT 1 /* EQLMIX_VOL4 - [7:1] */ 2004 #define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */ 2005 2006 /* 2007 * R1624 (0x658) - EQRMIX Input 1 Source 2008 */ 2009 #define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */ 2010 #define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */ 2011 #define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */ 2012 2013 /* 2014 * R1625 (0x659) - EQRMIX Input 1 Volume 2015 */ 2016 #define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */ 2017 #define WM2200_EQRMIX_VOL1_SHIFT 1 /* EQRMIX_VOL1 - [7:1] */ 2018 #define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */ 2019 2020 /* 2021 * R1626 (0x65A) - EQRMIX Input 2 Source 2022 */ 2023 #define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */ 2024 #define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */ 2025 #define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */ 2026 2027 /* 2028 * R1627 (0x65B) - EQRMIX Input 2 Volume 2029 */ 2030 #define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */ 2031 #define WM2200_EQRMIX_VOL2_SHIFT 1 /* EQRMIX_VOL2 - [7:1] */ 2032 #define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */ 2033 2034 /* 2035 * R1628 (0x65C) - EQRMIX Input 3 Source 2036 */ 2037 #define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */ 2038 #define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */ 2039 #define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */ 2040 2041 /* 2042 * R1629 (0x65D) - EQRMIX Input 3 Volume 2043 */ 2044 #define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */ 2045 #define WM2200_EQRMIX_VOL3_SHIFT 1 /* EQRMIX_VOL3 - [7:1] */ 2046 #define WM2200_EQRMIX_VOL3_WIDTH 7 /* EQRMIX_VOL3 - [7:1] */ 2047 2048 /* 2049 * R1630 (0x65E) - EQRMIX Input 4 Source 2050 */ 2051 #define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */ 2052 #define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */ 2053 #define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */ 2054 2055 /* 2056 * R1631 (0x65F) - EQRMIX Input 4 Volume 2057 */ 2058 #define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */ 2059 #define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */ 2060 #define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */ 2061 2062 /* 2063 * R1632 (0x660) - LHPF1MIX Input 1 Source 2064 */ 2065 #define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */ 2066 #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */ 2067 #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */ 2068 2069 /* 2070 * R1633 (0x661) - LHPF1MIX Input 1 Volume 2071 */ 2072 #define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */ 2073 #define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */ 2074 #define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */ 2075 2076 /* 2077 * R1634 (0x662) - LHPF1MIX Input 2 Source 2078 */ 2079 #define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */ 2080 #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */ 2081 #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */ 2082 2083 /* 2084 * R1635 (0x663) - LHPF1MIX Input 2 Volume 2085 */ 2086 #define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */ 2087 #define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */ 2088 #define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */ 2089 2090 /* 2091 * R1636 (0x664) - LHPF1MIX Input 3 Source 2092 */ 2093 #define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */ 2094 #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */ 2095 #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */ 2096 2097 /* 2098 * R1637 (0x665) - LHPF1MIX Input 3 Volume 2099 */ 2100 #define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */ 2101 #define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */ 2102 #define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */ 2103 2104 /* 2105 * R1638 (0x666) - LHPF1MIX Input 4 Source 2106 */ 2107 #define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */ 2108 #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */ 2109 #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */ 2110 2111 /* 2112 * R1639 (0x667) - LHPF1MIX Input 4 Volume 2113 */ 2114 #define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */ 2115 #define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */ 2116 #define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */ 2117 2118 /* 2119 * R1640 (0x668) - LHPF2MIX Input 1 Source 2120 */ 2121 #define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */ 2122 #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */ 2123 #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */ 2124 2125 /* 2126 * R1641 (0x669) - LHPF2MIX Input 1 Volume 2127 */ 2128 #define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */ 2129 #define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */ 2130 #define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */ 2131 2132 /* 2133 * R1642 (0x66A) - LHPF2MIX Input 2 Source 2134 */ 2135 #define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */ 2136 #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */ 2137 #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */ 2138 2139 /* 2140 * R1643 (0x66B) - LHPF2MIX Input 2 Volume 2141 */ 2142 #define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */ 2143 #define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */ 2144 #define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */ 2145 2146 /* 2147 * R1644 (0x66C) - LHPF2MIX Input 3 Source 2148 */ 2149 #define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */ 2150 #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */ 2151 #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */ 2152 2153 /* 2154 * R1645 (0x66D) - LHPF2MIX Input 3 Volume 2155 */ 2156 #define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */ 2157 #define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */ 2158 #define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */ 2159 2160 /* 2161 * R1646 (0x66E) - LHPF2MIX Input 4 Source 2162 */ 2163 #define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */ 2164 #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */ 2165 #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */ 2166 2167 /* 2168 * R1647 (0x66F) - LHPF2MIX Input 4 Volume 2169 */ 2170 #define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */ 2171 #define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */ 2172 #define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */ 2173 2174 /* 2175 * R1648 (0x670) - DSP1LMIX Input 1 Source 2176 */ 2177 #define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */ 2178 #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */ 2179 #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */ 2180 2181 /* 2182 * R1649 (0x671) - DSP1LMIX Input 1 Volume 2183 */ 2184 #define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */ 2185 #define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */ 2186 #define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */ 2187 2188 /* 2189 * R1650 (0x672) - DSP1LMIX Input 2 Source 2190 */ 2191 #define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */ 2192 #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */ 2193 #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */ 2194 2195 /* 2196 * R1651 (0x673) - DSP1LMIX Input 2 Volume 2197 */ 2198 #define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */ 2199 #define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */ 2200 #define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */ 2201 2202 /* 2203 * R1652 (0x674) - DSP1LMIX Input 3 Source 2204 */ 2205 #define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */ 2206 #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */ 2207 #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */ 2208 2209 /* 2210 * R1653 (0x675) - DSP1LMIX Input 3 Volume 2211 */ 2212 #define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */ 2213 #define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */ 2214 #define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */ 2215 2216 /* 2217 * R1654 (0x676) - DSP1LMIX Input 4 Source 2218 */ 2219 #define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */ 2220 #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */ 2221 #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */ 2222 2223 /* 2224 * R1655 (0x677) - DSP1LMIX Input 4 Volume 2225 */ 2226 #define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */ 2227 #define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */ 2228 #define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */ 2229 2230 /* 2231 * R1656 (0x678) - DSP1RMIX Input 1 Source 2232 */ 2233 #define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */ 2234 #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */ 2235 #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */ 2236 2237 /* 2238 * R1657 (0x679) - DSP1RMIX Input 1 Volume 2239 */ 2240 #define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */ 2241 #define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */ 2242 #define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */ 2243 2244 /* 2245 * R1658 (0x67A) - DSP1RMIX Input 2 Source 2246 */ 2247 #define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */ 2248 #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */ 2249 #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */ 2250 2251 /* 2252 * R1659 (0x67B) - DSP1RMIX Input 2 Volume 2253 */ 2254 #define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */ 2255 #define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */ 2256 #define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */ 2257 2258 /* 2259 * R1660 (0x67C) - DSP1RMIX Input 3 Source 2260 */ 2261 #define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */ 2262 #define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */ 2263 #define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */ 2264 2265 /* 2266 * R1661 (0x67D) - DSP1RMIX Input 3 Volume 2267 */ 2268 #define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */ 2269 #define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */ 2270 #define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */ 2271 2272 /* 2273 * R1662 (0x67E) - DSP1RMIX Input 4 Source 2274 */ 2275 #define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */ 2276 #define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */ 2277 #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */ 2278 2279 /* 2280 * R1663 (0x67F) - DSP1RMIX Input 4 Volume 2281 */ 2282 #define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */ 2283 #define WM2200_DSP1RMIX_VOL4_SHIFT 1 /* DSP1RMIX_VOL4 - [7:1] */ 2284 #define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */ 2285 2286 /* 2287 * R1664 (0x680) - DSP1AUX1MIX Input 1 Source 2288 */ 2289 #define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */ 2290 #define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */ 2291 #define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */ 2292 2293 /* 2294 * R1665 (0x681) - DSP1AUX2MIX Input 1 Source 2295 */ 2296 #define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */ 2297 #define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */ 2298 #define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */ 2299 2300 /* 2301 * R1666 (0x682) - DSP1AUX3MIX Input 1 Source 2302 */ 2303 #define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */ 2304 #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */ 2305 #define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */ 2306 2307 /* 2308 * R1667 (0x683) - DSP1AUX4MIX Input 1 Source 2309 */ 2310 #define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */ 2311 #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */ 2312 #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */ 2313 2314 /* 2315 * R1668 (0x684) - DSP1AUX5MIX Input 1 Source 2316 */ 2317 #define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */ 2318 #define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */ 2319 #define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */ 2320 2321 /* 2322 * R1669 (0x685) - DSP1AUX6MIX Input 1 Source 2323 */ 2324 #define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */ 2325 #define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */ 2326 #define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */ 2327 2328 /* 2329 * R1670 (0x686) - DSP2LMIX Input 1 Source 2330 */ 2331 #define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */ 2332 #define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */ 2333 #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */ 2334 2335 /* 2336 * R1671 (0x687) - DSP2LMIX Input 1 Volume 2337 */ 2338 #define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */ 2339 #define WM2200_DSP2LMIX_VOL1_SHIFT 1 /* DSP2LMIX_VOL1 - [7:1] */ 2340 #define WM2200_DSP2LMIX_VOL1_WIDTH 7 /* DSP2LMIX_VOL1 - [7:1] */ 2341 2342 /* 2343 * R1672 (0x688) - DSP2LMIX Input 2 Source 2344 */ 2345 #define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */ 2346 #define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */ 2347 #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */ 2348 2349 /* 2350 * R1673 (0x689) - DSP2LMIX Input 2 Volume 2351 */ 2352 #define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */ 2353 #define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */ 2354 #define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */ 2355 2356 /* 2357 * R1674 (0x68A) - DSP2LMIX Input 3 Source 2358 */ 2359 #define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */ 2360 #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */ 2361 #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */ 2362 2363 /* 2364 * R1675 (0x68B) - DSP2LMIX Input 3 Volume 2365 */ 2366 #define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */ 2367 #define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */ 2368 #define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */ 2369 2370 /* 2371 * R1676 (0x68C) - DSP2LMIX Input 4 Source 2372 */ 2373 #define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */ 2374 #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */ 2375 #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */ 2376 2377 /* 2378 * R1677 (0x68D) - DSP2LMIX Input 4 Volume 2379 */ 2380 #define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */ 2381 #define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */ 2382 #define WM2200_DSP2LMIX_VOL4_WIDTH 7 /* DSP2LMIX_VOL4 - [7:1] */ 2383 2384 /* 2385 * R1678 (0x68E) - DSP2RMIX Input 1 Source 2386 */ 2387 #define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */ 2388 #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */ 2389 #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */ 2390 2391 /* 2392 * R1679 (0x68F) - DSP2RMIX Input 1 Volume 2393 */ 2394 #define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */ 2395 #define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */ 2396 #define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */ 2397 2398 /* 2399 * R1680 (0x690) - DSP2RMIX Input 2 Source 2400 */ 2401 #define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */ 2402 #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */ 2403 #define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */ 2404 2405 /* 2406 * R1681 (0x691) - DSP2RMIX Input 2 Volume 2407 */ 2408 #define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */ 2409 #define WM2200_DSP2RMIX_VOL2_SHIFT 1 /* DSP2RMIX_VOL2 - [7:1] */ 2410 #define WM2200_DSP2RMIX_VOL2_WIDTH 7 /* DSP2RMIX_VOL2 - [7:1] */ 2411 2412 /* 2413 * R1682 (0x692) - DSP2RMIX Input 3 Source 2414 */ 2415 #define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */ 2416 #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */ 2417 #define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */ 2418 2419 /* 2420 * R1683 (0x693) - DSP2RMIX Input 3 Volume 2421 */ 2422 #define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */ 2423 #define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */ 2424 #define WM2200_DSP2RMIX_VOL3_WIDTH 7 /* DSP2RMIX_VOL3 - [7:1] */ 2425 2426 /* 2427 * R1684 (0x694) - DSP2RMIX Input 4 Source 2428 */ 2429 #define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */ 2430 #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */ 2431 #define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */ 2432 2433 /* 2434 * R1685 (0x695) - DSP2RMIX Input 4 Volume 2435 */ 2436 #define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */ 2437 #define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */ 2438 #define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */ 2439 2440 /* 2441 * R1686 (0x696) - DSP2AUX1MIX Input 1 Source 2442 */ 2443 #define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */ 2444 #define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */ 2445 #define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */ 2446 2447 /* 2448 * R1687 (0x697) - DSP2AUX2MIX Input 1 Source 2449 */ 2450 #define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */ 2451 #define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */ 2452 #define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */ 2453 2454 /* 2455 * R1688 (0x698) - DSP2AUX3MIX Input 1 Source 2456 */ 2457 #define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */ 2458 #define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */ 2459 #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */ 2460 2461 /* 2462 * R1689 (0x699) - DSP2AUX4MIX Input 1 Source 2463 */ 2464 #define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */ 2465 #define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */ 2466 #define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */ 2467 2468 /* 2469 * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source 2470 */ 2471 #define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */ 2472 #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */ 2473 #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */ 2474 2475 /* 2476 * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source 2477 */ 2478 #define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */ 2479 #define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */ 2480 #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */ 2481 2482 /* 2483 * R1792 (0x700) - GPIO CTRL 1 2484 */ 2485 #define WM2200_GP1_DIR 0x8000 /* GP1_DIR */ 2486 #define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 2487 #define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */ 2488 #define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */ 2489 #define WM2200_GP1_PU 0x4000 /* GP1_PU */ 2490 #define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */ 2491 #define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */ 2492 #define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */ 2493 #define WM2200_GP1_PD 0x2000 /* GP1_PD */ 2494 #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */ 2495 #define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */ 2496 #define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */ 2497 #define WM2200_GP1_POL 0x0400 /* GP1_POL */ 2498 #define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */ 2499 #define WM2200_GP1_POL_SHIFT 10 /* GP1_POL */ 2500 #define WM2200_GP1_POL_WIDTH 1 /* GP1_POL */ 2501 #define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 2502 #define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 2503 #define WM2200_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 2504 #define WM2200_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 2505 #define WM2200_GP1_DB 0x0100 /* GP1_DB */ 2506 #define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */ 2507 #define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */ 2508 #define WM2200_GP1_DB_WIDTH 1 /* GP1_DB */ 2509 #define WM2200_GP1_LVL 0x0040 /* GP1_LVL */ 2510 #define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 2511 #define WM2200_GP1_LVL_SHIFT 6 /* GP1_LVL */ 2512 #define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */ 2513 #define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 2514 #define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 2515 #define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 2516 2517 /* 2518 * R1793 (0x701) - GPIO CTRL 2 2519 */ 2520 #define WM2200_GP2_DIR 0x8000 /* GP2_DIR */ 2521 #define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 2522 #define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */ 2523 #define WM2200_GP2_DIR_WIDTH 1 /* GP2_DIR */ 2524 #define WM2200_GP2_PU 0x4000 /* GP2_PU */ 2525 #define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */ 2526 #define WM2200_GP2_PU_SHIFT 14 /* GP2_PU */ 2527 #define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */ 2528 #define WM2200_GP2_PD 0x2000 /* GP2_PD */ 2529 #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */ 2530 #define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */ 2531 #define WM2200_GP2_PD_WIDTH 1 /* GP2_PD */ 2532 #define WM2200_GP2_POL 0x0400 /* GP2_POL */ 2533 #define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */ 2534 #define WM2200_GP2_POL_SHIFT 10 /* GP2_POL */ 2535 #define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */ 2536 #define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 2537 #define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 2538 #define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 2539 #define WM2200_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 2540 #define WM2200_GP2_DB 0x0100 /* GP2_DB */ 2541 #define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */ 2542 #define WM2200_GP2_DB_SHIFT 8 /* GP2_DB */ 2543 #define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */ 2544 #define WM2200_GP2_LVL 0x0040 /* GP2_LVL */ 2545 #define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 2546 #define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */ 2547 #define WM2200_GP2_LVL_WIDTH 1 /* GP2_LVL */ 2548 #define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 2549 #define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 2550 #define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 2551 2552 /* 2553 * R1794 (0x702) - GPIO CTRL 3 2554 */ 2555 #define WM2200_GP3_DIR 0x8000 /* GP3_DIR */ 2556 #define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 2557 #define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */ 2558 #define WM2200_GP3_DIR_WIDTH 1 /* GP3_DIR */ 2559 #define WM2200_GP3_PU 0x4000 /* GP3_PU */ 2560 #define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */ 2561 #define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */ 2562 #define WM2200_GP3_PU_WIDTH 1 /* GP3_PU */ 2563 #define WM2200_GP3_PD 0x2000 /* GP3_PD */ 2564 #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */ 2565 #define WM2200_GP3_PD_SHIFT 13 /* GP3_PD */ 2566 #define WM2200_GP3_PD_WIDTH 1 /* GP3_PD */ 2567 #define WM2200_GP3_POL 0x0400 /* GP3_POL */ 2568 #define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */ 2569 #define WM2200_GP3_POL_SHIFT 10 /* GP3_POL */ 2570 #define WM2200_GP3_POL_WIDTH 1 /* GP3_POL */ 2571 #define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 2572 #define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 2573 #define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 2574 #define WM2200_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 2575 #define WM2200_GP3_DB 0x0100 /* GP3_DB */ 2576 #define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */ 2577 #define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */ 2578 #define WM2200_GP3_DB_WIDTH 1 /* GP3_DB */ 2579 #define WM2200_GP3_LVL 0x0040 /* GP3_LVL */ 2580 #define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 2581 #define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */ 2582 #define WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */ 2583 #define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 2584 #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 2585 #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 2586 2587 /* 2588 * R1795 (0x703) - GPIO CTRL 4 2589 */ 2590 #define WM2200_GP4_DIR 0x8000 /* GP4_DIR */ 2591 #define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 2592 #define WM2200_GP4_DIR_SHIFT 15 /* GP4_DIR */ 2593 #define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */ 2594 #define WM2200_GP4_PU 0x4000 /* GP4_PU */ 2595 #define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */ 2596 #define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */ 2597 #define WM2200_GP4_PU_WIDTH 1 /* GP4_PU */ 2598 #define WM2200_GP4_PD 0x2000 /* GP4_PD */ 2599 #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */ 2600 #define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */ 2601 #define WM2200_GP4_PD_WIDTH 1 /* GP4_PD */ 2602 #define WM2200_GP4_POL 0x0400 /* GP4_POL */ 2603 #define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */ 2604 #define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */ 2605 #define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */ 2606 #define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 2607 #define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 2608 #define WM2200_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 2609 #define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 2610 #define WM2200_GP4_DB 0x0100 /* GP4_DB */ 2611 #define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */ 2612 #define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */ 2613 #define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */ 2614 #define WM2200_GP4_LVL 0x0040 /* GP4_LVL */ 2615 #define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 2616 #define WM2200_GP4_LVL_SHIFT 6 /* GP4_LVL */ 2617 #define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */ 2618 #define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 2619 #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 2620 #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 2621 2622 /* 2623 * R1799 (0x707) - ADPS1 IRQ0 2624 */ 2625 #define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */ 2626 #define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */ 2627 #define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1 */ 2628 #define WM2200_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */ 2629 #define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */ 2630 #define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */ 2631 #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */ 2632 #define WM2200_DSP_IRQ0_WIDTH 1 /* DSP_IRQ0 */ 2633 2634 /* 2635 * R1800 (0x708) - ADPS1 IRQ1 2636 */ 2637 #define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */ 2638 #define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */ 2639 #define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */ 2640 #define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */ 2641 #define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */ 2642 #define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */ 2643 #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */ 2644 #define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */ 2645 2646 /* 2647 * R1801 (0x709) - Misc Pad Ctrl 1 2648 */ 2649 #define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 2650 #define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 2651 #define WM2200_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 2652 #define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 2653 #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */ 2654 #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 2655 #define WM2200_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 2656 #define WM2200_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 2657 #define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */ 2658 #define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 2659 #define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 2660 #define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 2661 #define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */ 2662 #define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */ 2663 #define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */ 2664 #define WM2200_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 2665 #define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */ 2666 #define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */ 2667 #define WM2200_DACLRCLK1_PD_SHIFT 9 /* DACLRCLK1_PD */ 2668 #define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 2669 #define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */ 2670 #define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */ 2671 #define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */ 2672 #define WM2200_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 2673 #define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */ 2674 #define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */ 2675 #define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */ 2676 #define WM2200_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 2677 #define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */ 2678 #define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */ 2679 #define WM2200_DACDAT1_PU_SHIFT 6 /* DACDAT1_PU */ 2680 #define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 2681 #define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */ 2682 #define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */ 2683 #define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */ 2684 #define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 2685 #define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */ 2686 #define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */ 2687 #define WM2200_DMICDAT3_PD_SHIFT 4 /* DMICDAT3_PD */ 2688 #define WM2200_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 2689 #define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */ 2690 #define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */ 2691 #define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */ 2692 #define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 2693 #define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */ 2694 #define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */ 2695 #define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */ 2696 #define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 2697 #define WM2200_RSTB_PU 0x0002 /* RSTB_PU */ 2698 #define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */ 2699 #define WM2200_RSTB_PU_SHIFT 1 /* RSTB_PU */ 2700 #define WM2200_RSTB_PU_WIDTH 1 /* RSTB_PU */ 2701 #define WM2200_ADDR_PD 0x0001 /* ADDR_PD */ 2702 #define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 2703 #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */ 2704 #define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */ 2705 2706 /* 2707 * R2048 (0x800) - Interrupt Status 1 2708 */ 2709 #define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */ 2710 #define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */ 2711 #define WM2200_DSP_IRQ0_EINT_SHIFT 7 /* DSP_IRQ0_EINT */ 2712 #define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */ 2713 #define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */ 2714 #define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */ 2715 #define WM2200_DSP_IRQ1_EINT_SHIFT 6 /* DSP_IRQ1_EINT */ 2716 #define WM2200_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 2717 #define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */ 2718 #define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */ 2719 #define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */ 2720 #define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 2721 #define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */ 2722 #define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */ 2723 #define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */ 2724 #define WM2200_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 2725 #define WM2200_GP4_EINT 0x0008 /* GP4_EINT */ 2726 #define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 2727 #define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */ 2728 #define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */ 2729 #define WM2200_GP3_EINT 0x0004 /* GP3_EINT */ 2730 #define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 2731 #define WM2200_GP3_EINT_SHIFT 2 /* GP3_EINT */ 2732 #define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */ 2733 #define WM2200_GP2_EINT 0x0002 /* GP2_EINT */ 2734 #define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 2735 #define WM2200_GP2_EINT_SHIFT 1 /* GP2_EINT */ 2736 #define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */ 2737 #define WM2200_GP1_EINT 0x0001 /* GP1_EINT */ 2738 #define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 2739 #define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */ 2740 #define WM2200_GP1_EINT_WIDTH 1 /* GP1_EINT */ 2741 2742 /* 2743 * R2049 (0x801) - Interrupt Status 1 Mask 2744 */ 2745 #define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */ 2746 #define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */ 2747 #define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */ 2748 #define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */ 2749 #define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */ 2750 #define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */ 2751 #define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */ 2752 #define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 2753 #define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */ 2754 #define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */ 2755 #define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */ 2756 #define WM2200_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 2757 #define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */ 2758 #define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */ 2759 #define WM2200_IM_DSP_IRQ3_EINT_SHIFT 4 /* IM_DSP_IRQ3_EINT */ 2760 #define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 2761 #define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 2762 #define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 2763 #define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 2764 #define WM2200_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 2765 #define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 2766 #define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 2767 #define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 2768 #define WM2200_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 2769 #define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 2770 #define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 2771 #define WM2200_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 2772 #define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 2773 #define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 2774 #define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 2775 #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 2776 #define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 2777 2778 /* 2779 * R2050 (0x802) - Interrupt Status 2 2780 */ 2781 #define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */ 2782 #define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */ 2783 #define WM2200_WSEQ_BUSY_EINT_SHIFT 8 /* WSEQ_BUSY_EINT */ 2784 #define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 2785 #define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */ 2786 #define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */ 2787 #define WM2200_FLL_LOCK_EINT_SHIFT 1 /* FLL_LOCK_EINT */ 2788 #define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 2789 #define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */ 2790 #define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */ 2791 #define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */ 2792 #define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */ 2793 2794 /* 2795 * R2051 (0x803) - Interrupt Raw Status 2 2796 */ 2797 #define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */ 2798 #define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */ 2799 #define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */ 2800 #define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */ 2801 #define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */ 2802 #define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */ 2803 #define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */ 2804 #define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ 2805 #define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */ 2806 #define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */ 2807 #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */ 2808 #define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */ 2809 2810 /* 2811 * R2052 (0x804) - Interrupt Status 2 Mask 2812 */ 2813 #define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */ 2814 #define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */ 2815 #define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */ 2816 #define WM2200_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 2817 #define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */ 2818 #define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */ 2819 #define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */ 2820 #define WM2200_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 2821 #define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */ 2822 #define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */ 2823 #define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */ 2824 #define WM2200_IM_CLKGEN_EINT_WIDTH 1 /* IM_CLKGEN_EINT */ 2825 2826 /* 2827 * R2056 (0x808) - Interrupt Control 2828 */ 2829 #define WM2200_IM_IRQ 0x0001 /* IM_IRQ */ 2830 #define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 2831 #define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */ 2832 #define WM2200_IM_IRQ_WIDTH 1 /* IM_IRQ */ 2833 2834 /* 2835 * R2304 (0x900) - EQL_1 2836 */ 2837 #define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */ 2838 #define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ 2839 #define WM2200_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */ 2840 #define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */ 2841 #define WM2200_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */ 2842 #define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ 2843 #define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */ 2844 #define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ 2845 #define WM2200_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */ 2846 #define WM2200_EQL_ENA 0x0001 /* EQL_ENA */ 2847 #define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */ 2848 #define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */ 2849 #define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */ 2850 2851 /* 2852 * R2305 (0x901) - EQL_2 2853 */ 2854 #define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */ 2855 #define WM2200_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */ 2856 #define WM2200_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */ 2857 #define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */ 2858 #define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ 2859 #define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ 2860 2861 /* 2862 * R2306 (0x902) - EQL_3 2863 */ 2864 #define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */ 2865 #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ 2866 #define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */ 2867 2868 /* 2869 * R2307 (0x903) - EQL_4 2870 */ 2871 #define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */ 2872 #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ 2873 #define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */ 2874 2875 /* 2876 * R2308 (0x904) - EQL_5 2877 */ 2878 #define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */ 2879 #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ 2880 #define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */ 2881 2882 /* 2883 * R2309 (0x905) - EQL_6 2884 */ 2885 #define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */ 2886 #define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ 2887 #define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */ 2888 2889 /* 2890 * R2310 (0x906) - EQL_7 2891 */ 2892 #define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */ 2893 #define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */ 2894 #define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */ 2895 2896 /* 2897 * R2311 (0x907) - EQL_8 2898 */ 2899 #define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */ 2900 #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ 2901 #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ 2902 2903 /* 2904 * R2312 (0x908) - EQL_9 2905 */ 2906 #define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */ 2907 #define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */ 2908 #define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */ 2909 2910 /* 2911 * R2313 (0x909) - EQL_10 2912 */ 2913 #define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */ 2914 #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ 2915 #define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */ 2916 2917 /* 2918 * R2314 (0x90A) - EQL_11 2919 */ 2920 #define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */ 2921 #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ 2922 #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ 2923 2924 /* 2925 * R2315 (0x90B) - EQL_12 2926 */ 2927 #define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */ 2928 #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ 2929 #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ 2930 2931 /* 2932 * R2316 (0x90C) - EQL_13 2933 */ 2934 #define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */ 2935 #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ 2936 #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ 2937 2938 /* 2939 * R2317 (0x90D) - EQL_14 2940 */ 2941 #define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */ 2942 #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ 2943 #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ 2944 2945 /* 2946 * R2318 (0x90E) - EQL_15 2947 */ 2948 #define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */ 2949 #define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */ 2950 #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ 2951 2952 /* 2953 * R2319 (0x90F) - EQL_16 2954 */ 2955 #define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */ 2956 #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ 2957 #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ 2958 2959 /* 2960 * R2320 (0x910) - EQL_17 2961 */ 2962 #define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */ 2963 #define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */ 2964 #define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */ 2965 2966 /* 2967 * R2321 (0x911) - EQL_18 2968 */ 2969 #define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */ 2970 #define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */ 2971 #define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */ 2972 2973 /* 2974 * R2322 (0x912) - EQL_19 2975 */ 2976 #define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */ 2977 #define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ 2978 #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ 2979 2980 /* 2981 * R2323 (0x913) - EQL_20 2982 */ 2983 #define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */ 2984 #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ 2985 #define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */ 2986 2987 /* 2988 * R2326 (0x916) - EQR_1 2989 */ 2990 #define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */ 2991 #define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ 2992 #define WM2200_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */ 2993 #define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */ 2994 #define WM2200_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */ 2995 #define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ 2996 #define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */ 2997 #define WM2200_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */ 2998 #define WM2200_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */ 2999 #define WM2200_EQR_ENA 0x0001 /* EQR_ENA */ 3000 #define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */ 3001 #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */ 3002 #define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */ 3003 3004 /* 3005 * R2327 (0x917) - EQR_2 3006 */ 3007 #define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */ 3008 #define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ 3009 #define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ 3010 #define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */ 3011 #define WM2200_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */ 3012 #define WM2200_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */ 3013 3014 /* 3015 * R2328 (0x918) - EQR_3 3016 */ 3017 #define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */ 3018 #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ 3019 #define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */ 3020 3021 /* 3022 * R2329 (0x919) - EQR_4 3023 */ 3024 #define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */ 3025 #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ 3026 #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ 3027 3028 /* 3029 * R2330 (0x91A) - EQR_5 3030 */ 3031 #define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */ 3032 #define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */ 3033 #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ 3034 3035 /* 3036 * R2331 (0x91B) - EQR_6 3037 */ 3038 #define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */ 3039 #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ 3040 #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ 3041 3042 /* 3043 * R2332 (0x91C) - EQR_7 3044 */ 3045 #define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */ 3046 #define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */ 3047 #define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ 3048 3049 /* 3050 * R2333 (0x91D) - EQR_8 3051 */ 3052 #define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */ 3053 #define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */ 3054 #define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */ 3055 3056 /* 3057 * R2334 (0x91E) - EQR_9 3058 */ 3059 #define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */ 3060 #define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */ 3061 #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ 3062 3063 /* 3064 * R2335 (0x91F) - EQR_10 3065 */ 3066 #define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */ 3067 #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ 3068 #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ 3069 3070 /* 3071 * R2336 (0x920) - EQR_11 3072 */ 3073 #define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */ 3074 #define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */ 3075 #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ 3076 3077 /* 3078 * R2337 (0x921) - EQR_12 3079 */ 3080 #define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */ 3081 #define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */ 3082 #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ 3083 3084 /* 3085 * R2338 (0x922) - EQR_13 3086 */ 3087 #define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */ 3088 #define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */ 3089 #define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ 3090 3091 /* 3092 * R2339 (0x923) - EQR_14 3093 */ 3094 #define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */ 3095 #define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */ 3096 #define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ 3097 3098 /* 3099 * R2340 (0x924) - EQR_15 3100 */ 3101 #define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */ 3102 #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ 3103 #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ 3104 3105 /* 3106 * R2341 (0x925) - EQR_16 3107 */ 3108 #define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */ 3109 #define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ 3110 #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ 3111 3112 /* 3113 * R2342 (0x926) - EQR_17 3114 */ 3115 #define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */ 3116 #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ 3117 #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ 3118 3119 /* 3120 * R2343 (0x927) - EQR_18 3121 */ 3122 #define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */ 3123 #define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */ 3124 #define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */ 3125 3126 /* 3127 * R2344 (0x928) - EQR_19 3128 */ 3129 #define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */ 3130 #define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */ 3131 #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ 3132 3133 /* 3134 * R2345 (0x929) - EQR_20 3135 */ 3136 #define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */ 3137 #define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */ 3138 #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ 3139 3140 /* 3141 * R2366 (0x93E) - HPLPF1_1 3142 */ 3143 #define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 3144 #define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 3145 #define WM2200_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 3146 #define WM2200_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 3147 #define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 3148 #define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 3149 #define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 3150 #define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 3151 3152 /* 3153 * R2367 (0x93F) - HPLPF1_2 3154 */ 3155 #define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 3156 #define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 3157 #define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 3158 3159 /* 3160 * R2370 (0x942) - HPLPF2_1 3161 */ 3162 #define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 3163 #define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 3164 #define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 3165 #define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 3166 #define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 3167 #define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 3168 #define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 3169 #define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 3170 3171 /* 3172 * R2371 (0x943) - HPLPF2_2 3173 */ 3174 #define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 3175 #define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 3176 #define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 3177 3178 /* 3179 * R2560 (0xA00) - DSP1 Control 1 3180 */ 3181 #define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */ 3182 #define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */ 3183 #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */ 3184 #define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH 1 /* DSP1_RW_SEQUENCE_ENA */ 3185 3186 /* 3187 * R2562 (0xA02) - DSP1 Control 2 3188 */ 3189 #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */ 3190 #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */ 3191 #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */ 3192 3193 /* 3194 * R2563 (0xA03) - DSP1 Control 3 3195 */ 3196 #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */ 3197 #define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 /* DSP1_PAGE_BASE_DM - [15:8] */ 3198 #define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */ 3199 3200 /* 3201 * R2564 (0xA04) - DSP1 Control 4 3202 */ 3203 #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3204 #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3205 #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3206 3207 /* 3208 * R2566 (0xA06) - DSP1 Control 5 3209 */ 3210 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3211 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3212 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3213 3214 /* 3215 * R2567 (0xA07) - DSP1 Control 6 3216 */ 3217 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3218 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3219 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3220 3221 /* 3222 * R2568 (0xA08) - DSP1 Control 7 3223 */ 3224 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3225 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3226 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3227 3228 /* 3229 * R2569 (0xA09) - DSP1 Control 8 3230 */ 3231 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3232 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3233 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3234 3235 /* 3236 * R2570 (0xA0A) - DSP1 Control 9 3237 */ 3238 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3239 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3240 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3241 3242 /* 3243 * R2571 (0xA0B) - DSP1 Control 10 3244 */ 3245 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3246 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3247 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3248 3249 /* 3250 * R2572 (0xA0C) - DSP1 Control 11 3251 */ 3252 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3253 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3254 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3255 3256 /* 3257 * R2573 (0xA0D) - DSP1 Control 12 3258 */ 3259 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3260 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3261 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3262 3263 /* 3264 * R2575 (0xA0F) - DSP1 Control 13 3265 */ 3266 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3267 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3268 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3269 3270 /* 3271 * R2576 (0xA10) - DSP1 Control 14 3272 */ 3273 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3274 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3275 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3276 3277 /* 3278 * R2577 (0xA11) - DSP1 Control 15 3279 */ 3280 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3281 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3282 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3283 3284 /* 3285 * R2578 (0xA12) - DSP1 Control 16 3286 */ 3287 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3288 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3289 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3290 3291 /* 3292 * R2579 (0xA13) - DSP1 Control 17 3293 */ 3294 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3295 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3296 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3297 3298 /* 3299 * R2580 (0xA14) - DSP1 Control 18 3300 */ 3301 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3302 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3303 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3304 3305 /* 3306 * R2582 (0xA16) - DSP1 Control 19 3307 */ 3308 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3309 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3310 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3311 3312 /* 3313 * R2583 (0xA17) - DSP1 Control 20 3314 */ 3315 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3316 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3317 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3318 3319 /* 3320 * R2584 (0xA18) - DSP1 Control 21 3321 */ 3322 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3323 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3324 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3325 3326 /* 3327 * R2586 (0xA1A) - DSP1 Control 22 3328 */ 3329 #define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */ 3330 #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */ 3331 #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */ 3332 3333 /* 3334 * R2587 (0xA1B) - DSP1 Control 23 3335 */ 3336 #define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */ 3337 #define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */ 3338 #define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */ 3339 3340 /* 3341 * R2588 (0xA1C) - DSP1 Control 24 3342 */ 3343 #define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */ 3344 #define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */ 3345 #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */ 3346 3347 /* 3348 * R2590 (0xA1E) - DSP1 Control 25 3349 */ 3350 #define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */ 3351 #define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */ 3352 #define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */ 3353 #define WM2200_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */ 3354 #define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */ 3355 #define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */ 3356 #define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */ 3357 #define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */ 3358 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3359 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3360 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3361 3362 /* 3363 * R2592 (0xA20) - DSP1 Control 26 3364 */ 3365 #define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */ 3366 #define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */ 3367 #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */ 3368 3369 /* 3370 * R2593 (0xA21) - DSP1 Control 27 3371 */ 3372 #define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */ 3373 #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */ 3374 #define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */ 3375 3376 /* 3377 * R2594 (0xA22) - DSP1 Control 28 3378 */ 3379 #define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */ 3380 #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */ 3381 #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */ 3382 3383 /* 3384 * R2595 (0xA23) - DSP1 Control 29 3385 */ 3386 #define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */ 3387 #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */ 3388 #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */ 3389 3390 /* 3391 * R2596 (0xA24) - DSP1 Control 30 3392 */ 3393 #define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 3394 #define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 3395 #define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 3396 #define WM2200_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 3397 #define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 3398 #define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 3399 #define WM2200_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 3400 #define WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 3401 #define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 3402 #define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 3403 #define WM2200_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 3404 #define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 3405 #define WM2200_DSP1_START 0x0001 /* DSP1_START */ 3406 #define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */ 3407 #define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */ 3408 #define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */ 3409 3410 /* 3411 * R2598 (0xA26) - DSP1 Control 31 3412 */ 3413 #define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */ 3414 #define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */ 3415 #define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */ 3416 #define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */ 3417 #define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */ 3418 #define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */ 3419 #define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */ 3420 #define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */ 3421 #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */ 3422 #define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */ 3423 3424 /* 3425 * R2816 (0xB00) - DSP2 Control 1 3426 */ 3427 #define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */ 3428 #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */ 3429 #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */ 3430 #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */ 3431 3432 /* 3433 * R2818 (0xB02) - DSP2 Control 2 3434 */ 3435 #define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */ 3436 #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 /* DSP2_PAGE_BASE_PM - [15:8] */ 3437 #define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */ 3438 3439 /* 3440 * R2819 (0xB03) - DSP2 Control 3 3441 */ 3442 #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */ 3443 #define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT 8 /* DSP2_PAGE_BASE_DM - [15:8] */ 3444 #define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH 8 /* DSP2_PAGE_BASE_DM - [15:8] */ 3445 3446 /* 3447 * R2820 (0xB04) - DSP2 Control 4 3448 */ 3449 #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3450 #define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3451 #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3452 3453 /* 3454 * R2822 (0xB06) - DSP2 Control 5 3455 */ 3456 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3457 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3458 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3459 3460 /* 3461 * R2823 (0xB07) - DSP2 Control 6 3462 */ 3463 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3464 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3465 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3466 3467 /* 3468 * R2824 (0xB08) - DSP2 Control 7 3469 */ 3470 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3471 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3472 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3473 3474 /* 3475 * R2825 (0xB09) - DSP2 Control 8 3476 */ 3477 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3478 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3479 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3480 3481 /* 3482 * R2826 (0xB0A) - DSP2 Control 9 3483 */ 3484 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3485 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3486 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3487 3488 /* 3489 * R2827 (0xB0B) - DSP2 Control 10 3490 */ 3491 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3492 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3493 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3494 3495 /* 3496 * R2828 (0xB0C) - DSP2 Control 11 3497 */ 3498 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3499 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3500 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3501 3502 /* 3503 * R2829 (0xB0D) - DSP2 Control 12 3504 */ 3505 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3506 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3507 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3508 3509 /* 3510 * R2831 (0xB0F) - DSP2 Control 13 3511 */ 3512 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3513 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3514 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3515 3516 /* 3517 * R2832 (0xB10) - DSP2 Control 14 3518 */ 3519 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3520 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3521 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3522 3523 /* 3524 * R2833 (0xB11) - DSP2 Control 15 3525 */ 3526 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3527 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3528 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3529 3530 /* 3531 * R2834 (0xB12) - DSP2 Control 16 3532 */ 3533 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3534 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3535 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3536 3537 /* 3538 * R2835 (0xB13) - DSP2 Control 17 3539 */ 3540 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3541 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3542 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3543 3544 /* 3545 * R2836 (0xB14) - DSP2 Control 18 3546 */ 3547 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3548 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3549 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3550 3551 /* 3552 * R2838 (0xB16) - DSP2 Control 19 3553 */ 3554 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3555 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3556 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3557 3558 /* 3559 * R2839 (0xB17) - DSP2 Control 20 3560 */ 3561 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3562 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3563 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3564 3565 /* 3566 * R2840 (0xB18) - DSP2 Control 21 3567 */ 3568 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3569 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3570 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3571 3572 /* 3573 * R2842 (0xB1A) - DSP2 Control 22 3574 */ 3575 #define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */ 3576 #define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */ 3577 #define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */ 3578 3579 /* 3580 * R2843 (0xB1B) - DSP2 Control 23 3581 */ 3582 #define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */ 3583 #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */ 3584 #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */ 3585 3586 /* 3587 * R2844 (0xB1C) - DSP2 Control 24 3588 */ 3589 #define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */ 3590 #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */ 3591 #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */ 3592 3593 /* 3594 * R2846 (0xB1E) - DSP2 Control 25 3595 */ 3596 #define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */ 3597 #define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */ 3598 #define WM2200_DSP2_PING_FULL_SHIFT 15 /* DSP2_PING_FULL */ 3599 #define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */ 3600 #define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */ 3601 #define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */ 3602 #define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */ 3603 #define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */ 3604 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3605 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3606 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3607 3608 /* 3609 * R2848 (0xB20) - DSP2 Control 26 3610 */ 3611 #define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */ 3612 #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */ 3613 #define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */ 3614 3615 /* 3616 * R2849 (0xB21) - DSP2 Control 27 3617 */ 3618 #define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */ 3619 #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */ 3620 #define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */ 3621 3622 /* 3623 * R2850 (0xB22) - DSP2 Control 28 3624 */ 3625 #define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */ 3626 #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */ 3627 #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */ 3628 3629 /* 3630 * R2851 (0xB23) - DSP2 Control 29 3631 */ 3632 #define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */ 3633 #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */ 3634 #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */ 3635 3636 /* 3637 * R2852 (0xB24) - DSP2 Control 30 3638 */ 3639 #define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */ 3640 #define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */ 3641 #define WM2200_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */ 3642 #define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ 3643 #define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */ 3644 #define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */ 3645 #define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ 3646 #define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ 3647 #define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */ 3648 #define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */ 3649 #define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ 3650 #define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ 3651 #define WM2200_DSP2_START 0x0001 /* DSP2_START */ 3652 #define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */ 3653 #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */ 3654 #define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */ 3655 3656 /* 3657 * R2854 (0xB26) - DSP2 Control 31 3658 */ 3659 #define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */ 3660 #define WM2200_DSP2_CLK_RATE_SHIFT 3 /* DSP2_CLK_RATE - [4:3] */ 3661 #define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */ 3662 #define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */ 3663 #define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */ 3664 #define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */ 3665 #define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */ 3666 #define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */ 3667 #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */ 3668 #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */ 3669 3670 #endif 3671