1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm0010.c -- WM0010 DSP Driver 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * 7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 9 * Scott Ling <sl@opensource.wolfsonmicro.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqreturn.h> 16 #include <linux/init.h> 17 #include <linux/spi/spi.h> 18 #include <linux/firmware.h> 19 #include <linux/delay.h> 20 #include <linux/fs.h> 21 #include <linux/gpio.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/mutex.h> 24 #include <linux/workqueue.h> 25 26 #include <sound/soc.h> 27 #include <sound/wm0010.h> 28 29 #define DEVICE_ID_WM0010 10 30 31 /* We only support v1 of the .dfw INFO record */ 32 #define INFO_VERSION 1 33 34 enum dfw_cmd { 35 DFW_CMD_FUSE = 0x01, 36 DFW_CMD_CODE_HDR, 37 DFW_CMD_CODE_DATA, 38 DFW_CMD_PLL, 39 DFW_CMD_INFO = 0xff 40 }; 41 42 struct dfw_binrec { 43 u8 command; 44 u32 length:24; 45 u32 address; 46 uint8_t data[]; 47 } __packed; 48 49 struct dfw_inforec { 50 u8 info_version; 51 u8 tool_major_version; 52 u8 tool_minor_version; 53 u8 dsp_target; 54 }; 55 56 struct dfw_pllrec { 57 u8 command; 58 u32 length:24; 59 u32 address; 60 u32 clkctrl1; 61 u32 clkctrl2; 62 u32 clkctrl3; 63 u32 ldetctrl; 64 u32 uart_div; 65 u32 spi_div; 66 } __packed; 67 68 static struct pll_clock_map { 69 int max_sysclk; 70 int max_pll_spi_speed; 71 u32 pll_clkctrl1; 72 } pll_clock_map[] = { /* Dividers */ 73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 79 }; 80 81 enum wm0010_state { 82 WM0010_POWER_OFF, 83 WM0010_OUT_OF_RESET, 84 WM0010_BOOTROM, 85 WM0010_STAGE2, 86 WM0010_FIRMWARE, 87 }; 88 89 struct wm0010_priv { 90 struct snd_soc_component *component; 91 92 struct mutex lock; 93 struct device *dev; 94 95 struct wm0010_pdata pdata; 96 97 int gpio_reset; 98 int gpio_reset_value; 99 100 struct regulator_bulk_data core_supplies[2]; 101 struct regulator *dbvdd; 102 103 int sysclk; 104 105 enum wm0010_state state; 106 bool boot_failed; 107 bool ready; 108 bool pll_running; 109 int max_spi_freq; 110 int board_max_spi_speed; 111 u32 pll_clkctrl1; 112 113 spinlock_t irq_lock; 114 int irq; 115 116 struct completion boot_completion; 117 }; 118 119 struct wm0010_spi_msg { 120 struct spi_message m; 121 struct spi_transfer t; 122 u8 *tx_buf; 123 u8 *rx_buf; 124 size_t len; 125 }; 126 127 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 128 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 129 }; 130 131 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 132 { "SDI2 Capture", NULL, "SDI1 Playback" }, 133 { "SDI1 Capture", NULL, "SDI2 Playback" }, 134 135 { "SDI1 Capture", NULL, "CLKIN" }, 136 { "SDI2 Capture", NULL, "CLKIN" }, 137 { "SDI1 Playback", NULL, "CLKIN" }, 138 { "SDI2 Playback", NULL, "CLKIN" }, 139 }; 140 141 static const char *wm0010_state_to_str(enum wm0010_state state) 142 { 143 static const char * const state_to_str[] = { 144 "Power off", 145 "Out of reset", 146 "Boot ROM", 147 "Stage2", 148 "Firmware" 149 }; 150 151 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 152 return "null"; 153 return state_to_str[state]; 154 } 155 156 /* Called with wm0010->lock held */ 157 static void wm0010_halt(struct snd_soc_component *component) 158 { 159 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 160 unsigned long flags; 161 enum wm0010_state state; 162 163 /* Fetch the wm0010 state */ 164 spin_lock_irqsave(&wm0010->irq_lock, flags); 165 state = wm0010->state; 166 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 167 168 switch (state) { 169 case WM0010_POWER_OFF: 170 /* If there's nothing to do, bail out */ 171 return; 172 case WM0010_OUT_OF_RESET: 173 case WM0010_BOOTROM: 174 case WM0010_STAGE2: 175 case WM0010_FIRMWARE: 176 /* Remember to put chip back into reset */ 177 gpio_set_value_cansleep(wm0010->gpio_reset, 178 wm0010->gpio_reset_value); 179 /* Disable the regulators */ 180 regulator_disable(wm0010->dbvdd); 181 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 182 wm0010->core_supplies); 183 break; 184 } 185 186 spin_lock_irqsave(&wm0010->irq_lock, flags); 187 wm0010->state = WM0010_POWER_OFF; 188 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 189 } 190 191 struct wm0010_boot_xfer { 192 struct list_head list; 193 struct snd_soc_component *component; 194 struct completion *done; 195 struct spi_message m; 196 struct spi_transfer t; 197 }; 198 199 /* Called with wm0010->lock held */ 200 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 201 { 202 enum wm0010_state state; 203 unsigned long flags; 204 205 spin_lock_irqsave(&wm0010->irq_lock, flags); 206 state = wm0010->state; 207 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 208 209 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 210 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 211 212 wm0010->boot_failed = true; 213 } 214 215 static void wm0010_boot_xfer_complete(void *data) 216 { 217 struct wm0010_boot_xfer *xfer = data; 218 struct snd_soc_component *component = xfer->component; 219 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 220 u32 *out32 = xfer->t.rx_buf; 221 int i; 222 223 if (xfer->m.status != 0) { 224 dev_err(component->dev, "SPI transfer failed: %d\n", 225 xfer->m.status); 226 wm0010_mark_boot_failure(wm0010); 227 if (xfer->done) 228 complete(xfer->done); 229 return; 230 } 231 232 for (i = 0; i < xfer->t.len / 4; i++) { 233 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); 234 235 switch (be32_to_cpu(out32[i])) { 236 case 0xe0e0e0e0: 237 dev_err(component->dev, 238 "%d: ROM error reported in stage 2\n", i); 239 wm0010_mark_boot_failure(wm0010); 240 break; 241 242 case 0x55555555: 243 if (wm0010->state < WM0010_STAGE2) 244 break; 245 dev_err(component->dev, 246 "%d: ROM bootloader running in stage 2\n", i); 247 wm0010_mark_boot_failure(wm0010); 248 break; 249 250 case 0x0fed0000: 251 dev_dbg(component->dev, "Stage2 loader running\n"); 252 break; 253 254 case 0x0fed0007: 255 dev_dbg(component->dev, "CODE_HDR packet received\n"); 256 break; 257 258 case 0x0fed0008: 259 dev_dbg(component->dev, "CODE_DATA packet received\n"); 260 break; 261 262 case 0x0fed0009: 263 dev_dbg(component->dev, "Download complete\n"); 264 break; 265 266 case 0x0fed000c: 267 dev_dbg(component->dev, "Application start\n"); 268 break; 269 270 case 0x0fed000e: 271 dev_dbg(component->dev, "PLL packet received\n"); 272 wm0010->pll_running = true; 273 break; 274 275 case 0x0fed0025: 276 dev_err(component->dev, "Device reports image too long\n"); 277 wm0010_mark_boot_failure(wm0010); 278 break; 279 280 case 0x0fed002c: 281 dev_err(component->dev, "Device reports bad SPI packet\n"); 282 wm0010_mark_boot_failure(wm0010); 283 break; 284 285 case 0x0fed0031: 286 dev_err(component->dev, "Device reports SPI read overflow\n"); 287 wm0010_mark_boot_failure(wm0010); 288 break; 289 290 case 0x0fed0032: 291 dev_err(component->dev, "Device reports SPI underclock\n"); 292 wm0010_mark_boot_failure(wm0010); 293 break; 294 295 case 0x0fed0033: 296 dev_err(component->dev, "Device reports bad header packet\n"); 297 wm0010_mark_boot_failure(wm0010); 298 break; 299 300 case 0x0fed0034: 301 dev_err(component->dev, "Device reports invalid packet type\n"); 302 wm0010_mark_boot_failure(wm0010); 303 break; 304 305 case 0x0fed0035: 306 dev_err(component->dev, "Device reports data before header error\n"); 307 wm0010_mark_boot_failure(wm0010); 308 break; 309 310 case 0x0fed0038: 311 dev_err(component->dev, "Device reports invalid PLL packet\n"); 312 break; 313 314 case 0x0fed003a: 315 dev_err(component->dev, "Device reports packet alignment error\n"); 316 wm0010_mark_boot_failure(wm0010); 317 break; 318 319 default: 320 dev_err(component->dev, "Unrecognised return 0x%x\n", 321 be32_to_cpu(out32[i])); 322 wm0010_mark_boot_failure(wm0010); 323 break; 324 } 325 326 if (wm0010->boot_failed) 327 break; 328 } 329 330 if (xfer->done) 331 complete(xfer->done); 332 } 333 334 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 335 { 336 int i; 337 338 for (i = 0; i < len / 8; i++) 339 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 340 } 341 342 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) 343 { 344 struct spi_device *spi = to_spi_device(component->dev); 345 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 346 struct list_head xfer_list; 347 struct wm0010_boot_xfer *xfer; 348 int ret; 349 struct completion done; 350 const struct firmware *fw; 351 const struct dfw_binrec *rec; 352 const struct dfw_inforec *inforec; 353 u64 *img; 354 u8 *out, dsp; 355 u32 len, offset; 356 357 INIT_LIST_HEAD(&xfer_list); 358 359 ret = request_firmware(&fw, name, component->dev); 360 if (ret != 0) { 361 dev_err(component->dev, "Failed to request application(%s): %d\n", 362 name, ret); 363 return ret; 364 } 365 366 rec = (const struct dfw_binrec *)fw->data; 367 inforec = (const struct dfw_inforec *)rec->data; 368 offset = 0; 369 dsp = inforec->dsp_target; 370 wm0010->boot_failed = false; 371 if (WARN_ON(!list_empty(&xfer_list))) 372 return -EINVAL; 373 init_completion(&done); 374 375 /* First record should be INFO */ 376 if (rec->command != DFW_CMD_INFO) { 377 dev_err(component->dev, "First record not INFO\r\n"); 378 ret = -EINVAL; 379 goto abort; 380 } 381 382 if (inforec->info_version != INFO_VERSION) { 383 dev_err(component->dev, 384 "Unsupported version (%02d) of INFO record\r\n", 385 inforec->info_version); 386 ret = -EINVAL; 387 goto abort; 388 } 389 390 dev_dbg(component->dev, "Version v%02d INFO record found\r\n", 391 inforec->info_version); 392 393 /* Check it's a DSP file */ 394 if (dsp != DEVICE_ID_WM0010) { 395 dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); 396 ret = -EINVAL; 397 goto abort; 398 } 399 400 /* Skip the info record as we don't need to send it */ 401 offset += ((rec->length) + 8); 402 rec = (void *)&rec->data[rec->length]; 403 404 while (offset < fw->size) { 405 dev_dbg(component->dev, 406 "Packet: command %d, data length = 0x%x\r\n", 407 rec->command, rec->length); 408 len = rec->length + 8; 409 410 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 411 if (!xfer) { 412 ret = -ENOMEM; 413 goto abort; 414 } 415 416 xfer->component = component; 417 list_add_tail(&xfer->list, &xfer_list); 418 419 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 420 if (!out) { 421 ret = -ENOMEM; 422 goto abort1; 423 } 424 xfer->t.rx_buf = out; 425 426 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 427 if (!img) { 428 ret = -ENOMEM; 429 goto abort1; 430 } 431 xfer->t.tx_buf = img; 432 433 byte_swap_64((u64 *)&rec->command, img, len); 434 435 spi_message_init(&xfer->m); 436 xfer->m.complete = wm0010_boot_xfer_complete; 437 xfer->m.context = xfer; 438 xfer->t.len = len; 439 xfer->t.bits_per_word = 8; 440 441 if (!wm0010->pll_running) { 442 xfer->t.speed_hz = wm0010->sysclk / 6; 443 } else { 444 xfer->t.speed_hz = wm0010->max_spi_freq; 445 446 if (wm0010->board_max_spi_speed && 447 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 448 xfer->t.speed_hz = wm0010->board_max_spi_speed; 449 } 450 451 /* Store max usable spi frequency for later use */ 452 wm0010->max_spi_freq = xfer->t.speed_hz; 453 454 spi_message_add_tail(&xfer->t, &xfer->m); 455 456 offset += ((rec->length) + 8); 457 rec = (void *)&rec->data[rec->length]; 458 459 if (offset >= fw->size) { 460 dev_dbg(component->dev, "All transfers scheduled\n"); 461 xfer->done = &done; 462 } 463 464 ret = spi_async(spi, &xfer->m); 465 if (ret != 0) { 466 dev_err(component->dev, "Write failed: %d\n", ret); 467 goto abort1; 468 } 469 470 if (wm0010->boot_failed) { 471 dev_dbg(component->dev, "Boot fail!\n"); 472 ret = -EINVAL; 473 goto abort1; 474 } 475 } 476 477 wait_for_completion(&done); 478 479 ret = 0; 480 481 abort1: 482 while (!list_empty(&xfer_list)) { 483 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 484 list); 485 kfree(xfer->t.rx_buf); 486 kfree(xfer->t.tx_buf); 487 list_del(&xfer->list); 488 kfree(xfer); 489 } 490 491 abort: 492 release_firmware(fw); 493 return ret; 494 } 495 496 static int wm0010_stage2_load(struct snd_soc_component *component) 497 { 498 struct spi_device *spi = to_spi_device(component->dev); 499 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 500 const struct firmware *fw; 501 struct spi_message m; 502 struct spi_transfer t; 503 u32 *img; 504 u8 *out; 505 int i; 506 int ret = 0; 507 508 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); 509 if (ret != 0) { 510 dev_err(component->dev, "Failed to request stage2 loader: %d\n", 511 ret); 512 return ret; 513 } 514 515 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 516 517 /* Copy to local buffer first as vmalloc causes problems for dma */ 518 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); 519 if (!img) { 520 ret = -ENOMEM; 521 goto abort2; 522 } 523 524 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 525 if (!out) { 526 ret = -ENOMEM; 527 goto abort1; 528 } 529 530 spi_message_init(&m); 531 memset(&t, 0, sizeof(t)); 532 t.rx_buf = out; 533 t.tx_buf = img; 534 t.len = fw->size; 535 t.bits_per_word = 8; 536 t.speed_hz = wm0010->sysclk / 10; 537 spi_message_add_tail(&t, &m); 538 539 dev_dbg(component->dev, "Starting initial download at %dHz\n", 540 t.speed_hz); 541 542 ret = spi_sync(spi, &m); 543 if (ret != 0) { 544 dev_err(component->dev, "Initial download failed: %d\n", ret); 545 goto abort; 546 } 547 548 /* Look for errors from the boot ROM */ 549 for (i = 0; i < fw->size; i++) { 550 if (out[i] != 0x55) { 551 dev_err(component->dev, "Boot ROM error: %x in %d\n", 552 out[i], i); 553 wm0010_mark_boot_failure(wm0010); 554 ret = -EBUSY; 555 goto abort; 556 } 557 } 558 abort: 559 kfree(out); 560 abort1: 561 kfree(img); 562 abort2: 563 release_firmware(fw); 564 565 return ret; 566 } 567 568 static int wm0010_boot(struct snd_soc_component *component) 569 { 570 struct spi_device *spi = to_spi_device(component->dev); 571 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 572 unsigned long flags; 573 int ret; 574 struct spi_message m; 575 struct spi_transfer t; 576 struct dfw_pllrec pll_rec; 577 u32 *p, len; 578 u64 *img_swap; 579 u8 *out; 580 int i; 581 582 spin_lock_irqsave(&wm0010->irq_lock, flags); 583 if (wm0010->state != WM0010_POWER_OFF) 584 dev_warn(wm0010->dev, "DSP already powered up!\n"); 585 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 586 587 if (wm0010->sysclk > 26000000) { 588 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); 589 ret = -ECANCELED; 590 goto err; 591 } 592 593 mutex_lock(&wm0010->lock); 594 wm0010->pll_running = false; 595 596 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 597 598 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 599 wm0010->core_supplies); 600 if (ret != 0) { 601 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 602 ret); 603 mutex_unlock(&wm0010->lock); 604 goto err; 605 } 606 607 ret = regulator_enable(wm0010->dbvdd); 608 if (ret != 0) { 609 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 610 goto err_core; 611 } 612 613 /* Release reset */ 614 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); 615 spin_lock_irqsave(&wm0010->irq_lock, flags); 616 wm0010->state = WM0010_OUT_OF_RESET; 617 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 618 619 if (!wait_for_completion_timeout(&wm0010->boot_completion, 620 msecs_to_jiffies(20))) 621 dev_err(component->dev, "Failed to get interrupt from DSP\n"); 622 623 spin_lock_irqsave(&wm0010->irq_lock, flags); 624 wm0010->state = WM0010_BOOTROM; 625 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 626 627 ret = wm0010_stage2_load(component); 628 if (ret) 629 goto abort; 630 631 if (!wait_for_completion_timeout(&wm0010->boot_completion, 632 msecs_to_jiffies(20))) 633 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); 634 635 spin_lock_irqsave(&wm0010->irq_lock, flags); 636 wm0010->state = WM0010_STAGE2; 637 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 638 639 /* Only initialise PLL if max_spi_freq initialised */ 640 if (wm0010->max_spi_freq) { 641 642 /* Initialise a PLL record */ 643 memset(&pll_rec, 0, sizeof(pll_rec)); 644 pll_rec.command = DFW_CMD_PLL; 645 pll_rec.length = (sizeof(pll_rec) - 8); 646 647 /* On wm0010 only the CLKCTRL1 value is used */ 648 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 649 650 ret = -ENOMEM; 651 len = pll_rec.length + 8; 652 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 653 if (!out) 654 goto abort; 655 656 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 657 if (!img_swap) 658 goto abort_out; 659 660 /* We need to re-order for 0010 */ 661 byte_swap_64((u64 *)&pll_rec, img_swap, len); 662 663 spi_message_init(&m); 664 memset(&t, 0, sizeof(t)); 665 t.rx_buf = out; 666 t.tx_buf = img_swap; 667 t.len = len; 668 t.bits_per_word = 8; 669 t.speed_hz = wm0010->sysclk / 6; 670 spi_message_add_tail(&t, &m); 671 672 ret = spi_sync(spi, &m); 673 if (ret) { 674 dev_err(component->dev, "First PLL write failed: %d\n", ret); 675 goto abort_swap; 676 } 677 678 /* Use a second send of the message to get the return status */ 679 ret = spi_sync(spi, &m); 680 if (ret) { 681 dev_err(component->dev, "Second PLL write failed: %d\n", ret); 682 goto abort_swap; 683 } 684 685 p = (u32 *)out; 686 687 /* Look for PLL active code from the DSP */ 688 for (i = 0; i < len / 4; i++) { 689 if (*p == 0x0e00ed0f) { 690 dev_dbg(component->dev, "PLL packet received\n"); 691 wm0010->pll_running = true; 692 break; 693 } 694 p++; 695 } 696 697 kfree(img_swap); 698 kfree(out); 699 } else 700 dev_dbg(component->dev, "Not enabling DSP PLL."); 701 702 ret = wm0010_firmware_load("wm0010.dfw", component); 703 704 if (ret != 0) 705 goto abort; 706 707 spin_lock_irqsave(&wm0010->irq_lock, flags); 708 wm0010->state = WM0010_FIRMWARE; 709 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 710 711 mutex_unlock(&wm0010->lock); 712 713 return 0; 714 715 abort_swap: 716 kfree(img_swap); 717 abort_out: 718 kfree(out); 719 abort: 720 /* Put the chip back into reset */ 721 wm0010_halt(component); 722 mutex_unlock(&wm0010->lock); 723 return ret; 724 725 err_core: 726 mutex_unlock(&wm0010->lock); 727 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 728 wm0010->core_supplies); 729 err: 730 return ret; 731 } 732 733 static int wm0010_set_bias_level(struct snd_soc_component *component, 734 enum snd_soc_bias_level level) 735 { 736 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 737 738 switch (level) { 739 case SND_SOC_BIAS_ON: 740 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) 741 wm0010_boot(component); 742 break; 743 case SND_SOC_BIAS_PREPARE: 744 break; 745 case SND_SOC_BIAS_STANDBY: 746 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) { 747 mutex_lock(&wm0010->lock); 748 wm0010_halt(component); 749 mutex_unlock(&wm0010->lock); 750 } 751 break; 752 case SND_SOC_BIAS_OFF: 753 break; 754 } 755 756 return 0; 757 } 758 759 static int wm0010_set_sysclk(struct snd_soc_component *component, int source, 760 int clk_id, unsigned int freq, int dir) 761 { 762 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 763 unsigned int i; 764 765 wm0010->sysclk = freq; 766 767 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 768 wm0010->max_spi_freq = 0; 769 } else { 770 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 771 if (freq >= pll_clock_map[i].max_sysclk) { 772 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 773 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 774 break; 775 } 776 } 777 778 return 0; 779 } 780 781 static int wm0010_probe(struct snd_soc_component *component); 782 783 static const struct snd_soc_component_driver soc_component_dev_wm0010 = { 784 .probe = wm0010_probe, 785 .set_bias_level = wm0010_set_bias_level, 786 .set_sysclk = wm0010_set_sysclk, 787 .dapm_widgets = wm0010_dapm_widgets, 788 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 789 .dapm_routes = wm0010_dapm_routes, 790 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 791 .use_pmdown_time = 1, 792 .endianness = 1, 793 .non_legacy_dai_naming = 1, 794 }; 795 796 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 797 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 798 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 799 SNDRV_PCM_FMTBIT_S32_LE) 800 801 static struct snd_soc_dai_driver wm0010_dai[] = { 802 { 803 .name = "wm0010-sdi1", 804 .playback = { 805 .stream_name = "SDI1 Playback", 806 .channels_min = 1, 807 .channels_max = 2, 808 .rates = WM0010_RATES, 809 .formats = WM0010_FORMATS, 810 }, 811 .capture = { 812 .stream_name = "SDI1 Capture", 813 .channels_min = 1, 814 .channels_max = 2, 815 .rates = WM0010_RATES, 816 .formats = WM0010_FORMATS, 817 }, 818 }, 819 { 820 .name = "wm0010-sdi2", 821 .playback = { 822 .stream_name = "SDI2 Playback", 823 .channels_min = 1, 824 .channels_max = 2, 825 .rates = WM0010_RATES, 826 .formats = WM0010_FORMATS, 827 }, 828 .capture = { 829 .stream_name = "SDI2 Capture", 830 .channels_min = 1, 831 .channels_max = 2, 832 .rates = WM0010_RATES, 833 .formats = WM0010_FORMATS, 834 }, 835 }, 836 }; 837 838 static irqreturn_t wm0010_irq(int irq, void *data) 839 { 840 struct wm0010_priv *wm0010 = data; 841 842 switch (wm0010->state) { 843 case WM0010_OUT_OF_RESET: 844 case WM0010_BOOTROM: 845 case WM0010_STAGE2: 846 spin_lock(&wm0010->irq_lock); 847 complete(&wm0010->boot_completion); 848 spin_unlock(&wm0010->irq_lock); 849 return IRQ_HANDLED; 850 default: 851 return IRQ_NONE; 852 } 853 854 return IRQ_NONE; 855 } 856 857 static int wm0010_probe(struct snd_soc_component *component) 858 { 859 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 860 861 wm0010->component = component; 862 863 return 0; 864 } 865 866 static int wm0010_spi_probe(struct spi_device *spi) 867 { 868 unsigned long gpio_flags; 869 int ret; 870 int trigger; 871 int irq; 872 struct wm0010_priv *wm0010; 873 874 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 875 GFP_KERNEL); 876 if (!wm0010) 877 return -ENOMEM; 878 879 mutex_init(&wm0010->lock); 880 spin_lock_init(&wm0010->irq_lock); 881 882 spi_set_drvdata(spi, wm0010); 883 wm0010->dev = &spi->dev; 884 885 if (dev_get_platdata(&spi->dev)) 886 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 887 sizeof(wm0010->pdata)); 888 889 init_completion(&wm0010->boot_completion); 890 891 wm0010->core_supplies[0].supply = "AVDD"; 892 wm0010->core_supplies[1].supply = "DCVDD"; 893 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 894 wm0010->core_supplies); 895 if (ret != 0) { 896 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 897 ret); 898 return ret; 899 } 900 901 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 902 if (IS_ERR(wm0010->dbvdd)) { 903 ret = PTR_ERR(wm0010->dbvdd); 904 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 905 return ret; 906 } 907 908 if (wm0010->pdata.gpio_reset) { 909 wm0010->gpio_reset = wm0010->pdata.gpio_reset; 910 911 if (wm0010->pdata.reset_active_high) 912 wm0010->gpio_reset_value = 1; 913 else 914 wm0010->gpio_reset_value = 0; 915 916 if (wm0010->gpio_reset_value) 917 gpio_flags = GPIOF_OUT_INIT_HIGH; 918 else 919 gpio_flags = GPIOF_OUT_INIT_LOW; 920 921 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, 922 gpio_flags, "wm0010 reset"); 923 if (ret < 0) { 924 dev_err(wm0010->dev, 925 "Failed to request GPIO for DSP reset: %d\n", 926 ret); 927 return ret; 928 } 929 } else { 930 dev_err(wm0010->dev, "No reset GPIO configured\n"); 931 return -EINVAL; 932 } 933 934 wm0010->state = WM0010_POWER_OFF; 935 936 irq = spi->irq; 937 if (wm0010->pdata.irq_flags) 938 trigger = wm0010->pdata.irq_flags; 939 else 940 trigger = IRQF_TRIGGER_FALLING; 941 trigger |= IRQF_ONESHOT; 942 943 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 944 "wm0010", wm0010); 945 if (ret) { 946 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 947 irq, ret); 948 return ret; 949 } 950 wm0010->irq = irq; 951 952 ret = irq_set_irq_wake(irq, 1); 953 if (ret) { 954 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 955 irq, ret); 956 return ret; 957 } 958 959 if (spi->max_speed_hz) 960 wm0010->board_max_spi_speed = spi->max_speed_hz; 961 else 962 wm0010->board_max_spi_speed = 0; 963 964 ret = devm_snd_soc_register_component(&spi->dev, 965 &soc_component_dev_wm0010, wm0010_dai, 966 ARRAY_SIZE(wm0010_dai)); 967 if (ret < 0) 968 return ret; 969 970 return 0; 971 } 972 973 static int wm0010_spi_remove(struct spi_device *spi) 974 { 975 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 976 977 gpio_set_value_cansleep(wm0010->gpio_reset, 978 wm0010->gpio_reset_value); 979 980 irq_set_irq_wake(wm0010->irq, 0); 981 982 if (wm0010->irq) 983 free_irq(wm0010->irq, wm0010); 984 985 return 0; 986 } 987 988 static struct spi_driver wm0010_spi_driver = { 989 .driver = { 990 .name = "wm0010", 991 }, 992 .probe = wm0010_spi_probe, 993 .remove = wm0010_spi_remove, 994 }; 995 996 module_spi_driver(wm0010_spi_driver); 997 998 MODULE_DESCRIPTION("ASoC WM0010 driver"); 999 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1000 MODULE_LICENSE("GPL"); 1001