xref: /openbmc/linux/sound/soc/codecs/wm0010.c (revision e2f1cf25)
1 /*
2  * wm0010.c  --  WM0010 DSP Driver
3  *
4  * Copyright 2012 Wolfson Microelectronics PLC.
5  *
6  * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *          Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8  *          Scott Ling <sl@opensource.wolfsonmicro.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqreturn.h>
19 #include <linux/init.h>
20 #include <linux/spi/spi.h>
21 #include <linux/firmware.h>
22 #include <linux/delay.h>
23 #include <linux/fs.h>
24 #include <linux/miscdevice.h>
25 #include <linux/gpio.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/mutex.h>
28 #include <linux/workqueue.h>
29 
30 #include <sound/soc.h>
31 #include <sound/wm0010.h>
32 
33 #define DEVICE_ID_WM0010	10
34 
35 /* We only support v1 of the .dfw INFO record */
36 #define INFO_VERSION		1
37 
38 enum dfw_cmd {
39 	DFW_CMD_FUSE = 0x01,
40 	DFW_CMD_CODE_HDR,
41 	DFW_CMD_CODE_DATA,
42 	DFW_CMD_PLL,
43 	DFW_CMD_INFO = 0xff
44 };
45 
46 struct dfw_binrec {
47 	u8 command;
48 	u32 length:24;
49 	u32 address;
50 	uint8_t data[0];
51 } __packed;
52 
53 struct dfw_inforec {
54 	u8 info_version;
55 	u8 tool_major_version;
56 	u8 tool_minor_version;
57 	u8 dsp_target;
58 };
59 
60 struct dfw_pllrec {
61 	u8 command;
62 	u32 length:24;
63 	u32 address;
64 	u32 clkctrl1;
65 	u32 clkctrl2;
66 	u32 clkctrl3;
67 	u32 ldetctrl;
68 	u32 uart_div;
69 	u32 spi_div;
70 } __packed;
71 
72 static struct pll_clock_map {
73 	int max_sysclk;
74 	int max_pll_spi_speed;
75 	u32 pll_clkctrl1;
76 } pll_clock_map[] = {			   /* Dividers */
77 	{ 22000000, 26000000, 0x00201f11 }, /* 2,32,2  */
78 	{ 18000000, 26000000, 0x00203f21 }, /* 2,64,4  */
79 	{ 14000000, 26000000, 0x00202620 }, /* 1,39,4  */
80 	{ 10000000, 22000000, 0x00203120 }, /* 1,50,4  */
81 	{  6500000, 22000000, 0x00204520 }, /* 1,70,4  */
82 	{  5500000, 22000000, 0x00103f10 }, /* 1,64,2  */
83 };
84 
85 enum wm0010_state {
86 	WM0010_POWER_OFF,
87 	WM0010_OUT_OF_RESET,
88 	WM0010_BOOTROM,
89 	WM0010_STAGE2,
90 	WM0010_FIRMWARE,
91 };
92 
93 struct wm0010_priv {
94 	struct snd_soc_codec *codec;
95 
96 	struct mutex lock;
97 	struct device *dev;
98 
99 	struct wm0010_pdata pdata;
100 
101 	int gpio_reset;
102 	int gpio_reset_value;
103 
104 	struct regulator_bulk_data core_supplies[2];
105 	struct regulator *dbvdd;
106 
107 	int sysclk;
108 
109 	enum wm0010_state state;
110 	bool boot_failed;
111 	bool ready;
112 	bool pll_running;
113 	int max_spi_freq;
114 	int board_max_spi_speed;
115 	u32 pll_clkctrl1;
116 
117 	spinlock_t irq_lock;
118 	int irq;
119 
120 	struct completion boot_completion;
121 };
122 
123 struct wm0010_spi_msg {
124 	struct spi_message m;
125 	struct spi_transfer t;
126 	u8 *tx_buf;
127 	u8 *rx_buf;
128 	size_t len;
129 };
130 
131 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
132 SND_SOC_DAPM_SUPPLY("CLKIN",  SND_SOC_NOPM, 0, 0, NULL, 0),
133 };
134 
135 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
136 	{ "SDI2 Capture", NULL, "SDI1 Playback" },
137 	{ "SDI1 Capture", NULL, "SDI2 Playback" },
138 
139 	{ "SDI1 Capture", NULL, "CLKIN" },
140 	{ "SDI2 Capture", NULL, "CLKIN" },
141 	{ "SDI1 Playback", NULL, "CLKIN" },
142 	{ "SDI2 Playback", NULL, "CLKIN" },
143 };
144 
145 static const char *wm0010_state_to_str(enum wm0010_state state)
146 {
147 	static const char * const state_to_str[] = {
148 		"Power off",
149 		"Out of reset",
150 		"Boot ROM",
151 		"Stage2",
152 		"Firmware"
153 	};
154 
155 	if (state < 0 || state >= ARRAY_SIZE(state_to_str))
156 		return "null";
157 	return state_to_str[state];
158 }
159 
160 /* Called with wm0010->lock held */
161 static void wm0010_halt(struct snd_soc_codec *codec)
162 {
163 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
164 	unsigned long flags;
165 	enum wm0010_state state;
166 
167 	/* Fetch the wm0010 state */
168 	spin_lock_irqsave(&wm0010->irq_lock, flags);
169 	state = wm0010->state;
170 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
171 
172 	switch (state) {
173 	case WM0010_POWER_OFF:
174 		/* If there's nothing to do, bail out */
175 		return;
176 	case WM0010_OUT_OF_RESET:
177 	case WM0010_BOOTROM:
178 	case WM0010_STAGE2:
179 	case WM0010_FIRMWARE:
180 		/* Remember to put chip back into reset */
181 		gpio_set_value_cansleep(wm0010->gpio_reset,
182 					wm0010->gpio_reset_value);
183 		/* Disable the regulators */
184 		regulator_disable(wm0010->dbvdd);
185 		regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
186 				       wm0010->core_supplies);
187 		break;
188 	}
189 
190 	spin_lock_irqsave(&wm0010->irq_lock, flags);
191 	wm0010->state = WM0010_POWER_OFF;
192 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
193 }
194 
195 struct wm0010_boot_xfer {
196 	struct list_head list;
197 	struct snd_soc_codec *codec;
198 	struct completion *done;
199 	struct spi_message m;
200 	struct spi_transfer t;
201 };
202 
203 /* Called with wm0010->lock held */
204 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
205 {
206 	enum wm0010_state state;
207 	unsigned long flags;
208 
209 	spin_lock_irqsave(&wm0010->irq_lock, flags);
210 	state = wm0010->state;
211 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
212 
213 	dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
214 		wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
215 
216 	wm0010->boot_failed = true;
217 }
218 
219 static void wm0010_boot_xfer_complete(void *data)
220 {
221 	struct wm0010_boot_xfer *xfer = data;
222 	struct snd_soc_codec *codec = xfer->codec;
223 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
224 	u32 *out32 = xfer->t.rx_buf;
225 	int i;
226 
227 	if (xfer->m.status != 0) {
228 		dev_err(codec->dev, "SPI transfer failed: %d\n",
229 			xfer->m.status);
230 		wm0010_mark_boot_failure(wm0010);
231 		if (xfer->done)
232 			complete(xfer->done);
233 		return;
234 	}
235 
236 	for (i = 0; i < xfer->t.len / 4; i++) {
237 		dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
238 
239 		switch (be32_to_cpu(out32[i])) {
240 		case 0xe0e0e0e0:
241 			dev_err(codec->dev,
242 				"%d: ROM error reported in stage 2\n", i);
243 			wm0010_mark_boot_failure(wm0010);
244 			break;
245 
246 		case 0x55555555:
247 			if (wm0010->state < WM0010_STAGE2)
248 				break;
249 			dev_err(codec->dev,
250 				"%d: ROM bootloader running in stage 2\n", i);
251 			wm0010_mark_boot_failure(wm0010);
252 			break;
253 
254 		case 0x0fed0000:
255 			dev_dbg(codec->dev, "Stage2 loader running\n");
256 			break;
257 
258 		case 0x0fed0007:
259 			dev_dbg(codec->dev, "CODE_HDR packet received\n");
260 			break;
261 
262 		case 0x0fed0008:
263 			dev_dbg(codec->dev, "CODE_DATA packet received\n");
264 			break;
265 
266 		case 0x0fed0009:
267 			dev_dbg(codec->dev, "Download complete\n");
268 			break;
269 
270 		case 0x0fed000c:
271 			dev_dbg(codec->dev, "Application start\n");
272 			break;
273 
274 		case 0x0fed000e:
275 			dev_dbg(codec->dev, "PLL packet received\n");
276 			wm0010->pll_running = true;
277 			break;
278 
279 		case 0x0fed0025:
280 			dev_err(codec->dev, "Device reports image too long\n");
281 			wm0010_mark_boot_failure(wm0010);
282 			break;
283 
284 		case 0x0fed002c:
285 			dev_err(codec->dev, "Device reports bad SPI packet\n");
286 			wm0010_mark_boot_failure(wm0010);
287 			break;
288 
289 		case 0x0fed0031:
290 			dev_err(codec->dev, "Device reports SPI read overflow\n");
291 			wm0010_mark_boot_failure(wm0010);
292 			break;
293 
294 		case 0x0fed0032:
295 			dev_err(codec->dev, "Device reports SPI underclock\n");
296 			wm0010_mark_boot_failure(wm0010);
297 			break;
298 
299 		case 0x0fed0033:
300 			dev_err(codec->dev, "Device reports bad header packet\n");
301 			wm0010_mark_boot_failure(wm0010);
302 			break;
303 
304 		case 0x0fed0034:
305 			dev_err(codec->dev, "Device reports invalid packet type\n");
306 			wm0010_mark_boot_failure(wm0010);
307 			break;
308 
309 		case 0x0fed0035:
310 			dev_err(codec->dev, "Device reports data before header error\n");
311 			wm0010_mark_boot_failure(wm0010);
312 			break;
313 
314 		case 0x0fed0038:
315 			dev_err(codec->dev, "Device reports invalid PLL packet\n");
316 			break;
317 
318 		case 0x0fed003a:
319 			dev_err(codec->dev, "Device reports packet alignment error\n");
320 			wm0010_mark_boot_failure(wm0010);
321 			break;
322 
323 		default:
324 			dev_err(codec->dev, "Unrecognised return 0x%x\n",
325 			    be32_to_cpu(out32[i]));
326 			wm0010_mark_boot_failure(wm0010);
327 			break;
328 		}
329 
330 		if (wm0010->boot_failed)
331 			break;
332 	}
333 
334 	if (xfer->done)
335 		complete(xfer->done);
336 }
337 
338 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
339 {
340 	int i;
341 
342 	for (i = 0; i < len / 8; i++)
343 		data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
344 }
345 
346 static int wm0010_firmware_load(const char *name, struct snd_soc_codec *codec)
347 {
348 	struct spi_device *spi = to_spi_device(codec->dev);
349 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
350 	struct list_head xfer_list;
351 	struct wm0010_boot_xfer *xfer;
352 	int ret;
353 	struct completion done;
354 	const struct firmware *fw;
355 	const struct dfw_binrec *rec;
356 	const struct dfw_inforec *inforec;
357 	u64 *img;
358 	u8 *out, dsp;
359 	u32 len, offset;
360 
361 	INIT_LIST_HEAD(&xfer_list);
362 
363 	ret = request_firmware(&fw, name, codec->dev);
364 	if (ret != 0) {
365 		dev_err(codec->dev, "Failed to request application(%s): %d\n",
366 			name, ret);
367 		return ret;
368 	}
369 
370 	rec = (const struct dfw_binrec *)fw->data;
371 	inforec = (const struct dfw_inforec *)rec->data;
372 	offset = 0;
373 	dsp = inforec->dsp_target;
374 	wm0010->boot_failed = false;
375 	if (WARN_ON(!list_empty(&xfer_list)))
376 		return -EINVAL;
377 	init_completion(&done);
378 
379 	/* First record should be INFO */
380 	if (rec->command != DFW_CMD_INFO) {
381 		dev_err(codec->dev, "First record not INFO\r\n");
382 		ret = -EINVAL;
383 		goto abort;
384 	}
385 
386 	if (inforec->info_version != INFO_VERSION) {
387 		dev_err(codec->dev,
388 			"Unsupported version (%02d) of INFO record\r\n",
389 			inforec->info_version);
390 		ret = -EINVAL;
391 		goto abort;
392 	}
393 
394 	dev_dbg(codec->dev, "Version v%02d INFO record found\r\n",
395 		inforec->info_version);
396 
397 	/* Check it's a DSP file */
398 	if (dsp != DEVICE_ID_WM0010) {
399 		dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
400 		ret = -EINVAL;
401 		goto abort;
402 	}
403 
404 	/* Skip the info record as we don't need to send it */
405 	offset += ((rec->length) + 8);
406 	rec = (void *)&rec->data[rec->length];
407 
408 	while (offset < fw->size) {
409 		dev_dbg(codec->dev,
410 			"Packet: command %d, data length = 0x%x\r\n",
411 			rec->command, rec->length);
412 		len = rec->length + 8;
413 
414 		xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
415 		if (!xfer) {
416 			ret = -ENOMEM;
417 			goto abort;
418 		}
419 
420 		xfer->codec = codec;
421 		list_add_tail(&xfer->list, &xfer_list);
422 
423 		out = kzalloc(len, GFP_KERNEL | GFP_DMA);
424 		if (!out) {
425 			ret = -ENOMEM;
426 			goto abort1;
427 		}
428 		xfer->t.rx_buf = out;
429 
430 		img = kzalloc(len, GFP_KERNEL | GFP_DMA);
431 		if (!img) {
432 			ret = -ENOMEM;
433 			goto abort1;
434 		}
435 		xfer->t.tx_buf = img;
436 
437 		byte_swap_64((u64 *)&rec->command, img, len);
438 
439 		spi_message_init(&xfer->m);
440 		xfer->m.complete = wm0010_boot_xfer_complete;
441 		xfer->m.context = xfer;
442 		xfer->t.len = len;
443 		xfer->t.bits_per_word = 8;
444 
445 		if (!wm0010->pll_running) {
446 			xfer->t.speed_hz = wm0010->sysclk / 6;
447 		} else {
448 			xfer->t.speed_hz = wm0010->max_spi_freq;
449 
450 			if (wm0010->board_max_spi_speed &&
451 			   (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
452 					xfer->t.speed_hz = wm0010->board_max_spi_speed;
453 		}
454 
455 		/* Store max usable spi frequency for later use */
456 		wm0010->max_spi_freq = xfer->t.speed_hz;
457 
458 		spi_message_add_tail(&xfer->t, &xfer->m);
459 
460 		offset += ((rec->length) + 8);
461 		rec = (void *)&rec->data[rec->length];
462 
463 		if (offset >= fw->size) {
464 			dev_dbg(codec->dev, "All transfers scheduled\n");
465 			xfer->done = &done;
466 		}
467 
468 		ret = spi_async(spi, &xfer->m);
469 		if (ret != 0) {
470 			dev_err(codec->dev, "Write failed: %d\n", ret);
471 			goto abort1;
472 		}
473 
474 		if (wm0010->boot_failed) {
475 			dev_dbg(codec->dev, "Boot fail!\n");
476 			ret = -EINVAL;
477 			goto abort1;
478 		}
479 	}
480 
481 	wait_for_completion(&done);
482 
483 	ret = 0;
484 
485 abort1:
486 	while (!list_empty(&xfer_list)) {
487 		xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
488 					list);
489 		kfree(xfer->t.rx_buf);
490 		kfree(xfer->t.tx_buf);
491 		list_del(&xfer->list);
492 		kfree(xfer);
493 	}
494 
495 abort:
496 	release_firmware(fw);
497 	return ret;
498 }
499 
500 static int wm0010_stage2_load(struct snd_soc_codec *codec)
501 {
502 	struct spi_device *spi = to_spi_device(codec->dev);
503 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
504 	const struct firmware *fw;
505 	struct spi_message m;
506 	struct spi_transfer t;
507 	u32 *img;
508 	u8 *out;
509 	int i;
510 	int ret = 0;
511 
512 	ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
513 	if (ret != 0) {
514 		dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
515 			ret);
516 		return ret;
517 	}
518 
519 	dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
520 
521 	/* Copy to local buffer first as vmalloc causes problems for dma */
522 	img = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
523 	if (!img) {
524 		ret = -ENOMEM;
525 		goto abort2;
526 	}
527 
528 	out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
529 	if (!out) {
530 		ret = -ENOMEM;
531 		goto abort1;
532 	}
533 
534 	memcpy(img, &fw->data[0], fw->size);
535 
536 	spi_message_init(&m);
537 	memset(&t, 0, sizeof(t));
538 	t.rx_buf = out;
539 	t.tx_buf = img;
540 	t.len = fw->size;
541 	t.bits_per_word = 8;
542 	t.speed_hz = wm0010->sysclk / 10;
543 	spi_message_add_tail(&t, &m);
544 
545 	dev_dbg(codec->dev, "Starting initial download at %dHz\n",
546 		t.speed_hz);
547 
548 	ret = spi_sync(spi, &m);
549 	if (ret != 0) {
550 		dev_err(codec->dev, "Initial download failed: %d\n", ret);
551 		goto abort;
552 	}
553 
554 	/* Look for errors from the boot ROM */
555 	for (i = 0; i < fw->size; i++) {
556 		if (out[i] != 0x55) {
557 			dev_err(codec->dev, "Boot ROM error: %x in %d\n",
558 				out[i], i);
559 			wm0010_mark_boot_failure(wm0010);
560 			ret = -EBUSY;
561 			goto abort;
562 		}
563 	}
564 abort:
565 	kfree(out);
566 abort1:
567 	kfree(img);
568 abort2:
569 	release_firmware(fw);
570 
571 	return ret;
572 }
573 
574 static int wm0010_boot(struct snd_soc_codec *codec)
575 {
576 	struct spi_device *spi = to_spi_device(codec->dev);
577 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
578 	unsigned long flags;
579 	int ret;
580 	const struct firmware *fw;
581 	struct spi_message m;
582 	struct spi_transfer t;
583 	struct dfw_pllrec pll_rec;
584 	u32 *p, len;
585 	u64 *img_swap;
586 	u8 *out;
587 	int i;
588 
589 	spin_lock_irqsave(&wm0010->irq_lock, flags);
590 	if (wm0010->state != WM0010_POWER_OFF)
591 		dev_warn(wm0010->dev, "DSP already powered up!\n");
592 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
593 
594 	if (wm0010->sysclk > 26000000) {
595 		dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
596 		ret = -ECANCELED;
597 		goto err;
598 	}
599 
600 	mutex_lock(&wm0010->lock);
601 	wm0010->pll_running = false;
602 
603 	dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
604 
605 	ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
606 				    wm0010->core_supplies);
607 	if (ret != 0) {
608 		dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
609 			ret);
610 		mutex_unlock(&wm0010->lock);
611 		goto err;
612 	}
613 
614 	ret = regulator_enable(wm0010->dbvdd);
615 	if (ret != 0) {
616 		dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
617 		goto err_core;
618 	}
619 
620 	/* Release reset */
621 	gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
622 	spin_lock_irqsave(&wm0010->irq_lock, flags);
623 	wm0010->state = WM0010_OUT_OF_RESET;
624 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
625 
626 	/* First the bootloader */
627 	ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
628 	if (ret != 0) {
629 		dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
630 			ret);
631 		goto abort;
632 	}
633 
634 	if (!wait_for_completion_timeout(&wm0010->boot_completion,
635 					 msecs_to_jiffies(20)))
636 		dev_err(codec->dev, "Failed to get interrupt from DSP\n");
637 
638 	spin_lock_irqsave(&wm0010->irq_lock, flags);
639 	wm0010->state = WM0010_BOOTROM;
640 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
641 
642 	ret = wm0010_stage2_load(codec);
643 	if (ret)
644 		goto abort;
645 
646 	if (!wait_for_completion_timeout(&wm0010->boot_completion,
647 					 msecs_to_jiffies(20)))
648 		dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
649 
650 	spin_lock_irqsave(&wm0010->irq_lock, flags);
651 	wm0010->state = WM0010_STAGE2;
652 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
653 
654 	/* Only initialise PLL if max_spi_freq initialised */
655 	if (wm0010->max_spi_freq) {
656 
657 		/* Initialise a PLL record */
658 		memset(&pll_rec, 0, sizeof(pll_rec));
659 		pll_rec.command = DFW_CMD_PLL;
660 		pll_rec.length = (sizeof(pll_rec) - 8);
661 
662 		/* On wm0010 only the CLKCTRL1 value is used */
663 		pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
664 
665 		ret = -ENOMEM;
666 		len = pll_rec.length + 8;
667 		out = kzalloc(len, GFP_KERNEL | GFP_DMA);
668 		if (!out) {
669 			dev_err(codec->dev,
670 				"Failed to allocate RX buffer\n");
671 			goto abort;
672 		}
673 
674 		img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
675 		if (!img_swap)
676 			goto abort;
677 
678 		/* We need to re-order for 0010 */
679 		byte_swap_64((u64 *)&pll_rec, img_swap, len);
680 
681 		spi_message_init(&m);
682 		memset(&t, 0, sizeof(t));
683 		t.rx_buf = out;
684 		t.tx_buf = img_swap;
685 		t.len = len;
686 		t.bits_per_word = 8;
687 		t.speed_hz = wm0010->sysclk / 6;
688 		spi_message_add_tail(&t, &m);
689 
690 		ret = spi_sync(spi, &m);
691 		if (ret != 0) {
692 			dev_err(codec->dev, "First PLL write failed: %d\n", ret);
693 			goto abort;
694 		}
695 
696 		/* Use a second send of the message to get the return status */
697 		ret = spi_sync(spi, &m);
698 		if (ret != 0) {
699 			dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
700 			goto abort;
701 		}
702 
703 		p = (u32 *)out;
704 
705 		/* Look for PLL active code from the DSP */
706 		for (i = 0; i < len / 4; i++) {
707 			if (*p == 0x0e00ed0f) {
708 				dev_dbg(codec->dev, "PLL packet received\n");
709 				wm0010->pll_running = true;
710 				break;
711 			}
712 			p++;
713 		}
714 
715 		kfree(img_swap);
716 		kfree(out);
717 	} else
718 		dev_dbg(codec->dev, "Not enabling DSP PLL.");
719 
720 	ret = wm0010_firmware_load("wm0010.dfw", codec);
721 
722 	if (ret != 0)
723 		goto abort;
724 
725 	spin_lock_irqsave(&wm0010->irq_lock, flags);
726 	wm0010->state = WM0010_FIRMWARE;
727 	spin_unlock_irqrestore(&wm0010->irq_lock, flags);
728 
729 	mutex_unlock(&wm0010->lock);
730 
731 	return 0;
732 
733 abort:
734 	/* Put the chip back into reset */
735 	wm0010_halt(codec);
736 	mutex_unlock(&wm0010->lock);
737 	return ret;
738 
739 err_core:
740 	mutex_unlock(&wm0010->lock);
741 	regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
742 			       wm0010->core_supplies);
743 err:
744 	return ret;
745 }
746 
747 static int wm0010_set_bias_level(struct snd_soc_codec *codec,
748 				 enum snd_soc_bias_level level)
749 {
750 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
751 
752 	switch (level) {
753 	case SND_SOC_BIAS_ON:
754 		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE)
755 			wm0010_boot(codec);
756 		break;
757 	case SND_SOC_BIAS_PREPARE:
758 		break;
759 	case SND_SOC_BIAS_STANDBY:
760 		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) {
761 			mutex_lock(&wm0010->lock);
762 			wm0010_halt(codec);
763 			mutex_unlock(&wm0010->lock);
764 		}
765 		break;
766 	case SND_SOC_BIAS_OFF:
767 		break;
768 	}
769 
770 	return 0;
771 }
772 
773 static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
774 			     int clk_id, unsigned int freq, int dir)
775 {
776 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
777 	unsigned int i;
778 
779 	wm0010->sysclk = freq;
780 
781 	if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
782 		wm0010->max_spi_freq = 0;
783 	} else {
784 		for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
785 			if (freq >= pll_clock_map[i].max_sysclk) {
786 				wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
787 				wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
788 				break;
789 			}
790 	}
791 
792 	return 0;
793 }
794 
795 static int wm0010_probe(struct snd_soc_codec *codec);
796 
797 static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
798 	.probe = wm0010_probe,
799 	.set_bias_level = wm0010_set_bias_level,
800 	.set_sysclk = wm0010_set_sysclk,
801 	.idle_bias_off = true,
802 
803 	.dapm_widgets = wm0010_dapm_widgets,
804 	.num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
805 	.dapm_routes = wm0010_dapm_routes,
806 	.num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
807 };
808 
809 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
810 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
811 			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
812 			SNDRV_PCM_FMTBIT_S32_LE)
813 
814 static struct snd_soc_dai_driver wm0010_dai[] = {
815 	{
816 		.name = "wm0010-sdi1",
817 		.playback = {
818 			.stream_name = "SDI1 Playback",
819 			.channels_min = 1,
820 			.channels_max = 2,
821 			.rates = WM0010_RATES,
822 			.formats = WM0010_FORMATS,
823 		},
824 		.capture = {
825 			 .stream_name = "SDI1 Capture",
826 			 .channels_min = 1,
827 			 .channels_max = 2,
828 			 .rates = WM0010_RATES,
829 			 .formats = WM0010_FORMATS,
830 		 },
831 	},
832 	{
833 		.name = "wm0010-sdi2",
834 		.playback = {
835 			.stream_name = "SDI2 Playback",
836 			.channels_min = 1,
837 			.channels_max = 2,
838 			.rates = WM0010_RATES,
839 			.formats = WM0010_FORMATS,
840 		},
841 		.capture = {
842 			 .stream_name = "SDI2 Capture",
843 			 .channels_min = 1,
844 			 .channels_max = 2,
845 			 .rates = WM0010_RATES,
846 			 .formats = WM0010_FORMATS,
847 		 },
848 	},
849 };
850 
851 static irqreturn_t wm0010_irq(int irq, void *data)
852 {
853 	struct wm0010_priv *wm0010 = data;
854 
855 	switch (wm0010->state) {
856 	case WM0010_OUT_OF_RESET:
857 	case WM0010_BOOTROM:
858 	case WM0010_STAGE2:
859 		spin_lock(&wm0010->irq_lock);
860 		complete(&wm0010->boot_completion);
861 		spin_unlock(&wm0010->irq_lock);
862 		return IRQ_HANDLED;
863 	default:
864 		return IRQ_NONE;
865 	}
866 
867 	return IRQ_NONE;
868 }
869 
870 static int wm0010_probe(struct snd_soc_codec *codec)
871 {
872 	struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
873 
874 	wm0010->codec = codec;
875 
876 	return 0;
877 }
878 
879 static int wm0010_spi_probe(struct spi_device *spi)
880 {
881 	unsigned long gpio_flags;
882 	int ret;
883 	int trigger;
884 	int irq;
885 	struct wm0010_priv *wm0010;
886 
887 	wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
888 			      GFP_KERNEL);
889 	if (!wm0010)
890 		return -ENOMEM;
891 
892 	mutex_init(&wm0010->lock);
893 	spin_lock_init(&wm0010->irq_lock);
894 
895 	spi_set_drvdata(spi, wm0010);
896 	wm0010->dev = &spi->dev;
897 
898 	if (dev_get_platdata(&spi->dev))
899 		memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
900 		       sizeof(wm0010->pdata));
901 
902 	init_completion(&wm0010->boot_completion);
903 
904 	wm0010->core_supplies[0].supply = "AVDD";
905 	wm0010->core_supplies[1].supply = "DCVDD";
906 	ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
907 				      wm0010->core_supplies);
908 	if (ret != 0) {
909 		dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
910 			ret);
911 		return ret;
912 	}
913 
914 	wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
915 	if (IS_ERR(wm0010->dbvdd)) {
916 		ret = PTR_ERR(wm0010->dbvdd);
917 		dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
918 		return ret;
919 	}
920 
921 	if (wm0010->pdata.gpio_reset) {
922 		wm0010->gpio_reset = wm0010->pdata.gpio_reset;
923 
924 		if (wm0010->pdata.reset_active_high)
925 			wm0010->gpio_reset_value = 1;
926 		else
927 			wm0010->gpio_reset_value = 0;
928 
929 		if (wm0010->gpio_reset_value)
930 			gpio_flags = GPIOF_OUT_INIT_HIGH;
931 		else
932 			gpio_flags = GPIOF_OUT_INIT_LOW;
933 
934 		ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
935 					    gpio_flags, "wm0010 reset");
936 		if (ret < 0) {
937 			dev_err(wm0010->dev,
938 				"Failed to request GPIO for DSP reset: %d\n",
939 				ret);
940 			return ret;
941 		}
942 	} else {
943 		dev_err(wm0010->dev, "No reset GPIO configured\n");
944 		return -EINVAL;
945 	}
946 
947 	wm0010->state = WM0010_POWER_OFF;
948 
949 	irq = spi->irq;
950 	if (wm0010->pdata.irq_flags)
951 		trigger = wm0010->pdata.irq_flags;
952 	else
953 		trigger = IRQF_TRIGGER_FALLING;
954 	trigger |= IRQF_ONESHOT;
955 
956 	ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
957 				   "wm0010", wm0010);
958 	if (ret) {
959 		dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
960 			irq, ret);
961 		return ret;
962 	}
963 	wm0010->irq = irq;
964 
965 	ret = irq_set_irq_wake(irq, 1);
966 	if (ret) {
967 		dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
968 			irq, ret);
969 		return ret;
970 	}
971 
972 	if (spi->max_speed_hz)
973 		wm0010->board_max_spi_speed = spi->max_speed_hz;
974 	else
975 		wm0010->board_max_spi_speed = 0;
976 
977 	ret = snd_soc_register_codec(&spi->dev,
978 				     &soc_codec_dev_wm0010, wm0010_dai,
979 				     ARRAY_SIZE(wm0010_dai));
980 	if (ret < 0)
981 		return ret;
982 
983 	return 0;
984 }
985 
986 static int wm0010_spi_remove(struct spi_device *spi)
987 {
988 	struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
989 
990 	snd_soc_unregister_codec(&spi->dev);
991 
992 	gpio_set_value_cansleep(wm0010->gpio_reset,
993 				wm0010->gpio_reset_value);
994 
995 	irq_set_irq_wake(wm0010->irq, 0);
996 
997 	if (wm0010->irq)
998 		free_irq(wm0010->irq, wm0010);
999 
1000 	return 0;
1001 }
1002 
1003 static struct spi_driver wm0010_spi_driver = {
1004 	.driver = {
1005 		.name	= "wm0010",
1006 		.bus 	= &spi_bus_type,
1007 		.owner	= THIS_MODULE,
1008 	},
1009 	.probe		= wm0010_spi_probe,
1010 	.remove		= wm0010_spi_remove,
1011 };
1012 
1013 module_spi_driver(wm0010_spi_driver);
1014 
1015 MODULE_DESCRIPTION("ASoC WM0010 driver");
1016 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1017 MODULE_LICENSE("GPL");
1018