1 /* 2 * wm0010.c -- WM0010 DSP Driver 3 * 4 * Copyright 2012 Wolfson Microelectronics PLC. 5 * 6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 * Scott Ling <sl@opensource.wolfsonmicro.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/interrupt.h> 18 #include <linux/irqreturn.h> 19 #include <linux/init.h> 20 #include <linux/spi/spi.h> 21 #include <linux/firmware.h> 22 #include <linux/delay.h> 23 #include <linux/fs.h> 24 #include <linux/miscdevice.h> 25 #include <linux/gpio.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/mutex.h> 28 #include <linux/workqueue.h> 29 30 #include <sound/soc.h> 31 #include <sound/wm0010.h> 32 33 #define DEVICE_ID_WM0010 10 34 35 /* We only support v1 of the .dfw INFO record */ 36 #define INFO_VERSION 1 37 38 enum dfw_cmd { 39 DFW_CMD_FUSE = 0x01, 40 DFW_CMD_CODE_HDR, 41 DFW_CMD_CODE_DATA, 42 DFW_CMD_PLL, 43 DFW_CMD_INFO = 0xff 44 }; 45 46 struct dfw_binrec { 47 u8 command; 48 u32 length:24; 49 u32 address; 50 uint8_t data[0]; 51 } __packed; 52 53 struct dfw_inforec { 54 u8 info_version; 55 u8 tool_major_version; 56 u8 tool_minor_version; 57 u8 dsp_target; 58 }; 59 60 struct dfw_pllrec { 61 u8 command; 62 u32 length:24; 63 u32 address; 64 u32 clkctrl1; 65 u32 clkctrl2; 66 u32 clkctrl3; 67 u32 ldetctrl; 68 u32 uart_div; 69 u32 spi_div; 70 } __packed; 71 72 static struct pll_clock_map { 73 int max_sysclk; 74 int max_pll_spi_speed; 75 u32 pll_clkctrl1; 76 } pll_clock_map[] = { /* Dividers */ 77 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 78 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 79 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 80 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 81 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 82 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 83 }; 84 85 enum wm0010_state { 86 WM0010_POWER_OFF, 87 WM0010_OUT_OF_RESET, 88 WM0010_BOOTROM, 89 WM0010_STAGE2, 90 WM0010_FIRMWARE, 91 }; 92 93 struct wm0010_priv { 94 struct snd_soc_codec *codec; 95 96 struct mutex lock; 97 struct device *dev; 98 99 struct wm0010_pdata pdata; 100 101 int gpio_reset; 102 int gpio_reset_value; 103 104 struct regulator_bulk_data core_supplies[2]; 105 struct regulator *dbvdd; 106 107 int sysclk; 108 109 enum wm0010_state state; 110 bool boot_failed; 111 bool ready; 112 bool pll_running; 113 int max_spi_freq; 114 int board_max_spi_speed; 115 u32 pll_clkctrl1; 116 117 spinlock_t irq_lock; 118 int irq; 119 120 struct completion boot_completion; 121 }; 122 123 struct wm0010_spi_msg { 124 struct spi_message m; 125 struct spi_transfer t; 126 u8 *tx_buf; 127 u8 *rx_buf; 128 size_t len; 129 }; 130 131 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 132 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 133 }; 134 135 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 136 { "SDI2 Capture", NULL, "SDI1 Playback" }, 137 { "SDI1 Capture", NULL, "SDI2 Playback" }, 138 139 { "SDI1 Capture", NULL, "CLKIN" }, 140 { "SDI2 Capture", NULL, "CLKIN" }, 141 { "SDI1 Playback", NULL, "CLKIN" }, 142 { "SDI2 Playback", NULL, "CLKIN" }, 143 }; 144 145 static const char *wm0010_state_to_str(enum wm0010_state state) 146 { 147 const char *state_to_str[] = { 148 "Power off", 149 "Out of reset", 150 "Boot ROM", 151 "Stage2", 152 "Firmware" 153 }; 154 155 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 156 return "null"; 157 return state_to_str[state]; 158 } 159 160 /* Called with wm0010->lock held */ 161 static void wm0010_halt(struct snd_soc_codec *codec) 162 { 163 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 164 unsigned long flags; 165 enum wm0010_state state; 166 167 /* Fetch the wm0010 state */ 168 spin_lock_irqsave(&wm0010->irq_lock, flags); 169 state = wm0010->state; 170 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 171 172 switch (state) { 173 case WM0010_POWER_OFF: 174 /* If there's nothing to do, bail out */ 175 return; 176 case WM0010_OUT_OF_RESET: 177 case WM0010_BOOTROM: 178 case WM0010_STAGE2: 179 case WM0010_FIRMWARE: 180 /* Remember to put chip back into reset */ 181 gpio_set_value_cansleep(wm0010->gpio_reset, 182 wm0010->gpio_reset_value); 183 /* Disable the regulators */ 184 regulator_disable(wm0010->dbvdd); 185 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 186 wm0010->core_supplies); 187 break; 188 } 189 190 spin_lock_irqsave(&wm0010->irq_lock, flags); 191 wm0010->state = WM0010_POWER_OFF; 192 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 193 } 194 195 struct wm0010_boot_xfer { 196 struct list_head list; 197 struct snd_soc_codec *codec; 198 struct completion *done; 199 struct spi_message m; 200 struct spi_transfer t; 201 }; 202 203 /* Called with wm0010->lock held */ 204 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 205 { 206 enum wm0010_state state; 207 unsigned long flags; 208 209 spin_lock_irqsave(&wm0010->irq_lock, flags); 210 state = wm0010->state; 211 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 212 213 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 214 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 215 216 wm0010->boot_failed = true; 217 } 218 219 static void wm0010_boot_xfer_complete(void *data) 220 { 221 struct wm0010_boot_xfer *xfer = data; 222 struct snd_soc_codec *codec = xfer->codec; 223 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 224 u32 *out32 = xfer->t.rx_buf; 225 int i; 226 227 if (xfer->m.status != 0) { 228 dev_err(codec->dev, "SPI transfer failed: %d\n", 229 xfer->m.status); 230 wm0010_mark_boot_failure(wm0010); 231 if (xfer->done) 232 complete(xfer->done); 233 return; 234 } 235 236 for (i = 0; i < xfer->t.len / 4; i++) { 237 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]); 238 239 switch (be32_to_cpu(out32[i])) { 240 case 0xe0e0e0e0: 241 dev_err(codec->dev, 242 "%d: ROM error reported in stage 2\n", i); 243 wm0010_mark_boot_failure(wm0010); 244 break; 245 246 case 0x55555555: 247 if (wm0010->state < WM0010_STAGE2) 248 break; 249 dev_err(codec->dev, 250 "%d: ROM bootloader running in stage 2\n", i); 251 wm0010_mark_boot_failure(wm0010); 252 break; 253 254 case 0x0fed0000: 255 dev_dbg(codec->dev, "Stage2 loader running\n"); 256 break; 257 258 case 0x0fed0007: 259 dev_dbg(codec->dev, "CODE_HDR packet received\n"); 260 break; 261 262 case 0x0fed0008: 263 dev_dbg(codec->dev, "CODE_DATA packet received\n"); 264 break; 265 266 case 0x0fed0009: 267 dev_dbg(codec->dev, "Download complete\n"); 268 break; 269 270 case 0x0fed000c: 271 dev_dbg(codec->dev, "Application start\n"); 272 break; 273 274 case 0x0fed000e: 275 dev_dbg(codec->dev, "PLL packet received\n"); 276 wm0010->pll_running = true; 277 break; 278 279 case 0x0fed0025: 280 dev_err(codec->dev, "Device reports image too long\n"); 281 wm0010_mark_boot_failure(wm0010); 282 break; 283 284 case 0x0fed002c: 285 dev_err(codec->dev, "Device reports bad SPI packet\n"); 286 wm0010_mark_boot_failure(wm0010); 287 break; 288 289 case 0x0fed0031: 290 dev_err(codec->dev, "Device reports SPI read overflow\n"); 291 wm0010_mark_boot_failure(wm0010); 292 break; 293 294 case 0x0fed0032: 295 dev_err(codec->dev, "Device reports SPI underclock\n"); 296 wm0010_mark_boot_failure(wm0010); 297 break; 298 299 case 0x0fed0033: 300 dev_err(codec->dev, "Device reports bad header packet\n"); 301 wm0010_mark_boot_failure(wm0010); 302 break; 303 304 case 0x0fed0034: 305 dev_err(codec->dev, "Device reports invalid packet type\n"); 306 wm0010_mark_boot_failure(wm0010); 307 break; 308 309 case 0x0fed0035: 310 dev_err(codec->dev, "Device reports data before header error\n"); 311 wm0010_mark_boot_failure(wm0010); 312 break; 313 314 case 0x0fed0038: 315 dev_err(codec->dev, "Device reports invalid PLL packet\n"); 316 break; 317 318 case 0x0fed003a: 319 dev_err(codec->dev, "Device reports packet alignment error\n"); 320 wm0010_mark_boot_failure(wm0010); 321 break; 322 323 default: 324 dev_err(codec->dev, "Unrecognised return 0x%x\n", 325 be32_to_cpu(out32[i])); 326 wm0010_mark_boot_failure(wm0010); 327 break; 328 } 329 330 if (wm0010->boot_failed) 331 break; 332 } 333 334 if (xfer->done) 335 complete(xfer->done); 336 } 337 338 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 339 { 340 int i; 341 342 for (i = 0; i < len / 8; i++) 343 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 344 } 345 346 static int wm0010_firmware_load(const char *name, struct snd_soc_codec *codec) 347 { 348 struct spi_device *spi = to_spi_device(codec->dev); 349 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 350 struct list_head xfer_list; 351 struct wm0010_boot_xfer *xfer; 352 int ret; 353 struct completion done; 354 const struct firmware *fw; 355 const struct dfw_binrec *rec; 356 const struct dfw_inforec *inforec; 357 u64 *img; 358 u8 *out, dsp; 359 u32 len, offset; 360 361 INIT_LIST_HEAD(&xfer_list); 362 363 ret = request_firmware(&fw, name, codec->dev); 364 if (ret != 0) { 365 dev_err(codec->dev, "Failed to request application(%s): %d\n", 366 name, ret); 367 return ret; 368 } 369 370 rec = (const struct dfw_binrec *)fw->data; 371 inforec = (const struct dfw_inforec *)rec->data; 372 offset = 0; 373 dsp = inforec->dsp_target; 374 wm0010->boot_failed = false; 375 BUG_ON(!list_empty(&xfer_list)); 376 init_completion(&done); 377 378 /* First record should be INFO */ 379 if (rec->command != DFW_CMD_INFO) { 380 dev_err(codec->dev, "First record not INFO\r\n"); 381 ret = -EINVAL; 382 goto abort; 383 } 384 385 if (inforec->info_version != INFO_VERSION) { 386 dev_err(codec->dev, 387 "Unsupported version (%02d) of INFO record\r\n", 388 inforec->info_version); 389 ret = -EINVAL; 390 goto abort; 391 } 392 393 dev_dbg(codec->dev, "Version v%02d INFO record found\r\n", 394 inforec->info_version); 395 396 /* Check it's a DSP file */ 397 if (dsp != DEVICE_ID_WM0010) { 398 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n"); 399 ret = -EINVAL; 400 goto abort; 401 } 402 403 /* Skip the info record as we don't need to send it */ 404 offset += ((rec->length) + 8); 405 rec = (void *)&rec->data[rec->length]; 406 407 while (offset < fw->size) { 408 dev_dbg(codec->dev, 409 "Packet: command %d, data length = 0x%x\r\n", 410 rec->command, rec->length); 411 len = rec->length + 8; 412 413 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 414 if (!xfer) { 415 dev_err(codec->dev, "Failed to allocate xfer\n"); 416 ret = -ENOMEM; 417 goto abort; 418 } 419 420 xfer->codec = codec; 421 list_add_tail(&xfer->list, &xfer_list); 422 423 out = kzalloc(len, GFP_KERNEL); 424 if (!out) { 425 dev_err(codec->dev, 426 "Failed to allocate RX buffer\n"); 427 ret = -ENOMEM; 428 goto abort1; 429 } 430 xfer->t.rx_buf = out; 431 432 img = kzalloc(len, GFP_KERNEL); 433 if (!img) { 434 dev_err(codec->dev, 435 "Failed to allocate image buffer\n"); 436 ret = -ENOMEM; 437 goto abort1; 438 } 439 xfer->t.tx_buf = img; 440 441 byte_swap_64((u64 *)&rec->command, img, len); 442 443 spi_message_init(&xfer->m); 444 xfer->m.complete = wm0010_boot_xfer_complete; 445 xfer->m.context = xfer; 446 xfer->t.len = len; 447 xfer->t.bits_per_word = 8; 448 449 if (!wm0010->pll_running) { 450 xfer->t.speed_hz = wm0010->sysclk / 6; 451 } else { 452 xfer->t.speed_hz = wm0010->max_spi_freq; 453 454 if (wm0010->board_max_spi_speed && 455 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 456 xfer->t.speed_hz = wm0010->board_max_spi_speed; 457 } 458 459 /* Store max usable spi frequency for later use */ 460 wm0010->max_spi_freq = xfer->t.speed_hz; 461 462 spi_message_add_tail(&xfer->t, &xfer->m); 463 464 offset += ((rec->length) + 8); 465 rec = (void *)&rec->data[rec->length]; 466 467 if (offset >= fw->size) { 468 dev_dbg(codec->dev, "All transfers scheduled\n"); 469 xfer->done = &done; 470 } 471 472 ret = spi_async(spi, &xfer->m); 473 if (ret != 0) { 474 dev_err(codec->dev, "Write failed: %d\n", ret); 475 goto abort1; 476 } 477 478 if (wm0010->boot_failed) { 479 dev_dbg(codec->dev, "Boot fail!\n"); 480 ret = -EINVAL; 481 goto abort1; 482 } 483 } 484 485 wait_for_completion(&done); 486 487 ret = 0; 488 489 abort1: 490 while (!list_empty(&xfer_list)) { 491 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 492 list); 493 kfree(xfer->t.rx_buf); 494 kfree(xfer->t.tx_buf); 495 list_del(&xfer->list); 496 kfree(xfer); 497 } 498 499 abort: 500 release_firmware(fw); 501 return ret; 502 } 503 504 static int wm0010_stage2_load(struct snd_soc_codec *codec) 505 { 506 struct spi_device *spi = to_spi_device(codec->dev); 507 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 508 const struct firmware *fw; 509 struct spi_message m; 510 struct spi_transfer t; 511 u32 *img; 512 u8 *out; 513 int i; 514 int ret = 0; 515 516 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev); 517 if (ret != 0) { 518 dev_err(codec->dev, "Failed to request stage2 loader: %d\n", 519 ret); 520 return ret; 521 } 522 523 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 524 525 /* Copy to local buffer first as vmalloc causes problems for dma */ 526 img = kzalloc(fw->size, GFP_KERNEL); 527 if (!img) { 528 dev_err(codec->dev, "Failed to allocate image buffer\n"); 529 ret = -ENOMEM; 530 goto abort2; 531 } 532 533 out = kzalloc(fw->size, GFP_KERNEL); 534 if (!out) { 535 dev_err(codec->dev, "Failed to allocate output buffer\n"); 536 ret = -ENOMEM; 537 goto abort1; 538 } 539 540 memcpy(img, &fw->data[0], fw->size); 541 542 spi_message_init(&m); 543 memset(&t, 0, sizeof(t)); 544 t.rx_buf = out; 545 t.tx_buf = img; 546 t.len = fw->size; 547 t.bits_per_word = 8; 548 t.speed_hz = wm0010->sysclk / 10; 549 spi_message_add_tail(&t, &m); 550 551 dev_dbg(codec->dev, "Starting initial download at %dHz\n", 552 t.speed_hz); 553 554 ret = spi_sync(spi, &m); 555 if (ret != 0) { 556 dev_err(codec->dev, "Initial download failed: %d\n", ret); 557 goto abort; 558 } 559 560 /* Look for errors from the boot ROM */ 561 for (i = 0; i < fw->size; i++) { 562 if (out[i] != 0x55) { 563 dev_err(codec->dev, "Boot ROM error: %x in %d\n", 564 out[i], i); 565 wm0010_mark_boot_failure(wm0010); 566 ret = -EBUSY; 567 goto abort; 568 } 569 } 570 abort: 571 kfree(out); 572 abort1: 573 kfree(img); 574 abort2: 575 release_firmware(fw); 576 577 return ret; 578 } 579 580 static int wm0010_boot(struct snd_soc_codec *codec) 581 { 582 struct spi_device *spi = to_spi_device(codec->dev); 583 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 584 unsigned long flags; 585 int ret; 586 const struct firmware *fw; 587 struct spi_message m; 588 struct spi_transfer t; 589 struct dfw_pllrec pll_rec; 590 u32 *p, len; 591 u64 *img_swap; 592 u8 *out; 593 int i; 594 595 spin_lock_irqsave(&wm0010->irq_lock, flags); 596 if (wm0010->state != WM0010_POWER_OFF) 597 dev_warn(wm0010->dev, "DSP already powered up!\n"); 598 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 599 600 if (wm0010->sysclk > 26000000) { 601 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n"); 602 ret = -ECANCELED; 603 goto err; 604 } 605 606 mutex_lock(&wm0010->lock); 607 wm0010->pll_running = false; 608 609 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 610 611 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 612 wm0010->core_supplies); 613 if (ret != 0) { 614 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 615 ret); 616 mutex_unlock(&wm0010->lock); 617 goto err; 618 } 619 620 ret = regulator_enable(wm0010->dbvdd); 621 if (ret != 0) { 622 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 623 goto err_core; 624 } 625 626 /* Release reset */ 627 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); 628 spin_lock_irqsave(&wm0010->irq_lock, flags); 629 wm0010->state = WM0010_OUT_OF_RESET; 630 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 631 632 /* First the bootloader */ 633 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev); 634 if (ret != 0) { 635 dev_err(codec->dev, "Failed to request stage2 loader: %d\n", 636 ret); 637 goto abort; 638 } 639 640 if (!wait_for_completion_timeout(&wm0010->boot_completion, 641 msecs_to_jiffies(20))) 642 dev_err(codec->dev, "Failed to get interrupt from DSP\n"); 643 644 spin_lock_irqsave(&wm0010->irq_lock, flags); 645 wm0010->state = WM0010_BOOTROM; 646 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 647 648 ret = wm0010_stage2_load(codec); 649 if (ret) 650 goto abort; 651 652 if (!wait_for_completion_timeout(&wm0010->boot_completion, 653 msecs_to_jiffies(20))) 654 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n"); 655 656 spin_lock_irqsave(&wm0010->irq_lock, flags); 657 wm0010->state = WM0010_STAGE2; 658 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 659 660 /* Only initialise PLL if max_spi_freq initialised */ 661 if (wm0010->max_spi_freq) { 662 663 /* Initialise a PLL record */ 664 memset(&pll_rec, 0, sizeof(pll_rec)); 665 pll_rec.command = DFW_CMD_PLL; 666 pll_rec.length = (sizeof(pll_rec) - 8); 667 668 /* On wm0010 only the CLKCTRL1 value is used */ 669 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 670 671 ret = -ENOMEM; 672 len = pll_rec.length + 8; 673 out = kzalloc(len, GFP_KERNEL); 674 if (!out) { 675 dev_err(codec->dev, 676 "Failed to allocate RX buffer\n"); 677 goto abort; 678 } 679 680 img_swap = kzalloc(len, GFP_KERNEL); 681 if (!img_swap) { 682 dev_err(codec->dev, 683 "Failed to allocate image buffer\n"); 684 goto abort; 685 } 686 687 /* We need to re-order for 0010 */ 688 byte_swap_64((u64 *)&pll_rec, img_swap, len); 689 690 spi_message_init(&m); 691 memset(&t, 0, sizeof(t)); 692 t.rx_buf = out; 693 t.tx_buf = img_swap; 694 t.len = len; 695 t.bits_per_word = 8; 696 t.speed_hz = wm0010->sysclk / 6; 697 spi_message_add_tail(&t, &m); 698 699 ret = spi_sync(spi, &m); 700 if (ret != 0) { 701 dev_err(codec->dev, "First PLL write failed: %d\n", ret); 702 goto abort; 703 } 704 705 /* Use a second send of the message to get the return status */ 706 ret = spi_sync(spi, &m); 707 if (ret != 0) { 708 dev_err(codec->dev, "Second PLL write failed: %d\n", ret); 709 goto abort; 710 } 711 712 p = (u32 *)out; 713 714 /* Look for PLL active code from the DSP */ 715 for (i = 0; i < len / 4; i++) { 716 if (*p == 0x0e00ed0f) { 717 dev_dbg(codec->dev, "PLL packet received\n"); 718 wm0010->pll_running = true; 719 break; 720 } 721 p++; 722 } 723 724 kfree(img_swap); 725 kfree(out); 726 } else 727 dev_dbg(codec->dev, "Not enabling DSP PLL."); 728 729 ret = wm0010_firmware_load("wm0010.dfw", codec); 730 731 if (ret != 0) 732 goto abort; 733 734 spin_lock_irqsave(&wm0010->irq_lock, flags); 735 wm0010->state = WM0010_FIRMWARE; 736 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 737 738 mutex_unlock(&wm0010->lock); 739 740 return 0; 741 742 abort: 743 /* Put the chip back into reset */ 744 wm0010_halt(codec); 745 mutex_unlock(&wm0010->lock); 746 return ret; 747 748 err_core: 749 mutex_unlock(&wm0010->lock); 750 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 751 wm0010->core_supplies); 752 err: 753 return ret; 754 } 755 756 static int wm0010_set_bias_level(struct snd_soc_codec *codec, 757 enum snd_soc_bias_level level) 758 { 759 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 760 761 switch (level) { 762 case SND_SOC_BIAS_ON: 763 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) 764 wm0010_boot(codec); 765 break; 766 case SND_SOC_BIAS_PREPARE: 767 break; 768 case SND_SOC_BIAS_STANDBY: 769 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) { 770 mutex_lock(&wm0010->lock); 771 wm0010_halt(codec); 772 mutex_unlock(&wm0010->lock); 773 } 774 break; 775 case SND_SOC_BIAS_OFF: 776 break; 777 } 778 779 codec->dapm.bias_level = level; 780 781 return 0; 782 } 783 784 static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source, 785 int clk_id, unsigned int freq, int dir) 786 { 787 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 788 unsigned int i; 789 790 wm0010->sysclk = freq; 791 792 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 793 wm0010->max_spi_freq = 0; 794 } else { 795 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 796 if (freq >= pll_clock_map[i].max_sysclk) 797 break; 798 799 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 800 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 801 } 802 803 return 0; 804 } 805 806 static int wm0010_probe(struct snd_soc_codec *codec); 807 808 static struct snd_soc_codec_driver soc_codec_dev_wm0010 = { 809 .probe = wm0010_probe, 810 .set_bias_level = wm0010_set_bias_level, 811 .set_sysclk = wm0010_set_sysclk, 812 .idle_bias_off = true, 813 814 .dapm_widgets = wm0010_dapm_widgets, 815 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 816 .dapm_routes = wm0010_dapm_routes, 817 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 818 }; 819 820 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 821 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 822 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 823 SNDRV_PCM_FMTBIT_S32_LE) 824 825 static struct snd_soc_dai_driver wm0010_dai[] = { 826 { 827 .name = "wm0010-sdi1", 828 .playback = { 829 .stream_name = "SDI1 Playback", 830 .channels_min = 1, 831 .channels_max = 2, 832 .rates = WM0010_RATES, 833 .formats = WM0010_FORMATS, 834 }, 835 .capture = { 836 .stream_name = "SDI1 Capture", 837 .channels_min = 1, 838 .channels_max = 2, 839 .rates = WM0010_RATES, 840 .formats = WM0010_FORMATS, 841 }, 842 }, 843 { 844 .name = "wm0010-sdi2", 845 .playback = { 846 .stream_name = "SDI2 Playback", 847 .channels_min = 1, 848 .channels_max = 2, 849 .rates = WM0010_RATES, 850 .formats = WM0010_FORMATS, 851 }, 852 .capture = { 853 .stream_name = "SDI2 Capture", 854 .channels_min = 1, 855 .channels_max = 2, 856 .rates = WM0010_RATES, 857 .formats = WM0010_FORMATS, 858 }, 859 }, 860 }; 861 862 static irqreturn_t wm0010_irq(int irq, void *data) 863 { 864 struct wm0010_priv *wm0010 = data; 865 866 switch (wm0010->state) { 867 case WM0010_OUT_OF_RESET: 868 case WM0010_BOOTROM: 869 case WM0010_STAGE2: 870 spin_lock(&wm0010->irq_lock); 871 complete(&wm0010->boot_completion); 872 spin_unlock(&wm0010->irq_lock); 873 return IRQ_HANDLED; 874 default: 875 return IRQ_NONE; 876 } 877 878 return IRQ_NONE; 879 } 880 881 static int wm0010_probe(struct snd_soc_codec *codec) 882 { 883 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 884 885 wm0010->codec = codec; 886 887 return 0; 888 } 889 890 static int wm0010_spi_probe(struct spi_device *spi) 891 { 892 unsigned long gpio_flags; 893 int ret; 894 int trigger; 895 int irq; 896 struct wm0010_priv *wm0010; 897 898 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 899 GFP_KERNEL); 900 if (!wm0010) 901 return -ENOMEM; 902 903 mutex_init(&wm0010->lock); 904 spin_lock_init(&wm0010->irq_lock); 905 906 spi_set_drvdata(spi, wm0010); 907 wm0010->dev = &spi->dev; 908 909 if (dev_get_platdata(&spi->dev)) 910 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 911 sizeof(wm0010->pdata)); 912 913 init_completion(&wm0010->boot_completion); 914 915 wm0010->core_supplies[0].supply = "AVDD"; 916 wm0010->core_supplies[1].supply = "DCVDD"; 917 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 918 wm0010->core_supplies); 919 if (ret != 0) { 920 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 921 ret); 922 return ret; 923 } 924 925 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 926 if (IS_ERR(wm0010->dbvdd)) { 927 ret = PTR_ERR(wm0010->dbvdd); 928 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 929 return ret; 930 } 931 932 if (wm0010->pdata.gpio_reset) { 933 wm0010->gpio_reset = wm0010->pdata.gpio_reset; 934 935 if (wm0010->pdata.reset_active_high) 936 wm0010->gpio_reset_value = 1; 937 else 938 wm0010->gpio_reset_value = 0; 939 940 if (wm0010->gpio_reset_value) 941 gpio_flags = GPIOF_OUT_INIT_HIGH; 942 else 943 gpio_flags = GPIOF_OUT_INIT_LOW; 944 945 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, 946 gpio_flags, "wm0010 reset"); 947 if (ret < 0) { 948 dev_err(wm0010->dev, 949 "Failed to request GPIO for DSP reset: %d\n", 950 ret); 951 return ret; 952 } 953 } else { 954 dev_err(wm0010->dev, "No reset GPIO configured\n"); 955 return -EINVAL; 956 } 957 958 wm0010->state = WM0010_POWER_OFF; 959 960 irq = spi->irq; 961 if (wm0010->pdata.irq_flags) 962 trigger = wm0010->pdata.irq_flags; 963 else 964 trigger = IRQF_TRIGGER_FALLING; 965 trigger |= IRQF_ONESHOT; 966 967 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT, 968 "wm0010", wm0010); 969 if (ret) { 970 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 971 irq, ret); 972 return ret; 973 } 974 wm0010->irq = irq; 975 976 ret = irq_set_irq_wake(irq, 1); 977 if (ret) { 978 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 979 irq, ret); 980 return ret; 981 } 982 983 if (spi->max_speed_hz) 984 wm0010->board_max_spi_speed = spi->max_speed_hz; 985 else 986 wm0010->board_max_spi_speed = 0; 987 988 ret = snd_soc_register_codec(&spi->dev, 989 &soc_codec_dev_wm0010, wm0010_dai, 990 ARRAY_SIZE(wm0010_dai)); 991 if (ret < 0) 992 return ret; 993 994 return 0; 995 } 996 997 static int wm0010_spi_remove(struct spi_device *spi) 998 { 999 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 1000 1001 snd_soc_unregister_codec(&spi->dev); 1002 1003 gpio_set_value_cansleep(wm0010->gpio_reset, 1004 wm0010->gpio_reset_value); 1005 1006 irq_set_irq_wake(wm0010->irq, 0); 1007 1008 if (wm0010->irq) 1009 free_irq(wm0010->irq, wm0010); 1010 1011 return 0; 1012 } 1013 1014 static struct spi_driver wm0010_spi_driver = { 1015 .driver = { 1016 .name = "wm0010", 1017 .bus = &spi_bus_type, 1018 .owner = THIS_MODULE, 1019 }, 1020 .probe = wm0010_spi_probe, 1021 .remove = wm0010_spi_remove, 1022 }; 1023 1024 module_spi_driver(wm0010_spi_driver); 1025 1026 MODULE_DESCRIPTION("ASoC WM0010 driver"); 1027 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1028 MODULE_LICENSE("GPL"); 1029