1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/kernel.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/component.h> 12 #include <sound/tlv.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of.h> 15 #include <sound/jack.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <linux/regmap.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dapm.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 #include "wcd938x.h" 26 27 #define WCD938X_MAX_MICBIAS (4) 28 #define WCD938X_MAX_SUPPLY (4) 29 #define WCD938X_MBHC_MAX_BUTTONS (8) 30 #define TX_ADC_MAX (4) 31 #define WCD938X_TX_MAX_SWR_PORTS (5) 32 33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 34 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 35 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 36 /* Fractional Rates */ 37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 38 SNDRV_PCM_RATE_176400) 39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 40 SNDRV_PCM_FMTBIT_S24_LE) 41 /* Convert from vout ctl to micbias voltage in mV */ 42 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50) 43 #define SWR_CLK_RATE_0P6MHZ (600000) 44 #define SWR_CLK_RATE_1P2MHZ (1200000) 45 #define SWR_CLK_RATE_2P4MHZ (2400000) 46 #define SWR_CLK_RATE_4P8MHZ (4800000) 47 #define SWR_CLK_RATE_9P6MHZ (9600000) 48 #define SWR_CLK_RATE_11P2896MHZ (1128960) 49 50 #define WCD938X_DRV_NAME "wcd938x_codec" 51 #define WCD938X_VERSION_1_0 (1) 52 #define EAR_RX_PATH_AUX (1) 53 54 #define ADC_MODE_VAL_HIFI 0x01 55 #define ADC_MODE_VAL_LO_HIF 0x02 56 #define ADC_MODE_VAL_NORMAL 0x03 57 #define ADC_MODE_VAL_LP 0x05 58 #define ADC_MODE_VAL_ULP1 0x09 59 #define ADC_MODE_VAL_ULP2 0x0B 60 61 /* Z value defined in milliohm */ 62 #define WCD938X_ZDET_VAL_32 (32000) 63 #define WCD938X_ZDET_VAL_400 (400000) 64 #define WCD938X_ZDET_VAL_1200 (1200000) 65 #define WCD938X_ZDET_VAL_100K (100000000) 66 /* Z floating defined in ohms */ 67 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 68 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 69 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 70 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 71 /* Z value compared in milliOhm */ 72 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 73 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 74 #define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM 75 #define WCD_MBHC_HS_V_MAX 1600 76 77 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 78 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 79 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 80 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 81 .tlv.p = (tlv_array), \ 82 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 83 .put = wcd938x_ear_pa_put_gain, \ 84 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 85 86 enum { 87 WCD9380 = 0, 88 WCD9385 = 5, 89 }; 90 91 enum { 92 TX_HDR12 = 0, 93 TX_HDR34, 94 TX_HDR_MAX, 95 }; 96 97 enum { 98 WCD_RX1, 99 WCD_RX2, 100 WCD_RX3 101 }; 102 103 enum { 104 /* INTR_CTRL_INT_MASK_0 */ 105 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 106 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 107 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 108 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 109 WCD938X_IRQ_MBHC_SW_DET, 110 WCD938X_IRQ_HPHR_OCP_INT, 111 WCD938X_IRQ_HPHR_CNP_INT, 112 WCD938X_IRQ_HPHL_OCP_INT, 113 114 /* INTR_CTRL_INT_MASK_1 */ 115 WCD938X_IRQ_HPHL_CNP_INT, 116 WCD938X_IRQ_EAR_CNP_INT, 117 WCD938X_IRQ_EAR_SCD_INT, 118 WCD938X_IRQ_AUX_CNP_INT, 119 WCD938X_IRQ_AUX_SCD_INT, 120 WCD938X_IRQ_HPHL_PDM_WD_INT, 121 WCD938X_IRQ_HPHR_PDM_WD_INT, 122 WCD938X_IRQ_AUX_PDM_WD_INT, 123 124 /* INTR_CTRL_INT_MASK_2 */ 125 WCD938X_IRQ_LDORT_SCD_INT, 126 WCD938X_IRQ_MBHC_MOISTURE_INT, 127 WCD938X_IRQ_HPHL_SURGE_DET_INT, 128 WCD938X_IRQ_HPHR_SURGE_DET_INT, 129 WCD938X_NUM_IRQS, 130 }; 131 132 enum { 133 WCD_ADC1 = 0, 134 WCD_ADC2, 135 WCD_ADC3, 136 WCD_ADC4, 137 ALLOW_BUCK_DISABLE, 138 HPH_COMP_DELAY, 139 HPH_PA_DELAY, 140 AMIC2_BCS_ENABLE, 141 WCD_SUPPLIES_LPM_MODE, 142 }; 143 144 enum { 145 ADC_MODE_INVALID = 0, 146 ADC_MODE_HIFI, 147 ADC_MODE_LO_HIF, 148 ADC_MODE_NORMAL, 149 ADC_MODE_LP, 150 ADC_MODE_ULP1, 151 ADC_MODE_ULP2, 152 }; 153 154 enum { 155 AIF1_PB = 0, 156 AIF1_CAP, 157 NUM_CODEC_DAIS, 158 }; 159 160 static u8 tx_mode_bit[] = { 161 [ADC_MODE_INVALID] = 0x00, 162 [ADC_MODE_HIFI] = 0x01, 163 [ADC_MODE_LO_HIF] = 0x02, 164 [ADC_MODE_NORMAL] = 0x04, 165 [ADC_MODE_LP] = 0x08, 166 [ADC_MODE_ULP1] = 0x10, 167 [ADC_MODE_ULP2] = 0x20, 168 }; 169 170 struct wcd938x_priv { 171 struct sdw_slave *tx_sdw_dev; 172 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 173 struct device *txdev; 174 struct device *rxdev; 175 struct device_node *rxnode, *txnode; 176 struct regmap *regmap; 177 struct mutex micb_lock; 178 /* mbhc module */ 179 struct wcd_mbhc *wcd_mbhc; 180 struct wcd_mbhc_config mbhc_cfg; 181 struct wcd_mbhc_intr intr_ids; 182 struct wcd_clsh_ctrl *clsh_info; 183 struct irq_domain *virq; 184 struct regmap_irq_chip *wcd_regmap_irq_chip; 185 struct regmap_irq_chip_data *irq_chip; 186 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY]; 187 struct snd_soc_jack *jack; 188 unsigned long status_mask; 189 s32 micb_ref[WCD938X_MAX_MICBIAS]; 190 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 191 u32 hph_mode; 192 u32 tx_mode[TX_ADC_MAX]; 193 int flyback_cur_det_disable; 194 int ear_rx_path; 195 int variant; 196 int reset_gpio; 197 u32 micb1_mv; 198 u32 micb2_mv; 199 u32 micb3_mv; 200 u32 micb4_mv; 201 int hphr_pdm_wd_int; 202 int hphl_pdm_wd_int; 203 int aux_pdm_wd_int; 204 bool comp1_enable; 205 bool comp2_enable; 206 bool ldoh; 207 bool bcs_dis; 208 }; 209 210 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 211 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000); 212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 213 214 struct wcd938x_mbhc_zdet_param { 215 u16 ldo_ctl; 216 u16 noff; 217 u16 nshift; 218 u16 btn5; 219 u16 btn6; 220 u16 btn7; 221 }; 222 223 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 224 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 225 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 226 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 227 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 228 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 229 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 230 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 231 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 232 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 233 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 234 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 235 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 236 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 237 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 238 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 239 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 240 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 241 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 242 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 243 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 244 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 245 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 246 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 247 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 248 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 249 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 250 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 251 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 252 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 253 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 254 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 255 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 256 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 257 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 258 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 261 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 262 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 263 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 264 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 265 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 267 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 268 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 269 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 270 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 271 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 272 }; 273 274 static const struct reg_default wcd938x_defaults[] = { 275 {WCD938X_ANA_PAGE_REGISTER, 0x00}, 276 {WCD938X_ANA_BIAS, 0x00}, 277 {WCD938X_ANA_RX_SUPPLIES, 0x00}, 278 {WCD938X_ANA_HPH, 0x0C}, 279 {WCD938X_ANA_EAR, 0x00}, 280 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, 281 {WCD938X_ANA_TX_CH1, 0x20}, 282 {WCD938X_ANA_TX_CH2, 0x00}, 283 {WCD938X_ANA_TX_CH3, 0x20}, 284 {WCD938X_ANA_TX_CH4, 0x00}, 285 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, 286 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, 287 {WCD938X_ANA_MBHC_MECH, 0x39}, 288 {WCD938X_ANA_MBHC_ELECT, 0x08}, 289 {WCD938X_ANA_MBHC_ZDET, 0x00}, 290 {WCD938X_ANA_MBHC_RESULT_1, 0x00}, 291 {WCD938X_ANA_MBHC_RESULT_2, 0x00}, 292 {WCD938X_ANA_MBHC_RESULT_3, 0x00}, 293 {WCD938X_ANA_MBHC_BTN0, 0x00}, 294 {WCD938X_ANA_MBHC_BTN1, 0x10}, 295 {WCD938X_ANA_MBHC_BTN2, 0x20}, 296 {WCD938X_ANA_MBHC_BTN3, 0x30}, 297 {WCD938X_ANA_MBHC_BTN4, 0x40}, 298 {WCD938X_ANA_MBHC_BTN5, 0x50}, 299 {WCD938X_ANA_MBHC_BTN6, 0x60}, 300 {WCD938X_ANA_MBHC_BTN7, 0x70}, 301 {WCD938X_ANA_MICB1, 0x10}, 302 {WCD938X_ANA_MICB2, 0x10}, 303 {WCD938X_ANA_MICB2_RAMP, 0x00}, 304 {WCD938X_ANA_MICB3, 0x10}, 305 {WCD938X_ANA_MICB4, 0x10}, 306 {WCD938X_BIAS_CTL, 0x2A}, 307 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, 308 {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, 309 {WCD938X_LDOL_DISABLE_LDOL, 0x00}, 310 {WCD938X_MBHC_CTL_CLK, 0x00}, 311 {WCD938X_MBHC_CTL_ANA, 0x00}, 312 {WCD938X_MBHC_CTL_SPARE_1, 0x00}, 313 {WCD938X_MBHC_CTL_SPARE_2, 0x00}, 314 {WCD938X_MBHC_CTL_BCS, 0x00}, 315 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, 316 {WCD938X_MBHC_TEST_CTL, 0x00}, 317 {WCD938X_LDOH_MODE, 0x2B}, 318 {WCD938X_LDOH_BIAS, 0x68}, 319 {WCD938X_LDOH_STB_LOADS, 0x00}, 320 {WCD938X_LDOH_SLOWRAMP, 0x50}, 321 {WCD938X_MICB1_TEST_CTL_1, 0x1A}, 322 {WCD938X_MICB1_TEST_CTL_2, 0x00}, 323 {WCD938X_MICB1_TEST_CTL_3, 0xA4}, 324 {WCD938X_MICB2_TEST_CTL_1, 0x1A}, 325 {WCD938X_MICB2_TEST_CTL_2, 0x00}, 326 {WCD938X_MICB2_TEST_CTL_3, 0x24}, 327 {WCD938X_MICB3_TEST_CTL_1, 0x1A}, 328 {WCD938X_MICB3_TEST_CTL_2, 0x00}, 329 {WCD938X_MICB3_TEST_CTL_3, 0xA4}, 330 {WCD938X_MICB4_TEST_CTL_1, 0x1A}, 331 {WCD938X_MICB4_TEST_CTL_2, 0x00}, 332 {WCD938X_MICB4_TEST_CTL_3, 0xA4}, 333 {WCD938X_TX_COM_ADC_VCM, 0x39}, 334 {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, 335 {WCD938X_TX_COM_SPARE1, 0x00}, 336 {WCD938X_TX_COM_SPARE2, 0x00}, 337 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, 338 {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, 339 {WCD938X_TX_COM_SPARE3, 0x00}, 340 {WCD938X_TX_COM_SPARE4, 0x00}, 341 {WCD938X_TX_1_2_TEST_EN, 0xCC}, 342 {WCD938X_TX_1_2_ADC_IB, 0xE9}, 343 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, 344 {WCD938X_TX_1_2_TEST_CTL, 0x38}, 345 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, 346 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, 347 {WCD938X_TX_1_2_SAR2_ERR, 0x00}, 348 {WCD938X_TX_1_2_SAR1_ERR, 0x00}, 349 {WCD938X_TX_3_4_TEST_EN, 0xCC}, 350 {WCD938X_TX_3_4_ADC_IB, 0xE9}, 351 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, 352 {WCD938X_TX_3_4_TEST_CTL, 0x38}, 353 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, 354 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, 355 {WCD938X_TX_3_4_SAR4_ERR, 0x00}, 356 {WCD938X_TX_3_4_SAR3_ERR, 0x00}, 357 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, 358 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, 359 {WCD938X_TX_3_4_SPARE1, 0x00}, 360 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, 361 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, 362 {WCD938X_TX_3_4_SPARE2, 0x00}, 363 {WCD938X_CLASSH_MODE_1, 0x40}, 364 {WCD938X_CLASSH_MODE_2, 0x3A}, 365 {WCD938X_CLASSH_MODE_3, 0x00}, 366 {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, 367 {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, 368 {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, 369 {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, 370 {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, 371 {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, 372 {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, 373 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, 374 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, 375 {WCD938X_CLASSH_SPARE, 0x00}, 376 {WCD938X_FLYBACK_EN, 0x4E}, 377 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, 378 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, 379 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, 380 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, 381 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, 382 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, 383 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, 384 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, 385 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, 386 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, 387 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, 388 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, 389 {WCD938X_FLYBACK_CTRL_1, 0x65}, 390 {WCD938X_FLYBACK_TEST_CTL, 0x00}, 391 {WCD938X_RX_AUX_SW_CTL, 0x00}, 392 {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, 393 {WCD938X_RX_TIMER_DIV, 0x32}, 394 {WCD938X_RX_OCP_CTL, 0x1F}, 395 {WCD938X_RX_OCP_COUNT, 0x77}, 396 {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, 397 {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, 398 {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, 399 {WCD938X_RX_BIAS_HPH_PA, 0xAA}, 400 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, 401 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, 402 {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, 403 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, 404 {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, 405 {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, 406 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, 407 {WCD938X_RX_BIAS_MISC, 0x00}, 408 {WCD938X_RX_BIAS_BUCK_RST, 0x08}, 409 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, 410 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, 411 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, 412 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, 413 {WCD938X_HPH_L_STATUS, 0x04}, 414 {WCD938X_HPH_R_STATUS, 0x04}, 415 {WCD938X_HPH_CNP_EN, 0x80}, 416 {WCD938X_HPH_CNP_WG_CTL, 0x9A}, 417 {WCD938X_HPH_CNP_WG_TIME, 0x14}, 418 {WCD938X_HPH_OCP_CTL, 0x28}, 419 {WCD938X_HPH_AUTO_CHOP, 0x16}, 420 {WCD938X_HPH_CHOP_CTL, 0x83}, 421 {WCD938X_HPH_PA_CTL1, 0x46}, 422 {WCD938X_HPH_PA_CTL2, 0x50}, 423 {WCD938X_HPH_L_EN, 0x80}, 424 {WCD938X_HPH_L_TEST, 0xE0}, 425 {WCD938X_HPH_L_ATEST, 0x50}, 426 {WCD938X_HPH_R_EN, 0x80}, 427 {WCD938X_HPH_R_TEST, 0xE0}, 428 {WCD938X_HPH_R_ATEST, 0x54}, 429 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, 430 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, 431 {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, 432 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, 433 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, 434 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, 435 {WCD938X_HPH_L_DAC_CTL, 0x20}, 436 {WCD938X_HPH_R_DAC_CTL, 0x20}, 437 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, 438 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, 439 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, 440 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, 441 {WCD938X_EAR_EAR_EN_REG, 0x22}, 442 {WCD938X_EAR_EAR_PA_CON, 0x44}, 443 {WCD938X_EAR_EAR_SP_CON, 0xDB}, 444 {WCD938X_EAR_EAR_DAC_CON, 0x80}, 445 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, 446 {WCD938X_EAR_TEST_CTL, 0x00}, 447 {WCD938X_EAR_STATUS_REG_1, 0x00}, 448 {WCD938X_EAR_STATUS_REG_2, 0x08}, 449 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, 450 {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, 451 {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, 452 {WCD938X_SLEEP_CTL, 0x16}, 453 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, 454 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, 455 {WCD938X_MBHC_NEW_CTL_1, 0x02}, 456 {WCD938X_MBHC_NEW_CTL_2, 0x05}, 457 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, 458 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, 459 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, 460 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, 461 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, 462 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, 463 {WCD938X_AUX_AUXPA, 0x00}, 464 {WCD938X_LDORXTX_MODE, 0x0C}, 465 {WCD938X_LDORXTX_CONFIG, 0x10}, 466 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, 467 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, 468 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, 469 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, 470 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, 471 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, 472 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, 473 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, 474 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, 475 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, 476 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, 477 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, 478 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, 479 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, 480 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, 481 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, 482 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, 483 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, 484 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, 485 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, 486 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, 487 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, 488 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, 489 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, 490 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, 491 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, 492 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, 493 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, 494 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, 495 {WCD938X_AUX_INT_EN_REG, 0x00}, 496 {WCD938X_AUX_INT_PA_CTRL, 0x06}, 497 {WCD938X_AUX_INT_SP_CTRL, 0xD2}, 498 {WCD938X_AUX_INT_DAC_CTRL, 0x80}, 499 {WCD938X_AUX_INT_CLK_CTRL, 0x50}, 500 {WCD938X_AUX_INT_TEST_CTRL, 0x00}, 501 {WCD938X_AUX_INT_STATUS_REG, 0x00}, 502 {WCD938X_AUX_INT_MISC, 0x00}, 503 {WCD938X_LDORXTX_INT_BIAS, 0x6E}, 504 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, 505 {WCD938X_LDORXTX_INT_TEST0, 0x1C}, 506 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, 507 {WCD938X_LDORXTX_INT_TEST1, 0x1F}, 508 {WCD938X_LDORXTX_INT_STATUS, 0x00}, 509 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, 510 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, 511 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, 512 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, 513 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, 514 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, 515 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, 516 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, 517 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, 518 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, 519 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, 520 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, 521 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, 522 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, 523 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, 524 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, 525 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, 526 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, 527 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, 528 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, 529 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, 530 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, 531 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, 532 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, 533 {WCD938X_DIGITAL_CHIP_ID0, 0x00}, 534 {WCD938X_DIGITAL_CHIP_ID1, 0x00}, 535 {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, 536 {WCD938X_DIGITAL_CHIP_ID3, 0x01}, 537 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, 538 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, 539 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, 540 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, 541 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, 542 {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, 543 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, 544 {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, 545 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, 546 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, 547 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, 548 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, 549 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, 550 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, 551 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, 552 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, 553 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, 554 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, 555 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, 556 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, 557 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, 558 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, 559 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, 560 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, 561 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, 562 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, 563 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, 564 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, 565 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, 566 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, 567 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, 568 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, 569 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, 570 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, 571 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, 572 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, 573 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, 574 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, 575 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, 576 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, 577 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, 578 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, 579 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, 580 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, 581 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, 582 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, 583 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, 584 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, 585 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, 586 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, 587 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, 588 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, 589 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, 590 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, 591 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, 592 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, 593 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, 594 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, 595 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, 596 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, 597 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, 598 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, 599 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, 600 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, 601 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, 602 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, 603 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, 604 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, 605 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, 606 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, 607 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, 608 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, 609 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, 610 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, 611 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, 612 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, 613 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, 614 {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, 615 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, 616 {WCD938X_DIGITAL_CDC_RST, 0x00}, 617 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, 618 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, 619 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, 620 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, 621 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, 622 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, 623 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, 624 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, 625 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, 626 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, 627 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, 628 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, 629 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, 630 {WCD938X_DIGITAL_INTR_MODE, 0x00}, 631 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, 632 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, 633 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, 634 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, 635 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, 636 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, 637 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, 638 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, 639 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, 640 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, 641 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, 642 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, 643 {WCD938X_DIGITAL_INTR_SET_0, 0x00}, 644 {WCD938X_DIGITAL_INTR_SET_1, 0x00}, 645 {WCD938X_DIGITAL_INTR_SET_2, 0x00}, 646 {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, 647 {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, 648 {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, 649 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, 650 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, 651 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, 652 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, 653 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, 654 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, 655 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, 656 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, 657 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, 658 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, 659 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, 660 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, 661 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, 662 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, 663 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, 664 {WCD938X_DIGITAL_I2C_CTL, 0x00}, 665 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, 666 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, 667 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, 668 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, 669 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, 670 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, 671 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, 672 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, 673 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, 674 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, 675 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, 676 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, 677 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, 678 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, 679 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, 680 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, 681 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, 682 {WCD938X_DIGITAL_GPIO_MODE, 0x00}, 683 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, 684 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, 685 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, 686 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, 687 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, 688 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, 689 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, 690 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, 691 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, 692 {WCD938X_DIGITAL_SSP_DBG, 0x00}, 693 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, 694 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, 695 {WCD938X_DIGITAL_SPARE_0, 0x00}, 696 {WCD938X_DIGITAL_SPARE_1, 0x00}, 697 {WCD938X_DIGITAL_SPARE_2, 0x00}, 698 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, 699 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, 700 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, 701 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, 702 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, 703 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, 704 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, 705 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, 706 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, 707 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, 708 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, 709 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, 710 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, 711 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, 712 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, 713 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, 714 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, 715 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, 716 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, 717 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, 718 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, 719 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, 720 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, 721 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, 722 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, 723 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, 724 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, 725 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, 726 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, 727 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, 728 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, 729 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, 730 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, 731 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, 732 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, 733 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, 734 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, 735 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, 736 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, 737 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, 738 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, 739 }; 740 741 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) 742 { 743 switch (reg) { 744 case WCD938X_ANA_PAGE_REGISTER: 745 case WCD938X_ANA_BIAS: 746 case WCD938X_ANA_RX_SUPPLIES: 747 case WCD938X_ANA_HPH: 748 case WCD938X_ANA_EAR: 749 case WCD938X_ANA_EAR_COMPANDER_CTL: 750 case WCD938X_ANA_TX_CH1: 751 case WCD938X_ANA_TX_CH2: 752 case WCD938X_ANA_TX_CH3: 753 case WCD938X_ANA_TX_CH4: 754 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: 755 case WCD938X_ANA_MICB3_DSP_EN_LOGIC: 756 case WCD938X_ANA_MBHC_MECH: 757 case WCD938X_ANA_MBHC_ELECT: 758 case WCD938X_ANA_MBHC_ZDET: 759 case WCD938X_ANA_MBHC_BTN0: 760 case WCD938X_ANA_MBHC_BTN1: 761 case WCD938X_ANA_MBHC_BTN2: 762 case WCD938X_ANA_MBHC_BTN3: 763 case WCD938X_ANA_MBHC_BTN4: 764 case WCD938X_ANA_MBHC_BTN5: 765 case WCD938X_ANA_MBHC_BTN6: 766 case WCD938X_ANA_MBHC_BTN7: 767 case WCD938X_ANA_MICB1: 768 case WCD938X_ANA_MICB2: 769 case WCD938X_ANA_MICB2_RAMP: 770 case WCD938X_ANA_MICB3: 771 case WCD938X_ANA_MICB4: 772 case WCD938X_BIAS_CTL: 773 case WCD938X_BIAS_VBG_FINE_ADJ: 774 case WCD938X_LDOL_VDDCX_ADJUST: 775 case WCD938X_LDOL_DISABLE_LDOL: 776 case WCD938X_MBHC_CTL_CLK: 777 case WCD938X_MBHC_CTL_ANA: 778 case WCD938X_MBHC_CTL_SPARE_1: 779 case WCD938X_MBHC_CTL_SPARE_2: 780 case WCD938X_MBHC_CTL_BCS: 781 case WCD938X_MBHC_TEST_CTL: 782 case WCD938X_LDOH_MODE: 783 case WCD938X_LDOH_BIAS: 784 case WCD938X_LDOH_STB_LOADS: 785 case WCD938X_LDOH_SLOWRAMP: 786 case WCD938X_MICB1_TEST_CTL_1: 787 case WCD938X_MICB1_TEST_CTL_2: 788 case WCD938X_MICB1_TEST_CTL_3: 789 case WCD938X_MICB2_TEST_CTL_1: 790 case WCD938X_MICB2_TEST_CTL_2: 791 case WCD938X_MICB2_TEST_CTL_3: 792 case WCD938X_MICB3_TEST_CTL_1: 793 case WCD938X_MICB3_TEST_CTL_2: 794 case WCD938X_MICB3_TEST_CTL_3: 795 case WCD938X_MICB4_TEST_CTL_1: 796 case WCD938X_MICB4_TEST_CTL_2: 797 case WCD938X_MICB4_TEST_CTL_3: 798 case WCD938X_TX_COM_ADC_VCM: 799 case WCD938X_TX_COM_BIAS_ATEST: 800 case WCD938X_TX_COM_SPARE1: 801 case WCD938X_TX_COM_SPARE2: 802 case WCD938X_TX_COM_TXFE_DIV_CTL: 803 case WCD938X_TX_COM_TXFE_DIV_START: 804 case WCD938X_TX_COM_SPARE3: 805 case WCD938X_TX_COM_SPARE4: 806 case WCD938X_TX_1_2_TEST_EN: 807 case WCD938X_TX_1_2_ADC_IB: 808 case WCD938X_TX_1_2_ATEST_REFCTL: 809 case WCD938X_TX_1_2_TEST_CTL: 810 case WCD938X_TX_1_2_TEST_BLK_EN1: 811 case WCD938X_TX_1_2_TXFE1_CLKDIV: 812 case WCD938X_TX_3_4_TEST_EN: 813 case WCD938X_TX_3_4_ADC_IB: 814 case WCD938X_TX_3_4_ATEST_REFCTL: 815 case WCD938X_TX_3_4_TEST_CTL: 816 case WCD938X_TX_3_4_TEST_BLK_EN3: 817 case WCD938X_TX_3_4_TXFE3_CLKDIV: 818 case WCD938X_TX_3_4_TEST_BLK_EN2: 819 case WCD938X_TX_3_4_TXFE2_CLKDIV: 820 case WCD938X_TX_3_4_SPARE1: 821 case WCD938X_TX_3_4_TEST_BLK_EN4: 822 case WCD938X_TX_3_4_TXFE4_CLKDIV: 823 case WCD938X_TX_3_4_SPARE2: 824 case WCD938X_CLASSH_MODE_1: 825 case WCD938X_CLASSH_MODE_2: 826 case WCD938X_CLASSH_MODE_3: 827 case WCD938X_CLASSH_CTRL_VCL_1: 828 case WCD938X_CLASSH_CTRL_VCL_2: 829 case WCD938X_CLASSH_CTRL_CCL_1: 830 case WCD938X_CLASSH_CTRL_CCL_2: 831 case WCD938X_CLASSH_CTRL_CCL_3: 832 case WCD938X_CLASSH_CTRL_CCL_4: 833 case WCD938X_CLASSH_CTRL_CCL_5: 834 case WCD938X_CLASSH_BUCK_TMUX_A_D: 835 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: 836 case WCD938X_CLASSH_SPARE: 837 case WCD938X_FLYBACK_EN: 838 case WCD938X_FLYBACK_VNEG_CTRL_1: 839 case WCD938X_FLYBACK_VNEG_CTRL_2: 840 case WCD938X_FLYBACK_VNEG_CTRL_3: 841 case WCD938X_FLYBACK_VNEG_CTRL_4: 842 case WCD938X_FLYBACK_VNEG_CTRL_5: 843 case WCD938X_FLYBACK_VNEG_CTRL_6: 844 case WCD938X_FLYBACK_VNEG_CTRL_7: 845 case WCD938X_FLYBACK_VNEG_CTRL_8: 846 case WCD938X_FLYBACK_VNEG_CTRL_9: 847 case WCD938X_FLYBACK_VNEGDAC_CTRL_1: 848 case WCD938X_FLYBACK_VNEGDAC_CTRL_2: 849 case WCD938X_FLYBACK_VNEGDAC_CTRL_3: 850 case WCD938X_FLYBACK_CTRL_1: 851 case WCD938X_FLYBACK_TEST_CTL: 852 case WCD938X_RX_AUX_SW_CTL: 853 case WCD938X_RX_PA_AUX_IN_CONN: 854 case WCD938X_RX_TIMER_DIV: 855 case WCD938X_RX_OCP_CTL: 856 case WCD938X_RX_OCP_COUNT: 857 case WCD938X_RX_BIAS_EAR_DAC: 858 case WCD938X_RX_BIAS_EAR_AMP: 859 case WCD938X_RX_BIAS_HPH_LDO: 860 case WCD938X_RX_BIAS_HPH_PA: 861 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: 862 case WCD938X_RX_BIAS_HPH_RDAC_LDO: 863 case WCD938X_RX_BIAS_HPH_CNP1: 864 case WCD938X_RX_BIAS_HPH_LOWPOWER: 865 case WCD938X_RX_BIAS_AUX_DAC: 866 case WCD938X_RX_BIAS_AUX_AMP: 867 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: 868 case WCD938X_RX_BIAS_MISC: 869 case WCD938X_RX_BIAS_BUCK_RST: 870 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: 871 case WCD938X_RX_BIAS_FLYB_ERRAMP: 872 case WCD938X_RX_BIAS_FLYB_BUFF: 873 case WCD938X_RX_BIAS_FLYB_MID_RST: 874 case WCD938X_HPH_CNP_EN: 875 case WCD938X_HPH_CNP_WG_CTL: 876 case WCD938X_HPH_CNP_WG_TIME: 877 case WCD938X_HPH_OCP_CTL: 878 case WCD938X_HPH_AUTO_CHOP: 879 case WCD938X_HPH_CHOP_CTL: 880 case WCD938X_HPH_PA_CTL1: 881 case WCD938X_HPH_PA_CTL2: 882 case WCD938X_HPH_L_EN: 883 case WCD938X_HPH_L_TEST: 884 case WCD938X_HPH_L_ATEST: 885 case WCD938X_HPH_R_EN: 886 case WCD938X_HPH_R_TEST: 887 case WCD938X_HPH_R_ATEST: 888 case WCD938X_HPH_RDAC_CLK_CTL1: 889 case WCD938X_HPH_RDAC_CLK_CTL2: 890 case WCD938X_HPH_RDAC_LDO_CTL: 891 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: 892 case WCD938X_HPH_REFBUFF_UHQA_CTL: 893 case WCD938X_HPH_REFBUFF_LP_CTL: 894 case WCD938X_HPH_L_DAC_CTL: 895 case WCD938X_HPH_R_DAC_CTL: 896 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: 897 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: 898 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: 899 case WCD938X_EAR_EAR_EN_REG: 900 case WCD938X_EAR_EAR_PA_CON: 901 case WCD938X_EAR_EAR_SP_CON: 902 case WCD938X_EAR_EAR_DAC_CON: 903 case WCD938X_EAR_EAR_CNP_FSM_CON: 904 case WCD938X_EAR_TEST_CTL: 905 case WCD938X_ANA_NEW_PAGE_REGISTER: 906 case WCD938X_HPH_NEW_ANA_HPH2: 907 case WCD938X_HPH_NEW_ANA_HPH3: 908 case WCD938X_SLEEP_CTL: 909 case WCD938X_SLEEP_WATCHDOG_CTL: 910 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: 911 case WCD938X_MBHC_NEW_CTL_1: 912 case WCD938X_MBHC_NEW_CTL_2: 913 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: 914 case WCD938X_MBHC_NEW_ZDET_ANA_CTL: 915 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: 916 case WCD938X_TX_NEW_AMIC_MUX_CFG: 917 case WCD938X_AUX_AUXPA: 918 case WCD938X_LDORXTX_MODE: 919 case WCD938X_LDORXTX_CONFIG: 920 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: 921 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: 922 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: 923 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: 924 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: 925 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: 926 case WCD938X_HPH_NEW_INT_PA_MISC1: 927 case WCD938X_HPH_NEW_INT_PA_MISC2: 928 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: 929 case WCD938X_HPH_NEW_INT_HPH_TIMER1: 930 case WCD938X_HPH_NEW_INT_HPH_TIMER2: 931 case WCD938X_HPH_NEW_INT_HPH_TIMER3: 932 case WCD938X_HPH_NEW_INT_HPH_TIMER4: 933 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: 934 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: 935 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: 936 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: 937 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: 938 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: 939 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: 940 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: 941 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: 942 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: 943 case WCD938X_MBHC_NEW_INT_SPARE_2: 944 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: 945 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: 946 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: 947 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: 948 case WCD938X_AUX_INT_EN_REG: 949 case WCD938X_AUX_INT_PA_CTRL: 950 case WCD938X_AUX_INT_SP_CTRL: 951 case WCD938X_AUX_INT_DAC_CTRL: 952 case WCD938X_AUX_INT_CLK_CTRL: 953 case WCD938X_AUX_INT_TEST_CTRL: 954 case WCD938X_AUX_INT_MISC: 955 case WCD938X_LDORXTX_INT_BIAS: 956 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: 957 case WCD938X_LDORXTX_INT_TEST0: 958 case WCD938X_LDORXTX_INT_STARTUP_TIMER: 959 case WCD938X_LDORXTX_INT_TEST1: 960 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: 961 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: 962 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: 963 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: 964 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: 965 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: 966 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: 967 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: 968 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: 969 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: 970 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: 971 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: 972 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: 973 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: 974 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: 975 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: 976 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: 977 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: 978 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: 979 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: 980 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: 981 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: 982 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: 983 case WCD938X_DIGITAL_PAGE_REGISTER: 984 case WCD938X_DIGITAL_SWR_TX_CLK_RATE: 985 case WCD938X_DIGITAL_CDC_RST_CTL: 986 case WCD938X_DIGITAL_TOP_CLK_CFG: 987 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: 988 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: 989 case WCD938X_DIGITAL_SWR_RST_EN: 990 case WCD938X_DIGITAL_CDC_PATH_MODE: 991 case WCD938X_DIGITAL_CDC_RX_RST: 992 case WCD938X_DIGITAL_CDC_RX0_CTL: 993 case WCD938X_DIGITAL_CDC_RX1_CTL: 994 case WCD938X_DIGITAL_CDC_RX2_CTL: 995 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: 996 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: 997 case WCD938X_DIGITAL_CDC_COMP_CTL_0: 998 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: 999 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: 1000 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: 1001 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: 1002 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: 1003 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: 1004 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: 1005 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: 1006 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: 1007 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: 1008 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: 1009 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: 1010 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: 1011 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: 1012 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: 1013 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: 1014 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: 1015 case WCD938X_DIGITAL_CDC_HPH_DSM_R1: 1016 case WCD938X_DIGITAL_CDC_HPH_DSM_R2: 1017 case WCD938X_DIGITAL_CDC_HPH_DSM_R3: 1018 case WCD938X_DIGITAL_CDC_HPH_DSM_R4: 1019 case WCD938X_DIGITAL_CDC_HPH_DSM_R5: 1020 case WCD938X_DIGITAL_CDC_HPH_DSM_R6: 1021 case WCD938X_DIGITAL_CDC_HPH_DSM_R7: 1022 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: 1023 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: 1024 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: 1025 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: 1026 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: 1027 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: 1028 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: 1029 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: 1030 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: 1031 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: 1032 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: 1033 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: 1034 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: 1035 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: 1036 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: 1037 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: 1038 case WCD938X_DIGITAL_CDC_AUX_DSM_R1: 1039 case WCD938X_DIGITAL_CDC_AUX_DSM_R2: 1040 case WCD938X_DIGITAL_CDC_AUX_DSM_R3: 1041 case WCD938X_DIGITAL_CDC_AUX_DSM_R4: 1042 case WCD938X_DIGITAL_CDC_AUX_DSM_R5: 1043 case WCD938X_DIGITAL_CDC_AUX_DSM_R6: 1044 case WCD938X_DIGITAL_CDC_AUX_DSM_R7: 1045 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: 1046 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: 1047 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: 1048 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: 1049 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: 1050 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: 1051 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: 1052 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: 1053 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: 1054 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: 1055 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: 1056 case WCD938X_DIGITAL_CDC_SWR_CLH: 1057 case WCD938X_DIGITAL_SWR_CLH_BYP: 1058 case WCD938X_DIGITAL_CDC_TX0_CTL: 1059 case WCD938X_DIGITAL_CDC_TX1_CTL: 1060 case WCD938X_DIGITAL_CDC_TX2_CTL: 1061 case WCD938X_DIGITAL_CDC_TX_RST: 1062 case WCD938X_DIGITAL_CDC_REQ_CTL: 1063 case WCD938X_DIGITAL_CDC_RST: 1064 case WCD938X_DIGITAL_CDC_AMIC_CTL: 1065 case WCD938X_DIGITAL_CDC_DMIC_CTL: 1066 case WCD938X_DIGITAL_CDC_DMIC1_CTL: 1067 case WCD938X_DIGITAL_CDC_DMIC2_CTL: 1068 case WCD938X_DIGITAL_CDC_DMIC3_CTL: 1069 case WCD938X_DIGITAL_CDC_DMIC4_CTL: 1070 case WCD938X_DIGITAL_EFUSE_PRG_CTL: 1071 case WCD938X_DIGITAL_EFUSE_CTL: 1072 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: 1073 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: 1074 case WCD938X_DIGITAL_PDM_WD_CTL0: 1075 case WCD938X_DIGITAL_PDM_WD_CTL1: 1076 case WCD938X_DIGITAL_PDM_WD_CTL2: 1077 case WCD938X_DIGITAL_INTR_MODE: 1078 case WCD938X_DIGITAL_INTR_MASK_0: 1079 case WCD938X_DIGITAL_INTR_MASK_1: 1080 case WCD938X_DIGITAL_INTR_MASK_2: 1081 case WCD938X_DIGITAL_INTR_CLEAR_0: 1082 case WCD938X_DIGITAL_INTR_CLEAR_1: 1083 case WCD938X_DIGITAL_INTR_CLEAR_2: 1084 case WCD938X_DIGITAL_INTR_LEVEL_0: 1085 case WCD938X_DIGITAL_INTR_LEVEL_1: 1086 case WCD938X_DIGITAL_INTR_LEVEL_2: 1087 case WCD938X_DIGITAL_INTR_SET_0: 1088 case WCD938X_DIGITAL_INTR_SET_1: 1089 case WCD938X_DIGITAL_INTR_SET_2: 1090 case WCD938X_DIGITAL_INTR_TEST_0: 1091 case WCD938X_DIGITAL_INTR_TEST_1: 1092 case WCD938X_DIGITAL_INTR_TEST_2: 1093 case WCD938X_DIGITAL_TX_MODE_DBG_EN: 1094 case WCD938X_DIGITAL_TX_MODE_DBG_0_1: 1095 case WCD938X_DIGITAL_TX_MODE_DBG_2_3: 1096 case WCD938X_DIGITAL_LB_IN_SEL_CTL: 1097 case WCD938X_DIGITAL_LOOP_BACK_MODE: 1098 case WCD938X_DIGITAL_SWR_DAC_TEST: 1099 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: 1100 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: 1101 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: 1102 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: 1103 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: 1104 case WCD938X_DIGITAL_PAD_CTL_SWR_0: 1105 case WCD938X_DIGITAL_PAD_CTL_SWR_1: 1106 case WCD938X_DIGITAL_I2C_CTL: 1107 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: 1108 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: 1109 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: 1110 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: 1111 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: 1112 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: 1113 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: 1114 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: 1115 case WCD938X_DIGITAL_PAD_INP_DIS_0: 1116 case WCD938X_DIGITAL_PAD_INP_DIS_1: 1117 case WCD938X_DIGITAL_DRIVE_STRENGTH_0: 1118 case WCD938X_DIGITAL_DRIVE_STRENGTH_1: 1119 case WCD938X_DIGITAL_DRIVE_STRENGTH_2: 1120 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: 1121 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: 1122 case WCD938X_DIGITAL_GPIO_MODE: 1123 case WCD938X_DIGITAL_PIN_CTL_OE: 1124 case WCD938X_DIGITAL_PIN_CTL_DATA_0: 1125 case WCD938X_DIGITAL_PIN_CTL_DATA_1: 1126 case WCD938X_DIGITAL_DIG_DEBUG_CTL: 1127 case WCD938X_DIGITAL_DIG_DEBUG_EN: 1128 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: 1129 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: 1130 case WCD938X_DIGITAL_SSP_DBG: 1131 case WCD938X_DIGITAL_SPARE_0: 1132 case WCD938X_DIGITAL_SPARE_1: 1133 case WCD938X_DIGITAL_SPARE_2: 1134 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: 1135 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: 1136 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: 1137 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: 1138 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: 1139 case WCD938X_DIGITAL_DEM_BYPASS_DATA0: 1140 case WCD938X_DIGITAL_DEM_BYPASS_DATA1: 1141 case WCD938X_DIGITAL_DEM_BYPASS_DATA2: 1142 case WCD938X_DIGITAL_DEM_BYPASS_DATA3: 1143 return true; 1144 } 1145 1146 return false; 1147 } 1148 1149 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) 1150 { 1151 switch (reg) { 1152 case WCD938X_ANA_MBHC_RESULT_1: 1153 case WCD938X_ANA_MBHC_RESULT_2: 1154 case WCD938X_ANA_MBHC_RESULT_3: 1155 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: 1156 case WCD938X_TX_1_2_SAR2_ERR: 1157 case WCD938X_TX_1_2_SAR1_ERR: 1158 case WCD938X_TX_3_4_SAR4_ERR: 1159 case WCD938X_TX_3_4_SAR3_ERR: 1160 case WCD938X_HPH_L_STATUS: 1161 case WCD938X_HPH_R_STATUS: 1162 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: 1163 case WCD938X_EAR_STATUS_REG_1: 1164 case WCD938X_EAR_STATUS_REG_2: 1165 case WCD938X_MBHC_NEW_FSM_STATUS: 1166 case WCD938X_MBHC_NEW_ADC_RESULT: 1167 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: 1168 case WCD938X_AUX_INT_STATUS_REG: 1169 case WCD938X_LDORXTX_INT_STATUS: 1170 case WCD938X_DIGITAL_CHIP_ID0: 1171 case WCD938X_DIGITAL_CHIP_ID1: 1172 case WCD938X_DIGITAL_CHIP_ID2: 1173 case WCD938X_DIGITAL_CHIP_ID3: 1174 case WCD938X_DIGITAL_INTR_STATUS_0: 1175 case WCD938X_DIGITAL_INTR_STATUS_1: 1176 case WCD938X_DIGITAL_INTR_STATUS_2: 1177 case WCD938X_DIGITAL_SWR_HM_TEST_0: 1178 case WCD938X_DIGITAL_SWR_HM_TEST_1: 1179 case WCD938X_DIGITAL_EFUSE_T_DATA_0: 1180 case WCD938X_DIGITAL_EFUSE_T_DATA_1: 1181 case WCD938X_DIGITAL_PIN_STATUS_0: 1182 case WCD938X_DIGITAL_PIN_STATUS_1: 1183 case WCD938X_DIGITAL_MODE_STATUS_0: 1184 case WCD938X_DIGITAL_MODE_STATUS_1: 1185 case WCD938X_DIGITAL_EFUSE_REG_0: 1186 case WCD938X_DIGITAL_EFUSE_REG_1: 1187 case WCD938X_DIGITAL_EFUSE_REG_2: 1188 case WCD938X_DIGITAL_EFUSE_REG_3: 1189 case WCD938X_DIGITAL_EFUSE_REG_4: 1190 case WCD938X_DIGITAL_EFUSE_REG_5: 1191 case WCD938X_DIGITAL_EFUSE_REG_6: 1192 case WCD938X_DIGITAL_EFUSE_REG_7: 1193 case WCD938X_DIGITAL_EFUSE_REG_8: 1194 case WCD938X_DIGITAL_EFUSE_REG_9: 1195 case WCD938X_DIGITAL_EFUSE_REG_10: 1196 case WCD938X_DIGITAL_EFUSE_REG_11: 1197 case WCD938X_DIGITAL_EFUSE_REG_12: 1198 case WCD938X_DIGITAL_EFUSE_REG_13: 1199 case WCD938X_DIGITAL_EFUSE_REG_14: 1200 case WCD938X_DIGITAL_EFUSE_REG_15: 1201 case WCD938X_DIGITAL_EFUSE_REG_16: 1202 case WCD938X_DIGITAL_EFUSE_REG_17: 1203 case WCD938X_DIGITAL_EFUSE_REG_18: 1204 case WCD938X_DIGITAL_EFUSE_REG_19: 1205 case WCD938X_DIGITAL_EFUSE_REG_20: 1206 case WCD938X_DIGITAL_EFUSE_REG_21: 1207 case WCD938X_DIGITAL_EFUSE_REG_22: 1208 case WCD938X_DIGITAL_EFUSE_REG_23: 1209 case WCD938X_DIGITAL_EFUSE_REG_24: 1210 case WCD938X_DIGITAL_EFUSE_REG_25: 1211 case WCD938X_DIGITAL_EFUSE_REG_26: 1212 case WCD938X_DIGITAL_EFUSE_REG_27: 1213 case WCD938X_DIGITAL_EFUSE_REG_28: 1214 case WCD938X_DIGITAL_EFUSE_REG_29: 1215 case WCD938X_DIGITAL_EFUSE_REG_30: 1216 case WCD938X_DIGITAL_EFUSE_REG_31: 1217 return true; 1218 } 1219 return false; 1220 } 1221 1222 static bool wcd938x_readable_register(struct device *dev, unsigned int reg) 1223 { 1224 bool ret; 1225 1226 ret = wcd938x_readonly_register(dev, reg); 1227 if (!ret) 1228 return wcd938x_rdwr_register(dev, reg); 1229 1230 return ret; 1231 } 1232 1233 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) 1234 { 1235 return wcd938x_rdwr_register(dev, reg); 1236 } 1237 1238 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) 1239 { 1240 if (reg <= WCD938X_BASE_ADDRESS) 1241 return false; 1242 1243 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) 1244 return true; 1245 1246 if (wcd938x_readonly_register(dev, reg)) 1247 return true; 1248 1249 return false; 1250 } 1251 1252 static struct regmap_config wcd938x_regmap_config = { 1253 .name = "wcd938x_csr", 1254 .reg_bits = 32, 1255 .val_bits = 8, 1256 .cache_type = REGCACHE_RBTREE, 1257 .reg_defaults = wcd938x_defaults, 1258 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), 1259 .max_register = WCD938X_MAX_REGISTER, 1260 .readable_reg = wcd938x_readable_register, 1261 .writeable_reg = wcd938x_writeable_register, 1262 .volatile_reg = wcd938x_volatile_register, 1263 .can_multi_write = true, 1264 }; 1265 1266 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 1267 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 1268 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 1269 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 1270 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 1271 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 1272 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 1273 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 1274 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 1275 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 1276 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 1277 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 1278 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 1279 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 1280 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 1281 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 1282 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 1283 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 1284 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 1285 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 1286 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 1287 }; 1288 1289 static struct regmap_irq_chip wcd938x_regmap_irq_chip = { 1290 .name = "wcd938x", 1291 .irqs = wcd938x_irqs, 1292 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 1293 .num_regs = 3, 1294 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 1295 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 1296 .type_base = WCD938X_DIGITAL_INTR_LEVEL_0, 1297 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 1298 .use_ack = 1, 1299 .runtime_pm = true, 1300 .irq_drv_data = NULL, 1301 }; 1302 1303 static int wcd938x_get_clk_rate(int mode) 1304 { 1305 int rate; 1306 1307 switch (mode) { 1308 case ADC_MODE_ULP2: 1309 rate = SWR_CLK_RATE_0P6MHZ; 1310 break; 1311 case ADC_MODE_ULP1: 1312 rate = SWR_CLK_RATE_1P2MHZ; 1313 break; 1314 case ADC_MODE_LP: 1315 rate = SWR_CLK_RATE_4P8MHZ; 1316 break; 1317 case ADC_MODE_NORMAL: 1318 case ADC_MODE_LO_HIF: 1319 case ADC_MODE_HIFI: 1320 case ADC_MODE_INVALID: 1321 default: 1322 rate = SWR_CLK_RATE_9P6MHZ; 1323 break; 1324 } 1325 1326 return rate; 1327 } 1328 1329 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 1330 { 1331 u8 mask = (bank ? 0xF0 : 0x0F); 1332 u8 val = 0; 1333 1334 switch (rate) { 1335 case SWR_CLK_RATE_0P6MHZ: 1336 val = (bank ? 0x60 : 0x06); 1337 break; 1338 case SWR_CLK_RATE_1P2MHZ: 1339 val = (bank ? 0x50 : 0x05); 1340 break; 1341 case SWR_CLK_RATE_2P4MHZ: 1342 val = (bank ? 0x30 : 0x03); 1343 break; 1344 case SWR_CLK_RATE_4P8MHZ: 1345 val = (bank ? 0x10 : 0x01); 1346 break; 1347 case SWR_CLK_RATE_9P6MHZ: 1348 default: 1349 val = 0x00; 1350 break; 1351 } 1352 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 1353 mask, val); 1354 1355 return 0; 1356 } 1357 1358 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 1359 { 1360 struct regmap *rm = wcd938x->regmap; 1361 1362 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 1363 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 1364 /* 1 msec delay as per HW requirement */ 1365 usleep_range(1000, 1010); 1366 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 1367 /* 1 msec delay as per HW requirement */ 1368 usleep_range(1000, 1010); 1369 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 1370 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 1371 0xF0, 0x80); 1372 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 1373 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 1374 /* 10 msec delay as per HW requirement */ 1375 usleep_range(10000, 10010); 1376 1377 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 1378 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 1379 0xF0, 0x00); 1380 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 1381 0x1F, 0x15); 1382 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 1383 0x1F, 0x15); 1384 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 1385 0xC0, 0x80); 1386 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 1387 0x02, 0x02); 1388 1389 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 1390 0xFF, 0x14); 1391 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 1392 0x1F, 0x08); 1393 1394 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 1395 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 1396 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 1397 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 1398 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 1399 1400 /* Set Noise Filter Resistor value */ 1401 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 1402 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 1403 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 1404 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 1405 1406 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 1407 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1408 1409 return 0; 1410 1411 } 1412 1413 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info, 1414 struct sdw_port_config *port_config, 1415 u8 enable) 1416 { 1417 u8 ch_mask, port_num; 1418 1419 port_num = ch_info->port_num; 1420 ch_mask = ch_info->ch_mask; 1421 1422 port_config->num = port_num; 1423 1424 if (enable) 1425 port_config->ch_mask |= ch_mask; 1426 else 1427 port_config->ch_mask &= ~ch_mask; 1428 1429 return 0; 1430 } 1431 1432 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable) 1433 { 1434 u8 port_num; 1435 1436 port_num = wcd->ch_info[ch_id].port_num; 1437 1438 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 1439 &wcd->port_config[port_num], 1440 enable); 1441 } 1442 1443 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 1444 struct snd_kcontrol *kcontrol, 1445 int event) 1446 { 1447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1448 1449 switch (event) { 1450 case SND_SOC_DAPM_PRE_PMU: 1451 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1452 WCD938X_ANA_RX_CLK_EN_MASK, 1); 1453 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1454 WCD938X_RX_BIAS_EN_MASK, 1); 1455 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 1456 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1457 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 1458 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1459 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 1460 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1461 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1462 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 1463 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 1464 WCD938X_AUXPA_CLK_EN_MASK, 1); 1465 break; 1466 case SND_SOC_DAPM_POST_PMD: 1467 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1468 WCD938X_VNEG_EN_MASK, 0); 1469 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1470 WCD938X_VPOS_EN_MASK, 0); 1471 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1472 WCD938X_RX_BIAS_EN_MASK, 0); 1473 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1474 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 1475 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1476 WCD938X_ANA_RX_CLK_EN_MASK, 0); 1477 break; 1478 } 1479 return 0; 1480 } 1481 1482 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 1483 struct snd_kcontrol *kcontrol, 1484 int event) 1485 { 1486 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1487 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1488 1489 switch (event) { 1490 case SND_SOC_DAPM_PRE_PMU: 1491 snd_soc_component_write_field(component, 1492 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1493 WCD938X_RXD0_CLK_EN_MASK, 0x01); 1494 snd_soc_component_write_field(component, 1495 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1496 WCD938X_HPHL_RX_EN_MASK, 1); 1497 snd_soc_component_write_field(component, 1498 WCD938X_HPH_RDAC_CLK_CTL1, 1499 WCD938X_CHOP_CLK_EN_MASK, 0); 1500 break; 1501 case SND_SOC_DAPM_POST_PMU: 1502 snd_soc_component_write_field(component, 1503 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 1504 WCD938X_HPH_RES_DIV_MASK, 0x02); 1505 if (wcd938x->comp1_enable) { 1506 snd_soc_component_write_field(component, 1507 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1508 WCD938X_HPHL_COMP_EN_MASK, 1); 1509 /* 5msec compander delay as per HW requirement */ 1510 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 1511 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 1512 usleep_range(5000, 5010); 1513 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1514 WCD938X_AUTOCHOP_TIMER_EN, 0); 1515 } else { 1516 snd_soc_component_write_field(component, 1517 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1518 WCD938X_HPHL_COMP_EN_MASK, 0); 1519 snd_soc_component_write_field(component, 1520 WCD938X_HPH_L_EN, 1521 WCD938X_GAIN_SRC_SEL_MASK, 1522 WCD938X_GAIN_SRC_SEL_REGISTER); 1523 1524 } 1525 break; 1526 case SND_SOC_DAPM_POST_PMD: 1527 snd_soc_component_write_field(component, 1528 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1529 WCD938X_HPH_RES_DIV_MASK, 0x1); 1530 break; 1531 } 1532 1533 return 0; 1534 } 1535 1536 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 1537 struct snd_kcontrol *kcontrol, 1538 int event) 1539 { 1540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1541 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1542 1543 switch (event) { 1544 case SND_SOC_DAPM_PRE_PMU: 1545 snd_soc_component_write_field(component, 1546 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1547 WCD938X_RXD1_CLK_EN_MASK, 1); 1548 snd_soc_component_write_field(component, 1549 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1550 WCD938X_HPHR_RX_EN_MASK, 1); 1551 snd_soc_component_write_field(component, 1552 WCD938X_HPH_RDAC_CLK_CTL1, 1553 WCD938X_CHOP_CLK_EN_MASK, 0); 1554 break; 1555 case SND_SOC_DAPM_POST_PMU: 1556 snd_soc_component_write_field(component, 1557 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1558 WCD938X_HPH_RES_DIV_MASK, 0x02); 1559 if (wcd938x->comp2_enable) { 1560 snd_soc_component_write_field(component, 1561 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1562 WCD938X_HPHR_COMP_EN_MASK, 1); 1563 /* 5msec compander delay as per HW requirement */ 1564 if (!wcd938x->comp1_enable || 1565 (snd_soc_component_read(component, 1566 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 1567 usleep_range(5000, 5010); 1568 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1569 WCD938X_AUTOCHOP_TIMER_EN, 0); 1570 } else { 1571 snd_soc_component_write_field(component, 1572 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1573 WCD938X_HPHR_COMP_EN_MASK, 0); 1574 snd_soc_component_write_field(component, 1575 WCD938X_HPH_R_EN, 1576 WCD938X_GAIN_SRC_SEL_MASK, 1577 WCD938X_GAIN_SRC_SEL_REGISTER); 1578 } 1579 break; 1580 case SND_SOC_DAPM_POST_PMD: 1581 snd_soc_component_write_field(component, 1582 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1583 WCD938X_HPH_RES_DIV_MASK, 0x01); 1584 break; 1585 } 1586 1587 return 0; 1588 } 1589 1590 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 1591 struct snd_kcontrol *kcontrol, 1592 int event) 1593 { 1594 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1595 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1596 1597 switch (event) { 1598 case SND_SOC_DAPM_PRE_PMU: 1599 wcd938x->ear_rx_path = 1600 snd_soc_component_read( 1601 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1602 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1603 snd_soc_component_write_field(component, 1604 WCD938X_EAR_EAR_DAC_CON, 1605 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 1606 snd_soc_component_write_field(component, 1607 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1608 WCD938X_AUX_EN_MASK, 1); 1609 snd_soc_component_write_field(component, 1610 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1611 WCD938X_RXD2_CLK_EN_MASK, 1); 1612 snd_soc_component_write_field(component, 1613 WCD938X_ANA_EAR_COMPANDER_CTL, 1614 WCD938X_GAIN_OVRD_REG_MASK, 1); 1615 } else { 1616 snd_soc_component_write_field(component, 1617 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1618 WCD938X_HPHL_RX_EN_MASK, 1); 1619 snd_soc_component_write_field(component, 1620 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1621 WCD938X_RXD0_CLK_EN_MASK, 1); 1622 if (wcd938x->comp1_enable) 1623 snd_soc_component_write_field(component, 1624 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1625 WCD938X_HPHL_COMP_EN_MASK, 1); 1626 } 1627 /* 5 msec delay as per HW requirement */ 1628 usleep_range(5000, 5010); 1629 if (wcd938x->flyback_cur_det_disable == 0) 1630 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1631 WCD938X_EN_CUR_DET_MASK, 0); 1632 wcd938x->flyback_cur_det_disable++; 1633 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1634 WCD_CLSH_EVENT_PRE_DAC, 1635 WCD_CLSH_STATE_EAR, 1636 wcd938x->hph_mode); 1637 break; 1638 case SND_SOC_DAPM_POST_PMD: 1639 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1640 snd_soc_component_write_field(component, 1641 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1642 WCD938X_AUX_EN_MASK, 0); 1643 snd_soc_component_write_field(component, 1644 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1645 WCD938X_RXD2_CLK_EN_MASK, 0); 1646 } else { 1647 snd_soc_component_write_field(component, 1648 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1649 WCD938X_HPHL_RX_EN_MASK, 0); 1650 snd_soc_component_write_field(component, 1651 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1652 WCD938X_RXD0_CLK_EN_MASK, 0); 1653 if (wcd938x->comp1_enable) 1654 snd_soc_component_write_field(component, 1655 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1656 WCD938X_HPHL_COMP_EN_MASK, 0); 1657 } 1658 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1659 WCD938X_GAIN_OVRD_REG_MASK, 0); 1660 snd_soc_component_write_field(component, 1661 WCD938X_EAR_EAR_DAC_CON, 1662 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 1663 break; 1664 } 1665 return 0; 1666 1667 } 1668 1669 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 1670 struct snd_kcontrol *kcontrol, 1671 int event) 1672 { 1673 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1674 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1675 1676 switch (event) { 1677 case SND_SOC_DAPM_PRE_PMU: 1678 snd_soc_component_write_field(component, 1679 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1680 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 1681 snd_soc_component_write_field(component, 1682 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1683 WCD938X_RXD2_CLK_EN_MASK, 1); 1684 snd_soc_component_write_field(component, 1685 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1686 WCD938X_AUX_EN_MASK, 1); 1687 if (wcd938x->flyback_cur_det_disable == 0) 1688 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1689 WCD938X_EN_CUR_DET_MASK, 0); 1690 wcd938x->flyback_cur_det_disable++; 1691 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1692 WCD_CLSH_EVENT_PRE_DAC, 1693 WCD_CLSH_STATE_AUX, 1694 wcd938x->hph_mode); 1695 break; 1696 case SND_SOC_DAPM_POST_PMD: 1697 snd_soc_component_write_field(component, 1698 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1699 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 1700 break; 1701 } 1702 return 0; 1703 1704 } 1705 1706 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 1707 struct snd_kcontrol *kcontrol, int event) 1708 { 1709 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1710 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1711 int hph_mode = wcd938x->hph_mode; 1712 1713 switch (event) { 1714 case SND_SOC_DAPM_PRE_PMU: 1715 if (wcd938x->ldoh) 1716 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1717 WCD938X_LDOH_EN_MASK, 1); 1718 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1719 WCD_CLSH_STATE_HPHR, hph_mode); 1720 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1721 1722 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1723 hph_mode == CLS_H_ULP) { 1724 snd_soc_component_write_field(component, 1725 WCD938X_HPH_REFBUFF_LP_CTL, 1726 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1727 } 1728 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1729 WCD938X_HPHR_REF_EN_MASK, 1); 1730 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1731 /* 100 usec delay as per HW requirement */ 1732 usleep_range(100, 110); 1733 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1734 snd_soc_component_write_field(component, 1735 WCD938X_DIGITAL_PDM_WD_CTL1, 1736 WCD938X_PDM_WD_EN_MASK, 0x3); 1737 break; 1738 case SND_SOC_DAPM_POST_PMU: 1739 /* 1740 * 7ms sleep is required if compander is enabled as per 1741 * HW requirement. If compander is disabled, then 1742 * 20ms delay is required. 1743 */ 1744 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1745 if (!wcd938x->comp2_enable) 1746 usleep_range(20000, 20100); 1747 else 1748 usleep_range(7000, 7100); 1749 1750 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1751 hph_mode == CLS_H_ULP) 1752 snd_soc_component_write_field(component, 1753 WCD938X_HPH_REFBUFF_LP_CTL, 1754 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1755 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1756 } 1757 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1758 WCD938X_AUTOCHOP_TIMER_EN, 1); 1759 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1760 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1761 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1762 WCD938X_REGULATOR_MODE_MASK, 1763 WCD938X_REGULATOR_MODE_CLASS_AB); 1764 enable_irq(wcd938x->hphr_pdm_wd_int); 1765 break; 1766 case SND_SOC_DAPM_PRE_PMD: 1767 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 1768 /* 1769 * 7ms sleep is required if compander is enabled as per 1770 * HW requirement. If compander is disabled, then 1771 * 20ms delay is required. 1772 */ 1773 if (!wcd938x->comp2_enable) 1774 usleep_range(20000, 20100); 1775 else 1776 usleep_range(7000, 7100); 1777 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1778 WCD938X_HPHR_EN_MASK, 0); 1779 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1780 WCD_EVENT_PRE_HPHR_PA_OFF); 1781 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1782 break; 1783 case SND_SOC_DAPM_POST_PMD: 1784 /* 1785 * 7ms sleep is required if compander is enabled as per 1786 * HW requirement. If compander is disabled, then 1787 * 20ms delay is required. 1788 */ 1789 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1790 if (!wcd938x->comp2_enable) 1791 usleep_range(20000, 20100); 1792 else 1793 usleep_range(7000, 7100); 1794 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1795 } 1796 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1797 WCD_EVENT_POST_HPHR_PA_OFF); 1798 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1799 WCD938X_HPHR_REF_EN_MASK, 0); 1800 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 1801 WCD938X_PDM_WD_EN_MASK, 0); 1802 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1803 WCD_CLSH_STATE_HPHR, hph_mode); 1804 if (wcd938x->ldoh) 1805 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1806 WCD938X_LDOH_EN_MASK, 0); 1807 break; 1808 } 1809 1810 return 0; 1811 } 1812 1813 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 1814 struct snd_kcontrol *kcontrol, int event) 1815 { 1816 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1817 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1818 int hph_mode = wcd938x->hph_mode; 1819 1820 switch (event) { 1821 case SND_SOC_DAPM_PRE_PMU: 1822 if (wcd938x->ldoh) 1823 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1824 WCD938X_LDOH_EN_MASK, 1); 1825 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1826 WCD_CLSH_STATE_HPHL, hph_mode); 1827 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1828 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1829 hph_mode == CLS_H_ULP) { 1830 snd_soc_component_write_field(component, 1831 WCD938X_HPH_REFBUFF_LP_CTL, 1832 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1833 } 1834 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1835 WCD938X_HPHL_REF_EN_MASK, 1); 1836 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1837 /* 100 usec delay as per HW requirement */ 1838 usleep_range(100, 110); 1839 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1840 snd_soc_component_write_field(component, 1841 WCD938X_DIGITAL_PDM_WD_CTL0, 1842 WCD938X_PDM_WD_EN_MASK, 0x3); 1843 break; 1844 case SND_SOC_DAPM_POST_PMU: 1845 /* 1846 * 7ms sleep is required if compander is enabled as per 1847 * HW requirement. If compander is disabled, then 1848 * 20ms delay is required. 1849 */ 1850 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1851 if (!wcd938x->comp1_enable) 1852 usleep_range(20000, 20100); 1853 else 1854 usleep_range(7000, 7100); 1855 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1856 hph_mode == CLS_H_ULP) 1857 snd_soc_component_write_field(component, 1858 WCD938X_HPH_REFBUFF_LP_CTL, 1859 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1860 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1861 } 1862 1863 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1864 WCD938X_AUTOCHOP_TIMER_EN, 1); 1865 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1866 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1867 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1868 WCD938X_REGULATOR_MODE_MASK, 1869 WCD938X_REGULATOR_MODE_CLASS_AB); 1870 enable_irq(wcd938x->hphl_pdm_wd_int); 1871 break; 1872 case SND_SOC_DAPM_PRE_PMD: 1873 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 1874 /* 1875 * 7ms sleep is required if compander is enabled as per 1876 * HW requirement. If compander is disabled, then 1877 * 20ms delay is required. 1878 */ 1879 if (!wcd938x->comp1_enable) 1880 usleep_range(20000, 20100); 1881 else 1882 usleep_range(7000, 7100); 1883 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1884 WCD938X_HPHL_EN_MASK, 0); 1885 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 1886 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1887 break; 1888 case SND_SOC_DAPM_POST_PMD: 1889 /* 1890 * 7ms sleep is required if compander is enabled as per 1891 * HW requirement. If compander is disabled, then 1892 * 20ms delay is required. 1893 */ 1894 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1895 if (!wcd938x->comp1_enable) 1896 usleep_range(21000, 21100); 1897 else 1898 usleep_range(7000, 7100); 1899 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1900 } 1901 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1902 WCD_EVENT_POST_HPHL_PA_OFF); 1903 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1904 WCD938X_HPHL_REF_EN_MASK, 0); 1905 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1906 WCD938X_PDM_WD_EN_MASK, 0); 1907 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1908 WCD_CLSH_STATE_HPHL, hph_mode); 1909 if (wcd938x->ldoh) 1910 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1911 WCD938X_LDOH_EN_MASK, 0); 1912 break; 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 1919 struct snd_kcontrol *kcontrol, int event) 1920 { 1921 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1922 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1923 int hph_mode = wcd938x->hph_mode; 1924 1925 switch (event) { 1926 case SND_SOC_DAPM_PRE_PMU: 1927 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1928 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1929 break; 1930 case SND_SOC_DAPM_POST_PMU: 1931 /* 1 msec delay as per HW requirement */ 1932 usleep_range(1000, 1010); 1933 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1934 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1935 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1936 WCD938X_REGULATOR_MODE_MASK, 1937 WCD938X_REGULATOR_MODE_CLASS_AB); 1938 enable_irq(wcd938x->aux_pdm_wd_int); 1939 break; 1940 case SND_SOC_DAPM_PRE_PMD: 1941 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 1942 break; 1943 case SND_SOC_DAPM_POST_PMD: 1944 /* 1 msec delay as per HW requirement */ 1945 usleep_range(1000, 1010); 1946 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1947 WCD938X_AUX_PDM_WD_EN_MASK, 0); 1948 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1949 WCD_CLSH_EVENT_POST_PA, 1950 WCD_CLSH_STATE_AUX, 1951 hph_mode); 1952 1953 wcd938x->flyback_cur_det_disable--; 1954 if (wcd938x->flyback_cur_det_disable == 0) 1955 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1956 WCD938X_EN_CUR_DET_MASK, 1); 1957 break; 1958 } 1959 return 0; 1960 } 1961 1962 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 1963 struct snd_kcontrol *kcontrol, int event) 1964 { 1965 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1966 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1967 int hph_mode = wcd938x->hph_mode; 1968 1969 switch (event) { 1970 case SND_SOC_DAPM_PRE_PMU: 1971 /* 1972 * Enable watchdog interrupt for HPHL or AUX 1973 * depending on mux value 1974 */ 1975 wcd938x->ear_rx_path = snd_soc_component_read(component, 1976 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1977 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1978 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1979 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1980 else 1981 snd_soc_component_write_field(component, 1982 WCD938X_DIGITAL_PDM_WD_CTL0, 1983 WCD938X_PDM_WD_EN_MASK, 0x3); 1984 if (!wcd938x->comp1_enable) 1985 snd_soc_component_write_field(component, 1986 WCD938X_ANA_EAR_COMPANDER_CTL, 1987 WCD938X_GAIN_OVRD_REG_MASK, 1); 1988 1989 break; 1990 case SND_SOC_DAPM_POST_PMU: 1991 /* 6 msec delay as per HW requirement */ 1992 usleep_range(6000, 6010); 1993 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1994 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1995 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1996 WCD938X_REGULATOR_MODE_MASK, 1997 WCD938X_REGULATOR_MODE_CLASS_AB); 1998 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1999 enable_irq(wcd938x->aux_pdm_wd_int); 2000 else 2001 enable_irq(wcd938x->hphl_pdm_wd_int); 2002 break; 2003 case SND_SOC_DAPM_PRE_PMD: 2004 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2005 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 2006 else 2007 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 2008 break; 2009 case SND_SOC_DAPM_POST_PMD: 2010 if (!wcd938x->comp1_enable) 2011 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2012 WCD938X_GAIN_OVRD_REG_MASK, 0); 2013 /* 7 msec delay as per HW requirement */ 2014 usleep_range(7000, 7010); 2015 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2016 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 2017 WCD938X_AUX_PDM_WD_EN_MASK, 0); 2018 else 2019 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 2020 WCD938X_PDM_WD_EN_MASK, 0); 2021 2022 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 2023 WCD_CLSH_STATE_EAR, hph_mode); 2024 2025 wcd938x->flyback_cur_det_disable--; 2026 if (wcd938x->flyback_cur_det_disable == 0) 2027 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 2028 WCD938X_EN_CUR_DET_MASK, 1); 2029 break; 2030 } 2031 2032 return 0; 2033 } 2034 2035 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2036 struct snd_kcontrol *kcontrol, 2037 int event) 2038 { 2039 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2040 u16 dmic_clk_reg, dmic_clk_en_reg; 2041 u8 dmic_sel_mask, dmic_clk_mask; 2042 2043 switch (w->shift) { 2044 case 0: 2045 case 1: 2046 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2047 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 2048 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 2049 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 2050 break; 2051 case 2: 2052 case 3: 2053 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2054 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 2055 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 2056 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 2057 break; 2058 case 4: 2059 case 5: 2060 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2061 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 2062 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 2063 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 2064 break; 2065 case 6: 2066 case 7: 2067 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2068 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 2069 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 2070 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 2071 break; 2072 default: 2073 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 2074 __func__); 2075 return -EINVAL; 2076 } 2077 2078 switch (event) { 2079 case SND_SOC_DAPM_PRE_PMU: 2080 snd_soc_component_write_field(component, 2081 WCD938X_DIGITAL_CDC_AMIC_CTL, 2082 dmic_sel_mask, 2083 WCD938X_AMIC1_IN_SEL_DMIC); 2084 /* 250us sleep as per HW requirement */ 2085 usleep_range(250, 260); 2086 /* Setting DMIC clock rate to 2.4MHz */ 2087 snd_soc_component_write_field(component, dmic_clk_reg, 2088 dmic_clk_mask, 2089 WCD938X_DMIC4_RATE_2P4MHZ); 2090 snd_soc_component_write_field(component, dmic_clk_en_reg, 2091 WCD938X_DMIC_CLK_EN_MASK, 1); 2092 /* enable clock scaling */ 2093 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 2094 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 2095 break; 2096 case SND_SOC_DAPM_POST_PMD: 2097 snd_soc_component_write_field(component, 2098 WCD938X_DIGITAL_CDC_AMIC_CTL, 2099 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 2100 snd_soc_component_write_field(component, dmic_clk_en_reg, 2101 WCD938X_DMIC_CLK_EN_MASK, 0); 2102 break; 2103 } 2104 return 0; 2105 } 2106 2107 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 2108 struct snd_kcontrol *kcontrol, int event) 2109 { 2110 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2111 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2112 int bank; 2113 int rate; 2114 2115 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 2116 bank = bank ? 0 : 1; 2117 2118 switch (event) { 2119 case SND_SOC_DAPM_PRE_PMU: 2120 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2121 int i = 0, mode = 0; 2122 2123 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 2124 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 2125 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 2126 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 2127 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 2128 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 2129 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 2130 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 2131 2132 if (mode != 0) { 2133 for (i = 0; i < ADC_MODE_ULP2; i++) { 2134 if (mode & (1 << i)) { 2135 i++; 2136 break; 2137 } 2138 } 2139 } 2140 rate = wcd938x_get_clk_rate(i); 2141 wcd938x_set_swr_clk_rate(component, rate, bank); 2142 /* Copy clk settings to active bank */ 2143 wcd938x_set_swr_clk_rate(component, rate, !bank); 2144 } 2145 break; 2146 case SND_SOC_DAPM_POST_PMD: 2147 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2148 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 2149 wcd938x_set_swr_clk_rate(component, rate, !bank); 2150 wcd938x_set_swr_clk_rate(component, rate, bank); 2151 } 2152 break; 2153 } 2154 2155 return 0; 2156 } 2157 2158 static int wcd938x_get_adc_mode(int val) 2159 { 2160 int ret = 0; 2161 2162 switch (val) { 2163 case ADC_MODE_INVALID: 2164 ret = ADC_MODE_VAL_NORMAL; 2165 break; 2166 case ADC_MODE_HIFI: 2167 ret = ADC_MODE_VAL_HIFI; 2168 break; 2169 case ADC_MODE_LO_HIF: 2170 ret = ADC_MODE_VAL_LO_HIF; 2171 break; 2172 case ADC_MODE_NORMAL: 2173 ret = ADC_MODE_VAL_NORMAL; 2174 break; 2175 case ADC_MODE_LP: 2176 ret = ADC_MODE_VAL_LP; 2177 break; 2178 case ADC_MODE_ULP1: 2179 ret = ADC_MODE_VAL_ULP1; 2180 break; 2181 case ADC_MODE_ULP2: 2182 ret = ADC_MODE_VAL_ULP2; 2183 break; 2184 default: 2185 ret = -EINVAL; 2186 break; 2187 } 2188 return ret; 2189 } 2190 2191 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 2192 struct snd_kcontrol *kcontrol, int event) 2193 { 2194 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2195 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2196 2197 switch (event) { 2198 case SND_SOC_DAPM_PRE_PMU: 2199 snd_soc_component_write_field(component, 2200 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2201 WCD938X_ANA_TX_CLK_EN_MASK, 1); 2202 snd_soc_component_write_field(component, 2203 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2204 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2205 set_bit(w->shift, &wcd938x->status_mask); 2206 break; 2207 case SND_SOC_DAPM_POST_PMD: 2208 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2209 WCD938X_ANA_TX_CLK_EN_MASK, 0); 2210 clear_bit(w->shift, &wcd938x->status_mask); 2211 break; 2212 } 2213 2214 return 0; 2215 } 2216 2217 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 2218 int channel, int mode) 2219 { 2220 int reg, mask; 2221 2222 switch (channel) { 2223 case 0: 2224 reg = WCD938X_ANA_TX_CH2; 2225 mask = WCD938X_HPF1_INIT_MASK; 2226 break; 2227 case 1: 2228 reg = WCD938X_ANA_TX_CH2; 2229 mask = WCD938X_HPF2_INIT_MASK; 2230 break; 2231 case 2: 2232 reg = WCD938X_ANA_TX_CH4; 2233 mask = WCD938X_HPF3_INIT_MASK; 2234 break; 2235 case 3: 2236 reg = WCD938X_ANA_TX_CH4; 2237 mask = WCD938X_HPF4_INIT_MASK; 2238 break; 2239 default: 2240 return; 2241 } 2242 2243 snd_soc_component_write_field(component, reg, mask, mode); 2244 } 2245 2246 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 2247 struct snd_kcontrol *kcontrol, int event) 2248 { 2249 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2250 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2251 int mode; 2252 2253 switch (event) { 2254 case SND_SOC_DAPM_PRE_PMU: 2255 snd_soc_component_write_field(component, 2256 WCD938X_DIGITAL_CDC_REQ_CTL, 2257 WCD938X_FS_RATE_4P8_MASK, 1); 2258 snd_soc_component_write_field(component, 2259 WCD938X_DIGITAL_CDC_REQ_CTL, 2260 WCD938X_NO_NOTCH_MASK, 0); 2261 wcd938x_tx_channel_config(component, w->shift, 1); 2262 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 2263 if (mode < 0) { 2264 dev_info(component->dev, "Invalid ADC mode\n"); 2265 return -EINVAL; 2266 } 2267 switch (w->shift) { 2268 case 0: 2269 snd_soc_component_write_field(component, 2270 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2271 WCD938X_TXD0_MODE_MASK, mode); 2272 snd_soc_component_write_field(component, 2273 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2274 WCD938X_TXD0_CLK_EN_MASK, 1); 2275 break; 2276 case 1: 2277 snd_soc_component_write_field(component, 2278 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2279 WCD938X_TXD1_MODE_MASK, mode); 2280 snd_soc_component_write_field(component, 2281 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2282 WCD938X_TXD1_CLK_EN_MASK, 1); 2283 break; 2284 case 2: 2285 snd_soc_component_write_field(component, 2286 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2287 WCD938X_TXD2_MODE_MASK, mode); 2288 snd_soc_component_write_field(component, 2289 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2290 WCD938X_TXD2_CLK_EN_MASK, 1); 2291 break; 2292 case 3: 2293 snd_soc_component_write_field(component, 2294 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2295 WCD938X_TXD3_MODE_MASK, mode); 2296 snd_soc_component_write_field(component, 2297 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2298 WCD938X_TXD3_CLK_EN_MASK, 1); 2299 break; 2300 default: 2301 break; 2302 } 2303 2304 wcd938x_tx_channel_config(component, w->shift, 0); 2305 break; 2306 case SND_SOC_DAPM_POST_PMD: 2307 switch (w->shift) { 2308 case 0: 2309 snd_soc_component_write_field(component, 2310 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2311 WCD938X_TXD0_MODE_MASK, 0); 2312 snd_soc_component_write_field(component, 2313 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2314 WCD938X_TXD0_CLK_EN_MASK, 0); 2315 break; 2316 case 1: 2317 snd_soc_component_write_field(component, 2318 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2319 WCD938X_TXD1_MODE_MASK, 0); 2320 snd_soc_component_write_field(component, 2321 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2322 WCD938X_TXD1_CLK_EN_MASK, 0); 2323 break; 2324 case 2: 2325 snd_soc_component_write_field(component, 2326 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2327 WCD938X_TXD2_MODE_MASK, 0); 2328 snd_soc_component_write_field(component, 2329 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2330 WCD938X_TXD2_CLK_EN_MASK, 0); 2331 break; 2332 case 3: 2333 snd_soc_component_write_field(component, 2334 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2335 WCD938X_TXD3_MODE_MASK, 0); 2336 snd_soc_component_write_field(component, 2337 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2338 WCD938X_TXD3_CLK_EN_MASK, 0); 2339 break; 2340 default: 2341 break; 2342 } 2343 snd_soc_component_write_field(component, 2344 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2345 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 2346 break; 2347 } 2348 2349 return 0; 2350 } 2351 2352 static int wcd938x_micbias_control(struct snd_soc_component *component, 2353 int micb_num, int req, bool is_dapm) 2354 { 2355 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2356 int micb_index = micb_num - 1; 2357 u16 micb_reg; 2358 2359 switch (micb_num) { 2360 case MIC_BIAS_1: 2361 micb_reg = WCD938X_ANA_MICB1; 2362 break; 2363 case MIC_BIAS_2: 2364 micb_reg = WCD938X_ANA_MICB2; 2365 break; 2366 case MIC_BIAS_3: 2367 micb_reg = WCD938X_ANA_MICB3; 2368 break; 2369 case MIC_BIAS_4: 2370 micb_reg = WCD938X_ANA_MICB4; 2371 break; 2372 default: 2373 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2374 __func__, micb_num); 2375 return -EINVAL; 2376 } 2377 2378 switch (req) { 2379 case MICB_PULLUP_ENABLE: 2380 wcd938x->pullup_ref[micb_index]++; 2381 if ((wcd938x->pullup_ref[micb_index] == 1) && 2382 (wcd938x->micb_ref[micb_index] == 0)) 2383 snd_soc_component_write_field(component, micb_reg, 2384 WCD938X_MICB_EN_MASK, 2385 WCD938X_MICB_PULL_UP); 2386 break; 2387 case MICB_PULLUP_DISABLE: 2388 if (wcd938x->pullup_ref[micb_index] > 0) 2389 wcd938x->pullup_ref[micb_index]--; 2390 2391 if ((wcd938x->pullup_ref[micb_index] == 0) && 2392 (wcd938x->micb_ref[micb_index] == 0)) 2393 snd_soc_component_write_field(component, micb_reg, 2394 WCD938X_MICB_EN_MASK, 0); 2395 break; 2396 case MICB_ENABLE: 2397 wcd938x->micb_ref[micb_index]++; 2398 if (wcd938x->micb_ref[micb_index] == 1) { 2399 snd_soc_component_write_field(component, 2400 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2401 WCD938X_TX_CLK_EN_MASK, 0xF); 2402 snd_soc_component_write_field(component, 2403 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2404 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2405 snd_soc_component_write_field(component, 2406 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 2407 WCD938X_TX_SC_CLK_EN_MASK, 1); 2408 2409 snd_soc_component_write_field(component, micb_reg, 2410 WCD938X_MICB_EN_MASK, 2411 WCD938X_MICB_ENABLE); 2412 if (micb_num == MIC_BIAS_2) 2413 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2414 WCD_EVENT_POST_MICBIAS_2_ON); 2415 } 2416 if (micb_num == MIC_BIAS_2 && is_dapm) 2417 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2418 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2419 2420 2421 break; 2422 case MICB_DISABLE: 2423 if (wcd938x->micb_ref[micb_index] > 0) 2424 wcd938x->micb_ref[micb_index]--; 2425 2426 if ((wcd938x->micb_ref[micb_index] == 0) && 2427 (wcd938x->pullup_ref[micb_index] > 0)) 2428 snd_soc_component_write_field(component, micb_reg, 2429 WCD938X_MICB_EN_MASK, 2430 WCD938X_MICB_PULL_UP); 2431 else if ((wcd938x->micb_ref[micb_index] == 0) && 2432 (wcd938x->pullup_ref[micb_index] == 0)) { 2433 if (micb_num == MIC_BIAS_2) 2434 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2435 WCD_EVENT_PRE_MICBIAS_2_OFF); 2436 2437 snd_soc_component_write_field(component, micb_reg, 2438 WCD938X_MICB_EN_MASK, 0); 2439 if (micb_num == MIC_BIAS_2) 2440 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2441 WCD_EVENT_POST_MICBIAS_2_OFF); 2442 } 2443 if (is_dapm && micb_num == MIC_BIAS_2) 2444 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2445 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2446 break; 2447 } 2448 2449 return 0; 2450 } 2451 2452 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2453 struct snd_kcontrol *kcontrol, 2454 int event) 2455 { 2456 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2457 int micb_num = w->shift; 2458 2459 switch (event) { 2460 case SND_SOC_DAPM_PRE_PMU: 2461 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 2462 break; 2463 case SND_SOC_DAPM_POST_PMU: 2464 /* 1 msec delay as per HW requirement */ 2465 usleep_range(1000, 1100); 2466 break; 2467 case SND_SOC_DAPM_POST_PMD: 2468 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 2469 break; 2470 } 2471 2472 return 0; 2473 } 2474 2475 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 2476 struct snd_kcontrol *kcontrol, 2477 int event) 2478 { 2479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2480 int micb_num = w->shift; 2481 2482 switch (event) { 2483 case SND_SOC_DAPM_PRE_PMU: 2484 wcd938x_micbias_control(component, micb_num, 2485 MICB_PULLUP_ENABLE, true); 2486 break; 2487 case SND_SOC_DAPM_POST_PMU: 2488 /* 1 msec delay as per HW requirement */ 2489 usleep_range(1000, 1100); 2490 break; 2491 case SND_SOC_DAPM_POST_PMD: 2492 wcd938x_micbias_control(component, micb_num, 2493 MICB_PULLUP_DISABLE, true); 2494 break; 2495 } 2496 2497 return 0; 2498 } 2499 2500 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 2501 struct snd_ctl_elem_value *ucontrol) 2502 { 2503 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2504 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2505 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2506 int path = e->shift_l; 2507 2508 ucontrol->value.integer.value[0] = wcd938x->tx_mode[path]; 2509 2510 return 0; 2511 } 2512 2513 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 2514 struct snd_ctl_elem_value *ucontrol) 2515 { 2516 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2517 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2518 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2519 int path = e->shift_l; 2520 2521 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 2522 2523 return 1; 2524 } 2525 2526 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 2527 struct snd_ctl_elem_value *ucontrol) 2528 { 2529 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2530 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2531 2532 ucontrol->value.integer.value[0] = wcd938x->hph_mode; 2533 2534 return 0; 2535 } 2536 2537 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 2538 struct snd_ctl_elem_value *ucontrol) 2539 { 2540 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2541 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2542 2543 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 2544 2545 return 1; 2546 } 2547 2548 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 2549 struct snd_ctl_elem_value *ucontrol) 2550 { 2551 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2552 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2553 2554 if (wcd938x->comp1_enable) { 2555 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 2556 return -EINVAL; 2557 } 2558 2559 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2560 WCD938X_EAR_GAIN_MASK, 2561 ucontrol->value.integer.value[0]); 2562 2563 return 0; 2564 } 2565 2566 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 2567 struct snd_ctl_elem_value *ucontrol) 2568 { 2569 2570 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2571 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2572 struct soc_mixer_control *mc; 2573 bool hphr; 2574 2575 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2576 hphr = mc->shift; 2577 2578 if (hphr) 2579 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 2580 else 2581 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 2582 2583 return 0; 2584 } 2585 2586 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 2587 struct snd_ctl_elem_value *ucontrol) 2588 { 2589 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2590 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2591 struct wcd938x_sdw_priv *wcd; 2592 int value = ucontrol->value.integer.value[0]; 2593 struct soc_mixer_control *mc; 2594 bool hphr; 2595 2596 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2597 hphr = mc->shift; 2598 2599 wcd = wcd938x->sdw_priv[AIF1_PB]; 2600 2601 if (hphr) 2602 wcd938x->comp2_enable = value; 2603 else 2604 wcd938x->comp1_enable = value; 2605 2606 if (value) 2607 wcd938x_connect_port(wcd, mc->reg, true); 2608 else 2609 wcd938x_connect_port(wcd, mc->reg, false); 2610 2611 return 0; 2612 } 2613 2614 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 2615 struct snd_ctl_elem_value *ucontrol) 2616 { 2617 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2618 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2619 2620 ucontrol->value.integer.value[0] = wcd938x->ldoh; 2621 2622 return 0; 2623 } 2624 2625 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 2626 struct snd_ctl_elem_value *ucontrol) 2627 { 2628 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2629 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2630 2631 wcd938x->ldoh = ucontrol->value.integer.value[0]; 2632 2633 return 1; 2634 } 2635 2636 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol, 2637 struct snd_ctl_elem_value *ucontrol) 2638 { 2639 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2640 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2641 2642 ucontrol->value.integer.value[0] = wcd938x->bcs_dis; 2643 2644 return 0; 2645 } 2646 2647 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol, 2648 struct snd_ctl_elem_value *ucontrol) 2649 { 2650 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2651 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2652 2653 wcd938x->bcs_dis = ucontrol->value.integer.value[0]; 2654 2655 return 1; 2656 } 2657 2658 static const char * const tx_mode_mux_text_wcd9380[] = { 2659 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2660 }; 2661 2662 static const char * const tx_mode_mux_text[] = { 2663 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2664 "ADC_ULP1", "ADC_ULP2", 2665 }; 2666 2667 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 2668 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 2669 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 2670 "CLS_AB_LOHIFI", 2671 }; 2672 2673 static const char * const rx_hph_mode_mux_text[] = { 2674 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 2675 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 2676 }; 2677 2678 static const char * const adc2_mux_text[] = { 2679 "INP2", "INP3" 2680 }; 2681 2682 static const char * const adc3_mux_text[] = { 2683 "INP4", "INP6" 2684 }; 2685 2686 static const char * const adc4_mux_text[] = { 2687 "INP5", "INP7" 2688 }; 2689 2690 static const char * const rdac3_mux_text[] = { 2691 "RX1", "RX3" 2692 }; 2693 2694 static const char * const hdr12_mux_text[] = { 2695 "NO_HDR12", "HDR12" 2696 }; 2697 2698 static const char * const hdr34_mux_text[] = { 2699 "NO_HDR34", "HDR34" 2700 }; 2701 2702 static const struct soc_enum tx0_mode_enum_wcd9380 = 2703 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2704 tx_mode_mux_text_wcd9380); 2705 2706 static const struct soc_enum tx1_mode_enum_wcd9380 = 2707 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2708 tx_mode_mux_text_wcd9380); 2709 2710 static const struct soc_enum tx2_mode_enum_wcd9380 = 2711 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2712 tx_mode_mux_text_wcd9380); 2713 2714 static const struct soc_enum tx3_mode_enum_wcd9380 = 2715 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2716 tx_mode_mux_text_wcd9380); 2717 2718 static const struct soc_enum tx0_mode_enum_wcd9385 = 2719 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 2720 tx_mode_mux_text); 2721 2722 static const struct soc_enum tx1_mode_enum_wcd9385 = 2723 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 2724 tx_mode_mux_text); 2725 2726 static const struct soc_enum tx2_mode_enum_wcd9385 = 2727 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 2728 tx_mode_mux_text); 2729 2730 static const struct soc_enum tx3_mode_enum_wcd9385 = 2731 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 2732 tx_mode_mux_text); 2733 2734 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 2735 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 2736 rx_hph_mode_mux_text_wcd9380); 2737 2738 static const struct soc_enum rx_hph_mode_mux_enum = 2739 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 2740 rx_hph_mode_mux_text); 2741 2742 static const struct soc_enum adc2_enum = 2743 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 2744 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2745 2746 static const struct soc_enum adc3_enum = 2747 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 2748 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 2749 2750 static const struct soc_enum adc4_enum = 2751 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 2752 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 2753 2754 static const struct soc_enum hdr12_enum = 2755 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 2756 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 2757 2758 static const struct soc_enum hdr34_enum = 2759 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 2760 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 2761 2762 static const struct soc_enum rdac3_enum = 2763 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2764 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2765 2766 static const struct snd_kcontrol_new adc1_switch[] = { 2767 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2768 }; 2769 2770 static const struct snd_kcontrol_new adc2_switch[] = { 2771 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2772 }; 2773 2774 static const struct snd_kcontrol_new adc3_switch[] = { 2775 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2776 }; 2777 2778 static const struct snd_kcontrol_new adc4_switch[] = { 2779 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2780 }; 2781 2782 static const struct snd_kcontrol_new dmic1_switch[] = { 2783 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2784 }; 2785 2786 static const struct snd_kcontrol_new dmic2_switch[] = { 2787 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2788 }; 2789 2790 static const struct snd_kcontrol_new dmic3_switch[] = { 2791 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2792 }; 2793 2794 static const struct snd_kcontrol_new dmic4_switch[] = { 2795 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2796 }; 2797 2798 static const struct snd_kcontrol_new dmic5_switch[] = { 2799 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2800 }; 2801 2802 static const struct snd_kcontrol_new dmic6_switch[] = { 2803 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2804 }; 2805 2806 static const struct snd_kcontrol_new dmic7_switch[] = { 2807 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2808 }; 2809 2810 static const struct snd_kcontrol_new dmic8_switch[] = { 2811 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2812 }; 2813 2814 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2815 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2816 }; 2817 2818 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2819 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2820 }; 2821 2822 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2823 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2824 }; 2825 2826 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2827 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2828 }; 2829 2830 static const struct snd_kcontrol_new tx_adc2_mux = 2831 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2832 2833 static const struct snd_kcontrol_new tx_adc3_mux = 2834 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 2835 2836 static const struct snd_kcontrol_new tx_adc4_mux = 2837 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 2838 2839 static const struct snd_kcontrol_new tx_hdr12_mux = 2840 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 2841 2842 static const struct snd_kcontrol_new tx_hdr34_mux = 2843 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 2844 2845 static const struct snd_kcontrol_new rx_rdac3_mux = 2846 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2847 2848 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 2849 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 2850 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2851 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 2852 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2853 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 2854 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2855 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 2856 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2857 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 2858 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2859 }; 2860 2861 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 2862 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2863 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2864 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 2865 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2866 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 2867 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2868 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 2869 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2870 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 2871 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2872 }; 2873 2874 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 2875 struct snd_ctl_elem_value *ucontrol) 2876 { 2877 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2878 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2879 struct wcd938x_sdw_priv *wcd; 2880 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 2881 int dai_id = mixer->shift; 2882 int portidx = mixer->reg; 2883 2884 wcd = wcd938x->sdw_priv[dai_id]; 2885 2886 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 2887 2888 return 0; 2889 } 2890 2891 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 2892 struct snd_ctl_elem_value *ucontrol) 2893 { 2894 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2895 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2896 struct wcd938x_sdw_priv *wcd; 2897 struct soc_mixer_control *mixer = 2898 (struct soc_mixer_control *)kcontrol->private_value; 2899 int portidx = mixer->reg; 2900 int dai_id = mixer->shift; 2901 bool enable; 2902 2903 wcd = wcd938x->sdw_priv[dai_id]; 2904 2905 if (ucontrol->value.integer.value[0]) 2906 enable = true; 2907 else 2908 enable = false; 2909 2910 wcd->port_enable[portidx] = enable; 2911 2912 wcd938x_connect_port(wcd, portidx, enable); 2913 2914 return 0; 2915 2916 } 2917 2918 /* MBHC related */ 2919 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 2920 bool enable) 2921 { 2922 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 2923 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 2924 } 2925 2926 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2927 bool enable) 2928 { 2929 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 2930 WCD938X_ANA_MBHC_BIAS_EN, enable); 2931 } 2932 2933 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 2934 int *btn_low, int *btn_high, 2935 int num_btn, bool is_micbias) 2936 { 2937 int i, vth; 2938 2939 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2940 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2941 __func__, num_btn); 2942 return; 2943 } 2944 2945 for (i = 0; i < num_btn; i++) { 2946 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2947 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 2948 WCD938X_MBHC_BTN_VTH_MASK, vth); 2949 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 2950 __func__, i, btn_high[i], vth); 2951 } 2952 } 2953 2954 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2955 { 2956 u8 val; 2957 2958 if (micb_num == MIC_BIAS_2) { 2959 val = snd_soc_component_read_field(component, 2960 WCD938X_ANA_MICB2, 2961 WCD938X_ANA_MICB2_ENABLE_MASK); 2962 if (val == WCD938X_MICB_ENABLE) 2963 return true; 2964 } 2965 return false; 2966 } 2967 2968 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2969 int pull_up_cur) 2970 { 2971 /* Default pull up current to 2uA */ 2972 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 2973 pull_up_cur = HS_PULLUP_I_2P0_UA; 2974 2975 snd_soc_component_write_field(component, 2976 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 2977 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 2978 } 2979 2980 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 2981 int micb_num, int req) 2982 { 2983 return wcd938x_micbias_control(component, micb_num, req, false); 2984 } 2985 2986 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2987 bool enable) 2988 { 2989 if (enable) { 2990 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2991 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 2992 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2993 WCD938X_RAMP_EN_MASK, 1); 2994 } else { 2995 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2996 WCD938X_RAMP_EN_MASK, 0); 2997 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2998 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 2999 } 3000 } 3001 3002 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 3003 { 3004 /* min micbias voltage is 1V and maximum is 2.85V */ 3005 if (micb_mv < 1000 || micb_mv > 2850) 3006 return -EINVAL; 3007 3008 return (micb_mv - 1000) / 50; 3009 } 3010 3011 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 3012 int req_volt, int micb_num) 3013 { 3014 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3015 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 3016 3017 switch (micb_num) { 3018 case MIC_BIAS_1: 3019 micb_reg = WCD938X_ANA_MICB1; 3020 break; 3021 case MIC_BIAS_2: 3022 micb_reg = WCD938X_ANA_MICB2; 3023 break; 3024 case MIC_BIAS_3: 3025 micb_reg = WCD938X_ANA_MICB3; 3026 break; 3027 case MIC_BIAS_4: 3028 micb_reg = WCD938X_ANA_MICB4; 3029 break; 3030 default: 3031 return -EINVAL; 3032 } 3033 mutex_lock(&wcd938x->micb_lock); 3034 /* 3035 * If requested micbias voltage is same as current micbias 3036 * voltage, then just return. Otherwise, adjust voltage as 3037 * per requested value. If micbias is already enabled, then 3038 * to avoid slow micbias ramp-up or down enable pull-up 3039 * momentarily, change the micbias value and then re-enable 3040 * micbias. 3041 */ 3042 micb_en = snd_soc_component_read_field(component, micb_reg, 3043 WCD938X_MICB_EN_MASK); 3044 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 3045 WCD938X_MICB_VOUT_MASK); 3046 3047 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 3048 if (req_vout_ctl < 0) { 3049 ret = -EINVAL; 3050 goto exit; 3051 } 3052 3053 if (cur_vout_ctl == req_vout_ctl) { 3054 ret = 0; 3055 goto exit; 3056 } 3057 3058 if (micb_en == WCD938X_MICB_ENABLE) 3059 snd_soc_component_write_field(component, micb_reg, 3060 WCD938X_MICB_EN_MASK, 3061 WCD938X_MICB_PULL_UP); 3062 3063 snd_soc_component_write_field(component, micb_reg, 3064 WCD938X_MICB_VOUT_MASK, 3065 req_vout_ctl); 3066 3067 if (micb_en == WCD938X_MICB_ENABLE) { 3068 snd_soc_component_write_field(component, micb_reg, 3069 WCD938X_MICB_EN_MASK, 3070 WCD938X_MICB_ENABLE); 3071 /* 3072 * Add 2ms delay as per HW requirement after enabling 3073 * micbias 3074 */ 3075 usleep_range(2000, 2100); 3076 } 3077 exit: 3078 mutex_unlock(&wcd938x->micb_lock); 3079 return ret; 3080 } 3081 3082 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 3083 int micb_num, bool req_en) 3084 { 3085 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3086 int rc, micb_mv; 3087 3088 if (micb_num != MIC_BIAS_2) 3089 return -EINVAL; 3090 /* 3091 * If device tree micbias level is already above the minimum 3092 * voltage needed to detect threshold microphone, then do 3093 * not change the micbias, just return. 3094 */ 3095 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 3096 return 0; 3097 3098 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 3099 3100 rc = wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 3101 3102 return rc; 3103 } 3104 3105 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x, 3106 s16 *d1_a, u16 noff, 3107 int32_t *zdet) 3108 { 3109 int i; 3110 int val, val1; 3111 s16 c1; 3112 s32 x1, d1; 3113 int32_t denom; 3114 int minCode_param[] = { 3115 3277, 1639, 820, 410, 205, 103, 52, 26 3116 }; 3117 3118 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 3119 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 3120 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 3121 if (val & 0x80) 3122 break; 3123 } 3124 val = val << 0x8; 3125 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 3126 val |= val1; 3127 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 3128 x1 = WCD938X_MBHC_GET_X1(val); 3129 c1 = WCD938X_MBHC_GET_C1(val); 3130 /* If ramp is not complete, give additional 5ms */ 3131 if ((c1 < 2) && x1) 3132 usleep_range(5000, 5050); 3133 3134 if (!c1 || !x1) { 3135 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 3136 __func__, c1, x1); 3137 goto ramp_down; 3138 } 3139 d1 = d1_a[c1]; 3140 denom = (x1 * d1) - (1 << (14 - noff)); 3141 if (denom > 0) 3142 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 3143 else if (x1 < minCode_param[noff]) 3144 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 3145 3146 pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 3147 __func__, d1, c1, x1, *zdet); 3148 ramp_down: 3149 i = 0; 3150 while (x1) { 3151 regmap_read(wcd938x->regmap, 3152 WCD938X_ANA_MBHC_RESULT_1, &val); 3153 regmap_read(wcd938x->regmap, 3154 WCD938X_ANA_MBHC_RESULT_2, &val1); 3155 val = val << 0x08; 3156 val |= val1; 3157 x1 = WCD938X_MBHC_GET_X1(val); 3158 i++; 3159 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 3160 break; 3161 } 3162 } 3163 3164 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 3165 struct wcd938x_mbhc_zdet_param *zdet_param, 3166 int32_t *zl, int32_t *zr, s16 *d1_a) 3167 { 3168 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3169 int32_t zdet = 0; 3170 3171 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3172 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 3173 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 3174 WCD938X_VTH_MASK, zdet_param->btn5); 3175 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 3176 WCD938X_VTH_MASK, zdet_param->btn6); 3177 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 3178 WCD938X_VTH_MASK, zdet_param->btn7); 3179 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3180 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 3181 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 3182 0x0F, zdet_param->nshift); 3183 3184 if (!zl) 3185 goto z_right; 3186 /* Start impedance measurement for HPH_L */ 3187 regmap_update_bits(wcd938x->regmap, 3188 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 3189 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 3190 __func__, zdet_param->noff); 3191 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3192 regmap_update_bits(wcd938x->regmap, 3193 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 3194 3195 *zl = zdet; 3196 3197 z_right: 3198 if (!zr) 3199 return; 3200 /* Start impedance measurement for HPH_R */ 3201 regmap_update_bits(wcd938x->regmap, 3202 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 3203 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 3204 __func__, zdet_param->noff); 3205 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3206 regmap_update_bits(wcd938x->regmap, 3207 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 3208 3209 *zr = zdet; 3210 } 3211 3212 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 3213 int32_t *z_val, int flag_l_r) 3214 { 3215 s16 q1; 3216 int q1_cal; 3217 3218 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 3219 q1 = snd_soc_component_read(component, 3220 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 3221 else 3222 q1 = snd_soc_component_read(component, 3223 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 3224 if (q1 & 0x80) 3225 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 3226 else 3227 q1_cal = (10000 + (q1 * 25)); 3228 if (q1_cal > 0) 3229 *z_val = ((*z_val) * 10000) / q1_cal; 3230 } 3231 3232 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 3233 uint32_t *zl, uint32_t *zr) 3234 { 3235 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3236 s16 reg0, reg1, reg2, reg3, reg4; 3237 int32_t z1L, z1R, z1Ls; 3238 int zMono, z_diff1, z_diff2; 3239 bool is_fsm_disable = false; 3240 struct wcd938x_mbhc_zdet_param zdet_param[] = { 3241 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 3242 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 3243 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 3244 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 3245 }; 3246 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 3247 s16 d1_a[][4] = { 3248 {0, 30, 90, 30}, 3249 {0, 30, 30, 5}, 3250 {0, 30, 30, 5}, 3251 {0, 30, 30, 5}, 3252 }; 3253 s16 *d1 = NULL; 3254 3255 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 3256 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 3257 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 3258 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 3259 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 3260 3261 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 3262 is_fsm_disable = true; 3263 regmap_update_bits(wcd938x->regmap, 3264 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 3265 } 3266 3267 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 3268 if (wcd938x->mbhc_cfg.hphl_swh) 3269 regmap_update_bits(wcd938x->regmap, 3270 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 3271 3272 /* Turn off 100k pull down on HPHL */ 3273 regmap_update_bits(wcd938x->regmap, 3274 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 3275 3276 /* Disable surge protection before impedance detection. 3277 * This is done to give correct value for high impedance. 3278 */ 3279 regmap_update_bits(wcd938x->regmap, 3280 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 3281 /* 1ms delay needed after disable surge protection */ 3282 usleep_range(1000, 1010); 3283 3284 /* First get impedance on Left */ 3285 d1 = d1_a[1]; 3286 zdet_param_ptr = &zdet_param[1]; 3287 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3288 3289 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 3290 goto left_ch_impedance; 3291 3292 /* Second ramp for left ch */ 3293 if (z1L < WCD938X_ZDET_VAL_32) { 3294 zdet_param_ptr = &zdet_param[0]; 3295 d1 = d1_a[0]; 3296 } else if ((z1L > WCD938X_ZDET_VAL_400) && 3297 (z1L <= WCD938X_ZDET_VAL_1200)) { 3298 zdet_param_ptr = &zdet_param[2]; 3299 d1 = d1_a[2]; 3300 } else if (z1L > WCD938X_ZDET_VAL_1200) { 3301 zdet_param_ptr = &zdet_param[3]; 3302 d1 = d1_a[3]; 3303 } 3304 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3305 3306 left_ch_impedance: 3307 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3308 (z1L > WCD938X_ZDET_VAL_100K)) { 3309 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 3310 zdet_param_ptr = &zdet_param[1]; 3311 d1 = d1_a[1]; 3312 } else { 3313 *zl = z1L/1000; 3314 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 3315 } 3316 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 3317 __func__, *zl); 3318 3319 /* Start of right impedance ramp and calculation */ 3320 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3321 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 3322 if (((z1R > WCD938X_ZDET_VAL_1200) && 3323 (zdet_param_ptr->noff == 0x6)) || 3324 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 3325 goto right_ch_impedance; 3326 /* Second ramp for right ch */ 3327 if (z1R < WCD938X_ZDET_VAL_32) { 3328 zdet_param_ptr = &zdet_param[0]; 3329 d1 = d1_a[0]; 3330 } else if ((z1R > WCD938X_ZDET_VAL_400) && 3331 (z1R <= WCD938X_ZDET_VAL_1200)) { 3332 zdet_param_ptr = &zdet_param[2]; 3333 d1 = d1_a[2]; 3334 } else if (z1R > WCD938X_ZDET_VAL_1200) { 3335 zdet_param_ptr = &zdet_param[3]; 3336 d1 = d1_a[3]; 3337 } 3338 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3339 } 3340 right_ch_impedance: 3341 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3342 (z1R > WCD938X_ZDET_VAL_100K)) { 3343 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 3344 } else { 3345 *zr = z1R/1000; 3346 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 3347 } 3348 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 3349 __func__, *zr); 3350 3351 /* Mono/stereo detection */ 3352 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 3353 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 3354 dev_dbg(component->dev, 3355 "%s: plug type is invalid or extension cable\n", 3356 __func__); 3357 goto zdet_complete; 3358 } 3359 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3360 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3361 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 3362 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 3363 dev_dbg(component->dev, 3364 "%s: Mono plug type with one ch floating or shorted to GND\n", 3365 __func__); 3366 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3367 goto zdet_complete; 3368 } 3369 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3370 WCD938X_HPHPA_GND_OVR_MASK, 1); 3371 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3372 WCD938X_HPHPA_GND_R_MASK, 1); 3373 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 3374 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 3375 else 3376 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 3377 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3378 WCD938X_HPHPA_GND_R_MASK, 0); 3379 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3380 WCD938X_HPHPA_GND_OVR_MASK, 0); 3381 z1Ls /= 1000; 3382 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 3383 /* Parallel of left Z and 9 ohm pull down resistor */ 3384 zMono = ((*zl) * 9) / ((*zl) + 9); 3385 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 3386 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 3387 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 3388 dev_dbg(component->dev, "%s: stereo plug type detected\n", 3389 __func__); 3390 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 3391 } else { 3392 dev_dbg(component->dev, "%s: MONO plug type detected\n", 3393 __func__); 3394 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3395 } 3396 3397 /* Enable surge protection again after impedance detection */ 3398 regmap_update_bits(wcd938x->regmap, 3399 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 3400 zdet_complete: 3401 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 3402 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 3403 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 3404 /* Turn on 100k pull down on HPHL */ 3405 regmap_update_bits(wcd938x->regmap, 3406 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 3407 3408 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 3409 if (wcd938x->mbhc_cfg.hphl_swh) 3410 regmap_update_bits(wcd938x->regmap, 3411 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 3412 3413 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 3414 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 3415 if (is_fsm_disable) 3416 regmap_update_bits(wcd938x->regmap, 3417 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 3418 } 3419 3420 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 3421 bool enable) 3422 { 3423 if (enable) { 3424 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3425 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 3426 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3427 WCD938X_MBHC_GND_DET_EN_MASK, 1); 3428 } else { 3429 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3430 WCD938X_MBHC_GND_DET_EN_MASK, 0); 3431 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3432 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 3433 } 3434 } 3435 3436 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 3437 bool enable) 3438 { 3439 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3440 WCD938X_HPHPA_GND_R_MASK, enable); 3441 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3442 WCD938X_HPHPA_GND_L_MASK, enable); 3443 } 3444 3445 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 3446 { 3447 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3448 3449 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3450 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3451 WCD938X_M_RTH_CTL_MASK, R_OFF); 3452 return; 3453 } 3454 3455 /* Do not enable moisture detection if jack type is NC */ 3456 if (!wcd938x->mbhc_cfg.hphl_swh) { 3457 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3458 __func__); 3459 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3460 WCD938X_M_RTH_CTL_MASK, R_OFF); 3461 return; 3462 } 3463 3464 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3465 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3466 } 3467 3468 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 3469 { 3470 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3471 3472 if (enable) 3473 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3474 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3475 else 3476 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3477 WCD938X_M_RTH_CTL_MASK, R_OFF); 3478 } 3479 3480 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 3481 { 3482 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3483 bool ret = false; 3484 3485 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3486 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3487 WCD938X_M_RTH_CTL_MASK, R_OFF); 3488 goto done; 3489 } 3490 3491 /* Do not enable moisture detection if jack type is NC */ 3492 if (!wcd938x->mbhc_cfg.hphl_swh) { 3493 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3494 __func__); 3495 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3496 WCD938X_M_RTH_CTL_MASK, R_OFF); 3497 goto done; 3498 } 3499 3500 /* 3501 * If moisture_en is already enabled, then skip to plug type 3502 * detection. 3503 */ 3504 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 3505 goto done; 3506 3507 wcd938x_mbhc_moisture_detect_en(component, true); 3508 /* Read moisture comparator status */ 3509 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 3510 & 0x20) ? 0 : 1); 3511 3512 done: 3513 return ret; 3514 3515 } 3516 3517 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 3518 bool enable) 3519 { 3520 snd_soc_component_write_field(component, 3521 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 3522 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 3523 } 3524 3525 static const struct wcd_mbhc_cb mbhc_cb = { 3526 .clk_setup = wcd938x_mbhc_clk_setup, 3527 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 3528 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 3529 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 3530 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 3531 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 3532 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 3533 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 3534 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 3535 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 3536 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 3537 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 3538 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 3539 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 3540 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 3541 }; 3542 3543 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 3544 struct snd_ctl_elem_value *ucontrol) 3545 { 3546 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3547 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3548 3549 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 3550 3551 return 0; 3552 } 3553 3554 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 3555 struct snd_ctl_elem_value *ucontrol) 3556 { 3557 uint32_t zl, zr; 3558 bool hphr; 3559 struct soc_mixer_control *mc; 3560 struct snd_soc_component *component = 3561 snd_soc_kcontrol_component(kcontrol); 3562 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3563 3564 mc = (struct soc_mixer_control *)(kcontrol->private_value); 3565 hphr = mc->shift; 3566 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 3567 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 3568 ucontrol->value.integer.value[0] = hphr ? zr : zl; 3569 3570 return 0; 3571 } 3572 3573 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3574 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 3575 wcd938x_get_hph_type, NULL), 3576 }; 3577 3578 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3579 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 3580 wcd938x_hph_impedance_get, NULL), 3581 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 3582 wcd938x_hph_impedance_get, NULL), 3583 }; 3584 3585 static int wcd938x_mbhc_init(struct snd_soc_component *component) 3586 { 3587 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3588 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 3589 3590 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3591 WCD938X_IRQ_MBHC_SW_DET); 3592 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3593 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 3594 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3595 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 3596 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3597 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3598 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3599 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 3600 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3601 WCD938X_IRQ_HPHL_OCP_INT); 3602 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3603 WCD938X_IRQ_HPHR_OCP_INT); 3604 3605 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3606 3607 snd_soc_add_component_controls(component, impedance_detect_controls, 3608 ARRAY_SIZE(impedance_detect_controls)); 3609 snd_soc_add_component_controls(component, hph_type_detect_controls, 3610 ARRAY_SIZE(hph_type_detect_controls)); 3611 3612 return 0; 3613 } 3614 /* END MBHC */ 3615 3616 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 3617 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 3618 wcd938x_get_compander, wcd938x_set_compander), 3619 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 3620 wcd938x_get_compander, wcd938x_set_compander), 3621 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 3622 wcd938x_get_swr_port, wcd938x_set_swr_port), 3623 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 3624 wcd938x_get_swr_port, wcd938x_set_swr_port), 3625 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 3626 wcd938x_get_swr_port, wcd938x_set_swr_port), 3627 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 3628 wcd938x_get_swr_port, wcd938x_set_swr_port), 3629 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 3630 wcd938x_get_swr_port, wcd938x_set_swr_port), 3631 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 3632 wcd938x_get_swr_port, wcd938x_set_swr_port), 3633 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain), 3634 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain), 3635 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 3636 2, 0x10, 0, ear_pa_gain), 3637 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 3638 wcd938x_get_swr_port, wcd938x_set_swr_port), 3639 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 3640 wcd938x_get_swr_port, wcd938x_set_swr_port), 3641 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 3642 wcd938x_get_swr_port, wcd938x_set_swr_port), 3643 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 3644 wcd938x_get_swr_port, wcd938x_set_swr_port), 3645 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 3646 wcd938x_get_swr_port, wcd938x_set_swr_port), 3647 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 3648 wcd938x_get_swr_port, wcd938x_set_swr_port), 3649 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 3650 wcd938x_get_swr_port, wcd938x_set_swr_port), 3651 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 3652 wcd938x_get_swr_port, wcd938x_set_swr_port), 3653 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 3654 wcd938x_get_swr_port, wcd938x_set_swr_port), 3655 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 3656 wcd938x_get_swr_port, wcd938x_set_swr_port), 3657 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 3658 wcd938x_get_swr_port, wcd938x_set_swr_port), 3659 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 3660 wcd938x_get_swr_port, wcd938x_set_swr_port), 3661 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 3662 wcd938x_get_swr_port, wcd938x_set_swr_port), 3663 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 3664 wcd938x_ldoh_get, wcd938x_ldoh_put), 3665 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0, 3666 wcd938x_bcs_get, wcd938x_bcs_put), 3667 3668 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 3669 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 3670 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 3671 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 3672 }; 3673 3674 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 3675 3676 /*input widgets*/ 3677 SND_SOC_DAPM_INPUT("AMIC1"), 3678 SND_SOC_DAPM_INPUT("AMIC2"), 3679 SND_SOC_DAPM_INPUT("AMIC3"), 3680 SND_SOC_DAPM_INPUT("AMIC4"), 3681 SND_SOC_DAPM_INPUT("AMIC5"), 3682 SND_SOC_DAPM_INPUT("AMIC6"), 3683 SND_SOC_DAPM_INPUT("AMIC7"), 3684 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 3685 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 3686 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 3687 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 3688 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 3689 3690 /*tx widgets*/ 3691 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 3692 wcd938x_codec_enable_adc, 3693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3694 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 3695 wcd938x_codec_enable_adc, 3696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3697 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 3698 wcd938x_codec_enable_adc, 3699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3700 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 3701 wcd938x_codec_enable_adc, 3702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3703 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 3704 wcd938x_codec_enable_dmic, 3705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3706 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 3707 wcd938x_codec_enable_dmic, 3708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3709 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 3710 wcd938x_codec_enable_dmic, 3711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3712 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 3713 wcd938x_codec_enable_dmic, 3714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3715 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 3716 wcd938x_codec_enable_dmic, 3717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3718 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 3719 wcd938x_codec_enable_dmic, 3720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3721 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 3722 wcd938x_codec_enable_dmic, 3723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3724 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 3725 wcd938x_codec_enable_dmic, 3726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3727 3728 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 3729 NULL, 0, wcd938x_adc_enable_req, 3730 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3731 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 3732 NULL, 0, wcd938x_adc_enable_req, 3733 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3734 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 3735 NULL, 0, wcd938x_adc_enable_req, 3736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3737 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 3738 wcd938x_adc_enable_req, 3739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3740 3741 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 3742 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 3743 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 3744 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 3745 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 3746 3747 /*tx mixers*/ 3748 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 3749 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 3750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3751 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 3752 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 3753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3754 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 3755 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 3756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3757 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 3758 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 3759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3760 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 3761 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 3762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3763 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 3764 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 3765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3766 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 3767 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 3768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3769 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 3770 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 3771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3772 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 3773 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 3774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3775 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 3776 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 3777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3778 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 3779 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 3780 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3781 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 3782 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 3783 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3784 /* micbias widgets*/ 3785 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3786 wcd938x_codec_enable_micbias, 3787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3788 SND_SOC_DAPM_POST_PMD), 3789 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3790 wcd938x_codec_enable_micbias, 3791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3792 SND_SOC_DAPM_POST_PMD), 3793 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3794 wcd938x_codec_enable_micbias, 3795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3796 SND_SOC_DAPM_POST_PMD), 3797 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3798 wcd938x_codec_enable_micbias, 3799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3800 SND_SOC_DAPM_POST_PMD), 3801 3802 /* micbias pull up widgets*/ 3803 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3804 wcd938x_codec_enable_micbias_pullup, 3805 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3806 SND_SOC_DAPM_POST_PMD), 3807 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3808 wcd938x_codec_enable_micbias_pullup, 3809 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3810 SND_SOC_DAPM_POST_PMD), 3811 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3812 wcd938x_codec_enable_micbias_pullup, 3813 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3814 SND_SOC_DAPM_POST_PMD), 3815 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3816 wcd938x_codec_enable_micbias_pullup, 3817 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3818 SND_SOC_DAPM_POST_PMD), 3819 3820 /*output widgets tx*/ 3821 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 3822 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 3823 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 3824 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 3825 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 3826 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 3827 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 3828 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 3829 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 3830 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 3831 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 3832 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 3833 3834 SND_SOC_DAPM_INPUT("IN1_HPHL"), 3835 SND_SOC_DAPM_INPUT("IN2_HPHR"), 3836 SND_SOC_DAPM_INPUT("IN3_AUX"), 3837 3838 /*rx widgets*/ 3839 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 3840 wcd938x_codec_enable_ear_pa, 3841 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3842 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3843 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 3844 wcd938x_codec_enable_aux_pa, 3845 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3846 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3847 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 3848 wcd938x_codec_enable_hphl_pa, 3849 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3850 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3851 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 3852 wcd938x_codec_enable_hphr_pa, 3853 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3854 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3855 3856 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 3857 wcd938x_codec_hphl_dac_event, 3858 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3859 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3860 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 3861 wcd938x_codec_hphr_dac_event, 3862 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3863 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3864 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 3865 wcd938x_codec_ear_dac_event, 3866 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3867 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3868 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 3869 wcd938x_codec_aux_dac_event, 3870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3871 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3872 3873 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 3874 3875 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 3876 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 3877 wcd938x_codec_enable_rxclk, 3878 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3879 SND_SOC_DAPM_POST_PMD), 3880 3881 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 3882 3883 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3884 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3885 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3886 3887 /* rx mixer widgets*/ 3888 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 3889 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 3890 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 3891 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 3892 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 3893 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 3894 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 3895 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 3896 3897 /*output widgets rx*/ 3898 SND_SOC_DAPM_OUTPUT("EAR"), 3899 SND_SOC_DAPM_OUTPUT("AUX"), 3900 SND_SOC_DAPM_OUTPUT("HPHL"), 3901 SND_SOC_DAPM_OUTPUT("HPHR"), 3902 3903 }; 3904 3905 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 3906 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 3907 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 3908 {"ADC1 REQ", NULL, "ADC1"}, 3909 {"ADC1", NULL, "AMIC1"}, 3910 3911 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 3912 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 3913 {"ADC2 REQ", NULL, "ADC2"}, 3914 {"ADC2", NULL, "HDR12 MUX"}, 3915 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 3916 {"HDR12 MUX", "HDR12", "AMIC1"}, 3917 {"ADC2 MUX", "INP3", "AMIC3"}, 3918 {"ADC2 MUX", "INP2", "AMIC2"}, 3919 3920 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 3921 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 3922 {"ADC3 REQ", NULL, "ADC3"}, 3923 {"ADC3", NULL, "HDR34 MUX"}, 3924 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 3925 {"HDR34 MUX", "HDR34", "AMIC5"}, 3926 {"ADC3 MUX", "INP4", "AMIC4"}, 3927 {"ADC3 MUX", "INP6", "AMIC6"}, 3928 3929 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 3930 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 3931 {"ADC4 REQ", NULL, "ADC4"}, 3932 {"ADC4", NULL, "ADC4 MUX"}, 3933 {"ADC4 MUX", "INP5", "AMIC5"}, 3934 {"ADC4 MUX", "INP7", "AMIC7"}, 3935 3936 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 3937 {"DMIC1_MIXER", "Switch", "DMIC1"}, 3938 3939 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 3940 {"DMIC2_MIXER", "Switch", "DMIC2"}, 3941 3942 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 3943 {"DMIC3_MIXER", "Switch", "DMIC3"}, 3944 3945 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 3946 {"DMIC4_MIXER", "Switch", "DMIC4"}, 3947 3948 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 3949 {"DMIC5_MIXER", "Switch", "DMIC5"}, 3950 3951 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 3952 {"DMIC6_MIXER", "Switch", "DMIC6"}, 3953 3954 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 3955 {"DMIC7_MIXER", "Switch", "DMIC7"}, 3956 3957 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 3958 {"DMIC8_MIXER", "Switch", "DMIC8"}, 3959 3960 {"IN1_HPHL", NULL, "VDD_BUCK"}, 3961 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 3962 3963 {"RX1", NULL, "IN1_HPHL"}, 3964 {"RX1", NULL, "RXCLK"}, 3965 {"RDAC1", NULL, "RX1"}, 3966 {"HPHL_RDAC", "Switch", "RDAC1"}, 3967 {"HPHL PGA", NULL, "HPHL_RDAC"}, 3968 {"HPHL", NULL, "HPHL PGA"}, 3969 3970 {"IN2_HPHR", NULL, "VDD_BUCK"}, 3971 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 3972 {"RX2", NULL, "IN2_HPHR"}, 3973 {"RDAC2", NULL, "RX2"}, 3974 {"RX2", NULL, "RXCLK"}, 3975 {"HPHR_RDAC", "Switch", "RDAC2"}, 3976 {"HPHR PGA", NULL, "HPHR_RDAC"}, 3977 {"HPHR", NULL, "HPHR PGA"}, 3978 3979 {"IN3_AUX", NULL, "VDD_BUCK"}, 3980 {"IN3_AUX", NULL, "CLS_H_PORT"}, 3981 {"RX3", NULL, "IN3_AUX"}, 3982 {"RDAC4", NULL, "RX3"}, 3983 {"RX3", NULL, "RXCLK"}, 3984 {"AUX_RDAC", "Switch", "RDAC4"}, 3985 {"AUX PGA", NULL, "AUX_RDAC"}, 3986 {"AUX", NULL, "AUX PGA"}, 3987 3988 {"RDAC3_MUX", "RX3", "RX3"}, 3989 {"RDAC3_MUX", "RX1", "RX1"}, 3990 {"RDAC3", NULL, "RDAC3_MUX"}, 3991 {"EAR_RDAC", "Switch", "RDAC3"}, 3992 {"EAR PGA", NULL, "EAR_RDAC"}, 3993 {"EAR", NULL, "EAR PGA"}, 3994 }; 3995 3996 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 3997 { 3998 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 3999 4000 /* set micbias voltage */ 4001 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 4002 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 4003 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 4004 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 4005 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 4006 return -EINVAL; 4007 4008 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 4009 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 4010 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 4011 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 4012 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 4013 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 4014 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 4015 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 4016 4017 return 0; 4018 } 4019 4020 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 4021 { 4022 return IRQ_HANDLED; 4023 } 4024 4025 static struct irq_chip wcd_irq_chip = { 4026 .name = "WCD938x", 4027 }; 4028 4029 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 4030 irq_hw_number_t hw) 4031 { 4032 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 4033 irq_set_nested_thread(virq, 1); 4034 irq_set_noprobe(virq); 4035 4036 return 0; 4037 } 4038 4039 static const struct irq_domain_ops wcd_domain_ops = { 4040 .map = wcd_irq_chip_map, 4041 }; 4042 4043 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 4044 { 4045 4046 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 4047 if (!(wcd->virq)) { 4048 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 4049 return -EINVAL; 4050 } 4051 4052 return devm_regmap_add_irq_chip(dev, wcd->regmap, 4053 irq_create_mapping(wcd->virq, 0), 4054 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 4055 &wcd->irq_chip); 4056 } 4057 4058 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 4059 { 4060 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 4061 struct device *dev = component->dev; 4062 int ret, i; 4063 4064 snd_soc_component_init_regmap(component, wcd938x->regmap); 4065 4066 wcd938x->variant = snd_soc_component_read_field(component, 4067 WCD938X_DIGITAL_EFUSE_REG_0, 4068 WCD938X_ID_MASK); 4069 4070 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 4071 4072 wcd938x_io_init(wcd938x); 4073 /* Set all interrupts as edge triggered */ 4074 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 4075 regmap_write(wcd938x->regmap, 4076 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 4077 } 4078 4079 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4080 WCD938X_IRQ_HPHR_PDM_WD_INT); 4081 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4082 WCD938X_IRQ_HPHL_PDM_WD_INT); 4083 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4084 WCD938X_IRQ_AUX_PDM_WD_INT); 4085 4086 /* Request for watchdog interrupt */ 4087 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4088 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4089 "HPHR PDM WD INT", wcd938x); 4090 if (ret) 4091 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 4092 4093 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4094 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4095 "HPHL PDM WD INT", wcd938x); 4096 if (ret) 4097 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 4098 4099 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4100 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4101 "AUX PDM WD INT", wcd938x); 4102 if (ret) 4103 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 4104 4105 /* Disable watchdog interrupt for HPH and AUX */ 4106 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 4107 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 4108 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 4109 4110 switch (wcd938x->variant) { 4111 case WCD9380: 4112 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 4113 ARRAY_SIZE(wcd9380_snd_controls)); 4114 if (ret < 0) { 4115 dev_err(component->dev, 4116 "%s: Failed to add snd ctrls for variant: %d\n", 4117 __func__, wcd938x->variant); 4118 goto err; 4119 } 4120 break; 4121 case WCD9385: 4122 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 4123 ARRAY_SIZE(wcd9385_snd_controls)); 4124 if (ret < 0) { 4125 dev_err(component->dev, 4126 "%s: Failed to add snd ctrls for variant: %d\n", 4127 __func__, wcd938x->variant); 4128 goto err; 4129 } 4130 break; 4131 default: 4132 break; 4133 } 4134 4135 ret = wcd938x_mbhc_init(component); 4136 if (ret) 4137 dev_err(component->dev, "mbhc initialization failed\n"); 4138 err: 4139 return ret; 4140 } 4141 4142 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 4143 struct snd_soc_jack *jack, void *data) 4144 { 4145 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 4146 4147 if (jack) 4148 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 4149 else 4150 wcd_mbhc_stop(wcd->wcd_mbhc); 4151 4152 return 0; 4153 } 4154 4155 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 4156 .name = "wcd938x_codec", 4157 .probe = wcd938x_soc_codec_probe, 4158 .controls = wcd938x_snd_controls, 4159 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 4160 .dapm_widgets = wcd938x_dapm_widgets, 4161 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 4162 .dapm_routes = wcd938x_audio_map, 4163 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 4164 .set_jack = wcd938x_codec_set_jack, 4165 }; 4166 4167 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 4168 { 4169 struct device_node *np = dev->of_node; 4170 u32 prop_val = 0; 4171 int rc = 0; 4172 4173 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 4174 if (!rc) 4175 wcd->micb1_mv = prop_val/1000; 4176 else 4177 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 4178 4179 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 4180 if (!rc) 4181 wcd->micb2_mv = prop_val/1000; 4182 else 4183 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 4184 4185 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 4186 if (!rc) 4187 wcd->micb3_mv = prop_val/1000; 4188 else 4189 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 4190 4191 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 4192 if (!rc) 4193 wcd->micb4_mv = prop_val/1000; 4194 else 4195 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 4196 } 4197 4198 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 4199 { 4200 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 4201 int ret; 4202 4203 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0); 4204 if (wcd938x->reset_gpio < 0) { 4205 dev_err(dev, "Failed to get reset gpio: err = %d\n", 4206 wcd938x->reset_gpio); 4207 return wcd938x->reset_gpio; 4208 } 4209 4210 wcd938x->supplies[0].supply = "vdd-rxtx"; 4211 wcd938x->supplies[1].supply = "vdd-io"; 4212 wcd938x->supplies[2].supply = "vdd-buck"; 4213 wcd938x->supplies[3].supply = "vdd-mic-bias"; 4214 4215 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies); 4216 if (ret) { 4217 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 4218 return ret; 4219 } 4220 4221 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 4222 if (ret) { 4223 dev_err(dev, "Failed to enable supplies: err = %d\n", ret); 4224 return ret; 4225 } 4226 4227 wcd938x_dt_parse_micbias_info(dev, wcd938x); 4228 4229 cfg->mbhc_micbias = MIC_BIAS_2; 4230 cfg->anc_micbias = MIC_BIAS_2; 4231 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 4232 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 4233 cfg->micb_mv = wcd938x->micb2_mv; 4234 cfg->linein_th = 5000; 4235 cfg->hs_thr = 1700; 4236 cfg->hph_thr = 50; 4237 4238 wcd_dt_parse_mbhc_data(dev, cfg); 4239 4240 return 0; 4241 } 4242 4243 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 4244 { 4245 gpio_direction_output(wcd938x->reset_gpio, 0); 4246 /* 20us sleep required after pulling the reset gpio to LOW */ 4247 usleep_range(20, 30); 4248 gpio_set_value(wcd938x->reset_gpio, 1); 4249 /* 20us sleep required after pulling the reset gpio to HIGH */ 4250 usleep_range(20, 30); 4251 4252 return 0; 4253 } 4254 4255 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 4256 struct snd_pcm_hw_params *params, 4257 struct snd_soc_dai *dai) 4258 { 4259 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4260 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4261 4262 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 4263 } 4264 4265 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 4266 struct snd_soc_dai *dai) 4267 { 4268 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4269 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4270 4271 return wcd938x_sdw_free(wcd, substream, dai); 4272 } 4273 4274 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 4275 void *stream, int direction) 4276 { 4277 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4278 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4279 4280 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 4281 4282 } 4283 4284 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 4285 .hw_params = wcd938x_codec_hw_params, 4286 .hw_free = wcd938x_codec_free, 4287 .set_sdw_stream = wcd938x_codec_set_sdw_stream, 4288 }; 4289 4290 static struct snd_soc_dai_driver wcd938x_dais[] = { 4291 [0] = { 4292 .name = "wcd938x-sdw-rx", 4293 .playback = { 4294 .stream_name = "WCD AIF1 Playback", 4295 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 4296 .formats = WCD938X_FORMATS_S16_S24_LE, 4297 .rate_max = 192000, 4298 .rate_min = 8000, 4299 .channels_min = 1, 4300 .channels_max = 2, 4301 }, 4302 .ops = &wcd938x_sdw_dai_ops, 4303 }, 4304 [1] = { 4305 .name = "wcd938x-sdw-tx", 4306 .capture = { 4307 .stream_name = "WCD AIF1 Capture", 4308 .rates = WCD938X_RATES_MASK, 4309 .formats = SNDRV_PCM_FMTBIT_S16_LE, 4310 .rate_min = 8000, 4311 .rate_max = 192000, 4312 .channels_min = 1, 4313 .channels_max = 4, 4314 }, 4315 .ops = &wcd938x_sdw_dai_ops, 4316 }, 4317 }; 4318 4319 static int wcd938x_bind(struct device *dev) 4320 { 4321 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4322 int ret; 4323 4324 ret = component_bind_all(dev, wcd938x); 4325 if (ret) { 4326 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 4327 __func__, ret); 4328 return ret; 4329 } 4330 4331 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 4332 if (!wcd938x->rxdev) { 4333 dev_err(dev, "could not find slave with matching of node\n"); 4334 return -EINVAL; 4335 } 4336 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 4337 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 4338 4339 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 4340 if (!wcd938x->txdev) { 4341 dev_err(dev, "could not find txslave with matching of node\n"); 4342 return -EINVAL; 4343 } 4344 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 4345 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 4346 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 4347 if (!wcd938x->tx_sdw_dev) { 4348 dev_err(dev, "could not get txslave with matching of dev\n"); 4349 return -EINVAL; 4350 } 4351 4352 /* As TX is main CSR reg interface, which should not be suspended first. 4353 * expicilty add the dependency link */ 4354 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 4355 DL_FLAG_PM_RUNTIME)) { 4356 dev_err(dev, "could not devlink tx and rx\n"); 4357 return -EINVAL; 4358 } 4359 4360 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 4361 DL_FLAG_PM_RUNTIME)) { 4362 dev_err(dev, "could not devlink wcd and tx\n"); 4363 return -EINVAL; 4364 } 4365 4366 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 4367 DL_FLAG_PM_RUNTIME)) { 4368 dev_err(dev, "could not devlink wcd and rx\n"); 4369 return -EINVAL; 4370 } 4371 4372 wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config); 4373 if (IS_ERR(wcd938x->regmap)) { 4374 dev_err(dev, "%s: tx csr regmap not found\n", __func__); 4375 return PTR_ERR(wcd938x->regmap); 4376 } 4377 4378 ret = wcd938x_irq_init(wcd938x, dev); 4379 if (ret) { 4380 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 4381 return ret; 4382 } 4383 4384 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 4385 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 4386 4387 ret = wcd938x_set_micbias_data(wcd938x); 4388 if (ret < 0) { 4389 dev_err(dev, "%s: bad micbias pdata\n", __func__); 4390 return ret; 4391 } 4392 4393 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 4394 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 4395 if (ret) 4396 dev_err(dev, "%s: Codec registration failed\n", 4397 __func__); 4398 4399 return ret; 4400 4401 } 4402 4403 static void wcd938x_unbind(struct device *dev) 4404 { 4405 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4406 4407 device_link_remove(dev, wcd938x->txdev); 4408 device_link_remove(dev, wcd938x->rxdev); 4409 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 4410 snd_soc_unregister_component(dev); 4411 component_unbind_all(dev, wcd938x); 4412 } 4413 4414 static const struct component_master_ops wcd938x_comp_ops = { 4415 .bind = wcd938x_bind, 4416 .unbind = wcd938x_unbind, 4417 }; 4418 4419 static int wcd938x_compare_of(struct device *dev, void *data) 4420 { 4421 return dev->of_node == data; 4422 } 4423 4424 static void wcd938x_release_of(struct device *dev, void *data) 4425 { 4426 of_node_put(data); 4427 } 4428 4429 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 4430 struct device *dev, 4431 struct component_match **matchptr) 4432 { 4433 struct device_node *np; 4434 4435 np = dev->of_node; 4436 4437 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 4438 if (!wcd938x->rxnode) { 4439 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 4440 return -ENODEV; 4441 } 4442 4443 of_node_get(wcd938x->rxnode); 4444 component_match_add_release(dev, matchptr, wcd938x_release_of, 4445 wcd938x_compare_of, wcd938x->rxnode); 4446 4447 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 4448 if (!wcd938x->txnode) { 4449 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 4450 return -ENODEV; 4451 } 4452 of_node_get(wcd938x->txnode); 4453 component_match_add_release(dev, matchptr, wcd938x_release_of, 4454 wcd938x_compare_of, wcd938x->txnode); 4455 return 0; 4456 } 4457 4458 static int wcd938x_probe(struct platform_device *pdev) 4459 { 4460 struct component_match *match = NULL; 4461 struct wcd938x_priv *wcd938x = NULL; 4462 struct device *dev = &pdev->dev; 4463 int ret; 4464 4465 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 4466 GFP_KERNEL); 4467 if (!wcd938x) 4468 return -ENOMEM; 4469 4470 dev_set_drvdata(dev, wcd938x); 4471 mutex_init(&wcd938x->micb_lock); 4472 4473 ret = wcd938x_populate_dt_data(wcd938x, dev); 4474 if (ret) { 4475 dev_err(dev, "%s: Fail to obtain platform data\n", __func__); 4476 return -EINVAL; 4477 } 4478 4479 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 4480 if (ret) 4481 return ret; 4482 4483 wcd938x_reset(wcd938x); 4484 4485 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 4486 if (ret) 4487 return ret; 4488 4489 pm_runtime_set_autosuspend_delay(dev, 1000); 4490 pm_runtime_use_autosuspend(dev); 4491 pm_runtime_mark_last_busy(dev); 4492 pm_runtime_set_active(dev); 4493 pm_runtime_enable(dev); 4494 pm_runtime_idle(dev); 4495 4496 return 0; 4497 } 4498 4499 static int wcd938x_remove(struct platform_device *pdev) 4500 { 4501 component_master_del(&pdev->dev, &wcd938x_comp_ops); 4502 4503 return 0; 4504 } 4505 4506 #if defined(CONFIG_OF) 4507 static const struct of_device_id wcd938x_dt_match[] = { 4508 { .compatible = "qcom,wcd9380-codec" }, 4509 { .compatible = "qcom,wcd9385-codec" }, 4510 {} 4511 }; 4512 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 4513 #endif 4514 4515 static struct platform_driver wcd938x_codec_driver = { 4516 .probe = wcd938x_probe, 4517 .remove = wcd938x_remove, 4518 .driver = { 4519 .name = "wcd938x_codec", 4520 .of_match_table = of_match_ptr(wcd938x_dt_match), 4521 .suppress_bind_attrs = true, 4522 }, 4523 }; 4524 4525 module_platform_driver(wcd938x_codec_driver); 4526 MODULE_DESCRIPTION("WCD938X Codec driver"); 4527 MODULE_LICENSE("GPL"); 4528