1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/kernel.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/component.h> 13 #include <sound/tlv.h> 14 #include <linux/of_gpio.h> 15 #include <linux/of.h> 16 #include <sound/jack.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <linux/regmap.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd938x.h" 27 28 #define WCD938X_MAX_MICBIAS (4) 29 #define WCD938X_MAX_SUPPLY (4) 30 #define WCD938X_MBHC_MAX_BUTTONS (8) 31 #define TX_ADC_MAX (4) 32 #define WCD938X_TX_MAX_SWR_PORTS (5) 33 34 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 35 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 36 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 37 /* Fractional Rates */ 38 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 39 SNDRV_PCM_RATE_176400) 40 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 41 SNDRV_PCM_FMTBIT_S24_LE) 42 /* Convert from vout ctl to micbias voltage in mV */ 43 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50) 44 #define SWR_CLK_RATE_0P6MHZ (600000) 45 #define SWR_CLK_RATE_1P2MHZ (1200000) 46 #define SWR_CLK_RATE_2P4MHZ (2400000) 47 #define SWR_CLK_RATE_4P8MHZ (4800000) 48 #define SWR_CLK_RATE_9P6MHZ (9600000) 49 #define SWR_CLK_RATE_11P2896MHZ (1128960) 50 51 #define WCD938X_DRV_NAME "wcd938x_codec" 52 #define WCD938X_VERSION_1_0 (1) 53 #define EAR_RX_PATH_AUX (1) 54 55 #define ADC_MODE_VAL_HIFI 0x01 56 #define ADC_MODE_VAL_LO_HIF 0x02 57 #define ADC_MODE_VAL_NORMAL 0x03 58 #define ADC_MODE_VAL_LP 0x05 59 #define ADC_MODE_VAL_ULP1 0x09 60 #define ADC_MODE_VAL_ULP2 0x0B 61 62 /* Z value defined in milliohm */ 63 #define WCD938X_ZDET_VAL_32 (32000) 64 #define WCD938X_ZDET_VAL_400 (400000) 65 #define WCD938X_ZDET_VAL_1200 (1200000) 66 #define WCD938X_ZDET_VAL_100K (100000000) 67 /* Z floating defined in ohms */ 68 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 69 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 70 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 71 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 72 /* Z value compared in milliOhm */ 73 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 74 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 75 #define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM 76 #define WCD_MBHC_HS_V_MAX 1600 77 78 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 79 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 80 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 81 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 82 .tlv.p = (tlv_array), \ 83 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 84 .put = wcd938x_ear_pa_put_gain, \ 85 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 86 87 enum { 88 WCD9380 = 0, 89 WCD9385 = 5, 90 }; 91 92 enum { 93 TX_HDR12 = 0, 94 TX_HDR34, 95 TX_HDR_MAX, 96 }; 97 98 enum { 99 WCD_RX1, 100 WCD_RX2, 101 WCD_RX3 102 }; 103 104 enum { 105 /* INTR_CTRL_INT_MASK_0 */ 106 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 107 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 108 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 109 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 110 WCD938X_IRQ_MBHC_SW_DET, 111 WCD938X_IRQ_HPHR_OCP_INT, 112 WCD938X_IRQ_HPHR_CNP_INT, 113 WCD938X_IRQ_HPHL_OCP_INT, 114 115 /* INTR_CTRL_INT_MASK_1 */ 116 WCD938X_IRQ_HPHL_CNP_INT, 117 WCD938X_IRQ_EAR_CNP_INT, 118 WCD938X_IRQ_EAR_SCD_INT, 119 WCD938X_IRQ_AUX_CNP_INT, 120 WCD938X_IRQ_AUX_SCD_INT, 121 WCD938X_IRQ_HPHL_PDM_WD_INT, 122 WCD938X_IRQ_HPHR_PDM_WD_INT, 123 WCD938X_IRQ_AUX_PDM_WD_INT, 124 125 /* INTR_CTRL_INT_MASK_2 */ 126 WCD938X_IRQ_LDORT_SCD_INT, 127 WCD938X_IRQ_MBHC_MOISTURE_INT, 128 WCD938X_IRQ_HPHL_SURGE_DET_INT, 129 WCD938X_IRQ_HPHR_SURGE_DET_INT, 130 WCD938X_NUM_IRQS, 131 }; 132 133 enum { 134 WCD_ADC1 = 0, 135 WCD_ADC2, 136 WCD_ADC3, 137 WCD_ADC4, 138 ALLOW_BUCK_DISABLE, 139 HPH_COMP_DELAY, 140 HPH_PA_DELAY, 141 AMIC2_BCS_ENABLE, 142 WCD_SUPPLIES_LPM_MODE, 143 }; 144 145 enum { 146 ADC_MODE_INVALID = 0, 147 ADC_MODE_HIFI, 148 ADC_MODE_LO_HIF, 149 ADC_MODE_NORMAL, 150 ADC_MODE_LP, 151 ADC_MODE_ULP1, 152 ADC_MODE_ULP2, 153 }; 154 155 enum { 156 AIF1_PB = 0, 157 AIF1_CAP, 158 NUM_CODEC_DAIS, 159 }; 160 161 static u8 tx_mode_bit[] = { 162 [ADC_MODE_INVALID] = 0x00, 163 [ADC_MODE_HIFI] = 0x01, 164 [ADC_MODE_LO_HIF] = 0x02, 165 [ADC_MODE_NORMAL] = 0x04, 166 [ADC_MODE_LP] = 0x08, 167 [ADC_MODE_ULP1] = 0x10, 168 [ADC_MODE_ULP2] = 0x20, 169 }; 170 171 struct wcd938x_priv { 172 struct sdw_slave *tx_sdw_dev; 173 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 174 struct device *txdev; 175 struct device *rxdev; 176 struct device_node *rxnode, *txnode; 177 struct regmap *regmap; 178 struct mutex micb_lock; 179 /* mbhc module */ 180 struct wcd_mbhc *wcd_mbhc; 181 struct wcd_mbhc_config mbhc_cfg; 182 struct wcd_mbhc_intr intr_ids; 183 struct wcd_clsh_ctrl *clsh_info; 184 struct irq_domain *virq; 185 struct regmap_irq_chip *wcd_regmap_irq_chip; 186 struct regmap_irq_chip_data *irq_chip; 187 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY]; 188 struct snd_soc_jack *jack; 189 unsigned long status_mask; 190 s32 micb_ref[WCD938X_MAX_MICBIAS]; 191 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 192 u32 hph_mode; 193 u32 tx_mode[TX_ADC_MAX]; 194 int flyback_cur_det_disable; 195 int ear_rx_path; 196 int variant; 197 int reset_gpio; 198 struct gpio_desc *us_euro_gpio; 199 u32 micb1_mv; 200 u32 micb2_mv; 201 u32 micb3_mv; 202 u32 micb4_mv; 203 int hphr_pdm_wd_int; 204 int hphl_pdm_wd_int; 205 int aux_pdm_wd_int; 206 bool comp1_enable; 207 bool comp2_enable; 208 bool ldoh; 209 bool bcs_dis; 210 }; 211 212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 213 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000); 214 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 215 216 struct wcd938x_mbhc_zdet_param { 217 u16 ldo_ctl; 218 u16 noff; 219 u16 nshift; 220 u16 btn5; 221 u16 btn6; 222 u16 btn7; 223 }; 224 225 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 226 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 227 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 228 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 229 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 230 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 231 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 232 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 233 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 234 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 235 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 236 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 237 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 238 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 239 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 240 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 241 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 242 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 243 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 244 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 245 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 246 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 247 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 248 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 250 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 251 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 252 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 253 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 254 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 255 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 256 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 257 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 258 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 259 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 262 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 263 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 264 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 265 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 267 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 268 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 269 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 270 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 271 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 272 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 273 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 274 }; 275 276 static const struct reg_default wcd938x_defaults[] = { 277 {WCD938X_ANA_PAGE_REGISTER, 0x00}, 278 {WCD938X_ANA_BIAS, 0x00}, 279 {WCD938X_ANA_RX_SUPPLIES, 0x00}, 280 {WCD938X_ANA_HPH, 0x0C}, 281 {WCD938X_ANA_EAR, 0x00}, 282 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, 283 {WCD938X_ANA_TX_CH1, 0x20}, 284 {WCD938X_ANA_TX_CH2, 0x00}, 285 {WCD938X_ANA_TX_CH3, 0x20}, 286 {WCD938X_ANA_TX_CH4, 0x00}, 287 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, 288 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, 289 {WCD938X_ANA_MBHC_MECH, 0x39}, 290 {WCD938X_ANA_MBHC_ELECT, 0x08}, 291 {WCD938X_ANA_MBHC_ZDET, 0x00}, 292 {WCD938X_ANA_MBHC_RESULT_1, 0x00}, 293 {WCD938X_ANA_MBHC_RESULT_2, 0x00}, 294 {WCD938X_ANA_MBHC_RESULT_3, 0x00}, 295 {WCD938X_ANA_MBHC_BTN0, 0x00}, 296 {WCD938X_ANA_MBHC_BTN1, 0x10}, 297 {WCD938X_ANA_MBHC_BTN2, 0x20}, 298 {WCD938X_ANA_MBHC_BTN3, 0x30}, 299 {WCD938X_ANA_MBHC_BTN4, 0x40}, 300 {WCD938X_ANA_MBHC_BTN5, 0x50}, 301 {WCD938X_ANA_MBHC_BTN6, 0x60}, 302 {WCD938X_ANA_MBHC_BTN7, 0x70}, 303 {WCD938X_ANA_MICB1, 0x10}, 304 {WCD938X_ANA_MICB2, 0x10}, 305 {WCD938X_ANA_MICB2_RAMP, 0x00}, 306 {WCD938X_ANA_MICB3, 0x10}, 307 {WCD938X_ANA_MICB4, 0x10}, 308 {WCD938X_BIAS_CTL, 0x2A}, 309 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, 310 {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, 311 {WCD938X_LDOL_DISABLE_LDOL, 0x00}, 312 {WCD938X_MBHC_CTL_CLK, 0x00}, 313 {WCD938X_MBHC_CTL_ANA, 0x00}, 314 {WCD938X_MBHC_CTL_SPARE_1, 0x00}, 315 {WCD938X_MBHC_CTL_SPARE_2, 0x00}, 316 {WCD938X_MBHC_CTL_BCS, 0x00}, 317 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, 318 {WCD938X_MBHC_TEST_CTL, 0x00}, 319 {WCD938X_LDOH_MODE, 0x2B}, 320 {WCD938X_LDOH_BIAS, 0x68}, 321 {WCD938X_LDOH_STB_LOADS, 0x00}, 322 {WCD938X_LDOH_SLOWRAMP, 0x50}, 323 {WCD938X_MICB1_TEST_CTL_1, 0x1A}, 324 {WCD938X_MICB1_TEST_CTL_2, 0x00}, 325 {WCD938X_MICB1_TEST_CTL_3, 0xA4}, 326 {WCD938X_MICB2_TEST_CTL_1, 0x1A}, 327 {WCD938X_MICB2_TEST_CTL_2, 0x00}, 328 {WCD938X_MICB2_TEST_CTL_3, 0x24}, 329 {WCD938X_MICB3_TEST_CTL_1, 0x1A}, 330 {WCD938X_MICB3_TEST_CTL_2, 0x00}, 331 {WCD938X_MICB3_TEST_CTL_3, 0xA4}, 332 {WCD938X_MICB4_TEST_CTL_1, 0x1A}, 333 {WCD938X_MICB4_TEST_CTL_2, 0x00}, 334 {WCD938X_MICB4_TEST_CTL_3, 0xA4}, 335 {WCD938X_TX_COM_ADC_VCM, 0x39}, 336 {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, 337 {WCD938X_TX_COM_SPARE1, 0x00}, 338 {WCD938X_TX_COM_SPARE2, 0x00}, 339 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, 340 {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, 341 {WCD938X_TX_COM_SPARE3, 0x00}, 342 {WCD938X_TX_COM_SPARE4, 0x00}, 343 {WCD938X_TX_1_2_TEST_EN, 0xCC}, 344 {WCD938X_TX_1_2_ADC_IB, 0xE9}, 345 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, 346 {WCD938X_TX_1_2_TEST_CTL, 0x38}, 347 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, 348 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, 349 {WCD938X_TX_1_2_SAR2_ERR, 0x00}, 350 {WCD938X_TX_1_2_SAR1_ERR, 0x00}, 351 {WCD938X_TX_3_4_TEST_EN, 0xCC}, 352 {WCD938X_TX_3_4_ADC_IB, 0xE9}, 353 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, 354 {WCD938X_TX_3_4_TEST_CTL, 0x38}, 355 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, 356 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, 357 {WCD938X_TX_3_4_SAR4_ERR, 0x00}, 358 {WCD938X_TX_3_4_SAR3_ERR, 0x00}, 359 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, 360 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, 361 {WCD938X_TX_3_4_SPARE1, 0x00}, 362 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, 363 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, 364 {WCD938X_TX_3_4_SPARE2, 0x00}, 365 {WCD938X_CLASSH_MODE_1, 0x40}, 366 {WCD938X_CLASSH_MODE_2, 0x3A}, 367 {WCD938X_CLASSH_MODE_3, 0x00}, 368 {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, 369 {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, 370 {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, 371 {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, 372 {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, 373 {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, 374 {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, 375 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, 376 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, 377 {WCD938X_CLASSH_SPARE, 0x00}, 378 {WCD938X_FLYBACK_EN, 0x4E}, 379 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, 380 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, 381 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, 382 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, 383 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, 384 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, 385 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, 386 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, 387 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, 388 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, 389 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, 390 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, 391 {WCD938X_FLYBACK_CTRL_1, 0x65}, 392 {WCD938X_FLYBACK_TEST_CTL, 0x00}, 393 {WCD938X_RX_AUX_SW_CTL, 0x00}, 394 {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, 395 {WCD938X_RX_TIMER_DIV, 0x32}, 396 {WCD938X_RX_OCP_CTL, 0x1F}, 397 {WCD938X_RX_OCP_COUNT, 0x77}, 398 {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, 399 {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, 400 {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, 401 {WCD938X_RX_BIAS_HPH_PA, 0xAA}, 402 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, 403 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, 404 {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, 405 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, 406 {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, 407 {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, 408 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, 409 {WCD938X_RX_BIAS_MISC, 0x00}, 410 {WCD938X_RX_BIAS_BUCK_RST, 0x08}, 411 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, 412 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, 413 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, 414 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, 415 {WCD938X_HPH_L_STATUS, 0x04}, 416 {WCD938X_HPH_R_STATUS, 0x04}, 417 {WCD938X_HPH_CNP_EN, 0x80}, 418 {WCD938X_HPH_CNP_WG_CTL, 0x9A}, 419 {WCD938X_HPH_CNP_WG_TIME, 0x14}, 420 {WCD938X_HPH_OCP_CTL, 0x28}, 421 {WCD938X_HPH_AUTO_CHOP, 0x16}, 422 {WCD938X_HPH_CHOP_CTL, 0x83}, 423 {WCD938X_HPH_PA_CTL1, 0x46}, 424 {WCD938X_HPH_PA_CTL2, 0x50}, 425 {WCD938X_HPH_L_EN, 0x80}, 426 {WCD938X_HPH_L_TEST, 0xE0}, 427 {WCD938X_HPH_L_ATEST, 0x50}, 428 {WCD938X_HPH_R_EN, 0x80}, 429 {WCD938X_HPH_R_TEST, 0xE0}, 430 {WCD938X_HPH_R_ATEST, 0x54}, 431 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, 432 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, 433 {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, 434 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, 435 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, 436 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, 437 {WCD938X_HPH_L_DAC_CTL, 0x20}, 438 {WCD938X_HPH_R_DAC_CTL, 0x20}, 439 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, 440 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, 441 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, 442 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, 443 {WCD938X_EAR_EAR_EN_REG, 0x22}, 444 {WCD938X_EAR_EAR_PA_CON, 0x44}, 445 {WCD938X_EAR_EAR_SP_CON, 0xDB}, 446 {WCD938X_EAR_EAR_DAC_CON, 0x80}, 447 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, 448 {WCD938X_EAR_TEST_CTL, 0x00}, 449 {WCD938X_EAR_STATUS_REG_1, 0x00}, 450 {WCD938X_EAR_STATUS_REG_2, 0x08}, 451 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, 452 {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, 453 {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, 454 {WCD938X_SLEEP_CTL, 0x16}, 455 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, 456 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, 457 {WCD938X_MBHC_NEW_CTL_1, 0x02}, 458 {WCD938X_MBHC_NEW_CTL_2, 0x05}, 459 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, 460 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, 461 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, 462 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, 463 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, 464 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, 465 {WCD938X_AUX_AUXPA, 0x00}, 466 {WCD938X_LDORXTX_MODE, 0x0C}, 467 {WCD938X_LDORXTX_CONFIG, 0x10}, 468 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, 469 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, 470 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, 471 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, 472 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, 473 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, 474 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, 475 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, 476 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, 477 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, 478 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, 479 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, 480 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, 481 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, 482 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, 483 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, 484 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, 485 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, 486 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, 487 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, 488 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, 489 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, 490 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, 491 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, 492 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, 493 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, 494 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, 495 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, 496 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, 497 {WCD938X_AUX_INT_EN_REG, 0x00}, 498 {WCD938X_AUX_INT_PA_CTRL, 0x06}, 499 {WCD938X_AUX_INT_SP_CTRL, 0xD2}, 500 {WCD938X_AUX_INT_DAC_CTRL, 0x80}, 501 {WCD938X_AUX_INT_CLK_CTRL, 0x50}, 502 {WCD938X_AUX_INT_TEST_CTRL, 0x00}, 503 {WCD938X_AUX_INT_STATUS_REG, 0x00}, 504 {WCD938X_AUX_INT_MISC, 0x00}, 505 {WCD938X_LDORXTX_INT_BIAS, 0x6E}, 506 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, 507 {WCD938X_LDORXTX_INT_TEST0, 0x1C}, 508 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, 509 {WCD938X_LDORXTX_INT_TEST1, 0x1F}, 510 {WCD938X_LDORXTX_INT_STATUS, 0x00}, 511 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, 512 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, 513 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, 514 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, 515 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, 516 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, 517 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, 518 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, 519 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, 520 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, 521 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, 522 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, 523 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, 524 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, 525 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, 526 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, 527 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, 528 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, 529 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, 530 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, 531 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, 532 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, 533 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, 534 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, 535 {WCD938X_DIGITAL_CHIP_ID0, 0x00}, 536 {WCD938X_DIGITAL_CHIP_ID1, 0x00}, 537 {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, 538 {WCD938X_DIGITAL_CHIP_ID3, 0x01}, 539 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, 540 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, 541 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, 542 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, 543 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, 544 {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, 545 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, 546 {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, 547 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, 548 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, 549 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, 550 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, 551 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, 552 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, 553 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, 554 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, 555 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, 556 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, 557 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, 558 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, 559 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, 560 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, 561 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, 562 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, 563 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, 564 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, 565 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, 566 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, 567 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, 568 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, 569 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, 570 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, 571 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, 572 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, 573 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, 574 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, 575 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, 576 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, 577 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, 578 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, 579 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, 580 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, 581 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, 582 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, 583 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, 584 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, 585 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, 586 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, 587 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, 588 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, 589 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, 590 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, 591 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, 592 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, 593 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, 594 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, 595 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, 596 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, 597 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, 598 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, 599 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, 600 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, 601 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, 602 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, 603 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, 604 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, 605 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, 606 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, 607 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, 608 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, 609 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, 610 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, 611 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, 612 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, 613 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, 614 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, 615 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, 616 {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, 617 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, 618 {WCD938X_DIGITAL_CDC_RST, 0x00}, 619 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, 620 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, 621 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, 622 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, 623 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, 624 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, 625 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, 626 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, 627 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, 628 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, 629 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, 630 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, 631 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, 632 {WCD938X_DIGITAL_INTR_MODE, 0x00}, 633 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, 634 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, 635 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, 636 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, 637 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, 638 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, 639 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, 640 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, 641 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, 642 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, 643 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, 644 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, 645 {WCD938X_DIGITAL_INTR_SET_0, 0x00}, 646 {WCD938X_DIGITAL_INTR_SET_1, 0x00}, 647 {WCD938X_DIGITAL_INTR_SET_2, 0x00}, 648 {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, 649 {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, 650 {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, 651 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, 652 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, 653 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, 654 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, 655 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, 656 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, 657 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, 658 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, 659 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, 660 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, 661 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, 662 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, 663 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, 664 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, 665 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, 666 {WCD938X_DIGITAL_I2C_CTL, 0x00}, 667 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, 668 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, 669 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, 670 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, 671 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, 672 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, 673 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, 674 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, 675 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, 676 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, 677 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, 678 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, 679 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, 680 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, 681 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, 682 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, 683 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, 684 {WCD938X_DIGITAL_GPIO_MODE, 0x00}, 685 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, 686 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, 687 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, 688 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, 689 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, 690 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, 691 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, 692 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, 693 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, 694 {WCD938X_DIGITAL_SSP_DBG, 0x00}, 695 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, 696 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, 697 {WCD938X_DIGITAL_SPARE_0, 0x00}, 698 {WCD938X_DIGITAL_SPARE_1, 0x00}, 699 {WCD938X_DIGITAL_SPARE_2, 0x00}, 700 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, 701 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, 702 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, 703 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, 704 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, 705 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, 706 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, 707 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, 708 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, 709 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, 710 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, 711 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, 712 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, 713 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, 714 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, 715 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, 716 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, 717 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, 718 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, 719 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, 720 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, 721 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, 722 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, 723 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, 724 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, 725 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, 726 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, 727 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, 728 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, 729 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, 730 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, 731 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, 732 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, 733 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, 734 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, 735 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, 736 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, 737 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, 738 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, 739 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, 740 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, 741 }; 742 743 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) 744 { 745 switch (reg) { 746 case WCD938X_ANA_PAGE_REGISTER: 747 case WCD938X_ANA_BIAS: 748 case WCD938X_ANA_RX_SUPPLIES: 749 case WCD938X_ANA_HPH: 750 case WCD938X_ANA_EAR: 751 case WCD938X_ANA_EAR_COMPANDER_CTL: 752 case WCD938X_ANA_TX_CH1: 753 case WCD938X_ANA_TX_CH2: 754 case WCD938X_ANA_TX_CH3: 755 case WCD938X_ANA_TX_CH4: 756 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: 757 case WCD938X_ANA_MICB3_DSP_EN_LOGIC: 758 case WCD938X_ANA_MBHC_MECH: 759 case WCD938X_ANA_MBHC_ELECT: 760 case WCD938X_ANA_MBHC_ZDET: 761 case WCD938X_ANA_MBHC_BTN0: 762 case WCD938X_ANA_MBHC_BTN1: 763 case WCD938X_ANA_MBHC_BTN2: 764 case WCD938X_ANA_MBHC_BTN3: 765 case WCD938X_ANA_MBHC_BTN4: 766 case WCD938X_ANA_MBHC_BTN5: 767 case WCD938X_ANA_MBHC_BTN6: 768 case WCD938X_ANA_MBHC_BTN7: 769 case WCD938X_ANA_MICB1: 770 case WCD938X_ANA_MICB2: 771 case WCD938X_ANA_MICB2_RAMP: 772 case WCD938X_ANA_MICB3: 773 case WCD938X_ANA_MICB4: 774 case WCD938X_BIAS_CTL: 775 case WCD938X_BIAS_VBG_FINE_ADJ: 776 case WCD938X_LDOL_VDDCX_ADJUST: 777 case WCD938X_LDOL_DISABLE_LDOL: 778 case WCD938X_MBHC_CTL_CLK: 779 case WCD938X_MBHC_CTL_ANA: 780 case WCD938X_MBHC_CTL_SPARE_1: 781 case WCD938X_MBHC_CTL_SPARE_2: 782 case WCD938X_MBHC_CTL_BCS: 783 case WCD938X_MBHC_TEST_CTL: 784 case WCD938X_LDOH_MODE: 785 case WCD938X_LDOH_BIAS: 786 case WCD938X_LDOH_STB_LOADS: 787 case WCD938X_LDOH_SLOWRAMP: 788 case WCD938X_MICB1_TEST_CTL_1: 789 case WCD938X_MICB1_TEST_CTL_2: 790 case WCD938X_MICB1_TEST_CTL_3: 791 case WCD938X_MICB2_TEST_CTL_1: 792 case WCD938X_MICB2_TEST_CTL_2: 793 case WCD938X_MICB2_TEST_CTL_3: 794 case WCD938X_MICB3_TEST_CTL_1: 795 case WCD938X_MICB3_TEST_CTL_2: 796 case WCD938X_MICB3_TEST_CTL_3: 797 case WCD938X_MICB4_TEST_CTL_1: 798 case WCD938X_MICB4_TEST_CTL_2: 799 case WCD938X_MICB4_TEST_CTL_3: 800 case WCD938X_TX_COM_ADC_VCM: 801 case WCD938X_TX_COM_BIAS_ATEST: 802 case WCD938X_TX_COM_SPARE1: 803 case WCD938X_TX_COM_SPARE2: 804 case WCD938X_TX_COM_TXFE_DIV_CTL: 805 case WCD938X_TX_COM_TXFE_DIV_START: 806 case WCD938X_TX_COM_SPARE3: 807 case WCD938X_TX_COM_SPARE4: 808 case WCD938X_TX_1_2_TEST_EN: 809 case WCD938X_TX_1_2_ADC_IB: 810 case WCD938X_TX_1_2_ATEST_REFCTL: 811 case WCD938X_TX_1_2_TEST_CTL: 812 case WCD938X_TX_1_2_TEST_BLK_EN1: 813 case WCD938X_TX_1_2_TXFE1_CLKDIV: 814 case WCD938X_TX_3_4_TEST_EN: 815 case WCD938X_TX_3_4_ADC_IB: 816 case WCD938X_TX_3_4_ATEST_REFCTL: 817 case WCD938X_TX_3_4_TEST_CTL: 818 case WCD938X_TX_3_4_TEST_BLK_EN3: 819 case WCD938X_TX_3_4_TXFE3_CLKDIV: 820 case WCD938X_TX_3_4_TEST_BLK_EN2: 821 case WCD938X_TX_3_4_TXFE2_CLKDIV: 822 case WCD938X_TX_3_4_SPARE1: 823 case WCD938X_TX_3_4_TEST_BLK_EN4: 824 case WCD938X_TX_3_4_TXFE4_CLKDIV: 825 case WCD938X_TX_3_4_SPARE2: 826 case WCD938X_CLASSH_MODE_1: 827 case WCD938X_CLASSH_MODE_2: 828 case WCD938X_CLASSH_MODE_3: 829 case WCD938X_CLASSH_CTRL_VCL_1: 830 case WCD938X_CLASSH_CTRL_VCL_2: 831 case WCD938X_CLASSH_CTRL_CCL_1: 832 case WCD938X_CLASSH_CTRL_CCL_2: 833 case WCD938X_CLASSH_CTRL_CCL_3: 834 case WCD938X_CLASSH_CTRL_CCL_4: 835 case WCD938X_CLASSH_CTRL_CCL_5: 836 case WCD938X_CLASSH_BUCK_TMUX_A_D: 837 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: 838 case WCD938X_CLASSH_SPARE: 839 case WCD938X_FLYBACK_EN: 840 case WCD938X_FLYBACK_VNEG_CTRL_1: 841 case WCD938X_FLYBACK_VNEG_CTRL_2: 842 case WCD938X_FLYBACK_VNEG_CTRL_3: 843 case WCD938X_FLYBACK_VNEG_CTRL_4: 844 case WCD938X_FLYBACK_VNEG_CTRL_5: 845 case WCD938X_FLYBACK_VNEG_CTRL_6: 846 case WCD938X_FLYBACK_VNEG_CTRL_7: 847 case WCD938X_FLYBACK_VNEG_CTRL_8: 848 case WCD938X_FLYBACK_VNEG_CTRL_9: 849 case WCD938X_FLYBACK_VNEGDAC_CTRL_1: 850 case WCD938X_FLYBACK_VNEGDAC_CTRL_2: 851 case WCD938X_FLYBACK_VNEGDAC_CTRL_3: 852 case WCD938X_FLYBACK_CTRL_1: 853 case WCD938X_FLYBACK_TEST_CTL: 854 case WCD938X_RX_AUX_SW_CTL: 855 case WCD938X_RX_PA_AUX_IN_CONN: 856 case WCD938X_RX_TIMER_DIV: 857 case WCD938X_RX_OCP_CTL: 858 case WCD938X_RX_OCP_COUNT: 859 case WCD938X_RX_BIAS_EAR_DAC: 860 case WCD938X_RX_BIAS_EAR_AMP: 861 case WCD938X_RX_BIAS_HPH_LDO: 862 case WCD938X_RX_BIAS_HPH_PA: 863 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: 864 case WCD938X_RX_BIAS_HPH_RDAC_LDO: 865 case WCD938X_RX_BIAS_HPH_CNP1: 866 case WCD938X_RX_BIAS_HPH_LOWPOWER: 867 case WCD938X_RX_BIAS_AUX_DAC: 868 case WCD938X_RX_BIAS_AUX_AMP: 869 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: 870 case WCD938X_RX_BIAS_MISC: 871 case WCD938X_RX_BIAS_BUCK_RST: 872 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: 873 case WCD938X_RX_BIAS_FLYB_ERRAMP: 874 case WCD938X_RX_BIAS_FLYB_BUFF: 875 case WCD938X_RX_BIAS_FLYB_MID_RST: 876 case WCD938X_HPH_CNP_EN: 877 case WCD938X_HPH_CNP_WG_CTL: 878 case WCD938X_HPH_CNP_WG_TIME: 879 case WCD938X_HPH_OCP_CTL: 880 case WCD938X_HPH_AUTO_CHOP: 881 case WCD938X_HPH_CHOP_CTL: 882 case WCD938X_HPH_PA_CTL1: 883 case WCD938X_HPH_PA_CTL2: 884 case WCD938X_HPH_L_EN: 885 case WCD938X_HPH_L_TEST: 886 case WCD938X_HPH_L_ATEST: 887 case WCD938X_HPH_R_EN: 888 case WCD938X_HPH_R_TEST: 889 case WCD938X_HPH_R_ATEST: 890 case WCD938X_HPH_RDAC_CLK_CTL1: 891 case WCD938X_HPH_RDAC_CLK_CTL2: 892 case WCD938X_HPH_RDAC_LDO_CTL: 893 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: 894 case WCD938X_HPH_REFBUFF_UHQA_CTL: 895 case WCD938X_HPH_REFBUFF_LP_CTL: 896 case WCD938X_HPH_L_DAC_CTL: 897 case WCD938X_HPH_R_DAC_CTL: 898 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: 899 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: 900 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: 901 case WCD938X_EAR_EAR_EN_REG: 902 case WCD938X_EAR_EAR_PA_CON: 903 case WCD938X_EAR_EAR_SP_CON: 904 case WCD938X_EAR_EAR_DAC_CON: 905 case WCD938X_EAR_EAR_CNP_FSM_CON: 906 case WCD938X_EAR_TEST_CTL: 907 case WCD938X_ANA_NEW_PAGE_REGISTER: 908 case WCD938X_HPH_NEW_ANA_HPH2: 909 case WCD938X_HPH_NEW_ANA_HPH3: 910 case WCD938X_SLEEP_CTL: 911 case WCD938X_SLEEP_WATCHDOG_CTL: 912 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: 913 case WCD938X_MBHC_NEW_CTL_1: 914 case WCD938X_MBHC_NEW_CTL_2: 915 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: 916 case WCD938X_MBHC_NEW_ZDET_ANA_CTL: 917 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: 918 case WCD938X_TX_NEW_AMIC_MUX_CFG: 919 case WCD938X_AUX_AUXPA: 920 case WCD938X_LDORXTX_MODE: 921 case WCD938X_LDORXTX_CONFIG: 922 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: 923 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: 924 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: 925 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: 926 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: 927 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: 928 case WCD938X_HPH_NEW_INT_PA_MISC1: 929 case WCD938X_HPH_NEW_INT_PA_MISC2: 930 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: 931 case WCD938X_HPH_NEW_INT_HPH_TIMER1: 932 case WCD938X_HPH_NEW_INT_HPH_TIMER2: 933 case WCD938X_HPH_NEW_INT_HPH_TIMER3: 934 case WCD938X_HPH_NEW_INT_HPH_TIMER4: 935 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: 936 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: 937 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: 938 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: 939 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: 940 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: 941 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: 942 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: 943 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: 944 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: 945 case WCD938X_MBHC_NEW_INT_SPARE_2: 946 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: 947 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: 948 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: 949 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: 950 case WCD938X_AUX_INT_EN_REG: 951 case WCD938X_AUX_INT_PA_CTRL: 952 case WCD938X_AUX_INT_SP_CTRL: 953 case WCD938X_AUX_INT_DAC_CTRL: 954 case WCD938X_AUX_INT_CLK_CTRL: 955 case WCD938X_AUX_INT_TEST_CTRL: 956 case WCD938X_AUX_INT_MISC: 957 case WCD938X_LDORXTX_INT_BIAS: 958 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: 959 case WCD938X_LDORXTX_INT_TEST0: 960 case WCD938X_LDORXTX_INT_STARTUP_TIMER: 961 case WCD938X_LDORXTX_INT_TEST1: 962 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: 963 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: 964 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: 965 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: 966 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: 967 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: 968 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: 969 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: 970 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: 971 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: 972 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: 973 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: 974 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: 975 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: 976 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: 977 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: 978 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: 979 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: 980 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: 981 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: 982 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: 983 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: 984 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: 985 case WCD938X_DIGITAL_PAGE_REGISTER: 986 case WCD938X_DIGITAL_SWR_TX_CLK_RATE: 987 case WCD938X_DIGITAL_CDC_RST_CTL: 988 case WCD938X_DIGITAL_TOP_CLK_CFG: 989 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: 990 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: 991 case WCD938X_DIGITAL_SWR_RST_EN: 992 case WCD938X_DIGITAL_CDC_PATH_MODE: 993 case WCD938X_DIGITAL_CDC_RX_RST: 994 case WCD938X_DIGITAL_CDC_RX0_CTL: 995 case WCD938X_DIGITAL_CDC_RX1_CTL: 996 case WCD938X_DIGITAL_CDC_RX2_CTL: 997 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: 998 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: 999 case WCD938X_DIGITAL_CDC_COMP_CTL_0: 1000 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: 1001 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: 1002 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: 1003 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: 1004 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: 1005 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: 1006 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: 1007 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: 1008 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: 1009 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: 1010 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: 1011 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: 1012 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: 1013 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: 1014 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: 1015 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: 1016 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: 1017 case WCD938X_DIGITAL_CDC_HPH_DSM_R1: 1018 case WCD938X_DIGITAL_CDC_HPH_DSM_R2: 1019 case WCD938X_DIGITAL_CDC_HPH_DSM_R3: 1020 case WCD938X_DIGITAL_CDC_HPH_DSM_R4: 1021 case WCD938X_DIGITAL_CDC_HPH_DSM_R5: 1022 case WCD938X_DIGITAL_CDC_HPH_DSM_R6: 1023 case WCD938X_DIGITAL_CDC_HPH_DSM_R7: 1024 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: 1025 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: 1026 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: 1027 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: 1028 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: 1029 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: 1030 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: 1031 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: 1032 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: 1033 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: 1034 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: 1035 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: 1036 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: 1037 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: 1038 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: 1039 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: 1040 case WCD938X_DIGITAL_CDC_AUX_DSM_R1: 1041 case WCD938X_DIGITAL_CDC_AUX_DSM_R2: 1042 case WCD938X_DIGITAL_CDC_AUX_DSM_R3: 1043 case WCD938X_DIGITAL_CDC_AUX_DSM_R4: 1044 case WCD938X_DIGITAL_CDC_AUX_DSM_R5: 1045 case WCD938X_DIGITAL_CDC_AUX_DSM_R6: 1046 case WCD938X_DIGITAL_CDC_AUX_DSM_R7: 1047 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: 1048 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: 1049 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: 1050 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: 1051 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: 1052 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: 1053 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: 1054 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: 1055 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: 1056 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: 1057 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: 1058 case WCD938X_DIGITAL_CDC_SWR_CLH: 1059 case WCD938X_DIGITAL_SWR_CLH_BYP: 1060 case WCD938X_DIGITAL_CDC_TX0_CTL: 1061 case WCD938X_DIGITAL_CDC_TX1_CTL: 1062 case WCD938X_DIGITAL_CDC_TX2_CTL: 1063 case WCD938X_DIGITAL_CDC_TX_RST: 1064 case WCD938X_DIGITAL_CDC_REQ_CTL: 1065 case WCD938X_DIGITAL_CDC_RST: 1066 case WCD938X_DIGITAL_CDC_AMIC_CTL: 1067 case WCD938X_DIGITAL_CDC_DMIC_CTL: 1068 case WCD938X_DIGITAL_CDC_DMIC1_CTL: 1069 case WCD938X_DIGITAL_CDC_DMIC2_CTL: 1070 case WCD938X_DIGITAL_CDC_DMIC3_CTL: 1071 case WCD938X_DIGITAL_CDC_DMIC4_CTL: 1072 case WCD938X_DIGITAL_EFUSE_PRG_CTL: 1073 case WCD938X_DIGITAL_EFUSE_CTL: 1074 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: 1075 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: 1076 case WCD938X_DIGITAL_PDM_WD_CTL0: 1077 case WCD938X_DIGITAL_PDM_WD_CTL1: 1078 case WCD938X_DIGITAL_PDM_WD_CTL2: 1079 case WCD938X_DIGITAL_INTR_MODE: 1080 case WCD938X_DIGITAL_INTR_MASK_0: 1081 case WCD938X_DIGITAL_INTR_MASK_1: 1082 case WCD938X_DIGITAL_INTR_MASK_2: 1083 case WCD938X_DIGITAL_INTR_CLEAR_0: 1084 case WCD938X_DIGITAL_INTR_CLEAR_1: 1085 case WCD938X_DIGITAL_INTR_CLEAR_2: 1086 case WCD938X_DIGITAL_INTR_LEVEL_0: 1087 case WCD938X_DIGITAL_INTR_LEVEL_1: 1088 case WCD938X_DIGITAL_INTR_LEVEL_2: 1089 case WCD938X_DIGITAL_INTR_SET_0: 1090 case WCD938X_DIGITAL_INTR_SET_1: 1091 case WCD938X_DIGITAL_INTR_SET_2: 1092 case WCD938X_DIGITAL_INTR_TEST_0: 1093 case WCD938X_DIGITAL_INTR_TEST_1: 1094 case WCD938X_DIGITAL_INTR_TEST_2: 1095 case WCD938X_DIGITAL_TX_MODE_DBG_EN: 1096 case WCD938X_DIGITAL_TX_MODE_DBG_0_1: 1097 case WCD938X_DIGITAL_TX_MODE_DBG_2_3: 1098 case WCD938X_DIGITAL_LB_IN_SEL_CTL: 1099 case WCD938X_DIGITAL_LOOP_BACK_MODE: 1100 case WCD938X_DIGITAL_SWR_DAC_TEST: 1101 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: 1102 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: 1103 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: 1104 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: 1105 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: 1106 case WCD938X_DIGITAL_PAD_CTL_SWR_0: 1107 case WCD938X_DIGITAL_PAD_CTL_SWR_1: 1108 case WCD938X_DIGITAL_I2C_CTL: 1109 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: 1110 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: 1111 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: 1112 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: 1113 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: 1114 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: 1115 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: 1116 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: 1117 case WCD938X_DIGITAL_PAD_INP_DIS_0: 1118 case WCD938X_DIGITAL_PAD_INP_DIS_1: 1119 case WCD938X_DIGITAL_DRIVE_STRENGTH_0: 1120 case WCD938X_DIGITAL_DRIVE_STRENGTH_1: 1121 case WCD938X_DIGITAL_DRIVE_STRENGTH_2: 1122 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: 1123 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: 1124 case WCD938X_DIGITAL_GPIO_MODE: 1125 case WCD938X_DIGITAL_PIN_CTL_OE: 1126 case WCD938X_DIGITAL_PIN_CTL_DATA_0: 1127 case WCD938X_DIGITAL_PIN_CTL_DATA_1: 1128 case WCD938X_DIGITAL_DIG_DEBUG_CTL: 1129 case WCD938X_DIGITAL_DIG_DEBUG_EN: 1130 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: 1131 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: 1132 case WCD938X_DIGITAL_SSP_DBG: 1133 case WCD938X_DIGITAL_SPARE_0: 1134 case WCD938X_DIGITAL_SPARE_1: 1135 case WCD938X_DIGITAL_SPARE_2: 1136 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: 1137 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: 1138 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: 1139 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: 1140 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: 1141 case WCD938X_DIGITAL_DEM_BYPASS_DATA0: 1142 case WCD938X_DIGITAL_DEM_BYPASS_DATA1: 1143 case WCD938X_DIGITAL_DEM_BYPASS_DATA2: 1144 case WCD938X_DIGITAL_DEM_BYPASS_DATA3: 1145 return true; 1146 } 1147 1148 return false; 1149 } 1150 1151 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) 1152 { 1153 switch (reg) { 1154 case WCD938X_ANA_MBHC_RESULT_1: 1155 case WCD938X_ANA_MBHC_RESULT_2: 1156 case WCD938X_ANA_MBHC_RESULT_3: 1157 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: 1158 case WCD938X_TX_1_2_SAR2_ERR: 1159 case WCD938X_TX_1_2_SAR1_ERR: 1160 case WCD938X_TX_3_4_SAR4_ERR: 1161 case WCD938X_TX_3_4_SAR3_ERR: 1162 case WCD938X_HPH_L_STATUS: 1163 case WCD938X_HPH_R_STATUS: 1164 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: 1165 case WCD938X_EAR_STATUS_REG_1: 1166 case WCD938X_EAR_STATUS_REG_2: 1167 case WCD938X_MBHC_NEW_FSM_STATUS: 1168 case WCD938X_MBHC_NEW_ADC_RESULT: 1169 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: 1170 case WCD938X_AUX_INT_STATUS_REG: 1171 case WCD938X_LDORXTX_INT_STATUS: 1172 case WCD938X_DIGITAL_CHIP_ID0: 1173 case WCD938X_DIGITAL_CHIP_ID1: 1174 case WCD938X_DIGITAL_CHIP_ID2: 1175 case WCD938X_DIGITAL_CHIP_ID3: 1176 case WCD938X_DIGITAL_INTR_STATUS_0: 1177 case WCD938X_DIGITAL_INTR_STATUS_1: 1178 case WCD938X_DIGITAL_INTR_STATUS_2: 1179 case WCD938X_DIGITAL_INTR_CLEAR_0: 1180 case WCD938X_DIGITAL_INTR_CLEAR_1: 1181 case WCD938X_DIGITAL_INTR_CLEAR_2: 1182 case WCD938X_DIGITAL_SWR_HM_TEST_0: 1183 case WCD938X_DIGITAL_SWR_HM_TEST_1: 1184 case WCD938X_DIGITAL_EFUSE_T_DATA_0: 1185 case WCD938X_DIGITAL_EFUSE_T_DATA_1: 1186 case WCD938X_DIGITAL_PIN_STATUS_0: 1187 case WCD938X_DIGITAL_PIN_STATUS_1: 1188 case WCD938X_DIGITAL_MODE_STATUS_0: 1189 case WCD938X_DIGITAL_MODE_STATUS_1: 1190 case WCD938X_DIGITAL_EFUSE_REG_0: 1191 case WCD938X_DIGITAL_EFUSE_REG_1: 1192 case WCD938X_DIGITAL_EFUSE_REG_2: 1193 case WCD938X_DIGITAL_EFUSE_REG_3: 1194 case WCD938X_DIGITAL_EFUSE_REG_4: 1195 case WCD938X_DIGITAL_EFUSE_REG_5: 1196 case WCD938X_DIGITAL_EFUSE_REG_6: 1197 case WCD938X_DIGITAL_EFUSE_REG_7: 1198 case WCD938X_DIGITAL_EFUSE_REG_8: 1199 case WCD938X_DIGITAL_EFUSE_REG_9: 1200 case WCD938X_DIGITAL_EFUSE_REG_10: 1201 case WCD938X_DIGITAL_EFUSE_REG_11: 1202 case WCD938X_DIGITAL_EFUSE_REG_12: 1203 case WCD938X_DIGITAL_EFUSE_REG_13: 1204 case WCD938X_DIGITAL_EFUSE_REG_14: 1205 case WCD938X_DIGITAL_EFUSE_REG_15: 1206 case WCD938X_DIGITAL_EFUSE_REG_16: 1207 case WCD938X_DIGITAL_EFUSE_REG_17: 1208 case WCD938X_DIGITAL_EFUSE_REG_18: 1209 case WCD938X_DIGITAL_EFUSE_REG_19: 1210 case WCD938X_DIGITAL_EFUSE_REG_20: 1211 case WCD938X_DIGITAL_EFUSE_REG_21: 1212 case WCD938X_DIGITAL_EFUSE_REG_22: 1213 case WCD938X_DIGITAL_EFUSE_REG_23: 1214 case WCD938X_DIGITAL_EFUSE_REG_24: 1215 case WCD938X_DIGITAL_EFUSE_REG_25: 1216 case WCD938X_DIGITAL_EFUSE_REG_26: 1217 case WCD938X_DIGITAL_EFUSE_REG_27: 1218 case WCD938X_DIGITAL_EFUSE_REG_28: 1219 case WCD938X_DIGITAL_EFUSE_REG_29: 1220 case WCD938X_DIGITAL_EFUSE_REG_30: 1221 case WCD938X_DIGITAL_EFUSE_REG_31: 1222 return true; 1223 } 1224 return false; 1225 } 1226 1227 static bool wcd938x_readable_register(struct device *dev, unsigned int reg) 1228 { 1229 bool ret; 1230 1231 ret = wcd938x_readonly_register(dev, reg); 1232 if (!ret) 1233 return wcd938x_rdwr_register(dev, reg); 1234 1235 return ret; 1236 } 1237 1238 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) 1239 { 1240 return wcd938x_rdwr_register(dev, reg); 1241 } 1242 1243 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) 1244 { 1245 if (reg <= WCD938X_BASE_ADDRESS) 1246 return false; 1247 1248 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) 1249 return true; 1250 1251 if (wcd938x_readonly_register(dev, reg)) 1252 return true; 1253 1254 return false; 1255 } 1256 1257 static struct regmap_config wcd938x_regmap_config = { 1258 .name = "wcd938x_csr", 1259 .reg_bits = 32, 1260 .val_bits = 8, 1261 .cache_type = REGCACHE_RBTREE, 1262 .reg_defaults = wcd938x_defaults, 1263 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), 1264 .max_register = WCD938X_MAX_REGISTER, 1265 .readable_reg = wcd938x_readable_register, 1266 .writeable_reg = wcd938x_writeable_register, 1267 .volatile_reg = wcd938x_volatile_register, 1268 .can_multi_write = true, 1269 }; 1270 1271 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 1272 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 1273 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 1274 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 1275 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 1276 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 1277 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 1278 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 1279 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 1280 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 1281 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 1282 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 1283 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 1284 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 1285 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 1286 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 1287 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 1288 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 1289 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 1290 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 1291 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 1292 }; 1293 1294 static struct regmap_irq_chip wcd938x_regmap_irq_chip = { 1295 .name = "wcd938x", 1296 .irqs = wcd938x_irqs, 1297 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 1298 .num_regs = 3, 1299 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 1300 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 1301 .type_base = WCD938X_DIGITAL_INTR_LEVEL_0, 1302 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 1303 .use_ack = 1, 1304 .runtime_pm = true, 1305 .irq_drv_data = NULL, 1306 }; 1307 1308 static int wcd938x_get_clk_rate(int mode) 1309 { 1310 int rate; 1311 1312 switch (mode) { 1313 case ADC_MODE_ULP2: 1314 rate = SWR_CLK_RATE_0P6MHZ; 1315 break; 1316 case ADC_MODE_ULP1: 1317 rate = SWR_CLK_RATE_1P2MHZ; 1318 break; 1319 case ADC_MODE_LP: 1320 rate = SWR_CLK_RATE_4P8MHZ; 1321 break; 1322 case ADC_MODE_NORMAL: 1323 case ADC_MODE_LO_HIF: 1324 case ADC_MODE_HIFI: 1325 case ADC_MODE_INVALID: 1326 default: 1327 rate = SWR_CLK_RATE_9P6MHZ; 1328 break; 1329 } 1330 1331 return rate; 1332 } 1333 1334 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 1335 { 1336 u8 mask = (bank ? 0xF0 : 0x0F); 1337 u8 val = 0; 1338 1339 switch (rate) { 1340 case SWR_CLK_RATE_0P6MHZ: 1341 val = (bank ? 0x60 : 0x06); 1342 break; 1343 case SWR_CLK_RATE_1P2MHZ: 1344 val = (bank ? 0x50 : 0x05); 1345 break; 1346 case SWR_CLK_RATE_2P4MHZ: 1347 val = (bank ? 0x30 : 0x03); 1348 break; 1349 case SWR_CLK_RATE_4P8MHZ: 1350 val = (bank ? 0x10 : 0x01); 1351 break; 1352 case SWR_CLK_RATE_9P6MHZ: 1353 default: 1354 val = 0x00; 1355 break; 1356 } 1357 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 1358 mask, val); 1359 1360 return 0; 1361 } 1362 1363 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 1364 { 1365 struct regmap *rm = wcd938x->regmap; 1366 1367 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 1368 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 1369 /* 1 msec delay as per HW requirement */ 1370 usleep_range(1000, 1010); 1371 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 1372 /* 1 msec delay as per HW requirement */ 1373 usleep_range(1000, 1010); 1374 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 1375 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 1376 0xF0, 0x80); 1377 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 1378 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 1379 /* 10 msec delay as per HW requirement */ 1380 usleep_range(10000, 10010); 1381 1382 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 1383 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 1384 0xF0, 0x00); 1385 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 1386 0x1F, 0x15); 1387 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 1388 0x1F, 0x15); 1389 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 1390 0xC0, 0x80); 1391 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 1392 0x02, 0x02); 1393 1394 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 1395 0xFF, 0x14); 1396 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 1397 0x1F, 0x08); 1398 1399 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 1400 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 1401 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 1402 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 1403 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 1404 1405 /* Set Noise Filter Resistor value */ 1406 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 1407 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 1408 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 1409 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 1410 1411 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 1412 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1413 1414 return 0; 1415 1416 } 1417 1418 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info, 1419 struct sdw_port_config *port_config, 1420 u8 enable) 1421 { 1422 u8 ch_mask, port_num; 1423 1424 port_num = ch_info->port_num; 1425 ch_mask = ch_info->ch_mask; 1426 1427 port_config->num = port_num; 1428 1429 if (enable) 1430 port_config->ch_mask |= ch_mask; 1431 else 1432 port_config->ch_mask &= ~ch_mask; 1433 1434 return 0; 1435 } 1436 1437 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 1438 { 1439 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 1440 &wcd->port_config[port_num - 1], 1441 enable); 1442 } 1443 1444 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 1445 struct snd_kcontrol *kcontrol, 1446 int event) 1447 { 1448 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1449 1450 switch (event) { 1451 case SND_SOC_DAPM_PRE_PMU: 1452 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1453 WCD938X_ANA_RX_CLK_EN_MASK, 1); 1454 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1455 WCD938X_RX_BIAS_EN_MASK, 1); 1456 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 1457 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1458 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 1459 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1460 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 1461 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1462 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1463 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 1464 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 1465 WCD938X_AUXPA_CLK_EN_MASK, 1); 1466 break; 1467 case SND_SOC_DAPM_POST_PMD: 1468 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1469 WCD938X_VNEG_EN_MASK, 0); 1470 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1471 WCD938X_VPOS_EN_MASK, 0); 1472 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1473 WCD938X_RX_BIAS_EN_MASK, 0); 1474 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1475 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 1476 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1477 WCD938X_ANA_RX_CLK_EN_MASK, 0); 1478 break; 1479 } 1480 return 0; 1481 } 1482 1483 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 1484 struct snd_kcontrol *kcontrol, 1485 int event) 1486 { 1487 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1488 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1489 1490 switch (event) { 1491 case SND_SOC_DAPM_PRE_PMU: 1492 snd_soc_component_write_field(component, 1493 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1494 WCD938X_RXD0_CLK_EN_MASK, 0x01); 1495 snd_soc_component_write_field(component, 1496 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1497 WCD938X_HPHL_RX_EN_MASK, 1); 1498 snd_soc_component_write_field(component, 1499 WCD938X_HPH_RDAC_CLK_CTL1, 1500 WCD938X_CHOP_CLK_EN_MASK, 0); 1501 break; 1502 case SND_SOC_DAPM_POST_PMU: 1503 snd_soc_component_write_field(component, 1504 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 1505 WCD938X_HPH_RES_DIV_MASK, 0x02); 1506 if (wcd938x->comp1_enable) { 1507 snd_soc_component_write_field(component, 1508 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1509 WCD938X_HPHL_COMP_EN_MASK, 1); 1510 /* 5msec compander delay as per HW requirement */ 1511 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 1512 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 1513 usleep_range(5000, 5010); 1514 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1515 WCD938X_AUTOCHOP_TIMER_EN, 0); 1516 } else { 1517 snd_soc_component_write_field(component, 1518 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1519 WCD938X_HPHL_COMP_EN_MASK, 0); 1520 snd_soc_component_write_field(component, 1521 WCD938X_HPH_L_EN, 1522 WCD938X_GAIN_SRC_SEL_MASK, 1523 WCD938X_GAIN_SRC_SEL_REGISTER); 1524 1525 } 1526 break; 1527 case SND_SOC_DAPM_POST_PMD: 1528 snd_soc_component_write_field(component, 1529 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1530 WCD938X_HPH_RES_DIV_MASK, 0x1); 1531 break; 1532 } 1533 1534 return 0; 1535 } 1536 1537 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 1538 struct snd_kcontrol *kcontrol, 1539 int event) 1540 { 1541 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1542 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1543 1544 switch (event) { 1545 case SND_SOC_DAPM_PRE_PMU: 1546 snd_soc_component_write_field(component, 1547 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1548 WCD938X_RXD1_CLK_EN_MASK, 1); 1549 snd_soc_component_write_field(component, 1550 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1551 WCD938X_HPHR_RX_EN_MASK, 1); 1552 snd_soc_component_write_field(component, 1553 WCD938X_HPH_RDAC_CLK_CTL1, 1554 WCD938X_CHOP_CLK_EN_MASK, 0); 1555 break; 1556 case SND_SOC_DAPM_POST_PMU: 1557 snd_soc_component_write_field(component, 1558 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1559 WCD938X_HPH_RES_DIV_MASK, 0x02); 1560 if (wcd938x->comp2_enable) { 1561 snd_soc_component_write_field(component, 1562 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1563 WCD938X_HPHR_COMP_EN_MASK, 1); 1564 /* 5msec compander delay as per HW requirement */ 1565 if (!wcd938x->comp1_enable || 1566 (snd_soc_component_read(component, 1567 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 1568 usleep_range(5000, 5010); 1569 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1570 WCD938X_AUTOCHOP_TIMER_EN, 0); 1571 } else { 1572 snd_soc_component_write_field(component, 1573 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1574 WCD938X_HPHR_COMP_EN_MASK, 0); 1575 snd_soc_component_write_field(component, 1576 WCD938X_HPH_R_EN, 1577 WCD938X_GAIN_SRC_SEL_MASK, 1578 WCD938X_GAIN_SRC_SEL_REGISTER); 1579 } 1580 break; 1581 case SND_SOC_DAPM_POST_PMD: 1582 snd_soc_component_write_field(component, 1583 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1584 WCD938X_HPH_RES_DIV_MASK, 0x01); 1585 break; 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 1592 struct snd_kcontrol *kcontrol, 1593 int event) 1594 { 1595 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1596 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1597 1598 switch (event) { 1599 case SND_SOC_DAPM_PRE_PMU: 1600 wcd938x->ear_rx_path = 1601 snd_soc_component_read( 1602 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1603 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1604 snd_soc_component_write_field(component, 1605 WCD938X_EAR_EAR_DAC_CON, 1606 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 1607 snd_soc_component_write_field(component, 1608 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1609 WCD938X_AUX_EN_MASK, 1); 1610 snd_soc_component_write_field(component, 1611 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1612 WCD938X_RXD2_CLK_EN_MASK, 1); 1613 snd_soc_component_write_field(component, 1614 WCD938X_ANA_EAR_COMPANDER_CTL, 1615 WCD938X_GAIN_OVRD_REG_MASK, 1); 1616 } else { 1617 snd_soc_component_write_field(component, 1618 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1619 WCD938X_HPHL_RX_EN_MASK, 1); 1620 snd_soc_component_write_field(component, 1621 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1622 WCD938X_RXD0_CLK_EN_MASK, 1); 1623 if (wcd938x->comp1_enable) 1624 snd_soc_component_write_field(component, 1625 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1626 WCD938X_HPHL_COMP_EN_MASK, 1); 1627 } 1628 /* 5 msec delay as per HW requirement */ 1629 usleep_range(5000, 5010); 1630 if (wcd938x->flyback_cur_det_disable == 0) 1631 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1632 WCD938X_EN_CUR_DET_MASK, 0); 1633 wcd938x->flyback_cur_det_disable++; 1634 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1635 WCD_CLSH_EVENT_PRE_DAC, 1636 WCD_CLSH_STATE_EAR, 1637 wcd938x->hph_mode); 1638 break; 1639 case SND_SOC_DAPM_POST_PMD: 1640 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1641 snd_soc_component_write_field(component, 1642 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1643 WCD938X_AUX_EN_MASK, 0); 1644 snd_soc_component_write_field(component, 1645 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1646 WCD938X_RXD2_CLK_EN_MASK, 0); 1647 } else { 1648 snd_soc_component_write_field(component, 1649 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1650 WCD938X_HPHL_RX_EN_MASK, 0); 1651 snd_soc_component_write_field(component, 1652 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1653 WCD938X_RXD0_CLK_EN_MASK, 0); 1654 if (wcd938x->comp1_enable) 1655 snd_soc_component_write_field(component, 1656 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1657 WCD938X_HPHL_COMP_EN_MASK, 0); 1658 } 1659 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1660 WCD938X_GAIN_OVRD_REG_MASK, 0); 1661 snd_soc_component_write_field(component, 1662 WCD938X_EAR_EAR_DAC_CON, 1663 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 1664 break; 1665 } 1666 return 0; 1667 1668 } 1669 1670 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 1671 struct snd_kcontrol *kcontrol, 1672 int event) 1673 { 1674 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1675 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1676 1677 switch (event) { 1678 case SND_SOC_DAPM_PRE_PMU: 1679 snd_soc_component_write_field(component, 1680 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1681 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 1682 snd_soc_component_write_field(component, 1683 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1684 WCD938X_RXD2_CLK_EN_MASK, 1); 1685 snd_soc_component_write_field(component, 1686 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1687 WCD938X_AUX_EN_MASK, 1); 1688 if (wcd938x->flyback_cur_det_disable == 0) 1689 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1690 WCD938X_EN_CUR_DET_MASK, 0); 1691 wcd938x->flyback_cur_det_disable++; 1692 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1693 WCD_CLSH_EVENT_PRE_DAC, 1694 WCD_CLSH_STATE_AUX, 1695 wcd938x->hph_mode); 1696 break; 1697 case SND_SOC_DAPM_POST_PMD: 1698 snd_soc_component_write_field(component, 1699 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1700 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 1701 break; 1702 } 1703 return 0; 1704 1705 } 1706 1707 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 1708 struct snd_kcontrol *kcontrol, int event) 1709 { 1710 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1711 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1712 int hph_mode = wcd938x->hph_mode; 1713 1714 switch (event) { 1715 case SND_SOC_DAPM_PRE_PMU: 1716 if (wcd938x->ldoh) 1717 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1718 WCD938X_LDOH_EN_MASK, 1); 1719 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1720 WCD_CLSH_STATE_HPHR, hph_mode); 1721 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1722 1723 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1724 hph_mode == CLS_H_ULP) { 1725 snd_soc_component_write_field(component, 1726 WCD938X_HPH_REFBUFF_LP_CTL, 1727 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1728 } 1729 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1730 WCD938X_HPHR_REF_EN_MASK, 1); 1731 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1732 /* 100 usec delay as per HW requirement */ 1733 usleep_range(100, 110); 1734 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1735 snd_soc_component_write_field(component, 1736 WCD938X_DIGITAL_PDM_WD_CTL1, 1737 WCD938X_PDM_WD_EN_MASK, 0x3); 1738 break; 1739 case SND_SOC_DAPM_POST_PMU: 1740 /* 1741 * 7ms sleep is required if compander is enabled as per 1742 * HW requirement. If compander is disabled, then 1743 * 20ms delay is required. 1744 */ 1745 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1746 if (!wcd938x->comp2_enable) 1747 usleep_range(20000, 20100); 1748 else 1749 usleep_range(7000, 7100); 1750 1751 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1752 hph_mode == CLS_H_ULP) 1753 snd_soc_component_write_field(component, 1754 WCD938X_HPH_REFBUFF_LP_CTL, 1755 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1756 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1757 } 1758 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1759 WCD938X_AUTOCHOP_TIMER_EN, 1); 1760 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1761 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1762 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1763 WCD938X_REGULATOR_MODE_MASK, 1764 WCD938X_REGULATOR_MODE_CLASS_AB); 1765 enable_irq(wcd938x->hphr_pdm_wd_int); 1766 break; 1767 case SND_SOC_DAPM_PRE_PMD: 1768 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 1769 /* 1770 * 7ms sleep is required if compander is enabled as per 1771 * HW requirement. If compander is disabled, then 1772 * 20ms delay is required. 1773 */ 1774 if (!wcd938x->comp2_enable) 1775 usleep_range(20000, 20100); 1776 else 1777 usleep_range(7000, 7100); 1778 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1779 WCD938X_HPHR_EN_MASK, 0); 1780 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1781 WCD_EVENT_PRE_HPHR_PA_OFF); 1782 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1783 break; 1784 case SND_SOC_DAPM_POST_PMD: 1785 /* 1786 * 7ms sleep is required if compander is enabled as per 1787 * HW requirement. If compander is disabled, then 1788 * 20ms delay is required. 1789 */ 1790 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1791 if (!wcd938x->comp2_enable) 1792 usleep_range(20000, 20100); 1793 else 1794 usleep_range(7000, 7100); 1795 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1796 } 1797 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1798 WCD_EVENT_POST_HPHR_PA_OFF); 1799 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1800 WCD938X_HPHR_REF_EN_MASK, 0); 1801 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 1802 WCD938X_PDM_WD_EN_MASK, 0); 1803 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1804 WCD_CLSH_STATE_HPHR, hph_mode); 1805 if (wcd938x->ldoh) 1806 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1807 WCD938X_LDOH_EN_MASK, 0); 1808 break; 1809 } 1810 1811 return 0; 1812 } 1813 1814 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 1815 struct snd_kcontrol *kcontrol, int event) 1816 { 1817 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1818 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1819 int hph_mode = wcd938x->hph_mode; 1820 1821 switch (event) { 1822 case SND_SOC_DAPM_PRE_PMU: 1823 if (wcd938x->ldoh) 1824 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1825 WCD938X_LDOH_EN_MASK, 1); 1826 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1827 WCD_CLSH_STATE_HPHL, hph_mode); 1828 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1829 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1830 hph_mode == CLS_H_ULP) { 1831 snd_soc_component_write_field(component, 1832 WCD938X_HPH_REFBUFF_LP_CTL, 1833 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1834 } 1835 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1836 WCD938X_HPHL_REF_EN_MASK, 1); 1837 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1838 /* 100 usec delay as per HW requirement */ 1839 usleep_range(100, 110); 1840 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1841 snd_soc_component_write_field(component, 1842 WCD938X_DIGITAL_PDM_WD_CTL0, 1843 WCD938X_PDM_WD_EN_MASK, 0x3); 1844 break; 1845 case SND_SOC_DAPM_POST_PMU: 1846 /* 1847 * 7ms sleep is required if compander is enabled as per 1848 * HW requirement. If compander is disabled, then 1849 * 20ms delay is required. 1850 */ 1851 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1852 if (!wcd938x->comp1_enable) 1853 usleep_range(20000, 20100); 1854 else 1855 usleep_range(7000, 7100); 1856 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1857 hph_mode == CLS_H_ULP) 1858 snd_soc_component_write_field(component, 1859 WCD938X_HPH_REFBUFF_LP_CTL, 1860 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1861 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1862 } 1863 1864 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1865 WCD938X_AUTOCHOP_TIMER_EN, 1); 1866 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1867 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1868 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1869 WCD938X_REGULATOR_MODE_MASK, 1870 WCD938X_REGULATOR_MODE_CLASS_AB); 1871 enable_irq(wcd938x->hphl_pdm_wd_int); 1872 break; 1873 case SND_SOC_DAPM_PRE_PMD: 1874 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 1875 /* 1876 * 7ms sleep is required if compander is enabled as per 1877 * HW requirement. If compander is disabled, then 1878 * 20ms delay is required. 1879 */ 1880 if (!wcd938x->comp1_enable) 1881 usleep_range(20000, 20100); 1882 else 1883 usleep_range(7000, 7100); 1884 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1885 WCD938X_HPHL_EN_MASK, 0); 1886 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 1887 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1888 break; 1889 case SND_SOC_DAPM_POST_PMD: 1890 /* 1891 * 7ms sleep is required if compander is enabled as per 1892 * HW requirement. If compander is disabled, then 1893 * 20ms delay is required. 1894 */ 1895 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1896 if (!wcd938x->comp1_enable) 1897 usleep_range(21000, 21100); 1898 else 1899 usleep_range(7000, 7100); 1900 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1901 } 1902 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1903 WCD_EVENT_POST_HPHL_PA_OFF); 1904 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1905 WCD938X_HPHL_REF_EN_MASK, 0); 1906 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1907 WCD938X_PDM_WD_EN_MASK, 0); 1908 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1909 WCD_CLSH_STATE_HPHL, hph_mode); 1910 if (wcd938x->ldoh) 1911 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1912 WCD938X_LDOH_EN_MASK, 0); 1913 break; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 1920 struct snd_kcontrol *kcontrol, int event) 1921 { 1922 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1923 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1924 int hph_mode = wcd938x->hph_mode; 1925 1926 switch (event) { 1927 case SND_SOC_DAPM_PRE_PMU: 1928 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1929 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1930 break; 1931 case SND_SOC_DAPM_POST_PMU: 1932 /* 1 msec delay as per HW requirement */ 1933 usleep_range(1000, 1010); 1934 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1935 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1936 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1937 WCD938X_REGULATOR_MODE_MASK, 1938 WCD938X_REGULATOR_MODE_CLASS_AB); 1939 enable_irq(wcd938x->aux_pdm_wd_int); 1940 break; 1941 case SND_SOC_DAPM_PRE_PMD: 1942 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 1943 break; 1944 case SND_SOC_DAPM_POST_PMD: 1945 /* 1 msec delay as per HW requirement */ 1946 usleep_range(1000, 1010); 1947 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1948 WCD938X_AUX_PDM_WD_EN_MASK, 0); 1949 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1950 WCD_CLSH_EVENT_POST_PA, 1951 WCD_CLSH_STATE_AUX, 1952 hph_mode); 1953 1954 wcd938x->flyback_cur_det_disable--; 1955 if (wcd938x->flyback_cur_det_disable == 0) 1956 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1957 WCD938X_EN_CUR_DET_MASK, 1); 1958 break; 1959 } 1960 return 0; 1961 } 1962 1963 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 1964 struct snd_kcontrol *kcontrol, int event) 1965 { 1966 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1967 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1968 int hph_mode = wcd938x->hph_mode; 1969 1970 switch (event) { 1971 case SND_SOC_DAPM_PRE_PMU: 1972 /* 1973 * Enable watchdog interrupt for HPHL or AUX 1974 * depending on mux value 1975 */ 1976 wcd938x->ear_rx_path = snd_soc_component_read(component, 1977 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1978 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1979 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1980 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1981 else 1982 snd_soc_component_write_field(component, 1983 WCD938X_DIGITAL_PDM_WD_CTL0, 1984 WCD938X_PDM_WD_EN_MASK, 0x3); 1985 if (!wcd938x->comp1_enable) 1986 snd_soc_component_write_field(component, 1987 WCD938X_ANA_EAR_COMPANDER_CTL, 1988 WCD938X_GAIN_OVRD_REG_MASK, 1); 1989 1990 break; 1991 case SND_SOC_DAPM_POST_PMU: 1992 /* 6 msec delay as per HW requirement */ 1993 usleep_range(6000, 6010); 1994 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1995 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1996 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1997 WCD938X_REGULATOR_MODE_MASK, 1998 WCD938X_REGULATOR_MODE_CLASS_AB); 1999 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2000 enable_irq(wcd938x->aux_pdm_wd_int); 2001 else 2002 enable_irq(wcd938x->hphl_pdm_wd_int); 2003 break; 2004 case SND_SOC_DAPM_PRE_PMD: 2005 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2006 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 2007 else 2008 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 2009 break; 2010 case SND_SOC_DAPM_POST_PMD: 2011 if (!wcd938x->comp1_enable) 2012 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2013 WCD938X_GAIN_OVRD_REG_MASK, 0); 2014 /* 7 msec delay as per HW requirement */ 2015 usleep_range(7000, 7010); 2016 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2017 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 2018 WCD938X_AUX_PDM_WD_EN_MASK, 0); 2019 else 2020 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 2021 WCD938X_PDM_WD_EN_MASK, 0); 2022 2023 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 2024 WCD_CLSH_STATE_EAR, hph_mode); 2025 2026 wcd938x->flyback_cur_det_disable--; 2027 if (wcd938x->flyback_cur_det_disable == 0) 2028 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 2029 WCD938X_EN_CUR_DET_MASK, 1); 2030 break; 2031 } 2032 2033 return 0; 2034 } 2035 2036 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2037 struct snd_kcontrol *kcontrol, 2038 int event) 2039 { 2040 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2041 u16 dmic_clk_reg, dmic_clk_en_reg; 2042 u8 dmic_sel_mask, dmic_clk_mask; 2043 2044 switch (w->shift) { 2045 case 0: 2046 case 1: 2047 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2048 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 2049 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 2050 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 2051 break; 2052 case 2: 2053 case 3: 2054 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2055 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 2056 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 2057 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 2058 break; 2059 case 4: 2060 case 5: 2061 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2062 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 2063 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 2064 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 2065 break; 2066 case 6: 2067 case 7: 2068 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2069 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 2070 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 2071 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 2072 break; 2073 default: 2074 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 2075 __func__); 2076 return -EINVAL; 2077 } 2078 2079 switch (event) { 2080 case SND_SOC_DAPM_PRE_PMU: 2081 snd_soc_component_write_field(component, 2082 WCD938X_DIGITAL_CDC_AMIC_CTL, 2083 dmic_sel_mask, 2084 WCD938X_AMIC1_IN_SEL_DMIC); 2085 /* 250us sleep as per HW requirement */ 2086 usleep_range(250, 260); 2087 /* Setting DMIC clock rate to 2.4MHz */ 2088 snd_soc_component_write_field(component, dmic_clk_reg, 2089 dmic_clk_mask, 2090 WCD938X_DMIC4_RATE_2P4MHZ); 2091 snd_soc_component_write_field(component, dmic_clk_en_reg, 2092 WCD938X_DMIC_CLK_EN_MASK, 1); 2093 /* enable clock scaling */ 2094 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 2095 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 2096 break; 2097 case SND_SOC_DAPM_POST_PMD: 2098 snd_soc_component_write_field(component, 2099 WCD938X_DIGITAL_CDC_AMIC_CTL, 2100 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 2101 snd_soc_component_write_field(component, dmic_clk_en_reg, 2102 WCD938X_DMIC_CLK_EN_MASK, 0); 2103 break; 2104 } 2105 return 0; 2106 } 2107 2108 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 2109 struct snd_kcontrol *kcontrol, int event) 2110 { 2111 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2112 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2113 int bank; 2114 int rate; 2115 2116 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 2117 bank = bank ? 0 : 1; 2118 2119 switch (event) { 2120 case SND_SOC_DAPM_PRE_PMU: 2121 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2122 int i = 0, mode = 0; 2123 2124 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 2125 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 2126 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 2127 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 2128 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 2129 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 2130 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 2131 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 2132 2133 if (mode != 0) { 2134 for (i = 0; i < ADC_MODE_ULP2; i++) { 2135 if (mode & (1 << i)) { 2136 i++; 2137 break; 2138 } 2139 } 2140 } 2141 rate = wcd938x_get_clk_rate(i); 2142 wcd938x_set_swr_clk_rate(component, rate, bank); 2143 /* Copy clk settings to active bank */ 2144 wcd938x_set_swr_clk_rate(component, rate, !bank); 2145 } 2146 break; 2147 case SND_SOC_DAPM_POST_PMD: 2148 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2149 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 2150 wcd938x_set_swr_clk_rate(component, rate, !bank); 2151 wcd938x_set_swr_clk_rate(component, rate, bank); 2152 } 2153 break; 2154 } 2155 2156 return 0; 2157 } 2158 2159 static int wcd938x_get_adc_mode(int val) 2160 { 2161 int ret = 0; 2162 2163 switch (val) { 2164 case ADC_MODE_INVALID: 2165 ret = ADC_MODE_VAL_NORMAL; 2166 break; 2167 case ADC_MODE_HIFI: 2168 ret = ADC_MODE_VAL_HIFI; 2169 break; 2170 case ADC_MODE_LO_HIF: 2171 ret = ADC_MODE_VAL_LO_HIF; 2172 break; 2173 case ADC_MODE_NORMAL: 2174 ret = ADC_MODE_VAL_NORMAL; 2175 break; 2176 case ADC_MODE_LP: 2177 ret = ADC_MODE_VAL_LP; 2178 break; 2179 case ADC_MODE_ULP1: 2180 ret = ADC_MODE_VAL_ULP1; 2181 break; 2182 case ADC_MODE_ULP2: 2183 ret = ADC_MODE_VAL_ULP2; 2184 break; 2185 default: 2186 ret = -EINVAL; 2187 break; 2188 } 2189 return ret; 2190 } 2191 2192 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 2193 struct snd_kcontrol *kcontrol, int event) 2194 { 2195 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2196 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2197 2198 switch (event) { 2199 case SND_SOC_DAPM_PRE_PMU: 2200 snd_soc_component_write_field(component, 2201 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2202 WCD938X_ANA_TX_CLK_EN_MASK, 1); 2203 snd_soc_component_write_field(component, 2204 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2205 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2206 set_bit(w->shift, &wcd938x->status_mask); 2207 break; 2208 case SND_SOC_DAPM_POST_PMD: 2209 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2210 WCD938X_ANA_TX_CLK_EN_MASK, 0); 2211 clear_bit(w->shift, &wcd938x->status_mask); 2212 break; 2213 } 2214 2215 return 0; 2216 } 2217 2218 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 2219 int channel, int mode) 2220 { 2221 int reg, mask; 2222 2223 switch (channel) { 2224 case 0: 2225 reg = WCD938X_ANA_TX_CH2; 2226 mask = WCD938X_HPF1_INIT_MASK; 2227 break; 2228 case 1: 2229 reg = WCD938X_ANA_TX_CH2; 2230 mask = WCD938X_HPF2_INIT_MASK; 2231 break; 2232 case 2: 2233 reg = WCD938X_ANA_TX_CH4; 2234 mask = WCD938X_HPF3_INIT_MASK; 2235 break; 2236 case 3: 2237 reg = WCD938X_ANA_TX_CH4; 2238 mask = WCD938X_HPF4_INIT_MASK; 2239 break; 2240 default: 2241 return; 2242 } 2243 2244 snd_soc_component_write_field(component, reg, mask, mode); 2245 } 2246 2247 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 2248 struct snd_kcontrol *kcontrol, int event) 2249 { 2250 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2251 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2252 int mode; 2253 2254 switch (event) { 2255 case SND_SOC_DAPM_PRE_PMU: 2256 snd_soc_component_write_field(component, 2257 WCD938X_DIGITAL_CDC_REQ_CTL, 2258 WCD938X_FS_RATE_4P8_MASK, 1); 2259 snd_soc_component_write_field(component, 2260 WCD938X_DIGITAL_CDC_REQ_CTL, 2261 WCD938X_NO_NOTCH_MASK, 0); 2262 wcd938x_tx_channel_config(component, w->shift, 1); 2263 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 2264 if (mode < 0) { 2265 dev_info(component->dev, "Invalid ADC mode\n"); 2266 return -EINVAL; 2267 } 2268 switch (w->shift) { 2269 case 0: 2270 snd_soc_component_write_field(component, 2271 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2272 WCD938X_TXD0_MODE_MASK, mode); 2273 snd_soc_component_write_field(component, 2274 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2275 WCD938X_TXD0_CLK_EN_MASK, 1); 2276 break; 2277 case 1: 2278 snd_soc_component_write_field(component, 2279 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2280 WCD938X_TXD1_MODE_MASK, mode); 2281 snd_soc_component_write_field(component, 2282 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2283 WCD938X_TXD1_CLK_EN_MASK, 1); 2284 break; 2285 case 2: 2286 snd_soc_component_write_field(component, 2287 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2288 WCD938X_TXD2_MODE_MASK, mode); 2289 snd_soc_component_write_field(component, 2290 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2291 WCD938X_TXD2_CLK_EN_MASK, 1); 2292 break; 2293 case 3: 2294 snd_soc_component_write_field(component, 2295 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2296 WCD938X_TXD3_MODE_MASK, mode); 2297 snd_soc_component_write_field(component, 2298 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2299 WCD938X_TXD3_CLK_EN_MASK, 1); 2300 break; 2301 default: 2302 break; 2303 } 2304 2305 wcd938x_tx_channel_config(component, w->shift, 0); 2306 break; 2307 case SND_SOC_DAPM_POST_PMD: 2308 switch (w->shift) { 2309 case 0: 2310 snd_soc_component_write_field(component, 2311 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2312 WCD938X_TXD0_MODE_MASK, 0); 2313 snd_soc_component_write_field(component, 2314 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2315 WCD938X_TXD0_CLK_EN_MASK, 0); 2316 break; 2317 case 1: 2318 snd_soc_component_write_field(component, 2319 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2320 WCD938X_TXD1_MODE_MASK, 0); 2321 snd_soc_component_write_field(component, 2322 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2323 WCD938X_TXD1_CLK_EN_MASK, 0); 2324 break; 2325 case 2: 2326 snd_soc_component_write_field(component, 2327 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2328 WCD938X_TXD2_MODE_MASK, 0); 2329 snd_soc_component_write_field(component, 2330 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2331 WCD938X_TXD2_CLK_EN_MASK, 0); 2332 break; 2333 case 3: 2334 snd_soc_component_write_field(component, 2335 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2336 WCD938X_TXD3_MODE_MASK, 0); 2337 snd_soc_component_write_field(component, 2338 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2339 WCD938X_TXD3_CLK_EN_MASK, 0); 2340 break; 2341 default: 2342 break; 2343 } 2344 snd_soc_component_write_field(component, 2345 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2346 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 2347 break; 2348 } 2349 2350 return 0; 2351 } 2352 2353 static int wcd938x_micbias_control(struct snd_soc_component *component, 2354 int micb_num, int req, bool is_dapm) 2355 { 2356 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2357 int micb_index = micb_num - 1; 2358 u16 micb_reg; 2359 2360 switch (micb_num) { 2361 case MIC_BIAS_1: 2362 micb_reg = WCD938X_ANA_MICB1; 2363 break; 2364 case MIC_BIAS_2: 2365 micb_reg = WCD938X_ANA_MICB2; 2366 break; 2367 case MIC_BIAS_3: 2368 micb_reg = WCD938X_ANA_MICB3; 2369 break; 2370 case MIC_BIAS_4: 2371 micb_reg = WCD938X_ANA_MICB4; 2372 break; 2373 default: 2374 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2375 __func__, micb_num); 2376 return -EINVAL; 2377 } 2378 2379 switch (req) { 2380 case MICB_PULLUP_ENABLE: 2381 wcd938x->pullup_ref[micb_index]++; 2382 if ((wcd938x->pullup_ref[micb_index] == 1) && 2383 (wcd938x->micb_ref[micb_index] == 0)) 2384 snd_soc_component_write_field(component, micb_reg, 2385 WCD938X_MICB_EN_MASK, 2386 WCD938X_MICB_PULL_UP); 2387 break; 2388 case MICB_PULLUP_DISABLE: 2389 if (wcd938x->pullup_ref[micb_index] > 0) 2390 wcd938x->pullup_ref[micb_index]--; 2391 2392 if ((wcd938x->pullup_ref[micb_index] == 0) && 2393 (wcd938x->micb_ref[micb_index] == 0)) 2394 snd_soc_component_write_field(component, micb_reg, 2395 WCD938X_MICB_EN_MASK, 0); 2396 break; 2397 case MICB_ENABLE: 2398 wcd938x->micb_ref[micb_index]++; 2399 if (wcd938x->micb_ref[micb_index] == 1) { 2400 snd_soc_component_write_field(component, 2401 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2402 WCD938X_TX_CLK_EN_MASK, 0xF); 2403 snd_soc_component_write_field(component, 2404 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2405 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2406 snd_soc_component_write_field(component, 2407 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 2408 WCD938X_TX_SC_CLK_EN_MASK, 1); 2409 2410 snd_soc_component_write_field(component, micb_reg, 2411 WCD938X_MICB_EN_MASK, 2412 WCD938X_MICB_ENABLE); 2413 if (micb_num == MIC_BIAS_2) 2414 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2415 WCD_EVENT_POST_MICBIAS_2_ON); 2416 } 2417 if (micb_num == MIC_BIAS_2 && is_dapm) 2418 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2419 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2420 2421 2422 break; 2423 case MICB_DISABLE: 2424 if (wcd938x->micb_ref[micb_index] > 0) 2425 wcd938x->micb_ref[micb_index]--; 2426 2427 if ((wcd938x->micb_ref[micb_index] == 0) && 2428 (wcd938x->pullup_ref[micb_index] > 0)) 2429 snd_soc_component_write_field(component, micb_reg, 2430 WCD938X_MICB_EN_MASK, 2431 WCD938X_MICB_PULL_UP); 2432 else if ((wcd938x->micb_ref[micb_index] == 0) && 2433 (wcd938x->pullup_ref[micb_index] == 0)) { 2434 if (micb_num == MIC_BIAS_2) 2435 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2436 WCD_EVENT_PRE_MICBIAS_2_OFF); 2437 2438 snd_soc_component_write_field(component, micb_reg, 2439 WCD938X_MICB_EN_MASK, 0); 2440 if (micb_num == MIC_BIAS_2) 2441 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2442 WCD_EVENT_POST_MICBIAS_2_OFF); 2443 } 2444 if (is_dapm && micb_num == MIC_BIAS_2) 2445 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2446 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2447 break; 2448 } 2449 2450 return 0; 2451 } 2452 2453 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2454 struct snd_kcontrol *kcontrol, 2455 int event) 2456 { 2457 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2458 int micb_num = w->shift; 2459 2460 switch (event) { 2461 case SND_SOC_DAPM_PRE_PMU: 2462 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 2463 break; 2464 case SND_SOC_DAPM_POST_PMU: 2465 /* 1 msec delay as per HW requirement */ 2466 usleep_range(1000, 1100); 2467 break; 2468 case SND_SOC_DAPM_POST_PMD: 2469 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 2470 break; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 2477 struct snd_kcontrol *kcontrol, 2478 int event) 2479 { 2480 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2481 int micb_num = w->shift; 2482 2483 switch (event) { 2484 case SND_SOC_DAPM_PRE_PMU: 2485 wcd938x_micbias_control(component, micb_num, 2486 MICB_PULLUP_ENABLE, true); 2487 break; 2488 case SND_SOC_DAPM_POST_PMU: 2489 /* 1 msec delay as per HW requirement */ 2490 usleep_range(1000, 1100); 2491 break; 2492 case SND_SOC_DAPM_POST_PMD: 2493 wcd938x_micbias_control(component, micb_num, 2494 MICB_PULLUP_DISABLE, true); 2495 break; 2496 } 2497 2498 return 0; 2499 } 2500 2501 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 2502 struct snd_ctl_elem_value *ucontrol) 2503 { 2504 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2505 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2506 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2507 int path = e->shift_l; 2508 2509 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 2510 2511 return 0; 2512 } 2513 2514 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 2515 struct snd_ctl_elem_value *ucontrol) 2516 { 2517 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2518 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2519 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2520 int path = e->shift_l; 2521 2522 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 2523 2524 return 1; 2525 } 2526 2527 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 2528 struct snd_ctl_elem_value *ucontrol) 2529 { 2530 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2531 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2532 2533 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 2534 2535 return 0; 2536 } 2537 2538 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 2539 struct snd_ctl_elem_value *ucontrol) 2540 { 2541 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2542 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2543 2544 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 2545 2546 return 1; 2547 } 2548 2549 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 2550 struct snd_ctl_elem_value *ucontrol) 2551 { 2552 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2553 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2554 2555 if (wcd938x->comp1_enable) { 2556 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 2557 return -EINVAL; 2558 } 2559 2560 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2561 WCD938X_EAR_GAIN_MASK, 2562 ucontrol->value.integer.value[0]); 2563 2564 return 1; 2565 } 2566 2567 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 2568 struct snd_ctl_elem_value *ucontrol) 2569 { 2570 2571 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2572 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2573 struct soc_mixer_control *mc; 2574 bool hphr; 2575 2576 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2577 hphr = mc->shift; 2578 2579 if (hphr) 2580 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 2581 else 2582 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 2583 2584 return 0; 2585 } 2586 2587 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 2588 struct snd_ctl_elem_value *ucontrol) 2589 { 2590 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2591 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2592 struct wcd938x_sdw_priv *wcd; 2593 int value = ucontrol->value.integer.value[0]; 2594 int portidx; 2595 struct soc_mixer_control *mc; 2596 bool hphr; 2597 2598 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2599 hphr = mc->shift; 2600 2601 wcd = wcd938x->sdw_priv[AIF1_PB]; 2602 2603 if (hphr) 2604 wcd938x->comp2_enable = value; 2605 else 2606 wcd938x->comp1_enable = value; 2607 2608 portidx = wcd->ch_info[mc->reg].port_num; 2609 2610 if (value) 2611 wcd938x_connect_port(wcd, portidx, mc->reg, true); 2612 else 2613 wcd938x_connect_port(wcd, portidx, mc->reg, false); 2614 2615 return 1; 2616 } 2617 2618 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 2619 struct snd_ctl_elem_value *ucontrol) 2620 { 2621 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2622 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2623 2624 ucontrol->value.integer.value[0] = wcd938x->ldoh; 2625 2626 return 0; 2627 } 2628 2629 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 2630 struct snd_ctl_elem_value *ucontrol) 2631 { 2632 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2633 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2634 2635 wcd938x->ldoh = ucontrol->value.integer.value[0]; 2636 2637 return 1; 2638 } 2639 2640 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol, 2641 struct snd_ctl_elem_value *ucontrol) 2642 { 2643 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2644 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2645 2646 ucontrol->value.integer.value[0] = wcd938x->bcs_dis; 2647 2648 return 0; 2649 } 2650 2651 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol, 2652 struct snd_ctl_elem_value *ucontrol) 2653 { 2654 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2655 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2656 2657 wcd938x->bcs_dis = ucontrol->value.integer.value[0]; 2658 2659 return 1; 2660 } 2661 2662 static const char * const tx_mode_mux_text_wcd9380[] = { 2663 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2664 }; 2665 2666 static const char * const tx_mode_mux_text[] = { 2667 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2668 "ADC_ULP1", "ADC_ULP2", 2669 }; 2670 2671 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 2672 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 2673 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 2674 "CLS_AB_LOHIFI", 2675 }; 2676 2677 static const char * const rx_hph_mode_mux_text[] = { 2678 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 2679 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 2680 }; 2681 2682 static const char * const adc2_mux_text[] = { 2683 "INP2", "INP3" 2684 }; 2685 2686 static const char * const adc3_mux_text[] = { 2687 "INP4", "INP6" 2688 }; 2689 2690 static const char * const adc4_mux_text[] = { 2691 "INP5", "INP7" 2692 }; 2693 2694 static const char * const rdac3_mux_text[] = { 2695 "RX1", "RX3" 2696 }; 2697 2698 static const char * const hdr12_mux_text[] = { 2699 "NO_HDR12", "HDR12" 2700 }; 2701 2702 static const char * const hdr34_mux_text[] = { 2703 "NO_HDR34", "HDR34" 2704 }; 2705 2706 static const struct soc_enum tx0_mode_enum_wcd9380 = 2707 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2708 tx_mode_mux_text_wcd9380); 2709 2710 static const struct soc_enum tx1_mode_enum_wcd9380 = 2711 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2712 tx_mode_mux_text_wcd9380); 2713 2714 static const struct soc_enum tx2_mode_enum_wcd9380 = 2715 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2716 tx_mode_mux_text_wcd9380); 2717 2718 static const struct soc_enum tx3_mode_enum_wcd9380 = 2719 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2720 tx_mode_mux_text_wcd9380); 2721 2722 static const struct soc_enum tx0_mode_enum_wcd9385 = 2723 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 2724 tx_mode_mux_text); 2725 2726 static const struct soc_enum tx1_mode_enum_wcd9385 = 2727 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 2728 tx_mode_mux_text); 2729 2730 static const struct soc_enum tx2_mode_enum_wcd9385 = 2731 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 2732 tx_mode_mux_text); 2733 2734 static const struct soc_enum tx3_mode_enum_wcd9385 = 2735 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 2736 tx_mode_mux_text); 2737 2738 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 2739 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 2740 rx_hph_mode_mux_text_wcd9380); 2741 2742 static const struct soc_enum rx_hph_mode_mux_enum = 2743 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 2744 rx_hph_mode_mux_text); 2745 2746 static const struct soc_enum adc2_enum = 2747 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 2748 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2749 2750 static const struct soc_enum adc3_enum = 2751 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 2752 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 2753 2754 static const struct soc_enum adc4_enum = 2755 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 2756 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 2757 2758 static const struct soc_enum hdr12_enum = 2759 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 2760 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 2761 2762 static const struct soc_enum hdr34_enum = 2763 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 2764 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 2765 2766 static const struct soc_enum rdac3_enum = 2767 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2768 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2769 2770 static const struct snd_kcontrol_new adc1_switch[] = { 2771 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2772 }; 2773 2774 static const struct snd_kcontrol_new adc2_switch[] = { 2775 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2776 }; 2777 2778 static const struct snd_kcontrol_new adc3_switch[] = { 2779 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2780 }; 2781 2782 static const struct snd_kcontrol_new adc4_switch[] = { 2783 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2784 }; 2785 2786 static const struct snd_kcontrol_new dmic1_switch[] = { 2787 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2788 }; 2789 2790 static const struct snd_kcontrol_new dmic2_switch[] = { 2791 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2792 }; 2793 2794 static const struct snd_kcontrol_new dmic3_switch[] = { 2795 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2796 }; 2797 2798 static const struct snd_kcontrol_new dmic4_switch[] = { 2799 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2800 }; 2801 2802 static const struct snd_kcontrol_new dmic5_switch[] = { 2803 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2804 }; 2805 2806 static const struct snd_kcontrol_new dmic6_switch[] = { 2807 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2808 }; 2809 2810 static const struct snd_kcontrol_new dmic7_switch[] = { 2811 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2812 }; 2813 2814 static const struct snd_kcontrol_new dmic8_switch[] = { 2815 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2816 }; 2817 2818 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2819 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2820 }; 2821 2822 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2823 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2824 }; 2825 2826 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2827 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2828 }; 2829 2830 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2831 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2832 }; 2833 2834 static const struct snd_kcontrol_new tx_adc2_mux = 2835 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2836 2837 static const struct snd_kcontrol_new tx_adc3_mux = 2838 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 2839 2840 static const struct snd_kcontrol_new tx_adc4_mux = 2841 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 2842 2843 static const struct snd_kcontrol_new tx_hdr12_mux = 2844 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 2845 2846 static const struct snd_kcontrol_new tx_hdr34_mux = 2847 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 2848 2849 static const struct snd_kcontrol_new rx_rdac3_mux = 2850 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2851 2852 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 2853 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 2854 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2855 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 2856 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2857 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 2858 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2859 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 2860 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2861 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 2862 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2863 }; 2864 2865 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 2866 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2867 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2868 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 2869 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2870 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 2871 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2872 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 2873 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2874 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 2875 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2876 }; 2877 2878 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 2879 struct snd_ctl_elem_value *ucontrol) 2880 { 2881 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2882 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2883 struct wcd938x_sdw_priv *wcd; 2884 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 2885 int dai_id = mixer->shift; 2886 int portidx, ch_idx = mixer->reg; 2887 2888 2889 wcd = wcd938x->sdw_priv[dai_id]; 2890 portidx = wcd->ch_info[ch_idx].port_num; 2891 2892 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 2893 2894 return 0; 2895 } 2896 2897 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 2898 struct snd_ctl_elem_value *ucontrol) 2899 { 2900 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2901 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2902 struct wcd938x_sdw_priv *wcd; 2903 struct soc_mixer_control *mixer = 2904 (struct soc_mixer_control *)kcontrol->private_value; 2905 int ch_idx = mixer->reg; 2906 int portidx; 2907 int dai_id = mixer->shift; 2908 bool enable; 2909 2910 wcd = wcd938x->sdw_priv[dai_id]; 2911 2912 portidx = wcd->ch_info[ch_idx].port_num; 2913 if (ucontrol->value.integer.value[0]) 2914 enable = true; 2915 else 2916 enable = false; 2917 2918 wcd->port_enable[portidx] = enable; 2919 2920 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 2921 2922 return 1; 2923 2924 } 2925 2926 /* MBHC related */ 2927 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 2928 bool enable) 2929 { 2930 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 2931 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 2932 } 2933 2934 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2935 bool enable) 2936 { 2937 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 2938 WCD938X_ANA_MBHC_BIAS_EN, enable); 2939 } 2940 2941 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 2942 int *btn_low, int *btn_high, 2943 int num_btn, bool is_micbias) 2944 { 2945 int i, vth; 2946 2947 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2948 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2949 __func__, num_btn); 2950 return; 2951 } 2952 2953 for (i = 0; i < num_btn; i++) { 2954 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2955 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 2956 WCD938X_MBHC_BTN_VTH_MASK, vth); 2957 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 2958 __func__, i, btn_high[i], vth); 2959 } 2960 } 2961 2962 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2963 { 2964 u8 val; 2965 2966 if (micb_num == MIC_BIAS_2) { 2967 val = snd_soc_component_read_field(component, 2968 WCD938X_ANA_MICB2, 2969 WCD938X_ANA_MICB2_ENABLE_MASK); 2970 if (val == WCD938X_MICB_ENABLE) 2971 return true; 2972 } 2973 return false; 2974 } 2975 2976 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2977 int pull_up_cur) 2978 { 2979 /* Default pull up current to 2uA */ 2980 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 2981 pull_up_cur = HS_PULLUP_I_2P0_UA; 2982 2983 snd_soc_component_write_field(component, 2984 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 2985 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 2986 } 2987 2988 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 2989 int micb_num, int req) 2990 { 2991 return wcd938x_micbias_control(component, micb_num, req, false); 2992 } 2993 2994 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2995 bool enable) 2996 { 2997 if (enable) { 2998 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2999 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 3000 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 3001 WCD938X_RAMP_EN_MASK, 1); 3002 } else { 3003 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 3004 WCD938X_RAMP_EN_MASK, 0); 3005 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 3006 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 3007 } 3008 } 3009 3010 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 3011 { 3012 /* min micbias voltage is 1V and maximum is 2.85V */ 3013 if (micb_mv < 1000 || micb_mv > 2850) 3014 return -EINVAL; 3015 3016 return (micb_mv - 1000) / 50; 3017 } 3018 3019 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 3020 int req_volt, int micb_num) 3021 { 3022 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3023 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 3024 3025 switch (micb_num) { 3026 case MIC_BIAS_1: 3027 micb_reg = WCD938X_ANA_MICB1; 3028 break; 3029 case MIC_BIAS_2: 3030 micb_reg = WCD938X_ANA_MICB2; 3031 break; 3032 case MIC_BIAS_3: 3033 micb_reg = WCD938X_ANA_MICB3; 3034 break; 3035 case MIC_BIAS_4: 3036 micb_reg = WCD938X_ANA_MICB4; 3037 break; 3038 default: 3039 return -EINVAL; 3040 } 3041 mutex_lock(&wcd938x->micb_lock); 3042 /* 3043 * If requested micbias voltage is same as current micbias 3044 * voltage, then just return. Otherwise, adjust voltage as 3045 * per requested value. If micbias is already enabled, then 3046 * to avoid slow micbias ramp-up or down enable pull-up 3047 * momentarily, change the micbias value and then re-enable 3048 * micbias. 3049 */ 3050 micb_en = snd_soc_component_read_field(component, micb_reg, 3051 WCD938X_MICB_EN_MASK); 3052 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 3053 WCD938X_MICB_VOUT_MASK); 3054 3055 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 3056 if (req_vout_ctl < 0) { 3057 ret = -EINVAL; 3058 goto exit; 3059 } 3060 3061 if (cur_vout_ctl == req_vout_ctl) { 3062 ret = 0; 3063 goto exit; 3064 } 3065 3066 if (micb_en == WCD938X_MICB_ENABLE) 3067 snd_soc_component_write_field(component, micb_reg, 3068 WCD938X_MICB_EN_MASK, 3069 WCD938X_MICB_PULL_UP); 3070 3071 snd_soc_component_write_field(component, micb_reg, 3072 WCD938X_MICB_VOUT_MASK, 3073 req_vout_ctl); 3074 3075 if (micb_en == WCD938X_MICB_ENABLE) { 3076 snd_soc_component_write_field(component, micb_reg, 3077 WCD938X_MICB_EN_MASK, 3078 WCD938X_MICB_ENABLE); 3079 /* 3080 * Add 2ms delay as per HW requirement after enabling 3081 * micbias 3082 */ 3083 usleep_range(2000, 2100); 3084 } 3085 exit: 3086 mutex_unlock(&wcd938x->micb_lock); 3087 return ret; 3088 } 3089 3090 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 3091 int micb_num, bool req_en) 3092 { 3093 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3094 int micb_mv; 3095 3096 if (micb_num != MIC_BIAS_2) 3097 return -EINVAL; 3098 /* 3099 * If device tree micbias level is already above the minimum 3100 * voltage needed to detect threshold microphone, then do 3101 * not change the micbias, just return. 3102 */ 3103 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 3104 return 0; 3105 3106 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 3107 3108 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 3109 } 3110 3111 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x, 3112 s16 *d1_a, u16 noff, 3113 int32_t *zdet) 3114 { 3115 int i; 3116 int val, val1; 3117 s16 c1; 3118 s32 x1, d1; 3119 int32_t denom; 3120 int minCode_param[] = { 3121 3277, 1639, 820, 410, 205, 103, 52, 26 3122 }; 3123 3124 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 3125 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 3126 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 3127 if (val & 0x80) 3128 break; 3129 } 3130 val = val << 0x8; 3131 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 3132 val |= val1; 3133 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 3134 x1 = WCD938X_MBHC_GET_X1(val); 3135 c1 = WCD938X_MBHC_GET_C1(val); 3136 /* If ramp is not complete, give additional 5ms */ 3137 if ((c1 < 2) && x1) 3138 usleep_range(5000, 5050); 3139 3140 if (!c1 || !x1) { 3141 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 3142 __func__, c1, x1); 3143 goto ramp_down; 3144 } 3145 d1 = d1_a[c1]; 3146 denom = (x1 * d1) - (1 << (14 - noff)); 3147 if (denom > 0) 3148 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 3149 else if (x1 < minCode_param[noff]) 3150 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 3151 3152 pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 3153 __func__, d1, c1, x1, *zdet); 3154 ramp_down: 3155 i = 0; 3156 while (x1) { 3157 regmap_read(wcd938x->regmap, 3158 WCD938X_ANA_MBHC_RESULT_1, &val); 3159 regmap_read(wcd938x->regmap, 3160 WCD938X_ANA_MBHC_RESULT_2, &val1); 3161 val = val << 0x08; 3162 val |= val1; 3163 x1 = WCD938X_MBHC_GET_X1(val); 3164 i++; 3165 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 3166 break; 3167 } 3168 } 3169 3170 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 3171 struct wcd938x_mbhc_zdet_param *zdet_param, 3172 int32_t *zl, int32_t *zr, s16 *d1_a) 3173 { 3174 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3175 int32_t zdet = 0; 3176 3177 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3178 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 3179 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 3180 WCD938X_VTH_MASK, zdet_param->btn5); 3181 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 3182 WCD938X_VTH_MASK, zdet_param->btn6); 3183 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 3184 WCD938X_VTH_MASK, zdet_param->btn7); 3185 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3186 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 3187 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 3188 0x0F, zdet_param->nshift); 3189 3190 if (!zl) 3191 goto z_right; 3192 /* Start impedance measurement for HPH_L */ 3193 regmap_update_bits(wcd938x->regmap, 3194 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 3195 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 3196 __func__, zdet_param->noff); 3197 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3198 regmap_update_bits(wcd938x->regmap, 3199 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 3200 3201 *zl = zdet; 3202 3203 z_right: 3204 if (!zr) 3205 return; 3206 /* Start impedance measurement for HPH_R */ 3207 regmap_update_bits(wcd938x->regmap, 3208 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 3209 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 3210 __func__, zdet_param->noff); 3211 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3212 regmap_update_bits(wcd938x->regmap, 3213 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 3214 3215 *zr = zdet; 3216 } 3217 3218 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 3219 int32_t *z_val, int flag_l_r) 3220 { 3221 s16 q1; 3222 int q1_cal; 3223 3224 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 3225 q1 = snd_soc_component_read(component, 3226 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 3227 else 3228 q1 = snd_soc_component_read(component, 3229 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 3230 if (q1 & 0x80) 3231 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 3232 else 3233 q1_cal = (10000 + (q1 * 25)); 3234 if (q1_cal > 0) 3235 *z_val = ((*z_val) * 10000) / q1_cal; 3236 } 3237 3238 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 3239 uint32_t *zl, uint32_t *zr) 3240 { 3241 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3242 s16 reg0, reg1, reg2, reg3, reg4; 3243 int32_t z1L, z1R, z1Ls; 3244 int zMono, z_diff1, z_diff2; 3245 bool is_fsm_disable = false; 3246 struct wcd938x_mbhc_zdet_param zdet_param[] = { 3247 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 3248 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 3249 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 3250 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 3251 }; 3252 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 3253 s16 d1_a[][4] = { 3254 {0, 30, 90, 30}, 3255 {0, 30, 30, 5}, 3256 {0, 30, 30, 5}, 3257 {0, 30, 30, 5}, 3258 }; 3259 s16 *d1 = NULL; 3260 3261 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 3262 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 3263 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 3264 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 3265 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 3266 3267 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 3268 is_fsm_disable = true; 3269 regmap_update_bits(wcd938x->regmap, 3270 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 3271 } 3272 3273 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 3274 if (wcd938x->mbhc_cfg.hphl_swh) 3275 regmap_update_bits(wcd938x->regmap, 3276 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 3277 3278 /* Turn off 100k pull down on HPHL */ 3279 regmap_update_bits(wcd938x->regmap, 3280 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 3281 3282 /* Disable surge protection before impedance detection. 3283 * This is done to give correct value for high impedance. 3284 */ 3285 regmap_update_bits(wcd938x->regmap, 3286 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 3287 /* 1ms delay needed after disable surge protection */ 3288 usleep_range(1000, 1010); 3289 3290 /* First get impedance on Left */ 3291 d1 = d1_a[1]; 3292 zdet_param_ptr = &zdet_param[1]; 3293 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3294 3295 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 3296 goto left_ch_impedance; 3297 3298 /* Second ramp for left ch */ 3299 if (z1L < WCD938X_ZDET_VAL_32) { 3300 zdet_param_ptr = &zdet_param[0]; 3301 d1 = d1_a[0]; 3302 } else if ((z1L > WCD938X_ZDET_VAL_400) && 3303 (z1L <= WCD938X_ZDET_VAL_1200)) { 3304 zdet_param_ptr = &zdet_param[2]; 3305 d1 = d1_a[2]; 3306 } else if (z1L > WCD938X_ZDET_VAL_1200) { 3307 zdet_param_ptr = &zdet_param[3]; 3308 d1 = d1_a[3]; 3309 } 3310 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3311 3312 left_ch_impedance: 3313 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3314 (z1L > WCD938X_ZDET_VAL_100K)) { 3315 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 3316 zdet_param_ptr = &zdet_param[1]; 3317 d1 = d1_a[1]; 3318 } else { 3319 *zl = z1L/1000; 3320 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 3321 } 3322 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 3323 __func__, *zl); 3324 3325 /* Start of right impedance ramp and calculation */ 3326 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3327 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 3328 if (((z1R > WCD938X_ZDET_VAL_1200) && 3329 (zdet_param_ptr->noff == 0x6)) || 3330 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 3331 goto right_ch_impedance; 3332 /* Second ramp for right ch */ 3333 if (z1R < WCD938X_ZDET_VAL_32) { 3334 zdet_param_ptr = &zdet_param[0]; 3335 d1 = d1_a[0]; 3336 } else if ((z1R > WCD938X_ZDET_VAL_400) && 3337 (z1R <= WCD938X_ZDET_VAL_1200)) { 3338 zdet_param_ptr = &zdet_param[2]; 3339 d1 = d1_a[2]; 3340 } else if (z1R > WCD938X_ZDET_VAL_1200) { 3341 zdet_param_ptr = &zdet_param[3]; 3342 d1 = d1_a[3]; 3343 } 3344 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3345 } 3346 right_ch_impedance: 3347 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3348 (z1R > WCD938X_ZDET_VAL_100K)) { 3349 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 3350 } else { 3351 *zr = z1R/1000; 3352 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 3353 } 3354 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 3355 __func__, *zr); 3356 3357 /* Mono/stereo detection */ 3358 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 3359 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 3360 dev_dbg(component->dev, 3361 "%s: plug type is invalid or extension cable\n", 3362 __func__); 3363 goto zdet_complete; 3364 } 3365 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3366 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3367 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 3368 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 3369 dev_dbg(component->dev, 3370 "%s: Mono plug type with one ch floating or shorted to GND\n", 3371 __func__); 3372 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3373 goto zdet_complete; 3374 } 3375 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3376 WCD938X_HPHPA_GND_OVR_MASK, 1); 3377 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3378 WCD938X_HPHPA_GND_R_MASK, 1); 3379 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 3380 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 3381 else 3382 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 3383 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3384 WCD938X_HPHPA_GND_R_MASK, 0); 3385 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3386 WCD938X_HPHPA_GND_OVR_MASK, 0); 3387 z1Ls /= 1000; 3388 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 3389 /* Parallel of left Z and 9 ohm pull down resistor */ 3390 zMono = ((*zl) * 9) / ((*zl) + 9); 3391 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 3392 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 3393 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 3394 dev_dbg(component->dev, "%s: stereo plug type detected\n", 3395 __func__); 3396 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 3397 } else { 3398 dev_dbg(component->dev, "%s: MONO plug type detected\n", 3399 __func__); 3400 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3401 } 3402 3403 /* Enable surge protection again after impedance detection */ 3404 regmap_update_bits(wcd938x->regmap, 3405 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 3406 zdet_complete: 3407 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 3408 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 3409 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 3410 /* Turn on 100k pull down on HPHL */ 3411 regmap_update_bits(wcd938x->regmap, 3412 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 3413 3414 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 3415 if (wcd938x->mbhc_cfg.hphl_swh) 3416 regmap_update_bits(wcd938x->regmap, 3417 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 3418 3419 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 3420 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 3421 if (is_fsm_disable) 3422 regmap_update_bits(wcd938x->regmap, 3423 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 3424 } 3425 3426 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 3427 bool enable) 3428 { 3429 if (enable) { 3430 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3431 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 3432 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3433 WCD938X_MBHC_GND_DET_EN_MASK, 1); 3434 } else { 3435 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3436 WCD938X_MBHC_GND_DET_EN_MASK, 0); 3437 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3438 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 3439 } 3440 } 3441 3442 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 3443 bool enable) 3444 { 3445 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3446 WCD938X_HPHPA_GND_R_MASK, enable); 3447 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3448 WCD938X_HPHPA_GND_L_MASK, enable); 3449 } 3450 3451 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 3452 { 3453 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3454 3455 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3456 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3457 WCD938X_M_RTH_CTL_MASK, R_OFF); 3458 return; 3459 } 3460 3461 /* Do not enable moisture detection if jack type is NC */ 3462 if (!wcd938x->mbhc_cfg.hphl_swh) { 3463 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3464 __func__); 3465 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3466 WCD938X_M_RTH_CTL_MASK, R_OFF); 3467 return; 3468 } 3469 3470 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3471 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3472 } 3473 3474 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 3475 { 3476 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3477 3478 if (enable) 3479 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3480 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3481 else 3482 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3483 WCD938X_M_RTH_CTL_MASK, R_OFF); 3484 } 3485 3486 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 3487 { 3488 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3489 bool ret = false; 3490 3491 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3492 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3493 WCD938X_M_RTH_CTL_MASK, R_OFF); 3494 goto done; 3495 } 3496 3497 /* Do not enable moisture detection if jack type is NC */ 3498 if (!wcd938x->mbhc_cfg.hphl_swh) { 3499 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3500 __func__); 3501 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3502 WCD938X_M_RTH_CTL_MASK, R_OFF); 3503 goto done; 3504 } 3505 3506 /* 3507 * If moisture_en is already enabled, then skip to plug type 3508 * detection. 3509 */ 3510 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 3511 goto done; 3512 3513 wcd938x_mbhc_moisture_detect_en(component, true); 3514 /* Read moisture comparator status */ 3515 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 3516 & 0x20) ? 0 : 1); 3517 3518 done: 3519 return ret; 3520 3521 } 3522 3523 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 3524 bool enable) 3525 { 3526 snd_soc_component_write_field(component, 3527 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 3528 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 3529 } 3530 3531 static const struct wcd_mbhc_cb mbhc_cb = { 3532 .clk_setup = wcd938x_mbhc_clk_setup, 3533 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 3534 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 3535 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 3536 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 3537 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 3538 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 3539 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 3540 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 3541 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 3542 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 3543 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 3544 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 3545 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 3546 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 3547 }; 3548 3549 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 3550 struct snd_ctl_elem_value *ucontrol) 3551 { 3552 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3553 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3554 3555 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 3556 3557 return 0; 3558 } 3559 3560 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 3561 struct snd_ctl_elem_value *ucontrol) 3562 { 3563 uint32_t zl, zr; 3564 bool hphr; 3565 struct soc_mixer_control *mc; 3566 struct snd_soc_component *component = 3567 snd_soc_kcontrol_component(kcontrol); 3568 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3569 3570 mc = (struct soc_mixer_control *)(kcontrol->private_value); 3571 hphr = mc->shift; 3572 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 3573 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 3574 ucontrol->value.integer.value[0] = hphr ? zr : zl; 3575 3576 return 0; 3577 } 3578 3579 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3580 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 3581 wcd938x_get_hph_type, NULL), 3582 }; 3583 3584 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3585 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 3586 wcd938x_hph_impedance_get, NULL), 3587 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 3588 wcd938x_hph_impedance_get, NULL), 3589 }; 3590 3591 static int wcd938x_mbhc_init(struct snd_soc_component *component) 3592 { 3593 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3594 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 3595 3596 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3597 WCD938X_IRQ_MBHC_SW_DET); 3598 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3599 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 3600 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3601 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 3602 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3603 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3604 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3605 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 3606 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3607 WCD938X_IRQ_HPHL_OCP_INT); 3608 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3609 WCD938X_IRQ_HPHR_OCP_INT); 3610 3611 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3612 3613 snd_soc_add_component_controls(component, impedance_detect_controls, 3614 ARRAY_SIZE(impedance_detect_controls)); 3615 snd_soc_add_component_controls(component, hph_type_detect_controls, 3616 ARRAY_SIZE(hph_type_detect_controls)); 3617 3618 return 0; 3619 } 3620 /* END MBHC */ 3621 3622 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 3623 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 3624 wcd938x_get_compander, wcd938x_set_compander), 3625 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 3626 wcd938x_get_compander, wcd938x_set_compander), 3627 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 3628 wcd938x_get_swr_port, wcd938x_set_swr_port), 3629 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 3630 wcd938x_get_swr_port, wcd938x_set_swr_port), 3631 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 3632 wcd938x_get_swr_port, wcd938x_set_swr_port), 3633 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 3634 wcd938x_get_swr_port, wcd938x_set_swr_port), 3635 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 3636 wcd938x_get_swr_port, wcd938x_set_swr_port), 3637 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 3638 wcd938x_get_swr_port, wcd938x_set_swr_port), 3639 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain), 3640 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain), 3641 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 3642 2, 0x10, 0, ear_pa_gain), 3643 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 3644 wcd938x_get_swr_port, wcd938x_set_swr_port), 3645 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 3646 wcd938x_get_swr_port, wcd938x_set_swr_port), 3647 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 3648 wcd938x_get_swr_port, wcd938x_set_swr_port), 3649 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 3650 wcd938x_get_swr_port, wcd938x_set_swr_port), 3651 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 3652 wcd938x_get_swr_port, wcd938x_set_swr_port), 3653 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 3654 wcd938x_get_swr_port, wcd938x_set_swr_port), 3655 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 3656 wcd938x_get_swr_port, wcd938x_set_swr_port), 3657 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 3658 wcd938x_get_swr_port, wcd938x_set_swr_port), 3659 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 3660 wcd938x_get_swr_port, wcd938x_set_swr_port), 3661 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 3662 wcd938x_get_swr_port, wcd938x_set_swr_port), 3663 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 3664 wcd938x_get_swr_port, wcd938x_set_swr_port), 3665 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 3666 wcd938x_get_swr_port, wcd938x_set_swr_port), 3667 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 3668 wcd938x_get_swr_port, wcd938x_set_swr_port), 3669 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 3670 wcd938x_ldoh_get, wcd938x_ldoh_put), 3671 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0, 3672 wcd938x_bcs_get, wcd938x_bcs_put), 3673 3674 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 3675 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 3676 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 3677 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 3678 }; 3679 3680 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 3681 3682 /*input widgets*/ 3683 SND_SOC_DAPM_INPUT("AMIC1"), 3684 SND_SOC_DAPM_INPUT("AMIC2"), 3685 SND_SOC_DAPM_INPUT("AMIC3"), 3686 SND_SOC_DAPM_INPUT("AMIC4"), 3687 SND_SOC_DAPM_INPUT("AMIC5"), 3688 SND_SOC_DAPM_INPUT("AMIC6"), 3689 SND_SOC_DAPM_INPUT("AMIC7"), 3690 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 3691 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 3692 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 3693 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 3694 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 3695 3696 /*tx widgets*/ 3697 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 3698 wcd938x_codec_enable_adc, 3699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3700 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 3701 wcd938x_codec_enable_adc, 3702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3703 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 3704 wcd938x_codec_enable_adc, 3705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3706 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 3707 wcd938x_codec_enable_adc, 3708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3709 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 3710 wcd938x_codec_enable_dmic, 3711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3712 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 3713 wcd938x_codec_enable_dmic, 3714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3715 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 3716 wcd938x_codec_enable_dmic, 3717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3718 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 3719 wcd938x_codec_enable_dmic, 3720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3721 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 3722 wcd938x_codec_enable_dmic, 3723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3724 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 3725 wcd938x_codec_enable_dmic, 3726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3727 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 3728 wcd938x_codec_enable_dmic, 3729 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3730 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 3731 wcd938x_codec_enable_dmic, 3732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3733 3734 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 3735 NULL, 0, wcd938x_adc_enable_req, 3736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3737 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 3738 NULL, 0, wcd938x_adc_enable_req, 3739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3740 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 3741 NULL, 0, wcd938x_adc_enable_req, 3742 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3743 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 3744 wcd938x_adc_enable_req, 3745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3746 3747 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 3748 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 3749 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 3750 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 3751 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 3752 3753 /*tx mixers*/ 3754 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 3755 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 3756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3757 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 3758 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 3759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3760 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 3761 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 3762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3763 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 3764 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 3765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3766 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 3767 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 3768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3769 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 3770 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 3771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3772 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 3773 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 3774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3775 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 3776 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 3777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3778 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 3779 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 3780 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3781 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 3782 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 3783 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3784 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 3785 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 3786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3787 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 3788 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 3789 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3790 /* micbias widgets*/ 3791 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3792 wcd938x_codec_enable_micbias, 3793 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3794 SND_SOC_DAPM_POST_PMD), 3795 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3796 wcd938x_codec_enable_micbias, 3797 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3798 SND_SOC_DAPM_POST_PMD), 3799 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3800 wcd938x_codec_enable_micbias, 3801 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3802 SND_SOC_DAPM_POST_PMD), 3803 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3804 wcd938x_codec_enable_micbias, 3805 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3806 SND_SOC_DAPM_POST_PMD), 3807 3808 /* micbias pull up widgets*/ 3809 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3810 wcd938x_codec_enable_micbias_pullup, 3811 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3812 SND_SOC_DAPM_POST_PMD), 3813 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3814 wcd938x_codec_enable_micbias_pullup, 3815 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3816 SND_SOC_DAPM_POST_PMD), 3817 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3818 wcd938x_codec_enable_micbias_pullup, 3819 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3820 SND_SOC_DAPM_POST_PMD), 3821 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3822 wcd938x_codec_enable_micbias_pullup, 3823 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3824 SND_SOC_DAPM_POST_PMD), 3825 3826 /*output widgets tx*/ 3827 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 3828 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 3829 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 3830 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 3831 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 3832 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 3833 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 3834 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 3835 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 3836 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 3837 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 3838 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 3839 3840 SND_SOC_DAPM_INPUT("IN1_HPHL"), 3841 SND_SOC_DAPM_INPUT("IN2_HPHR"), 3842 SND_SOC_DAPM_INPUT("IN3_AUX"), 3843 3844 /*rx widgets*/ 3845 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 3846 wcd938x_codec_enable_ear_pa, 3847 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3848 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3849 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 3850 wcd938x_codec_enable_aux_pa, 3851 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3852 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3853 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 3854 wcd938x_codec_enable_hphl_pa, 3855 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3856 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3857 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 3858 wcd938x_codec_enable_hphr_pa, 3859 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3860 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3861 3862 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 3863 wcd938x_codec_hphl_dac_event, 3864 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3865 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3866 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 3867 wcd938x_codec_hphr_dac_event, 3868 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3869 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3870 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 3871 wcd938x_codec_ear_dac_event, 3872 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3873 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3874 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 3875 wcd938x_codec_aux_dac_event, 3876 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3877 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3878 3879 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 3880 3881 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 3882 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 3883 wcd938x_codec_enable_rxclk, 3884 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3885 SND_SOC_DAPM_POST_PMD), 3886 3887 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 3888 3889 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3890 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3891 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3892 3893 /* rx mixer widgets*/ 3894 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 3895 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 3896 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 3897 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 3898 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 3899 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 3900 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 3901 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 3902 3903 /*output widgets rx*/ 3904 SND_SOC_DAPM_OUTPUT("EAR"), 3905 SND_SOC_DAPM_OUTPUT("AUX"), 3906 SND_SOC_DAPM_OUTPUT("HPHL"), 3907 SND_SOC_DAPM_OUTPUT("HPHR"), 3908 3909 }; 3910 3911 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 3912 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 3913 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 3914 {"ADC1 REQ", NULL, "ADC1"}, 3915 {"ADC1", NULL, "AMIC1"}, 3916 3917 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 3918 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 3919 {"ADC2 REQ", NULL, "ADC2"}, 3920 {"ADC2", NULL, "HDR12 MUX"}, 3921 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 3922 {"HDR12 MUX", "HDR12", "AMIC1"}, 3923 {"ADC2 MUX", "INP3", "AMIC3"}, 3924 {"ADC2 MUX", "INP2", "AMIC2"}, 3925 3926 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 3927 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 3928 {"ADC3 REQ", NULL, "ADC3"}, 3929 {"ADC3", NULL, "HDR34 MUX"}, 3930 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 3931 {"HDR34 MUX", "HDR34", "AMIC5"}, 3932 {"ADC3 MUX", "INP4", "AMIC4"}, 3933 {"ADC3 MUX", "INP6", "AMIC6"}, 3934 3935 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 3936 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 3937 {"ADC4 REQ", NULL, "ADC4"}, 3938 {"ADC4", NULL, "ADC4 MUX"}, 3939 {"ADC4 MUX", "INP5", "AMIC5"}, 3940 {"ADC4 MUX", "INP7", "AMIC7"}, 3941 3942 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 3943 {"DMIC1_MIXER", "Switch", "DMIC1"}, 3944 3945 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 3946 {"DMIC2_MIXER", "Switch", "DMIC2"}, 3947 3948 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 3949 {"DMIC3_MIXER", "Switch", "DMIC3"}, 3950 3951 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 3952 {"DMIC4_MIXER", "Switch", "DMIC4"}, 3953 3954 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 3955 {"DMIC5_MIXER", "Switch", "DMIC5"}, 3956 3957 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 3958 {"DMIC6_MIXER", "Switch", "DMIC6"}, 3959 3960 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 3961 {"DMIC7_MIXER", "Switch", "DMIC7"}, 3962 3963 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 3964 {"DMIC8_MIXER", "Switch", "DMIC8"}, 3965 3966 {"IN1_HPHL", NULL, "VDD_BUCK"}, 3967 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 3968 3969 {"RX1", NULL, "IN1_HPHL"}, 3970 {"RX1", NULL, "RXCLK"}, 3971 {"RDAC1", NULL, "RX1"}, 3972 {"HPHL_RDAC", "Switch", "RDAC1"}, 3973 {"HPHL PGA", NULL, "HPHL_RDAC"}, 3974 {"HPHL", NULL, "HPHL PGA"}, 3975 3976 {"IN2_HPHR", NULL, "VDD_BUCK"}, 3977 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 3978 {"RX2", NULL, "IN2_HPHR"}, 3979 {"RDAC2", NULL, "RX2"}, 3980 {"RX2", NULL, "RXCLK"}, 3981 {"HPHR_RDAC", "Switch", "RDAC2"}, 3982 {"HPHR PGA", NULL, "HPHR_RDAC"}, 3983 {"HPHR", NULL, "HPHR PGA"}, 3984 3985 {"IN3_AUX", NULL, "VDD_BUCK"}, 3986 {"IN3_AUX", NULL, "CLS_H_PORT"}, 3987 {"RX3", NULL, "IN3_AUX"}, 3988 {"RDAC4", NULL, "RX3"}, 3989 {"RX3", NULL, "RXCLK"}, 3990 {"AUX_RDAC", "Switch", "RDAC4"}, 3991 {"AUX PGA", NULL, "AUX_RDAC"}, 3992 {"AUX", NULL, "AUX PGA"}, 3993 3994 {"RDAC3_MUX", "RX3", "RX3"}, 3995 {"RDAC3_MUX", "RX1", "RX1"}, 3996 {"RDAC3", NULL, "RDAC3_MUX"}, 3997 {"EAR_RDAC", "Switch", "RDAC3"}, 3998 {"EAR PGA", NULL, "EAR_RDAC"}, 3999 {"EAR", NULL, "EAR PGA"}, 4000 }; 4001 4002 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 4003 { 4004 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 4005 4006 /* set micbias voltage */ 4007 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 4008 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 4009 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 4010 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 4011 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 4012 return -EINVAL; 4013 4014 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 4015 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 4016 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 4017 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 4018 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 4019 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 4020 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 4021 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 4022 4023 return 0; 4024 } 4025 4026 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 4027 { 4028 return IRQ_HANDLED; 4029 } 4030 4031 static struct irq_chip wcd_irq_chip = { 4032 .name = "WCD938x", 4033 }; 4034 4035 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 4036 irq_hw_number_t hw) 4037 { 4038 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 4039 irq_set_nested_thread(virq, 1); 4040 irq_set_noprobe(virq); 4041 4042 return 0; 4043 } 4044 4045 static const struct irq_domain_ops wcd_domain_ops = { 4046 .map = wcd_irq_chip_map, 4047 }; 4048 4049 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 4050 { 4051 4052 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 4053 if (!(wcd->virq)) { 4054 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 4055 return -EINVAL; 4056 } 4057 4058 return devm_regmap_add_irq_chip(dev, wcd->regmap, 4059 irq_create_mapping(wcd->virq, 0), 4060 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 4061 &wcd->irq_chip); 4062 } 4063 4064 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 4065 { 4066 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 4067 struct device *dev = component->dev; 4068 int ret, i; 4069 4070 snd_soc_component_init_regmap(component, wcd938x->regmap); 4071 4072 wcd938x->variant = snd_soc_component_read_field(component, 4073 WCD938X_DIGITAL_EFUSE_REG_0, 4074 WCD938X_ID_MASK); 4075 4076 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 4077 4078 wcd938x_io_init(wcd938x); 4079 /* Set all interrupts as edge triggered */ 4080 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 4081 regmap_write(wcd938x->regmap, 4082 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 4083 } 4084 4085 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4086 WCD938X_IRQ_HPHR_PDM_WD_INT); 4087 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4088 WCD938X_IRQ_HPHL_PDM_WD_INT); 4089 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4090 WCD938X_IRQ_AUX_PDM_WD_INT); 4091 4092 /* Request for watchdog interrupt */ 4093 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4094 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4095 "HPHR PDM WD INT", wcd938x); 4096 if (ret) 4097 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 4098 4099 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4100 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4101 "HPHL PDM WD INT", wcd938x); 4102 if (ret) 4103 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 4104 4105 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4106 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4107 "AUX PDM WD INT", wcd938x); 4108 if (ret) 4109 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 4110 4111 /* Disable watchdog interrupt for HPH and AUX */ 4112 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 4113 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 4114 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 4115 4116 switch (wcd938x->variant) { 4117 case WCD9380: 4118 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 4119 ARRAY_SIZE(wcd9380_snd_controls)); 4120 if (ret < 0) { 4121 dev_err(component->dev, 4122 "%s: Failed to add snd ctrls for variant: %d\n", 4123 __func__, wcd938x->variant); 4124 goto err; 4125 } 4126 break; 4127 case WCD9385: 4128 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 4129 ARRAY_SIZE(wcd9385_snd_controls)); 4130 if (ret < 0) { 4131 dev_err(component->dev, 4132 "%s: Failed to add snd ctrls for variant: %d\n", 4133 __func__, wcd938x->variant); 4134 goto err; 4135 } 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 ret = wcd938x_mbhc_init(component); 4142 if (ret) 4143 dev_err(component->dev, "mbhc initialization failed\n"); 4144 err: 4145 return ret; 4146 } 4147 4148 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 4149 struct snd_soc_jack *jack, void *data) 4150 { 4151 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 4152 4153 if (jack) 4154 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 4155 else 4156 wcd_mbhc_stop(wcd->wcd_mbhc); 4157 4158 return 0; 4159 } 4160 4161 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 4162 .name = "wcd938x_codec", 4163 .probe = wcd938x_soc_codec_probe, 4164 .controls = wcd938x_snd_controls, 4165 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 4166 .dapm_widgets = wcd938x_dapm_widgets, 4167 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 4168 .dapm_routes = wcd938x_audio_map, 4169 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 4170 .set_jack = wcd938x_codec_set_jack, 4171 .endianness = 1, 4172 }; 4173 4174 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 4175 { 4176 struct device_node *np = dev->of_node; 4177 u32 prop_val = 0; 4178 int rc = 0; 4179 4180 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 4181 if (!rc) 4182 wcd->micb1_mv = prop_val/1000; 4183 else 4184 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 4185 4186 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 4187 if (!rc) 4188 wcd->micb2_mv = prop_val/1000; 4189 else 4190 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 4191 4192 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 4193 if (!rc) 4194 wcd->micb3_mv = prop_val/1000; 4195 else 4196 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 4197 4198 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 4199 if (!rc) 4200 wcd->micb4_mv = prop_val/1000; 4201 else 4202 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 4203 } 4204 4205 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active) 4206 { 4207 int value; 4208 4209 struct wcd938x_priv *wcd938x; 4210 4211 wcd938x = snd_soc_component_get_drvdata(component); 4212 4213 value = gpiod_get_value(wcd938x->us_euro_gpio); 4214 4215 gpiod_set_value(wcd938x->us_euro_gpio, !value); 4216 4217 return true; 4218 } 4219 4220 4221 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 4222 { 4223 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 4224 int ret; 4225 4226 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0); 4227 if (wcd938x->reset_gpio < 0) { 4228 dev_err(dev, "Failed to get reset gpio: err = %d\n", 4229 wcd938x->reset_gpio); 4230 return wcd938x->reset_gpio; 4231 } 4232 4233 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", 4234 GPIOD_OUT_LOW); 4235 if (IS_ERR(wcd938x->us_euro_gpio)) { 4236 dev_err(dev, "us-euro swap Control GPIO not found\n"); 4237 return PTR_ERR(wcd938x->us_euro_gpio); 4238 } 4239 4240 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 4241 4242 wcd938x->supplies[0].supply = "vdd-rxtx"; 4243 wcd938x->supplies[1].supply = "vdd-io"; 4244 wcd938x->supplies[2].supply = "vdd-buck"; 4245 wcd938x->supplies[3].supply = "vdd-mic-bias"; 4246 4247 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies); 4248 if (ret) { 4249 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 4250 return ret; 4251 } 4252 4253 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 4254 if (ret) { 4255 dev_err(dev, "Failed to enable supplies: err = %d\n", ret); 4256 return ret; 4257 } 4258 4259 wcd938x_dt_parse_micbias_info(dev, wcd938x); 4260 4261 cfg->mbhc_micbias = MIC_BIAS_2; 4262 cfg->anc_micbias = MIC_BIAS_2; 4263 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 4264 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 4265 cfg->micb_mv = wcd938x->micb2_mv; 4266 cfg->linein_th = 5000; 4267 cfg->hs_thr = 1700; 4268 cfg->hph_thr = 50; 4269 4270 wcd_dt_parse_mbhc_data(dev, cfg); 4271 4272 return 0; 4273 } 4274 4275 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 4276 { 4277 gpio_direction_output(wcd938x->reset_gpio, 0); 4278 /* 20us sleep required after pulling the reset gpio to LOW */ 4279 usleep_range(20, 30); 4280 gpio_set_value(wcd938x->reset_gpio, 1); 4281 /* 20us sleep required after pulling the reset gpio to HIGH */ 4282 usleep_range(20, 30); 4283 4284 return 0; 4285 } 4286 4287 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 4288 struct snd_pcm_hw_params *params, 4289 struct snd_soc_dai *dai) 4290 { 4291 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4292 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4293 4294 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 4295 } 4296 4297 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 4298 struct snd_soc_dai *dai) 4299 { 4300 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4301 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4302 4303 return wcd938x_sdw_free(wcd, substream, dai); 4304 } 4305 4306 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 4307 void *stream, int direction) 4308 { 4309 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4310 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4311 4312 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 4313 4314 } 4315 4316 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 4317 .hw_params = wcd938x_codec_hw_params, 4318 .hw_free = wcd938x_codec_free, 4319 .set_stream = wcd938x_codec_set_sdw_stream, 4320 }; 4321 4322 static struct snd_soc_dai_driver wcd938x_dais[] = { 4323 [0] = { 4324 .name = "wcd938x-sdw-rx", 4325 .playback = { 4326 .stream_name = "WCD AIF1 Playback", 4327 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 4328 .formats = WCD938X_FORMATS_S16_S24_LE, 4329 .rate_max = 192000, 4330 .rate_min = 8000, 4331 .channels_min = 1, 4332 .channels_max = 2, 4333 }, 4334 .ops = &wcd938x_sdw_dai_ops, 4335 }, 4336 [1] = { 4337 .name = "wcd938x-sdw-tx", 4338 .capture = { 4339 .stream_name = "WCD AIF1 Capture", 4340 .rates = WCD938X_RATES_MASK, 4341 .formats = SNDRV_PCM_FMTBIT_S16_LE, 4342 .rate_min = 8000, 4343 .rate_max = 192000, 4344 .channels_min = 1, 4345 .channels_max = 4, 4346 }, 4347 .ops = &wcd938x_sdw_dai_ops, 4348 }, 4349 }; 4350 4351 static int wcd938x_bind(struct device *dev) 4352 { 4353 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4354 int ret; 4355 4356 ret = component_bind_all(dev, wcd938x); 4357 if (ret) { 4358 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 4359 __func__, ret); 4360 return ret; 4361 } 4362 4363 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 4364 if (!wcd938x->rxdev) { 4365 dev_err(dev, "could not find slave with matching of node\n"); 4366 return -EINVAL; 4367 } 4368 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 4369 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 4370 4371 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 4372 if (!wcd938x->txdev) { 4373 dev_err(dev, "could not find txslave with matching of node\n"); 4374 return -EINVAL; 4375 } 4376 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 4377 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 4378 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 4379 if (!wcd938x->tx_sdw_dev) { 4380 dev_err(dev, "could not get txslave with matching of dev\n"); 4381 return -EINVAL; 4382 } 4383 4384 /* As TX is main CSR reg interface, which should not be suspended first. 4385 * expicilty add the dependency link */ 4386 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 4387 DL_FLAG_PM_RUNTIME)) { 4388 dev_err(dev, "could not devlink tx and rx\n"); 4389 return -EINVAL; 4390 } 4391 4392 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 4393 DL_FLAG_PM_RUNTIME)) { 4394 dev_err(dev, "could not devlink wcd and tx\n"); 4395 return -EINVAL; 4396 } 4397 4398 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 4399 DL_FLAG_PM_RUNTIME)) { 4400 dev_err(dev, "could not devlink wcd and rx\n"); 4401 return -EINVAL; 4402 } 4403 4404 wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config); 4405 if (IS_ERR(wcd938x->regmap)) { 4406 dev_err(dev, "%s: tx csr regmap not found\n", __func__); 4407 return PTR_ERR(wcd938x->regmap); 4408 } 4409 4410 ret = wcd938x_irq_init(wcd938x, dev); 4411 if (ret) { 4412 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 4413 return ret; 4414 } 4415 4416 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 4417 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 4418 4419 ret = wcd938x_set_micbias_data(wcd938x); 4420 if (ret < 0) { 4421 dev_err(dev, "%s: bad micbias pdata\n", __func__); 4422 return ret; 4423 } 4424 4425 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 4426 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 4427 if (ret) 4428 dev_err(dev, "%s: Codec registration failed\n", 4429 __func__); 4430 4431 return ret; 4432 4433 } 4434 4435 static void wcd938x_unbind(struct device *dev) 4436 { 4437 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4438 4439 device_link_remove(dev, wcd938x->txdev); 4440 device_link_remove(dev, wcd938x->rxdev); 4441 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 4442 snd_soc_unregister_component(dev); 4443 component_unbind_all(dev, wcd938x); 4444 } 4445 4446 static const struct component_master_ops wcd938x_comp_ops = { 4447 .bind = wcd938x_bind, 4448 .unbind = wcd938x_unbind, 4449 }; 4450 4451 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 4452 struct device *dev, 4453 struct component_match **matchptr) 4454 { 4455 struct device_node *np; 4456 4457 np = dev->of_node; 4458 4459 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 4460 if (!wcd938x->rxnode) { 4461 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 4462 return -ENODEV; 4463 } 4464 4465 of_node_get(wcd938x->rxnode); 4466 component_match_add_release(dev, matchptr, component_release_of, 4467 component_compare_of, wcd938x->rxnode); 4468 4469 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 4470 if (!wcd938x->txnode) { 4471 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 4472 return -ENODEV; 4473 } 4474 of_node_get(wcd938x->txnode); 4475 component_match_add_release(dev, matchptr, component_release_of, 4476 component_compare_of, wcd938x->txnode); 4477 return 0; 4478 } 4479 4480 static int wcd938x_probe(struct platform_device *pdev) 4481 { 4482 struct component_match *match = NULL; 4483 struct wcd938x_priv *wcd938x = NULL; 4484 struct device *dev = &pdev->dev; 4485 int ret; 4486 4487 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 4488 GFP_KERNEL); 4489 if (!wcd938x) 4490 return -ENOMEM; 4491 4492 dev_set_drvdata(dev, wcd938x); 4493 mutex_init(&wcd938x->micb_lock); 4494 4495 ret = wcd938x_populate_dt_data(wcd938x, dev); 4496 if (ret) { 4497 dev_err(dev, "%s: Fail to obtain platform data\n", __func__); 4498 return -EINVAL; 4499 } 4500 4501 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 4502 if (ret) 4503 return ret; 4504 4505 wcd938x_reset(wcd938x); 4506 4507 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 4508 if (ret) 4509 return ret; 4510 4511 pm_runtime_set_autosuspend_delay(dev, 1000); 4512 pm_runtime_use_autosuspend(dev); 4513 pm_runtime_mark_last_busy(dev); 4514 pm_runtime_set_active(dev); 4515 pm_runtime_enable(dev); 4516 pm_runtime_idle(dev); 4517 4518 return 0; 4519 } 4520 4521 static int wcd938x_remove(struct platform_device *pdev) 4522 { 4523 component_master_del(&pdev->dev, &wcd938x_comp_ops); 4524 4525 return 0; 4526 } 4527 4528 #if defined(CONFIG_OF) 4529 static const struct of_device_id wcd938x_dt_match[] = { 4530 { .compatible = "qcom,wcd9380-codec" }, 4531 { .compatible = "qcom,wcd9385-codec" }, 4532 {} 4533 }; 4534 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 4535 #endif 4536 4537 static struct platform_driver wcd938x_codec_driver = { 4538 .probe = wcd938x_probe, 4539 .remove = wcd938x_remove, 4540 .driver = { 4541 .name = "wcd938x_codec", 4542 .of_match_table = of_match_ptr(wcd938x_dt_match), 4543 .suppress_bind_attrs = true, 4544 }, 4545 }; 4546 4547 module_platform_driver(wcd938x_codec_driver); 4548 MODULE_DESCRIPTION("WCD938X Codec driver"); 4549 MODULE_LICENSE("GPL"); 4550