1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/kernel.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/component.h> 13 #include <sound/tlv.h> 14 #include <linux/of_gpio.h> 15 #include <linux/of.h> 16 #include <sound/jack.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <linux/regmap.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd938x.h" 27 28 #define WCD938X_MAX_MICBIAS (4) 29 #define WCD938X_MAX_SUPPLY (4) 30 #define WCD938X_MBHC_MAX_BUTTONS (8) 31 #define TX_ADC_MAX (4) 32 #define WCD938X_TX_MAX_SWR_PORTS (5) 33 34 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 35 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 36 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 37 /* Fractional Rates */ 38 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 39 SNDRV_PCM_RATE_176400) 40 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 41 SNDRV_PCM_FMTBIT_S24_LE) 42 /* Convert from vout ctl to micbias voltage in mV */ 43 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50) 44 #define SWR_CLK_RATE_0P6MHZ (600000) 45 #define SWR_CLK_RATE_1P2MHZ (1200000) 46 #define SWR_CLK_RATE_2P4MHZ (2400000) 47 #define SWR_CLK_RATE_4P8MHZ (4800000) 48 #define SWR_CLK_RATE_9P6MHZ (9600000) 49 #define SWR_CLK_RATE_11P2896MHZ (1128960) 50 51 #define WCD938X_DRV_NAME "wcd938x_codec" 52 #define WCD938X_VERSION_1_0 (1) 53 #define EAR_RX_PATH_AUX (1) 54 55 #define ADC_MODE_VAL_HIFI 0x01 56 #define ADC_MODE_VAL_LO_HIF 0x02 57 #define ADC_MODE_VAL_NORMAL 0x03 58 #define ADC_MODE_VAL_LP 0x05 59 #define ADC_MODE_VAL_ULP1 0x09 60 #define ADC_MODE_VAL_ULP2 0x0B 61 62 /* Z value defined in milliohm */ 63 #define WCD938X_ZDET_VAL_32 (32000) 64 #define WCD938X_ZDET_VAL_400 (400000) 65 #define WCD938X_ZDET_VAL_1200 (1200000) 66 #define WCD938X_ZDET_VAL_100K (100000000) 67 /* Z floating defined in ohms */ 68 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 69 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 70 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 71 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 72 /* Z value compared in milliOhm */ 73 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 74 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 75 #define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM 76 #define WCD_MBHC_HS_V_MAX 1600 77 78 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 79 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 80 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 81 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 82 .tlv.p = (tlv_array), \ 83 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 84 .put = wcd938x_ear_pa_put_gain, \ 85 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 86 87 enum { 88 WCD9380 = 0, 89 WCD9385 = 5, 90 }; 91 92 enum { 93 TX_HDR12 = 0, 94 TX_HDR34, 95 TX_HDR_MAX, 96 }; 97 98 enum { 99 WCD_RX1, 100 WCD_RX2, 101 WCD_RX3 102 }; 103 104 enum { 105 /* INTR_CTRL_INT_MASK_0 */ 106 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 107 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 108 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 109 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 110 WCD938X_IRQ_MBHC_SW_DET, 111 WCD938X_IRQ_HPHR_OCP_INT, 112 WCD938X_IRQ_HPHR_CNP_INT, 113 WCD938X_IRQ_HPHL_OCP_INT, 114 115 /* INTR_CTRL_INT_MASK_1 */ 116 WCD938X_IRQ_HPHL_CNP_INT, 117 WCD938X_IRQ_EAR_CNP_INT, 118 WCD938X_IRQ_EAR_SCD_INT, 119 WCD938X_IRQ_AUX_CNP_INT, 120 WCD938X_IRQ_AUX_SCD_INT, 121 WCD938X_IRQ_HPHL_PDM_WD_INT, 122 WCD938X_IRQ_HPHR_PDM_WD_INT, 123 WCD938X_IRQ_AUX_PDM_WD_INT, 124 125 /* INTR_CTRL_INT_MASK_2 */ 126 WCD938X_IRQ_LDORT_SCD_INT, 127 WCD938X_IRQ_MBHC_MOISTURE_INT, 128 WCD938X_IRQ_HPHL_SURGE_DET_INT, 129 WCD938X_IRQ_HPHR_SURGE_DET_INT, 130 WCD938X_NUM_IRQS, 131 }; 132 133 enum { 134 WCD_ADC1 = 0, 135 WCD_ADC2, 136 WCD_ADC3, 137 WCD_ADC4, 138 ALLOW_BUCK_DISABLE, 139 HPH_COMP_DELAY, 140 HPH_PA_DELAY, 141 AMIC2_BCS_ENABLE, 142 WCD_SUPPLIES_LPM_MODE, 143 }; 144 145 enum { 146 ADC_MODE_INVALID = 0, 147 ADC_MODE_HIFI, 148 ADC_MODE_LO_HIF, 149 ADC_MODE_NORMAL, 150 ADC_MODE_LP, 151 ADC_MODE_ULP1, 152 ADC_MODE_ULP2, 153 }; 154 155 enum { 156 AIF1_PB = 0, 157 AIF1_CAP, 158 NUM_CODEC_DAIS, 159 }; 160 161 static u8 tx_mode_bit[] = { 162 [ADC_MODE_INVALID] = 0x00, 163 [ADC_MODE_HIFI] = 0x01, 164 [ADC_MODE_LO_HIF] = 0x02, 165 [ADC_MODE_NORMAL] = 0x04, 166 [ADC_MODE_LP] = 0x08, 167 [ADC_MODE_ULP1] = 0x10, 168 [ADC_MODE_ULP2] = 0x20, 169 }; 170 171 struct wcd938x_priv { 172 struct sdw_slave *tx_sdw_dev; 173 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 174 struct device *txdev; 175 struct device *rxdev; 176 struct device_node *rxnode, *txnode; 177 struct regmap *regmap; 178 struct mutex micb_lock; 179 /* mbhc module */ 180 struct wcd_mbhc *wcd_mbhc; 181 struct wcd_mbhc_config mbhc_cfg; 182 struct wcd_mbhc_intr intr_ids; 183 struct wcd_clsh_ctrl *clsh_info; 184 struct irq_domain *virq; 185 struct regmap_irq_chip *wcd_regmap_irq_chip; 186 struct regmap_irq_chip_data *irq_chip; 187 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY]; 188 struct snd_soc_jack *jack; 189 unsigned long status_mask; 190 s32 micb_ref[WCD938X_MAX_MICBIAS]; 191 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 192 u32 hph_mode; 193 u32 tx_mode[TX_ADC_MAX]; 194 int flyback_cur_det_disable; 195 int ear_rx_path; 196 int variant; 197 int reset_gpio; 198 struct gpio_desc *us_euro_gpio; 199 u32 micb1_mv; 200 u32 micb2_mv; 201 u32 micb3_mv; 202 u32 micb4_mv; 203 int hphr_pdm_wd_int; 204 int hphl_pdm_wd_int; 205 int aux_pdm_wd_int; 206 bool comp1_enable; 207 bool comp2_enable; 208 bool ldoh; 209 bool bcs_dis; 210 }; 211 212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 213 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000); 214 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 215 216 struct wcd938x_mbhc_zdet_param { 217 u16 ldo_ctl; 218 u16 noff; 219 u16 nshift; 220 u16 btn5; 221 u16 btn6; 222 u16 btn7; 223 }; 224 225 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 226 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 227 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 228 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 229 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 230 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 231 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 232 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 233 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 234 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 235 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 236 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 237 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 238 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 239 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 240 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 241 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 242 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 243 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 244 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 245 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 246 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 247 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 248 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 250 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 251 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 252 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 253 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 254 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 255 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 256 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 257 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 258 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 259 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 262 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 263 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 264 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 265 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 267 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 268 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 269 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 270 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 271 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 272 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 273 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 274 }; 275 276 static const struct reg_default wcd938x_defaults[] = { 277 {WCD938X_ANA_PAGE_REGISTER, 0x00}, 278 {WCD938X_ANA_BIAS, 0x00}, 279 {WCD938X_ANA_RX_SUPPLIES, 0x00}, 280 {WCD938X_ANA_HPH, 0x0C}, 281 {WCD938X_ANA_EAR, 0x00}, 282 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02}, 283 {WCD938X_ANA_TX_CH1, 0x20}, 284 {WCD938X_ANA_TX_CH2, 0x00}, 285 {WCD938X_ANA_TX_CH3, 0x20}, 286 {WCD938X_ANA_TX_CH4, 0x00}, 287 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00}, 288 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00}, 289 {WCD938X_ANA_MBHC_MECH, 0x39}, 290 {WCD938X_ANA_MBHC_ELECT, 0x08}, 291 {WCD938X_ANA_MBHC_ZDET, 0x00}, 292 {WCD938X_ANA_MBHC_RESULT_1, 0x00}, 293 {WCD938X_ANA_MBHC_RESULT_2, 0x00}, 294 {WCD938X_ANA_MBHC_RESULT_3, 0x00}, 295 {WCD938X_ANA_MBHC_BTN0, 0x00}, 296 {WCD938X_ANA_MBHC_BTN1, 0x10}, 297 {WCD938X_ANA_MBHC_BTN2, 0x20}, 298 {WCD938X_ANA_MBHC_BTN3, 0x30}, 299 {WCD938X_ANA_MBHC_BTN4, 0x40}, 300 {WCD938X_ANA_MBHC_BTN5, 0x50}, 301 {WCD938X_ANA_MBHC_BTN6, 0x60}, 302 {WCD938X_ANA_MBHC_BTN7, 0x70}, 303 {WCD938X_ANA_MICB1, 0x10}, 304 {WCD938X_ANA_MICB2, 0x10}, 305 {WCD938X_ANA_MICB2_RAMP, 0x00}, 306 {WCD938X_ANA_MICB3, 0x10}, 307 {WCD938X_ANA_MICB4, 0x10}, 308 {WCD938X_BIAS_CTL, 0x2A}, 309 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55}, 310 {WCD938X_LDOL_VDDCX_ADJUST, 0x01}, 311 {WCD938X_LDOL_DISABLE_LDOL, 0x00}, 312 {WCD938X_MBHC_CTL_CLK, 0x00}, 313 {WCD938X_MBHC_CTL_ANA, 0x00}, 314 {WCD938X_MBHC_CTL_SPARE_1, 0x00}, 315 {WCD938X_MBHC_CTL_SPARE_2, 0x00}, 316 {WCD938X_MBHC_CTL_BCS, 0x00}, 317 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00}, 318 {WCD938X_MBHC_TEST_CTL, 0x00}, 319 {WCD938X_LDOH_MODE, 0x2B}, 320 {WCD938X_LDOH_BIAS, 0x68}, 321 {WCD938X_LDOH_STB_LOADS, 0x00}, 322 {WCD938X_LDOH_SLOWRAMP, 0x50}, 323 {WCD938X_MICB1_TEST_CTL_1, 0x1A}, 324 {WCD938X_MICB1_TEST_CTL_2, 0x00}, 325 {WCD938X_MICB1_TEST_CTL_3, 0xA4}, 326 {WCD938X_MICB2_TEST_CTL_1, 0x1A}, 327 {WCD938X_MICB2_TEST_CTL_2, 0x00}, 328 {WCD938X_MICB2_TEST_CTL_3, 0x24}, 329 {WCD938X_MICB3_TEST_CTL_1, 0x1A}, 330 {WCD938X_MICB3_TEST_CTL_2, 0x00}, 331 {WCD938X_MICB3_TEST_CTL_3, 0xA4}, 332 {WCD938X_MICB4_TEST_CTL_1, 0x1A}, 333 {WCD938X_MICB4_TEST_CTL_2, 0x00}, 334 {WCD938X_MICB4_TEST_CTL_3, 0xA4}, 335 {WCD938X_TX_COM_ADC_VCM, 0x39}, 336 {WCD938X_TX_COM_BIAS_ATEST, 0xE0}, 337 {WCD938X_TX_COM_SPARE1, 0x00}, 338 {WCD938X_TX_COM_SPARE2, 0x00}, 339 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22}, 340 {WCD938X_TX_COM_TXFE_DIV_START, 0x00}, 341 {WCD938X_TX_COM_SPARE3, 0x00}, 342 {WCD938X_TX_COM_SPARE4, 0x00}, 343 {WCD938X_TX_1_2_TEST_EN, 0xCC}, 344 {WCD938X_TX_1_2_ADC_IB, 0xE9}, 345 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A}, 346 {WCD938X_TX_1_2_TEST_CTL, 0x38}, 347 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF}, 348 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00}, 349 {WCD938X_TX_1_2_SAR2_ERR, 0x00}, 350 {WCD938X_TX_1_2_SAR1_ERR, 0x00}, 351 {WCD938X_TX_3_4_TEST_EN, 0xCC}, 352 {WCD938X_TX_3_4_ADC_IB, 0xE9}, 353 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A}, 354 {WCD938X_TX_3_4_TEST_CTL, 0x38}, 355 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF}, 356 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00}, 357 {WCD938X_TX_3_4_SAR4_ERR, 0x00}, 358 {WCD938X_TX_3_4_SAR3_ERR, 0x00}, 359 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB}, 360 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00}, 361 {WCD938X_TX_3_4_SPARE1, 0x00}, 362 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB}, 363 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00}, 364 {WCD938X_TX_3_4_SPARE2, 0x00}, 365 {WCD938X_CLASSH_MODE_1, 0x40}, 366 {WCD938X_CLASSH_MODE_2, 0x3A}, 367 {WCD938X_CLASSH_MODE_3, 0x00}, 368 {WCD938X_CLASSH_CTRL_VCL_1, 0x70}, 369 {WCD938X_CLASSH_CTRL_VCL_2, 0x82}, 370 {WCD938X_CLASSH_CTRL_CCL_1, 0x31}, 371 {WCD938X_CLASSH_CTRL_CCL_2, 0x80}, 372 {WCD938X_CLASSH_CTRL_CCL_3, 0x80}, 373 {WCD938X_CLASSH_CTRL_CCL_4, 0x51}, 374 {WCD938X_CLASSH_CTRL_CCL_5, 0x00}, 375 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00}, 376 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77}, 377 {WCD938X_CLASSH_SPARE, 0x00}, 378 {WCD938X_FLYBACK_EN, 0x4E}, 379 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B}, 380 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45}, 381 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74}, 382 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F}, 383 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83}, 384 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98}, 385 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9}, 386 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68}, 387 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64}, 388 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED}, 389 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0}, 390 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6}, 391 {WCD938X_FLYBACK_CTRL_1, 0x65}, 392 {WCD938X_FLYBACK_TEST_CTL, 0x00}, 393 {WCD938X_RX_AUX_SW_CTL, 0x00}, 394 {WCD938X_RX_PA_AUX_IN_CONN, 0x01}, 395 {WCD938X_RX_TIMER_DIV, 0x32}, 396 {WCD938X_RX_OCP_CTL, 0x1F}, 397 {WCD938X_RX_OCP_COUNT, 0x77}, 398 {WCD938X_RX_BIAS_EAR_DAC, 0xA0}, 399 {WCD938X_RX_BIAS_EAR_AMP, 0xAA}, 400 {WCD938X_RX_BIAS_HPH_LDO, 0xA9}, 401 {WCD938X_RX_BIAS_HPH_PA, 0xAA}, 402 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A}, 403 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88}, 404 {WCD938X_RX_BIAS_HPH_CNP1, 0x82}, 405 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82}, 406 {WCD938X_RX_BIAS_AUX_DAC, 0xA0}, 407 {WCD938X_RX_BIAS_AUX_AMP, 0xAA}, 408 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50}, 409 {WCD938X_RX_BIAS_MISC, 0x00}, 410 {WCD938X_RX_BIAS_BUCK_RST, 0x08}, 411 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44}, 412 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40}, 413 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA}, 414 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14}, 415 {WCD938X_HPH_L_STATUS, 0x04}, 416 {WCD938X_HPH_R_STATUS, 0x04}, 417 {WCD938X_HPH_CNP_EN, 0x80}, 418 {WCD938X_HPH_CNP_WG_CTL, 0x9A}, 419 {WCD938X_HPH_CNP_WG_TIME, 0x14}, 420 {WCD938X_HPH_OCP_CTL, 0x28}, 421 {WCD938X_HPH_AUTO_CHOP, 0x16}, 422 {WCD938X_HPH_CHOP_CTL, 0x83}, 423 {WCD938X_HPH_PA_CTL1, 0x46}, 424 {WCD938X_HPH_PA_CTL2, 0x50}, 425 {WCD938X_HPH_L_EN, 0x80}, 426 {WCD938X_HPH_L_TEST, 0xE0}, 427 {WCD938X_HPH_L_ATEST, 0x50}, 428 {WCD938X_HPH_R_EN, 0x80}, 429 {WCD938X_HPH_R_TEST, 0xE0}, 430 {WCD938X_HPH_R_ATEST, 0x54}, 431 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99}, 432 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B}, 433 {WCD938X_HPH_RDAC_LDO_CTL, 0x33}, 434 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00}, 435 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68}, 436 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E}, 437 {WCD938X_HPH_L_DAC_CTL, 0x20}, 438 {WCD938X_HPH_R_DAC_CTL, 0x20}, 439 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55}, 440 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19}, 441 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0}, 442 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00}, 443 {WCD938X_EAR_EAR_EN_REG, 0x22}, 444 {WCD938X_EAR_EAR_PA_CON, 0x44}, 445 {WCD938X_EAR_EAR_SP_CON, 0xDB}, 446 {WCD938X_EAR_EAR_DAC_CON, 0x80}, 447 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2}, 448 {WCD938X_EAR_TEST_CTL, 0x00}, 449 {WCD938X_EAR_STATUS_REG_1, 0x00}, 450 {WCD938X_EAR_STATUS_REG_2, 0x08}, 451 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00}, 452 {WCD938X_HPH_NEW_ANA_HPH2, 0x00}, 453 {WCD938X_HPH_NEW_ANA_HPH3, 0x00}, 454 {WCD938X_SLEEP_CTL, 0x16}, 455 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00}, 456 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00}, 457 {WCD938X_MBHC_NEW_CTL_1, 0x02}, 458 {WCD938X_MBHC_NEW_CTL_2, 0x05}, 459 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9}, 460 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F}, 461 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00}, 462 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00}, 463 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00}, 464 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00}, 465 {WCD938X_AUX_AUXPA, 0x00}, 466 {WCD938X_LDORXTX_MODE, 0x0C}, 467 {WCD938X_LDORXTX_CONFIG, 0x10}, 468 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00}, 469 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00}, 470 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40}, 471 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81}, 472 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10}, 473 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00}, 474 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81}, 475 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22}, 476 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00}, 477 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00}, 478 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE}, 479 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02}, 480 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E}, 481 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54}, 482 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00}, 483 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00}, 484 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90}, 485 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90}, 486 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62}, 487 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01}, 488 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11}, 489 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57}, 490 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01}, 491 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00}, 492 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00}, 493 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8}, 494 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42}, 495 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22}, 496 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00}, 497 {WCD938X_AUX_INT_EN_REG, 0x00}, 498 {WCD938X_AUX_INT_PA_CTRL, 0x06}, 499 {WCD938X_AUX_INT_SP_CTRL, 0xD2}, 500 {WCD938X_AUX_INT_DAC_CTRL, 0x80}, 501 {WCD938X_AUX_INT_CLK_CTRL, 0x50}, 502 {WCD938X_AUX_INT_TEST_CTRL, 0x00}, 503 {WCD938X_AUX_INT_STATUS_REG, 0x00}, 504 {WCD938X_AUX_INT_MISC, 0x00}, 505 {WCD938X_LDORXTX_INT_BIAS, 0x6E}, 506 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50}, 507 {WCD938X_LDORXTX_INT_TEST0, 0x1C}, 508 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF}, 509 {WCD938X_LDORXTX_INT_TEST1, 0x1F}, 510 {WCD938X_LDORXTX_INT_STATUS, 0x00}, 511 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A}, 512 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A}, 513 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02}, 514 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60}, 515 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF}, 516 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F}, 517 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F}, 518 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F}, 519 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F}, 520 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7}, 521 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8}, 522 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6}, 523 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5}, 524 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA}, 525 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05}, 526 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5}, 527 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13}, 528 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88}, 529 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42}, 530 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF}, 531 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64}, 532 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64}, 533 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77}, 534 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00}, 535 {WCD938X_DIGITAL_CHIP_ID0, 0x00}, 536 {WCD938X_DIGITAL_CHIP_ID1, 0x00}, 537 {WCD938X_DIGITAL_CHIP_ID2, 0x0D}, 538 {WCD938X_DIGITAL_CHIP_ID3, 0x01}, 539 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00}, 540 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03}, 541 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00}, 542 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, 543 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0}, 544 {WCD938X_DIGITAL_SWR_RST_EN, 0x00}, 545 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55}, 546 {WCD938X_DIGITAL_CDC_RX_RST, 0x00}, 547 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC}, 548 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC}, 549 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC}, 550 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00}, 551 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00}, 552 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00}, 553 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E}, 554 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00}, 555 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01}, 556 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63}, 557 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04}, 558 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC}, 559 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04}, 560 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A}, 561 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03}, 562 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC}, 563 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02}, 564 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7}, 565 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8}, 566 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47}, 567 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43}, 568 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1}, 569 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17}, 570 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D}, 571 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29}, 572 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34}, 573 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59}, 574 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66}, 575 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87}, 576 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64}, 577 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00}, 578 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01}, 579 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96}, 580 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09}, 581 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB}, 582 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05}, 583 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C}, 584 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02}, 585 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17}, 586 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02}, 587 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA}, 588 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3}, 589 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69}, 590 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54}, 591 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02}, 592 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15}, 593 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4}, 594 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5}, 595 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86}, 596 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85}, 597 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA}, 598 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2}, 599 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62}, 600 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55}, 601 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9}, 602 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D}, 603 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E}, 604 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01}, 605 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00}, 606 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC}, 607 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01}, 608 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00}, 609 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00}, 610 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00}, 611 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00}, 612 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00}, 613 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68}, 614 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68}, 615 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68}, 616 {WCD938X_DIGITAL_CDC_TX_RST, 0x00}, 617 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01}, 618 {WCD938X_DIGITAL_CDC_RST, 0x00}, 619 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F}, 620 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04}, 621 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01}, 622 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01}, 623 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01}, 624 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01}, 625 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00}, 626 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B}, 627 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11}, 628 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11}, 629 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00}, 630 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00}, 631 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00}, 632 {WCD938X_DIGITAL_INTR_MODE, 0x00}, 633 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF}, 634 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF}, 635 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F}, 636 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00}, 637 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00}, 638 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00}, 639 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00}, 640 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00}, 641 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00}, 642 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00}, 643 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00}, 644 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00}, 645 {WCD938X_DIGITAL_INTR_SET_0, 0x00}, 646 {WCD938X_DIGITAL_INTR_SET_1, 0x00}, 647 {WCD938X_DIGITAL_INTR_SET_2, 0x00}, 648 {WCD938X_DIGITAL_INTR_TEST_0, 0x00}, 649 {WCD938X_DIGITAL_INTR_TEST_1, 0x00}, 650 {WCD938X_DIGITAL_INTR_TEST_2, 0x00}, 651 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00}, 652 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00}, 653 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00}, 654 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00}, 655 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00}, 656 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00}, 657 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40}, 658 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40}, 659 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00}, 660 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00}, 661 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00}, 662 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00}, 663 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00}, 664 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F}, 665 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06}, 666 {WCD938X_DIGITAL_I2C_CTL, 0x00}, 667 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00}, 668 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00}, 669 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00}, 670 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00}, 671 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00}, 672 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1}, 673 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1}, 674 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1}, 675 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1}, 676 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1}, 677 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00}, 678 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00}, 679 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00}, 680 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00}, 681 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00}, 682 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F}, 683 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80}, 684 {WCD938X_DIGITAL_GPIO_MODE, 0x00}, 685 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00}, 686 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00}, 687 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00}, 688 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00}, 689 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00}, 690 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00}, 691 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00}, 692 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00}, 693 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48}, 694 {WCD938X_DIGITAL_SSP_DBG, 0x00}, 695 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00}, 696 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00}, 697 {WCD938X_DIGITAL_SPARE_0, 0x00}, 698 {WCD938X_DIGITAL_SPARE_1, 0x00}, 699 {WCD938X_DIGITAL_SPARE_2, 0x00}, 700 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00}, 701 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF}, 702 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF}, 703 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF}, 704 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF}, 705 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF}, 706 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF}, 707 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF}, 708 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF}, 709 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF}, 710 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF}, 711 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF}, 712 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF}, 713 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF}, 714 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF}, 715 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF}, 716 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF}, 717 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF}, 718 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF}, 719 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF}, 720 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E}, 721 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00}, 722 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00}, 723 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8}, 724 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16}, 725 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00}, 726 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00}, 727 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00}, 728 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00}, 729 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00}, 730 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00}, 731 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00}, 732 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88}, 733 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88}, 734 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88}, 735 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88}, 736 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88}, 737 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55}, 738 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55}, 739 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55}, 740 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01}, 741 }; 742 743 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg) 744 { 745 switch (reg) { 746 case WCD938X_ANA_PAGE_REGISTER: 747 case WCD938X_ANA_BIAS: 748 case WCD938X_ANA_RX_SUPPLIES: 749 case WCD938X_ANA_HPH: 750 case WCD938X_ANA_EAR: 751 case WCD938X_ANA_EAR_COMPANDER_CTL: 752 case WCD938X_ANA_TX_CH1: 753 case WCD938X_ANA_TX_CH2: 754 case WCD938X_ANA_TX_CH3: 755 case WCD938X_ANA_TX_CH4: 756 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC: 757 case WCD938X_ANA_MICB3_DSP_EN_LOGIC: 758 case WCD938X_ANA_MBHC_MECH: 759 case WCD938X_ANA_MBHC_ELECT: 760 case WCD938X_ANA_MBHC_ZDET: 761 case WCD938X_ANA_MBHC_BTN0: 762 case WCD938X_ANA_MBHC_BTN1: 763 case WCD938X_ANA_MBHC_BTN2: 764 case WCD938X_ANA_MBHC_BTN3: 765 case WCD938X_ANA_MBHC_BTN4: 766 case WCD938X_ANA_MBHC_BTN5: 767 case WCD938X_ANA_MBHC_BTN6: 768 case WCD938X_ANA_MBHC_BTN7: 769 case WCD938X_ANA_MICB1: 770 case WCD938X_ANA_MICB2: 771 case WCD938X_ANA_MICB2_RAMP: 772 case WCD938X_ANA_MICB3: 773 case WCD938X_ANA_MICB4: 774 case WCD938X_BIAS_CTL: 775 case WCD938X_BIAS_VBG_FINE_ADJ: 776 case WCD938X_LDOL_VDDCX_ADJUST: 777 case WCD938X_LDOL_DISABLE_LDOL: 778 case WCD938X_MBHC_CTL_CLK: 779 case WCD938X_MBHC_CTL_ANA: 780 case WCD938X_MBHC_CTL_SPARE_1: 781 case WCD938X_MBHC_CTL_SPARE_2: 782 case WCD938X_MBHC_CTL_BCS: 783 case WCD938X_MBHC_TEST_CTL: 784 case WCD938X_LDOH_MODE: 785 case WCD938X_LDOH_BIAS: 786 case WCD938X_LDOH_STB_LOADS: 787 case WCD938X_LDOH_SLOWRAMP: 788 case WCD938X_MICB1_TEST_CTL_1: 789 case WCD938X_MICB1_TEST_CTL_2: 790 case WCD938X_MICB1_TEST_CTL_3: 791 case WCD938X_MICB2_TEST_CTL_1: 792 case WCD938X_MICB2_TEST_CTL_2: 793 case WCD938X_MICB2_TEST_CTL_3: 794 case WCD938X_MICB3_TEST_CTL_1: 795 case WCD938X_MICB3_TEST_CTL_2: 796 case WCD938X_MICB3_TEST_CTL_3: 797 case WCD938X_MICB4_TEST_CTL_1: 798 case WCD938X_MICB4_TEST_CTL_2: 799 case WCD938X_MICB4_TEST_CTL_3: 800 case WCD938X_TX_COM_ADC_VCM: 801 case WCD938X_TX_COM_BIAS_ATEST: 802 case WCD938X_TX_COM_SPARE1: 803 case WCD938X_TX_COM_SPARE2: 804 case WCD938X_TX_COM_TXFE_DIV_CTL: 805 case WCD938X_TX_COM_TXFE_DIV_START: 806 case WCD938X_TX_COM_SPARE3: 807 case WCD938X_TX_COM_SPARE4: 808 case WCD938X_TX_1_2_TEST_EN: 809 case WCD938X_TX_1_2_ADC_IB: 810 case WCD938X_TX_1_2_ATEST_REFCTL: 811 case WCD938X_TX_1_2_TEST_CTL: 812 case WCD938X_TX_1_2_TEST_BLK_EN1: 813 case WCD938X_TX_1_2_TXFE1_CLKDIV: 814 case WCD938X_TX_3_4_TEST_EN: 815 case WCD938X_TX_3_4_ADC_IB: 816 case WCD938X_TX_3_4_ATEST_REFCTL: 817 case WCD938X_TX_3_4_TEST_CTL: 818 case WCD938X_TX_3_4_TEST_BLK_EN3: 819 case WCD938X_TX_3_4_TXFE3_CLKDIV: 820 case WCD938X_TX_3_4_TEST_BLK_EN2: 821 case WCD938X_TX_3_4_TXFE2_CLKDIV: 822 case WCD938X_TX_3_4_SPARE1: 823 case WCD938X_TX_3_4_TEST_BLK_EN4: 824 case WCD938X_TX_3_4_TXFE4_CLKDIV: 825 case WCD938X_TX_3_4_SPARE2: 826 case WCD938X_CLASSH_MODE_1: 827 case WCD938X_CLASSH_MODE_2: 828 case WCD938X_CLASSH_MODE_3: 829 case WCD938X_CLASSH_CTRL_VCL_1: 830 case WCD938X_CLASSH_CTRL_VCL_2: 831 case WCD938X_CLASSH_CTRL_CCL_1: 832 case WCD938X_CLASSH_CTRL_CCL_2: 833 case WCD938X_CLASSH_CTRL_CCL_3: 834 case WCD938X_CLASSH_CTRL_CCL_4: 835 case WCD938X_CLASSH_CTRL_CCL_5: 836 case WCD938X_CLASSH_BUCK_TMUX_A_D: 837 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL: 838 case WCD938X_CLASSH_SPARE: 839 case WCD938X_FLYBACK_EN: 840 case WCD938X_FLYBACK_VNEG_CTRL_1: 841 case WCD938X_FLYBACK_VNEG_CTRL_2: 842 case WCD938X_FLYBACK_VNEG_CTRL_3: 843 case WCD938X_FLYBACK_VNEG_CTRL_4: 844 case WCD938X_FLYBACK_VNEG_CTRL_5: 845 case WCD938X_FLYBACK_VNEG_CTRL_6: 846 case WCD938X_FLYBACK_VNEG_CTRL_7: 847 case WCD938X_FLYBACK_VNEG_CTRL_8: 848 case WCD938X_FLYBACK_VNEG_CTRL_9: 849 case WCD938X_FLYBACK_VNEGDAC_CTRL_1: 850 case WCD938X_FLYBACK_VNEGDAC_CTRL_2: 851 case WCD938X_FLYBACK_VNEGDAC_CTRL_3: 852 case WCD938X_FLYBACK_CTRL_1: 853 case WCD938X_FLYBACK_TEST_CTL: 854 case WCD938X_RX_AUX_SW_CTL: 855 case WCD938X_RX_PA_AUX_IN_CONN: 856 case WCD938X_RX_TIMER_DIV: 857 case WCD938X_RX_OCP_CTL: 858 case WCD938X_RX_OCP_COUNT: 859 case WCD938X_RX_BIAS_EAR_DAC: 860 case WCD938X_RX_BIAS_EAR_AMP: 861 case WCD938X_RX_BIAS_HPH_LDO: 862 case WCD938X_RX_BIAS_HPH_PA: 863 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2: 864 case WCD938X_RX_BIAS_HPH_RDAC_LDO: 865 case WCD938X_RX_BIAS_HPH_CNP1: 866 case WCD938X_RX_BIAS_HPH_LOWPOWER: 867 case WCD938X_RX_BIAS_AUX_DAC: 868 case WCD938X_RX_BIAS_AUX_AMP: 869 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER: 870 case WCD938X_RX_BIAS_MISC: 871 case WCD938X_RX_BIAS_BUCK_RST: 872 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP: 873 case WCD938X_RX_BIAS_FLYB_ERRAMP: 874 case WCD938X_RX_BIAS_FLYB_BUFF: 875 case WCD938X_RX_BIAS_FLYB_MID_RST: 876 case WCD938X_HPH_CNP_EN: 877 case WCD938X_HPH_CNP_WG_CTL: 878 case WCD938X_HPH_CNP_WG_TIME: 879 case WCD938X_HPH_OCP_CTL: 880 case WCD938X_HPH_AUTO_CHOP: 881 case WCD938X_HPH_CHOP_CTL: 882 case WCD938X_HPH_PA_CTL1: 883 case WCD938X_HPH_PA_CTL2: 884 case WCD938X_HPH_L_EN: 885 case WCD938X_HPH_L_TEST: 886 case WCD938X_HPH_L_ATEST: 887 case WCD938X_HPH_R_EN: 888 case WCD938X_HPH_R_TEST: 889 case WCD938X_HPH_R_ATEST: 890 case WCD938X_HPH_RDAC_CLK_CTL1: 891 case WCD938X_HPH_RDAC_CLK_CTL2: 892 case WCD938X_HPH_RDAC_LDO_CTL: 893 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL: 894 case WCD938X_HPH_REFBUFF_UHQA_CTL: 895 case WCD938X_HPH_REFBUFF_LP_CTL: 896 case WCD938X_HPH_L_DAC_CTL: 897 case WCD938X_HPH_R_DAC_CTL: 898 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL: 899 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN: 900 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1: 901 case WCD938X_EAR_EAR_EN_REG: 902 case WCD938X_EAR_EAR_PA_CON: 903 case WCD938X_EAR_EAR_SP_CON: 904 case WCD938X_EAR_EAR_DAC_CON: 905 case WCD938X_EAR_EAR_CNP_FSM_CON: 906 case WCD938X_EAR_TEST_CTL: 907 case WCD938X_ANA_NEW_PAGE_REGISTER: 908 case WCD938X_HPH_NEW_ANA_HPH2: 909 case WCD938X_HPH_NEW_ANA_HPH3: 910 case WCD938X_SLEEP_CTL: 911 case WCD938X_SLEEP_WATCHDOG_CTL: 912 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL: 913 case WCD938X_MBHC_NEW_CTL_1: 914 case WCD938X_MBHC_NEW_CTL_2: 915 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL: 916 case WCD938X_MBHC_NEW_ZDET_ANA_CTL: 917 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL: 918 case WCD938X_TX_NEW_AMIC_MUX_CFG: 919 case WCD938X_AUX_AUXPA: 920 case WCD938X_LDORXTX_MODE: 921 case WCD938X_LDORXTX_CONFIG: 922 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN: 923 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL: 924 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L: 925 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL: 926 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL: 927 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R: 928 case WCD938X_HPH_NEW_INT_PA_MISC1: 929 case WCD938X_HPH_NEW_INT_PA_MISC2: 930 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC: 931 case WCD938X_HPH_NEW_INT_HPH_TIMER1: 932 case WCD938X_HPH_NEW_INT_HPH_TIMER2: 933 case WCD938X_HPH_NEW_INT_HPH_TIMER3: 934 case WCD938X_HPH_NEW_INT_HPH_TIMER4: 935 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2: 936 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3: 937 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW: 938 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW: 939 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI: 940 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP: 941 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP: 942 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL: 943 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL: 944 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT: 945 case WCD938X_MBHC_NEW_INT_SPARE_2: 946 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON: 947 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1: 948 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2: 949 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS: 950 case WCD938X_AUX_INT_EN_REG: 951 case WCD938X_AUX_INT_PA_CTRL: 952 case WCD938X_AUX_INT_SP_CTRL: 953 case WCD938X_AUX_INT_DAC_CTRL: 954 case WCD938X_AUX_INT_CLK_CTRL: 955 case WCD938X_AUX_INT_TEST_CTRL: 956 case WCD938X_AUX_INT_MISC: 957 case WCD938X_LDORXTX_INT_BIAS: 958 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST: 959 case WCD938X_LDORXTX_INT_TEST0: 960 case WCD938X_LDORXTX_INT_STARTUP_TIMER: 961 case WCD938X_LDORXTX_INT_TEST1: 962 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1: 963 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2: 964 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1: 965 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2: 966 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2: 967 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1: 968 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0: 969 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M: 970 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M: 971 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1: 972 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0: 973 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP: 974 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1: 975 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0: 976 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP: 977 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0: 978 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP: 979 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1: 980 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP: 981 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2: 982 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1: 983 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0: 984 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP: 985 case WCD938X_DIGITAL_PAGE_REGISTER: 986 case WCD938X_DIGITAL_SWR_TX_CLK_RATE: 987 case WCD938X_DIGITAL_CDC_RST_CTL: 988 case WCD938X_DIGITAL_TOP_CLK_CFG: 989 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL: 990 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL: 991 case WCD938X_DIGITAL_SWR_RST_EN: 992 case WCD938X_DIGITAL_CDC_PATH_MODE: 993 case WCD938X_DIGITAL_CDC_RX_RST: 994 case WCD938X_DIGITAL_CDC_RX0_CTL: 995 case WCD938X_DIGITAL_CDC_RX1_CTL: 996 case WCD938X_DIGITAL_CDC_RX2_CTL: 997 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1: 998 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3: 999 case WCD938X_DIGITAL_CDC_COMP_CTL_0: 1000 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL: 1001 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0: 1002 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1: 1003 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0: 1004 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1: 1005 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0: 1006 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1: 1007 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0: 1008 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1: 1009 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0: 1010 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1: 1011 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0: 1012 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0: 1013 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0: 1014 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1: 1015 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2: 1016 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3: 1017 case WCD938X_DIGITAL_CDC_HPH_DSM_R1: 1018 case WCD938X_DIGITAL_CDC_HPH_DSM_R2: 1019 case WCD938X_DIGITAL_CDC_HPH_DSM_R3: 1020 case WCD938X_DIGITAL_CDC_HPH_DSM_R4: 1021 case WCD938X_DIGITAL_CDC_HPH_DSM_R5: 1022 case WCD938X_DIGITAL_CDC_HPH_DSM_R6: 1023 case WCD938X_DIGITAL_CDC_HPH_DSM_R7: 1024 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0: 1025 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1: 1026 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0: 1027 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1: 1028 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0: 1029 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1: 1030 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0: 1031 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1: 1032 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0: 1033 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1: 1034 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0: 1035 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0: 1036 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0: 1037 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1: 1038 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2: 1039 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3: 1040 case WCD938X_DIGITAL_CDC_AUX_DSM_R1: 1041 case WCD938X_DIGITAL_CDC_AUX_DSM_R2: 1042 case WCD938X_DIGITAL_CDC_AUX_DSM_R3: 1043 case WCD938X_DIGITAL_CDC_AUX_DSM_R4: 1044 case WCD938X_DIGITAL_CDC_AUX_DSM_R5: 1045 case WCD938X_DIGITAL_CDC_AUX_DSM_R6: 1046 case WCD938X_DIGITAL_CDC_AUX_DSM_R7: 1047 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0: 1048 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1: 1049 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0: 1050 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1: 1051 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2: 1052 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0: 1053 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1: 1054 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2: 1055 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL: 1056 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL: 1057 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL: 1058 case WCD938X_DIGITAL_CDC_SWR_CLH: 1059 case WCD938X_DIGITAL_SWR_CLH_BYP: 1060 case WCD938X_DIGITAL_CDC_TX0_CTL: 1061 case WCD938X_DIGITAL_CDC_TX1_CTL: 1062 case WCD938X_DIGITAL_CDC_TX2_CTL: 1063 case WCD938X_DIGITAL_CDC_TX_RST: 1064 case WCD938X_DIGITAL_CDC_REQ_CTL: 1065 case WCD938X_DIGITAL_CDC_RST: 1066 case WCD938X_DIGITAL_CDC_AMIC_CTL: 1067 case WCD938X_DIGITAL_CDC_DMIC_CTL: 1068 case WCD938X_DIGITAL_CDC_DMIC1_CTL: 1069 case WCD938X_DIGITAL_CDC_DMIC2_CTL: 1070 case WCD938X_DIGITAL_CDC_DMIC3_CTL: 1071 case WCD938X_DIGITAL_CDC_DMIC4_CTL: 1072 case WCD938X_DIGITAL_EFUSE_PRG_CTL: 1073 case WCD938X_DIGITAL_EFUSE_CTL: 1074 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2: 1075 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4: 1076 case WCD938X_DIGITAL_PDM_WD_CTL0: 1077 case WCD938X_DIGITAL_PDM_WD_CTL1: 1078 case WCD938X_DIGITAL_PDM_WD_CTL2: 1079 case WCD938X_DIGITAL_INTR_MODE: 1080 case WCD938X_DIGITAL_INTR_MASK_0: 1081 case WCD938X_DIGITAL_INTR_MASK_1: 1082 case WCD938X_DIGITAL_INTR_MASK_2: 1083 case WCD938X_DIGITAL_INTR_CLEAR_0: 1084 case WCD938X_DIGITAL_INTR_CLEAR_1: 1085 case WCD938X_DIGITAL_INTR_CLEAR_2: 1086 case WCD938X_DIGITAL_INTR_LEVEL_0: 1087 case WCD938X_DIGITAL_INTR_LEVEL_1: 1088 case WCD938X_DIGITAL_INTR_LEVEL_2: 1089 case WCD938X_DIGITAL_INTR_SET_0: 1090 case WCD938X_DIGITAL_INTR_SET_1: 1091 case WCD938X_DIGITAL_INTR_SET_2: 1092 case WCD938X_DIGITAL_INTR_TEST_0: 1093 case WCD938X_DIGITAL_INTR_TEST_1: 1094 case WCD938X_DIGITAL_INTR_TEST_2: 1095 case WCD938X_DIGITAL_TX_MODE_DBG_EN: 1096 case WCD938X_DIGITAL_TX_MODE_DBG_0_1: 1097 case WCD938X_DIGITAL_TX_MODE_DBG_2_3: 1098 case WCD938X_DIGITAL_LB_IN_SEL_CTL: 1099 case WCD938X_DIGITAL_LOOP_BACK_MODE: 1100 case WCD938X_DIGITAL_SWR_DAC_TEST: 1101 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0: 1102 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0: 1103 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1: 1104 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1: 1105 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2: 1106 case WCD938X_DIGITAL_PAD_CTL_SWR_0: 1107 case WCD938X_DIGITAL_PAD_CTL_SWR_1: 1108 case WCD938X_DIGITAL_I2C_CTL: 1109 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE: 1110 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0: 1111 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1: 1112 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0: 1113 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1: 1114 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0: 1115 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1: 1116 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2: 1117 case WCD938X_DIGITAL_PAD_INP_DIS_0: 1118 case WCD938X_DIGITAL_PAD_INP_DIS_1: 1119 case WCD938X_DIGITAL_DRIVE_STRENGTH_0: 1120 case WCD938X_DIGITAL_DRIVE_STRENGTH_1: 1121 case WCD938X_DIGITAL_DRIVE_STRENGTH_2: 1122 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL: 1123 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL: 1124 case WCD938X_DIGITAL_GPIO_MODE: 1125 case WCD938X_DIGITAL_PIN_CTL_OE: 1126 case WCD938X_DIGITAL_PIN_CTL_DATA_0: 1127 case WCD938X_DIGITAL_PIN_CTL_DATA_1: 1128 case WCD938X_DIGITAL_DIG_DEBUG_CTL: 1129 case WCD938X_DIGITAL_DIG_DEBUG_EN: 1130 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD: 1131 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL: 1132 case WCD938X_DIGITAL_SSP_DBG: 1133 case WCD938X_DIGITAL_SPARE_0: 1134 case WCD938X_DIGITAL_SPARE_1: 1135 case WCD938X_DIGITAL_SPARE_2: 1136 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0: 1137 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1: 1138 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2: 1139 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3: 1140 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4: 1141 case WCD938X_DIGITAL_DEM_BYPASS_DATA0: 1142 case WCD938X_DIGITAL_DEM_BYPASS_DATA1: 1143 case WCD938X_DIGITAL_DEM_BYPASS_DATA2: 1144 case WCD938X_DIGITAL_DEM_BYPASS_DATA3: 1145 return true; 1146 } 1147 1148 return false; 1149 } 1150 1151 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg) 1152 { 1153 switch (reg) { 1154 case WCD938X_ANA_MBHC_RESULT_1: 1155 case WCD938X_ANA_MBHC_RESULT_2: 1156 case WCD938X_ANA_MBHC_RESULT_3: 1157 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS: 1158 case WCD938X_TX_1_2_SAR2_ERR: 1159 case WCD938X_TX_1_2_SAR1_ERR: 1160 case WCD938X_TX_3_4_SAR4_ERR: 1161 case WCD938X_TX_3_4_SAR3_ERR: 1162 case WCD938X_HPH_L_STATUS: 1163 case WCD938X_HPH_R_STATUS: 1164 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS: 1165 case WCD938X_EAR_STATUS_REG_1: 1166 case WCD938X_EAR_STATUS_REG_2: 1167 case WCD938X_MBHC_NEW_FSM_STATUS: 1168 case WCD938X_MBHC_NEW_ADC_RESULT: 1169 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT: 1170 case WCD938X_AUX_INT_STATUS_REG: 1171 case WCD938X_LDORXTX_INT_STATUS: 1172 case WCD938X_DIGITAL_CHIP_ID0: 1173 case WCD938X_DIGITAL_CHIP_ID1: 1174 case WCD938X_DIGITAL_CHIP_ID2: 1175 case WCD938X_DIGITAL_CHIP_ID3: 1176 case WCD938X_DIGITAL_INTR_STATUS_0: 1177 case WCD938X_DIGITAL_INTR_STATUS_1: 1178 case WCD938X_DIGITAL_INTR_STATUS_2: 1179 case WCD938X_DIGITAL_INTR_CLEAR_0: 1180 case WCD938X_DIGITAL_INTR_CLEAR_1: 1181 case WCD938X_DIGITAL_INTR_CLEAR_2: 1182 case WCD938X_DIGITAL_SWR_HM_TEST_0: 1183 case WCD938X_DIGITAL_SWR_HM_TEST_1: 1184 case WCD938X_DIGITAL_EFUSE_T_DATA_0: 1185 case WCD938X_DIGITAL_EFUSE_T_DATA_1: 1186 case WCD938X_DIGITAL_PIN_STATUS_0: 1187 case WCD938X_DIGITAL_PIN_STATUS_1: 1188 case WCD938X_DIGITAL_MODE_STATUS_0: 1189 case WCD938X_DIGITAL_MODE_STATUS_1: 1190 case WCD938X_DIGITAL_EFUSE_REG_0: 1191 case WCD938X_DIGITAL_EFUSE_REG_1: 1192 case WCD938X_DIGITAL_EFUSE_REG_2: 1193 case WCD938X_DIGITAL_EFUSE_REG_3: 1194 case WCD938X_DIGITAL_EFUSE_REG_4: 1195 case WCD938X_DIGITAL_EFUSE_REG_5: 1196 case WCD938X_DIGITAL_EFUSE_REG_6: 1197 case WCD938X_DIGITAL_EFUSE_REG_7: 1198 case WCD938X_DIGITAL_EFUSE_REG_8: 1199 case WCD938X_DIGITAL_EFUSE_REG_9: 1200 case WCD938X_DIGITAL_EFUSE_REG_10: 1201 case WCD938X_DIGITAL_EFUSE_REG_11: 1202 case WCD938X_DIGITAL_EFUSE_REG_12: 1203 case WCD938X_DIGITAL_EFUSE_REG_13: 1204 case WCD938X_DIGITAL_EFUSE_REG_14: 1205 case WCD938X_DIGITAL_EFUSE_REG_15: 1206 case WCD938X_DIGITAL_EFUSE_REG_16: 1207 case WCD938X_DIGITAL_EFUSE_REG_17: 1208 case WCD938X_DIGITAL_EFUSE_REG_18: 1209 case WCD938X_DIGITAL_EFUSE_REG_19: 1210 case WCD938X_DIGITAL_EFUSE_REG_20: 1211 case WCD938X_DIGITAL_EFUSE_REG_21: 1212 case WCD938X_DIGITAL_EFUSE_REG_22: 1213 case WCD938X_DIGITAL_EFUSE_REG_23: 1214 case WCD938X_DIGITAL_EFUSE_REG_24: 1215 case WCD938X_DIGITAL_EFUSE_REG_25: 1216 case WCD938X_DIGITAL_EFUSE_REG_26: 1217 case WCD938X_DIGITAL_EFUSE_REG_27: 1218 case WCD938X_DIGITAL_EFUSE_REG_28: 1219 case WCD938X_DIGITAL_EFUSE_REG_29: 1220 case WCD938X_DIGITAL_EFUSE_REG_30: 1221 case WCD938X_DIGITAL_EFUSE_REG_31: 1222 return true; 1223 } 1224 return false; 1225 } 1226 1227 static bool wcd938x_readable_register(struct device *dev, unsigned int reg) 1228 { 1229 bool ret; 1230 1231 ret = wcd938x_readonly_register(dev, reg); 1232 if (!ret) 1233 return wcd938x_rdwr_register(dev, reg); 1234 1235 return ret; 1236 } 1237 1238 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg) 1239 { 1240 return wcd938x_rdwr_register(dev, reg); 1241 } 1242 1243 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg) 1244 { 1245 if (reg <= WCD938X_BASE_ADDRESS) 1246 return false; 1247 1248 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE) 1249 return true; 1250 1251 if (wcd938x_readonly_register(dev, reg)) 1252 return true; 1253 1254 return false; 1255 } 1256 1257 static struct regmap_config wcd938x_regmap_config = { 1258 .name = "wcd938x_csr", 1259 .reg_bits = 32, 1260 .val_bits = 8, 1261 .cache_type = REGCACHE_RBTREE, 1262 .reg_defaults = wcd938x_defaults, 1263 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults), 1264 .max_register = WCD938X_MAX_REGISTER, 1265 .readable_reg = wcd938x_readable_register, 1266 .writeable_reg = wcd938x_writeable_register, 1267 .volatile_reg = wcd938x_volatile_register, 1268 .can_multi_write = true, 1269 }; 1270 1271 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 1272 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 1273 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 1274 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 1275 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 1276 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 1277 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 1278 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 1279 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 1280 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 1281 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 1282 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 1283 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 1284 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 1285 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 1286 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 1287 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 1288 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 1289 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 1290 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 1291 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 1292 }; 1293 1294 static struct regmap_irq_chip wcd938x_regmap_irq_chip = { 1295 .name = "wcd938x", 1296 .irqs = wcd938x_irqs, 1297 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 1298 .num_regs = 3, 1299 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 1300 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 1301 .type_base = WCD938X_DIGITAL_INTR_LEVEL_0, 1302 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 1303 .use_ack = 1, 1304 .runtime_pm = true, 1305 .irq_drv_data = NULL, 1306 }; 1307 1308 static int wcd938x_get_clk_rate(int mode) 1309 { 1310 int rate; 1311 1312 switch (mode) { 1313 case ADC_MODE_ULP2: 1314 rate = SWR_CLK_RATE_0P6MHZ; 1315 break; 1316 case ADC_MODE_ULP1: 1317 rate = SWR_CLK_RATE_1P2MHZ; 1318 break; 1319 case ADC_MODE_LP: 1320 rate = SWR_CLK_RATE_4P8MHZ; 1321 break; 1322 case ADC_MODE_NORMAL: 1323 case ADC_MODE_LO_HIF: 1324 case ADC_MODE_HIFI: 1325 case ADC_MODE_INVALID: 1326 default: 1327 rate = SWR_CLK_RATE_9P6MHZ; 1328 break; 1329 } 1330 1331 return rate; 1332 } 1333 1334 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 1335 { 1336 u8 mask = (bank ? 0xF0 : 0x0F); 1337 u8 val = 0; 1338 1339 switch (rate) { 1340 case SWR_CLK_RATE_0P6MHZ: 1341 val = (bank ? 0x60 : 0x06); 1342 break; 1343 case SWR_CLK_RATE_1P2MHZ: 1344 val = (bank ? 0x50 : 0x05); 1345 break; 1346 case SWR_CLK_RATE_2P4MHZ: 1347 val = (bank ? 0x30 : 0x03); 1348 break; 1349 case SWR_CLK_RATE_4P8MHZ: 1350 val = (bank ? 0x10 : 0x01); 1351 break; 1352 case SWR_CLK_RATE_9P6MHZ: 1353 default: 1354 val = 0x00; 1355 break; 1356 } 1357 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 1358 mask, val); 1359 1360 return 0; 1361 } 1362 1363 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 1364 { 1365 struct regmap *rm = wcd938x->regmap; 1366 1367 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 1368 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 1369 /* 1 msec delay as per HW requirement */ 1370 usleep_range(1000, 1010); 1371 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 1372 /* 1 msec delay as per HW requirement */ 1373 usleep_range(1000, 1010); 1374 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 1375 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 1376 0xF0, 0x80); 1377 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 1378 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 1379 /* 10 msec delay as per HW requirement */ 1380 usleep_range(10000, 10010); 1381 1382 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 1383 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 1384 0xF0, 0x00); 1385 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 1386 0x1F, 0x15); 1387 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 1388 0x1F, 0x15); 1389 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 1390 0xC0, 0x80); 1391 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 1392 0x02, 0x02); 1393 1394 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 1395 0xFF, 0x14); 1396 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 1397 0x1F, 0x08); 1398 1399 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 1400 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 1401 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 1402 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 1403 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 1404 1405 /* Set Noise Filter Resistor value */ 1406 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 1407 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 1408 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 1409 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 1410 1411 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 1412 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 1413 1414 return 0; 1415 1416 } 1417 1418 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info, 1419 struct sdw_port_config *port_config, 1420 u8 enable) 1421 { 1422 u8 ch_mask, port_num; 1423 1424 port_num = ch_info->port_num; 1425 ch_mask = ch_info->ch_mask; 1426 1427 port_config->num = port_num; 1428 1429 if (enable) 1430 port_config->ch_mask |= ch_mask; 1431 else 1432 port_config->ch_mask &= ~ch_mask; 1433 1434 return 0; 1435 } 1436 1437 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable) 1438 { 1439 u8 port_num; 1440 1441 port_num = wcd->ch_info[ch_id].port_num; 1442 1443 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 1444 &wcd->port_config[port_num], 1445 enable); 1446 } 1447 1448 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 1449 struct snd_kcontrol *kcontrol, 1450 int event) 1451 { 1452 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1453 1454 switch (event) { 1455 case SND_SOC_DAPM_PRE_PMU: 1456 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1457 WCD938X_ANA_RX_CLK_EN_MASK, 1); 1458 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1459 WCD938X_RX_BIAS_EN_MASK, 1); 1460 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 1461 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1462 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 1463 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1464 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 1465 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 1466 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1467 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 1468 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 1469 WCD938X_AUXPA_CLK_EN_MASK, 1); 1470 break; 1471 case SND_SOC_DAPM_POST_PMD: 1472 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1473 WCD938X_VNEG_EN_MASK, 0); 1474 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1475 WCD938X_VPOS_EN_MASK, 0); 1476 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1477 WCD938X_RX_BIAS_EN_MASK, 0); 1478 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1479 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 1480 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1481 WCD938X_ANA_RX_CLK_EN_MASK, 0); 1482 break; 1483 } 1484 return 0; 1485 } 1486 1487 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 1488 struct snd_kcontrol *kcontrol, 1489 int event) 1490 { 1491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1492 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1493 1494 switch (event) { 1495 case SND_SOC_DAPM_PRE_PMU: 1496 snd_soc_component_write_field(component, 1497 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1498 WCD938X_RXD0_CLK_EN_MASK, 0x01); 1499 snd_soc_component_write_field(component, 1500 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1501 WCD938X_HPHL_RX_EN_MASK, 1); 1502 snd_soc_component_write_field(component, 1503 WCD938X_HPH_RDAC_CLK_CTL1, 1504 WCD938X_CHOP_CLK_EN_MASK, 0); 1505 break; 1506 case SND_SOC_DAPM_POST_PMU: 1507 snd_soc_component_write_field(component, 1508 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 1509 WCD938X_HPH_RES_DIV_MASK, 0x02); 1510 if (wcd938x->comp1_enable) { 1511 snd_soc_component_write_field(component, 1512 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1513 WCD938X_HPHL_COMP_EN_MASK, 1); 1514 /* 5msec compander delay as per HW requirement */ 1515 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 1516 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 1517 usleep_range(5000, 5010); 1518 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1519 WCD938X_AUTOCHOP_TIMER_EN, 0); 1520 } else { 1521 snd_soc_component_write_field(component, 1522 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1523 WCD938X_HPHL_COMP_EN_MASK, 0); 1524 snd_soc_component_write_field(component, 1525 WCD938X_HPH_L_EN, 1526 WCD938X_GAIN_SRC_SEL_MASK, 1527 WCD938X_GAIN_SRC_SEL_REGISTER); 1528 1529 } 1530 break; 1531 case SND_SOC_DAPM_POST_PMD: 1532 snd_soc_component_write_field(component, 1533 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1534 WCD938X_HPH_RES_DIV_MASK, 0x1); 1535 break; 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 1542 struct snd_kcontrol *kcontrol, 1543 int event) 1544 { 1545 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1546 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1547 1548 switch (event) { 1549 case SND_SOC_DAPM_PRE_PMU: 1550 snd_soc_component_write_field(component, 1551 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1552 WCD938X_RXD1_CLK_EN_MASK, 1); 1553 snd_soc_component_write_field(component, 1554 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1555 WCD938X_HPHR_RX_EN_MASK, 1); 1556 snd_soc_component_write_field(component, 1557 WCD938X_HPH_RDAC_CLK_CTL1, 1558 WCD938X_CHOP_CLK_EN_MASK, 0); 1559 break; 1560 case SND_SOC_DAPM_POST_PMU: 1561 snd_soc_component_write_field(component, 1562 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1563 WCD938X_HPH_RES_DIV_MASK, 0x02); 1564 if (wcd938x->comp2_enable) { 1565 snd_soc_component_write_field(component, 1566 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1567 WCD938X_HPHR_COMP_EN_MASK, 1); 1568 /* 5msec compander delay as per HW requirement */ 1569 if (!wcd938x->comp1_enable || 1570 (snd_soc_component_read(component, 1571 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 1572 usleep_range(5000, 5010); 1573 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1574 WCD938X_AUTOCHOP_TIMER_EN, 0); 1575 } else { 1576 snd_soc_component_write_field(component, 1577 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1578 WCD938X_HPHR_COMP_EN_MASK, 0); 1579 snd_soc_component_write_field(component, 1580 WCD938X_HPH_R_EN, 1581 WCD938X_GAIN_SRC_SEL_MASK, 1582 WCD938X_GAIN_SRC_SEL_REGISTER); 1583 } 1584 break; 1585 case SND_SOC_DAPM_POST_PMD: 1586 snd_soc_component_write_field(component, 1587 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 1588 WCD938X_HPH_RES_DIV_MASK, 0x01); 1589 break; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 1596 struct snd_kcontrol *kcontrol, 1597 int event) 1598 { 1599 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1600 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1601 1602 switch (event) { 1603 case SND_SOC_DAPM_PRE_PMU: 1604 wcd938x->ear_rx_path = 1605 snd_soc_component_read( 1606 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1607 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1608 snd_soc_component_write_field(component, 1609 WCD938X_EAR_EAR_DAC_CON, 1610 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 1611 snd_soc_component_write_field(component, 1612 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1613 WCD938X_AUX_EN_MASK, 1); 1614 snd_soc_component_write_field(component, 1615 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1616 WCD938X_RXD2_CLK_EN_MASK, 1); 1617 snd_soc_component_write_field(component, 1618 WCD938X_ANA_EAR_COMPANDER_CTL, 1619 WCD938X_GAIN_OVRD_REG_MASK, 1); 1620 } else { 1621 snd_soc_component_write_field(component, 1622 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1623 WCD938X_HPHL_RX_EN_MASK, 1); 1624 snd_soc_component_write_field(component, 1625 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1626 WCD938X_RXD0_CLK_EN_MASK, 1); 1627 if (wcd938x->comp1_enable) 1628 snd_soc_component_write_field(component, 1629 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1630 WCD938X_HPHL_COMP_EN_MASK, 1); 1631 } 1632 /* 5 msec delay as per HW requirement */ 1633 usleep_range(5000, 5010); 1634 if (wcd938x->flyback_cur_det_disable == 0) 1635 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1636 WCD938X_EN_CUR_DET_MASK, 0); 1637 wcd938x->flyback_cur_det_disable++; 1638 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1639 WCD_CLSH_EVENT_PRE_DAC, 1640 WCD_CLSH_STATE_EAR, 1641 wcd938x->hph_mode); 1642 break; 1643 case SND_SOC_DAPM_POST_PMD: 1644 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 1645 snd_soc_component_write_field(component, 1646 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1647 WCD938X_AUX_EN_MASK, 0); 1648 snd_soc_component_write_field(component, 1649 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1650 WCD938X_RXD2_CLK_EN_MASK, 0); 1651 } else { 1652 snd_soc_component_write_field(component, 1653 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 1654 WCD938X_HPHL_RX_EN_MASK, 0); 1655 snd_soc_component_write_field(component, 1656 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1657 WCD938X_RXD0_CLK_EN_MASK, 0); 1658 if (wcd938x->comp1_enable) 1659 snd_soc_component_write_field(component, 1660 WCD938X_DIGITAL_CDC_COMP_CTL_0, 1661 WCD938X_HPHL_COMP_EN_MASK, 0); 1662 } 1663 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1664 WCD938X_GAIN_OVRD_REG_MASK, 0); 1665 snd_soc_component_write_field(component, 1666 WCD938X_EAR_EAR_DAC_CON, 1667 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 1668 break; 1669 } 1670 return 0; 1671 1672 } 1673 1674 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 1675 struct snd_kcontrol *kcontrol, 1676 int event) 1677 { 1678 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1679 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1680 1681 switch (event) { 1682 case SND_SOC_DAPM_PRE_PMU: 1683 snd_soc_component_write_field(component, 1684 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1685 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 1686 snd_soc_component_write_field(component, 1687 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1688 WCD938X_RXD2_CLK_EN_MASK, 1); 1689 snd_soc_component_write_field(component, 1690 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 1691 WCD938X_AUX_EN_MASK, 1); 1692 if (wcd938x->flyback_cur_det_disable == 0) 1693 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1694 WCD938X_EN_CUR_DET_MASK, 0); 1695 wcd938x->flyback_cur_det_disable++; 1696 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1697 WCD_CLSH_EVENT_PRE_DAC, 1698 WCD_CLSH_STATE_AUX, 1699 wcd938x->hph_mode); 1700 break; 1701 case SND_SOC_DAPM_POST_PMD: 1702 snd_soc_component_write_field(component, 1703 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1704 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 1705 break; 1706 } 1707 return 0; 1708 1709 } 1710 1711 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 1712 struct snd_kcontrol *kcontrol, int event) 1713 { 1714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1715 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1716 int hph_mode = wcd938x->hph_mode; 1717 1718 switch (event) { 1719 case SND_SOC_DAPM_PRE_PMU: 1720 if (wcd938x->ldoh) 1721 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1722 WCD938X_LDOH_EN_MASK, 1); 1723 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1724 WCD_CLSH_STATE_HPHR, hph_mode); 1725 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1726 1727 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1728 hph_mode == CLS_H_ULP) { 1729 snd_soc_component_write_field(component, 1730 WCD938X_HPH_REFBUFF_LP_CTL, 1731 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1732 } 1733 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1734 WCD938X_HPHR_REF_EN_MASK, 1); 1735 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1736 /* 100 usec delay as per HW requirement */ 1737 usleep_range(100, 110); 1738 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1739 snd_soc_component_write_field(component, 1740 WCD938X_DIGITAL_PDM_WD_CTL1, 1741 WCD938X_PDM_WD_EN_MASK, 0x3); 1742 break; 1743 case SND_SOC_DAPM_POST_PMU: 1744 /* 1745 * 7ms sleep is required if compander is enabled as per 1746 * HW requirement. If compander is disabled, then 1747 * 20ms delay is required. 1748 */ 1749 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1750 if (!wcd938x->comp2_enable) 1751 usleep_range(20000, 20100); 1752 else 1753 usleep_range(7000, 7100); 1754 1755 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1756 hph_mode == CLS_H_ULP) 1757 snd_soc_component_write_field(component, 1758 WCD938X_HPH_REFBUFF_LP_CTL, 1759 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1760 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1761 } 1762 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1763 WCD938X_AUTOCHOP_TIMER_EN, 1); 1764 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1765 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1766 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1767 WCD938X_REGULATOR_MODE_MASK, 1768 WCD938X_REGULATOR_MODE_CLASS_AB); 1769 enable_irq(wcd938x->hphr_pdm_wd_int); 1770 break; 1771 case SND_SOC_DAPM_PRE_PMD: 1772 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 1773 /* 1774 * 7ms sleep is required if compander is enabled as per 1775 * HW requirement. If compander is disabled, then 1776 * 20ms delay is required. 1777 */ 1778 if (!wcd938x->comp2_enable) 1779 usleep_range(20000, 20100); 1780 else 1781 usleep_range(7000, 7100); 1782 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1783 WCD938X_HPHR_EN_MASK, 0); 1784 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1785 WCD_EVENT_PRE_HPHR_PA_OFF); 1786 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1787 break; 1788 case SND_SOC_DAPM_POST_PMD: 1789 /* 1790 * 7ms sleep is required if compander is enabled as per 1791 * HW requirement. If compander is disabled, then 1792 * 20ms delay is required. 1793 */ 1794 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1795 if (!wcd938x->comp2_enable) 1796 usleep_range(20000, 20100); 1797 else 1798 usleep_range(7000, 7100); 1799 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1800 } 1801 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1802 WCD_EVENT_POST_HPHR_PA_OFF); 1803 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1804 WCD938X_HPHR_REF_EN_MASK, 0); 1805 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 1806 WCD938X_PDM_WD_EN_MASK, 0); 1807 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1808 WCD_CLSH_STATE_HPHR, hph_mode); 1809 if (wcd938x->ldoh) 1810 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1811 WCD938X_LDOH_EN_MASK, 0); 1812 break; 1813 } 1814 1815 return 0; 1816 } 1817 1818 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 1819 struct snd_kcontrol *kcontrol, int event) 1820 { 1821 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1822 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1823 int hph_mode = wcd938x->hph_mode; 1824 1825 switch (event) { 1826 case SND_SOC_DAPM_PRE_PMU: 1827 if (wcd938x->ldoh) 1828 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1829 WCD938X_LDOH_EN_MASK, 1); 1830 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 1831 WCD_CLSH_STATE_HPHL, hph_mode); 1832 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 1833 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1834 hph_mode == CLS_H_ULP) { 1835 snd_soc_component_write_field(component, 1836 WCD938X_HPH_REFBUFF_LP_CTL, 1837 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 1838 } 1839 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1840 WCD938X_HPHL_REF_EN_MASK, 1); 1841 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 1842 /* 100 usec delay as per HW requirement */ 1843 usleep_range(100, 110); 1844 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1845 snd_soc_component_write_field(component, 1846 WCD938X_DIGITAL_PDM_WD_CTL0, 1847 WCD938X_PDM_WD_EN_MASK, 0x3); 1848 break; 1849 case SND_SOC_DAPM_POST_PMU: 1850 /* 1851 * 7ms sleep is required if compander is enabled as per 1852 * HW requirement. If compander is disabled, then 1853 * 20ms delay is required. 1854 */ 1855 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1856 if (!wcd938x->comp1_enable) 1857 usleep_range(20000, 20100); 1858 else 1859 usleep_range(7000, 7100); 1860 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 1861 hph_mode == CLS_H_ULP) 1862 snd_soc_component_write_field(component, 1863 WCD938X_HPH_REFBUFF_LP_CTL, 1864 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 1865 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1866 } 1867 1868 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 1869 WCD938X_AUTOCHOP_TIMER_EN, 1); 1870 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1871 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1872 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1873 WCD938X_REGULATOR_MODE_MASK, 1874 WCD938X_REGULATOR_MODE_CLASS_AB); 1875 enable_irq(wcd938x->hphl_pdm_wd_int); 1876 break; 1877 case SND_SOC_DAPM_PRE_PMD: 1878 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 1879 /* 1880 * 7ms sleep is required if compander is enabled as per 1881 * HW requirement. If compander is disabled, then 1882 * 20ms delay is required. 1883 */ 1884 if (!wcd938x->comp1_enable) 1885 usleep_range(20000, 20100); 1886 else 1887 usleep_range(7000, 7100); 1888 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1889 WCD938X_HPHL_EN_MASK, 0); 1890 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 1891 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1892 break; 1893 case SND_SOC_DAPM_POST_PMD: 1894 /* 1895 * 7ms sleep is required if compander is enabled as per 1896 * HW requirement. If compander is disabled, then 1897 * 20ms delay is required. 1898 */ 1899 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 1900 if (!wcd938x->comp1_enable) 1901 usleep_range(21000, 21100); 1902 else 1903 usleep_range(7000, 7100); 1904 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 1905 } 1906 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1907 WCD_EVENT_POST_HPHL_PA_OFF); 1908 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 1909 WCD938X_HPHL_REF_EN_MASK, 0); 1910 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1911 WCD938X_PDM_WD_EN_MASK, 0); 1912 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1913 WCD_CLSH_STATE_HPHL, hph_mode); 1914 if (wcd938x->ldoh) 1915 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 1916 WCD938X_LDOH_EN_MASK, 0); 1917 break; 1918 } 1919 1920 return 0; 1921 } 1922 1923 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 1924 struct snd_kcontrol *kcontrol, int event) 1925 { 1926 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1927 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1928 int hph_mode = wcd938x->hph_mode; 1929 1930 switch (event) { 1931 case SND_SOC_DAPM_PRE_PMU: 1932 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1933 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1934 break; 1935 case SND_SOC_DAPM_POST_PMU: 1936 /* 1 msec delay as per HW requirement */ 1937 usleep_range(1000, 1010); 1938 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1939 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 1940 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 1941 WCD938X_REGULATOR_MODE_MASK, 1942 WCD938X_REGULATOR_MODE_CLASS_AB); 1943 enable_irq(wcd938x->aux_pdm_wd_int); 1944 break; 1945 case SND_SOC_DAPM_PRE_PMD: 1946 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 1947 break; 1948 case SND_SOC_DAPM_POST_PMD: 1949 /* 1 msec delay as per HW requirement */ 1950 usleep_range(1000, 1010); 1951 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1952 WCD938X_AUX_PDM_WD_EN_MASK, 0); 1953 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 1954 WCD_CLSH_EVENT_POST_PA, 1955 WCD_CLSH_STATE_AUX, 1956 hph_mode); 1957 1958 wcd938x->flyback_cur_det_disable--; 1959 if (wcd938x->flyback_cur_det_disable == 0) 1960 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1961 WCD938X_EN_CUR_DET_MASK, 1); 1962 break; 1963 } 1964 return 0; 1965 } 1966 1967 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 1968 struct snd_kcontrol *kcontrol, int event) 1969 { 1970 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1971 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1972 int hph_mode = wcd938x->hph_mode; 1973 1974 switch (event) { 1975 case SND_SOC_DAPM_PRE_PMU: 1976 /* 1977 * Enable watchdog interrupt for HPHL or AUX 1978 * depending on mux value 1979 */ 1980 wcd938x->ear_rx_path = snd_soc_component_read(component, 1981 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 1982 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 1983 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 1984 WCD938X_AUX_PDM_WD_EN_MASK, 1); 1985 else 1986 snd_soc_component_write_field(component, 1987 WCD938X_DIGITAL_PDM_WD_CTL0, 1988 WCD938X_PDM_WD_EN_MASK, 0x3); 1989 if (!wcd938x->comp1_enable) 1990 snd_soc_component_write_field(component, 1991 WCD938X_ANA_EAR_COMPANDER_CTL, 1992 WCD938X_GAIN_OVRD_REG_MASK, 1); 1993 1994 break; 1995 case SND_SOC_DAPM_POST_PMU: 1996 /* 6 msec delay as per HW requirement */ 1997 usleep_range(6000, 6010); 1998 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 1999 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 2000 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 2001 WCD938X_REGULATOR_MODE_MASK, 2002 WCD938X_REGULATOR_MODE_CLASS_AB); 2003 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2004 enable_irq(wcd938x->aux_pdm_wd_int); 2005 else 2006 enable_irq(wcd938x->hphl_pdm_wd_int); 2007 break; 2008 case SND_SOC_DAPM_PRE_PMD: 2009 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2010 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 2011 else 2012 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 2013 break; 2014 case SND_SOC_DAPM_POST_PMD: 2015 if (!wcd938x->comp1_enable) 2016 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2017 WCD938X_GAIN_OVRD_REG_MASK, 0); 2018 /* 7 msec delay as per HW requirement */ 2019 usleep_range(7000, 7010); 2020 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 2021 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 2022 WCD938X_AUX_PDM_WD_EN_MASK, 0); 2023 else 2024 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 2025 WCD938X_PDM_WD_EN_MASK, 0); 2026 2027 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 2028 WCD_CLSH_STATE_EAR, hph_mode); 2029 2030 wcd938x->flyback_cur_det_disable--; 2031 if (wcd938x->flyback_cur_det_disable == 0) 2032 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 2033 WCD938X_EN_CUR_DET_MASK, 1); 2034 break; 2035 } 2036 2037 return 0; 2038 } 2039 2040 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2041 struct snd_kcontrol *kcontrol, 2042 int event) 2043 { 2044 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2045 u16 dmic_clk_reg, dmic_clk_en_reg; 2046 u8 dmic_sel_mask, dmic_clk_mask; 2047 2048 switch (w->shift) { 2049 case 0: 2050 case 1: 2051 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2052 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 2053 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 2054 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 2055 break; 2056 case 2: 2057 case 3: 2058 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 2059 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 2060 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 2061 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 2062 break; 2063 case 4: 2064 case 5: 2065 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2066 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 2067 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 2068 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 2069 break; 2070 case 6: 2071 case 7: 2072 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 2073 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 2074 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 2075 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 2076 break; 2077 default: 2078 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 2079 __func__); 2080 return -EINVAL; 2081 } 2082 2083 switch (event) { 2084 case SND_SOC_DAPM_PRE_PMU: 2085 snd_soc_component_write_field(component, 2086 WCD938X_DIGITAL_CDC_AMIC_CTL, 2087 dmic_sel_mask, 2088 WCD938X_AMIC1_IN_SEL_DMIC); 2089 /* 250us sleep as per HW requirement */ 2090 usleep_range(250, 260); 2091 /* Setting DMIC clock rate to 2.4MHz */ 2092 snd_soc_component_write_field(component, dmic_clk_reg, 2093 dmic_clk_mask, 2094 WCD938X_DMIC4_RATE_2P4MHZ); 2095 snd_soc_component_write_field(component, dmic_clk_en_reg, 2096 WCD938X_DMIC_CLK_EN_MASK, 1); 2097 /* enable clock scaling */ 2098 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 2099 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 2100 break; 2101 case SND_SOC_DAPM_POST_PMD: 2102 snd_soc_component_write_field(component, 2103 WCD938X_DIGITAL_CDC_AMIC_CTL, 2104 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 2105 snd_soc_component_write_field(component, dmic_clk_en_reg, 2106 WCD938X_DMIC_CLK_EN_MASK, 0); 2107 break; 2108 } 2109 return 0; 2110 } 2111 2112 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 2113 struct snd_kcontrol *kcontrol, int event) 2114 { 2115 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2116 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2117 int bank; 2118 int rate; 2119 2120 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 2121 bank = bank ? 0 : 1; 2122 2123 switch (event) { 2124 case SND_SOC_DAPM_PRE_PMU: 2125 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2126 int i = 0, mode = 0; 2127 2128 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 2129 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 2130 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 2131 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 2132 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 2133 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 2134 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 2135 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 2136 2137 if (mode != 0) { 2138 for (i = 0; i < ADC_MODE_ULP2; i++) { 2139 if (mode & (1 << i)) { 2140 i++; 2141 break; 2142 } 2143 } 2144 } 2145 rate = wcd938x_get_clk_rate(i); 2146 wcd938x_set_swr_clk_rate(component, rate, bank); 2147 /* Copy clk settings to active bank */ 2148 wcd938x_set_swr_clk_rate(component, rate, !bank); 2149 } 2150 break; 2151 case SND_SOC_DAPM_POST_PMD: 2152 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 2153 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 2154 wcd938x_set_swr_clk_rate(component, rate, !bank); 2155 wcd938x_set_swr_clk_rate(component, rate, bank); 2156 } 2157 break; 2158 } 2159 2160 return 0; 2161 } 2162 2163 static int wcd938x_get_adc_mode(int val) 2164 { 2165 int ret = 0; 2166 2167 switch (val) { 2168 case ADC_MODE_INVALID: 2169 ret = ADC_MODE_VAL_NORMAL; 2170 break; 2171 case ADC_MODE_HIFI: 2172 ret = ADC_MODE_VAL_HIFI; 2173 break; 2174 case ADC_MODE_LO_HIF: 2175 ret = ADC_MODE_VAL_LO_HIF; 2176 break; 2177 case ADC_MODE_NORMAL: 2178 ret = ADC_MODE_VAL_NORMAL; 2179 break; 2180 case ADC_MODE_LP: 2181 ret = ADC_MODE_VAL_LP; 2182 break; 2183 case ADC_MODE_ULP1: 2184 ret = ADC_MODE_VAL_ULP1; 2185 break; 2186 case ADC_MODE_ULP2: 2187 ret = ADC_MODE_VAL_ULP2; 2188 break; 2189 default: 2190 ret = -EINVAL; 2191 break; 2192 } 2193 return ret; 2194 } 2195 2196 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 2197 struct snd_kcontrol *kcontrol, int event) 2198 { 2199 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2200 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2201 2202 switch (event) { 2203 case SND_SOC_DAPM_PRE_PMU: 2204 snd_soc_component_write_field(component, 2205 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2206 WCD938X_ANA_TX_CLK_EN_MASK, 1); 2207 snd_soc_component_write_field(component, 2208 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2209 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2210 set_bit(w->shift, &wcd938x->status_mask); 2211 break; 2212 case SND_SOC_DAPM_POST_PMD: 2213 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2214 WCD938X_ANA_TX_CLK_EN_MASK, 0); 2215 clear_bit(w->shift, &wcd938x->status_mask); 2216 break; 2217 } 2218 2219 return 0; 2220 } 2221 2222 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 2223 int channel, int mode) 2224 { 2225 int reg, mask; 2226 2227 switch (channel) { 2228 case 0: 2229 reg = WCD938X_ANA_TX_CH2; 2230 mask = WCD938X_HPF1_INIT_MASK; 2231 break; 2232 case 1: 2233 reg = WCD938X_ANA_TX_CH2; 2234 mask = WCD938X_HPF2_INIT_MASK; 2235 break; 2236 case 2: 2237 reg = WCD938X_ANA_TX_CH4; 2238 mask = WCD938X_HPF3_INIT_MASK; 2239 break; 2240 case 3: 2241 reg = WCD938X_ANA_TX_CH4; 2242 mask = WCD938X_HPF4_INIT_MASK; 2243 break; 2244 default: 2245 return; 2246 } 2247 2248 snd_soc_component_write_field(component, reg, mask, mode); 2249 } 2250 2251 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 2252 struct snd_kcontrol *kcontrol, int event) 2253 { 2254 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2255 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2256 int mode; 2257 2258 switch (event) { 2259 case SND_SOC_DAPM_PRE_PMU: 2260 snd_soc_component_write_field(component, 2261 WCD938X_DIGITAL_CDC_REQ_CTL, 2262 WCD938X_FS_RATE_4P8_MASK, 1); 2263 snd_soc_component_write_field(component, 2264 WCD938X_DIGITAL_CDC_REQ_CTL, 2265 WCD938X_NO_NOTCH_MASK, 0); 2266 wcd938x_tx_channel_config(component, w->shift, 1); 2267 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 2268 if (mode < 0) { 2269 dev_info(component->dev, "Invalid ADC mode\n"); 2270 return -EINVAL; 2271 } 2272 switch (w->shift) { 2273 case 0: 2274 snd_soc_component_write_field(component, 2275 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2276 WCD938X_TXD0_MODE_MASK, mode); 2277 snd_soc_component_write_field(component, 2278 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2279 WCD938X_TXD0_CLK_EN_MASK, 1); 2280 break; 2281 case 1: 2282 snd_soc_component_write_field(component, 2283 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2284 WCD938X_TXD1_MODE_MASK, mode); 2285 snd_soc_component_write_field(component, 2286 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2287 WCD938X_TXD1_CLK_EN_MASK, 1); 2288 break; 2289 case 2: 2290 snd_soc_component_write_field(component, 2291 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2292 WCD938X_TXD2_MODE_MASK, mode); 2293 snd_soc_component_write_field(component, 2294 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2295 WCD938X_TXD2_CLK_EN_MASK, 1); 2296 break; 2297 case 3: 2298 snd_soc_component_write_field(component, 2299 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2300 WCD938X_TXD3_MODE_MASK, mode); 2301 snd_soc_component_write_field(component, 2302 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2303 WCD938X_TXD3_CLK_EN_MASK, 1); 2304 break; 2305 default: 2306 break; 2307 } 2308 2309 wcd938x_tx_channel_config(component, w->shift, 0); 2310 break; 2311 case SND_SOC_DAPM_POST_PMD: 2312 switch (w->shift) { 2313 case 0: 2314 snd_soc_component_write_field(component, 2315 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2316 WCD938X_TXD0_MODE_MASK, 0); 2317 snd_soc_component_write_field(component, 2318 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2319 WCD938X_TXD0_CLK_EN_MASK, 0); 2320 break; 2321 case 1: 2322 snd_soc_component_write_field(component, 2323 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 2324 WCD938X_TXD1_MODE_MASK, 0); 2325 snd_soc_component_write_field(component, 2326 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2327 WCD938X_TXD1_CLK_EN_MASK, 0); 2328 break; 2329 case 2: 2330 snd_soc_component_write_field(component, 2331 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2332 WCD938X_TXD2_MODE_MASK, 0); 2333 snd_soc_component_write_field(component, 2334 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2335 WCD938X_TXD2_CLK_EN_MASK, 0); 2336 break; 2337 case 3: 2338 snd_soc_component_write_field(component, 2339 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 2340 WCD938X_TXD3_MODE_MASK, 0); 2341 snd_soc_component_write_field(component, 2342 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2343 WCD938X_TXD3_CLK_EN_MASK, 0); 2344 break; 2345 default: 2346 break; 2347 } 2348 snd_soc_component_write_field(component, 2349 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2350 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 2351 break; 2352 } 2353 2354 return 0; 2355 } 2356 2357 static int wcd938x_micbias_control(struct snd_soc_component *component, 2358 int micb_num, int req, bool is_dapm) 2359 { 2360 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2361 int micb_index = micb_num - 1; 2362 u16 micb_reg; 2363 2364 switch (micb_num) { 2365 case MIC_BIAS_1: 2366 micb_reg = WCD938X_ANA_MICB1; 2367 break; 2368 case MIC_BIAS_2: 2369 micb_reg = WCD938X_ANA_MICB2; 2370 break; 2371 case MIC_BIAS_3: 2372 micb_reg = WCD938X_ANA_MICB3; 2373 break; 2374 case MIC_BIAS_4: 2375 micb_reg = WCD938X_ANA_MICB4; 2376 break; 2377 default: 2378 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2379 __func__, micb_num); 2380 return -EINVAL; 2381 } 2382 2383 switch (req) { 2384 case MICB_PULLUP_ENABLE: 2385 wcd938x->pullup_ref[micb_index]++; 2386 if ((wcd938x->pullup_ref[micb_index] == 1) && 2387 (wcd938x->micb_ref[micb_index] == 0)) 2388 snd_soc_component_write_field(component, micb_reg, 2389 WCD938X_MICB_EN_MASK, 2390 WCD938X_MICB_PULL_UP); 2391 break; 2392 case MICB_PULLUP_DISABLE: 2393 if (wcd938x->pullup_ref[micb_index] > 0) 2394 wcd938x->pullup_ref[micb_index]--; 2395 2396 if ((wcd938x->pullup_ref[micb_index] == 0) && 2397 (wcd938x->micb_ref[micb_index] == 0)) 2398 snd_soc_component_write_field(component, micb_reg, 2399 WCD938X_MICB_EN_MASK, 0); 2400 break; 2401 case MICB_ENABLE: 2402 wcd938x->micb_ref[micb_index]++; 2403 if (wcd938x->micb_ref[micb_index] == 1) { 2404 snd_soc_component_write_field(component, 2405 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 2406 WCD938X_TX_CLK_EN_MASK, 0xF); 2407 snd_soc_component_write_field(component, 2408 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 2409 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 2410 snd_soc_component_write_field(component, 2411 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 2412 WCD938X_TX_SC_CLK_EN_MASK, 1); 2413 2414 snd_soc_component_write_field(component, micb_reg, 2415 WCD938X_MICB_EN_MASK, 2416 WCD938X_MICB_ENABLE); 2417 if (micb_num == MIC_BIAS_2) 2418 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2419 WCD_EVENT_POST_MICBIAS_2_ON); 2420 } 2421 if (micb_num == MIC_BIAS_2 && is_dapm) 2422 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2423 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2424 2425 2426 break; 2427 case MICB_DISABLE: 2428 if (wcd938x->micb_ref[micb_index] > 0) 2429 wcd938x->micb_ref[micb_index]--; 2430 2431 if ((wcd938x->micb_ref[micb_index] == 0) && 2432 (wcd938x->pullup_ref[micb_index] > 0)) 2433 snd_soc_component_write_field(component, micb_reg, 2434 WCD938X_MICB_EN_MASK, 2435 WCD938X_MICB_PULL_UP); 2436 else if ((wcd938x->micb_ref[micb_index] == 0) && 2437 (wcd938x->pullup_ref[micb_index] == 0)) { 2438 if (micb_num == MIC_BIAS_2) 2439 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2440 WCD_EVENT_PRE_MICBIAS_2_OFF); 2441 2442 snd_soc_component_write_field(component, micb_reg, 2443 WCD938X_MICB_EN_MASK, 0); 2444 if (micb_num == MIC_BIAS_2) 2445 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2446 WCD_EVENT_POST_MICBIAS_2_OFF); 2447 } 2448 if (is_dapm && micb_num == MIC_BIAS_2) 2449 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 2450 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2451 break; 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2458 struct snd_kcontrol *kcontrol, 2459 int event) 2460 { 2461 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2462 int micb_num = w->shift; 2463 2464 switch (event) { 2465 case SND_SOC_DAPM_PRE_PMU: 2466 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 2467 break; 2468 case SND_SOC_DAPM_POST_PMU: 2469 /* 1 msec delay as per HW requirement */ 2470 usleep_range(1000, 1100); 2471 break; 2472 case SND_SOC_DAPM_POST_PMD: 2473 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 2474 break; 2475 } 2476 2477 return 0; 2478 } 2479 2480 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 2481 struct snd_kcontrol *kcontrol, 2482 int event) 2483 { 2484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2485 int micb_num = w->shift; 2486 2487 switch (event) { 2488 case SND_SOC_DAPM_PRE_PMU: 2489 wcd938x_micbias_control(component, micb_num, 2490 MICB_PULLUP_ENABLE, true); 2491 break; 2492 case SND_SOC_DAPM_POST_PMU: 2493 /* 1 msec delay as per HW requirement */ 2494 usleep_range(1000, 1100); 2495 break; 2496 case SND_SOC_DAPM_POST_PMD: 2497 wcd938x_micbias_control(component, micb_num, 2498 MICB_PULLUP_DISABLE, true); 2499 break; 2500 } 2501 2502 return 0; 2503 } 2504 2505 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 2506 struct snd_ctl_elem_value *ucontrol) 2507 { 2508 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2509 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2510 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2511 int path = e->shift_l; 2512 2513 ucontrol->value.integer.value[0] = wcd938x->tx_mode[path]; 2514 2515 return 0; 2516 } 2517 2518 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 2519 struct snd_ctl_elem_value *ucontrol) 2520 { 2521 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2522 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2523 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2524 int path = e->shift_l; 2525 2526 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 2527 2528 return 1; 2529 } 2530 2531 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 2532 struct snd_ctl_elem_value *ucontrol) 2533 { 2534 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2535 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2536 2537 ucontrol->value.integer.value[0] = wcd938x->hph_mode; 2538 2539 return 0; 2540 } 2541 2542 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 2543 struct snd_ctl_elem_value *ucontrol) 2544 { 2545 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2546 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2547 2548 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 2549 2550 return 1; 2551 } 2552 2553 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 2554 struct snd_ctl_elem_value *ucontrol) 2555 { 2556 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2557 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2558 2559 if (wcd938x->comp1_enable) { 2560 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 2561 return -EINVAL; 2562 } 2563 2564 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 2565 WCD938X_EAR_GAIN_MASK, 2566 ucontrol->value.integer.value[0]); 2567 2568 return 0; 2569 } 2570 2571 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 2572 struct snd_ctl_elem_value *ucontrol) 2573 { 2574 2575 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2576 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2577 struct soc_mixer_control *mc; 2578 bool hphr; 2579 2580 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2581 hphr = mc->shift; 2582 2583 if (hphr) 2584 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 2585 else 2586 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 2587 2588 return 0; 2589 } 2590 2591 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 2592 struct snd_ctl_elem_value *ucontrol) 2593 { 2594 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2595 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2596 struct wcd938x_sdw_priv *wcd; 2597 int value = ucontrol->value.integer.value[0]; 2598 struct soc_mixer_control *mc; 2599 bool hphr; 2600 2601 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2602 hphr = mc->shift; 2603 2604 wcd = wcd938x->sdw_priv[AIF1_PB]; 2605 2606 if (hphr) 2607 wcd938x->comp2_enable = value; 2608 else 2609 wcd938x->comp1_enable = value; 2610 2611 if (value) 2612 wcd938x_connect_port(wcd, mc->reg, true); 2613 else 2614 wcd938x_connect_port(wcd, mc->reg, false); 2615 2616 return 0; 2617 } 2618 2619 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 2620 struct snd_ctl_elem_value *ucontrol) 2621 { 2622 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2623 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2624 2625 ucontrol->value.integer.value[0] = wcd938x->ldoh; 2626 2627 return 0; 2628 } 2629 2630 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 2631 struct snd_ctl_elem_value *ucontrol) 2632 { 2633 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2634 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2635 2636 wcd938x->ldoh = ucontrol->value.integer.value[0]; 2637 2638 return 1; 2639 } 2640 2641 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol, 2642 struct snd_ctl_elem_value *ucontrol) 2643 { 2644 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2645 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2646 2647 ucontrol->value.integer.value[0] = wcd938x->bcs_dis; 2648 2649 return 0; 2650 } 2651 2652 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol, 2653 struct snd_ctl_elem_value *ucontrol) 2654 { 2655 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2656 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2657 2658 wcd938x->bcs_dis = ucontrol->value.integer.value[0]; 2659 2660 return 1; 2661 } 2662 2663 static const char * const tx_mode_mux_text_wcd9380[] = { 2664 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2665 }; 2666 2667 static const char * const tx_mode_mux_text[] = { 2668 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 2669 "ADC_ULP1", "ADC_ULP2", 2670 }; 2671 2672 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 2673 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 2674 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 2675 "CLS_AB_LOHIFI", 2676 }; 2677 2678 static const char * const rx_hph_mode_mux_text[] = { 2679 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 2680 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 2681 }; 2682 2683 static const char * const adc2_mux_text[] = { 2684 "INP2", "INP3" 2685 }; 2686 2687 static const char * const adc3_mux_text[] = { 2688 "INP4", "INP6" 2689 }; 2690 2691 static const char * const adc4_mux_text[] = { 2692 "INP5", "INP7" 2693 }; 2694 2695 static const char * const rdac3_mux_text[] = { 2696 "RX1", "RX3" 2697 }; 2698 2699 static const char * const hdr12_mux_text[] = { 2700 "NO_HDR12", "HDR12" 2701 }; 2702 2703 static const char * const hdr34_mux_text[] = { 2704 "NO_HDR34", "HDR34" 2705 }; 2706 2707 static const struct soc_enum tx0_mode_enum_wcd9380 = 2708 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2709 tx_mode_mux_text_wcd9380); 2710 2711 static const struct soc_enum tx1_mode_enum_wcd9380 = 2712 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2713 tx_mode_mux_text_wcd9380); 2714 2715 static const struct soc_enum tx2_mode_enum_wcd9380 = 2716 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2717 tx_mode_mux_text_wcd9380); 2718 2719 static const struct soc_enum tx3_mode_enum_wcd9380 = 2720 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 2721 tx_mode_mux_text_wcd9380); 2722 2723 static const struct soc_enum tx0_mode_enum_wcd9385 = 2724 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 2725 tx_mode_mux_text); 2726 2727 static const struct soc_enum tx1_mode_enum_wcd9385 = 2728 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 2729 tx_mode_mux_text); 2730 2731 static const struct soc_enum tx2_mode_enum_wcd9385 = 2732 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 2733 tx_mode_mux_text); 2734 2735 static const struct soc_enum tx3_mode_enum_wcd9385 = 2736 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 2737 tx_mode_mux_text); 2738 2739 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 2740 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 2741 rx_hph_mode_mux_text_wcd9380); 2742 2743 static const struct soc_enum rx_hph_mode_mux_enum = 2744 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 2745 rx_hph_mode_mux_text); 2746 2747 static const struct soc_enum adc2_enum = 2748 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 2749 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 2750 2751 static const struct soc_enum adc3_enum = 2752 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 2753 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 2754 2755 static const struct soc_enum adc4_enum = 2756 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 2757 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 2758 2759 static const struct soc_enum hdr12_enum = 2760 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 2761 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 2762 2763 static const struct soc_enum hdr34_enum = 2764 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 2765 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 2766 2767 static const struct soc_enum rdac3_enum = 2768 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 2769 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 2770 2771 static const struct snd_kcontrol_new adc1_switch[] = { 2772 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2773 }; 2774 2775 static const struct snd_kcontrol_new adc2_switch[] = { 2776 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2777 }; 2778 2779 static const struct snd_kcontrol_new adc3_switch[] = { 2780 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2781 }; 2782 2783 static const struct snd_kcontrol_new adc4_switch[] = { 2784 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2785 }; 2786 2787 static const struct snd_kcontrol_new dmic1_switch[] = { 2788 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2789 }; 2790 2791 static const struct snd_kcontrol_new dmic2_switch[] = { 2792 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2793 }; 2794 2795 static const struct snd_kcontrol_new dmic3_switch[] = { 2796 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2797 }; 2798 2799 static const struct snd_kcontrol_new dmic4_switch[] = { 2800 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2801 }; 2802 2803 static const struct snd_kcontrol_new dmic5_switch[] = { 2804 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2805 }; 2806 2807 static const struct snd_kcontrol_new dmic6_switch[] = { 2808 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2809 }; 2810 2811 static const struct snd_kcontrol_new dmic7_switch[] = { 2812 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2813 }; 2814 2815 static const struct snd_kcontrol_new dmic8_switch[] = { 2816 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2817 }; 2818 2819 static const struct snd_kcontrol_new ear_rdac_switch[] = { 2820 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2821 }; 2822 2823 static const struct snd_kcontrol_new aux_rdac_switch[] = { 2824 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2825 }; 2826 2827 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 2828 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2829 }; 2830 2831 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 2832 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 2833 }; 2834 2835 static const struct snd_kcontrol_new tx_adc2_mux = 2836 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 2837 2838 static const struct snd_kcontrol_new tx_adc3_mux = 2839 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 2840 2841 static const struct snd_kcontrol_new tx_adc4_mux = 2842 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 2843 2844 static const struct snd_kcontrol_new tx_hdr12_mux = 2845 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 2846 2847 static const struct snd_kcontrol_new tx_hdr34_mux = 2848 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 2849 2850 static const struct snd_kcontrol_new rx_rdac3_mux = 2851 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 2852 2853 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 2854 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 2855 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2856 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 2857 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2858 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 2859 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2860 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 2861 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2862 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 2863 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2864 }; 2865 2866 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 2867 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2868 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 2869 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 2870 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2871 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 2872 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2873 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 2874 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2875 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 2876 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 2877 }; 2878 2879 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 2880 struct snd_ctl_elem_value *ucontrol) 2881 { 2882 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2883 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2884 struct wcd938x_sdw_priv *wcd; 2885 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 2886 int dai_id = mixer->shift; 2887 int portidx = mixer->reg; 2888 2889 wcd = wcd938x->sdw_priv[dai_id]; 2890 2891 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 2892 2893 return 0; 2894 } 2895 2896 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 2897 struct snd_ctl_elem_value *ucontrol) 2898 { 2899 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 2900 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 2901 struct wcd938x_sdw_priv *wcd; 2902 struct soc_mixer_control *mixer = 2903 (struct soc_mixer_control *)kcontrol->private_value; 2904 int portidx = mixer->reg; 2905 int dai_id = mixer->shift; 2906 bool enable; 2907 2908 wcd = wcd938x->sdw_priv[dai_id]; 2909 2910 if (ucontrol->value.integer.value[0]) 2911 enable = true; 2912 else 2913 enable = false; 2914 2915 wcd->port_enable[portidx] = enable; 2916 2917 wcd938x_connect_port(wcd, portidx, enable); 2918 2919 return 0; 2920 2921 } 2922 2923 /* MBHC related */ 2924 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 2925 bool enable) 2926 { 2927 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 2928 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 2929 } 2930 2931 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2932 bool enable) 2933 { 2934 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 2935 WCD938X_ANA_MBHC_BIAS_EN, enable); 2936 } 2937 2938 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 2939 int *btn_low, int *btn_high, 2940 int num_btn, bool is_micbias) 2941 { 2942 int i, vth; 2943 2944 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2945 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2946 __func__, num_btn); 2947 return; 2948 } 2949 2950 for (i = 0; i < num_btn; i++) { 2951 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2952 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 2953 WCD938X_MBHC_BTN_VTH_MASK, vth); 2954 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 2955 __func__, i, btn_high[i], vth); 2956 } 2957 } 2958 2959 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2960 { 2961 u8 val; 2962 2963 if (micb_num == MIC_BIAS_2) { 2964 val = snd_soc_component_read_field(component, 2965 WCD938X_ANA_MICB2, 2966 WCD938X_ANA_MICB2_ENABLE_MASK); 2967 if (val == WCD938X_MICB_ENABLE) 2968 return true; 2969 } 2970 return false; 2971 } 2972 2973 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2974 int pull_up_cur) 2975 { 2976 /* Default pull up current to 2uA */ 2977 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 2978 pull_up_cur = HS_PULLUP_I_2P0_UA; 2979 2980 snd_soc_component_write_field(component, 2981 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 2982 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 2983 } 2984 2985 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 2986 int micb_num, int req) 2987 { 2988 return wcd938x_micbias_control(component, micb_num, req, false); 2989 } 2990 2991 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2992 bool enable) 2993 { 2994 if (enable) { 2995 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2996 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 2997 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 2998 WCD938X_RAMP_EN_MASK, 1); 2999 } else { 3000 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 3001 WCD938X_RAMP_EN_MASK, 0); 3002 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 3003 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 3004 } 3005 } 3006 3007 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 3008 { 3009 /* min micbias voltage is 1V and maximum is 2.85V */ 3010 if (micb_mv < 1000 || micb_mv > 2850) 3011 return -EINVAL; 3012 3013 return (micb_mv - 1000) / 50; 3014 } 3015 3016 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 3017 int req_volt, int micb_num) 3018 { 3019 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3020 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 3021 3022 switch (micb_num) { 3023 case MIC_BIAS_1: 3024 micb_reg = WCD938X_ANA_MICB1; 3025 break; 3026 case MIC_BIAS_2: 3027 micb_reg = WCD938X_ANA_MICB2; 3028 break; 3029 case MIC_BIAS_3: 3030 micb_reg = WCD938X_ANA_MICB3; 3031 break; 3032 case MIC_BIAS_4: 3033 micb_reg = WCD938X_ANA_MICB4; 3034 break; 3035 default: 3036 return -EINVAL; 3037 } 3038 mutex_lock(&wcd938x->micb_lock); 3039 /* 3040 * If requested micbias voltage is same as current micbias 3041 * voltage, then just return. Otherwise, adjust voltage as 3042 * per requested value. If micbias is already enabled, then 3043 * to avoid slow micbias ramp-up or down enable pull-up 3044 * momentarily, change the micbias value and then re-enable 3045 * micbias. 3046 */ 3047 micb_en = snd_soc_component_read_field(component, micb_reg, 3048 WCD938X_MICB_EN_MASK); 3049 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 3050 WCD938X_MICB_VOUT_MASK); 3051 3052 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 3053 if (req_vout_ctl < 0) { 3054 ret = -EINVAL; 3055 goto exit; 3056 } 3057 3058 if (cur_vout_ctl == req_vout_ctl) { 3059 ret = 0; 3060 goto exit; 3061 } 3062 3063 if (micb_en == WCD938X_MICB_ENABLE) 3064 snd_soc_component_write_field(component, micb_reg, 3065 WCD938X_MICB_EN_MASK, 3066 WCD938X_MICB_PULL_UP); 3067 3068 snd_soc_component_write_field(component, micb_reg, 3069 WCD938X_MICB_VOUT_MASK, 3070 req_vout_ctl); 3071 3072 if (micb_en == WCD938X_MICB_ENABLE) { 3073 snd_soc_component_write_field(component, micb_reg, 3074 WCD938X_MICB_EN_MASK, 3075 WCD938X_MICB_ENABLE); 3076 /* 3077 * Add 2ms delay as per HW requirement after enabling 3078 * micbias 3079 */ 3080 usleep_range(2000, 2100); 3081 } 3082 exit: 3083 mutex_unlock(&wcd938x->micb_lock); 3084 return ret; 3085 } 3086 3087 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 3088 int micb_num, bool req_en) 3089 { 3090 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3091 int micb_mv; 3092 3093 if (micb_num != MIC_BIAS_2) 3094 return -EINVAL; 3095 /* 3096 * If device tree micbias level is already above the minimum 3097 * voltage needed to detect threshold microphone, then do 3098 * not change the micbias, just return. 3099 */ 3100 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 3101 return 0; 3102 3103 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 3104 3105 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 3106 } 3107 3108 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x, 3109 s16 *d1_a, u16 noff, 3110 int32_t *zdet) 3111 { 3112 int i; 3113 int val, val1; 3114 s16 c1; 3115 s32 x1, d1; 3116 int32_t denom; 3117 int minCode_param[] = { 3118 3277, 1639, 820, 410, 205, 103, 52, 26 3119 }; 3120 3121 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 3122 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 3123 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 3124 if (val & 0x80) 3125 break; 3126 } 3127 val = val << 0x8; 3128 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 3129 val |= val1; 3130 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 3131 x1 = WCD938X_MBHC_GET_X1(val); 3132 c1 = WCD938X_MBHC_GET_C1(val); 3133 /* If ramp is not complete, give additional 5ms */ 3134 if ((c1 < 2) && x1) 3135 usleep_range(5000, 5050); 3136 3137 if (!c1 || !x1) { 3138 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 3139 __func__, c1, x1); 3140 goto ramp_down; 3141 } 3142 d1 = d1_a[c1]; 3143 denom = (x1 * d1) - (1 << (14 - noff)); 3144 if (denom > 0) 3145 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 3146 else if (x1 < minCode_param[noff]) 3147 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 3148 3149 pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 3150 __func__, d1, c1, x1, *zdet); 3151 ramp_down: 3152 i = 0; 3153 while (x1) { 3154 regmap_read(wcd938x->regmap, 3155 WCD938X_ANA_MBHC_RESULT_1, &val); 3156 regmap_read(wcd938x->regmap, 3157 WCD938X_ANA_MBHC_RESULT_2, &val1); 3158 val = val << 0x08; 3159 val |= val1; 3160 x1 = WCD938X_MBHC_GET_X1(val); 3161 i++; 3162 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 3163 break; 3164 } 3165 } 3166 3167 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 3168 struct wcd938x_mbhc_zdet_param *zdet_param, 3169 int32_t *zl, int32_t *zr, s16 *d1_a) 3170 { 3171 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3172 int32_t zdet = 0; 3173 3174 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3175 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 3176 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 3177 WCD938X_VTH_MASK, zdet_param->btn5); 3178 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 3179 WCD938X_VTH_MASK, zdet_param->btn6); 3180 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 3181 WCD938X_VTH_MASK, zdet_param->btn7); 3182 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 3183 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 3184 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 3185 0x0F, zdet_param->nshift); 3186 3187 if (!zl) 3188 goto z_right; 3189 /* Start impedance measurement for HPH_L */ 3190 regmap_update_bits(wcd938x->regmap, 3191 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 3192 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 3193 __func__, zdet_param->noff); 3194 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3195 regmap_update_bits(wcd938x->regmap, 3196 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 3197 3198 *zl = zdet; 3199 3200 z_right: 3201 if (!zr) 3202 return; 3203 /* Start impedance measurement for HPH_R */ 3204 regmap_update_bits(wcd938x->regmap, 3205 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 3206 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 3207 __func__, zdet_param->noff); 3208 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet); 3209 regmap_update_bits(wcd938x->regmap, 3210 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 3211 3212 *zr = zdet; 3213 } 3214 3215 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 3216 int32_t *z_val, int flag_l_r) 3217 { 3218 s16 q1; 3219 int q1_cal; 3220 3221 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 3222 q1 = snd_soc_component_read(component, 3223 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 3224 else 3225 q1 = snd_soc_component_read(component, 3226 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 3227 if (q1 & 0x80) 3228 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 3229 else 3230 q1_cal = (10000 + (q1 * 25)); 3231 if (q1_cal > 0) 3232 *z_val = ((*z_val) * 10000) / q1_cal; 3233 } 3234 3235 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 3236 uint32_t *zl, uint32_t *zr) 3237 { 3238 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3239 s16 reg0, reg1, reg2, reg3, reg4; 3240 int32_t z1L, z1R, z1Ls; 3241 int zMono, z_diff1, z_diff2; 3242 bool is_fsm_disable = false; 3243 struct wcd938x_mbhc_zdet_param zdet_param[] = { 3244 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 3245 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 3246 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 3247 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 3248 }; 3249 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 3250 s16 d1_a[][4] = { 3251 {0, 30, 90, 30}, 3252 {0, 30, 30, 5}, 3253 {0, 30, 30, 5}, 3254 {0, 30, 30, 5}, 3255 }; 3256 s16 *d1 = NULL; 3257 3258 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 3259 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 3260 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 3261 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 3262 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 3263 3264 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 3265 is_fsm_disable = true; 3266 regmap_update_bits(wcd938x->regmap, 3267 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 3268 } 3269 3270 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 3271 if (wcd938x->mbhc_cfg.hphl_swh) 3272 regmap_update_bits(wcd938x->regmap, 3273 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 3274 3275 /* Turn off 100k pull down on HPHL */ 3276 regmap_update_bits(wcd938x->regmap, 3277 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 3278 3279 /* Disable surge protection before impedance detection. 3280 * This is done to give correct value for high impedance. 3281 */ 3282 regmap_update_bits(wcd938x->regmap, 3283 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 3284 /* 1ms delay needed after disable surge protection */ 3285 usleep_range(1000, 1010); 3286 3287 /* First get impedance on Left */ 3288 d1 = d1_a[1]; 3289 zdet_param_ptr = &zdet_param[1]; 3290 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3291 3292 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 3293 goto left_ch_impedance; 3294 3295 /* Second ramp for left ch */ 3296 if (z1L < WCD938X_ZDET_VAL_32) { 3297 zdet_param_ptr = &zdet_param[0]; 3298 d1 = d1_a[0]; 3299 } else if ((z1L > WCD938X_ZDET_VAL_400) && 3300 (z1L <= WCD938X_ZDET_VAL_1200)) { 3301 zdet_param_ptr = &zdet_param[2]; 3302 d1 = d1_a[2]; 3303 } else if (z1L > WCD938X_ZDET_VAL_1200) { 3304 zdet_param_ptr = &zdet_param[3]; 3305 d1 = d1_a[3]; 3306 } 3307 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 3308 3309 left_ch_impedance: 3310 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3311 (z1L > WCD938X_ZDET_VAL_100K)) { 3312 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 3313 zdet_param_ptr = &zdet_param[1]; 3314 d1 = d1_a[1]; 3315 } else { 3316 *zl = z1L/1000; 3317 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 3318 } 3319 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 3320 __func__, *zl); 3321 3322 /* Start of right impedance ramp and calculation */ 3323 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3324 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 3325 if (((z1R > WCD938X_ZDET_VAL_1200) && 3326 (zdet_param_ptr->noff == 0x6)) || 3327 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 3328 goto right_ch_impedance; 3329 /* Second ramp for right ch */ 3330 if (z1R < WCD938X_ZDET_VAL_32) { 3331 zdet_param_ptr = &zdet_param[0]; 3332 d1 = d1_a[0]; 3333 } else if ((z1R > WCD938X_ZDET_VAL_400) && 3334 (z1R <= WCD938X_ZDET_VAL_1200)) { 3335 zdet_param_ptr = &zdet_param[2]; 3336 d1 = d1_a[2]; 3337 } else if (z1R > WCD938X_ZDET_VAL_1200) { 3338 zdet_param_ptr = &zdet_param[3]; 3339 d1 = d1_a[3]; 3340 } 3341 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 3342 } 3343 right_ch_impedance: 3344 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3345 (z1R > WCD938X_ZDET_VAL_100K)) { 3346 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 3347 } else { 3348 *zr = z1R/1000; 3349 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 3350 } 3351 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 3352 __func__, *zr); 3353 3354 /* Mono/stereo detection */ 3355 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 3356 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 3357 dev_dbg(component->dev, 3358 "%s: plug type is invalid or extension cable\n", 3359 __func__); 3360 goto zdet_complete; 3361 } 3362 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3363 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 3364 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 3365 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 3366 dev_dbg(component->dev, 3367 "%s: Mono plug type with one ch floating or shorted to GND\n", 3368 __func__); 3369 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3370 goto zdet_complete; 3371 } 3372 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3373 WCD938X_HPHPA_GND_OVR_MASK, 1); 3374 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3375 WCD938X_HPHPA_GND_R_MASK, 1); 3376 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 3377 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 3378 else 3379 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 3380 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3381 WCD938X_HPHPA_GND_R_MASK, 0); 3382 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 3383 WCD938X_HPHPA_GND_OVR_MASK, 0); 3384 z1Ls /= 1000; 3385 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 3386 /* Parallel of left Z and 9 ohm pull down resistor */ 3387 zMono = ((*zl) * 9) / ((*zl) + 9); 3388 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 3389 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 3390 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 3391 dev_dbg(component->dev, "%s: stereo plug type detected\n", 3392 __func__); 3393 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 3394 } else { 3395 dev_dbg(component->dev, "%s: MONO plug type detected\n", 3396 __func__); 3397 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 3398 } 3399 3400 /* Enable surge protection again after impedance detection */ 3401 regmap_update_bits(wcd938x->regmap, 3402 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 3403 zdet_complete: 3404 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 3405 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 3406 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 3407 /* Turn on 100k pull down on HPHL */ 3408 regmap_update_bits(wcd938x->regmap, 3409 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 3410 3411 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 3412 if (wcd938x->mbhc_cfg.hphl_swh) 3413 regmap_update_bits(wcd938x->regmap, 3414 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 3415 3416 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 3417 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 3418 if (is_fsm_disable) 3419 regmap_update_bits(wcd938x->regmap, 3420 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 3421 } 3422 3423 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 3424 bool enable) 3425 { 3426 if (enable) { 3427 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3428 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 3429 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3430 WCD938X_MBHC_GND_DET_EN_MASK, 1); 3431 } else { 3432 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3433 WCD938X_MBHC_GND_DET_EN_MASK, 0); 3434 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 3435 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 3436 } 3437 } 3438 3439 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 3440 bool enable) 3441 { 3442 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3443 WCD938X_HPHPA_GND_R_MASK, enable); 3444 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 3445 WCD938X_HPHPA_GND_L_MASK, enable); 3446 } 3447 3448 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 3449 { 3450 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3451 3452 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3453 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3454 WCD938X_M_RTH_CTL_MASK, R_OFF); 3455 return; 3456 } 3457 3458 /* Do not enable moisture detection if jack type is NC */ 3459 if (!wcd938x->mbhc_cfg.hphl_swh) { 3460 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3461 __func__); 3462 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3463 WCD938X_M_RTH_CTL_MASK, R_OFF); 3464 return; 3465 } 3466 3467 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3468 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3469 } 3470 3471 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 3472 { 3473 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3474 3475 if (enable) 3476 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3477 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 3478 else 3479 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3480 WCD938X_M_RTH_CTL_MASK, R_OFF); 3481 } 3482 3483 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 3484 { 3485 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3486 bool ret = false; 3487 3488 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 3489 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3490 WCD938X_M_RTH_CTL_MASK, R_OFF); 3491 goto done; 3492 } 3493 3494 /* Do not enable moisture detection if jack type is NC */ 3495 if (!wcd938x->mbhc_cfg.hphl_swh) { 3496 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 3497 __func__); 3498 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 3499 WCD938X_M_RTH_CTL_MASK, R_OFF); 3500 goto done; 3501 } 3502 3503 /* 3504 * If moisture_en is already enabled, then skip to plug type 3505 * detection. 3506 */ 3507 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 3508 goto done; 3509 3510 wcd938x_mbhc_moisture_detect_en(component, true); 3511 /* Read moisture comparator status */ 3512 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 3513 & 0x20) ? 0 : 1); 3514 3515 done: 3516 return ret; 3517 3518 } 3519 3520 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 3521 bool enable) 3522 { 3523 snd_soc_component_write_field(component, 3524 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 3525 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 3526 } 3527 3528 static const struct wcd_mbhc_cb mbhc_cb = { 3529 .clk_setup = wcd938x_mbhc_clk_setup, 3530 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 3531 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 3532 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 3533 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 3534 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 3535 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 3536 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 3537 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 3538 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 3539 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 3540 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 3541 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 3542 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 3543 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 3544 }; 3545 3546 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 3547 struct snd_ctl_elem_value *ucontrol) 3548 { 3549 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3550 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3551 3552 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 3553 3554 return 0; 3555 } 3556 3557 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 3558 struct snd_ctl_elem_value *ucontrol) 3559 { 3560 uint32_t zl, zr; 3561 bool hphr; 3562 struct soc_mixer_control *mc; 3563 struct snd_soc_component *component = 3564 snd_soc_kcontrol_component(kcontrol); 3565 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3566 3567 mc = (struct soc_mixer_control *)(kcontrol->private_value); 3568 hphr = mc->shift; 3569 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 3570 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 3571 ucontrol->value.integer.value[0] = hphr ? zr : zl; 3572 3573 return 0; 3574 } 3575 3576 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3577 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 3578 wcd938x_get_hph_type, NULL), 3579 }; 3580 3581 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3582 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 3583 wcd938x_hph_impedance_get, NULL), 3584 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 3585 wcd938x_hph_impedance_get, NULL), 3586 }; 3587 3588 static int wcd938x_mbhc_init(struct snd_soc_component *component) 3589 { 3590 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3591 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 3592 3593 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3594 WCD938X_IRQ_MBHC_SW_DET); 3595 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3596 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 3597 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3598 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 3599 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3600 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3601 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 3602 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 3603 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3604 WCD938X_IRQ_HPHL_OCP_INT); 3605 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 3606 WCD938X_IRQ_HPHR_OCP_INT); 3607 3608 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3609 3610 snd_soc_add_component_controls(component, impedance_detect_controls, 3611 ARRAY_SIZE(impedance_detect_controls)); 3612 snd_soc_add_component_controls(component, hph_type_detect_controls, 3613 ARRAY_SIZE(hph_type_detect_controls)); 3614 3615 return 0; 3616 } 3617 /* END MBHC */ 3618 3619 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 3620 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 3621 wcd938x_get_compander, wcd938x_set_compander), 3622 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 3623 wcd938x_get_compander, wcd938x_set_compander), 3624 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 3625 wcd938x_get_swr_port, wcd938x_set_swr_port), 3626 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 3627 wcd938x_get_swr_port, wcd938x_set_swr_port), 3628 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 3629 wcd938x_get_swr_port, wcd938x_set_swr_port), 3630 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 3631 wcd938x_get_swr_port, wcd938x_set_swr_port), 3632 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 3633 wcd938x_get_swr_port, wcd938x_set_swr_port), 3634 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 3635 wcd938x_get_swr_port, wcd938x_set_swr_port), 3636 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain), 3637 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain), 3638 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 3639 2, 0x10, 0, ear_pa_gain), 3640 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 3641 wcd938x_get_swr_port, wcd938x_set_swr_port), 3642 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 3643 wcd938x_get_swr_port, wcd938x_set_swr_port), 3644 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 3645 wcd938x_get_swr_port, wcd938x_set_swr_port), 3646 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 3647 wcd938x_get_swr_port, wcd938x_set_swr_port), 3648 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 3649 wcd938x_get_swr_port, wcd938x_set_swr_port), 3650 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 3651 wcd938x_get_swr_port, wcd938x_set_swr_port), 3652 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 3653 wcd938x_get_swr_port, wcd938x_set_swr_port), 3654 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 3655 wcd938x_get_swr_port, wcd938x_set_swr_port), 3656 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 3657 wcd938x_get_swr_port, wcd938x_set_swr_port), 3658 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 3659 wcd938x_get_swr_port, wcd938x_set_swr_port), 3660 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 3661 wcd938x_get_swr_port, wcd938x_set_swr_port), 3662 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 3663 wcd938x_get_swr_port, wcd938x_set_swr_port), 3664 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 3665 wcd938x_get_swr_port, wcd938x_set_swr_port), 3666 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 3667 wcd938x_ldoh_get, wcd938x_ldoh_put), 3668 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0, 3669 wcd938x_bcs_get, wcd938x_bcs_put), 3670 3671 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 3672 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 3673 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 3674 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 3675 }; 3676 3677 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 3678 3679 /*input widgets*/ 3680 SND_SOC_DAPM_INPUT("AMIC1"), 3681 SND_SOC_DAPM_INPUT("AMIC2"), 3682 SND_SOC_DAPM_INPUT("AMIC3"), 3683 SND_SOC_DAPM_INPUT("AMIC4"), 3684 SND_SOC_DAPM_INPUT("AMIC5"), 3685 SND_SOC_DAPM_INPUT("AMIC6"), 3686 SND_SOC_DAPM_INPUT("AMIC7"), 3687 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 3688 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 3689 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 3690 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 3691 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 3692 3693 /*tx widgets*/ 3694 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 3695 wcd938x_codec_enable_adc, 3696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3697 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 3698 wcd938x_codec_enable_adc, 3699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3700 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 3701 wcd938x_codec_enable_adc, 3702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3703 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 3704 wcd938x_codec_enable_adc, 3705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3706 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 3707 wcd938x_codec_enable_dmic, 3708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3709 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 3710 wcd938x_codec_enable_dmic, 3711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3712 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 3713 wcd938x_codec_enable_dmic, 3714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3715 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 3716 wcd938x_codec_enable_dmic, 3717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3718 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 3719 wcd938x_codec_enable_dmic, 3720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3721 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 3722 wcd938x_codec_enable_dmic, 3723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3724 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 3725 wcd938x_codec_enable_dmic, 3726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3727 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 3728 wcd938x_codec_enable_dmic, 3729 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3730 3731 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 3732 NULL, 0, wcd938x_adc_enable_req, 3733 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3734 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 3735 NULL, 0, wcd938x_adc_enable_req, 3736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3737 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 3738 NULL, 0, wcd938x_adc_enable_req, 3739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3740 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 3741 wcd938x_adc_enable_req, 3742 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3743 3744 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 3745 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 3746 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 3747 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 3748 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 3749 3750 /*tx mixers*/ 3751 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 3752 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 3753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3754 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 3755 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 3756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3757 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 3758 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 3759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3760 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 3761 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 3762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3763 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 3764 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 3765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3766 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 3767 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 3768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3769 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 3770 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 3771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3772 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 3773 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 3774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3775 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 3776 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 3777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3778 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 3779 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 3780 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3781 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 3782 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 3783 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3784 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 3785 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 3786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3787 /* micbias widgets*/ 3788 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3789 wcd938x_codec_enable_micbias, 3790 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3791 SND_SOC_DAPM_POST_PMD), 3792 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3793 wcd938x_codec_enable_micbias, 3794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3795 SND_SOC_DAPM_POST_PMD), 3796 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3797 wcd938x_codec_enable_micbias, 3798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3799 SND_SOC_DAPM_POST_PMD), 3800 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3801 wcd938x_codec_enable_micbias, 3802 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3803 SND_SOC_DAPM_POST_PMD), 3804 3805 /* micbias pull up widgets*/ 3806 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 3807 wcd938x_codec_enable_micbias_pullup, 3808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3809 SND_SOC_DAPM_POST_PMD), 3810 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 3811 wcd938x_codec_enable_micbias_pullup, 3812 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3813 SND_SOC_DAPM_POST_PMD), 3814 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 3815 wcd938x_codec_enable_micbias_pullup, 3816 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3817 SND_SOC_DAPM_POST_PMD), 3818 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 3819 wcd938x_codec_enable_micbias_pullup, 3820 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3821 SND_SOC_DAPM_POST_PMD), 3822 3823 /*output widgets tx*/ 3824 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 3825 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 3826 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 3827 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 3828 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 3829 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 3830 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 3831 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 3832 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 3833 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 3834 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 3835 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 3836 3837 SND_SOC_DAPM_INPUT("IN1_HPHL"), 3838 SND_SOC_DAPM_INPUT("IN2_HPHR"), 3839 SND_SOC_DAPM_INPUT("IN3_AUX"), 3840 3841 /*rx widgets*/ 3842 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 3843 wcd938x_codec_enable_ear_pa, 3844 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3845 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3846 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 3847 wcd938x_codec_enable_aux_pa, 3848 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3849 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3850 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 3851 wcd938x_codec_enable_hphl_pa, 3852 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3853 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3854 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 3855 wcd938x_codec_enable_hphr_pa, 3856 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3857 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3858 3859 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 3860 wcd938x_codec_hphl_dac_event, 3861 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3862 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3863 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 3864 wcd938x_codec_hphr_dac_event, 3865 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3866 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3867 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 3868 wcd938x_codec_ear_dac_event, 3869 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3870 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3871 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 3872 wcd938x_codec_aux_dac_event, 3873 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3874 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 3875 3876 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 3877 3878 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 3879 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 3880 wcd938x_codec_enable_rxclk, 3881 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3882 SND_SOC_DAPM_POST_PMD), 3883 3884 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 3885 3886 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3887 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3888 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 3889 3890 /* rx mixer widgets*/ 3891 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 3892 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 3893 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 3894 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 3895 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 3896 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 3897 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 3898 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 3899 3900 /*output widgets rx*/ 3901 SND_SOC_DAPM_OUTPUT("EAR"), 3902 SND_SOC_DAPM_OUTPUT("AUX"), 3903 SND_SOC_DAPM_OUTPUT("HPHL"), 3904 SND_SOC_DAPM_OUTPUT("HPHR"), 3905 3906 }; 3907 3908 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 3909 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 3910 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 3911 {"ADC1 REQ", NULL, "ADC1"}, 3912 {"ADC1", NULL, "AMIC1"}, 3913 3914 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 3915 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 3916 {"ADC2 REQ", NULL, "ADC2"}, 3917 {"ADC2", NULL, "HDR12 MUX"}, 3918 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 3919 {"HDR12 MUX", "HDR12", "AMIC1"}, 3920 {"ADC2 MUX", "INP3", "AMIC3"}, 3921 {"ADC2 MUX", "INP2", "AMIC2"}, 3922 3923 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 3924 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 3925 {"ADC3 REQ", NULL, "ADC3"}, 3926 {"ADC3", NULL, "HDR34 MUX"}, 3927 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 3928 {"HDR34 MUX", "HDR34", "AMIC5"}, 3929 {"ADC3 MUX", "INP4", "AMIC4"}, 3930 {"ADC3 MUX", "INP6", "AMIC6"}, 3931 3932 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 3933 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 3934 {"ADC4 REQ", NULL, "ADC4"}, 3935 {"ADC4", NULL, "ADC4 MUX"}, 3936 {"ADC4 MUX", "INP5", "AMIC5"}, 3937 {"ADC4 MUX", "INP7", "AMIC7"}, 3938 3939 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 3940 {"DMIC1_MIXER", "Switch", "DMIC1"}, 3941 3942 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 3943 {"DMIC2_MIXER", "Switch", "DMIC2"}, 3944 3945 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 3946 {"DMIC3_MIXER", "Switch", "DMIC3"}, 3947 3948 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 3949 {"DMIC4_MIXER", "Switch", "DMIC4"}, 3950 3951 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 3952 {"DMIC5_MIXER", "Switch", "DMIC5"}, 3953 3954 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 3955 {"DMIC6_MIXER", "Switch", "DMIC6"}, 3956 3957 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 3958 {"DMIC7_MIXER", "Switch", "DMIC7"}, 3959 3960 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 3961 {"DMIC8_MIXER", "Switch", "DMIC8"}, 3962 3963 {"IN1_HPHL", NULL, "VDD_BUCK"}, 3964 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 3965 3966 {"RX1", NULL, "IN1_HPHL"}, 3967 {"RX1", NULL, "RXCLK"}, 3968 {"RDAC1", NULL, "RX1"}, 3969 {"HPHL_RDAC", "Switch", "RDAC1"}, 3970 {"HPHL PGA", NULL, "HPHL_RDAC"}, 3971 {"HPHL", NULL, "HPHL PGA"}, 3972 3973 {"IN2_HPHR", NULL, "VDD_BUCK"}, 3974 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 3975 {"RX2", NULL, "IN2_HPHR"}, 3976 {"RDAC2", NULL, "RX2"}, 3977 {"RX2", NULL, "RXCLK"}, 3978 {"HPHR_RDAC", "Switch", "RDAC2"}, 3979 {"HPHR PGA", NULL, "HPHR_RDAC"}, 3980 {"HPHR", NULL, "HPHR PGA"}, 3981 3982 {"IN3_AUX", NULL, "VDD_BUCK"}, 3983 {"IN3_AUX", NULL, "CLS_H_PORT"}, 3984 {"RX3", NULL, "IN3_AUX"}, 3985 {"RDAC4", NULL, "RX3"}, 3986 {"RX3", NULL, "RXCLK"}, 3987 {"AUX_RDAC", "Switch", "RDAC4"}, 3988 {"AUX PGA", NULL, "AUX_RDAC"}, 3989 {"AUX", NULL, "AUX PGA"}, 3990 3991 {"RDAC3_MUX", "RX3", "RX3"}, 3992 {"RDAC3_MUX", "RX1", "RX1"}, 3993 {"RDAC3", NULL, "RDAC3_MUX"}, 3994 {"EAR_RDAC", "Switch", "RDAC3"}, 3995 {"EAR PGA", NULL, "EAR_RDAC"}, 3996 {"EAR", NULL, "EAR PGA"}, 3997 }; 3998 3999 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 4000 { 4001 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 4002 4003 /* set micbias voltage */ 4004 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 4005 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 4006 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 4007 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 4008 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 4009 return -EINVAL; 4010 4011 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 4012 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 4013 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 4014 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 4015 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 4016 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 4017 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 4018 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 4019 4020 return 0; 4021 } 4022 4023 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 4024 { 4025 return IRQ_HANDLED; 4026 } 4027 4028 static struct irq_chip wcd_irq_chip = { 4029 .name = "WCD938x", 4030 }; 4031 4032 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 4033 irq_hw_number_t hw) 4034 { 4035 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 4036 irq_set_nested_thread(virq, 1); 4037 irq_set_noprobe(virq); 4038 4039 return 0; 4040 } 4041 4042 static const struct irq_domain_ops wcd_domain_ops = { 4043 .map = wcd_irq_chip_map, 4044 }; 4045 4046 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 4047 { 4048 4049 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL); 4050 if (!(wcd->virq)) { 4051 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 4052 return -EINVAL; 4053 } 4054 4055 return devm_regmap_add_irq_chip(dev, wcd->regmap, 4056 irq_create_mapping(wcd->virq, 0), 4057 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 4058 &wcd->irq_chip); 4059 } 4060 4061 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 4062 { 4063 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 4064 struct device *dev = component->dev; 4065 int ret, i; 4066 4067 snd_soc_component_init_regmap(component, wcd938x->regmap); 4068 4069 wcd938x->variant = snd_soc_component_read_field(component, 4070 WCD938X_DIGITAL_EFUSE_REG_0, 4071 WCD938X_ID_MASK); 4072 4073 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 4074 4075 wcd938x_io_init(wcd938x); 4076 /* Set all interrupts as edge triggered */ 4077 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 4078 regmap_write(wcd938x->regmap, 4079 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 4080 } 4081 4082 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4083 WCD938X_IRQ_HPHR_PDM_WD_INT); 4084 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4085 WCD938X_IRQ_HPHL_PDM_WD_INT); 4086 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 4087 WCD938X_IRQ_AUX_PDM_WD_INT); 4088 4089 /* Request for watchdog interrupt */ 4090 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4091 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4092 "HPHR PDM WD INT", wcd938x); 4093 if (ret) 4094 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 4095 4096 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4097 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4098 "HPHL PDM WD INT", wcd938x); 4099 if (ret) 4100 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 4101 4102 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 4103 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 4104 "AUX PDM WD INT", wcd938x); 4105 if (ret) 4106 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 4107 4108 /* Disable watchdog interrupt for HPH and AUX */ 4109 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 4110 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 4111 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 4112 4113 switch (wcd938x->variant) { 4114 case WCD9380: 4115 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 4116 ARRAY_SIZE(wcd9380_snd_controls)); 4117 if (ret < 0) { 4118 dev_err(component->dev, 4119 "%s: Failed to add snd ctrls for variant: %d\n", 4120 __func__, wcd938x->variant); 4121 goto err; 4122 } 4123 break; 4124 case WCD9385: 4125 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 4126 ARRAY_SIZE(wcd9385_snd_controls)); 4127 if (ret < 0) { 4128 dev_err(component->dev, 4129 "%s: Failed to add snd ctrls for variant: %d\n", 4130 __func__, wcd938x->variant); 4131 goto err; 4132 } 4133 break; 4134 default: 4135 break; 4136 } 4137 4138 ret = wcd938x_mbhc_init(component); 4139 if (ret) 4140 dev_err(component->dev, "mbhc initialization failed\n"); 4141 err: 4142 return ret; 4143 } 4144 4145 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 4146 struct snd_soc_jack *jack, void *data) 4147 { 4148 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 4149 4150 if (jack) 4151 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 4152 else 4153 wcd_mbhc_stop(wcd->wcd_mbhc); 4154 4155 return 0; 4156 } 4157 4158 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 4159 .name = "wcd938x_codec", 4160 .probe = wcd938x_soc_codec_probe, 4161 .controls = wcd938x_snd_controls, 4162 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 4163 .dapm_widgets = wcd938x_dapm_widgets, 4164 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 4165 .dapm_routes = wcd938x_audio_map, 4166 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 4167 .set_jack = wcd938x_codec_set_jack, 4168 }; 4169 4170 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 4171 { 4172 struct device_node *np = dev->of_node; 4173 u32 prop_val = 0; 4174 int rc = 0; 4175 4176 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 4177 if (!rc) 4178 wcd->micb1_mv = prop_val/1000; 4179 else 4180 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 4181 4182 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 4183 if (!rc) 4184 wcd->micb2_mv = prop_val/1000; 4185 else 4186 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 4187 4188 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 4189 if (!rc) 4190 wcd->micb3_mv = prop_val/1000; 4191 else 4192 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 4193 4194 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 4195 if (!rc) 4196 wcd->micb4_mv = prop_val/1000; 4197 else 4198 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 4199 } 4200 4201 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active) 4202 { 4203 int value; 4204 4205 struct wcd938x_priv *wcd938x; 4206 4207 wcd938x = snd_soc_component_get_drvdata(component); 4208 4209 value = gpiod_get_value(wcd938x->us_euro_gpio); 4210 4211 gpiod_set_value(wcd938x->us_euro_gpio, !value); 4212 4213 return true; 4214 } 4215 4216 4217 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 4218 { 4219 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 4220 int ret; 4221 4222 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0); 4223 if (wcd938x->reset_gpio < 0) { 4224 dev_err(dev, "Failed to get reset gpio: err = %d\n", 4225 wcd938x->reset_gpio); 4226 return wcd938x->reset_gpio; 4227 } 4228 4229 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", 4230 GPIOD_OUT_LOW); 4231 if (IS_ERR(wcd938x->us_euro_gpio)) { 4232 dev_err(dev, "us-euro swap Control GPIO not found\n"); 4233 return PTR_ERR(wcd938x->us_euro_gpio); 4234 } 4235 4236 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 4237 4238 wcd938x->supplies[0].supply = "vdd-rxtx"; 4239 wcd938x->supplies[1].supply = "vdd-io"; 4240 wcd938x->supplies[2].supply = "vdd-buck"; 4241 wcd938x->supplies[3].supply = "vdd-mic-bias"; 4242 4243 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies); 4244 if (ret) { 4245 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 4246 return ret; 4247 } 4248 4249 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 4250 if (ret) { 4251 dev_err(dev, "Failed to enable supplies: err = %d\n", ret); 4252 return ret; 4253 } 4254 4255 wcd938x_dt_parse_micbias_info(dev, wcd938x); 4256 4257 cfg->mbhc_micbias = MIC_BIAS_2; 4258 cfg->anc_micbias = MIC_BIAS_2; 4259 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 4260 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 4261 cfg->micb_mv = wcd938x->micb2_mv; 4262 cfg->linein_th = 5000; 4263 cfg->hs_thr = 1700; 4264 cfg->hph_thr = 50; 4265 4266 wcd_dt_parse_mbhc_data(dev, cfg); 4267 4268 return 0; 4269 } 4270 4271 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 4272 { 4273 gpio_direction_output(wcd938x->reset_gpio, 0); 4274 /* 20us sleep required after pulling the reset gpio to LOW */ 4275 usleep_range(20, 30); 4276 gpio_set_value(wcd938x->reset_gpio, 1); 4277 /* 20us sleep required after pulling the reset gpio to HIGH */ 4278 usleep_range(20, 30); 4279 4280 return 0; 4281 } 4282 4283 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 4284 struct snd_pcm_hw_params *params, 4285 struct snd_soc_dai *dai) 4286 { 4287 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4288 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4289 4290 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 4291 } 4292 4293 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 4294 struct snd_soc_dai *dai) 4295 { 4296 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4297 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4298 4299 return wcd938x_sdw_free(wcd, substream, dai); 4300 } 4301 4302 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 4303 void *stream, int direction) 4304 { 4305 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 4306 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 4307 4308 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 4309 4310 } 4311 4312 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 4313 .hw_params = wcd938x_codec_hw_params, 4314 .hw_free = wcd938x_codec_free, 4315 .set_stream = wcd938x_codec_set_sdw_stream, 4316 }; 4317 4318 static struct snd_soc_dai_driver wcd938x_dais[] = { 4319 [0] = { 4320 .name = "wcd938x-sdw-rx", 4321 .playback = { 4322 .stream_name = "WCD AIF1 Playback", 4323 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 4324 .formats = WCD938X_FORMATS_S16_S24_LE, 4325 .rate_max = 192000, 4326 .rate_min = 8000, 4327 .channels_min = 1, 4328 .channels_max = 2, 4329 }, 4330 .ops = &wcd938x_sdw_dai_ops, 4331 }, 4332 [1] = { 4333 .name = "wcd938x-sdw-tx", 4334 .capture = { 4335 .stream_name = "WCD AIF1 Capture", 4336 .rates = WCD938X_RATES_MASK, 4337 .formats = SNDRV_PCM_FMTBIT_S16_LE, 4338 .rate_min = 8000, 4339 .rate_max = 192000, 4340 .channels_min = 1, 4341 .channels_max = 4, 4342 }, 4343 .ops = &wcd938x_sdw_dai_ops, 4344 }, 4345 }; 4346 4347 static int wcd938x_bind(struct device *dev) 4348 { 4349 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4350 int ret; 4351 4352 ret = component_bind_all(dev, wcd938x); 4353 if (ret) { 4354 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 4355 __func__, ret); 4356 return ret; 4357 } 4358 4359 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 4360 if (!wcd938x->rxdev) { 4361 dev_err(dev, "could not find slave with matching of node\n"); 4362 return -EINVAL; 4363 } 4364 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 4365 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 4366 4367 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 4368 if (!wcd938x->txdev) { 4369 dev_err(dev, "could not find txslave with matching of node\n"); 4370 return -EINVAL; 4371 } 4372 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 4373 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 4374 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 4375 if (!wcd938x->tx_sdw_dev) { 4376 dev_err(dev, "could not get txslave with matching of dev\n"); 4377 return -EINVAL; 4378 } 4379 4380 /* As TX is main CSR reg interface, which should not be suspended first. 4381 * expicilty add the dependency link */ 4382 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 4383 DL_FLAG_PM_RUNTIME)) { 4384 dev_err(dev, "could not devlink tx and rx\n"); 4385 return -EINVAL; 4386 } 4387 4388 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 4389 DL_FLAG_PM_RUNTIME)) { 4390 dev_err(dev, "could not devlink wcd and tx\n"); 4391 return -EINVAL; 4392 } 4393 4394 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 4395 DL_FLAG_PM_RUNTIME)) { 4396 dev_err(dev, "could not devlink wcd and rx\n"); 4397 return -EINVAL; 4398 } 4399 4400 wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config); 4401 if (IS_ERR(wcd938x->regmap)) { 4402 dev_err(dev, "%s: tx csr regmap not found\n", __func__); 4403 return PTR_ERR(wcd938x->regmap); 4404 } 4405 4406 ret = wcd938x_irq_init(wcd938x, dev); 4407 if (ret) { 4408 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 4409 return ret; 4410 } 4411 4412 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 4413 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 4414 4415 ret = wcd938x_set_micbias_data(wcd938x); 4416 if (ret < 0) { 4417 dev_err(dev, "%s: bad micbias pdata\n", __func__); 4418 return ret; 4419 } 4420 4421 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 4422 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 4423 if (ret) 4424 dev_err(dev, "%s: Codec registration failed\n", 4425 __func__); 4426 4427 return ret; 4428 4429 } 4430 4431 static void wcd938x_unbind(struct device *dev) 4432 { 4433 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 4434 4435 device_link_remove(dev, wcd938x->txdev); 4436 device_link_remove(dev, wcd938x->rxdev); 4437 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 4438 snd_soc_unregister_component(dev); 4439 component_unbind_all(dev, wcd938x); 4440 } 4441 4442 static const struct component_master_ops wcd938x_comp_ops = { 4443 .bind = wcd938x_bind, 4444 .unbind = wcd938x_unbind, 4445 }; 4446 4447 static int wcd938x_compare_of(struct device *dev, void *data) 4448 { 4449 return dev->of_node == data; 4450 } 4451 4452 static void wcd938x_release_of(struct device *dev, void *data) 4453 { 4454 of_node_put(data); 4455 } 4456 4457 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 4458 struct device *dev, 4459 struct component_match **matchptr) 4460 { 4461 struct device_node *np; 4462 4463 np = dev->of_node; 4464 4465 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 4466 if (!wcd938x->rxnode) { 4467 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 4468 return -ENODEV; 4469 } 4470 4471 of_node_get(wcd938x->rxnode); 4472 component_match_add_release(dev, matchptr, wcd938x_release_of, 4473 wcd938x_compare_of, wcd938x->rxnode); 4474 4475 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 4476 if (!wcd938x->txnode) { 4477 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 4478 return -ENODEV; 4479 } 4480 of_node_get(wcd938x->txnode); 4481 component_match_add_release(dev, matchptr, wcd938x_release_of, 4482 wcd938x_compare_of, wcd938x->txnode); 4483 return 0; 4484 } 4485 4486 static int wcd938x_probe(struct platform_device *pdev) 4487 { 4488 struct component_match *match = NULL; 4489 struct wcd938x_priv *wcd938x = NULL; 4490 struct device *dev = &pdev->dev; 4491 int ret; 4492 4493 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 4494 GFP_KERNEL); 4495 if (!wcd938x) 4496 return -ENOMEM; 4497 4498 dev_set_drvdata(dev, wcd938x); 4499 mutex_init(&wcd938x->micb_lock); 4500 4501 ret = wcd938x_populate_dt_data(wcd938x, dev); 4502 if (ret) { 4503 dev_err(dev, "%s: Fail to obtain platform data\n", __func__); 4504 return -EINVAL; 4505 } 4506 4507 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 4508 if (ret) 4509 return ret; 4510 4511 wcd938x_reset(wcd938x); 4512 4513 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 4514 if (ret) 4515 return ret; 4516 4517 pm_runtime_set_autosuspend_delay(dev, 1000); 4518 pm_runtime_use_autosuspend(dev); 4519 pm_runtime_mark_last_busy(dev); 4520 pm_runtime_set_active(dev); 4521 pm_runtime_enable(dev); 4522 pm_runtime_idle(dev); 4523 4524 return 0; 4525 } 4526 4527 static int wcd938x_remove(struct platform_device *pdev) 4528 { 4529 component_master_del(&pdev->dev, &wcd938x_comp_ops); 4530 4531 return 0; 4532 } 4533 4534 #if defined(CONFIG_OF) 4535 static const struct of_device_id wcd938x_dt_match[] = { 4536 { .compatible = "qcom,wcd9380-codec" }, 4537 { .compatible = "qcom,wcd9385-codec" }, 4538 {} 4539 }; 4540 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 4541 #endif 4542 4543 static struct platform_driver wcd938x_codec_driver = { 4544 .probe = wcd938x_probe, 4545 .remove = wcd938x_remove, 4546 .driver = { 4547 .name = "wcd938x_codec", 4548 .of_match_table = of_match_ptr(wcd938x_dt_match), 4549 .suppress_bind_attrs = true, 4550 }, 4551 }; 4552 4553 module_platform_driver(wcd938x_codec_driver); 4554 MODULE_DESCRIPTION("WCD938X Codec driver"); 4555 MODULE_LICENSE("GPL"); 4556