1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/interrupt.h> 7 #include <linux/kernel.h> 8 #include <linux/mfd/wcd934x/registers.h> 9 #include <linux/mfd/wcd934x/wcd934x.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/of_clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/slimbus.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/tlv.h> 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 26 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 27 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 28 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 29 /* Fractional Rates */ 30 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 31 SNDRV_PCM_RATE_176400) 32 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD934X_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD934X_SLIM_NUM_PORT_REG 3 50 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 51 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 52 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 53 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 54 55 #define WCD934X_MCLK_CLK_12P288MHZ 12288000 56 #define WCD934X_MCLK_CLK_9P6MHZ 9600000 57 58 /* Only valid for 9.6 MHz mclk */ 59 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 60 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 61 62 /* Only valid for 12.288 MHz mclk */ 63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 64 65 #define WCD934X_DMIC_CLK_DIV_2 0x0 66 #define WCD934X_DMIC_CLK_DIV_3 0x1 67 #define WCD934X_DMIC_CLK_DIV_4 0x2 68 #define WCD934X_DMIC_CLK_DIV_6 0x3 69 #define WCD934X_DMIC_CLK_DIV_8 0x4 70 #define WCD934X_DMIC_CLK_DIV_16 0x5 71 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 72 73 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 74 #define CF_MIN_3DB_4HZ 0x0 75 #define CF_MIN_3DB_75HZ 0x1 76 #define CF_MIN_3DB_150HZ 0x2 77 78 #define WCD934X_RX_START 16 79 #define WCD934X_NUM_INTERPOLATORS 9 80 #define WCD934X_RX_PATH_CTL_OFFSET 20 81 #define WCD934X_MAX_VALID_ADC_MUX 13 82 #define WCD934X_INVALID_ADC_MUX 9 83 84 #define WCD934X_SLIM_RX_CH(p) \ 85 {.port = p + WCD934X_RX_START, .shift = p,} 86 87 #define WCD934X_SLIM_TX_CH(p) \ 88 {.port = p, .shift = p,} 89 90 /* Feature masks to distinguish codec version */ 91 #define DSD_DISABLED_MASK 0 92 #define SLNQ_DISABLED_MASK 1 93 94 #define DSD_DISABLED BIT(DSD_DISABLED_MASK) 95 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 96 97 /* As fine version info cannot be retrieved before wcd probe. 98 * Define three coarse versions for possible future use before wcd probe. 99 */ 100 #define WCD_VERSION_WCD9340_1_0 0x400 101 #define WCD_VERSION_WCD9341_1_0 0x410 102 #define WCD_VERSION_WCD9340_1_1 0x401 103 #define WCD_VERSION_WCD9341_1_1 0x411 104 #define WCD934X_AMIC_PWR_LEVEL_LP 0 105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 106 #define WCD934X_AMIC_PWR_LEVEL_HP 2 107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 108 #define WCD934X_AMIC_PWR_LVL_MASK 0x60 109 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 110 111 #define WCD934X_DEC_PWR_LVL_MASK 0x06 112 #define WCD934X_DEC_PWR_LVL_LP 0x02 113 #define WCD934X_DEC_PWR_LVL_HP 0x04 114 #define WCD934X_DEC_PWR_LVL_DF 0x00 115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 116 117 #define WCD934X_DEF_MICBIAS_MV 1800 118 #define WCD934X_MAX_MICBIAS_MV 2850 119 120 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 121 122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 123 { \ 124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 125 .info = wcd934x_iir_filter_info, \ 126 .get = wcd934x_get_iir_band_audio_mixer, \ 127 .put = wcd934x_put_iir_band_audio_mixer, \ 128 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 129 .iir_idx = iidx, \ 130 .band_idx = bidx, \ 131 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 132 } \ 133 } 134 135 /* Z value defined in milliohm */ 136 #define WCD934X_ZDET_VAL_32 32000 137 #define WCD934X_ZDET_VAL_400 400000 138 #define WCD934X_ZDET_VAL_1200 1200000 139 #define WCD934X_ZDET_VAL_100K 100000000 140 /* Z floating defined in ohms */ 141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 142 143 #define WCD934X_ZDET_NUM_MEASUREMENTS 900 144 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 145 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 146 /* Z value compared in milliOhm */ 147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 148 #define WCD934X_MBHC_ZDET_CONST (86 * 16384) 149 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 150 #define WCD934X_MBHC_MAX_BUTTONS (8) 151 #define WCD_MBHC_HS_V_MAX 1600 152 153 #define WCD934X_INTERPOLATOR_PATH(id) \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 192 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 193 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 194 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 196 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 197 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 198 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 201 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 202 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 203 204 #define WCD934X_INTERPOLATOR_MIX2(id) \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 206 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 207 208 #define WCD934X_SLIM_RX_AIF_PATH(id) \ 209 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 212 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 213 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 214 215 #define WCD934X_ADC_MUX(id) \ 216 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 217 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 218 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 219 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 220 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 221 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 222 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 223 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 224 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 225 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 226 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 227 {"AMIC MUX" #id, "ADC4", "ADC4"} 228 229 #define WCD934X_IIR_INP_MUX(id) \ 230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 238 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 239 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 240 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 241 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 242 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 243 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 244 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 245 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 246 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 247 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 248 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 249 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 250 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 251 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 252 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 253 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 254 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 255 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 256 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 257 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 258 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 259 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 260 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 261 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 262 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 263 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 264 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 265 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 266 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 267 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 268 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 269 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 270 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 271 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 272 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 273 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 274 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 275 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 276 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 277 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 278 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 279 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 280 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 281 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 282 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 283 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 284 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 285 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 286 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 287 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 288 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 289 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 290 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 291 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 292 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 293 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 294 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 295 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 296 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 297 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 298 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 299 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 300 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 301 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 302 303 #define WCD934X_SLIM_TX_AIF_PATH(id) \ 304 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 307 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 308 309 #define WCD934X_MAX_MICBIAS MIC_BIAS_4 310 311 enum { 312 SIDO_SOURCE_INTERNAL, 313 SIDO_SOURCE_RCO_BG, 314 }; 315 316 enum { 317 INTERP_EAR = 0, 318 INTERP_HPHL, 319 INTERP_HPHR, 320 INTERP_LO1, 321 INTERP_LO2, 322 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 323 INTERP_LO4_NA, 324 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 325 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 326 INTERP_MAX, 327 }; 328 329 enum { 330 WCD934X_RX0 = 0, 331 WCD934X_RX1, 332 WCD934X_RX2, 333 WCD934X_RX3, 334 WCD934X_RX4, 335 WCD934X_RX5, 336 WCD934X_RX6, 337 WCD934X_RX7, 338 WCD934X_RX8, 339 WCD934X_RX9, 340 WCD934X_RX10, 341 WCD934X_RX11, 342 WCD934X_RX12, 343 WCD934X_RX_MAX, 344 }; 345 346 enum { 347 WCD934X_TX0 = 0, 348 WCD934X_TX1, 349 WCD934X_TX2, 350 WCD934X_TX3, 351 WCD934X_TX4, 352 WCD934X_TX5, 353 WCD934X_TX6, 354 WCD934X_TX7, 355 WCD934X_TX8, 356 WCD934X_TX9, 357 WCD934X_TX10, 358 WCD934X_TX11, 359 WCD934X_TX12, 360 WCD934X_TX13, 361 WCD934X_TX14, 362 WCD934X_TX15, 363 WCD934X_TX_MAX, 364 }; 365 366 struct wcd934x_slim_ch { 367 u32 ch_num; 368 u16 port; 369 u16 shift; 370 struct list_head list; 371 }; 372 373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 374 WCD934X_SLIM_TX_CH(0), 375 WCD934X_SLIM_TX_CH(1), 376 WCD934X_SLIM_TX_CH(2), 377 WCD934X_SLIM_TX_CH(3), 378 WCD934X_SLIM_TX_CH(4), 379 WCD934X_SLIM_TX_CH(5), 380 WCD934X_SLIM_TX_CH(6), 381 WCD934X_SLIM_TX_CH(7), 382 WCD934X_SLIM_TX_CH(8), 383 WCD934X_SLIM_TX_CH(9), 384 WCD934X_SLIM_TX_CH(10), 385 WCD934X_SLIM_TX_CH(11), 386 WCD934X_SLIM_TX_CH(12), 387 WCD934X_SLIM_TX_CH(13), 388 WCD934X_SLIM_TX_CH(14), 389 WCD934X_SLIM_TX_CH(15), 390 }; 391 392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 393 WCD934X_SLIM_RX_CH(0), /* 16 */ 394 WCD934X_SLIM_RX_CH(1), /* 17 */ 395 WCD934X_SLIM_RX_CH(2), 396 WCD934X_SLIM_RX_CH(3), 397 WCD934X_SLIM_RX_CH(4), 398 WCD934X_SLIM_RX_CH(5), 399 WCD934X_SLIM_RX_CH(6), 400 WCD934X_SLIM_RX_CH(7), 401 WCD934X_SLIM_RX_CH(8), 402 WCD934X_SLIM_RX_CH(9), 403 WCD934X_SLIM_RX_CH(10), 404 WCD934X_SLIM_RX_CH(11), 405 WCD934X_SLIM_RX_CH(12), 406 }; 407 408 /* Codec supports 2 IIR filters */ 409 enum { 410 IIR0 = 0, 411 IIR1, 412 IIR_MAX, 413 }; 414 415 /* Each IIR has 5 Filter Stages */ 416 enum { 417 BAND1 = 0, 418 BAND2, 419 BAND3, 420 BAND4, 421 BAND5, 422 BAND_MAX, 423 }; 424 425 enum { 426 COMPANDER_1, /* HPH_L */ 427 COMPANDER_2, /* HPH_R */ 428 COMPANDER_3, /* LO1_DIFF */ 429 COMPANDER_4, /* LO2_DIFF */ 430 COMPANDER_5, /* LO3_SE - not used in Tavil */ 431 COMPANDER_6, /* LO4_SE - not used in Tavil */ 432 COMPANDER_7, /* SWR SPK CH1 */ 433 COMPANDER_8, /* SWR SPK CH2 */ 434 COMPANDER_MAX, 435 }; 436 437 enum { 438 AIF1_PB = 0, 439 AIF1_CAP, 440 AIF2_PB, 441 AIF2_CAP, 442 AIF3_PB, 443 AIF3_CAP, 444 AIF4_PB, 445 AIF4_VIFEED, 446 AIF4_MAD_TX, 447 NUM_CODEC_DAIS, 448 }; 449 450 enum { 451 INTn_1_INP_SEL_ZERO = 0, 452 INTn_1_INP_SEL_DEC0, 453 INTn_1_INP_SEL_DEC1, 454 INTn_1_INP_SEL_IIR0, 455 INTn_1_INP_SEL_IIR1, 456 INTn_1_INP_SEL_RX0, 457 INTn_1_INP_SEL_RX1, 458 INTn_1_INP_SEL_RX2, 459 INTn_1_INP_SEL_RX3, 460 INTn_1_INP_SEL_RX4, 461 INTn_1_INP_SEL_RX5, 462 INTn_1_INP_SEL_RX6, 463 INTn_1_INP_SEL_RX7, 464 }; 465 466 enum { 467 INTn_2_INP_SEL_ZERO = 0, 468 INTn_2_INP_SEL_RX0, 469 INTn_2_INP_SEL_RX1, 470 INTn_2_INP_SEL_RX2, 471 INTn_2_INP_SEL_RX3, 472 INTn_2_INP_SEL_RX4, 473 INTn_2_INP_SEL_RX5, 474 INTn_2_INP_SEL_RX6, 475 INTn_2_INP_SEL_RX7, 476 INTn_2_INP_SEL_PROXIMITY, 477 }; 478 479 enum { 480 INTERP_MAIN_PATH, 481 INTERP_MIX_PATH, 482 }; 483 484 struct interp_sample_rate { 485 int sample_rate; 486 int rate_val; 487 }; 488 489 static struct interp_sample_rate sr_val_tbl[] = { 490 {8000, 0x0}, 491 {16000, 0x1}, 492 {32000, 0x3}, 493 {48000, 0x4}, 494 {96000, 0x5}, 495 {192000, 0x6}, 496 {384000, 0x7}, 497 {44100, 0x9}, 498 {88200, 0xA}, 499 {176400, 0xB}, 500 {352800, 0xC}, 501 }; 502 503 struct wcd934x_mbhc_zdet_param { 504 u16 ldo_ctl; 505 u16 noff; 506 u16 nshift; 507 u16 btn5; 508 u16 btn6; 509 u16 btn7; 510 }; 511 512 struct wcd_slim_codec_dai_data { 513 struct list_head slim_ch_list; 514 struct slim_stream_config sconfig; 515 struct slim_stream_runtime *sruntime; 516 }; 517 518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 519 { 520 .name = "WCD9335-IFC-DEV", 521 .range_min = 0x0, 522 .range_max = 0xffff, 523 .selector_reg = 0x800, 524 .selector_mask = 0xfff, 525 .selector_shift = 0, 526 .window_start = 0x800, 527 .window_len = 0x400, 528 }, 529 }; 530 531 static struct regmap_config wcd934x_ifc_regmap_config = { 532 .reg_bits = 16, 533 .val_bits = 8, 534 .max_register = 0xffff, 535 .ranges = wcd934x_ifc_ranges, 536 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 537 }; 538 539 struct wcd934x_codec { 540 struct device *dev; 541 struct clk_hw hw; 542 struct clk *extclk; 543 struct regmap *regmap; 544 struct regmap *if_regmap; 545 struct slim_device *sdev; 546 struct slim_device *sidev; 547 struct wcd_clsh_ctrl *clsh_ctrl; 548 struct snd_soc_component *component; 549 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 550 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 551 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 552 int rate; 553 u32 version; 554 u32 hph_mode; 555 int num_rx_port; 556 int num_tx_port; 557 u32 tx_port_value[WCD934X_TX_MAX]; 558 u32 rx_port_value[WCD934X_RX_MAX]; 559 int sido_input_src; 560 int dmic_0_1_clk_cnt; 561 int dmic_2_3_clk_cnt; 562 int dmic_4_5_clk_cnt; 563 int dmic_sample_rate; 564 int comp_enabled[COMPANDER_MAX]; 565 int sysclk_users; 566 struct mutex sysclk_mutex; 567 /* mbhc module */ 568 struct wcd_mbhc *mbhc; 569 struct wcd_mbhc_config mbhc_cfg; 570 struct wcd_mbhc_intr intr_ids; 571 bool mbhc_started; 572 struct mutex micb_lock; 573 u32 micb_ref[WCD934X_MAX_MICBIAS]; 574 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 575 u32 micb1_mv; 576 u32 micb2_mv; 577 u32 micb3_mv; 578 u32 micb4_mv; 579 }; 580 581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 582 583 struct wcd_iir_filter_ctl { 584 unsigned int iir_idx; 585 unsigned int band_idx; 586 struct soc_bytes_ext bytes_ext; 587 }; 588 589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 593 594 /* Cutoff frequency for high pass filter */ 595 static const char * const cf_text[] = { 596 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 597 }; 598 599 static const char * const rx_cf_text[] = { 600 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 601 "CF_NEG_3DB_0P48HZ" 602 }; 603 604 static const char * const rx_hph_mode_mux_text[] = { 605 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 606 "Class-H Hi-Fi Low Power" 607 }; 608 609 static const char *const slim_rx_mux_text[] = { 610 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 611 }; 612 613 static const char * const rx_int0_7_mix_mux_text[] = { 614 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 615 "RX6", "RX7", "PROXIMITY" 616 }; 617 618 static const char * const rx_int_mix_mux_text[] = { 619 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 620 "RX6", "RX7" 621 }; 622 623 static const char * const rx_prim_mix_text[] = { 624 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 625 "RX3", "RX4", "RX5", "RX6", "RX7" 626 }; 627 628 static const char * const rx_sidetone_mix_text[] = { 629 "ZERO", "SRC0", "SRC1", "SRC_SUM" 630 }; 631 632 static const char * const iir_inp_mux_text[] = { 633 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 634 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 635 }; 636 637 static const char * const rx_int_dem_inp_mux_text[] = { 638 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 639 }; 640 641 static const char * const rx_int0_1_interp_mux_text[] = { 642 "ZERO", "RX INT0_1 MIX1", 643 }; 644 645 static const char * const rx_int1_1_interp_mux_text[] = { 646 "ZERO", "RX INT1_1 MIX1", 647 }; 648 649 static const char * const rx_int2_1_interp_mux_text[] = { 650 "ZERO", "RX INT2_1 MIX1", 651 }; 652 653 static const char * const rx_int3_1_interp_mux_text[] = { 654 "ZERO", "RX INT3_1 MIX1", 655 }; 656 657 static const char * const rx_int4_1_interp_mux_text[] = { 658 "ZERO", "RX INT4_1 MIX1", 659 }; 660 661 static const char * const rx_int7_1_interp_mux_text[] = { 662 "ZERO", "RX INT7_1 MIX1", 663 }; 664 665 static const char * const rx_int8_1_interp_mux_text[] = { 666 "ZERO", "RX INT8_1 MIX1", 667 }; 668 669 static const char * const rx_int0_2_interp_mux_text[] = { 670 "ZERO", "RX INT0_2 MUX", 671 }; 672 673 static const char * const rx_int1_2_interp_mux_text[] = { 674 "ZERO", "RX INT1_2 MUX", 675 }; 676 677 static const char * const rx_int2_2_interp_mux_text[] = { 678 "ZERO", "RX INT2_2 MUX", 679 }; 680 681 static const char * const rx_int3_2_interp_mux_text[] = { 682 "ZERO", "RX INT3_2 MUX", 683 }; 684 685 static const char * const rx_int4_2_interp_mux_text[] = { 686 "ZERO", "RX INT4_2 MUX", 687 }; 688 689 static const char * const rx_int7_2_interp_mux_text[] = { 690 "ZERO", "RX INT7_2 MUX", 691 }; 692 693 static const char * const rx_int8_2_interp_mux_text[] = { 694 "ZERO", "RX INT8_2 MUX", 695 }; 696 697 static const char * const dmic_mux_text[] = { 698 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 699 }; 700 701 static const char * const amic_mux_text[] = { 702 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 703 }; 704 705 static const char * const amic4_5_sel_text[] = { 706 "AMIC4", "AMIC5" 707 }; 708 709 static const char * const adc_mux_text[] = { 710 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 711 }; 712 713 static const char * const cdc_if_tx0_mux_text[] = { 714 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 715 }; 716 717 static const char * const cdc_if_tx1_mux_text[] = { 718 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 719 }; 720 721 static const char * const cdc_if_tx2_mux_text[] = { 722 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 723 }; 724 725 static const char * const cdc_if_tx3_mux_text[] = { 726 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 727 }; 728 729 static const char * const cdc_if_tx4_mux_text[] = { 730 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 731 }; 732 733 static const char * const cdc_if_tx5_mux_text[] = { 734 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 735 }; 736 737 static const char * const cdc_if_tx6_mux_text[] = { 738 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 739 }; 740 741 static const char * const cdc_if_tx7_mux_text[] = { 742 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 743 }; 744 745 static const char * const cdc_if_tx8_mux_text[] = { 746 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 747 }; 748 749 static const char * const cdc_if_tx9_mux_text[] = { 750 "ZERO", "DEC7", "DEC7_192" 751 }; 752 753 static const char * const cdc_if_tx10_mux_text[] = { 754 "ZERO", "DEC6", "DEC6_192" 755 }; 756 757 static const char * const cdc_if_tx11_mux_text[] = { 758 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 759 }; 760 761 static const char * const cdc_if_tx11_inp1_mux_text[] = { 762 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 763 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 764 }; 765 766 static const char * const cdc_if_tx13_mux_text[] = { 767 "CDC_DEC_5", "MAD_BRDCST" 768 }; 769 770 static const char * const cdc_if_tx13_inp1_mux_text[] = { 771 "ZERO", "DEC5", "DEC5_192" 772 }; 773 774 static const struct soc_enum cf_dec0_enum = 775 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 776 777 static const struct soc_enum cf_dec1_enum = 778 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 779 780 static const struct soc_enum cf_dec2_enum = 781 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 782 783 static const struct soc_enum cf_dec3_enum = 784 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 785 786 static const struct soc_enum cf_dec4_enum = 787 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 788 789 static const struct soc_enum cf_dec5_enum = 790 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 791 792 static const struct soc_enum cf_dec6_enum = 793 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 794 795 static const struct soc_enum cf_dec7_enum = 796 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 797 798 static const struct soc_enum cf_dec8_enum = 799 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 800 801 static const struct soc_enum cf_int0_1_enum = 802 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 803 804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 805 rx_cf_text); 806 807 static const struct soc_enum cf_int1_1_enum = 808 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 809 810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 811 rx_cf_text); 812 813 static const struct soc_enum cf_int2_1_enum = 814 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 815 816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 817 rx_cf_text); 818 819 static const struct soc_enum cf_int3_1_enum = 820 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 821 822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 823 rx_cf_text); 824 825 static const struct soc_enum cf_int4_1_enum = 826 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 827 828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 829 rx_cf_text); 830 831 static const struct soc_enum cf_int7_1_enum = 832 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 833 834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 835 rx_cf_text); 836 837 static const struct soc_enum cf_int8_1_enum = 838 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 839 840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 841 rx_cf_text); 842 843 static const struct soc_enum rx_hph_mode_mux_enum = 844 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 845 rx_hph_mode_mux_text); 846 847 static const struct soc_enum slim_rx_mux_enum = 848 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 849 850 static const struct soc_enum rx_int0_2_mux_chain_enum = 851 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 852 rx_int0_7_mix_mux_text); 853 854 static const struct soc_enum rx_int1_2_mux_chain_enum = 855 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 856 rx_int_mix_mux_text); 857 858 static const struct soc_enum rx_int2_2_mux_chain_enum = 859 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 860 rx_int_mix_mux_text); 861 862 static const struct soc_enum rx_int3_2_mux_chain_enum = 863 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 864 rx_int_mix_mux_text); 865 866 static const struct soc_enum rx_int4_2_mux_chain_enum = 867 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 868 rx_int_mix_mux_text); 869 870 static const struct soc_enum rx_int7_2_mux_chain_enum = 871 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 872 rx_int0_7_mix_mux_text); 873 874 static const struct soc_enum rx_int8_2_mux_chain_enum = 875 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 876 rx_int_mix_mux_text); 877 878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 879 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 880 rx_prim_mix_text); 881 882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 883 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 884 rx_prim_mix_text); 885 886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 887 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 888 rx_prim_mix_text); 889 890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 891 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 892 rx_prim_mix_text); 893 894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 895 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 896 rx_prim_mix_text); 897 898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 899 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 900 rx_prim_mix_text); 901 902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 903 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 904 rx_prim_mix_text); 905 906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 907 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 908 rx_prim_mix_text); 909 910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 911 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 912 rx_prim_mix_text); 913 914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 915 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 916 rx_prim_mix_text); 917 918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 919 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 920 rx_prim_mix_text); 921 922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 923 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 924 rx_prim_mix_text); 925 926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 927 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 928 rx_prim_mix_text); 929 930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 931 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 932 rx_prim_mix_text); 933 934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 935 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 936 rx_prim_mix_text); 937 938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 939 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 940 rx_prim_mix_text); 941 942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 943 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 944 rx_prim_mix_text); 945 946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 947 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 948 rx_prim_mix_text); 949 950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 951 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 952 rx_prim_mix_text); 953 954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 955 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 956 rx_prim_mix_text); 957 958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 959 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 960 rx_prim_mix_text); 961 962 static const struct soc_enum rx_int0_mix2_inp_mux_enum = 963 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 964 rx_sidetone_mix_text); 965 966 static const struct soc_enum rx_int1_mix2_inp_mux_enum = 967 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 968 rx_sidetone_mix_text); 969 970 static const struct soc_enum rx_int2_mix2_inp_mux_enum = 971 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 972 rx_sidetone_mix_text); 973 974 static const struct soc_enum rx_int3_mix2_inp_mux_enum = 975 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 976 rx_sidetone_mix_text); 977 978 static const struct soc_enum rx_int4_mix2_inp_mux_enum = 979 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 980 rx_sidetone_mix_text); 981 982 static const struct soc_enum rx_int7_mix2_inp_mux_enum = 983 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 984 rx_sidetone_mix_text); 985 986 static const struct soc_enum iir0_inp0_mux_enum = 987 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 988 0, 18, iir_inp_mux_text); 989 990 static const struct soc_enum iir0_inp1_mux_enum = 991 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 992 0, 18, iir_inp_mux_text); 993 994 static const struct soc_enum iir0_inp2_mux_enum = 995 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 996 0, 18, iir_inp_mux_text); 997 998 static const struct soc_enum iir0_inp3_mux_enum = 999 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 1000 0, 18, iir_inp_mux_text); 1001 1002 static const struct soc_enum iir1_inp0_mux_enum = 1003 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 1004 0, 18, iir_inp_mux_text); 1005 1006 static const struct soc_enum iir1_inp1_mux_enum = 1007 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 1008 0, 18, iir_inp_mux_text); 1009 1010 static const struct soc_enum iir1_inp2_mux_enum = 1011 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 1012 0, 18, iir_inp_mux_text); 1013 1014 static const struct soc_enum iir1_inp3_mux_enum = 1015 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 1016 0, 18, iir_inp_mux_text); 1017 1018 static const struct soc_enum rx_int0_dem_inp_mux_enum = 1019 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 1020 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1021 rx_int_dem_inp_mux_text); 1022 1023 static const struct soc_enum rx_int1_dem_inp_mux_enum = 1024 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1025 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1026 rx_int_dem_inp_mux_text); 1027 1028 static const struct soc_enum rx_int2_dem_inp_mux_enum = 1029 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1030 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1031 rx_int_dem_inp_mux_text); 1032 1033 static const struct soc_enum tx_adc_mux0_enum = 1034 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1035 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1036 static const struct soc_enum tx_adc_mux1_enum = 1037 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1038 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1039 static const struct soc_enum tx_adc_mux2_enum = 1040 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1041 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1042 static const struct soc_enum tx_adc_mux3_enum = 1043 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1044 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1045 static const struct soc_enum tx_adc_mux4_enum = 1046 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1047 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1048 static const struct soc_enum tx_adc_mux5_enum = 1049 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1050 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1051 static const struct soc_enum tx_adc_mux6_enum = 1052 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1053 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1054 static const struct soc_enum tx_adc_mux7_enum = 1055 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1056 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1057 static const struct soc_enum tx_adc_mux8_enum = 1058 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1059 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1060 1061 static const struct soc_enum rx_int0_1_interp_mux_enum = 1062 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1063 rx_int0_1_interp_mux_text); 1064 1065 static const struct soc_enum rx_int1_1_interp_mux_enum = 1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1067 rx_int1_1_interp_mux_text); 1068 1069 static const struct soc_enum rx_int2_1_interp_mux_enum = 1070 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1071 rx_int2_1_interp_mux_text); 1072 1073 static const struct soc_enum rx_int3_1_interp_mux_enum = 1074 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1075 1076 static const struct soc_enum rx_int4_1_interp_mux_enum = 1077 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1078 1079 static const struct soc_enum rx_int7_1_interp_mux_enum = 1080 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1081 1082 static const struct soc_enum rx_int8_1_interp_mux_enum = 1083 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1084 1085 static const struct soc_enum rx_int0_2_interp_mux_enum = 1086 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1087 1088 static const struct soc_enum rx_int1_2_interp_mux_enum = 1089 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1090 1091 static const struct soc_enum rx_int2_2_interp_mux_enum = 1092 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1093 1094 static const struct soc_enum rx_int3_2_interp_mux_enum = 1095 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1096 1097 static const struct soc_enum rx_int4_2_interp_mux_enum = 1098 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1099 1100 static const struct soc_enum rx_int7_2_interp_mux_enum = 1101 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1102 1103 static const struct soc_enum rx_int8_2_interp_mux_enum = 1104 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1105 1106 static const struct soc_enum tx_dmic_mux0_enum = 1107 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1108 dmic_mux_text); 1109 1110 static const struct soc_enum tx_dmic_mux1_enum = 1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1112 dmic_mux_text); 1113 1114 static const struct soc_enum tx_dmic_mux2_enum = 1115 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1116 dmic_mux_text); 1117 1118 static const struct soc_enum tx_dmic_mux3_enum = 1119 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1120 dmic_mux_text); 1121 1122 static const struct soc_enum tx_dmic_mux4_enum = 1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1124 dmic_mux_text); 1125 1126 static const struct soc_enum tx_dmic_mux5_enum = 1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1128 dmic_mux_text); 1129 1130 static const struct soc_enum tx_dmic_mux6_enum = 1131 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1132 dmic_mux_text); 1133 1134 static const struct soc_enum tx_dmic_mux7_enum = 1135 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1136 dmic_mux_text); 1137 1138 static const struct soc_enum tx_dmic_mux8_enum = 1139 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1140 dmic_mux_text); 1141 1142 static const struct soc_enum tx_amic_mux0_enum = 1143 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1144 amic_mux_text); 1145 static const struct soc_enum tx_amic_mux1_enum = 1146 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1147 amic_mux_text); 1148 static const struct soc_enum tx_amic_mux2_enum = 1149 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1150 amic_mux_text); 1151 static const struct soc_enum tx_amic_mux3_enum = 1152 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1153 amic_mux_text); 1154 static const struct soc_enum tx_amic_mux4_enum = 1155 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1156 amic_mux_text); 1157 static const struct soc_enum tx_amic_mux5_enum = 1158 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1159 amic_mux_text); 1160 static const struct soc_enum tx_amic_mux6_enum = 1161 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1162 amic_mux_text); 1163 static const struct soc_enum tx_amic_mux7_enum = 1164 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1165 amic_mux_text); 1166 static const struct soc_enum tx_amic_mux8_enum = 1167 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1168 amic_mux_text); 1169 1170 static const struct soc_enum tx_amic4_5_enum = 1171 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1172 1173 static const struct soc_enum cdc_if_tx0_mux_enum = 1174 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1175 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1176 static const struct soc_enum cdc_if_tx1_mux_enum = 1177 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1178 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1179 static const struct soc_enum cdc_if_tx2_mux_enum = 1180 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1181 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1182 static const struct soc_enum cdc_if_tx3_mux_enum = 1183 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1184 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1185 static const struct soc_enum cdc_if_tx4_mux_enum = 1186 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1187 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1188 static const struct soc_enum cdc_if_tx5_mux_enum = 1189 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1190 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1191 static const struct soc_enum cdc_if_tx6_mux_enum = 1192 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1193 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1194 static const struct soc_enum cdc_if_tx7_mux_enum = 1195 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1196 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1197 static const struct soc_enum cdc_if_tx8_mux_enum = 1198 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1199 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1200 static const struct soc_enum cdc_if_tx9_mux_enum = 1201 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1202 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1203 static const struct soc_enum cdc_if_tx10_mux_enum = 1204 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1205 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1207 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1208 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1209 cdc_if_tx11_inp1_mux_text); 1210 static const struct soc_enum cdc_if_tx11_mux_enum = 1211 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1212 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1214 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1215 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1216 cdc_if_tx13_inp1_mux_text); 1217 static const struct soc_enum cdc_if_tx13_mux_enum = 1218 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1219 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1220 1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1222 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1223 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1224 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1225 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1226 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1227 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1228 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1229 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1230 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1231 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1232 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1233 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1234 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1235 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1236 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1237 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1238 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1239 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1242 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1243 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1244 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1245 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1246 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1247 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1248 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1249 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1250 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1251 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1252 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1253 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1254 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1255 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1256 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1257 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1258 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1259 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1261 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1262 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1263 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1264 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1265 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1266 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1267 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1268 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1269 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1270 }; 1271 1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1273 { 1274 if (sido_src == wcd->sido_input_src) 1275 return 0; 1276 1277 if (sido_src == SIDO_SOURCE_INTERNAL) { 1278 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1279 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0); 1280 usleep_range(100, 110); 1281 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1282 WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0); 1283 usleep_range(100, 110); 1284 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1285 WCD934X_ANA_RCO_BG_EN_MASK, 0); 1286 usleep_range(100, 110); 1287 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1288 WCD934X_ANA_BUCK_PRE_EN1_MASK, 1289 WCD934X_ANA_BUCK_PRE_EN1_ENABLE); 1290 usleep_range(100, 110); 1291 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1292 WCD934X_ANA_BUCK_PRE_EN2_MASK, 1293 WCD934X_ANA_BUCK_PRE_EN2_ENABLE); 1294 usleep_range(100, 110); 1295 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1296 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 1297 WCD934X_ANA_BUCK_HI_ACCU_ENABLE); 1298 usleep_range(100, 110); 1299 } else if (sido_src == SIDO_SOURCE_RCO_BG) { 1300 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1301 WCD934X_ANA_RCO_BG_EN_MASK, 1302 WCD934X_ANA_RCO_BG_ENABLE); 1303 usleep_range(100, 110); 1304 } 1305 wcd->sido_input_src = sido_src; 1306 1307 return 0; 1308 } 1309 1310 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1311 { 1312 mutex_lock(&wcd->sysclk_mutex); 1313 1314 if (++wcd->sysclk_users != 1) { 1315 mutex_unlock(&wcd->sysclk_mutex); 1316 return 0; 1317 } 1318 mutex_unlock(&wcd->sysclk_mutex); 1319 1320 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1321 WCD934X_ANA_BIAS_EN_MASK, 1322 WCD934X_ANA_BIAS_EN); 1323 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1324 WCD934X_ANA_PRECHRG_EN_MASK, 1325 WCD934X_ANA_PRECHRG_EN); 1326 /* 1327 * 1ms delay is required after pre-charge is enabled 1328 * as per HW requirement 1329 */ 1330 usleep_range(1000, 1100); 1331 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1332 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1333 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1334 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1335 1336 /* 1337 * In data clock contrl register is changed 1338 * to CLK_SYS_MCLK_PRG 1339 */ 1340 1341 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1342 WCD934X_EXT_CLK_BUF_EN_MASK, 1343 WCD934X_EXT_CLK_BUF_EN); 1344 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1345 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1346 WCD934X_EXT_CLK_DIV_BY_2); 1347 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1348 WCD934X_MCLK_SRC_MASK, 1349 WCD934X_MCLK_SRC_EXT_CLK); 1350 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1351 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1352 regmap_update_bits(wcd->regmap, 1353 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1354 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1355 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1356 regmap_update_bits(wcd->regmap, 1357 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1358 WCD934X_MCLK_EN_MASK, 1359 WCD934X_MCLK_EN); 1360 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1361 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1362 /* 1363 * 10us sleep is required after clock is enabled 1364 * as per HW requirement 1365 */ 1366 usleep_range(10, 15); 1367 1368 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1369 1370 return 0; 1371 } 1372 1373 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1374 { 1375 mutex_lock(&wcd->sysclk_mutex); 1376 if (--wcd->sysclk_users != 0) { 1377 mutex_unlock(&wcd->sysclk_mutex); 1378 return 0; 1379 } 1380 mutex_unlock(&wcd->sysclk_mutex); 1381 1382 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1383 WCD934X_EXT_CLK_BUF_EN_MASK | 1384 WCD934X_MCLK_EN_MASK, 0x0); 1385 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL); 1386 1387 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1388 WCD934X_ANA_BIAS_EN_MASK, 0); 1389 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1390 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1391 1392 return 0; 1393 } 1394 1395 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1396 { 1397 int ret = 0; 1398 1399 if (enable) { 1400 ret = clk_prepare_enable(wcd->extclk); 1401 1402 if (ret) { 1403 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1404 __func__); 1405 return ret; 1406 } 1407 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1408 } else { 1409 int val; 1410 1411 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1412 &val); 1413 1414 /* Don't disable clock if soundwire using it.*/ 1415 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1416 return 0; 1417 1418 wcd934x_disable_ana_bias_and_syclk(wcd); 1419 clk_disable_unprepare(wcd->extclk); 1420 } 1421 1422 return ret; 1423 } 1424 1425 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1426 struct snd_kcontrol *kc, int event) 1427 { 1428 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1429 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1430 1431 switch (event) { 1432 case SND_SOC_DAPM_PRE_PMU: 1433 return __wcd934x_cdc_mclk_enable(wcd, true); 1434 case SND_SOC_DAPM_POST_PMD: 1435 return __wcd934x_cdc_mclk_enable(wcd, false); 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int wcd934x_get_version(struct wcd934x_codec *wcd) 1442 { 1443 int val1, val2, ver, ret; 1444 struct regmap *regmap; 1445 u16 id_minor; 1446 u32 version_mask = 0; 1447 1448 regmap = wcd->regmap; 1449 ver = 0; 1450 1451 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1452 (u8 *)&id_minor, sizeof(u16)); 1453 1454 if (ret) 1455 return ret; 1456 1457 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1458 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1459 1460 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1461 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1462 1463 switch (version_mask) { 1464 case DSD_DISABLED | SLNQ_DISABLED: 1465 if (id_minor == 0) 1466 ver = WCD_VERSION_WCD9340_1_0; 1467 else if (id_minor == 0x01) 1468 ver = WCD_VERSION_WCD9340_1_1; 1469 break; 1470 case SLNQ_DISABLED: 1471 if (id_minor == 0) 1472 ver = WCD_VERSION_WCD9341_1_0; 1473 else if (id_minor == 0x01) 1474 ver = WCD_VERSION_WCD9341_1_1; 1475 break; 1476 } 1477 1478 wcd->version = ver; 1479 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1480 1481 return 0; 1482 } 1483 1484 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1485 { 1486 int rc, val; 1487 1488 __wcd934x_cdc_mclk_enable(wcd, true); 1489 1490 regmap_update_bits(wcd->regmap, 1491 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1492 WCD934X_EFUSE_SENSE_STATE_MASK, 1493 WCD934X_EFUSE_SENSE_STATE_DEF); 1494 regmap_update_bits(wcd->regmap, 1495 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1496 WCD934X_EFUSE_SENSE_EN_MASK, 1497 WCD934X_EFUSE_SENSE_ENABLE); 1498 /* 1499 * 5ms sleep required after enabling efuse control 1500 * before checking the status. 1501 */ 1502 usleep_range(5000, 5500); 1503 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1504 1505 rc = regmap_read(wcd->regmap, 1506 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1507 if (rc || (!(val & 0x01))) 1508 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1509 __func__, val, rc); 1510 1511 __wcd934x_cdc_mclk_enable(wcd, false); 1512 } 1513 1514 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1515 { 1516 if (enable) { 1517 __wcd934x_cdc_mclk_enable(wcd, true); 1518 regmap_update_bits(wcd->regmap, 1519 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1520 WCD934X_CDC_SWR_CLK_EN_MASK, 1521 WCD934X_CDC_SWR_CLK_ENABLE); 1522 } else { 1523 regmap_update_bits(wcd->regmap, 1524 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1525 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1526 __wcd934x_cdc_mclk_enable(wcd, false); 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1533 u8 rate_val, u32 rate) 1534 { 1535 struct snd_soc_component *comp = dai->component; 1536 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1537 struct wcd934x_slim_ch *ch; 1538 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1539 int inp, j; 1540 1541 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1542 inp = ch->shift + INTn_1_INP_SEL_RX0; 1543 /* 1544 * Loop through all interpolator MUX inputs and find out 1545 * to which interpolator input, the slim rx port 1546 * is connected 1547 */ 1548 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1549 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1550 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1551 continue; 1552 1553 cfg0 = snd_soc_component_read(comp, 1554 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1555 cfg1 = snd_soc_component_read(comp, 1556 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1557 1558 inp0_sel = cfg0 & 1559 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1560 inp1_sel = (cfg0 >> 4) & 1561 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1562 inp2_sel = (cfg1 >> 4) & 1563 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1564 1565 if ((inp0_sel == inp) || (inp1_sel == inp) || 1566 (inp2_sel == inp)) { 1567 /* rate is in Hz */ 1568 /* 1569 * Ear and speaker primary path does not support 1570 * native sample rates 1571 */ 1572 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1573 j == INTERP_SPKR2) && rate == 44100) 1574 dev_err(wcd->dev, 1575 "Cannot set 44.1KHz on INT%d\n", 1576 j); 1577 else 1578 snd_soc_component_update_bits(comp, 1579 WCD934X_CDC_RX_PATH_CTL(j), 1580 WCD934X_CDC_MIX_PCM_RATE_MASK, 1581 rate_val); 1582 } 1583 } 1584 } 1585 1586 return 0; 1587 } 1588 1589 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1590 int rate_val, u32 rate) 1591 { 1592 struct snd_soc_component *component = dai->component; 1593 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1594 struct wcd934x_slim_ch *ch; 1595 int val, j; 1596 1597 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1598 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1599 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1600 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1601 continue; 1602 val = snd_soc_component_read(component, 1603 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1604 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1605 1606 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1607 /* 1608 * Ear mix path supports only 48, 96, 192, 1609 * 384KHz only 1610 */ 1611 if ((j == INTERP_EAR) && 1612 (rate_val < 0x4 || 1613 rate_val > 0x7)) { 1614 dev_err(component->dev, 1615 "Invalid rate for AIF_PB DAI(%d)\n", 1616 dai->id); 1617 return -EINVAL; 1618 } 1619 1620 snd_soc_component_update_bits(component, 1621 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1622 WCD934X_CDC_MIX_PCM_RATE_MASK, 1623 rate_val); 1624 } 1625 } 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1632 u32 sample_rate) 1633 { 1634 int rate_val = 0; 1635 int i, ret; 1636 1637 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1638 if (sample_rate == sr_val_tbl[i].sample_rate) { 1639 rate_val = sr_val_tbl[i].rate_val; 1640 break; 1641 } 1642 } 1643 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1644 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1645 return -EINVAL; 1646 } 1647 1648 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1649 sample_rate); 1650 if (ret) 1651 return ret; 1652 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1653 sample_rate); 1654 1655 return ret; 1656 } 1657 1658 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1659 u8 rate_val, u32 rate) 1660 { 1661 struct snd_soc_component *comp = dai->component; 1662 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1663 u8 shift = 0, shift_val = 0, tx_mux_sel; 1664 struct wcd934x_slim_ch *ch; 1665 int tx_port, tx_port_reg; 1666 int decimator = -1; 1667 1668 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1669 tx_port = ch->port; 1670 /* Find the SB TX MUX input - which decimator is connected */ 1671 switch (tx_port) { 1672 case 0 ... 3: 1673 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1674 shift = (tx_port << 1); 1675 shift_val = 0x03; 1676 break; 1677 case 4 ... 7: 1678 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1679 shift = ((tx_port - 4) << 1); 1680 shift_val = 0x03; 1681 break; 1682 case 8 ... 10: 1683 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1684 shift = ((tx_port - 8) << 1); 1685 shift_val = 0x03; 1686 break; 1687 case 11: 1688 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1689 shift = 0; 1690 shift_val = 0x0F; 1691 break; 1692 case 13: 1693 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1694 shift = 4; 1695 shift_val = 0x03; 1696 break; 1697 default: 1698 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1699 tx_port, dai->id); 1700 return -EINVAL; 1701 } 1702 1703 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1704 (shift_val << shift); 1705 1706 tx_mux_sel = tx_mux_sel >> shift; 1707 switch (tx_port) { 1708 case 0 ... 8: 1709 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1710 decimator = tx_port; 1711 break; 1712 case 9 ... 10: 1713 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1714 decimator = ((tx_port == 9) ? 7 : 6); 1715 break; 1716 case 11: 1717 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1718 decimator = tx_mux_sel - 1; 1719 break; 1720 case 13: 1721 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1722 decimator = 5; 1723 break; 1724 default: 1725 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1726 tx_port); 1727 return -EINVAL; 1728 } 1729 1730 snd_soc_component_update_bits(comp, 1731 WCD934X_CDC_TX_PATH_CTL(decimator), 1732 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1733 rate_val); 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1740 struct wcd_slim_codec_dai_data *dai_data, 1741 int direction) 1742 { 1743 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1744 struct slim_stream_config *cfg = &dai_data->sconfig; 1745 struct wcd934x_slim_ch *ch; 1746 u16 payload = 0; 1747 int ret, i; 1748 1749 cfg->ch_count = 0; 1750 cfg->direction = direction; 1751 cfg->port_mask = 0; 1752 1753 /* Configure slave interface device */ 1754 list_for_each_entry(ch, slim_ch_list, list) { 1755 cfg->ch_count++; 1756 payload |= 1 << ch->shift; 1757 cfg->port_mask |= BIT(ch->port); 1758 } 1759 1760 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1761 if (!cfg->chs) 1762 return -ENOMEM; 1763 1764 i = 0; 1765 list_for_each_entry(ch, slim_ch_list, list) { 1766 cfg->chs[i++] = ch->ch_num; 1767 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1768 /* write to interface device */ 1769 ret = regmap_write(wcd->if_regmap, 1770 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1771 payload); 1772 1773 if (ret < 0) 1774 goto err; 1775 1776 /* configure the slave port for water mark and enable*/ 1777 ret = regmap_write(wcd->if_regmap, 1778 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1779 WCD934X_SLIM_WATER_MARK_VAL); 1780 if (ret < 0) 1781 goto err; 1782 } else { 1783 ret = regmap_write(wcd->if_regmap, 1784 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1785 payload & 0x00FF); 1786 if (ret < 0) 1787 goto err; 1788 1789 /* ports 8,9 */ 1790 ret = regmap_write(wcd->if_regmap, 1791 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1792 (payload & 0xFF00) >> 8); 1793 if (ret < 0) 1794 goto err; 1795 1796 /* configure the slave port for water mark and enable*/ 1797 ret = regmap_write(wcd->if_regmap, 1798 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1799 WCD934X_SLIM_WATER_MARK_VAL); 1800 1801 if (ret < 0) 1802 goto err; 1803 } 1804 } 1805 1806 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1807 1808 return 0; 1809 1810 err: 1811 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1812 kfree(cfg->chs); 1813 cfg->chs = NULL; 1814 1815 return ret; 1816 } 1817 1818 static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1819 struct snd_pcm_hw_params *params, 1820 struct snd_soc_dai *dai) 1821 { 1822 struct wcd934x_codec *wcd; 1823 int ret, tx_fs_rate = 0; 1824 1825 wcd = snd_soc_component_get_drvdata(dai->component); 1826 1827 switch (substream->stream) { 1828 case SNDRV_PCM_STREAM_PLAYBACK: 1829 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1830 if (ret) { 1831 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1832 params_rate(params)); 1833 return ret; 1834 } 1835 switch (params_width(params)) { 1836 case 16 ... 24: 1837 wcd->dai[dai->id].sconfig.bps = params_width(params); 1838 break; 1839 default: 1840 dev_err(wcd->dev, "Invalid format 0x%x\n", 1841 params_width(params)); 1842 return -EINVAL; 1843 } 1844 break; 1845 1846 case SNDRV_PCM_STREAM_CAPTURE: 1847 switch (params_rate(params)) { 1848 case 8000: 1849 tx_fs_rate = 0; 1850 break; 1851 case 16000: 1852 tx_fs_rate = 1; 1853 break; 1854 case 32000: 1855 tx_fs_rate = 3; 1856 break; 1857 case 48000: 1858 tx_fs_rate = 4; 1859 break; 1860 case 96000: 1861 tx_fs_rate = 5; 1862 break; 1863 case 192000: 1864 tx_fs_rate = 6; 1865 break; 1866 case 384000: 1867 tx_fs_rate = 7; 1868 break; 1869 default: 1870 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1871 params_rate(params)); 1872 return -EINVAL; 1873 1874 } 1875 1876 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1877 params_rate(params)); 1878 if (ret < 0) { 1879 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1880 return ret; 1881 } 1882 switch (params_width(params)) { 1883 case 16 ... 32: 1884 wcd->dai[dai->id].sconfig.bps = params_width(params); 1885 break; 1886 default: 1887 dev_err(wcd->dev, "Invalid format 0x%x\n", 1888 params_width(params)); 1889 return -EINVAL; 1890 } 1891 break; 1892 default: 1893 dev_err(wcd->dev, "Invalid stream type %d\n", 1894 substream->stream); 1895 return -EINVAL; 1896 } 1897 1898 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1899 wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1900 1901 return 0; 1902 } 1903 1904 static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1905 struct snd_soc_dai *dai) 1906 { 1907 struct wcd_slim_codec_dai_data *dai_data; 1908 struct wcd934x_codec *wcd; 1909 1910 wcd = snd_soc_component_get_drvdata(dai->component); 1911 1912 dai_data = &wcd->dai[dai->id]; 1913 1914 kfree(dai_data->sconfig.chs); 1915 1916 return 0; 1917 } 1918 1919 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1920 struct snd_soc_dai *dai) 1921 { 1922 struct wcd_slim_codec_dai_data *dai_data; 1923 struct wcd934x_codec *wcd; 1924 struct slim_stream_config *cfg; 1925 1926 wcd = snd_soc_component_get_drvdata(dai->component); 1927 1928 dai_data = &wcd->dai[dai->id]; 1929 1930 switch (cmd) { 1931 case SNDRV_PCM_TRIGGER_START: 1932 case SNDRV_PCM_TRIGGER_RESUME: 1933 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1934 cfg = &dai_data->sconfig; 1935 slim_stream_prepare(dai_data->sruntime, cfg); 1936 slim_stream_enable(dai_data->sruntime); 1937 break; 1938 case SNDRV_PCM_TRIGGER_STOP: 1939 case SNDRV_PCM_TRIGGER_SUSPEND: 1940 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1941 slim_stream_unprepare(dai_data->sruntime); 1942 slim_stream_disable(dai_data->sruntime); 1943 break; 1944 default: 1945 break; 1946 } 1947 1948 return 0; 1949 } 1950 1951 static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1952 unsigned int tx_num, unsigned int *tx_slot, 1953 unsigned int rx_num, unsigned int *rx_slot) 1954 { 1955 struct wcd934x_codec *wcd; 1956 int i; 1957 1958 wcd = snd_soc_component_get_drvdata(dai->component); 1959 1960 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1961 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1962 tx_num, rx_num); 1963 return -EINVAL; 1964 } 1965 1966 if (!tx_slot || !rx_slot) { 1967 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1968 tx_slot, rx_slot); 1969 return -EINVAL; 1970 } 1971 1972 wcd->num_rx_port = rx_num; 1973 for (i = 0; i < rx_num; i++) { 1974 wcd->rx_chs[i].ch_num = rx_slot[i]; 1975 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1976 } 1977 1978 wcd->num_tx_port = tx_num; 1979 for (i = 0; i < tx_num; i++) { 1980 wcd->tx_chs[i].ch_num = tx_slot[i]; 1981 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1982 } 1983 1984 return 0; 1985 } 1986 1987 static int wcd934x_get_channel_map(struct snd_soc_dai *dai, 1988 unsigned int *tx_num, unsigned int *tx_slot, 1989 unsigned int *rx_num, unsigned int *rx_slot) 1990 { 1991 struct wcd934x_slim_ch *ch; 1992 struct wcd934x_codec *wcd; 1993 int i = 0; 1994 1995 wcd = snd_soc_component_get_drvdata(dai->component); 1996 1997 switch (dai->id) { 1998 case AIF1_PB: 1999 case AIF2_PB: 2000 case AIF3_PB: 2001 case AIF4_PB: 2002 if (!rx_slot || !rx_num) { 2003 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2004 rx_slot, rx_num); 2005 return -EINVAL; 2006 } 2007 2008 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2009 rx_slot[i++] = ch->ch_num; 2010 2011 *rx_num = i; 2012 break; 2013 case AIF1_CAP: 2014 case AIF2_CAP: 2015 case AIF3_CAP: 2016 if (!tx_slot || !tx_num) { 2017 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2018 tx_slot, tx_num); 2019 return -EINVAL; 2020 } 2021 2022 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2023 tx_slot[i++] = ch->ch_num; 2024 2025 *tx_num = i; 2026 break; 2027 default: 2028 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2029 break; 2030 } 2031 2032 return 0; 2033 } 2034 2035 static const struct snd_soc_dai_ops wcd934x_dai_ops = { 2036 .hw_params = wcd934x_hw_params, 2037 .hw_free = wcd934x_hw_free, 2038 .trigger = wcd934x_trigger, 2039 .set_channel_map = wcd934x_set_channel_map, 2040 .get_channel_map = wcd934x_get_channel_map, 2041 }; 2042 2043 static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 2044 [0] = { 2045 .name = "wcd934x_rx1", 2046 .id = AIF1_PB, 2047 .playback = { 2048 .stream_name = "AIF1 Playback", 2049 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2050 .formats = WCD934X_FORMATS_S16_S24_LE, 2051 .rate_max = 192000, 2052 .rate_min = 8000, 2053 .channels_min = 1, 2054 .channels_max = 2, 2055 }, 2056 .ops = &wcd934x_dai_ops, 2057 }, 2058 [1] = { 2059 .name = "wcd934x_tx1", 2060 .id = AIF1_CAP, 2061 .capture = { 2062 .stream_name = "AIF1 Capture", 2063 .rates = WCD934X_RATES_MASK, 2064 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2065 .rate_min = 8000, 2066 .rate_max = 192000, 2067 .channels_min = 1, 2068 .channels_max = 4, 2069 }, 2070 .ops = &wcd934x_dai_ops, 2071 }, 2072 [2] = { 2073 .name = "wcd934x_rx2", 2074 .id = AIF2_PB, 2075 .playback = { 2076 .stream_name = "AIF2 Playback", 2077 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2078 .formats = WCD934X_FORMATS_S16_S24_LE, 2079 .rate_min = 8000, 2080 .rate_max = 192000, 2081 .channels_min = 1, 2082 .channels_max = 2, 2083 }, 2084 .ops = &wcd934x_dai_ops, 2085 }, 2086 [3] = { 2087 .name = "wcd934x_tx2", 2088 .id = AIF2_CAP, 2089 .capture = { 2090 .stream_name = "AIF2 Capture", 2091 .rates = WCD934X_RATES_MASK, 2092 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2093 .rate_min = 8000, 2094 .rate_max = 192000, 2095 .channels_min = 1, 2096 .channels_max = 4, 2097 }, 2098 .ops = &wcd934x_dai_ops, 2099 }, 2100 [4] = { 2101 .name = "wcd934x_rx3", 2102 .id = AIF3_PB, 2103 .playback = { 2104 .stream_name = "AIF3 Playback", 2105 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2106 .formats = WCD934X_FORMATS_S16_S24_LE, 2107 .rate_min = 8000, 2108 .rate_max = 192000, 2109 .channels_min = 1, 2110 .channels_max = 2, 2111 }, 2112 .ops = &wcd934x_dai_ops, 2113 }, 2114 [5] = { 2115 .name = "wcd934x_tx3", 2116 .id = AIF3_CAP, 2117 .capture = { 2118 .stream_name = "AIF3 Capture", 2119 .rates = WCD934X_RATES_MASK, 2120 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2121 .rate_min = 8000, 2122 .rate_max = 192000, 2123 .channels_min = 1, 2124 .channels_max = 4, 2125 }, 2126 .ops = &wcd934x_dai_ops, 2127 }, 2128 [6] = { 2129 .name = "wcd934x_rx4", 2130 .id = AIF4_PB, 2131 .playback = { 2132 .stream_name = "AIF4 Playback", 2133 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2134 .formats = WCD934X_FORMATS_S16_S24_LE, 2135 .rate_min = 8000, 2136 .rate_max = 192000, 2137 .channels_min = 1, 2138 .channels_max = 2, 2139 }, 2140 .ops = &wcd934x_dai_ops, 2141 }, 2142 }; 2143 2144 static int swclk_gate_enable(struct clk_hw *hw) 2145 { 2146 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2147 } 2148 2149 static void swclk_gate_disable(struct clk_hw *hw) 2150 { 2151 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2152 } 2153 2154 static int swclk_gate_is_enabled(struct clk_hw *hw) 2155 { 2156 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2157 int ret, val; 2158 2159 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2160 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2161 2162 return ret; 2163 } 2164 2165 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2166 unsigned long parent_rate) 2167 { 2168 return parent_rate / 2; 2169 } 2170 2171 static const struct clk_ops swclk_gate_ops = { 2172 .prepare = swclk_gate_enable, 2173 .unprepare = swclk_gate_disable, 2174 .is_enabled = swclk_gate_is_enabled, 2175 .recalc_rate = swclk_recalc_rate, 2176 2177 }; 2178 2179 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2180 { 2181 struct clk *parent = wcd->extclk; 2182 struct device *dev = wcd->dev; 2183 struct device_node *np = dev->parent->of_node; 2184 const char *parent_clk_name = NULL; 2185 const char *clk_name = "mclk"; 2186 struct clk_hw *hw; 2187 struct clk_init_data init; 2188 int ret; 2189 2190 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2191 return NULL; 2192 2193 parent_clk_name = __clk_get_name(parent); 2194 2195 of_property_read_string(np, "clock-output-names", &clk_name); 2196 2197 init.name = clk_name; 2198 init.ops = &swclk_gate_ops; 2199 init.flags = 0; 2200 init.parent_names = &parent_clk_name; 2201 init.num_parents = 1; 2202 wcd->hw.init = &init; 2203 2204 hw = &wcd->hw; 2205 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2206 if (ret) 2207 return ERR_PTR(ret); 2208 2209 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2210 if (ret) 2211 return ERR_PTR(ret); 2212 2213 return NULL; 2214 } 2215 2216 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias, 2217 u32 *micb_mv) 2218 { 2219 int mv; 2220 2221 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) { 2222 dev_err(dev, "%s value not found, using default\n", micbias); 2223 mv = WCD934X_DEF_MICBIAS_MV; 2224 } else { 2225 /* convert it to milli volts */ 2226 mv = mv/1000; 2227 } 2228 2229 if (mv < 1000 || mv > 2850) { 2230 dev_err(dev, "%s value not in valid range, using default\n", 2231 micbias); 2232 mv = WCD934X_DEF_MICBIAS_MV; 2233 } 2234 2235 *micb_mv = mv; 2236 2237 return (mv - 1000) / 50; 2238 } 2239 2240 static int wcd934x_init_dmic(struct snd_soc_component *comp) 2241 { 2242 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2243 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2244 u32 def_dmic_rate, dmic_clk_drv; 2245 2246 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev, 2247 "qcom,micbias1-microvolt", 2248 &wcd->micb1_mv); 2249 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev, 2250 "qcom,micbias2-microvolt", 2251 &wcd->micb2_mv); 2252 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev, 2253 "qcom,micbias3-microvolt", 2254 &wcd->micb3_mv); 2255 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev, 2256 "qcom,micbias4-microvolt", 2257 &wcd->micb4_mv); 2258 2259 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2260 WCD934X_MICB_VAL_MASK, vout_ctl_1); 2261 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2262 WCD934X_MICB_VAL_MASK, vout_ctl_2); 2263 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2264 WCD934X_MICB_VAL_MASK, vout_ctl_3); 2265 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2266 WCD934X_MICB_VAL_MASK, vout_ctl_4); 2267 2268 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2269 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2270 else 2271 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2272 2273 wcd->dmic_sample_rate = def_dmic_rate; 2274 2275 dmic_clk_drv = 0; 2276 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2277 0x0C, dmic_clk_drv << 2); 2278 2279 return 0; 2280 } 2281 2282 static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2283 { 2284 struct regmap *rm = wcd->regmap; 2285 2286 /* set SPKR rate to FS_2P4_3P072 */ 2287 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2288 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2289 2290 /* Take DMICs out of reset */ 2291 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2292 } 2293 2294 static int wcd934x_comp_init(struct snd_soc_component *component) 2295 { 2296 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2297 2298 wcd934x_hw_init(wcd); 2299 wcd934x_enable_efuse_sensing(wcd); 2300 wcd934x_get_version(wcd); 2301 2302 return 0; 2303 } 2304 2305 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2306 { 2307 struct wcd934x_codec *wcd = data; 2308 unsigned long status = 0; 2309 int i, j, port_id; 2310 unsigned int val, int_val = 0; 2311 irqreturn_t ret = IRQ_NONE; 2312 bool tx; 2313 unsigned short reg = 0; 2314 2315 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2316 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2317 regmap_read(wcd->if_regmap, i, &val); 2318 status |= ((u32)val << (8 * j)); 2319 } 2320 2321 for_each_set_bit(j, &status, 32) { 2322 tx = false; 2323 port_id = j; 2324 2325 if (j >= 16) { 2326 tx = true; 2327 port_id = j - 16; 2328 } 2329 2330 regmap_read(wcd->if_regmap, 2331 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2332 if (val) { 2333 if (!tx) 2334 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2335 (port_id / 8); 2336 else 2337 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2338 (port_id / 8); 2339 regmap_read(wcd->if_regmap, reg, &int_val); 2340 } 2341 2342 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2343 dev_err_ratelimited(wcd->dev, 2344 "overflow error on %s port %d, value %x\n", 2345 (tx ? "TX" : "RX"), port_id, val); 2346 2347 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2348 dev_err_ratelimited(wcd->dev, 2349 "underflow error on %s port %d, value %x\n", 2350 (tx ? "TX" : "RX"), port_id, val); 2351 2352 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2353 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2354 if (!tx) 2355 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2356 (port_id / 8); 2357 else 2358 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2359 (port_id / 8); 2360 regmap_read( 2361 wcd->if_regmap, reg, &int_val); 2362 if (int_val & (1 << (port_id % 8))) { 2363 int_val = int_val ^ (1 << (port_id % 8)); 2364 regmap_write(wcd->if_regmap, 2365 reg, int_val); 2366 } 2367 } 2368 2369 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2370 dev_err_ratelimited(wcd->dev, 2371 "Port Closed %s port %d, value %x\n", 2372 (tx ? "TX" : "RX"), port_id, val); 2373 2374 regmap_write(wcd->if_regmap, 2375 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2376 BIT(j % 8)); 2377 ret = IRQ_HANDLED; 2378 } 2379 2380 return ret; 2381 } 2382 2383 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2384 bool enable) 2385 { 2386 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2387 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2388 } 2389 2390 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2391 bool enable) 2392 { 2393 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2394 WCD934X_ANA_MBHC_BIAS_EN, enable); 2395 } 2396 2397 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2398 int *btn_low, int *btn_high, 2399 int num_btn, bool is_micbias) 2400 { 2401 int i, vth; 2402 2403 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2404 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2405 __func__, num_btn); 2406 return; 2407 } 2408 2409 for (i = 0; i < num_btn; i++) { 2410 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2411 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2412 WCD934X_MBHC_BTN_VTH_MASK, vth); 2413 } 2414 } 2415 2416 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2417 { 2418 u8 val; 2419 2420 if (micb_num == MIC_BIAS_2) { 2421 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2422 WCD934X_ANA_MICB2_ENABLE_MASK); 2423 if (val == WCD934X_MICB_ENABLE) 2424 return true; 2425 } 2426 return false; 2427 } 2428 2429 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2430 enum mbhc_hs_pullup_iref pull_up_cur) 2431 { 2432 /* Default pull up current to 2uA */ 2433 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2434 pull_up_cur == I_DEFAULT) 2435 pull_up_cur = I_2P0_UA; 2436 2437 2438 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2439 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2440 } 2441 2442 static int wcd934x_micbias_control(struct snd_soc_component *component, 2443 int micb_num, int req, bool is_dapm) 2444 { 2445 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2446 int micb_index = micb_num - 1; 2447 u16 micb_reg; 2448 2449 switch (micb_num) { 2450 case MIC_BIAS_1: 2451 micb_reg = WCD934X_ANA_MICB1; 2452 break; 2453 case MIC_BIAS_2: 2454 micb_reg = WCD934X_ANA_MICB2; 2455 break; 2456 case MIC_BIAS_3: 2457 micb_reg = WCD934X_ANA_MICB3; 2458 break; 2459 case MIC_BIAS_4: 2460 micb_reg = WCD934X_ANA_MICB4; 2461 break; 2462 default: 2463 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2464 __func__, micb_num); 2465 return -EINVAL; 2466 } 2467 mutex_lock(&wcd934x->micb_lock); 2468 2469 switch (req) { 2470 case MICB_PULLUP_ENABLE: 2471 wcd934x->pullup_ref[micb_index]++; 2472 if ((wcd934x->pullup_ref[micb_index] == 1) && 2473 (wcd934x->micb_ref[micb_index] == 0)) 2474 snd_soc_component_write_field(component, micb_reg, 2475 WCD934X_ANA_MICB_EN_MASK, 2476 WCD934X_MICB_PULL_UP); 2477 break; 2478 case MICB_PULLUP_DISABLE: 2479 if (wcd934x->pullup_ref[micb_index] > 0) 2480 wcd934x->pullup_ref[micb_index]--; 2481 2482 if ((wcd934x->pullup_ref[micb_index] == 0) && 2483 (wcd934x->micb_ref[micb_index] == 0)) 2484 snd_soc_component_write_field(component, micb_reg, 2485 WCD934X_ANA_MICB_EN_MASK, 0); 2486 break; 2487 case MICB_ENABLE: 2488 wcd934x->micb_ref[micb_index]++; 2489 if (wcd934x->micb_ref[micb_index] == 1) { 2490 snd_soc_component_write_field(component, micb_reg, 2491 WCD934X_ANA_MICB_EN_MASK, 2492 WCD934X_MICB_ENABLE); 2493 if (micb_num == MIC_BIAS_2) 2494 wcd_mbhc_event_notify(wcd934x->mbhc, 2495 WCD_EVENT_POST_MICBIAS_2_ON); 2496 } 2497 2498 if (micb_num == MIC_BIAS_2 && is_dapm) 2499 wcd_mbhc_event_notify(wcd934x->mbhc, 2500 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2501 break; 2502 case MICB_DISABLE: 2503 if (wcd934x->micb_ref[micb_index] > 0) 2504 wcd934x->micb_ref[micb_index]--; 2505 2506 if ((wcd934x->micb_ref[micb_index] == 0) && 2507 (wcd934x->pullup_ref[micb_index] > 0)) 2508 snd_soc_component_write_field(component, micb_reg, 2509 WCD934X_ANA_MICB_EN_MASK, 2510 WCD934X_MICB_PULL_UP); 2511 else if ((wcd934x->micb_ref[micb_index] == 0) && 2512 (wcd934x->pullup_ref[micb_index] == 0)) { 2513 if (micb_num == MIC_BIAS_2) 2514 wcd_mbhc_event_notify(wcd934x->mbhc, 2515 WCD_EVENT_PRE_MICBIAS_2_OFF); 2516 2517 snd_soc_component_write_field(component, micb_reg, 2518 WCD934X_ANA_MICB_EN_MASK, 0); 2519 if (micb_num == MIC_BIAS_2) 2520 wcd_mbhc_event_notify(wcd934x->mbhc, 2521 WCD_EVENT_POST_MICBIAS_2_OFF); 2522 } 2523 if (is_dapm && micb_num == MIC_BIAS_2) 2524 wcd_mbhc_event_notify(wcd934x->mbhc, 2525 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2526 break; 2527 } 2528 2529 mutex_unlock(&wcd934x->micb_lock); 2530 2531 return 0; 2532 } 2533 2534 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2535 int micb_num, int req) 2536 { 2537 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2538 int ret; 2539 2540 if (req == MICB_ENABLE) 2541 __wcd934x_cdc_mclk_enable(wcd, true); 2542 2543 ret = wcd934x_micbias_control(component, micb_num, req, false); 2544 2545 if (req == MICB_DISABLE) 2546 __wcd934x_cdc_mclk_enable(wcd, false); 2547 2548 return ret; 2549 } 2550 2551 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2552 bool enable) 2553 { 2554 if (enable) { 2555 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2556 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2557 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2558 WCD934X_RAMP_EN_MASK, 1); 2559 } else { 2560 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2561 WCD934X_RAMP_EN_MASK, 0); 2562 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2563 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2564 } 2565 } 2566 2567 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv) 2568 { 2569 /* min micbias voltage is 1V and maximum is 2.85V */ 2570 if (micb_mv < 1000 || micb_mv > 2850) 2571 return -EINVAL; 2572 2573 return (micb_mv - 1000) / 50; 2574 } 2575 2576 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2577 int req_volt, int micb_num) 2578 { 2579 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2580 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2581 2582 switch (micb_num) { 2583 case MIC_BIAS_1: 2584 micb_reg = WCD934X_ANA_MICB1; 2585 break; 2586 case MIC_BIAS_2: 2587 micb_reg = WCD934X_ANA_MICB2; 2588 break; 2589 case MIC_BIAS_3: 2590 micb_reg = WCD934X_ANA_MICB3; 2591 break; 2592 case MIC_BIAS_4: 2593 micb_reg = WCD934X_ANA_MICB4; 2594 break; 2595 default: 2596 return -EINVAL; 2597 } 2598 mutex_lock(&wcd934x->micb_lock); 2599 /* 2600 * If requested micbias voltage is same as current micbias 2601 * voltage, then just return. Otherwise, adjust voltage as 2602 * per requested value. If micbias is already enabled, then 2603 * to avoid slow micbias ramp-up or down enable pull-up 2604 * momentarily, change the micbias value and then re-enable 2605 * micbias. 2606 */ 2607 micb_en = snd_soc_component_read_field(component, micb_reg, 2608 WCD934X_ANA_MICB_EN_MASK); 2609 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2610 WCD934X_MICB_VAL_MASK); 2611 2612 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt); 2613 if (req_vout_ctl < 0) { 2614 ret = -EINVAL; 2615 goto exit; 2616 } 2617 2618 if (cur_vout_ctl == req_vout_ctl) { 2619 ret = 0; 2620 goto exit; 2621 } 2622 2623 if (micb_en == WCD934X_MICB_ENABLE) 2624 snd_soc_component_write_field(component, micb_reg, 2625 WCD934X_ANA_MICB_EN_MASK, 2626 WCD934X_MICB_PULL_UP); 2627 2628 snd_soc_component_write_field(component, micb_reg, 2629 WCD934X_MICB_VAL_MASK, 2630 req_vout_ctl); 2631 2632 if (micb_en == WCD934X_MICB_ENABLE) { 2633 snd_soc_component_write_field(component, micb_reg, 2634 WCD934X_ANA_MICB_EN_MASK, 2635 WCD934X_MICB_ENABLE); 2636 /* 2637 * Add 2ms delay as per HW requirement after enabling 2638 * micbias 2639 */ 2640 usleep_range(2000, 2100); 2641 } 2642 exit: 2643 mutex_unlock(&wcd934x->micb_lock); 2644 return ret; 2645 } 2646 2647 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2648 int micb_num, bool req_en) 2649 { 2650 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2651 int rc, micb_mv; 2652 2653 if (micb_num != MIC_BIAS_2) 2654 return -EINVAL; 2655 /* 2656 * If device tree micbias level is already above the minimum 2657 * voltage needed to detect threshold microphone, then do 2658 * not change the micbias, just return. 2659 */ 2660 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2661 return 0; 2662 2663 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv; 2664 2665 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2666 2667 return rc; 2668 } 2669 2670 static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2671 s16 *d1_a, u16 noff, 2672 int32_t *zdet) 2673 { 2674 int i; 2675 int val, val1; 2676 s16 c1; 2677 s32 x1, d1; 2678 int32_t denom; 2679 int minCode_param[] = { 2680 3277, 1639, 820, 410, 205, 103, 52, 26 2681 }; 2682 2683 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2684 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2685 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2686 if (val & 0x80) 2687 break; 2688 } 2689 val = val << 0x8; 2690 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2691 val |= val1; 2692 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2693 x1 = WCD934X_MBHC_GET_X1(val); 2694 c1 = WCD934X_MBHC_GET_C1(val); 2695 /* If ramp is not complete, give additional 5ms */ 2696 if ((c1 < 2) && x1) 2697 usleep_range(5000, 5050); 2698 2699 if (!c1 || !x1) { 2700 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2701 __func__, c1, x1); 2702 goto ramp_down; 2703 } 2704 d1 = d1_a[c1]; 2705 denom = (x1 * d1) - (1 << (14 - noff)); 2706 if (denom > 0) 2707 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2708 else if (x1 < minCode_param[noff]) 2709 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2710 2711 dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2712 __func__, d1, c1, x1, *zdet); 2713 ramp_down: 2714 i = 0; 2715 2716 while (x1) { 2717 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2718 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2719 val = val << 0x08; 2720 val |= val1; 2721 x1 = WCD934X_MBHC_GET_X1(val); 2722 i++; 2723 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2724 break; 2725 } 2726 } 2727 2728 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2729 struct wcd934x_mbhc_zdet_param *zdet_param, 2730 int32_t *zl, int32_t *zr, s16 *d1_a) 2731 { 2732 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2733 int32_t zdet = 0; 2734 2735 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2736 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2737 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2738 WCD934X_VTH_MASK, zdet_param->btn5); 2739 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2740 WCD934X_VTH_MASK, zdet_param->btn6); 2741 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2742 WCD934X_VTH_MASK, zdet_param->btn7); 2743 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2744 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2745 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2746 0x0F, zdet_param->nshift); 2747 2748 if (!zl) 2749 goto z_right; 2750 /* Start impedance measurement for HPH_L */ 2751 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2752 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2753 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2754 2755 *zl = zdet; 2756 2757 z_right: 2758 if (!zr) 2759 return; 2760 /* Start impedance measurement for HPH_R */ 2761 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2762 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2763 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2764 2765 *zr = zdet; 2766 } 2767 2768 static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2769 int32_t *z_val, int flag_l_r) 2770 { 2771 s16 q1; 2772 int q1_cal; 2773 2774 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2775 q1 = snd_soc_component_read(component, 2776 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2777 else 2778 q1 = snd_soc_component_read(component, 2779 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2780 if (q1 & 0x80) 2781 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2782 else 2783 q1_cal = (10000 + (q1 * 25)); 2784 if (q1_cal > 0) 2785 *z_val = ((*z_val) * 10000) / q1_cal; 2786 } 2787 2788 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2789 uint32_t *zl, uint32_t *zr) 2790 { 2791 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2792 s16 reg0, reg1, reg2, reg3, reg4; 2793 int32_t z1L, z1R, z1Ls; 2794 int zMono, z_diff1, z_diff2; 2795 bool is_fsm_disable = false; 2796 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2797 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2798 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2799 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2800 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2801 }; 2802 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2803 s16 d1_a[][4] = { 2804 {0, 30, 90, 30}, 2805 {0, 30, 30, 5}, 2806 {0, 30, 30, 5}, 2807 {0, 30, 30, 5}, 2808 }; 2809 s16 *d1 = NULL; 2810 2811 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2812 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2813 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2814 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2815 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2816 2817 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2818 is_fsm_disable = true; 2819 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2820 } 2821 2822 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2823 if (wcd934x->mbhc_cfg.hphl_swh) 2824 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2825 2826 /* Turn off 100k pull down on HPHL */ 2827 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2828 2829 /* First get impedance on Left */ 2830 d1 = d1_a[1]; 2831 zdet_param_ptr = &zdet_param[1]; 2832 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2833 2834 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2835 goto left_ch_impedance; 2836 2837 /* Second ramp for left ch */ 2838 if (z1L < WCD934X_ZDET_VAL_32) { 2839 zdet_param_ptr = &zdet_param[0]; 2840 d1 = d1_a[0]; 2841 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2842 (z1L <= WCD934X_ZDET_VAL_1200)) { 2843 zdet_param_ptr = &zdet_param[2]; 2844 d1 = d1_a[2]; 2845 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2846 zdet_param_ptr = &zdet_param[3]; 2847 d1 = d1_a[3]; 2848 } 2849 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2850 2851 left_ch_impedance: 2852 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2853 (z1L > WCD934X_ZDET_VAL_100K)) { 2854 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2855 zdet_param_ptr = &zdet_param[1]; 2856 d1 = d1_a[1]; 2857 } else { 2858 *zl = z1L/1000; 2859 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2860 } 2861 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2862 __func__, *zl); 2863 2864 /* Start of right impedance ramp and calculation */ 2865 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2866 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2867 if (((z1R > WCD934X_ZDET_VAL_1200) && 2868 (zdet_param_ptr->noff == 0x6)) || 2869 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2870 goto right_ch_impedance; 2871 /* Second ramp for right ch */ 2872 if (z1R < WCD934X_ZDET_VAL_32) { 2873 zdet_param_ptr = &zdet_param[0]; 2874 d1 = d1_a[0]; 2875 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2876 (z1R <= WCD934X_ZDET_VAL_1200)) { 2877 zdet_param_ptr = &zdet_param[2]; 2878 d1 = d1_a[2]; 2879 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2880 zdet_param_ptr = &zdet_param[3]; 2881 d1 = d1_a[3]; 2882 } 2883 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2884 } 2885 right_ch_impedance: 2886 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2887 (z1R > WCD934X_ZDET_VAL_100K)) { 2888 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2889 } else { 2890 *zr = z1R/1000; 2891 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2892 } 2893 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2894 __func__, *zr); 2895 2896 /* Mono/stereo detection */ 2897 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2898 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2899 dev_dbg(component->dev, 2900 "%s: plug type is invalid or extension cable\n", 2901 __func__); 2902 goto zdet_complete; 2903 } 2904 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2905 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2906 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2907 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2908 dev_dbg(component->dev, 2909 "%s: Mono plug type with one ch floating or shorted to GND\n", 2910 __func__); 2911 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2912 goto zdet_complete; 2913 } 2914 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2915 WCD934X_HPHPA_GND_OVR_MASK, 1); 2916 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2917 WCD934X_HPHPA_GND_R_MASK, 1); 2918 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2919 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2920 else 2921 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2922 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2923 WCD934X_HPHPA_GND_R_MASK, 0); 2924 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2925 WCD934X_HPHPA_GND_OVR_MASK, 0); 2926 z1Ls /= 1000; 2927 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2928 /* Parallel of left Z and 9 ohm pull down resistor */ 2929 zMono = ((*zl) * 9) / ((*zl) + 9); 2930 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2931 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2932 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2933 dev_err(component->dev, "%s: stereo plug type detected\n", 2934 __func__); 2935 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2936 } else { 2937 dev_err(component->dev, "%s: MONO plug type detected\n", 2938 __func__); 2939 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2940 } 2941 2942 zdet_complete: 2943 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2944 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2945 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2946 /* Turn on 100k pull down on HPHL */ 2947 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2948 2949 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2950 if (wcd934x->mbhc_cfg.hphl_swh) 2951 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2952 2953 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2954 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2955 if (is_fsm_disable) 2956 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2957 } 2958 2959 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2960 bool enable) 2961 { 2962 if (enable) { 2963 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2964 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2965 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2966 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2967 } else { 2968 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2969 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2970 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2971 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2972 } 2973 } 2974 2975 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2976 bool enable) 2977 { 2978 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2979 WCD934X_HPHPA_GND_R_MASK, enable); 2980 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2981 WCD934X_HPHPA_GND_L_MASK, enable); 2982 } 2983 2984 static const struct wcd_mbhc_cb mbhc_cb = { 2985 .clk_setup = wcd934x_mbhc_clk_setup, 2986 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2987 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2988 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2989 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2990 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2991 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2992 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2993 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2994 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2995 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2996 }; 2997 2998 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2999 struct snd_ctl_elem_value *ucontrol) 3000 { 3001 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3002 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3003 3004 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 3005 3006 return 0; 3007 } 3008 3009 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 3010 struct snd_ctl_elem_value *ucontrol) 3011 { 3012 uint32_t zl, zr; 3013 bool hphr; 3014 struct soc_mixer_control *mc; 3015 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3016 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3017 3018 mc = (struct soc_mixer_control *)(kcontrol->private_value); 3019 hphr = mc->shift; 3020 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 3021 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 3022 ucontrol->value.integer.value[0] = hphr ? zr : zl; 3023 3024 return 0; 3025 } 3026 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3027 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 3028 wcd934x_get_hph_type, NULL), 3029 }; 3030 3031 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3032 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 3033 wcd934x_hph_impedance_get, NULL), 3034 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 3035 wcd934x_hph_impedance_get, NULL), 3036 }; 3037 3038 static int wcd934x_mbhc_init(struct snd_soc_component *component) 3039 { 3040 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 3041 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3042 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 3043 3044 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 3045 WCD934X_IRQ_MBHC_SW_DET); 3046 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 3047 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 3048 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 3049 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 3050 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 3051 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3052 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 3053 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 3054 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 3055 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 3056 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 3057 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 3058 3059 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3060 if (IS_ERR(wcd->mbhc)) { 3061 wcd->mbhc = NULL; 3062 return -EINVAL; 3063 } 3064 3065 snd_soc_add_component_controls(component, impedance_detect_controls, 3066 ARRAY_SIZE(impedance_detect_controls)); 3067 snd_soc_add_component_controls(component, hph_type_detect_controls, 3068 ARRAY_SIZE(hph_type_detect_controls)); 3069 3070 return 0; 3071 } 3072 static int wcd934x_comp_probe(struct snd_soc_component *component) 3073 { 3074 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3075 int i; 3076 3077 snd_soc_component_init_regmap(component, wcd->regmap); 3078 wcd->component = component; 3079 3080 /* Class-H Init*/ 3081 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3082 if (IS_ERR(wcd->clsh_ctrl)) 3083 return PTR_ERR(wcd->clsh_ctrl); 3084 3085 /* Default HPH Mode to Class-H Low HiFi */ 3086 wcd->hph_mode = CLS_H_LOHIFI; 3087 3088 wcd934x_comp_init(component); 3089 3090 for (i = 0; i < NUM_CODEC_DAIS; i++) 3091 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3092 3093 wcd934x_init_dmic(component); 3094 3095 if (wcd934x_mbhc_init(component)) 3096 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3097 3098 return 0; 3099 } 3100 3101 static void wcd934x_comp_remove(struct snd_soc_component *comp) 3102 { 3103 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3104 3105 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3106 } 3107 3108 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3109 int clk_id, int source, 3110 unsigned int freq, int dir) 3111 { 3112 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3113 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3114 3115 wcd->rate = freq; 3116 3117 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3118 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3119 3120 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3121 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3122 val); 3123 3124 return clk_set_rate(wcd->extclk, freq); 3125 } 3126 3127 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3128 int iir_idx, int band_idx, int coeff_idx) 3129 { 3130 u32 value = 0; 3131 int reg, b2_reg; 3132 3133 /* Address does not automatically update if reading */ 3134 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3135 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3136 3137 snd_soc_component_write(component, reg, 3138 ((band_idx * BAND_MAX + coeff_idx) * 3139 sizeof(uint32_t)) & 0x7F); 3140 3141 value |= snd_soc_component_read(component, b2_reg); 3142 snd_soc_component_write(component, reg, 3143 ((band_idx * BAND_MAX + coeff_idx) 3144 * sizeof(uint32_t) + 1) & 0x7F); 3145 3146 value |= (snd_soc_component_read(component, b2_reg) << 8); 3147 snd_soc_component_write(component, reg, 3148 ((band_idx * BAND_MAX + coeff_idx) 3149 * sizeof(uint32_t) + 2) & 0x7F); 3150 3151 value |= (snd_soc_component_read(component, b2_reg) << 16); 3152 snd_soc_component_write(component, reg, 3153 ((band_idx * BAND_MAX + coeff_idx) 3154 * sizeof(uint32_t) + 3) & 0x7F); 3155 3156 /* Mask bits top 2 bits since they are reserved */ 3157 value |= (snd_soc_component_read(component, b2_reg) << 24); 3158 return value; 3159 } 3160 3161 static void set_iir_band_coeff(struct snd_soc_component *component, 3162 int iir_idx, int band_idx, uint32_t value) 3163 { 3164 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3165 3166 snd_soc_component_write(component, reg, (value & 0xFF)); 3167 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3168 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3169 /* Mask top 2 bits, 7-8 are reserved */ 3170 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3171 } 3172 3173 static int wcd934x_put_iir_band_audio_mixer( 3174 struct snd_kcontrol *kcontrol, 3175 struct snd_ctl_elem_value *ucontrol) 3176 { 3177 struct snd_soc_component *component = 3178 snd_soc_kcontrol_component(kcontrol); 3179 struct wcd_iir_filter_ctl *ctl = 3180 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3181 struct soc_bytes_ext *params = &ctl->bytes_ext; 3182 int iir_idx = ctl->iir_idx; 3183 int band_idx = ctl->band_idx; 3184 u32 coeff[BAND_MAX]; 3185 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3186 3187 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3188 3189 /* Mask top bit it is reserved */ 3190 /* Updates addr automatically for each B2 write */ 3191 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3192 sizeof(uint32_t)) & 0x7F); 3193 3194 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3195 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3196 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3197 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3198 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3199 3200 return 0; 3201 } 3202 3203 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3204 struct snd_ctl_elem_value *ucontrol) 3205 { 3206 struct snd_soc_component *component = 3207 snd_soc_kcontrol_component(kcontrol); 3208 struct wcd_iir_filter_ctl *ctl = 3209 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3210 struct soc_bytes_ext *params = &ctl->bytes_ext; 3211 int iir_idx = ctl->iir_idx; 3212 int band_idx = ctl->band_idx; 3213 u32 coeff[BAND_MAX]; 3214 3215 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3216 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3217 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3218 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3219 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3220 3221 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3222 3223 return 0; 3224 } 3225 3226 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3227 struct snd_ctl_elem_info *ucontrol) 3228 { 3229 struct wcd_iir_filter_ctl *ctl = 3230 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3231 struct soc_bytes_ext *params = &ctl->bytes_ext; 3232 3233 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3234 ucontrol->count = params->max; 3235 3236 return 0; 3237 } 3238 3239 static int wcd934x_compander_get(struct snd_kcontrol *kc, 3240 struct snd_ctl_elem_value *ucontrol) 3241 { 3242 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3243 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3244 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3245 3246 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3247 3248 return 0; 3249 } 3250 3251 static int wcd934x_compander_set(struct snd_kcontrol *kc, 3252 struct snd_ctl_elem_value *ucontrol) 3253 { 3254 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3255 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3256 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3257 int value = ucontrol->value.integer.value[0]; 3258 int sel; 3259 3260 wcd->comp_enabled[comp] = value; 3261 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3262 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3263 3264 /* Any specific register configuration for compander */ 3265 switch (comp) { 3266 case COMPANDER_1: 3267 /* Set Gain Source Select based on compander enable/disable */ 3268 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3269 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3270 sel); 3271 break; 3272 case COMPANDER_2: 3273 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3274 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3275 sel); 3276 break; 3277 case COMPANDER_3: 3278 case COMPANDER_4: 3279 case COMPANDER_7: 3280 case COMPANDER_8: 3281 break; 3282 default: 3283 break; 3284 } 3285 3286 return 0; 3287 } 3288 3289 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3290 struct snd_ctl_elem_value *ucontrol) 3291 { 3292 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3293 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3294 3295 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3296 3297 return 0; 3298 } 3299 3300 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3301 struct snd_ctl_elem_value *ucontrol) 3302 { 3303 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3304 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3305 u32 mode_val; 3306 3307 mode_val = ucontrol->value.enumerated.item[0]; 3308 3309 if (mode_val == 0) { 3310 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3311 mode_val = CLS_H_LOHIFI; 3312 } 3313 wcd->hph_mode = mode_val; 3314 3315 return 0; 3316 } 3317 3318 static int slim_rx_mux_get(struct snd_kcontrol *kc, 3319 struct snd_ctl_elem_value *ucontrol) 3320 { 3321 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3322 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3323 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3324 3325 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3326 3327 return 0; 3328 } 3329 3330 static int slim_rx_mux_put(struct snd_kcontrol *kc, 3331 struct snd_ctl_elem_value *ucontrol) 3332 { 3333 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3334 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev); 3335 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3336 struct snd_soc_dapm_update *update = NULL; 3337 u32 port_id = w->shift; 3338 3339 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 3340 return 0; 3341 3342 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 3343 3344 switch (wcd->rx_port_value[port_id]) { 3345 case 0: 3346 list_del_init(&wcd->rx_chs[port_id].list); 3347 break; 3348 case 1: 3349 list_add_tail(&wcd->rx_chs[port_id].list, 3350 &wcd->dai[AIF1_PB].slim_ch_list); 3351 break; 3352 case 2: 3353 list_add_tail(&wcd->rx_chs[port_id].list, 3354 &wcd->dai[AIF2_PB].slim_ch_list); 3355 break; 3356 case 3: 3357 list_add_tail(&wcd->rx_chs[port_id].list, 3358 &wcd->dai[AIF3_PB].slim_ch_list); 3359 break; 3360 case 4: 3361 list_add_tail(&wcd->rx_chs[port_id].list, 3362 &wcd->dai[AIF4_PB].slim_ch_list); 3363 break; 3364 default: 3365 dev_err(wcd->dev, "Unknown AIF %d\n", 3366 wcd->rx_port_value[port_id]); 3367 goto err; 3368 } 3369 3370 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3371 e, update); 3372 3373 return 0; 3374 err: 3375 return -EINVAL; 3376 } 3377 3378 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3379 struct snd_ctl_elem_value *ucontrol) 3380 { 3381 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3382 struct snd_soc_component *component; 3383 int reg, val, ret; 3384 3385 component = snd_soc_dapm_kcontrol_component(kc); 3386 val = ucontrol->value.enumerated.item[0]; 3387 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3388 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3389 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3390 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3391 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3392 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3393 else 3394 return -EINVAL; 3395 3396 /* Set Look Ahead Delay */ 3397 if (val) 3398 snd_soc_component_update_bits(component, reg, 3399 WCD934X_RX_DLY_ZN_EN_MASK, 3400 WCD934X_RX_DLY_ZN_ENABLE); 3401 else 3402 snd_soc_component_update_bits(component, reg, 3403 WCD934X_RX_DLY_ZN_EN_MASK, 3404 WCD934X_RX_DLY_ZN_DISABLE); 3405 3406 ret = snd_soc_dapm_put_enum_double(kc, ucontrol); 3407 3408 return ret; 3409 } 3410 3411 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3412 struct snd_ctl_elem_value *ucontrol) 3413 { 3414 struct snd_soc_component *comp; 3415 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3416 unsigned int val; 3417 u16 mic_sel_reg = 0; 3418 u8 mic_sel; 3419 3420 comp = snd_soc_dapm_kcontrol_component(kcontrol); 3421 3422 val = ucontrol->value.enumerated.item[0]; 3423 if (val > e->items - 1) 3424 return -EINVAL; 3425 3426 switch (e->reg) { 3427 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3428 if (e->shift_l == 0) 3429 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3430 else if (e->shift_l == 2) 3431 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3432 else if (e->shift_l == 4) 3433 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3434 break; 3435 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3436 if (e->shift_l == 0) 3437 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3438 else if (e->shift_l == 2) 3439 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3440 break; 3441 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3442 if (e->shift_l == 0) 3443 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3444 else if (e->shift_l == 2) 3445 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3446 break; 3447 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3448 if (e->shift_l == 0) 3449 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3450 else if (e->shift_l == 2) 3451 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3452 break; 3453 default: 3454 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3455 __func__, e->reg); 3456 return -EINVAL; 3457 } 3458 3459 /* ADC: 0, DMIC: 1 */ 3460 mic_sel = val ? 0x0 : 0x1; 3461 if (mic_sel_reg) 3462 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3463 mic_sel << 7); 3464 3465 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3466 } 3467 3468 static const struct snd_kcontrol_new rx_int0_2_mux = 3469 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3470 3471 static const struct snd_kcontrol_new rx_int1_2_mux = 3472 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3473 3474 static const struct snd_kcontrol_new rx_int2_2_mux = 3475 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3476 3477 static const struct snd_kcontrol_new rx_int3_2_mux = 3478 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3479 3480 static const struct snd_kcontrol_new rx_int4_2_mux = 3481 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3482 3483 static const struct snd_kcontrol_new rx_int7_2_mux = 3484 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3485 3486 static const struct snd_kcontrol_new rx_int8_2_mux = 3487 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3488 3489 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3490 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3491 3492 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3493 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3494 3495 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3496 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3497 3498 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3499 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3500 3501 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3502 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3503 3504 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3505 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3506 3507 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3508 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3509 3510 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3511 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3512 3513 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3514 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3515 3516 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3517 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3518 3519 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3520 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3521 3522 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3523 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3524 3525 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3526 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3527 3528 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3529 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3530 3531 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3532 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3533 3534 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3535 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3536 3537 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3538 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3539 3540 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3541 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3542 3543 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3544 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3545 3546 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3547 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3548 3549 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3550 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3551 3552 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3553 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3554 3555 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3556 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3557 3558 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3559 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3560 3561 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3562 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3563 3564 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3565 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3566 3567 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3568 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3569 3570 static const struct snd_kcontrol_new iir0_inp0_mux = 3571 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3572 static const struct snd_kcontrol_new iir0_inp1_mux = 3573 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3574 static const struct snd_kcontrol_new iir0_inp2_mux = 3575 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3576 static const struct snd_kcontrol_new iir0_inp3_mux = 3577 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3578 3579 static const struct snd_kcontrol_new iir1_inp0_mux = 3580 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3581 static const struct snd_kcontrol_new iir1_inp1_mux = 3582 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3583 static const struct snd_kcontrol_new iir1_inp2_mux = 3584 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3585 static const struct snd_kcontrol_new iir1_inp3_mux = 3586 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3587 3588 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3589 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3590 slim_rx_mux_get, slim_rx_mux_put), 3591 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3592 slim_rx_mux_get, slim_rx_mux_put), 3593 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3594 slim_rx_mux_get, slim_rx_mux_put), 3595 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3596 slim_rx_mux_get, slim_rx_mux_put), 3597 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3598 slim_rx_mux_get, slim_rx_mux_put), 3599 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3600 slim_rx_mux_get, slim_rx_mux_put), 3601 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3602 slim_rx_mux_get, slim_rx_mux_put), 3603 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3604 slim_rx_mux_get, slim_rx_mux_put), 3605 }; 3606 3607 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3608 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3609 }; 3610 3611 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3612 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3613 }; 3614 3615 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3616 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3617 }; 3618 3619 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3620 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3621 }; 3622 3623 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3624 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3625 snd_soc_dapm_get_enum_double, 3626 wcd934x_int_dem_inp_mux_put); 3627 3628 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3629 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3630 snd_soc_dapm_get_enum_double, 3631 wcd934x_int_dem_inp_mux_put); 3632 3633 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3634 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3635 snd_soc_dapm_get_enum_double, 3636 wcd934x_int_dem_inp_mux_put); 3637 3638 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3639 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3640 3641 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3642 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3643 3644 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3645 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3646 3647 static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3648 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3649 3650 static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3651 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3652 3653 static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3654 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3655 3656 static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3657 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3658 3659 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3660 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3661 3662 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3663 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3664 3665 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3666 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3667 3668 static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3669 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3670 3671 static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3672 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3673 3674 static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3675 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3676 3677 static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3678 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3679 3680 static const struct snd_kcontrol_new tx_dmic_mux0 = 3681 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3682 3683 static const struct snd_kcontrol_new tx_dmic_mux1 = 3684 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3685 3686 static const struct snd_kcontrol_new tx_dmic_mux2 = 3687 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3688 3689 static const struct snd_kcontrol_new tx_dmic_mux3 = 3690 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3691 3692 static const struct snd_kcontrol_new tx_dmic_mux4 = 3693 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3694 3695 static const struct snd_kcontrol_new tx_dmic_mux5 = 3696 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3697 3698 static const struct snd_kcontrol_new tx_dmic_mux6 = 3699 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3700 3701 static const struct snd_kcontrol_new tx_dmic_mux7 = 3702 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3703 3704 static const struct snd_kcontrol_new tx_dmic_mux8 = 3705 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3706 3707 static const struct snd_kcontrol_new tx_amic_mux0 = 3708 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3709 3710 static const struct snd_kcontrol_new tx_amic_mux1 = 3711 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3712 3713 static const struct snd_kcontrol_new tx_amic_mux2 = 3714 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3715 3716 static const struct snd_kcontrol_new tx_amic_mux3 = 3717 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3718 3719 static const struct snd_kcontrol_new tx_amic_mux4 = 3720 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3721 3722 static const struct snd_kcontrol_new tx_amic_mux5 = 3723 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3724 3725 static const struct snd_kcontrol_new tx_amic_mux6 = 3726 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3727 3728 static const struct snd_kcontrol_new tx_amic_mux7 = 3729 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3730 3731 static const struct snd_kcontrol_new tx_amic_mux8 = 3732 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3733 3734 static const struct snd_kcontrol_new tx_amic4_5 = 3735 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3736 3737 static const struct snd_kcontrol_new tx_adc_mux0_mux = 3738 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3739 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3740 static const struct snd_kcontrol_new tx_adc_mux1_mux = 3741 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3742 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3743 static const struct snd_kcontrol_new tx_adc_mux2_mux = 3744 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3745 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3746 static const struct snd_kcontrol_new tx_adc_mux3_mux = 3747 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3748 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3749 static const struct snd_kcontrol_new tx_adc_mux4_mux = 3750 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3751 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3752 static const struct snd_kcontrol_new tx_adc_mux5_mux = 3753 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3754 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3755 static const struct snd_kcontrol_new tx_adc_mux6_mux = 3756 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3757 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3758 static const struct snd_kcontrol_new tx_adc_mux7_mux = 3759 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3760 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3761 static const struct snd_kcontrol_new tx_adc_mux8_mux = 3762 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3763 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3764 3765 static const struct snd_kcontrol_new cdc_if_tx0_mux = 3766 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3767 static const struct snd_kcontrol_new cdc_if_tx1_mux = 3768 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3769 static const struct snd_kcontrol_new cdc_if_tx2_mux = 3770 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3771 static const struct snd_kcontrol_new cdc_if_tx3_mux = 3772 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3773 static const struct snd_kcontrol_new cdc_if_tx4_mux = 3774 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3775 static const struct snd_kcontrol_new cdc_if_tx5_mux = 3776 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3777 static const struct snd_kcontrol_new cdc_if_tx6_mux = 3778 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3779 static const struct snd_kcontrol_new cdc_if_tx7_mux = 3780 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3781 static const struct snd_kcontrol_new cdc_if_tx8_mux = 3782 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3783 static const struct snd_kcontrol_new cdc_if_tx9_mux = 3784 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3785 static const struct snd_kcontrol_new cdc_if_tx10_mux = 3786 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3787 static const struct snd_kcontrol_new cdc_if_tx11_mux = 3788 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3789 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3790 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3791 static const struct snd_kcontrol_new cdc_if_tx13_mux = 3792 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3793 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3794 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3795 3796 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3797 struct snd_ctl_elem_value *ucontrol) 3798 { 3799 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3800 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3801 struct soc_mixer_control *mixer = 3802 (struct soc_mixer_control *)kc->private_value; 3803 int port_id = mixer->shift; 3804 3805 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3806 3807 return 0; 3808 } 3809 3810 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3811 struct snd_ctl_elem_value *ucontrol) 3812 { 3813 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 3814 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev); 3815 struct snd_soc_dapm_update *update = NULL; 3816 struct soc_mixer_control *mixer = 3817 (struct soc_mixer_control *)kc->private_value; 3818 int enable = ucontrol->value.integer.value[0]; 3819 int dai_id = widget->shift; 3820 int port_id = mixer->shift; 3821 3822 /* only add to the list if value not set */ 3823 if (enable == wcd->tx_port_value[port_id]) 3824 return 0; 3825 3826 wcd->tx_port_value[port_id] = enable; 3827 3828 if (enable) 3829 list_add_tail(&wcd->tx_chs[port_id].list, 3830 &wcd->dai[dai_id].slim_ch_list); 3831 else 3832 list_del_init(&wcd->tx_chs[port_id].list); 3833 3834 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3835 3836 return 0; 3837 } 3838 3839 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3840 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3841 slim_tx_mixer_get, slim_tx_mixer_put), 3842 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3843 slim_tx_mixer_get, slim_tx_mixer_put), 3844 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3845 slim_tx_mixer_get, slim_tx_mixer_put), 3846 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3847 slim_tx_mixer_get, slim_tx_mixer_put), 3848 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3849 slim_tx_mixer_get, slim_tx_mixer_put), 3850 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3851 slim_tx_mixer_get, slim_tx_mixer_put), 3852 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3853 slim_tx_mixer_get, slim_tx_mixer_put), 3854 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3855 slim_tx_mixer_get, slim_tx_mixer_put), 3856 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3857 slim_tx_mixer_get, slim_tx_mixer_put), 3858 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3859 slim_tx_mixer_get, slim_tx_mixer_put), 3860 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3861 slim_tx_mixer_get, slim_tx_mixer_put), 3862 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3863 slim_tx_mixer_get, slim_tx_mixer_put), 3864 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3865 slim_tx_mixer_get, slim_tx_mixer_put), 3866 }; 3867 3868 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3869 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3870 slim_tx_mixer_get, slim_tx_mixer_put), 3871 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3872 slim_tx_mixer_get, slim_tx_mixer_put), 3873 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3874 slim_tx_mixer_get, slim_tx_mixer_put), 3875 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3876 slim_tx_mixer_get, slim_tx_mixer_put), 3877 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3878 slim_tx_mixer_get, slim_tx_mixer_put), 3879 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3880 slim_tx_mixer_get, slim_tx_mixer_put), 3881 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3882 slim_tx_mixer_get, slim_tx_mixer_put), 3883 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3884 slim_tx_mixer_get, slim_tx_mixer_put), 3885 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3886 slim_tx_mixer_get, slim_tx_mixer_put), 3887 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3888 slim_tx_mixer_get, slim_tx_mixer_put), 3889 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3890 slim_tx_mixer_get, slim_tx_mixer_put), 3891 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3892 slim_tx_mixer_get, slim_tx_mixer_put), 3893 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3894 slim_tx_mixer_get, slim_tx_mixer_put), 3895 }; 3896 3897 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3898 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3899 slim_tx_mixer_get, slim_tx_mixer_put), 3900 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3901 slim_tx_mixer_get, slim_tx_mixer_put), 3902 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3903 slim_tx_mixer_get, slim_tx_mixer_put), 3904 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3905 slim_tx_mixer_get, slim_tx_mixer_put), 3906 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3907 slim_tx_mixer_get, slim_tx_mixer_put), 3908 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3909 slim_tx_mixer_get, slim_tx_mixer_put), 3910 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3911 slim_tx_mixer_get, slim_tx_mixer_put), 3912 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3913 slim_tx_mixer_get, slim_tx_mixer_put), 3914 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3915 slim_tx_mixer_get, slim_tx_mixer_put), 3916 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3917 slim_tx_mixer_get, slim_tx_mixer_put), 3918 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3919 slim_tx_mixer_get, slim_tx_mixer_put), 3920 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3921 slim_tx_mixer_get, slim_tx_mixer_put), 3922 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3923 slim_tx_mixer_get, slim_tx_mixer_put), 3924 }; 3925 3926 static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3927 /* Gain Controls */ 3928 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3929 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3930 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3931 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3932 3, 16, 1, line_gain), 3933 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3934 3, 16, 1, line_gain), 3935 3936 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3937 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3938 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3939 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3940 3941 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3942 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3943 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3944 -84, 40, digital_gain), 3945 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3946 -84, 40, digital_gain), 3947 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3948 -84, 40, digital_gain), 3949 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3950 -84, 40, digital_gain), 3951 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3952 -84, 40, digital_gain), 3953 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 3954 -84, 40, digital_gain), 3955 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 3956 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 3957 -84, 40, digital_gain), 3958 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 3959 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 3960 -84, 40, digital_gain), 3961 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 3962 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 3963 -84, 40, digital_gain), 3964 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 3965 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 3966 -84, 40, digital_gain), 3967 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 3968 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 3969 -84, 40, digital_gain), 3970 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 3971 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 3972 -84, 40, digital_gain), 3973 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 3974 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 3975 -84, 40, digital_gain), 3976 3977 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 3978 -84, 40, digital_gain), 3979 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 3980 -84, 40, digital_gain), 3981 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 3982 -84, 40, digital_gain), 3983 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 3984 -84, 40, digital_gain), 3985 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 3986 -84, 40, digital_gain), 3987 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 3988 -84, 40, digital_gain), 3989 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 3990 -84, 40, digital_gain), 3991 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 3992 -84, 40, digital_gain), 3993 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 3994 -84, 40, digital_gain), 3995 3996 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3997 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3998 digital_gain), 3999 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 4000 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 4001 digital_gain), 4002 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 4003 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 4004 digital_gain), 4005 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 4006 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 4007 digital_gain), 4008 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4009 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4010 digital_gain), 4011 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4012 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4013 digital_gain), 4014 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4015 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4016 digital_gain), 4017 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4018 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4019 digital_gain), 4020 4021 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4022 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4023 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4024 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4025 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4026 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4027 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4028 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4029 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4030 4031 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4032 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4033 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4034 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4035 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4036 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4037 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4038 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4039 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4040 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4041 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4042 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4043 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4044 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4045 4046 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4047 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4048 4049 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4050 0, 1, 0), 4051 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4052 1, 1, 0), 4053 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4054 2, 1, 0), 4055 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4056 3, 1, 0), 4057 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4058 4, 1, 0), 4059 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4060 0, 1, 0), 4061 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4062 1, 1, 0), 4063 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4064 2, 1, 0), 4065 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4066 3, 1, 0), 4067 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4068 4, 1, 0), 4069 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4070 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4071 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4072 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4073 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4074 4075 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4076 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4077 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4078 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4079 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4080 4081 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4082 wcd934x_compander_get, wcd934x_compander_set), 4083 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4084 wcd934x_compander_get, wcd934x_compander_set), 4085 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4086 wcd934x_compander_get, wcd934x_compander_set), 4087 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4088 wcd934x_compander_get, wcd934x_compander_set), 4089 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4090 wcd934x_compander_get, wcd934x_compander_set), 4091 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4092 wcd934x_compander_get, wcd934x_compander_set), 4093 }; 4094 4095 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4096 struct snd_soc_component *component) 4097 { 4098 int port_num = 0; 4099 unsigned short reg = 0; 4100 unsigned int val = 0; 4101 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4102 struct wcd934x_slim_ch *ch; 4103 4104 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4105 if (ch->port >= WCD934X_RX_START) { 4106 port_num = ch->port - WCD934X_RX_START; 4107 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4108 } else { 4109 port_num = ch->port; 4110 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4111 } 4112 4113 regmap_read(wcd->if_regmap, reg, &val); 4114 if (!(val & BIT(port_num % 8))) 4115 regmap_write(wcd->if_regmap, reg, 4116 val | BIT(port_num % 8)); 4117 } 4118 } 4119 4120 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4121 struct snd_kcontrol *kc, int event) 4122 { 4123 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4124 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4125 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4126 4127 switch (event) { 4128 case SND_SOC_DAPM_POST_PMU: 4129 wcd934x_codec_enable_int_port(dai, comp); 4130 break; 4131 } 4132 4133 return 0; 4134 } 4135 4136 static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4137 u16 interp_idx, int event) 4138 { 4139 u16 hd2_scale_reg; 4140 u16 hd2_enable_reg = 0; 4141 4142 switch (interp_idx) { 4143 case INTERP_HPHL: 4144 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4145 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4146 break; 4147 case INTERP_HPHR: 4148 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4149 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4150 break; 4151 default: 4152 return; 4153 } 4154 4155 if (SND_SOC_DAPM_EVENT_ON(event)) { 4156 snd_soc_component_update_bits(component, hd2_scale_reg, 4157 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4158 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4159 snd_soc_component_update_bits(component, hd2_enable_reg, 4160 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4161 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4162 } 4163 4164 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4165 snd_soc_component_update_bits(component, hd2_enable_reg, 4166 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4167 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4168 snd_soc_component_update_bits(component, hd2_scale_reg, 4169 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4170 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4171 } 4172 } 4173 4174 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4175 u16 interp_idx, int event) 4176 { 4177 u8 hph_dly_mask; 4178 u16 hph_lut_bypass_reg = 0; 4179 4180 switch (interp_idx) { 4181 case INTERP_HPHL: 4182 hph_dly_mask = 1; 4183 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4184 break; 4185 case INTERP_HPHR: 4186 hph_dly_mask = 2; 4187 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4188 break; 4189 default: 4190 return; 4191 } 4192 4193 if (SND_SOC_DAPM_EVENT_ON(event)) { 4194 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4195 hph_dly_mask, 0x0); 4196 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4197 WCD934X_HPH_LUT_BYPASS_MASK, 4198 WCD934X_HPH_LUT_BYPASS_ENABLE); 4199 } 4200 4201 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4202 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4203 hph_dly_mask, hph_dly_mask); 4204 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4205 WCD934X_HPH_LUT_BYPASS_MASK, 4206 WCD934X_HPH_LUT_BYPASS_DISABLE); 4207 } 4208 } 4209 4210 static int wcd934x_config_compander(struct snd_soc_component *comp, 4211 int interp_n, int event) 4212 { 4213 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4214 int compander; 4215 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4216 4217 /* EAR does not have compander */ 4218 if (!interp_n) 4219 return 0; 4220 4221 compander = interp_n - 1; 4222 if (!wcd->comp_enabled[compander]) 4223 return 0; 4224 4225 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4226 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4227 4228 switch (event) { 4229 case SND_SOC_DAPM_PRE_PMU: 4230 /* Enable Compander Clock */ 4231 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4232 WCD934X_COMP_CLK_EN_MASK, 4233 WCD934X_COMP_CLK_ENABLE); 4234 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4235 WCD934X_COMP_SOFT_RST_MASK, 4236 WCD934X_COMP_SOFT_RST_ENABLE); 4237 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4238 WCD934X_COMP_SOFT_RST_MASK, 4239 WCD934X_COMP_SOFT_RST_DISABLE); 4240 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4241 WCD934X_HPH_CMP_EN_MASK, 4242 WCD934X_HPH_CMP_ENABLE); 4243 break; 4244 case SND_SOC_DAPM_POST_PMD: 4245 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4246 WCD934X_HPH_CMP_EN_MASK, 4247 WCD934X_HPH_CMP_DISABLE); 4248 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4249 WCD934X_COMP_HALT_MASK, 4250 WCD934X_COMP_HALT); 4251 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4252 WCD934X_COMP_SOFT_RST_MASK, 4253 WCD934X_COMP_SOFT_RST_ENABLE); 4254 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4255 WCD934X_COMP_SOFT_RST_MASK, 4256 WCD934X_COMP_SOFT_RST_DISABLE); 4257 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4258 WCD934X_COMP_CLK_EN_MASK, 0x0); 4259 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4260 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4261 break; 4262 } 4263 4264 return 0; 4265 } 4266 4267 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4268 struct snd_kcontrol *kc, int event) 4269 { 4270 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4271 int interp_idx = w->shift; 4272 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4273 4274 switch (event) { 4275 case SND_SOC_DAPM_PRE_PMU: 4276 /* Clk enable */ 4277 snd_soc_component_update_bits(comp, main_reg, 4278 WCD934X_RX_CLK_EN_MASK, 4279 WCD934X_RX_CLK_ENABLE); 4280 wcd934x_codec_hd2_control(comp, interp_idx, event); 4281 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4282 wcd934x_config_compander(comp, interp_idx, event); 4283 break; 4284 case SND_SOC_DAPM_POST_PMD: 4285 wcd934x_config_compander(comp, interp_idx, event); 4286 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4287 wcd934x_codec_hd2_control(comp, interp_idx, event); 4288 /* Clk Disable */ 4289 snd_soc_component_update_bits(comp, main_reg, 4290 WCD934X_RX_CLK_EN_MASK, 0); 4291 /* Reset enable and disable */ 4292 snd_soc_component_update_bits(comp, main_reg, 4293 WCD934X_RX_RESET_MASK, 4294 WCD934X_RX_RESET_ENABLE); 4295 snd_soc_component_update_bits(comp, main_reg, 4296 WCD934X_RX_RESET_MASK, 4297 WCD934X_RX_RESET_DISABLE); 4298 /* Reset rate to 48K*/ 4299 snd_soc_component_update_bits(comp, main_reg, 4300 WCD934X_RX_PCM_RATE_MASK, 4301 WCD934X_RX_PCM_RATE_F_48K); 4302 break; 4303 } 4304 4305 return 0; 4306 } 4307 4308 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4309 struct snd_kcontrol *kc, int event) 4310 { 4311 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4312 int offset_val = 0; 4313 u16 gain_reg, mix_reg; 4314 int val = 0; 4315 4316 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4317 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4318 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4319 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4320 4321 switch (event) { 4322 case SND_SOC_DAPM_PRE_PMU: 4323 /* Clk enable */ 4324 snd_soc_component_update_bits(comp, mix_reg, 4325 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4326 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4327 break; 4328 4329 case SND_SOC_DAPM_POST_PMU: 4330 val = snd_soc_component_read(comp, gain_reg); 4331 val += offset_val; 4332 snd_soc_component_write(comp, gain_reg, val); 4333 break; 4334 } 4335 4336 return 0; 4337 } 4338 4339 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4340 struct snd_kcontrol *kcontrol, int event) 4341 { 4342 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4343 int reg = w->reg; 4344 4345 switch (event) { 4346 case SND_SOC_DAPM_POST_PMU: 4347 /* B1 GAIN */ 4348 snd_soc_component_write(comp, reg, 4349 snd_soc_component_read(comp, reg)); 4350 /* B2 GAIN */ 4351 reg++; 4352 snd_soc_component_write(comp, reg, 4353 snd_soc_component_read(comp, reg)); 4354 /* B3 GAIN */ 4355 reg++; 4356 snd_soc_component_write(comp, reg, 4357 snd_soc_component_read(comp, reg)); 4358 /* B4 GAIN */ 4359 reg++; 4360 snd_soc_component_write(comp, reg, 4361 snd_soc_component_read(comp, reg)); 4362 /* B5 GAIN */ 4363 reg++; 4364 snd_soc_component_write(comp, reg, 4365 snd_soc_component_read(comp, reg)); 4366 break; 4367 default: 4368 break; 4369 } 4370 return 0; 4371 } 4372 4373 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4374 struct snd_kcontrol *kcontrol, 4375 int event) 4376 { 4377 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4378 u16 gain_reg; 4379 4380 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4381 WCD934X_RX_PATH_CTL_OFFSET); 4382 4383 switch (event) { 4384 case SND_SOC_DAPM_POST_PMU: 4385 snd_soc_component_write(comp, gain_reg, 4386 snd_soc_component_read(comp, gain_reg)); 4387 break; 4388 } 4389 4390 return 0; 4391 } 4392 4393 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4394 struct snd_kcontrol *kc, int event) 4395 { 4396 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4397 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4398 4399 switch (event) { 4400 case SND_SOC_DAPM_PRE_PMU: 4401 /* Disable AutoChop timer during power up */ 4402 snd_soc_component_update_bits(comp, 4403 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4404 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4405 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4406 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4407 4408 break; 4409 case SND_SOC_DAPM_POST_PMD: 4410 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4411 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4412 break; 4413 } 4414 4415 return 0; 4416 } 4417 4418 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4419 struct snd_kcontrol *kcontrol, 4420 int event) 4421 { 4422 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4423 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4424 int hph_mode = wcd->hph_mode; 4425 u8 dem_inp; 4426 4427 switch (event) { 4428 case SND_SOC_DAPM_PRE_PMU: 4429 /* Read DEM INP Select */ 4430 dem_inp = snd_soc_component_read(comp, 4431 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4432 4433 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4434 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4435 return -EINVAL; 4436 } 4437 if (hph_mode != CLS_H_LP) 4438 /* Ripple freq control enable */ 4439 snd_soc_component_update_bits(comp, 4440 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4441 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4442 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4443 /* Disable AutoChop timer during power up */ 4444 snd_soc_component_update_bits(comp, 4445 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4446 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4447 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4448 WCD_CLSH_STATE_HPHL, hph_mode); 4449 4450 break; 4451 case SND_SOC_DAPM_POST_PMD: 4452 /* 1000us required as per HW requirement */ 4453 usleep_range(1000, 1100); 4454 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4455 WCD_CLSH_STATE_HPHL, hph_mode); 4456 if (hph_mode != CLS_H_LP) 4457 /* Ripple freq control disable */ 4458 snd_soc_component_update_bits(comp, 4459 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4460 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4461 4462 break; 4463 default: 4464 break; 4465 } 4466 4467 return 0; 4468 } 4469 4470 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4471 struct snd_kcontrol *kcontrol, 4472 int event) 4473 { 4474 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4475 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4476 int hph_mode = wcd->hph_mode; 4477 u8 dem_inp; 4478 4479 switch (event) { 4480 case SND_SOC_DAPM_PRE_PMU: 4481 dem_inp = snd_soc_component_read(comp, 4482 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4483 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4484 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4485 return -EINVAL; 4486 } 4487 if (hph_mode != CLS_H_LP) 4488 /* Ripple freq control enable */ 4489 snd_soc_component_update_bits(comp, 4490 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4491 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4492 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4493 /* Disable AutoChop timer during power up */ 4494 snd_soc_component_update_bits(comp, 4495 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4496 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4497 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4498 WCD_CLSH_STATE_HPHR, 4499 hph_mode); 4500 break; 4501 case SND_SOC_DAPM_POST_PMD: 4502 /* 1000us required as per HW requirement */ 4503 usleep_range(1000, 1100); 4504 4505 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4506 WCD_CLSH_STATE_HPHR, hph_mode); 4507 if (hph_mode != CLS_H_LP) 4508 /* Ripple freq control disable */ 4509 snd_soc_component_update_bits(comp, 4510 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4511 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4512 break; 4513 default: 4514 break; 4515 } 4516 4517 return 0; 4518 } 4519 4520 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4521 struct snd_kcontrol *kc, int event) 4522 { 4523 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4524 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4525 4526 switch (event) { 4527 case SND_SOC_DAPM_PRE_PMU: 4528 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4529 WCD_CLSH_STATE_LO, CLS_AB); 4530 break; 4531 case SND_SOC_DAPM_POST_PMD: 4532 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4533 WCD_CLSH_STATE_LO, CLS_AB); 4534 break; 4535 } 4536 4537 return 0; 4538 } 4539 4540 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4541 struct snd_kcontrol *kcontrol, 4542 int event) 4543 { 4544 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4545 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4546 4547 switch (event) { 4548 case SND_SOC_DAPM_POST_PMU: 4549 /* 4550 * 7ms sleep is required after PA is enabled as per 4551 * HW requirement. If compander is disabled, then 4552 * 20ms delay is needed. 4553 */ 4554 usleep_range(20000, 20100); 4555 4556 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4557 WCD934X_HPH_OCP_DET_MASK, 4558 WCD934X_HPH_OCP_DET_ENABLE); 4559 /* Remove Mute on primary path */ 4560 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4561 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4562 0); 4563 /* Enable GM3 boost */ 4564 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4565 WCD934X_HPH_GM3_BOOST_EN_MASK, 4566 WCD934X_HPH_GM3_BOOST_ENABLE); 4567 /* Enable AutoChop timer at the end of power up */ 4568 snd_soc_component_update_bits(comp, 4569 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4570 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4571 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4572 /* Remove mix path mute */ 4573 snd_soc_component_update_bits(comp, 4574 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4575 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4576 break; 4577 case SND_SOC_DAPM_PRE_PMD: 4578 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4579 /* Enable DSD Mute before PA disable */ 4580 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4581 WCD934X_HPH_OCP_DET_MASK, 4582 WCD934X_HPH_OCP_DET_DISABLE); 4583 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4584 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4585 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4586 snd_soc_component_update_bits(comp, 4587 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4588 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4589 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4590 break; 4591 case SND_SOC_DAPM_POST_PMD: 4592 /* 4593 * 5ms sleep is required after PA disable. If compander is 4594 * disabled, then 20ms delay is needed after PA disable. 4595 */ 4596 usleep_range(20000, 20100); 4597 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4598 break; 4599 } 4600 4601 return 0; 4602 } 4603 4604 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4605 struct snd_kcontrol *kcontrol, 4606 int event) 4607 { 4608 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4609 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4610 4611 switch (event) { 4612 case SND_SOC_DAPM_POST_PMU: 4613 /* 4614 * 7ms sleep is required after PA is enabled as per 4615 * HW requirement. If compander is disabled, then 4616 * 20ms delay is needed. 4617 */ 4618 usleep_range(20000, 20100); 4619 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4620 WCD934X_HPH_OCP_DET_MASK, 4621 WCD934X_HPH_OCP_DET_ENABLE); 4622 /* Remove mute */ 4623 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4624 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4625 0); 4626 /* Enable GM3 boost */ 4627 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4628 WCD934X_HPH_GM3_BOOST_EN_MASK, 4629 WCD934X_HPH_GM3_BOOST_ENABLE); 4630 /* Enable AutoChop timer at the end of power up */ 4631 snd_soc_component_update_bits(comp, 4632 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4633 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4634 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4635 /* Remove mix path mute if it is enabled */ 4636 if ((snd_soc_component_read(comp, 4637 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4638 snd_soc_component_update_bits(comp, 4639 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4640 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4641 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4642 break; 4643 case SND_SOC_DAPM_PRE_PMD: 4644 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4645 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4646 WCD934X_HPH_OCP_DET_MASK, 4647 WCD934X_HPH_OCP_DET_DISABLE); 4648 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4649 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4650 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4651 snd_soc_component_update_bits(comp, 4652 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4653 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4654 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4655 break; 4656 case SND_SOC_DAPM_POST_PMD: 4657 /* 4658 * 5ms sleep is required after PA disable. If compander is 4659 * disabled, then 20ms delay is needed after PA disable. 4660 */ 4661 usleep_range(20000, 20100); 4662 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4663 break; 4664 } 4665 4666 return 0; 4667 } 4668 4669 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4670 unsigned int dmic, 4671 struct wcd934x_codec *wcd) 4672 { 4673 u8 tx_stream_fs; 4674 u8 adc_mux_index = 0, adc_mux_sel = 0; 4675 bool dec_found = false; 4676 u16 adc_mux_ctl_reg, tx_fs_reg; 4677 u32 dmic_fs; 4678 4679 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4680 if (adc_mux_index < 4) { 4681 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4682 (adc_mux_index * 2); 4683 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4684 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4685 adc_mux_index - 4; 4686 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4687 ++adc_mux_index; 4688 continue; 4689 } 4690 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4691 & 0xF8) >> 3) - 1; 4692 4693 if (adc_mux_sel == dmic) { 4694 dec_found = true; 4695 break; 4696 } 4697 4698 ++adc_mux_index; 4699 } 4700 4701 if (dec_found && adc_mux_index <= 8) { 4702 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4703 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4704 if (tx_stream_fs <= 4) { 4705 if (wcd->dmic_sample_rate <= 4706 WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ) 4707 dmic_fs = wcd->dmic_sample_rate; 4708 else 4709 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ; 4710 } else 4711 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4712 } else { 4713 dmic_fs = wcd->dmic_sample_rate; 4714 } 4715 4716 return dmic_fs; 4717 } 4718 4719 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4720 u32 mclk_rate, u32 dmic_clk_rate) 4721 { 4722 u32 div_factor; 4723 u8 dmic_ctl_val; 4724 4725 /* Default value to return in case of error */ 4726 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4727 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4728 else 4729 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4730 4731 if (dmic_clk_rate == 0) { 4732 dev_err(comp->dev, 4733 "%s: dmic_sample_rate cannot be 0\n", 4734 __func__); 4735 goto done; 4736 } 4737 4738 div_factor = mclk_rate / dmic_clk_rate; 4739 switch (div_factor) { 4740 case 2: 4741 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4742 break; 4743 case 3: 4744 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4745 break; 4746 case 4: 4747 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4748 break; 4749 case 6: 4750 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4751 break; 4752 case 8: 4753 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4754 break; 4755 case 16: 4756 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4757 break; 4758 default: 4759 dev_err(comp->dev, 4760 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4761 __func__, div_factor, mclk_rate, dmic_clk_rate); 4762 break; 4763 } 4764 4765 done: 4766 return dmic_ctl_val; 4767 } 4768 4769 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4770 struct snd_kcontrol *kcontrol, int event) 4771 { 4772 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4773 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4774 u8 dmic_clk_en = 0x01; 4775 u16 dmic_clk_reg; 4776 s32 *dmic_clk_cnt; 4777 u8 dmic_rate_val, dmic_rate_shift = 1; 4778 unsigned int dmic; 4779 u32 dmic_sample_rate; 4780 int ret; 4781 char *wname; 4782 4783 wname = strpbrk(w->name, "012345"); 4784 if (!wname) { 4785 dev_err(comp->dev, "%s: widget not found\n", __func__); 4786 return -EINVAL; 4787 } 4788 4789 ret = kstrtouint(wname, 10, &dmic); 4790 if (ret < 0) { 4791 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4792 __func__); 4793 return -EINVAL; 4794 } 4795 4796 switch (dmic) { 4797 case 0: 4798 case 1: 4799 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4800 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4801 break; 4802 case 2: 4803 case 3: 4804 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4805 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4806 break; 4807 case 4: 4808 case 5: 4809 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4810 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4811 break; 4812 default: 4813 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4814 __func__); 4815 return -EINVAL; 4816 } 4817 4818 switch (event) { 4819 case SND_SOC_DAPM_PRE_PMU: 4820 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4821 wcd); 4822 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4823 dmic_sample_rate); 4824 (*dmic_clk_cnt)++; 4825 if (*dmic_clk_cnt == 1) { 4826 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4827 snd_soc_component_update_bits(comp, dmic_clk_reg, 4828 WCD934X_DMIC_RATE_MASK, 4829 dmic_rate_val); 4830 snd_soc_component_update_bits(comp, dmic_clk_reg, 4831 dmic_clk_en, dmic_clk_en); 4832 } 4833 4834 break; 4835 case SND_SOC_DAPM_POST_PMD: 4836 (*dmic_clk_cnt)--; 4837 if (*dmic_clk_cnt == 0) 4838 snd_soc_component_update_bits(comp, dmic_clk_reg, 4839 dmic_clk_en, 0); 4840 break; 4841 } 4842 4843 return 0; 4844 } 4845 4846 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4847 int adc_mux_n) 4848 { 4849 u16 mask, shift, adc_mux_in_reg; 4850 u16 amic_mux_sel_reg; 4851 bool is_amic; 4852 4853 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4854 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4855 return 0; 4856 4857 if (adc_mux_n < 3) { 4858 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4859 adc_mux_n; 4860 mask = 0x03; 4861 shift = 0; 4862 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4863 2 * adc_mux_n; 4864 } else if (adc_mux_n < 4) { 4865 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4866 mask = 0x03; 4867 shift = 0; 4868 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4869 2 * adc_mux_n; 4870 } else if (adc_mux_n < 7) { 4871 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4872 (adc_mux_n - 4); 4873 mask = 0x0C; 4874 shift = 2; 4875 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4876 adc_mux_n - 4; 4877 } else if (adc_mux_n < 8) { 4878 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4879 mask = 0x0C; 4880 shift = 2; 4881 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4882 adc_mux_n - 4; 4883 } else if (adc_mux_n < 12) { 4884 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4885 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4886 (adc_mux_n - 9)); 4887 mask = 0x30; 4888 shift = 4; 4889 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4890 adc_mux_n - 4; 4891 } else if (adc_mux_n < 13) { 4892 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4893 mask = 0x30; 4894 shift = 4; 4895 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4896 adc_mux_n - 4; 4897 } else { 4898 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4899 mask = 0xC0; 4900 shift = 6; 4901 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4902 adc_mux_n - 4; 4903 } 4904 4905 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4906 & mask) >> shift) == 1); 4907 if (!is_amic) 4908 return 0; 4909 4910 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4911 } 4912 4913 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4914 int amic) 4915 { 4916 u16 pwr_level_reg = 0; 4917 4918 switch (amic) { 4919 case 1: 4920 case 2: 4921 pwr_level_reg = WCD934X_ANA_AMIC1; 4922 break; 4923 4924 case 3: 4925 case 4: 4926 pwr_level_reg = WCD934X_ANA_AMIC3; 4927 break; 4928 default: 4929 break; 4930 } 4931 4932 return pwr_level_reg; 4933 } 4934 4935 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4936 struct snd_kcontrol *kcontrol, int event) 4937 { 4938 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4939 unsigned int decimator; 4940 char *dec_adc_mux_name = NULL; 4941 char *widget_name = NULL; 4942 char *wname; 4943 int ret = 0, amic_n; 4944 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4945 u16 tx_gain_ctl_reg; 4946 char *dec; 4947 u8 hpf_coff_freq; 4948 4949 widget_name = kstrndup(w->name, 15, GFP_KERNEL); 4950 if (!widget_name) 4951 return -ENOMEM; 4952 4953 wname = widget_name; 4954 dec_adc_mux_name = strsep(&widget_name, " "); 4955 if (!dec_adc_mux_name) { 4956 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4957 __func__, w->name); 4958 ret = -EINVAL; 4959 goto out; 4960 } 4961 dec_adc_mux_name = widget_name; 4962 4963 dec = strpbrk(dec_adc_mux_name, "012345678"); 4964 if (!dec) { 4965 dev_err(comp->dev, "%s: decimator index not found\n", 4966 __func__); 4967 ret = -EINVAL; 4968 goto out; 4969 } 4970 4971 ret = kstrtouint(dec, 10, &decimator); 4972 if (ret < 0) { 4973 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4974 __func__, wname); 4975 ret = -EINVAL; 4976 goto out; 4977 } 4978 4979 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 4980 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 4981 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 4982 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 4983 4984 switch (event) { 4985 case SND_SOC_DAPM_PRE_PMU: 4986 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 4987 if (amic_n) 4988 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 4989 amic_n); 4990 4991 if (!pwr_level_reg) 4992 break; 4993 4994 switch ((snd_soc_component_read(comp, pwr_level_reg) & 4995 WCD934X_AMIC_PWR_LVL_MASK) >> 4996 WCD934X_AMIC_PWR_LVL_SHIFT) { 4997 case WCD934X_AMIC_PWR_LEVEL_LP: 4998 snd_soc_component_update_bits(comp, dec_cfg_reg, 4999 WCD934X_DEC_PWR_LVL_MASK, 5000 WCD934X_DEC_PWR_LVL_LP); 5001 break; 5002 case WCD934X_AMIC_PWR_LEVEL_HP: 5003 snd_soc_component_update_bits(comp, dec_cfg_reg, 5004 WCD934X_DEC_PWR_LVL_MASK, 5005 WCD934X_DEC_PWR_LVL_HP); 5006 break; 5007 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 5008 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 5009 default: 5010 snd_soc_component_update_bits(comp, dec_cfg_reg, 5011 WCD934X_DEC_PWR_LVL_MASK, 5012 WCD934X_DEC_PWR_LVL_DF); 5013 break; 5014 } 5015 break; 5016 case SND_SOC_DAPM_POST_PMU: 5017 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5018 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5019 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5020 snd_soc_component_update_bits(comp, dec_cfg_reg, 5021 TX_HPF_CUT_OFF_FREQ_MASK, 5022 CF_MIN_3DB_150HZ << 5); 5023 snd_soc_component_update_bits(comp, hpf_gate_reg, 5024 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5025 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5026 /* 5027 * Minimum 1 clk cycle delay is required as per 5028 * HW spec. 5029 */ 5030 usleep_range(1000, 1010); 5031 snd_soc_component_update_bits(comp, hpf_gate_reg, 5032 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5033 0); 5034 } 5035 /* apply gain after decimator is enabled */ 5036 snd_soc_component_write(comp, tx_gain_ctl_reg, 5037 snd_soc_component_read(comp, 5038 tx_gain_ctl_reg)); 5039 break; 5040 case SND_SOC_DAPM_PRE_PMD: 5041 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5042 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5043 5044 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5045 snd_soc_component_update_bits(comp, dec_cfg_reg, 5046 TX_HPF_CUT_OFF_FREQ_MASK, 5047 hpf_coff_freq << 5); 5048 snd_soc_component_update_bits(comp, hpf_gate_reg, 5049 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5050 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5051 /* 5052 * Minimum 1 clk cycle delay is required as per 5053 * HW spec. 5054 */ 5055 usleep_range(1000, 1010); 5056 snd_soc_component_update_bits(comp, hpf_gate_reg, 5057 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5058 0); 5059 } 5060 break; 5061 case SND_SOC_DAPM_POST_PMD: 5062 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5063 0x10, 0x00); 5064 snd_soc_component_update_bits(comp, dec_cfg_reg, 5065 WCD934X_DEC_PWR_LVL_MASK, 5066 WCD934X_DEC_PWR_LVL_DF); 5067 break; 5068 } 5069 out: 5070 kfree(wname); 5071 return ret; 5072 } 5073 5074 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5075 u16 amic_reg, bool set) 5076 { 5077 u8 mask = 0x20; 5078 u8 val; 5079 5080 if (amic_reg == WCD934X_ANA_AMIC1 || 5081 amic_reg == WCD934X_ANA_AMIC3) 5082 mask = 0x40; 5083 5084 val = set ? mask : 0x00; 5085 5086 switch (amic_reg) { 5087 case WCD934X_ANA_AMIC1: 5088 case WCD934X_ANA_AMIC2: 5089 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5090 mask, val); 5091 break; 5092 case WCD934X_ANA_AMIC3: 5093 case WCD934X_ANA_AMIC4: 5094 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5095 mask, val); 5096 break; 5097 default: 5098 break; 5099 } 5100 } 5101 5102 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5103 struct snd_kcontrol *kcontrol, int event) 5104 { 5105 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5106 5107 switch (event) { 5108 case SND_SOC_DAPM_PRE_PMU: 5109 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5110 break; 5111 default: 5112 break; 5113 } 5114 5115 return 0; 5116 } 5117 5118 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5119 struct snd_kcontrol *kcontrol, 5120 int event) 5121 { 5122 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5123 int micb_num = w->shift; 5124 5125 switch (event) { 5126 case SND_SOC_DAPM_PRE_PMU: 5127 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5128 break; 5129 case SND_SOC_DAPM_POST_PMU: 5130 /* 1 msec delay as per HW requirement */ 5131 usleep_range(1000, 1100); 5132 break; 5133 case SND_SOC_DAPM_POST_PMD: 5134 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5135 break; 5136 } 5137 5138 return 0; 5139 } 5140 5141 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5142 /* Analog Outputs */ 5143 SND_SOC_DAPM_OUTPUT("EAR"), 5144 SND_SOC_DAPM_OUTPUT("HPHL"), 5145 SND_SOC_DAPM_OUTPUT("HPHR"), 5146 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5147 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5148 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5149 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5150 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5151 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5152 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5153 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5154 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5155 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5156 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5157 AIF1_PB, 0, wcd934x_codec_enable_slim, 5158 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5159 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5160 AIF2_PB, 0, wcd934x_codec_enable_slim, 5161 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5162 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5163 AIF3_PB, 0, wcd934x_codec_enable_slim, 5164 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5165 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5166 AIF4_PB, 0, wcd934x_codec_enable_slim, 5167 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5168 5169 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5170 &slim_rx_mux[WCD934X_RX0]), 5171 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5172 &slim_rx_mux[WCD934X_RX1]), 5173 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5174 &slim_rx_mux[WCD934X_RX2]), 5175 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5176 &slim_rx_mux[WCD934X_RX3]), 5177 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5178 &slim_rx_mux[WCD934X_RX4]), 5179 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5180 &slim_rx_mux[WCD934X_RX5]), 5181 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5182 &slim_rx_mux[WCD934X_RX6]), 5183 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5184 &slim_rx_mux[WCD934X_RX7]), 5185 5186 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5187 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5188 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5189 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5190 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5191 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5192 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5193 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5194 5195 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5196 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5197 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5198 SND_SOC_DAPM_POST_PMD), 5199 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5200 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5201 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5202 SND_SOC_DAPM_POST_PMD), 5203 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5204 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5205 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5206 SND_SOC_DAPM_POST_PMD), 5207 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5208 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5209 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5210 SND_SOC_DAPM_POST_PMD), 5211 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5212 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5213 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5214 SND_SOC_DAPM_POST_PMD), 5215 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5216 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5217 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5218 SND_SOC_DAPM_POST_PMD), 5219 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5220 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5221 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5222 SND_SOC_DAPM_POST_PMD), 5223 5224 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5225 &rx_int0_1_mix_inp0_mux), 5226 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5227 &rx_int0_1_mix_inp1_mux), 5228 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5229 &rx_int0_1_mix_inp2_mux), 5230 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5231 &rx_int1_1_mix_inp0_mux), 5232 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5233 &rx_int1_1_mix_inp1_mux), 5234 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5235 &rx_int1_1_mix_inp2_mux), 5236 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5237 &rx_int2_1_mix_inp0_mux), 5238 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5239 &rx_int2_1_mix_inp1_mux), 5240 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5241 &rx_int2_1_mix_inp2_mux), 5242 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5243 &rx_int3_1_mix_inp0_mux), 5244 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5245 &rx_int3_1_mix_inp1_mux), 5246 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5247 &rx_int3_1_mix_inp2_mux), 5248 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5249 &rx_int4_1_mix_inp0_mux), 5250 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5251 &rx_int4_1_mix_inp1_mux), 5252 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5253 &rx_int4_1_mix_inp2_mux), 5254 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5255 &rx_int7_1_mix_inp0_mux), 5256 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5257 &rx_int7_1_mix_inp1_mux), 5258 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5259 &rx_int7_1_mix_inp2_mux), 5260 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5261 &rx_int8_1_mix_inp0_mux), 5262 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5263 &rx_int8_1_mix_inp1_mux), 5264 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5265 &rx_int8_1_mix_inp2_mux), 5266 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5267 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5268 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5269 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5270 rx_int1_asrc_switch, 5271 ARRAY_SIZE(rx_int1_asrc_switch)), 5272 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5273 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5274 rx_int2_asrc_switch, 5275 ARRAY_SIZE(rx_int2_asrc_switch)), 5276 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5277 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5278 rx_int3_asrc_switch, 5279 ARRAY_SIZE(rx_int3_asrc_switch)), 5280 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5281 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5282 rx_int4_asrc_switch, 5283 ARRAY_SIZE(rx_int4_asrc_switch)), 5284 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5285 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5286 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5287 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5288 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5289 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5290 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5291 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5292 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5293 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5294 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5295 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5296 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5297 5298 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5299 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5300 NULL, 0, NULL, 0), 5301 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5302 NULL, 0, NULL, 0), 5303 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5304 0, &rx_int0_mix2_inp_mux, NULL, 5305 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5306 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5307 0, &rx_int1_mix2_inp_mux, NULL, 5308 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5309 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5310 0, &rx_int2_mix2_inp_mux, NULL, 5311 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5312 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5313 0, &rx_int3_mix2_inp_mux, NULL, 5314 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5315 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5316 0, &rx_int4_mix2_inp_mux, NULL, 5317 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5318 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5319 0, &rx_int7_mix2_inp_mux, NULL, 5320 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5321 5322 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5323 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5324 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5325 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5326 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5327 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5328 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5329 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5330 5331 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5332 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5333 SND_SOC_DAPM_POST_PMU), 5334 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5335 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5336 SND_SOC_DAPM_POST_PMU), 5337 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5338 4, 0, NULL, 0), 5339 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5340 4, 0, NULL, 0), 5341 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5342 &rx_int0_dem_inp_mux), 5343 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5344 &rx_int1_dem_inp_mux), 5345 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5346 &rx_int2_dem_inp_mux), 5347 5348 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5349 &rx_int0_1_interp_mux, 5350 wcd934x_codec_enable_main_path, 5351 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5352 SND_SOC_DAPM_POST_PMD), 5353 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5354 &rx_int1_1_interp_mux, 5355 wcd934x_codec_enable_main_path, 5356 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5357 SND_SOC_DAPM_POST_PMD), 5358 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5359 &rx_int2_1_interp_mux, 5360 wcd934x_codec_enable_main_path, 5361 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5362 SND_SOC_DAPM_POST_PMD), 5363 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5364 &rx_int3_1_interp_mux, 5365 wcd934x_codec_enable_main_path, 5366 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5367 SND_SOC_DAPM_POST_PMD), 5368 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5369 &rx_int4_1_interp_mux, 5370 wcd934x_codec_enable_main_path, 5371 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5372 SND_SOC_DAPM_POST_PMD), 5373 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5374 &rx_int7_1_interp_mux, 5375 wcd934x_codec_enable_main_path, 5376 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5377 SND_SOC_DAPM_POST_PMD), 5378 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5379 &rx_int8_1_interp_mux, 5380 wcd934x_codec_enable_main_path, 5381 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5382 SND_SOC_DAPM_POST_PMD), 5383 5384 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5385 &rx_int0_2_interp_mux), 5386 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5387 &rx_int1_2_interp_mux), 5388 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5389 &rx_int2_2_interp_mux), 5390 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5391 &rx_int3_2_interp_mux), 5392 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5393 &rx_int4_2_interp_mux), 5394 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5395 &rx_int7_2_interp_mux), 5396 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5397 &rx_int8_2_interp_mux), 5398 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5399 0, 0, wcd934x_codec_ear_dac_event, 5400 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5401 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5402 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5403 5, 0, wcd934x_codec_hphl_dac_event, 5404 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5405 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5406 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5407 4, 0, wcd934x_codec_hphr_dac_event, 5408 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5409 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5410 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5411 0, 0, wcd934x_codec_lineout_dac_event, 5412 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5413 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5414 0, 0, wcd934x_codec_lineout_dac_event, 5415 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5416 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5417 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5418 wcd934x_codec_enable_hphl_pa, 5419 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5420 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5421 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5422 wcd934x_codec_enable_hphr_pa, 5423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5424 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5425 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5426 NULL, 0), 5427 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5428 NULL, 0), 5429 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5430 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5431 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5432 0, 0, NULL, 0), 5433 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5434 0, 0, NULL, 0), 5435 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5436 0, 0, NULL, 0), 5437 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5438 0, 0, NULL, 0), 5439 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5440 wcd934x_codec_enable_interp_clk, 5441 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5442 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5443 wcd934x_codec_enable_interp_clk, 5444 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5445 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5446 wcd934x_codec_enable_interp_clk, 5447 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5448 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5449 wcd934x_codec_enable_interp_clk, 5450 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5451 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5452 wcd934x_codec_enable_interp_clk, 5453 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5454 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5455 wcd934x_codec_enable_interp_clk, 5456 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5457 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5458 wcd934x_codec_enable_interp_clk, 5459 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5460 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5461 0, 0, NULL, 0), 5462 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5463 0, 0, NULL, 0), 5464 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5465 0, 0, NULL, 0), 5466 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5467 0, 0, NULL, 0), 5468 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5469 0, 0, NULL, 0), 5470 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5471 0, 0, NULL, 0), 5472 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5473 0, 0, NULL, 0), 5474 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5475 wcd934x_codec_enable_mclk, 5476 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5477 5478 /* TX */ 5479 SND_SOC_DAPM_INPUT("AMIC1"), 5480 SND_SOC_DAPM_INPUT("AMIC2"), 5481 SND_SOC_DAPM_INPUT("AMIC3"), 5482 SND_SOC_DAPM_INPUT("AMIC4"), 5483 SND_SOC_DAPM_INPUT("AMIC5"), 5484 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5485 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5486 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5487 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5488 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5489 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5490 5491 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5492 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5493 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5494 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5495 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5496 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5497 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5498 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5499 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5500 5501 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5502 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5503 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5504 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5505 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5506 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5507 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5508 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5509 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5510 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5511 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5512 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5513 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5514 5515 /* Digital Mic Inputs */ 5516 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5517 wcd934x_codec_enable_dmic, 5518 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5519 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5520 wcd934x_codec_enable_dmic, 5521 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5522 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5523 wcd934x_codec_enable_dmic, 5524 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5525 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5526 wcd934x_codec_enable_dmic, 5527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5528 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5529 wcd934x_codec_enable_dmic, 5530 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5531 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5532 wcd934x_codec_enable_dmic, 5533 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5534 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5535 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5536 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5537 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5538 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5539 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5540 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5541 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5542 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5543 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5544 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5545 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5546 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5547 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5548 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5549 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5550 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5551 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5552 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5553 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5555 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5556 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5557 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5558 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5559 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5560 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5561 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5563 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5564 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5565 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5567 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5568 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5569 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5571 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5572 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5573 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5574 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5575 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5576 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5577 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5578 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5579 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5580 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5581 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5582 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5583 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5584 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5585 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5586 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5587 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5588 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5589 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5590 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5591 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5592 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5593 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5594 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5595 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5596 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5597 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5598 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5599 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5600 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5601 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5602 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5603 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5604 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5605 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5606 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5607 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5608 5609 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5610 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5611 &cdc_if_tx0_mux), 5612 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5613 &cdc_if_tx1_mux), 5614 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5615 &cdc_if_tx2_mux), 5616 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5617 &cdc_if_tx3_mux), 5618 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5619 &cdc_if_tx4_mux), 5620 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5621 &cdc_if_tx5_mux), 5622 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5623 &cdc_if_tx6_mux), 5624 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5625 &cdc_if_tx7_mux), 5626 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5627 &cdc_if_tx8_mux), 5628 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5629 &cdc_if_tx9_mux), 5630 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5631 &cdc_if_tx10_mux), 5632 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5633 &cdc_if_tx11_mux), 5634 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5635 &cdc_if_tx11_inp1_mux), 5636 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5637 &cdc_if_tx13_mux), 5638 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5639 &cdc_if_tx13_inp1_mux), 5640 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5641 aif1_slim_cap_mixer, 5642 ARRAY_SIZE(aif1_slim_cap_mixer)), 5643 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5644 aif2_slim_cap_mixer, 5645 ARRAY_SIZE(aif2_slim_cap_mixer)), 5646 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5647 aif3_slim_cap_mixer, 5648 ARRAY_SIZE(aif3_slim_cap_mixer)), 5649 }; 5650 5651 static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5652 /* RX0-RX7 */ 5653 WCD934X_SLIM_RX_AIF_PATH(0), 5654 WCD934X_SLIM_RX_AIF_PATH(1), 5655 WCD934X_SLIM_RX_AIF_PATH(2), 5656 WCD934X_SLIM_RX_AIF_PATH(3), 5657 WCD934X_SLIM_RX_AIF_PATH(4), 5658 WCD934X_SLIM_RX_AIF_PATH(5), 5659 WCD934X_SLIM_RX_AIF_PATH(6), 5660 WCD934X_SLIM_RX_AIF_PATH(7), 5661 5662 /* RX0 Ear out */ 5663 WCD934X_INTERPOLATOR_PATH(0), 5664 WCD934X_INTERPOLATOR_MIX2(0), 5665 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5666 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5667 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5668 {"EAR PA", NULL, "RX INT0 DAC"}, 5669 {"EAR", NULL, "EAR PA"}, 5670 5671 /* RX1 Headphone left */ 5672 WCD934X_INTERPOLATOR_PATH(1), 5673 WCD934X_INTERPOLATOR_MIX2(1), 5674 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5675 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5676 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5677 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5678 {"HPHL PA", NULL, "RX INT1 DAC"}, 5679 {"HPHL", NULL, "HPHL PA"}, 5680 5681 /* RX2 Headphone right */ 5682 WCD934X_INTERPOLATOR_PATH(2), 5683 WCD934X_INTERPOLATOR_MIX2(2), 5684 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5685 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5686 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5687 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5688 {"HPHR PA", NULL, "RX INT2 DAC"}, 5689 {"HPHR", NULL, "HPHR PA"}, 5690 5691 /* RX3 HIFi LineOut1 */ 5692 WCD934X_INTERPOLATOR_PATH(3), 5693 WCD934X_INTERPOLATOR_MIX2(3), 5694 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5695 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5696 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5697 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5698 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5699 5700 /* RX4 HIFi LineOut2 */ 5701 WCD934X_INTERPOLATOR_PATH(4), 5702 WCD934X_INTERPOLATOR_MIX2(4), 5703 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5704 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5705 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5706 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5707 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5708 5709 /* RX7 Speaker Left Out PA */ 5710 WCD934X_INTERPOLATOR_PATH(7), 5711 WCD934X_INTERPOLATOR_MIX2(7), 5712 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5713 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5714 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5715 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5716 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5717 5718 /* RX8 Speaker Right Out PA */ 5719 WCD934X_INTERPOLATOR_PATH(8), 5720 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5721 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5722 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5723 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5724 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5725 5726 /* Tx */ 5727 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5728 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5729 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5730 5731 WCD934X_SLIM_TX_AIF_PATH(0), 5732 WCD934X_SLIM_TX_AIF_PATH(1), 5733 WCD934X_SLIM_TX_AIF_PATH(2), 5734 WCD934X_SLIM_TX_AIF_PATH(3), 5735 WCD934X_SLIM_TX_AIF_PATH(4), 5736 WCD934X_SLIM_TX_AIF_PATH(5), 5737 WCD934X_SLIM_TX_AIF_PATH(6), 5738 WCD934X_SLIM_TX_AIF_PATH(7), 5739 WCD934X_SLIM_TX_AIF_PATH(8), 5740 5741 WCD934X_ADC_MUX(0), 5742 WCD934X_ADC_MUX(1), 5743 WCD934X_ADC_MUX(2), 5744 WCD934X_ADC_MUX(3), 5745 WCD934X_ADC_MUX(4), 5746 WCD934X_ADC_MUX(5), 5747 WCD934X_ADC_MUX(6), 5748 WCD934X_ADC_MUX(7), 5749 WCD934X_ADC_MUX(8), 5750 5751 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5752 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5753 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5754 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5755 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5756 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5757 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5758 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5759 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5760 5761 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5762 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5763 5764 { "DMIC0", NULL, "DMIC0 Pin" }, 5765 { "DMIC1", NULL, "DMIC1 Pin" }, 5766 { "DMIC2", NULL, "DMIC2 Pin" }, 5767 { "DMIC3", NULL, "DMIC3 Pin" }, 5768 { "DMIC4", NULL, "DMIC4 Pin" }, 5769 { "DMIC5", NULL, "DMIC5 Pin" }, 5770 5771 {"ADC1", NULL, "AMIC1"}, 5772 {"ADC2", NULL, "AMIC2"}, 5773 {"ADC3", NULL, "AMIC3"}, 5774 {"ADC4", NULL, "AMIC4_5 SEL"}, 5775 5776 WCD934X_IIR_INP_MUX(0), 5777 WCD934X_IIR_INP_MUX(1), 5778 5779 {"SRC0", NULL, "IIR0"}, 5780 {"SRC1", NULL, "IIR1"}, 5781 }; 5782 5783 static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5784 struct snd_soc_jack *jack, void *data) 5785 { 5786 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5787 int ret = 0; 5788 5789 if (!wcd->mbhc) 5790 return -ENOTSUPP; 5791 5792 if (jack && !wcd->mbhc_started) { 5793 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5794 wcd->mbhc_started = true; 5795 } else if (wcd->mbhc_started) { 5796 wcd_mbhc_stop(wcd->mbhc); 5797 wcd->mbhc_started = false; 5798 } 5799 5800 return ret; 5801 } 5802 5803 static const struct snd_soc_component_driver wcd934x_component_drv = { 5804 .probe = wcd934x_comp_probe, 5805 .remove = wcd934x_comp_remove, 5806 .set_sysclk = wcd934x_comp_set_sysclk, 5807 .controls = wcd934x_snd_controls, 5808 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5809 .dapm_widgets = wcd934x_dapm_widgets, 5810 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5811 .dapm_routes = wcd934x_audio_map, 5812 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5813 .set_jack = wcd934x_codec_set_jack, 5814 }; 5815 5816 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5817 { 5818 struct device *dev = &wcd->sdev->dev; 5819 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5820 struct device_node *ifc_dev_np; 5821 5822 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5823 if (!ifc_dev_np) { 5824 dev_err(dev, "No Interface device found\n"); 5825 return -EINVAL; 5826 } 5827 5828 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5829 if (!wcd->sidev) { 5830 dev_err(dev, "Unable to get SLIM Interface device\n"); 5831 return -EINVAL; 5832 } 5833 5834 slim_get_logical_addr(wcd->sidev); 5835 wcd->if_regmap = regmap_init_slimbus(wcd->sidev, 5836 &wcd934x_ifc_regmap_config); 5837 if (IS_ERR(wcd->if_regmap)) { 5838 dev_err(dev, "Failed to allocate ifc register map\n"); 5839 return PTR_ERR(wcd->if_regmap); 5840 } 5841 5842 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5843 &wcd->dmic_sample_rate); 5844 5845 cfg->mbhc_micbias = MIC_BIAS_2; 5846 cfg->anc_micbias = MIC_BIAS_2; 5847 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5848 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5849 cfg->micb_mv = wcd->micb2_mv; 5850 cfg->linein_th = 5000; 5851 cfg->hs_thr = 1700; 5852 cfg->hph_thr = 50; 5853 5854 wcd_dt_parse_mbhc_data(dev, cfg); 5855 5856 5857 return 0; 5858 } 5859 5860 static int wcd934x_codec_probe(struct platform_device *pdev) 5861 { 5862 struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent); 5863 struct wcd934x_codec *wcd; 5864 struct device *dev = &pdev->dev; 5865 int ret, irq; 5866 5867 wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL); 5868 if (!wcd) 5869 return -ENOMEM; 5870 5871 wcd->dev = dev; 5872 wcd->regmap = data->regmap; 5873 wcd->extclk = data->extclk; 5874 wcd->sdev = to_slim_device(data->dev); 5875 mutex_init(&wcd->sysclk_mutex); 5876 mutex_init(&wcd->micb_lock); 5877 5878 ret = wcd934x_codec_parse_data(wcd); 5879 if (ret) { 5880 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5881 return ret; 5882 } 5883 5884 /* set default rate 9P6MHz */ 5885 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5886 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5887 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5888 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5889 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5890 5891 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5892 if (irq < 0) { 5893 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5894 return irq; 5895 } 5896 5897 ret = devm_request_threaded_irq(dev, irq, NULL, 5898 wcd934x_slim_irq_handler, 5899 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5900 "slim", wcd); 5901 if (ret) { 5902 dev_err(dev, "Failed to request slimbus irq\n"); 5903 return ret; 5904 } 5905 5906 wcd934x_register_mclk_output(wcd); 5907 platform_set_drvdata(pdev, wcd); 5908 5909 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5910 wcd934x_slim_dais, 5911 ARRAY_SIZE(wcd934x_slim_dais)); 5912 } 5913 5914 static const struct platform_device_id wcd934x_driver_id[] = { 5915 { 5916 .name = "wcd934x-codec", 5917 }, 5918 {}, 5919 }; 5920 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5921 5922 static struct platform_driver wcd934x_codec_driver = { 5923 .probe = &wcd934x_codec_probe, 5924 .id_table = wcd934x_driver_id, 5925 .driver = { 5926 .name = "wcd934x-codec", 5927 } 5928 }; 5929 5930 MODULE_ALIAS("platform:wcd934x-codec"); 5931 module_platform_driver(wcd934x_codec_driver); 5932 MODULE_DESCRIPTION("WCD934x codec driver"); 5933 MODULE_LICENSE("GPL v2"); 5934