1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/interrupt.h> 7 #include <linux/kernel.h> 8 #include <linux/mfd/wcd934x/registers.h> 9 #include <linux/mfd/wcd934x/wcd934x.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/of_clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/slimbus.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/tlv.h> 23 #include "wcd-clsh-v2.h" 24 #include "wcd-mbhc-v2.h" 25 26 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 27 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 28 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 29 /* Fractional Rates */ 30 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 31 SNDRV_PCM_RATE_176400) 32 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD934X_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD934X_SLIM_NUM_PORT_REG 3 50 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 51 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 52 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 53 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 54 55 #define WCD934X_MCLK_CLK_12P288MHZ 12288000 56 #define WCD934X_MCLK_CLK_9P6MHZ 9600000 57 58 /* Only valid for 9.6 MHz mclk */ 59 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 60 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 61 62 /* Only valid for 12.288 MHz mclk */ 63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 64 65 #define WCD934X_DMIC_CLK_DIV_2 0x0 66 #define WCD934X_DMIC_CLK_DIV_3 0x1 67 #define WCD934X_DMIC_CLK_DIV_4 0x2 68 #define WCD934X_DMIC_CLK_DIV_6 0x3 69 #define WCD934X_DMIC_CLK_DIV_8 0x4 70 #define WCD934X_DMIC_CLK_DIV_16 0x5 71 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 72 73 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 74 #define CF_MIN_3DB_4HZ 0x0 75 #define CF_MIN_3DB_75HZ 0x1 76 #define CF_MIN_3DB_150HZ 0x2 77 78 #define WCD934X_RX_START 16 79 #define WCD934X_NUM_INTERPOLATORS 9 80 #define WCD934X_RX_PATH_CTL_OFFSET 20 81 #define WCD934X_MAX_VALID_ADC_MUX 13 82 #define WCD934X_INVALID_ADC_MUX 9 83 84 #define WCD934X_SLIM_RX_CH(p) \ 85 {.port = p + WCD934X_RX_START, .shift = p,} 86 87 #define WCD934X_SLIM_TX_CH(p) \ 88 {.port = p, .shift = p,} 89 90 /* Feature masks to distinguish codec version */ 91 #define DSD_DISABLED_MASK 0 92 #define SLNQ_DISABLED_MASK 1 93 94 #define DSD_DISABLED BIT(DSD_DISABLED_MASK) 95 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 96 97 /* As fine version info cannot be retrieved before wcd probe. 98 * Define three coarse versions for possible future use before wcd probe. 99 */ 100 #define WCD_VERSION_WCD9340_1_0 0x400 101 #define WCD_VERSION_WCD9341_1_0 0x410 102 #define WCD_VERSION_WCD9340_1_1 0x401 103 #define WCD_VERSION_WCD9341_1_1 0x411 104 #define WCD934X_AMIC_PWR_LEVEL_LP 0 105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 106 #define WCD934X_AMIC_PWR_LEVEL_HP 2 107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 108 #define WCD934X_AMIC_PWR_LVL_MASK 0x60 109 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 110 111 #define WCD934X_DEC_PWR_LVL_MASK 0x06 112 #define WCD934X_DEC_PWR_LVL_LP 0x02 113 #define WCD934X_DEC_PWR_LVL_HP 0x04 114 #define WCD934X_DEC_PWR_LVL_DF 0x00 115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 116 117 #define WCD934X_DEF_MICBIAS_MV 1800 118 #define WCD934X_MAX_MICBIAS_MV 2850 119 120 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 121 122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 123 { \ 124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 125 .info = wcd934x_iir_filter_info, \ 126 .get = wcd934x_get_iir_band_audio_mixer, \ 127 .put = wcd934x_put_iir_band_audio_mixer, \ 128 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 129 .iir_idx = iidx, \ 130 .band_idx = bidx, \ 131 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 132 } \ 133 } 134 135 /* Z value defined in milliohm */ 136 #define WCD934X_ZDET_VAL_32 32000 137 #define WCD934X_ZDET_VAL_400 400000 138 #define WCD934X_ZDET_VAL_1200 1200000 139 #define WCD934X_ZDET_VAL_100K 100000000 140 /* Z floating defined in ohms */ 141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 142 143 #define WCD934X_ZDET_NUM_MEASUREMENTS 900 144 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 145 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 146 /* Z value compared in milliOhm */ 147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 148 #define WCD934X_MBHC_ZDET_CONST (86 * 16384) 149 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 150 #define WCD934X_MBHC_MAX_BUTTONS (8) 151 #define WCD_MBHC_HS_V_MAX 1600 152 153 #define WCD934X_INTERPOLATOR_PATH(id) \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 192 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 193 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 194 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 196 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 197 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 198 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 201 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 202 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 203 204 #define WCD934X_INTERPOLATOR_MIX2(id) \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 206 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 207 208 #define WCD934X_SLIM_RX_AIF_PATH(id) \ 209 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 212 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 213 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 214 215 #define WCD934X_ADC_MUX(id) \ 216 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 217 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 218 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 219 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 220 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 221 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 222 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 223 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 224 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 225 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 226 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 227 {"AMIC MUX" #id, "ADC4", "ADC4"} 228 229 #define WCD934X_IIR_INP_MUX(id) \ 230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 238 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 239 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 240 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 241 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 242 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 243 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 244 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 245 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 246 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 247 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 248 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 249 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 250 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 251 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 252 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 253 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 254 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 255 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 256 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 257 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 258 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 259 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 260 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 261 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 262 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 263 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 264 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 265 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 266 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 267 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 268 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 269 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 270 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 271 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 272 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 273 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 274 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 275 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 276 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 277 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 278 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 279 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 280 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 281 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 282 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 283 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 284 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 285 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 286 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 287 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 288 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 289 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 290 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 291 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 292 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 293 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 294 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 295 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 296 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 297 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 298 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 299 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 300 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 301 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 302 303 #define WCD934X_SLIM_TX_AIF_PATH(id) \ 304 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 307 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 308 309 #define WCD934X_MAX_MICBIAS MIC_BIAS_4 310 311 enum { 312 SIDO_SOURCE_INTERNAL, 313 SIDO_SOURCE_RCO_BG, 314 }; 315 316 enum { 317 INTERP_EAR = 0, 318 INTERP_HPHL, 319 INTERP_HPHR, 320 INTERP_LO1, 321 INTERP_LO2, 322 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 323 INTERP_LO4_NA, 324 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 325 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 326 INTERP_MAX, 327 }; 328 329 enum { 330 WCD934X_RX0 = 0, 331 WCD934X_RX1, 332 WCD934X_RX2, 333 WCD934X_RX3, 334 WCD934X_RX4, 335 WCD934X_RX5, 336 WCD934X_RX6, 337 WCD934X_RX7, 338 WCD934X_RX8, 339 WCD934X_RX9, 340 WCD934X_RX10, 341 WCD934X_RX11, 342 WCD934X_RX12, 343 WCD934X_RX_MAX, 344 }; 345 346 enum { 347 WCD934X_TX0 = 0, 348 WCD934X_TX1, 349 WCD934X_TX2, 350 WCD934X_TX3, 351 WCD934X_TX4, 352 WCD934X_TX5, 353 WCD934X_TX6, 354 WCD934X_TX7, 355 WCD934X_TX8, 356 WCD934X_TX9, 357 WCD934X_TX10, 358 WCD934X_TX11, 359 WCD934X_TX12, 360 WCD934X_TX13, 361 WCD934X_TX14, 362 WCD934X_TX15, 363 WCD934X_TX_MAX, 364 }; 365 366 struct wcd934x_slim_ch { 367 u32 ch_num; 368 u16 port; 369 u16 shift; 370 struct list_head list; 371 }; 372 373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 374 WCD934X_SLIM_TX_CH(0), 375 WCD934X_SLIM_TX_CH(1), 376 WCD934X_SLIM_TX_CH(2), 377 WCD934X_SLIM_TX_CH(3), 378 WCD934X_SLIM_TX_CH(4), 379 WCD934X_SLIM_TX_CH(5), 380 WCD934X_SLIM_TX_CH(6), 381 WCD934X_SLIM_TX_CH(7), 382 WCD934X_SLIM_TX_CH(8), 383 WCD934X_SLIM_TX_CH(9), 384 WCD934X_SLIM_TX_CH(10), 385 WCD934X_SLIM_TX_CH(11), 386 WCD934X_SLIM_TX_CH(12), 387 WCD934X_SLIM_TX_CH(13), 388 WCD934X_SLIM_TX_CH(14), 389 WCD934X_SLIM_TX_CH(15), 390 }; 391 392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 393 WCD934X_SLIM_RX_CH(0), /* 16 */ 394 WCD934X_SLIM_RX_CH(1), /* 17 */ 395 WCD934X_SLIM_RX_CH(2), 396 WCD934X_SLIM_RX_CH(3), 397 WCD934X_SLIM_RX_CH(4), 398 WCD934X_SLIM_RX_CH(5), 399 WCD934X_SLIM_RX_CH(6), 400 WCD934X_SLIM_RX_CH(7), 401 WCD934X_SLIM_RX_CH(8), 402 WCD934X_SLIM_RX_CH(9), 403 WCD934X_SLIM_RX_CH(10), 404 WCD934X_SLIM_RX_CH(11), 405 WCD934X_SLIM_RX_CH(12), 406 }; 407 408 /* Codec supports 2 IIR filters */ 409 enum { 410 IIR0 = 0, 411 IIR1, 412 IIR_MAX, 413 }; 414 415 /* Each IIR has 5 Filter Stages */ 416 enum { 417 BAND1 = 0, 418 BAND2, 419 BAND3, 420 BAND4, 421 BAND5, 422 BAND_MAX, 423 }; 424 425 enum { 426 COMPANDER_1, /* HPH_L */ 427 COMPANDER_2, /* HPH_R */ 428 COMPANDER_3, /* LO1_DIFF */ 429 COMPANDER_4, /* LO2_DIFF */ 430 COMPANDER_5, /* LO3_SE - not used in Tavil */ 431 COMPANDER_6, /* LO4_SE - not used in Tavil */ 432 COMPANDER_7, /* SWR SPK CH1 */ 433 COMPANDER_8, /* SWR SPK CH2 */ 434 COMPANDER_MAX, 435 }; 436 437 enum { 438 AIF1_PB = 0, 439 AIF1_CAP, 440 AIF2_PB, 441 AIF2_CAP, 442 AIF3_PB, 443 AIF3_CAP, 444 AIF4_PB, 445 AIF4_VIFEED, 446 AIF4_MAD_TX, 447 NUM_CODEC_DAIS, 448 }; 449 450 enum { 451 INTn_1_INP_SEL_ZERO = 0, 452 INTn_1_INP_SEL_DEC0, 453 INTn_1_INP_SEL_DEC1, 454 INTn_1_INP_SEL_IIR0, 455 INTn_1_INP_SEL_IIR1, 456 INTn_1_INP_SEL_RX0, 457 INTn_1_INP_SEL_RX1, 458 INTn_1_INP_SEL_RX2, 459 INTn_1_INP_SEL_RX3, 460 INTn_1_INP_SEL_RX4, 461 INTn_1_INP_SEL_RX5, 462 INTn_1_INP_SEL_RX6, 463 INTn_1_INP_SEL_RX7, 464 }; 465 466 enum { 467 INTn_2_INP_SEL_ZERO = 0, 468 INTn_2_INP_SEL_RX0, 469 INTn_2_INP_SEL_RX1, 470 INTn_2_INP_SEL_RX2, 471 INTn_2_INP_SEL_RX3, 472 INTn_2_INP_SEL_RX4, 473 INTn_2_INP_SEL_RX5, 474 INTn_2_INP_SEL_RX6, 475 INTn_2_INP_SEL_RX7, 476 INTn_2_INP_SEL_PROXIMITY, 477 }; 478 479 enum { 480 INTERP_MAIN_PATH, 481 INTERP_MIX_PATH, 482 }; 483 484 struct interp_sample_rate { 485 int sample_rate; 486 int rate_val; 487 }; 488 489 static struct interp_sample_rate sr_val_tbl[] = { 490 {8000, 0x0}, 491 {16000, 0x1}, 492 {32000, 0x3}, 493 {48000, 0x4}, 494 {96000, 0x5}, 495 {192000, 0x6}, 496 {384000, 0x7}, 497 {44100, 0x9}, 498 {88200, 0xA}, 499 {176400, 0xB}, 500 {352800, 0xC}, 501 }; 502 503 struct wcd934x_mbhc_zdet_param { 504 u16 ldo_ctl; 505 u16 noff; 506 u16 nshift; 507 u16 btn5; 508 u16 btn6; 509 u16 btn7; 510 }; 511 512 struct wcd_slim_codec_dai_data { 513 struct list_head slim_ch_list; 514 struct slim_stream_config sconfig; 515 struct slim_stream_runtime *sruntime; 516 }; 517 518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 519 { 520 .name = "WCD9335-IFC-DEV", 521 .range_min = 0x0, 522 .range_max = 0xffff, 523 .selector_reg = 0x800, 524 .selector_mask = 0xfff, 525 .selector_shift = 0, 526 .window_start = 0x800, 527 .window_len = 0x400, 528 }, 529 }; 530 531 static struct regmap_config wcd934x_ifc_regmap_config = { 532 .reg_bits = 16, 533 .val_bits = 8, 534 .max_register = 0xffff, 535 .ranges = wcd934x_ifc_ranges, 536 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 537 }; 538 539 struct wcd934x_codec { 540 struct device *dev; 541 struct clk_hw hw; 542 struct clk *extclk; 543 struct regmap *regmap; 544 struct regmap *if_regmap; 545 struct slim_device *sdev; 546 struct slim_device *sidev; 547 struct wcd_clsh_ctrl *clsh_ctrl; 548 struct snd_soc_component *component; 549 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 550 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 551 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 552 int rate; 553 u32 version; 554 u32 hph_mode; 555 int num_rx_port; 556 int num_tx_port; 557 u32 tx_port_value[WCD934X_TX_MAX]; 558 u32 rx_port_value[WCD934X_RX_MAX]; 559 int sido_input_src; 560 int dmic_0_1_clk_cnt; 561 int dmic_2_3_clk_cnt; 562 int dmic_4_5_clk_cnt; 563 int dmic_sample_rate; 564 int comp_enabled[COMPANDER_MAX]; 565 int sysclk_users; 566 struct mutex sysclk_mutex; 567 /* mbhc module */ 568 struct wcd_mbhc *mbhc; 569 struct wcd_mbhc_config mbhc_cfg; 570 struct wcd_mbhc_intr intr_ids; 571 bool mbhc_started; 572 struct mutex micb_lock; 573 u32 micb_ref[WCD934X_MAX_MICBIAS]; 574 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 575 u32 micb1_mv; 576 u32 micb2_mv; 577 u32 micb3_mv; 578 u32 micb4_mv; 579 }; 580 581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 582 583 struct wcd_iir_filter_ctl { 584 unsigned int iir_idx; 585 unsigned int band_idx; 586 struct soc_bytes_ext bytes_ext; 587 }; 588 589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 593 594 /* Cutoff frequency for high pass filter */ 595 static const char * const cf_text[] = { 596 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 597 }; 598 599 static const char * const rx_cf_text[] = { 600 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 601 "CF_NEG_3DB_0P48HZ" 602 }; 603 604 static const char * const rx_hph_mode_mux_text[] = { 605 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 606 "Class-H Hi-Fi Low Power" 607 }; 608 609 static const char *const slim_rx_mux_text[] = { 610 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 611 }; 612 613 static const char * const rx_int0_7_mix_mux_text[] = { 614 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 615 "RX6", "RX7", "PROXIMITY" 616 }; 617 618 static const char * const rx_int_mix_mux_text[] = { 619 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 620 "RX6", "RX7" 621 }; 622 623 static const char * const rx_prim_mix_text[] = { 624 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 625 "RX3", "RX4", "RX5", "RX6", "RX7" 626 }; 627 628 static const char * const rx_sidetone_mix_text[] = { 629 "ZERO", "SRC0", "SRC1", "SRC_SUM" 630 }; 631 632 static const char * const iir_inp_mux_text[] = { 633 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 634 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 635 }; 636 637 static const char * const rx_int_dem_inp_mux_text[] = { 638 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 639 }; 640 641 static const char * const rx_int0_1_interp_mux_text[] = { 642 "ZERO", "RX INT0_1 MIX1", 643 }; 644 645 static const char * const rx_int1_1_interp_mux_text[] = { 646 "ZERO", "RX INT1_1 MIX1", 647 }; 648 649 static const char * const rx_int2_1_interp_mux_text[] = { 650 "ZERO", "RX INT2_1 MIX1", 651 }; 652 653 static const char * const rx_int3_1_interp_mux_text[] = { 654 "ZERO", "RX INT3_1 MIX1", 655 }; 656 657 static const char * const rx_int4_1_interp_mux_text[] = { 658 "ZERO", "RX INT4_1 MIX1", 659 }; 660 661 static const char * const rx_int7_1_interp_mux_text[] = { 662 "ZERO", "RX INT7_1 MIX1", 663 }; 664 665 static const char * const rx_int8_1_interp_mux_text[] = { 666 "ZERO", "RX INT8_1 MIX1", 667 }; 668 669 static const char * const rx_int0_2_interp_mux_text[] = { 670 "ZERO", "RX INT0_2 MUX", 671 }; 672 673 static const char * const rx_int1_2_interp_mux_text[] = { 674 "ZERO", "RX INT1_2 MUX", 675 }; 676 677 static const char * const rx_int2_2_interp_mux_text[] = { 678 "ZERO", "RX INT2_2 MUX", 679 }; 680 681 static const char * const rx_int3_2_interp_mux_text[] = { 682 "ZERO", "RX INT3_2 MUX", 683 }; 684 685 static const char * const rx_int4_2_interp_mux_text[] = { 686 "ZERO", "RX INT4_2 MUX", 687 }; 688 689 static const char * const rx_int7_2_interp_mux_text[] = { 690 "ZERO", "RX INT7_2 MUX", 691 }; 692 693 static const char * const rx_int8_2_interp_mux_text[] = { 694 "ZERO", "RX INT8_2 MUX", 695 }; 696 697 static const char * const dmic_mux_text[] = { 698 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 699 }; 700 701 static const char * const amic_mux_text[] = { 702 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 703 }; 704 705 static const char * const amic4_5_sel_text[] = { 706 "AMIC4", "AMIC5" 707 }; 708 709 static const char * const adc_mux_text[] = { 710 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 711 }; 712 713 static const char * const cdc_if_tx0_mux_text[] = { 714 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 715 }; 716 717 static const char * const cdc_if_tx1_mux_text[] = { 718 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 719 }; 720 721 static const char * const cdc_if_tx2_mux_text[] = { 722 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 723 }; 724 725 static const char * const cdc_if_tx3_mux_text[] = { 726 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 727 }; 728 729 static const char * const cdc_if_tx4_mux_text[] = { 730 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 731 }; 732 733 static const char * const cdc_if_tx5_mux_text[] = { 734 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 735 }; 736 737 static const char * const cdc_if_tx6_mux_text[] = { 738 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 739 }; 740 741 static const char * const cdc_if_tx7_mux_text[] = { 742 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 743 }; 744 745 static const char * const cdc_if_tx8_mux_text[] = { 746 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 747 }; 748 749 static const char * const cdc_if_tx9_mux_text[] = { 750 "ZERO", "DEC7", "DEC7_192" 751 }; 752 753 static const char * const cdc_if_tx10_mux_text[] = { 754 "ZERO", "DEC6", "DEC6_192" 755 }; 756 757 static const char * const cdc_if_tx11_mux_text[] = { 758 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 759 }; 760 761 static const char * const cdc_if_tx11_inp1_mux_text[] = { 762 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 763 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 764 }; 765 766 static const char * const cdc_if_tx13_mux_text[] = { 767 "CDC_DEC_5", "MAD_BRDCST" 768 }; 769 770 static const char * const cdc_if_tx13_inp1_mux_text[] = { 771 "ZERO", "DEC5", "DEC5_192" 772 }; 773 774 static const struct soc_enum cf_dec0_enum = 775 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 776 777 static const struct soc_enum cf_dec1_enum = 778 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 779 780 static const struct soc_enum cf_dec2_enum = 781 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 782 783 static const struct soc_enum cf_dec3_enum = 784 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 785 786 static const struct soc_enum cf_dec4_enum = 787 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 788 789 static const struct soc_enum cf_dec5_enum = 790 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 791 792 static const struct soc_enum cf_dec6_enum = 793 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 794 795 static const struct soc_enum cf_dec7_enum = 796 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 797 798 static const struct soc_enum cf_dec8_enum = 799 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 800 801 static const struct soc_enum cf_int0_1_enum = 802 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 803 804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 805 rx_cf_text); 806 807 static const struct soc_enum cf_int1_1_enum = 808 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 809 810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 811 rx_cf_text); 812 813 static const struct soc_enum cf_int2_1_enum = 814 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 815 816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 817 rx_cf_text); 818 819 static const struct soc_enum cf_int3_1_enum = 820 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 821 822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 823 rx_cf_text); 824 825 static const struct soc_enum cf_int4_1_enum = 826 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 827 828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 829 rx_cf_text); 830 831 static const struct soc_enum cf_int7_1_enum = 832 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 833 834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 835 rx_cf_text); 836 837 static const struct soc_enum cf_int8_1_enum = 838 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 839 840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 841 rx_cf_text); 842 843 static const struct soc_enum rx_hph_mode_mux_enum = 844 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 845 rx_hph_mode_mux_text); 846 847 static const struct soc_enum slim_rx_mux_enum = 848 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 849 850 static const struct soc_enum rx_int0_2_mux_chain_enum = 851 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 852 rx_int0_7_mix_mux_text); 853 854 static const struct soc_enum rx_int1_2_mux_chain_enum = 855 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 856 rx_int_mix_mux_text); 857 858 static const struct soc_enum rx_int2_2_mux_chain_enum = 859 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 860 rx_int_mix_mux_text); 861 862 static const struct soc_enum rx_int3_2_mux_chain_enum = 863 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 864 rx_int_mix_mux_text); 865 866 static const struct soc_enum rx_int4_2_mux_chain_enum = 867 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 868 rx_int_mix_mux_text); 869 870 static const struct soc_enum rx_int7_2_mux_chain_enum = 871 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 872 rx_int0_7_mix_mux_text); 873 874 static const struct soc_enum rx_int8_2_mux_chain_enum = 875 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 876 rx_int_mix_mux_text); 877 878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 879 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 880 rx_prim_mix_text); 881 882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 883 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 884 rx_prim_mix_text); 885 886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 887 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 888 rx_prim_mix_text); 889 890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 891 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 892 rx_prim_mix_text); 893 894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 895 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 896 rx_prim_mix_text); 897 898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 899 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 900 rx_prim_mix_text); 901 902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 903 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 904 rx_prim_mix_text); 905 906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 907 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 908 rx_prim_mix_text); 909 910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 911 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 912 rx_prim_mix_text); 913 914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 915 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 916 rx_prim_mix_text); 917 918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 919 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 920 rx_prim_mix_text); 921 922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 923 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 924 rx_prim_mix_text); 925 926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 927 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 928 rx_prim_mix_text); 929 930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 931 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 932 rx_prim_mix_text); 933 934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 935 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 936 rx_prim_mix_text); 937 938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 939 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 940 rx_prim_mix_text); 941 942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 943 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 944 rx_prim_mix_text); 945 946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 947 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 948 rx_prim_mix_text); 949 950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 951 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 952 rx_prim_mix_text); 953 954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 955 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 956 rx_prim_mix_text); 957 958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 959 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 960 rx_prim_mix_text); 961 962 static const struct soc_enum rx_int0_mix2_inp_mux_enum = 963 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 964 rx_sidetone_mix_text); 965 966 static const struct soc_enum rx_int1_mix2_inp_mux_enum = 967 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 968 rx_sidetone_mix_text); 969 970 static const struct soc_enum rx_int2_mix2_inp_mux_enum = 971 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 972 rx_sidetone_mix_text); 973 974 static const struct soc_enum rx_int3_mix2_inp_mux_enum = 975 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 976 rx_sidetone_mix_text); 977 978 static const struct soc_enum rx_int4_mix2_inp_mux_enum = 979 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 980 rx_sidetone_mix_text); 981 982 static const struct soc_enum rx_int7_mix2_inp_mux_enum = 983 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 984 rx_sidetone_mix_text); 985 986 static const struct soc_enum iir0_inp0_mux_enum = 987 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 988 0, 18, iir_inp_mux_text); 989 990 static const struct soc_enum iir0_inp1_mux_enum = 991 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 992 0, 18, iir_inp_mux_text); 993 994 static const struct soc_enum iir0_inp2_mux_enum = 995 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 996 0, 18, iir_inp_mux_text); 997 998 static const struct soc_enum iir0_inp3_mux_enum = 999 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 1000 0, 18, iir_inp_mux_text); 1001 1002 static const struct soc_enum iir1_inp0_mux_enum = 1003 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 1004 0, 18, iir_inp_mux_text); 1005 1006 static const struct soc_enum iir1_inp1_mux_enum = 1007 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 1008 0, 18, iir_inp_mux_text); 1009 1010 static const struct soc_enum iir1_inp2_mux_enum = 1011 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 1012 0, 18, iir_inp_mux_text); 1013 1014 static const struct soc_enum iir1_inp3_mux_enum = 1015 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 1016 0, 18, iir_inp_mux_text); 1017 1018 static const struct soc_enum rx_int0_dem_inp_mux_enum = 1019 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 1020 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1021 rx_int_dem_inp_mux_text); 1022 1023 static const struct soc_enum rx_int1_dem_inp_mux_enum = 1024 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1025 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1026 rx_int_dem_inp_mux_text); 1027 1028 static const struct soc_enum rx_int2_dem_inp_mux_enum = 1029 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1030 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1031 rx_int_dem_inp_mux_text); 1032 1033 static const struct soc_enum tx_adc_mux0_enum = 1034 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1035 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1036 static const struct soc_enum tx_adc_mux1_enum = 1037 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1038 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1039 static const struct soc_enum tx_adc_mux2_enum = 1040 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1041 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1042 static const struct soc_enum tx_adc_mux3_enum = 1043 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1044 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1045 static const struct soc_enum tx_adc_mux4_enum = 1046 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1047 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1048 static const struct soc_enum tx_adc_mux5_enum = 1049 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1050 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1051 static const struct soc_enum tx_adc_mux6_enum = 1052 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1053 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1054 static const struct soc_enum tx_adc_mux7_enum = 1055 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1056 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1057 static const struct soc_enum tx_adc_mux8_enum = 1058 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1059 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1060 1061 static const struct soc_enum rx_int0_1_interp_mux_enum = 1062 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1063 rx_int0_1_interp_mux_text); 1064 1065 static const struct soc_enum rx_int1_1_interp_mux_enum = 1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1067 rx_int1_1_interp_mux_text); 1068 1069 static const struct soc_enum rx_int2_1_interp_mux_enum = 1070 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1071 rx_int2_1_interp_mux_text); 1072 1073 static const struct soc_enum rx_int3_1_interp_mux_enum = 1074 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1075 1076 static const struct soc_enum rx_int4_1_interp_mux_enum = 1077 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1078 1079 static const struct soc_enum rx_int7_1_interp_mux_enum = 1080 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1081 1082 static const struct soc_enum rx_int8_1_interp_mux_enum = 1083 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1084 1085 static const struct soc_enum rx_int0_2_interp_mux_enum = 1086 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1087 1088 static const struct soc_enum rx_int1_2_interp_mux_enum = 1089 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1090 1091 static const struct soc_enum rx_int2_2_interp_mux_enum = 1092 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1093 1094 static const struct soc_enum rx_int3_2_interp_mux_enum = 1095 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1096 1097 static const struct soc_enum rx_int4_2_interp_mux_enum = 1098 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1099 1100 static const struct soc_enum rx_int7_2_interp_mux_enum = 1101 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1102 1103 static const struct soc_enum rx_int8_2_interp_mux_enum = 1104 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1105 1106 static const struct soc_enum tx_dmic_mux0_enum = 1107 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1108 dmic_mux_text); 1109 1110 static const struct soc_enum tx_dmic_mux1_enum = 1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1112 dmic_mux_text); 1113 1114 static const struct soc_enum tx_dmic_mux2_enum = 1115 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1116 dmic_mux_text); 1117 1118 static const struct soc_enum tx_dmic_mux3_enum = 1119 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1120 dmic_mux_text); 1121 1122 static const struct soc_enum tx_dmic_mux4_enum = 1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1124 dmic_mux_text); 1125 1126 static const struct soc_enum tx_dmic_mux5_enum = 1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1128 dmic_mux_text); 1129 1130 static const struct soc_enum tx_dmic_mux6_enum = 1131 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1132 dmic_mux_text); 1133 1134 static const struct soc_enum tx_dmic_mux7_enum = 1135 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1136 dmic_mux_text); 1137 1138 static const struct soc_enum tx_dmic_mux8_enum = 1139 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1140 dmic_mux_text); 1141 1142 static const struct soc_enum tx_amic_mux0_enum = 1143 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1144 amic_mux_text); 1145 static const struct soc_enum tx_amic_mux1_enum = 1146 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1147 amic_mux_text); 1148 static const struct soc_enum tx_amic_mux2_enum = 1149 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1150 amic_mux_text); 1151 static const struct soc_enum tx_amic_mux3_enum = 1152 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1153 amic_mux_text); 1154 static const struct soc_enum tx_amic_mux4_enum = 1155 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1156 amic_mux_text); 1157 static const struct soc_enum tx_amic_mux5_enum = 1158 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1159 amic_mux_text); 1160 static const struct soc_enum tx_amic_mux6_enum = 1161 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1162 amic_mux_text); 1163 static const struct soc_enum tx_amic_mux7_enum = 1164 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1165 amic_mux_text); 1166 static const struct soc_enum tx_amic_mux8_enum = 1167 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1168 amic_mux_text); 1169 1170 static const struct soc_enum tx_amic4_5_enum = 1171 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1172 1173 static const struct soc_enum cdc_if_tx0_mux_enum = 1174 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1175 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1176 static const struct soc_enum cdc_if_tx1_mux_enum = 1177 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1178 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1179 static const struct soc_enum cdc_if_tx2_mux_enum = 1180 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1181 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1182 static const struct soc_enum cdc_if_tx3_mux_enum = 1183 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1184 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1185 static const struct soc_enum cdc_if_tx4_mux_enum = 1186 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1187 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1188 static const struct soc_enum cdc_if_tx5_mux_enum = 1189 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1190 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1191 static const struct soc_enum cdc_if_tx6_mux_enum = 1192 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1193 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1194 static const struct soc_enum cdc_if_tx7_mux_enum = 1195 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1196 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1197 static const struct soc_enum cdc_if_tx8_mux_enum = 1198 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1199 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1200 static const struct soc_enum cdc_if_tx9_mux_enum = 1201 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1202 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1203 static const struct soc_enum cdc_if_tx10_mux_enum = 1204 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1205 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1207 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1208 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1209 cdc_if_tx11_inp1_mux_text); 1210 static const struct soc_enum cdc_if_tx11_mux_enum = 1211 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1212 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1214 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1215 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1216 cdc_if_tx13_inp1_mux_text); 1217 static const struct soc_enum cdc_if_tx13_mux_enum = 1218 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1219 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1220 1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1222 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1223 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1224 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1225 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1226 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1227 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1228 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1229 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1230 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1231 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1232 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1233 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1234 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1235 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1236 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1237 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1238 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1239 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1242 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1243 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1244 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1245 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1246 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1247 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1248 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1249 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1250 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1251 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1252 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1253 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1254 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1255 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1256 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1257 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1258 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1259 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1261 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1262 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1263 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1264 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1265 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1266 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1267 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1268 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1269 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1270 }; 1271 1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1273 { 1274 if (sido_src == wcd->sido_input_src) 1275 return 0; 1276 1277 if (sido_src == SIDO_SOURCE_INTERNAL) { 1278 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1279 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0); 1280 usleep_range(100, 110); 1281 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1282 WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0); 1283 usleep_range(100, 110); 1284 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1285 WCD934X_ANA_RCO_BG_EN_MASK, 0); 1286 usleep_range(100, 110); 1287 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1288 WCD934X_ANA_BUCK_PRE_EN1_MASK, 1289 WCD934X_ANA_BUCK_PRE_EN1_ENABLE); 1290 usleep_range(100, 110); 1291 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1292 WCD934X_ANA_BUCK_PRE_EN2_MASK, 1293 WCD934X_ANA_BUCK_PRE_EN2_ENABLE); 1294 usleep_range(100, 110); 1295 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL, 1296 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 1297 WCD934X_ANA_BUCK_HI_ACCU_ENABLE); 1298 usleep_range(100, 110); 1299 } else if (sido_src == SIDO_SOURCE_RCO_BG) { 1300 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1301 WCD934X_ANA_RCO_BG_EN_MASK, 1302 WCD934X_ANA_RCO_BG_ENABLE); 1303 usleep_range(100, 110); 1304 } 1305 wcd->sido_input_src = sido_src; 1306 1307 return 0; 1308 } 1309 1310 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1311 { 1312 mutex_lock(&wcd->sysclk_mutex); 1313 1314 if (++wcd->sysclk_users != 1) { 1315 mutex_unlock(&wcd->sysclk_mutex); 1316 return 0; 1317 } 1318 mutex_unlock(&wcd->sysclk_mutex); 1319 1320 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1321 WCD934X_ANA_BIAS_EN_MASK, 1322 WCD934X_ANA_BIAS_EN); 1323 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1324 WCD934X_ANA_PRECHRG_EN_MASK, 1325 WCD934X_ANA_PRECHRG_EN); 1326 /* 1327 * 1ms delay is required after pre-charge is enabled 1328 * as per HW requirement 1329 */ 1330 usleep_range(1000, 1100); 1331 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1332 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1333 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1334 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1335 1336 /* 1337 * In data clock contrl register is changed 1338 * to CLK_SYS_MCLK_PRG 1339 */ 1340 1341 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1342 WCD934X_EXT_CLK_BUF_EN_MASK, 1343 WCD934X_EXT_CLK_BUF_EN); 1344 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1345 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1346 WCD934X_EXT_CLK_DIV_BY_2); 1347 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1348 WCD934X_MCLK_SRC_MASK, 1349 WCD934X_MCLK_SRC_EXT_CLK); 1350 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1351 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1352 regmap_update_bits(wcd->regmap, 1353 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1354 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1355 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1356 regmap_update_bits(wcd->regmap, 1357 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1358 WCD934X_MCLK_EN_MASK, 1359 WCD934X_MCLK_EN); 1360 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1361 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1362 /* 1363 * 10us sleep is required after clock is enabled 1364 * as per HW requirement 1365 */ 1366 usleep_range(10, 15); 1367 1368 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1369 1370 return 0; 1371 } 1372 1373 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1374 { 1375 mutex_lock(&wcd->sysclk_mutex); 1376 if (--wcd->sysclk_users != 0) { 1377 mutex_unlock(&wcd->sysclk_mutex); 1378 return 0; 1379 } 1380 mutex_unlock(&wcd->sysclk_mutex); 1381 1382 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1383 WCD934X_EXT_CLK_BUF_EN_MASK | 1384 WCD934X_MCLK_EN_MASK, 0x0); 1385 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL); 1386 1387 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1388 WCD934X_ANA_BIAS_EN_MASK, 0); 1389 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1390 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1391 1392 return 0; 1393 } 1394 1395 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1396 { 1397 int ret = 0; 1398 1399 if (enable) { 1400 ret = clk_prepare_enable(wcd->extclk); 1401 1402 if (ret) { 1403 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1404 __func__); 1405 return ret; 1406 } 1407 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1408 } else { 1409 int val; 1410 1411 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1412 &val); 1413 1414 /* Don't disable clock if soundwire using it.*/ 1415 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1416 return 0; 1417 1418 wcd934x_disable_ana_bias_and_syclk(wcd); 1419 clk_disable_unprepare(wcd->extclk); 1420 } 1421 1422 return ret; 1423 } 1424 1425 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1426 struct snd_kcontrol *kc, int event) 1427 { 1428 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1429 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1430 1431 switch (event) { 1432 case SND_SOC_DAPM_PRE_PMU: 1433 return __wcd934x_cdc_mclk_enable(wcd, true); 1434 case SND_SOC_DAPM_POST_PMD: 1435 return __wcd934x_cdc_mclk_enable(wcd, false); 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int wcd934x_get_version(struct wcd934x_codec *wcd) 1442 { 1443 int val1, val2, ver, ret; 1444 struct regmap *regmap; 1445 u16 id_minor; 1446 u32 version_mask = 0; 1447 1448 regmap = wcd->regmap; 1449 ver = 0; 1450 1451 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1452 (u8 *)&id_minor, sizeof(u16)); 1453 1454 if (ret) 1455 return ret; 1456 1457 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1458 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1459 1460 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1461 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1462 1463 switch (version_mask) { 1464 case DSD_DISABLED | SLNQ_DISABLED: 1465 if (id_minor == 0) 1466 ver = WCD_VERSION_WCD9340_1_0; 1467 else if (id_minor == 0x01) 1468 ver = WCD_VERSION_WCD9340_1_1; 1469 break; 1470 case SLNQ_DISABLED: 1471 if (id_minor == 0) 1472 ver = WCD_VERSION_WCD9341_1_0; 1473 else if (id_minor == 0x01) 1474 ver = WCD_VERSION_WCD9341_1_1; 1475 break; 1476 } 1477 1478 wcd->version = ver; 1479 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1480 1481 return 0; 1482 } 1483 1484 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1485 { 1486 int rc, val; 1487 1488 __wcd934x_cdc_mclk_enable(wcd, true); 1489 1490 regmap_update_bits(wcd->regmap, 1491 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1492 WCD934X_EFUSE_SENSE_STATE_MASK, 1493 WCD934X_EFUSE_SENSE_STATE_DEF); 1494 regmap_update_bits(wcd->regmap, 1495 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1496 WCD934X_EFUSE_SENSE_EN_MASK, 1497 WCD934X_EFUSE_SENSE_ENABLE); 1498 /* 1499 * 5ms sleep required after enabling efuse control 1500 * before checking the status. 1501 */ 1502 usleep_range(5000, 5500); 1503 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1504 1505 rc = regmap_read(wcd->regmap, 1506 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1507 if (rc || (!(val & 0x01))) 1508 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1509 __func__, val, rc); 1510 1511 __wcd934x_cdc_mclk_enable(wcd, false); 1512 } 1513 1514 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1515 { 1516 if (enable) { 1517 __wcd934x_cdc_mclk_enable(wcd, true); 1518 regmap_update_bits(wcd->regmap, 1519 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1520 WCD934X_CDC_SWR_CLK_EN_MASK, 1521 WCD934X_CDC_SWR_CLK_ENABLE); 1522 } else { 1523 regmap_update_bits(wcd->regmap, 1524 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1525 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1526 __wcd934x_cdc_mclk_enable(wcd, false); 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1533 u8 rate_val, u32 rate) 1534 { 1535 struct snd_soc_component *comp = dai->component; 1536 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1537 struct wcd934x_slim_ch *ch; 1538 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1539 int inp, j; 1540 1541 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1542 inp = ch->shift + INTn_1_INP_SEL_RX0; 1543 /* 1544 * Loop through all interpolator MUX inputs and find out 1545 * to which interpolator input, the slim rx port 1546 * is connected 1547 */ 1548 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1549 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1550 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1551 continue; 1552 1553 cfg0 = snd_soc_component_read(comp, 1554 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1555 cfg1 = snd_soc_component_read(comp, 1556 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1557 1558 inp0_sel = cfg0 & 1559 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1560 inp1_sel = (cfg0 >> 4) & 1561 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1562 inp2_sel = (cfg1 >> 4) & 1563 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1564 1565 if ((inp0_sel == inp) || (inp1_sel == inp) || 1566 (inp2_sel == inp)) { 1567 /* rate is in Hz */ 1568 /* 1569 * Ear and speaker primary path does not support 1570 * native sample rates 1571 */ 1572 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1573 j == INTERP_SPKR2) && rate == 44100) 1574 dev_err(wcd->dev, 1575 "Cannot set 44.1KHz on INT%d\n", 1576 j); 1577 else 1578 snd_soc_component_update_bits(comp, 1579 WCD934X_CDC_RX_PATH_CTL(j), 1580 WCD934X_CDC_MIX_PCM_RATE_MASK, 1581 rate_val); 1582 } 1583 } 1584 } 1585 1586 return 0; 1587 } 1588 1589 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1590 int rate_val, u32 rate) 1591 { 1592 struct snd_soc_component *component = dai->component; 1593 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1594 struct wcd934x_slim_ch *ch; 1595 int val, j; 1596 1597 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1598 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1599 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1600 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1601 continue; 1602 val = snd_soc_component_read(component, 1603 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1604 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1605 1606 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1607 /* 1608 * Ear mix path supports only 48, 96, 192, 1609 * 384KHz only 1610 */ 1611 if ((j == INTERP_EAR) && 1612 (rate_val < 0x4 || 1613 rate_val > 0x7)) { 1614 dev_err(component->dev, 1615 "Invalid rate for AIF_PB DAI(%d)\n", 1616 dai->id); 1617 return -EINVAL; 1618 } 1619 1620 snd_soc_component_update_bits(component, 1621 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1622 WCD934X_CDC_MIX_PCM_RATE_MASK, 1623 rate_val); 1624 } 1625 } 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1632 u32 sample_rate) 1633 { 1634 int rate_val = 0; 1635 int i, ret; 1636 1637 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1638 if (sample_rate == sr_val_tbl[i].sample_rate) { 1639 rate_val = sr_val_tbl[i].rate_val; 1640 break; 1641 } 1642 } 1643 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1644 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1645 return -EINVAL; 1646 } 1647 1648 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1649 sample_rate); 1650 if (ret) 1651 return ret; 1652 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1653 sample_rate); 1654 1655 return ret; 1656 } 1657 1658 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1659 u8 rate_val, u32 rate) 1660 { 1661 struct snd_soc_component *comp = dai->component; 1662 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1663 u8 shift = 0, shift_val = 0, tx_mux_sel; 1664 struct wcd934x_slim_ch *ch; 1665 int tx_port, tx_port_reg; 1666 int decimator = -1; 1667 1668 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1669 tx_port = ch->port; 1670 /* Find the SB TX MUX input - which decimator is connected */ 1671 switch (tx_port) { 1672 case 0 ... 3: 1673 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1674 shift = (tx_port << 1); 1675 shift_val = 0x03; 1676 break; 1677 case 4 ... 7: 1678 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1679 shift = ((tx_port - 4) << 1); 1680 shift_val = 0x03; 1681 break; 1682 case 8 ... 10: 1683 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1684 shift = ((tx_port - 8) << 1); 1685 shift_val = 0x03; 1686 break; 1687 case 11: 1688 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1689 shift = 0; 1690 shift_val = 0x0F; 1691 break; 1692 case 13: 1693 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1694 shift = 4; 1695 shift_val = 0x03; 1696 break; 1697 default: 1698 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1699 tx_port, dai->id); 1700 return -EINVAL; 1701 } 1702 1703 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1704 (shift_val << shift); 1705 1706 tx_mux_sel = tx_mux_sel >> shift; 1707 switch (tx_port) { 1708 case 0 ... 8: 1709 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1710 decimator = tx_port; 1711 break; 1712 case 9 ... 10: 1713 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1714 decimator = ((tx_port == 9) ? 7 : 6); 1715 break; 1716 case 11: 1717 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1718 decimator = tx_mux_sel - 1; 1719 break; 1720 case 13: 1721 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1722 decimator = 5; 1723 break; 1724 default: 1725 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1726 tx_port); 1727 return -EINVAL; 1728 } 1729 1730 snd_soc_component_update_bits(comp, 1731 WCD934X_CDC_TX_PATH_CTL(decimator), 1732 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1733 rate_val); 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1740 struct wcd_slim_codec_dai_data *dai_data, 1741 int direction) 1742 { 1743 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1744 struct slim_stream_config *cfg = &dai_data->sconfig; 1745 struct wcd934x_slim_ch *ch; 1746 u16 payload = 0; 1747 int ret, i; 1748 1749 cfg->ch_count = 0; 1750 cfg->direction = direction; 1751 cfg->port_mask = 0; 1752 1753 /* Configure slave interface device */ 1754 list_for_each_entry(ch, slim_ch_list, list) { 1755 cfg->ch_count++; 1756 payload |= 1 << ch->shift; 1757 cfg->port_mask |= BIT(ch->port); 1758 } 1759 1760 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1761 if (!cfg->chs) 1762 return -ENOMEM; 1763 1764 i = 0; 1765 list_for_each_entry(ch, slim_ch_list, list) { 1766 cfg->chs[i++] = ch->ch_num; 1767 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1768 /* write to interface device */ 1769 ret = regmap_write(wcd->if_regmap, 1770 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1771 payload); 1772 1773 if (ret < 0) 1774 goto err; 1775 1776 /* configure the slave port for water mark and enable*/ 1777 ret = regmap_write(wcd->if_regmap, 1778 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1779 WCD934X_SLIM_WATER_MARK_VAL); 1780 if (ret < 0) 1781 goto err; 1782 } else { 1783 ret = regmap_write(wcd->if_regmap, 1784 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1785 payload & 0x00FF); 1786 if (ret < 0) 1787 goto err; 1788 1789 /* ports 8,9 */ 1790 ret = regmap_write(wcd->if_regmap, 1791 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1792 (payload & 0xFF00) >> 8); 1793 if (ret < 0) 1794 goto err; 1795 1796 /* configure the slave port for water mark and enable*/ 1797 ret = regmap_write(wcd->if_regmap, 1798 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1799 WCD934X_SLIM_WATER_MARK_VAL); 1800 1801 if (ret < 0) 1802 goto err; 1803 } 1804 } 1805 1806 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1807 1808 return 0; 1809 1810 err: 1811 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1812 kfree(cfg->chs); 1813 cfg->chs = NULL; 1814 1815 return ret; 1816 } 1817 1818 static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1819 struct snd_pcm_hw_params *params, 1820 struct snd_soc_dai *dai) 1821 { 1822 struct wcd934x_codec *wcd; 1823 int ret, tx_fs_rate = 0; 1824 1825 wcd = snd_soc_component_get_drvdata(dai->component); 1826 1827 switch (substream->stream) { 1828 case SNDRV_PCM_STREAM_PLAYBACK: 1829 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1830 if (ret) { 1831 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1832 params_rate(params)); 1833 return ret; 1834 } 1835 switch (params_width(params)) { 1836 case 16 ... 24: 1837 wcd->dai[dai->id].sconfig.bps = params_width(params); 1838 break; 1839 default: 1840 dev_err(wcd->dev, "Invalid format 0x%x\n", 1841 params_width(params)); 1842 return -EINVAL; 1843 } 1844 break; 1845 1846 case SNDRV_PCM_STREAM_CAPTURE: 1847 switch (params_rate(params)) { 1848 case 8000: 1849 tx_fs_rate = 0; 1850 break; 1851 case 16000: 1852 tx_fs_rate = 1; 1853 break; 1854 case 32000: 1855 tx_fs_rate = 3; 1856 break; 1857 case 48000: 1858 tx_fs_rate = 4; 1859 break; 1860 case 96000: 1861 tx_fs_rate = 5; 1862 break; 1863 case 192000: 1864 tx_fs_rate = 6; 1865 break; 1866 case 384000: 1867 tx_fs_rate = 7; 1868 break; 1869 default: 1870 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1871 params_rate(params)); 1872 return -EINVAL; 1873 1874 } 1875 1876 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1877 params_rate(params)); 1878 if (ret < 0) { 1879 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1880 return ret; 1881 } 1882 switch (params_width(params)) { 1883 case 16 ... 32: 1884 wcd->dai[dai->id].sconfig.bps = params_width(params); 1885 break; 1886 default: 1887 dev_err(wcd->dev, "Invalid format 0x%x\n", 1888 params_width(params)); 1889 return -EINVAL; 1890 } 1891 break; 1892 default: 1893 dev_err(wcd->dev, "Invalid stream type %d\n", 1894 substream->stream); 1895 return -EINVAL; 1896 } 1897 1898 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1899 1900 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1901 } 1902 1903 static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1904 struct snd_soc_dai *dai) 1905 { 1906 struct wcd_slim_codec_dai_data *dai_data; 1907 struct wcd934x_codec *wcd; 1908 1909 wcd = snd_soc_component_get_drvdata(dai->component); 1910 1911 dai_data = &wcd->dai[dai->id]; 1912 1913 kfree(dai_data->sconfig.chs); 1914 1915 return 0; 1916 } 1917 1918 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1919 struct snd_soc_dai *dai) 1920 { 1921 struct wcd_slim_codec_dai_data *dai_data; 1922 struct wcd934x_codec *wcd; 1923 struct slim_stream_config *cfg; 1924 1925 wcd = snd_soc_component_get_drvdata(dai->component); 1926 1927 dai_data = &wcd->dai[dai->id]; 1928 1929 switch (cmd) { 1930 case SNDRV_PCM_TRIGGER_START: 1931 case SNDRV_PCM_TRIGGER_RESUME: 1932 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1933 cfg = &dai_data->sconfig; 1934 slim_stream_prepare(dai_data->sruntime, cfg); 1935 slim_stream_enable(dai_data->sruntime); 1936 break; 1937 case SNDRV_PCM_TRIGGER_STOP: 1938 case SNDRV_PCM_TRIGGER_SUSPEND: 1939 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1940 slim_stream_unprepare(dai_data->sruntime); 1941 slim_stream_disable(dai_data->sruntime); 1942 break; 1943 default: 1944 break; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1951 unsigned int tx_num, unsigned int *tx_slot, 1952 unsigned int rx_num, unsigned int *rx_slot) 1953 { 1954 struct wcd934x_codec *wcd; 1955 int i; 1956 1957 wcd = snd_soc_component_get_drvdata(dai->component); 1958 1959 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1960 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1961 tx_num, rx_num); 1962 return -EINVAL; 1963 } 1964 1965 if (!tx_slot || !rx_slot) { 1966 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1967 tx_slot, rx_slot); 1968 return -EINVAL; 1969 } 1970 1971 wcd->num_rx_port = rx_num; 1972 for (i = 0; i < rx_num; i++) { 1973 wcd->rx_chs[i].ch_num = rx_slot[i]; 1974 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1975 } 1976 1977 wcd->num_tx_port = tx_num; 1978 for (i = 0; i < tx_num; i++) { 1979 wcd->tx_chs[i].ch_num = tx_slot[i]; 1980 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1981 } 1982 1983 return 0; 1984 } 1985 1986 static int wcd934x_get_channel_map(struct snd_soc_dai *dai, 1987 unsigned int *tx_num, unsigned int *tx_slot, 1988 unsigned int *rx_num, unsigned int *rx_slot) 1989 { 1990 struct wcd934x_slim_ch *ch; 1991 struct wcd934x_codec *wcd; 1992 int i = 0; 1993 1994 wcd = snd_soc_component_get_drvdata(dai->component); 1995 1996 switch (dai->id) { 1997 case AIF1_PB: 1998 case AIF2_PB: 1999 case AIF3_PB: 2000 case AIF4_PB: 2001 if (!rx_slot || !rx_num) { 2002 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2003 rx_slot, rx_num); 2004 return -EINVAL; 2005 } 2006 2007 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2008 rx_slot[i++] = ch->ch_num; 2009 2010 *rx_num = i; 2011 break; 2012 case AIF1_CAP: 2013 case AIF2_CAP: 2014 case AIF3_CAP: 2015 if (!tx_slot || !tx_num) { 2016 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2017 tx_slot, tx_num); 2018 return -EINVAL; 2019 } 2020 2021 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2022 tx_slot[i++] = ch->ch_num; 2023 2024 *tx_num = i; 2025 break; 2026 default: 2027 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2028 break; 2029 } 2030 2031 return 0; 2032 } 2033 2034 static const struct snd_soc_dai_ops wcd934x_dai_ops = { 2035 .hw_params = wcd934x_hw_params, 2036 .hw_free = wcd934x_hw_free, 2037 .trigger = wcd934x_trigger, 2038 .set_channel_map = wcd934x_set_channel_map, 2039 .get_channel_map = wcd934x_get_channel_map, 2040 }; 2041 2042 static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 2043 [0] = { 2044 .name = "wcd934x_rx1", 2045 .id = AIF1_PB, 2046 .playback = { 2047 .stream_name = "AIF1 Playback", 2048 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2049 .formats = WCD934X_FORMATS_S16_S24_LE, 2050 .rate_max = 192000, 2051 .rate_min = 8000, 2052 .channels_min = 1, 2053 .channels_max = 2, 2054 }, 2055 .ops = &wcd934x_dai_ops, 2056 }, 2057 [1] = { 2058 .name = "wcd934x_tx1", 2059 .id = AIF1_CAP, 2060 .capture = { 2061 .stream_name = "AIF1 Capture", 2062 .rates = WCD934X_RATES_MASK, 2063 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2064 .rate_min = 8000, 2065 .rate_max = 192000, 2066 .channels_min = 1, 2067 .channels_max = 4, 2068 }, 2069 .ops = &wcd934x_dai_ops, 2070 }, 2071 [2] = { 2072 .name = "wcd934x_rx2", 2073 .id = AIF2_PB, 2074 .playback = { 2075 .stream_name = "AIF2 Playback", 2076 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2077 .formats = WCD934X_FORMATS_S16_S24_LE, 2078 .rate_min = 8000, 2079 .rate_max = 192000, 2080 .channels_min = 1, 2081 .channels_max = 2, 2082 }, 2083 .ops = &wcd934x_dai_ops, 2084 }, 2085 [3] = { 2086 .name = "wcd934x_tx2", 2087 .id = AIF2_CAP, 2088 .capture = { 2089 .stream_name = "AIF2 Capture", 2090 .rates = WCD934X_RATES_MASK, 2091 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2092 .rate_min = 8000, 2093 .rate_max = 192000, 2094 .channels_min = 1, 2095 .channels_max = 4, 2096 }, 2097 .ops = &wcd934x_dai_ops, 2098 }, 2099 [4] = { 2100 .name = "wcd934x_rx3", 2101 .id = AIF3_PB, 2102 .playback = { 2103 .stream_name = "AIF3 Playback", 2104 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2105 .formats = WCD934X_FORMATS_S16_S24_LE, 2106 .rate_min = 8000, 2107 .rate_max = 192000, 2108 .channels_min = 1, 2109 .channels_max = 2, 2110 }, 2111 .ops = &wcd934x_dai_ops, 2112 }, 2113 [5] = { 2114 .name = "wcd934x_tx3", 2115 .id = AIF3_CAP, 2116 .capture = { 2117 .stream_name = "AIF3 Capture", 2118 .rates = WCD934X_RATES_MASK, 2119 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2120 .rate_min = 8000, 2121 .rate_max = 192000, 2122 .channels_min = 1, 2123 .channels_max = 4, 2124 }, 2125 .ops = &wcd934x_dai_ops, 2126 }, 2127 [6] = { 2128 .name = "wcd934x_rx4", 2129 .id = AIF4_PB, 2130 .playback = { 2131 .stream_name = "AIF4 Playback", 2132 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2133 .formats = WCD934X_FORMATS_S16_S24_LE, 2134 .rate_min = 8000, 2135 .rate_max = 192000, 2136 .channels_min = 1, 2137 .channels_max = 2, 2138 }, 2139 .ops = &wcd934x_dai_ops, 2140 }, 2141 }; 2142 2143 static int swclk_gate_enable(struct clk_hw *hw) 2144 { 2145 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2146 } 2147 2148 static void swclk_gate_disable(struct clk_hw *hw) 2149 { 2150 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2151 } 2152 2153 static int swclk_gate_is_enabled(struct clk_hw *hw) 2154 { 2155 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2156 int ret, val; 2157 2158 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2159 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2160 2161 return ret; 2162 } 2163 2164 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2165 unsigned long parent_rate) 2166 { 2167 return parent_rate / 2; 2168 } 2169 2170 static const struct clk_ops swclk_gate_ops = { 2171 .prepare = swclk_gate_enable, 2172 .unprepare = swclk_gate_disable, 2173 .is_enabled = swclk_gate_is_enabled, 2174 .recalc_rate = swclk_recalc_rate, 2175 2176 }; 2177 2178 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2179 { 2180 struct clk *parent = wcd->extclk; 2181 struct device *dev = wcd->dev; 2182 struct device_node *np = dev->parent->of_node; 2183 const char *parent_clk_name = NULL; 2184 const char *clk_name = "mclk"; 2185 struct clk_hw *hw; 2186 struct clk_init_data init; 2187 int ret; 2188 2189 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2190 return NULL; 2191 2192 parent_clk_name = __clk_get_name(parent); 2193 2194 of_property_read_string(np, "clock-output-names", &clk_name); 2195 2196 init.name = clk_name; 2197 init.ops = &swclk_gate_ops; 2198 init.flags = 0; 2199 init.parent_names = &parent_clk_name; 2200 init.num_parents = 1; 2201 wcd->hw.init = &init; 2202 2203 hw = &wcd->hw; 2204 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2205 if (ret) 2206 return ERR_PTR(ret); 2207 2208 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2209 if (ret) 2210 return ERR_PTR(ret); 2211 2212 return NULL; 2213 } 2214 2215 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias, 2216 u32 *micb_mv) 2217 { 2218 int mv; 2219 2220 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) { 2221 dev_err(dev, "%s value not found, using default\n", micbias); 2222 mv = WCD934X_DEF_MICBIAS_MV; 2223 } else { 2224 /* convert it to milli volts */ 2225 mv = mv/1000; 2226 } 2227 2228 if (mv < 1000 || mv > 2850) { 2229 dev_err(dev, "%s value not in valid range, using default\n", 2230 micbias); 2231 mv = WCD934X_DEF_MICBIAS_MV; 2232 } 2233 2234 *micb_mv = mv; 2235 2236 return (mv - 1000) / 50; 2237 } 2238 2239 static int wcd934x_init_dmic(struct snd_soc_component *comp) 2240 { 2241 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2242 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2243 u32 def_dmic_rate, dmic_clk_drv; 2244 2245 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev, 2246 "qcom,micbias1-microvolt", 2247 &wcd->micb1_mv); 2248 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev, 2249 "qcom,micbias2-microvolt", 2250 &wcd->micb2_mv); 2251 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev, 2252 "qcom,micbias3-microvolt", 2253 &wcd->micb3_mv); 2254 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev, 2255 "qcom,micbias4-microvolt", 2256 &wcd->micb4_mv); 2257 2258 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2259 WCD934X_MICB_VAL_MASK, vout_ctl_1); 2260 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2261 WCD934X_MICB_VAL_MASK, vout_ctl_2); 2262 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2263 WCD934X_MICB_VAL_MASK, vout_ctl_3); 2264 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2265 WCD934X_MICB_VAL_MASK, vout_ctl_4); 2266 2267 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2268 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2269 else 2270 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2271 2272 wcd->dmic_sample_rate = def_dmic_rate; 2273 2274 dmic_clk_drv = 0; 2275 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2276 0x0C, dmic_clk_drv << 2); 2277 2278 return 0; 2279 } 2280 2281 static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2282 { 2283 struct regmap *rm = wcd->regmap; 2284 2285 /* set SPKR rate to FS_2P4_3P072 */ 2286 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2287 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2288 2289 /* Take DMICs out of reset */ 2290 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2291 } 2292 2293 static int wcd934x_comp_init(struct snd_soc_component *component) 2294 { 2295 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2296 2297 wcd934x_hw_init(wcd); 2298 wcd934x_enable_efuse_sensing(wcd); 2299 wcd934x_get_version(wcd); 2300 2301 return 0; 2302 } 2303 2304 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2305 { 2306 struct wcd934x_codec *wcd = data; 2307 unsigned long status = 0; 2308 int i, j, port_id; 2309 unsigned int val, int_val = 0; 2310 irqreturn_t ret = IRQ_NONE; 2311 bool tx; 2312 unsigned short reg = 0; 2313 2314 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2315 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2316 regmap_read(wcd->if_regmap, i, &val); 2317 status |= ((u32)val << (8 * j)); 2318 } 2319 2320 for_each_set_bit(j, &status, 32) { 2321 tx = false; 2322 port_id = j; 2323 2324 if (j >= 16) { 2325 tx = true; 2326 port_id = j - 16; 2327 } 2328 2329 regmap_read(wcd->if_regmap, 2330 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2331 if (val) { 2332 if (!tx) 2333 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2334 (port_id / 8); 2335 else 2336 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2337 (port_id / 8); 2338 regmap_read(wcd->if_regmap, reg, &int_val); 2339 } 2340 2341 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2342 dev_err_ratelimited(wcd->dev, 2343 "overflow error on %s port %d, value %x\n", 2344 (tx ? "TX" : "RX"), port_id, val); 2345 2346 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2347 dev_err_ratelimited(wcd->dev, 2348 "underflow error on %s port %d, value %x\n", 2349 (tx ? "TX" : "RX"), port_id, val); 2350 2351 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2352 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2353 if (!tx) 2354 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2355 (port_id / 8); 2356 else 2357 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2358 (port_id / 8); 2359 regmap_read( 2360 wcd->if_regmap, reg, &int_val); 2361 if (int_val & (1 << (port_id % 8))) { 2362 int_val = int_val ^ (1 << (port_id % 8)); 2363 regmap_write(wcd->if_regmap, 2364 reg, int_val); 2365 } 2366 } 2367 2368 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2369 dev_err_ratelimited(wcd->dev, 2370 "Port Closed %s port %d, value %x\n", 2371 (tx ? "TX" : "RX"), port_id, val); 2372 2373 regmap_write(wcd->if_regmap, 2374 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2375 BIT(j % 8)); 2376 ret = IRQ_HANDLED; 2377 } 2378 2379 return ret; 2380 } 2381 2382 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2383 bool enable) 2384 { 2385 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2386 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2387 } 2388 2389 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2390 bool enable) 2391 { 2392 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2393 WCD934X_ANA_MBHC_BIAS_EN, enable); 2394 } 2395 2396 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2397 int *btn_low, int *btn_high, 2398 int num_btn, bool is_micbias) 2399 { 2400 int i, vth; 2401 2402 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2403 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2404 __func__, num_btn); 2405 return; 2406 } 2407 2408 for (i = 0; i < num_btn; i++) { 2409 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2410 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2411 WCD934X_MBHC_BTN_VTH_MASK, vth); 2412 } 2413 } 2414 2415 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2416 { 2417 u8 val; 2418 2419 if (micb_num == MIC_BIAS_2) { 2420 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2421 WCD934X_ANA_MICB2_ENABLE_MASK); 2422 if (val == WCD934X_MICB_ENABLE) 2423 return true; 2424 } 2425 return false; 2426 } 2427 2428 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2429 enum mbhc_hs_pullup_iref pull_up_cur) 2430 { 2431 /* Default pull up current to 2uA */ 2432 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2433 pull_up_cur == I_DEFAULT) 2434 pull_up_cur = I_2P0_UA; 2435 2436 2437 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2438 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2439 } 2440 2441 static int wcd934x_micbias_control(struct snd_soc_component *component, 2442 int micb_num, int req, bool is_dapm) 2443 { 2444 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2445 int micb_index = micb_num - 1; 2446 u16 micb_reg; 2447 2448 switch (micb_num) { 2449 case MIC_BIAS_1: 2450 micb_reg = WCD934X_ANA_MICB1; 2451 break; 2452 case MIC_BIAS_2: 2453 micb_reg = WCD934X_ANA_MICB2; 2454 break; 2455 case MIC_BIAS_3: 2456 micb_reg = WCD934X_ANA_MICB3; 2457 break; 2458 case MIC_BIAS_4: 2459 micb_reg = WCD934X_ANA_MICB4; 2460 break; 2461 default: 2462 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2463 __func__, micb_num); 2464 return -EINVAL; 2465 } 2466 mutex_lock(&wcd934x->micb_lock); 2467 2468 switch (req) { 2469 case MICB_PULLUP_ENABLE: 2470 wcd934x->pullup_ref[micb_index]++; 2471 if ((wcd934x->pullup_ref[micb_index] == 1) && 2472 (wcd934x->micb_ref[micb_index] == 0)) 2473 snd_soc_component_write_field(component, micb_reg, 2474 WCD934X_ANA_MICB_EN_MASK, 2475 WCD934X_MICB_PULL_UP); 2476 break; 2477 case MICB_PULLUP_DISABLE: 2478 if (wcd934x->pullup_ref[micb_index] > 0) 2479 wcd934x->pullup_ref[micb_index]--; 2480 2481 if ((wcd934x->pullup_ref[micb_index] == 0) && 2482 (wcd934x->micb_ref[micb_index] == 0)) 2483 snd_soc_component_write_field(component, micb_reg, 2484 WCD934X_ANA_MICB_EN_MASK, 0); 2485 break; 2486 case MICB_ENABLE: 2487 wcd934x->micb_ref[micb_index]++; 2488 if (wcd934x->micb_ref[micb_index] == 1) { 2489 snd_soc_component_write_field(component, micb_reg, 2490 WCD934X_ANA_MICB_EN_MASK, 2491 WCD934X_MICB_ENABLE); 2492 if (micb_num == MIC_BIAS_2) 2493 wcd_mbhc_event_notify(wcd934x->mbhc, 2494 WCD_EVENT_POST_MICBIAS_2_ON); 2495 } 2496 2497 if (micb_num == MIC_BIAS_2 && is_dapm) 2498 wcd_mbhc_event_notify(wcd934x->mbhc, 2499 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2500 break; 2501 case MICB_DISABLE: 2502 if (wcd934x->micb_ref[micb_index] > 0) 2503 wcd934x->micb_ref[micb_index]--; 2504 2505 if ((wcd934x->micb_ref[micb_index] == 0) && 2506 (wcd934x->pullup_ref[micb_index] > 0)) 2507 snd_soc_component_write_field(component, micb_reg, 2508 WCD934X_ANA_MICB_EN_MASK, 2509 WCD934X_MICB_PULL_UP); 2510 else if ((wcd934x->micb_ref[micb_index] == 0) && 2511 (wcd934x->pullup_ref[micb_index] == 0)) { 2512 if (micb_num == MIC_BIAS_2) 2513 wcd_mbhc_event_notify(wcd934x->mbhc, 2514 WCD_EVENT_PRE_MICBIAS_2_OFF); 2515 2516 snd_soc_component_write_field(component, micb_reg, 2517 WCD934X_ANA_MICB_EN_MASK, 0); 2518 if (micb_num == MIC_BIAS_2) 2519 wcd_mbhc_event_notify(wcd934x->mbhc, 2520 WCD_EVENT_POST_MICBIAS_2_OFF); 2521 } 2522 if (is_dapm && micb_num == MIC_BIAS_2) 2523 wcd_mbhc_event_notify(wcd934x->mbhc, 2524 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2525 break; 2526 } 2527 2528 mutex_unlock(&wcd934x->micb_lock); 2529 2530 return 0; 2531 } 2532 2533 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2534 int micb_num, int req) 2535 { 2536 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2537 int ret; 2538 2539 if (req == MICB_ENABLE) 2540 __wcd934x_cdc_mclk_enable(wcd, true); 2541 2542 ret = wcd934x_micbias_control(component, micb_num, req, false); 2543 2544 if (req == MICB_DISABLE) 2545 __wcd934x_cdc_mclk_enable(wcd, false); 2546 2547 return ret; 2548 } 2549 2550 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2551 bool enable) 2552 { 2553 if (enable) { 2554 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2555 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2556 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2557 WCD934X_RAMP_EN_MASK, 1); 2558 } else { 2559 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2560 WCD934X_RAMP_EN_MASK, 0); 2561 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2562 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2563 } 2564 } 2565 2566 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv) 2567 { 2568 /* min micbias voltage is 1V and maximum is 2.85V */ 2569 if (micb_mv < 1000 || micb_mv > 2850) 2570 return -EINVAL; 2571 2572 return (micb_mv - 1000) / 50; 2573 } 2574 2575 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2576 int req_volt, int micb_num) 2577 { 2578 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2579 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2580 2581 switch (micb_num) { 2582 case MIC_BIAS_1: 2583 micb_reg = WCD934X_ANA_MICB1; 2584 break; 2585 case MIC_BIAS_2: 2586 micb_reg = WCD934X_ANA_MICB2; 2587 break; 2588 case MIC_BIAS_3: 2589 micb_reg = WCD934X_ANA_MICB3; 2590 break; 2591 case MIC_BIAS_4: 2592 micb_reg = WCD934X_ANA_MICB4; 2593 break; 2594 default: 2595 return -EINVAL; 2596 } 2597 mutex_lock(&wcd934x->micb_lock); 2598 /* 2599 * If requested micbias voltage is same as current micbias 2600 * voltage, then just return. Otherwise, adjust voltage as 2601 * per requested value. If micbias is already enabled, then 2602 * to avoid slow micbias ramp-up or down enable pull-up 2603 * momentarily, change the micbias value and then re-enable 2604 * micbias. 2605 */ 2606 micb_en = snd_soc_component_read_field(component, micb_reg, 2607 WCD934X_ANA_MICB_EN_MASK); 2608 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2609 WCD934X_MICB_VAL_MASK); 2610 2611 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt); 2612 if (req_vout_ctl < 0) { 2613 ret = -EINVAL; 2614 goto exit; 2615 } 2616 2617 if (cur_vout_ctl == req_vout_ctl) { 2618 ret = 0; 2619 goto exit; 2620 } 2621 2622 if (micb_en == WCD934X_MICB_ENABLE) 2623 snd_soc_component_write_field(component, micb_reg, 2624 WCD934X_ANA_MICB_EN_MASK, 2625 WCD934X_MICB_PULL_UP); 2626 2627 snd_soc_component_write_field(component, micb_reg, 2628 WCD934X_MICB_VAL_MASK, 2629 req_vout_ctl); 2630 2631 if (micb_en == WCD934X_MICB_ENABLE) { 2632 snd_soc_component_write_field(component, micb_reg, 2633 WCD934X_ANA_MICB_EN_MASK, 2634 WCD934X_MICB_ENABLE); 2635 /* 2636 * Add 2ms delay as per HW requirement after enabling 2637 * micbias 2638 */ 2639 usleep_range(2000, 2100); 2640 } 2641 exit: 2642 mutex_unlock(&wcd934x->micb_lock); 2643 return ret; 2644 } 2645 2646 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2647 int micb_num, bool req_en) 2648 { 2649 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2650 int rc, micb_mv; 2651 2652 if (micb_num != MIC_BIAS_2) 2653 return -EINVAL; 2654 /* 2655 * If device tree micbias level is already above the minimum 2656 * voltage needed to detect threshold microphone, then do 2657 * not change the micbias, just return. 2658 */ 2659 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2660 return 0; 2661 2662 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv; 2663 2664 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2665 2666 return rc; 2667 } 2668 2669 static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2670 s16 *d1_a, u16 noff, 2671 int32_t *zdet) 2672 { 2673 int i; 2674 int val, val1; 2675 s16 c1; 2676 s32 x1, d1; 2677 int32_t denom; 2678 int minCode_param[] = { 2679 3277, 1639, 820, 410, 205, 103, 52, 26 2680 }; 2681 2682 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2683 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2684 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2685 if (val & 0x80) 2686 break; 2687 } 2688 val = val << 0x8; 2689 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2690 val |= val1; 2691 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2692 x1 = WCD934X_MBHC_GET_X1(val); 2693 c1 = WCD934X_MBHC_GET_C1(val); 2694 /* If ramp is not complete, give additional 5ms */ 2695 if ((c1 < 2) && x1) 2696 usleep_range(5000, 5050); 2697 2698 if (!c1 || !x1) { 2699 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2700 __func__, c1, x1); 2701 goto ramp_down; 2702 } 2703 d1 = d1_a[c1]; 2704 denom = (x1 * d1) - (1 << (14 - noff)); 2705 if (denom > 0) 2706 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2707 else if (x1 < minCode_param[noff]) 2708 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2709 2710 dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2711 __func__, d1, c1, x1, *zdet); 2712 ramp_down: 2713 i = 0; 2714 2715 while (x1) { 2716 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2717 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2718 val = val << 0x08; 2719 val |= val1; 2720 x1 = WCD934X_MBHC_GET_X1(val); 2721 i++; 2722 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2723 break; 2724 } 2725 } 2726 2727 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2728 struct wcd934x_mbhc_zdet_param *zdet_param, 2729 int32_t *zl, int32_t *zr, s16 *d1_a) 2730 { 2731 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2732 int32_t zdet = 0; 2733 2734 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2735 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2736 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2737 WCD934X_VTH_MASK, zdet_param->btn5); 2738 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2739 WCD934X_VTH_MASK, zdet_param->btn6); 2740 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2741 WCD934X_VTH_MASK, zdet_param->btn7); 2742 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2743 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2744 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2745 0x0F, zdet_param->nshift); 2746 2747 if (!zl) 2748 goto z_right; 2749 /* Start impedance measurement for HPH_L */ 2750 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2751 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2752 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2753 2754 *zl = zdet; 2755 2756 z_right: 2757 if (!zr) 2758 return; 2759 /* Start impedance measurement for HPH_R */ 2760 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2761 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2762 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2763 2764 *zr = zdet; 2765 } 2766 2767 static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2768 int32_t *z_val, int flag_l_r) 2769 { 2770 s16 q1; 2771 int q1_cal; 2772 2773 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2774 q1 = snd_soc_component_read(component, 2775 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2776 else 2777 q1 = snd_soc_component_read(component, 2778 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2779 if (q1 & 0x80) 2780 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2781 else 2782 q1_cal = (10000 + (q1 * 25)); 2783 if (q1_cal > 0) 2784 *z_val = ((*z_val) * 10000) / q1_cal; 2785 } 2786 2787 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2788 uint32_t *zl, uint32_t *zr) 2789 { 2790 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2791 s16 reg0, reg1, reg2, reg3, reg4; 2792 int32_t z1L, z1R, z1Ls; 2793 int zMono, z_diff1, z_diff2; 2794 bool is_fsm_disable = false; 2795 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2796 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2797 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2798 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2799 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2800 }; 2801 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2802 s16 d1_a[][4] = { 2803 {0, 30, 90, 30}, 2804 {0, 30, 30, 5}, 2805 {0, 30, 30, 5}, 2806 {0, 30, 30, 5}, 2807 }; 2808 s16 *d1 = NULL; 2809 2810 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2811 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2812 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2813 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2814 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2815 2816 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2817 is_fsm_disable = true; 2818 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2819 } 2820 2821 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2822 if (wcd934x->mbhc_cfg.hphl_swh) 2823 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2824 2825 /* Turn off 100k pull down on HPHL */ 2826 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2827 2828 /* First get impedance on Left */ 2829 d1 = d1_a[1]; 2830 zdet_param_ptr = &zdet_param[1]; 2831 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2832 2833 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2834 goto left_ch_impedance; 2835 2836 /* Second ramp for left ch */ 2837 if (z1L < WCD934X_ZDET_VAL_32) { 2838 zdet_param_ptr = &zdet_param[0]; 2839 d1 = d1_a[0]; 2840 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2841 (z1L <= WCD934X_ZDET_VAL_1200)) { 2842 zdet_param_ptr = &zdet_param[2]; 2843 d1 = d1_a[2]; 2844 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2845 zdet_param_ptr = &zdet_param[3]; 2846 d1 = d1_a[3]; 2847 } 2848 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2849 2850 left_ch_impedance: 2851 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2852 (z1L > WCD934X_ZDET_VAL_100K)) { 2853 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2854 zdet_param_ptr = &zdet_param[1]; 2855 d1 = d1_a[1]; 2856 } else { 2857 *zl = z1L/1000; 2858 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2859 } 2860 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2861 __func__, *zl); 2862 2863 /* Start of right impedance ramp and calculation */ 2864 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2865 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2866 if (((z1R > WCD934X_ZDET_VAL_1200) && 2867 (zdet_param_ptr->noff == 0x6)) || 2868 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2869 goto right_ch_impedance; 2870 /* Second ramp for right ch */ 2871 if (z1R < WCD934X_ZDET_VAL_32) { 2872 zdet_param_ptr = &zdet_param[0]; 2873 d1 = d1_a[0]; 2874 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2875 (z1R <= WCD934X_ZDET_VAL_1200)) { 2876 zdet_param_ptr = &zdet_param[2]; 2877 d1 = d1_a[2]; 2878 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2879 zdet_param_ptr = &zdet_param[3]; 2880 d1 = d1_a[3]; 2881 } 2882 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2883 } 2884 right_ch_impedance: 2885 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2886 (z1R > WCD934X_ZDET_VAL_100K)) { 2887 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2888 } else { 2889 *zr = z1R/1000; 2890 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2891 } 2892 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2893 __func__, *zr); 2894 2895 /* Mono/stereo detection */ 2896 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2897 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2898 dev_dbg(component->dev, 2899 "%s: plug type is invalid or extension cable\n", 2900 __func__); 2901 goto zdet_complete; 2902 } 2903 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2904 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2905 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2906 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2907 dev_dbg(component->dev, 2908 "%s: Mono plug type with one ch floating or shorted to GND\n", 2909 __func__); 2910 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2911 goto zdet_complete; 2912 } 2913 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2914 WCD934X_HPHPA_GND_OVR_MASK, 1); 2915 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2916 WCD934X_HPHPA_GND_R_MASK, 1); 2917 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2918 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2919 else 2920 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2921 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2922 WCD934X_HPHPA_GND_R_MASK, 0); 2923 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2924 WCD934X_HPHPA_GND_OVR_MASK, 0); 2925 z1Ls /= 1000; 2926 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2927 /* Parallel of left Z and 9 ohm pull down resistor */ 2928 zMono = ((*zl) * 9) / ((*zl) + 9); 2929 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2930 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2931 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2932 dev_err(component->dev, "%s: stereo plug type detected\n", 2933 __func__); 2934 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2935 } else { 2936 dev_err(component->dev, "%s: MONO plug type detected\n", 2937 __func__); 2938 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2939 } 2940 2941 zdet_complete: 2942 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2943 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2944 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2945 /* Turn on 100k pull down on HPHL */ 2946 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2947 2948 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2949 if (wcd934x->mbhc_cfg.hphl_swh) 2950 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2951 2952 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2953 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2954 if (is_fsm_disable) 2955 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2956 } 2957 2958 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2959 bool enable) 2960 { 2961 if (enable) { 2962 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2963 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2964 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2965 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2966 } else { 2967 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2968 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2969 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2970 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2971 } 2972 } 2973 2974 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2975 bool enable) 2976 { 2977 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2978 WCD934X_HPHPA_GND_R_MASK, enable); 2979 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2980 WCD934X_HPHPA_GND_L_MASK, enable); 2981 } 2982 2983 static const struct wcd_mbhc_cb mbhc_cb = { 2984 .clk_setup = wcd934x_mbhc_clk_setup, 2985 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2986 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2987 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2988 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2989 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2990 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2991 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2992 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2993 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2994 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2995 }; 2996 2997 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2998 struct snd_ctl_elem_value *ucontrol) 2999 { 3000 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3001 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3002 3003 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 3004 3005 return 0; 3006 } 3007 3008 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 3009 struct snd_ctl_elem_value *ucontrol) 3010 { 3011 uint32_t zl, zr; 3012 bool hphr; 3013 struct soc_mixer_control *mc; 3014 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3015 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3016 3017 mc = (struct soc_mixer_control *)(kcontrol->private_value); 3018 hphr = mc->shift; 3019 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 3020 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 3021 ucontrol->value.integer.value[0] = hphr ? zr : zl; 3022 3023 return 0; 3024 } 3025 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3026 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 3027 wcd934x_get_hph_type, NULL), 3028 }; 3029 3030 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3031 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 3032 wcd934x_hph_impedance_get, NULL), 3033 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 3034 wcd934x_hph_impedance_get, NULL), 3035 }; 3036 3037 static int wcd934x_mbhc_init(struct snd_soc_component *component) 3038 { 3039 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 3040 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3041 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 3042 3043 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 3044 WCD934X_IRQ_MBHC_SW_DET); 3045 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 3046 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 3047 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 3048 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 3049 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 3050 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3051 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 3052 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 3053 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 3054 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 3055 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 3056 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 3057 3058 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3059 if (IS_ERR(wcd->mbhc)) { 3060 wcd->mbhc = NULL; 3061 return -EINVAL; 3062 } 3063 3064 snd_soc_add_component_controls(component, impedance_detect_controls, 3065 ARRAY_SIZE(impedance_detect_controls)); 3066 snd_soc_add_component_controls(component, hph_type_detect_controls, 3067 ARRAY_SIZE(hph_type_detect_controls)); 3068 3069 return 0; 3070 } 3071 static int wcd934x_comp_probe(struct snd_soc_component *component) 3072 { 3073 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3074 int i; 3075 3076 snd_soc_component_init_regmap(component, wcd->regmap); 3077 wcd->component = component; 3078 3079 /* Class-H Init*/ 3080 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3081 if (IS_ERR(wcd->clsh_ctrl)) 3082 return PTR_ERR(wcd->clsh_ctrl); 3083 3084 /* Default HPH Mode to Class-H Low HiFi */ 3085 wcd->hph_mode = CLS_H_LOHIFI; 3086 3087 wcd934x_comp_init(component); 3088 3089 for (i = 0; i < NUM_CODEC_DAIS; i++) 3090 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3091 3092 wcd934x_init_dmic(component); 3093 3094 if (wcd934x_mbhc_init(component)) 3095 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3096 3097 return 0; 3098 } 3099 3100 static void wcd934x_comp_remove(struct snd_soc_component *comp) 3101 { 3102 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3103 3104 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3105 } 3106 3107 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3108 int clk_id, int source, 3109 unsigned int freq, int dir) 3110 { 3111 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3112 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3113 3114 wcd->rate = freq; 3115 3116 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3117 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3118 3119 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3120 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3121 val); 3122 3123 return clk_set_rate(wcd->extclk, freq); 3124 } 3125 3126 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3127 int iir_idx, int band_idx, int coeff_idx) 3128 { 3129 u32 value = 0; 3130 int reg, b2_reg; 3131 3132 /* Address does not automatically update if reading */ 3133 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3134 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3135 3136 snd_soc_component_write(component, reg, 3137 ((band_idx * BAND_MAX + coeff_idx) * 3138 sizeof(uint32_t)) & 0x7F); 3139 3140 value |= snd_soc_component_read(component, b2_reg); 3141 snd_soc_component_write(component, reg, 3142 ((band_idx * BAND_MAX + coeff_idx) 3143 * sizeof(uint32_t) + 1) & 0x7F); 3144 3145 value |= (snd_soc_component_read(component, b2_reg) << 8); 3146 snd_soc_component_write(component, reg, 3147 ((band_idx * BAND_MAX + coeff_idx) 3148 * sizeof(uint32_t) + 2) & 0x7F); 3149 3150 value |= (snd_soc_component_read(component, b2_reg) << 16); 3151 snd_soc_component_write(component, reg, 3152 ((band_idx * BAND_MAX + coeff_idx) 3153 * sizeof(uint32_t) + 3) & 0x7F); 3154 3155 /* Mask bits top 2 bits since they are reserved */ 3156 value |= (snd_soc_component_read(component, b2_reg) << 24); 3157 return value; 3158 } 3159 3160 static void set_iir_band_coeff(struct snd_soc_component *component, 3161 int iir_idx, int band_idx, uint32_t value) 3162 { 3163 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3164 3165 snd_soc_component_write(component, reg, (value & 0xFF)); 3166 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3167 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3168 /* Mask top 2 bits, 7-8 are reserved */ 3169 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3170 } 3171 3172 static int wcd934x_put_iir_band_audio_mixer( 3173 struct snd_kcontrol *kcontrol, 3174 struct snd_ctl_elem_value *ucontrol) 3175 { 3176 struct snd_soc_component *component = 3177 snd_soc_kcontrol_component(kcontrol); 3178 struct wcd_iir_filter_ctl *ctl = 3179 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3180 struct soc_bytes_ext *params = &ctl->bytes_ext; 3181 int iir_idx = ctl->iir_idx; 3182 int band_idx = ctl->band_idx; 3183 u32 coeff[BAND_MAX]; 3184 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3185 3186 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3187 3188 /* Mask top bit it is reserved */ 3189 /* Updates addr automatically for each B2 write */ 3190 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3191 sizeof(uint32_t)) & 0x7F); 3192 3193 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3194 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3195 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3196 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3197 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3198 3199 return 0; 3200 } 3201 3202 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3203 struct snd_ctl_elem_value *ucontrol) 3204 { 3205 struct snd_soc_component *component = 3206 snd_soc_kcontrol_component(kcontrol); 3207 struct wcd_iir_filter_ctl *ctl = 3208 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3209 struct soc_bytes_ext *params = &ctl->bytes_ext; 3210 int iir_idx = ctl->iir_idx; 3211 int band_idx = ctl->band_idx; 3212 u32 coeff[BAND_MAX]; 3213 3214 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3215 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3216 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3217 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3218 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3219 3220 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3221 3222 return 0; 3223 } 3224 3225 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3226 struct snd_ctl_elem_info *ucontrol) 3227 { 3228 struct wcd_iir_filter_ctl *ctl = 3229 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3230 struct soc_bytes_ext *params = &ctl->bytes_ext; 3231 3232 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3233 ucontrol->count = params->max; 3234 3235 return 0; 3236 } 3237 3238 static int wcd934x_compander_get(struct snd_kcontrol *kc, 3239 struct snd_ctl_elem_value *ucontrol) 3240 { 3241 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3242 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3243 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3244 3245 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3246 3247 return 0; 3248 } 3249 3250 static int wcd934x_compander_set(struct snd_kcontrol *kc, 3251 struct snd_ctl_elem_value *ucontrol) 3252 { 3253 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3254 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3255 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3256 int value = ucontrol->value.integer.value[0]; 3257 int sel; 3258 3259 wcd->comp_enabled[comp] = value; 3260 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3261 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3262 3263 /* Any specific register configuration for compander */ 3264 switch (comp) { 3265 case COMPANDER_1: 3266 /* Set Gain Source Select based on compander enable/disable */ 3267 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3268 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3269 sel); 3270 break; 3271 case COMPANDER_2: 3272 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3273 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3274 sel); 3275 break; 3276 case COMPANDER_3: 3277 case COMPANDER_4: 3278 case COMPANDER_7: 3279 case COMPANDER_8: 3280 break; 3281 default: 3282 break; 3283 } 3284 3285 return 0; 3286 } 3287 3288 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3289 struct snd_ctl_elem_value *ucontrol) 3290 { 3291 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3292 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3293 3294 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3295 3296 return 0; 3297 } 3298 3299 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3300 struct snd_ctl_elem_value *ucontrol) 3301 { 3302 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3303 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3304 u32 mode_val; 3305 3306 mode_val = ucontrol->value.enumerated.item[0]; 3307 3308 if (mode_val == 0) { 3309 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3310 mode_val = CLS_H_LOHIFI; 3311 } 3312 wcd->hph_mode = mode_val; 3313 3314 return 0; 3315 } 3316 3317 static int slim_rx_mux_get(struct snd_kcontrol *kc, 3318 struct snd_ctl_elem_value *ucontrol) 3319 { 3320 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3321 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3322 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3323 3324 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3325 3326 return 0; 3327 } 3328 3329 static int slim_rx_mux_put(struct snd_kcontrol *kc, 3330 struct snd_ctl_elem_value *ucontrol) 3331 { 3332 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3333 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev); 3334 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3335 struct snd_soc_dapm_update *update = NULL; 3336 u32 port_id = w->shift; 3337 3338 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 3339 return 0; 3340 3341 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 3342 3343 switch (wcd->rx_port_value[port_id]) { 3344 case 0: 3345 list_del_init(&wcd->rx_chs[port_id].list); 3346 break; 3347 case 1: 3348 list_add_tail(&wcd->rx_chs[port_id].list, 3349 &wcd->dai[AIF1_PB].slim_ch_list); 3350 break; 3351 case 2: 3352 list_add_tail(&wcd->rx_chs[port_id].list, 3353 &wcd->dai[AIF2_PB].slim_ch_list); 3354 break; 3355 case 3: 3356 list_add_tail(&wcd->rx_chs[port_id].list, 3357 &wcd->dai[AIF3_PB].slim_ch_list); 3358 break; 3359 case 4: 3360 list_add_tail(&wcd->rx_chs[port_id].list, 3361 &wcd->dai[AIF4_PB].slim_ch_list); 3362 break; 3363 default: 3364 dev_err(wcd->dev, "Unknown AIF %d\n", 3365 wcd->rx_port_value[port_id]); 3366 goto err; 3367 } 3368 3369 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3370 e, update); 3371 3372 return 0; 3373 err: 3374 return -EINVAL; 3375 } 3376 3377 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3378 struct snd_ctl_elem_value *ucontrol) 3379 { 3380 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3381 struct snd_soc_component *component; 3382 int reg, val, ret; 3383 3384 component = snd_soc_dapm_kcontrol_component(kc); 3385 val = ucontrol->value.enumerated.item[0]; 3386 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3387 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3388 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3389 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3390 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3391 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3392 else 3393 return -EINVAL; 3394 3395 /* Set Look Ahead Delay */ 3396 if (val) 3397 snd_soc_component_update_bits(component, reg, 3398 WCD934X_RX_DLY_ZN_EN_MASK, 3399 WCD934X_RX_DLY_ZN_ENABLE); 3400 else 3401 snd_soc_component_update_bits(component, reg, 3402 WCD934X_RX_DLY_ZN_EN_MASK, 3403 WCD934X_RX_DLY_ZN_DISABLE); 3404 3405 ret = snd_soc_dapm_put_enum_double(kc, ucontrol); 3406 3407 return ret; 3408 } 3409 3410 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3411 struct snd_ctl_elem_value *ucontrol) 3412 { 3413 struct snd_soc_component *comp; 3414 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3415 unsigned int val; 3416 u16 mic_sel_reg = 0; 3417 u8 mic_sel; 3418 3419 comp = snd_soc_dapm_kcontrol_component(kcontrol); 3420 3421 val = ucontrol->value.enumerated.item[0]; 3422 if (val > e->items - 1) 3423 return -EINVAL; 3424 3425 switch (e->reg) { 3426 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3427 if (e->shift_l == 0) 3428 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3429 else if (e->shift_l == 2) 3430 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3431 else if (e->shift_l == 4) 3432 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3433 break; 3434 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3435 if (e->shift_l == 0) 3436 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3437 else if (e->shift_l == 2) 3438 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3439 break; 3440 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3441 if (e->shift_l == 0) 3442 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3443 else if (e->shift_l == 2) 3444 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3445 break; 3446 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3447 if (e->shift_l == 0) 3448 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3449 else if (e->shift_l == 2) 3450 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3451 break; 3452 default: 3453 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3454 __func__, e->reg); 3455 return -EINVAL; 3456 } 3457 3458 /* ADC: 0, DMIC: 1 */ 3459 mic_sel = val ? 0x0 : 0x1; 3460 if (mic_sel_reg) 3461 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3462 mic_sel << 7); 3463 3464 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3465 } 3466 3467 static const struct snd_kcontrol_new rx_int0_2_mux = 3468 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3469 3470 static const struct snd_kcontrol_new rx_int1_2_mux = 3471 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3472 3473 static const struct snd_kcontrol_new rx_int2_2_mux = 3474 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3475 3476 static const struct snd_kcontrol_new rx_int3_2_mux = 3477 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3478 3479 static const struct snd_kcontrol_new rx_int4_2_mux = 3480 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3481 3482 static const struct snd_kcontrol_new rx_int7_2_mux = 3483 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3484 3485 static const struct snd_kcontrol_new rx_int8_2_mux = 3486 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3487 3488 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3489 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3490 3491 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3492 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3493 3494 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3495 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3496 3497 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3498 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3499 3500 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3501 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3502 3503 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3504 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3505 3506 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3507 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3508 3509 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3510 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3511 3512 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3513 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3514 3515 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3516 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3517 3518 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3519 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3520 3521 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3522 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3523 3524 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3525 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3526 3527 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3528 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3529 3530 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3531 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3532 3533 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3534 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3535 3536 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3537 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3538 3539 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3540 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3541 3542 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3543 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3544 3545 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3546 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3547 3548 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3549 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3550 3551 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3552 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3553 3554 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3555 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3556 3557 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3558 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3559 3560 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3561 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3562 3563 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3564 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3565 3566 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3567 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3568 3569 static const struct snd_kcontrol_new iir0_inp0_mux = 3570 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3571 static const struct snd_kcontrol_new iir0_inp1_mux = 3572 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3573 static const struct snd_kcontrol_new iir0_inp2_mux = 3574 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3575 static const struct snd_kcontrol_new iir0_inp3_mux = 3576 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3577 3578 static const struct snd_kcontrol_new iir1_inp0_mux = 3579 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3580 static const struct snd_kcontrol_new iir1_inp1_mux = 3581 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3582 static const struct snd_kcontrol_new iir1_inp2_mux = 3583 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3584 static const struct snd_kcontrol_new iir1_inp3_mux = 3585 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3586 3587 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3588 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3589 slim_rx_mux_get, slim_rx_mux_put), 3590 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3591 slim_rx_mux_get, slim_rx_mux_put), 3592 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3593 slim_rx_mux_get, slim_rx_mux_put), 3594 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3595 slim_rx_mux_get, slim_rx_mux_put), 3596 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3597 slim_rx_mux_get, slim_rx_mux_put), 3598 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3599 slim_rx_mux_get, slim_rx_mux_put), 3600 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3601 slim_rx_mux_get, slim_rx_mux_put), 3602 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3603 slim_rx_mux_get, slim_rx_mux_put), 3604 }; 3605 3606 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3607 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3608 }; 3609 3610 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3611 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3612 }; 3613 3614 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3615 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3616 }; 3617 3618 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3619 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3620 }; 3621 3622 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3623 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3624 snd_soc_dapm_get_enum_double, 3625 wcd934x_int_dem_inp_mux_put); 3626 3627 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3628 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3629 snd_soc_dapm_get_enum_double, 3630 wcd934x_int_dem_inp_mux_put); 3631 3632 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3633 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3634 snd_soc_dapm_get_enum_double, 3635 wcd934x_int_dem_inp_mux_put); 3636 3637 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3638 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3639 3640 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3641 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3642 3643 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3644 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3645 3646 static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3647 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3648 3649 static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3650 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3651 3652 static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3653 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3654 3655 static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3656 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3657 3658 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3659 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3660 3661 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3662 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3663 3664 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3665 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3666 3667 static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3668 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3669 3670 static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3671 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3672 3673 static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3674 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3675 3676 static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3677 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3678 3679 static const struct snd_kcontrol_new tx_dmic_mux0 = 3680 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3681 3682 static const struct snd_kcontrol_new tx_dmic_mux1 = 3683 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3684 3685 static const struct snd_kcontrol_new tx_dmic_mux2 = 3686 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3687 3688 static const struct snd_kcontrol_new tx_dmic_mux3 = 3689 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3690 3691 static const struct snd_kcontrol_new tx_dmic_mux4 = 3692 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3693 3694 static const struct snd_kcontrol_new tx_dmic_mux5 = 3695 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3696 3697 static const struct snd_kcontrol_new tx_dmic_mux6 = 3698 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3699 3700 static const struct snd_kcontrol_new tx_dmic_mux7 = 3701 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3702 3703 static const struct snd_kcontrol_new tx_dmic_mux8 = 3704 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3705 3706 static const struct snd_kcontrol_new tx_amic_mux0 = 3707 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3708 3709 static const struct snd_kcontrol_new tx_amic_mux1 = 3710 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3711 3712 static const struct snd_kcontrol_new tx_amic_mux2 = 3713 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3714 3715 static const struct snd_kcontrol_new tx_amic_mux3 = 3716 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3717 3718 static const struct snd_kcontrol_new tx_amic_mux4 = 3719 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3720 3721 static const struct snd_kcontrol_new tx_amic_mux5 = 3722 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3723 3724 static const struct snd_kcontrol_new tx_amic_mux6 = 3725 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3726 3727 static const struct snd_kcontrol_new tx_amic_mux7 = 3728 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3729 3730 static const struct snd_kcontrol_new tx_amic_mux8 = 3731 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3732 3733 static const struct snd_kcontrol_new tx_amic4_5 = 3734 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3735 3736 static const struct snd_kcontrol_new tx_adc_mux0_mux = 3737 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3738 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3739 static const struct snd_kcontrol_new tx_adc_mux1_mux = 3740 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3741 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3742 static const struct snd_kcontrol_new tx_adc_mux2_mux = 3743 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3744 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3745 static const struct snd_kcontrol_new tx_adc_mux3_mux = 3746 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3747 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3748 static const struct snd_kcontrol_new tx_adc_mux4_mux = 3749 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3750 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3751 static const struct snd_kcontrol_new tx_adc_mux5_mux = 3752 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3753 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3754 static const struct snd_kcontrol_new tx_adc_mux6_mux = 3755 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3756 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3757 static const struct snd_kcontrol_new tx_adc_mux7_mux = 3758 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3759 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3760 static const struct snd_kcontrol_new tx_adc_mux8_mux = 3761 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3762 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3763 3764 static const struct snd_kcontrol_new cdc_if_tx0_mux = 3765 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3766 static const struct snd_kcontrol_new cdc_if_tx1_mux = 3767 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3768 static const struct snd_kcontrol_new cdc_if_tx2_mux = 3769 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3770 static const struct snd_kcontrol_new cdc_if_tx3_mux = 3771 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3772 static const struct snd_kcontrol_new cdc_if_tx4_mux = 3773 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3774 static const struct snd_kcontrol_new cdc_if_tx5_mux = 3775 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3776 static const struct snd_kcontrol_new cdc_if_tx6_mux = 3777 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3778 static const struct snd_kcontrol_new cdc_if_tx7_mux = 3779 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3780 static const struct snd_kcontrol_new cdc_if_tx8_mux = 3781 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3782 static const struct snd_kcontrol_new cdc_if_tx9_mux = 3783 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3784 static const struct snd_kcontrol_new cdc_if_tx10_mux = 3785 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3786 static const struct snd_kcontrol_new cdc_if_tx11_mux = 3787 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3788 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3789 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3790 static const struct snd_kcontrol_new cdc_if_tx13_mux = 3791 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3792 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3793 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3794 3795 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3796 struct snd_ctl_elem_value *ucontrol) 3797 { 3798 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3799 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3800 struct soc_mixer_control *mixer = 3801 (struct soc_mixer_control *)kc->private_value; 3802 int port_id = mixer->shift; 3803 3804 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3805 3806 return 0; 3807 } 3808 3809 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3810 struct snd_ctl_elem_value *ucontrol) 3811 { 3812 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 3813 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev); 3814 struct snd_soc_dapm_update *update = NULL; 3815 struct soc_mixer_control *mixer = 3816 (struct soc_mixer_control *)kc->private_value; 3817 int enable = ucontrol->value.integer.value[0]; 3818 int dai_id = widget->shift; 3819 int port_id = mixer->shift; 3820 3821 /* only add to the list if value not set */ 3822 if (enable == wcd->tx_port_value[port_id]) 3823 return 0; 3824 3825 wcd->tx_port_value[port_id] = enable; 3826 3827 if (enable) 3828 list_add_tail(&wcd->tx_chs[port_id].list, 3829 &wcd->dai[dai_id].slim_ch_list); 3830 else 3831 list_del_init(&wcd->tx_chs[port_id].list); 3832 3833 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3834 3835 return 0; 3836 } 3837 3838 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3839 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3840 slim_tx_mixer_get, slim_tx_mixer_put), 3841 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3842 slim_tx_mixer_get, slim_tx_mixer_put), 3843 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3844 slim_tx_mixer_get, slim_tx_mixer_put), 3845 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3846 slim_tx_mixer_get, slim_tx_mixer_put), 3847 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3848 slim_tx_mixer_get, slim_tx_mixer_put), 3849 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3850 slim_tx_mixer_get, slim_tx_mixer_put), 3851 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3852 slim_tx_mixer_get, slim_tx_mixer_put), 3853 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3854 slim_tx_mixer_get, slim_tx_mixer_put), 3855 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3856 slim_tx_mixer_get, slim_tx_mixer_put), 3857 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3858 slim_tx_mixer_get, slim_tx_mixer_put), 3859 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3860 slim_tx_mixer_get, slim_tx_mixer_put), 3861 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3862 slim_tx_mixer_get, slim_tx_mixer_put), 3863 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3864 slim_tx_mixer_get, slim_tx_mixer_put), 3865 }; 3866 3867 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3868 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3869 slim_tx_mixer_get, slim_tx_mixer_put), 3870 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3871 slim_tx_mixer_get, slim_tx_mixer_put), 3872 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3873 slim_tx_mixer_get, slim_tx_mixer_put), 3874 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3875 slim_tx_mixer_get, slim_tx_mixer_put), 3876 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3877 slim_tx_mixer_get, slim_tx_mixer_put), 3878 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3879 slim_tx_mixer_get, slim_tx_mixer_put), 3880 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3881 slim_tx_mixer_get, slim_tx_mixer_put), 3882 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3883 slim_tx_mixer_get, slim_tx_mixer_put), 3884 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3885 slim_tx_mixer_get, slim_tx_mixer_put), 3886 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3887 slim_tx_mixer_get, slim_tx_mixer_put), 3888 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3889 slim_tx_mixer_get, slim_tx_mixer_put), 3890 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3891 slim_tx_mixer_get, slim_tx_mixer_put), 3892 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3893 slim_tx_mixer_get, slim_tx_mixer_put), 3894 }; 3895 3896 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3897 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3898 slim_tx_mixer_get, slim_tx_mixer_put), 3899 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3904 slim_tx_mixer_get, slim_tx_mixer_put), 3905 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3906 slim_tx_mixer_get, slim_tx_mixer_put), 3907 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3908 slim_tx_mixer_get, slim_tx_mixer_put), 3909 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3910 slim_tx_mixer_get, slim_tx_mixer_put), 3911 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3912 slim_tx_mixer_get, slim_tx_mixer_put), 3913 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3914 slim_tx_mixer_get, slim_tx_mixer_put), 3915 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3916 slim_tx_mixer_get, slim_tx_mixer_put), 3917 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3918 slim_tx_mixer_get, slim_tx_mixer_put), 3919 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3920 slim_tx_mixer_get, slim_tx_mixer_put), 3921 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3922 slim_tx_mixer_get, slim_tx_mixer_put), 3923 }; 3924 3925 static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3926 /* Gain Controls */ 3927 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3928 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3929 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3930 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3931 3, 16, 1, line_gain), 3932 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3933 3, 16, 1, line_gain), 3934 3935 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3936 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3937 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3938 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3939 3940 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3941 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3942 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3943 -84, 40, digital_gain), 3944 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3945 -84, 40, digital_gain), 3946 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3947 -84, 40, digital_gain), 3948 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3949 -84, 40, digital_gain), 3950 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 3951 -84, 40, digital_gain), 3952 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 3953 -84, 40, digital_gain), 3954 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 3955 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 3956 -84, 40, digital_gain), 3957 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 3958 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 3959 -84, 40, digital_gain), 3960 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 3961 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 3962 -84, 40, digital_gain), 3963 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 3964 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 3965 -84, 40, digital_gain), 3966 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 3967 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 3968 -84, 40, digital_gain), 3969 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 3970 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 3971 -84, 40, digital_gain), 3972 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 3973 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 3974 -84, 40, digital_gain), 3975 3976 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 3977 -84, 40, digital_gain), 3978 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 3979 -84, 40, digital_gain), 3980 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 3981 -84, 40, digital_gain), 3982 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 3983 -84, 40, digital_gain), 3984 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 3985 -84, 40, digital_gain), 3986 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 3987 -84, 40, digital_gain), 3988 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 3989 -84, 40, digital_gain), 3990 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 3991 -84, 40, digital_gain), 3992 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 3993 -84, 40, digital_gain), 3994 3995 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3996 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3997 digital_gain), 3998 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 3999 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 4000 digital_gain), 4001 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 4002 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 4003 digital_gain), 4004 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 4005 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 4006 digital_gain), 4007 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4008 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4009 digital_gain), 4010 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4011 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4012 digital_gain), 4013 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4014 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4015 digital_gain), 4016 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4017 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4018 digital_gain), 4019 4020 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4021 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4022 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4023 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4024 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4025 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4026 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4027 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4028 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4029 4030 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4031 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4032 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4033 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4034 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4035 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4036 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4037 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4038 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4039 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4040 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4041 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4042 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4043 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4044 4045 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4046 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4047 4048 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4049 0, 1, 0), 4050 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4051 1, 1, 0), 4052 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4053 2, 1, 0), 4054 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4055 3, 1, 0), 4056 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4057 4, 1, 0), 4058 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4059 0, 1, 0), 4060 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4061 1, 1, 0), 4062 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4063 2, 1, 0), 4064 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4065 3, 1, 0), 4066 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4067 4, 1, 0), 4068 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4069 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4070 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4071 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4072 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4073 4074 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4075 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4076 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4077 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4078 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4079 4080 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4081 wcd934x_compander_get, wcd934x_compander_set), 4082 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4083 wcd934x_compander_get, wcd934x_compander_set), 4084 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4085 wcd934x_compander_get, wcd934x_compander_set), 4086 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4087 wcd934x_compander_get, wcd934x_compander_set), 4088 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4089 wcd934x_compander_get, wcd934x_compander_set), 4090 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4091 wcd934x_compander_get, wcd934x_compander_set), 4092 }; 4093 4094 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4095 struct snd_soc_component *component) 4096 { 4097 int port_num = 0; 4098 unsigned short reg = 0; 4099 unsigned int val = 0; 4100 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4101 struct wcd934x_slim_ch *ch; 4102 4103 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4104 if (ch->port >= WCD934X_RX_START) { 4105 port_num = ch->port - WCD934X_RX_START; 4106 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4107 } else { 4108 port_num = ch->port; 4109 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4110 } 4111 4112 regmap_read(wcd->if_regmap, reg, &val); 4113 if (!(val & BIT(port_num % 8))) 4114 regmap_write(wcd->if_regmap, reg, 4115 val | BIT(port_num % 8)); 4116 } 4117 } 4118 4119 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4120 struct snd_kcontrol *kc, int event) 4121 { 4122 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4123 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4124 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4125 4126 switch (event) { 4127 case SND_SOC_DAPM_POST_PMU: 4128 wcd934x_codec_enable_int_port(dai, comp); 4129 break; 4130 } 4131 4132 return 0; 4133 } 4134 4135 static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4136 u16 interp_idx, int event) 4137 { 4138 u16 hd2_scale_reg; 4139 u16 hd2_enable_reg = 0; 4140 4141 switch (interp_idx) { 4142 case INTERP_HPHL: 4143 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4144 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4145 break; 4146 case INTERP_HPHR: 4147 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4148 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4149 break; 4150 default: 4151 return; 4152 } 4153 4154 if (SND_SOC_DAPM_EVENT_ON(event)) { 4155 snd_soc_component_update_bits(component, hd2_scale_reg, 4156 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4157 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4158 snd_soc_component_update_bits(component, hd2_enable_reg, 4159 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4160 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4161 } 4162 4163 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4164 snd_soc_component_update_bits(component, hd2_enable_reg, 4165 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4166 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4167 snd_soc_component_update_bits(component, hd2_scale_reg, 4168 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4169 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4170 } 4171 } 4172 4173 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4174 u16 interp_idx, int event) 4175 { 4176 u8 hph_dly_mask; 4177 u16 hph_lut_bypass_reg = 0; 4178 4179 switch (interp_idx) { 4180 case INTERP_HPHL: 4181 hph_dly_mask = 1; 4182 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4183 break; 4184 case INTERP_HPHR: 4185 hph_dly_mask = 2; 4186 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4187 break; 4188 default: 4189 return; 4190 } 4191 4192 if (SND_SOC_DAPM_EVENT_ON(event)) { 4193 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4194 hph_dly_mask, 0x0); 4195 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4196 WCD934X_HPH_LUT_BYPASS_MASK, 4197 WCD934X_HPH_LUT_BYPASS_ENABLE); 4198 } 4199 4200 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4201 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4202 hph_dly_mask, hph_dly_mask); 4203 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4204 WCD934X_HPH_LUT_BYPASS_MASK, 4205 WCD934X_HPH_LUT_BYPASS_DISABLE); 4206 } 4207 } 4208 4209 static int wcd934x_config_compander(struct snd_soc_component *comp, 4210 int interp_n, int event) 4211 { 4212 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4213 int compander; 4214 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4215 4216 /* EAR does not have compander */ 4217 if (!interp_n) 4218 return 0; 4219 4220 compander = interp_n - 1; 4221 if (!wcd->comp_enabled[compander]) 4222 return 0; 4223 4224 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4225 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4226 4227 switch (event) { 4228 case SND_SOC_DAPM_PRE_PMU: 4229 /* Enable Compander Clock */ 4230 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4231 WCD934X_COMP_CLK_EN_MASK, 4232 WCD934X_COMP_CLK_ENABLE); 4233 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4234 WCD934X_COMP_SOFT_RST_MASK, 4235 WCD934X_COMP_SOFT_RST_ENABLE); 4236 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4237 WCD934X_COMP_SOFT_RST_MASK, 4238 WCD934X_COMP_SOFT_RST_DISABLE); 4239 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4240 WCD934X_HPH_CMP_EN_MASK, 4241 WCD934X_HPH_CMP_ENABLE); 4242 break; 4243 case SND_SOC_DAPM_POST_PMD: 4244 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4245 WCD934X_HPH_CMP_EN_MASK, 4246 WCD934X_HPH_CMP_DISABLE); 4247 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4248 WCD934X_COMP_HALT_MASK, 4249 WCD934X_COMP_HALT); 4250 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4251 WCD934X_COMP_SOFT_RST_MASK, 4252 WCD934X_COMP_SOFT_RST_ENABLE); 4253 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4254 WCD934X_COMP_SOFT_RST_MASK, 4255 WCD934X_COMP_SOFT_RST_DISABLE); 4256 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4257 WCD934X_COMP_CLK_EN_MASK, 0x0); 4258 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4259 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4260 break; 4261 } 4262 4263 return 0; 4264 } 4265 4266 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4267 struct snd_kcontrol *kc, int event) 4268 { 4269 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4270 int interp_idx = w->shift; 4271 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4272 4273 switch (event) { 4274 case SND_SOC_DAPM_PRE_PMU: 4275 /* Clk enable */ 4276 snd_soc_component_update_bits(comp, main_reg, 4277 WCD934X_RX_CLK_EN_MASK, 4278 WCD934X_RX_CLK_ENABLE); 4279 wcd934x_codec_hd2_control(comp, interp_idx, event); 4280 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4281 wcd934x_config_compander(comp, interp_idx, event); 4282 break; 4283 case SND_SOC_DAPM_POST_PMD: 4284 wcd934x_config_compander(comp, interp_idx, event); 4285 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4286 wcd934x_codec_hd2_control(comp, interp_idx, event); 4287 /* Clk Disable */ 4288 snd_soc_component_update_bits(comp, main_reg, 4289 WCD934X_RX_CLK_EN_MASK, 0); 4290 /* Reset enable and disable */ 4291 snd_soc_component_update_bits(comp, main_reg, 4292 WCD934X_RX_RESET_MASK, 4293 WCD934X_RX_RESET_ENABLE); 4294 snd_soc_component_update_bits(comp, main_reg, 4295 WCD934X_RX_RESET_MASK, 4296 WCD934X_RX_RESET_DISABLE); 4297 /* Reset rate to 48K*/ 4298 snd_soc_component_update_bits(comp, main_reg, 4299 WCD934X_RX_PCM_RATE_MASK, 4300 WCD934X_RX_PCM_RATE_F_48K); 4301 break; 4302 } 4303 4304 return 0; 4305 } 4306 4307 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4308 struct snd_kcontrol *kc, int event) 4309 { 4310 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4311 int offset_val = 0; 4312 u16 gain_reg, mix_reg; 4313 int val = 0; 4314 4315 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4316 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4317 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4318 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4319 4320 switch (event) { 4321 case SND_SOC_DAPM_PRE_PMU: 4322 /* Clk enable */ 4323 snd_soc_component_update_bits(comp, mix_reg, 4324 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4325 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4326 break; 4327 4328 case SND_SOC_DAPM_POST_PMU: 4329 val = snd_soc_component_read(comp, gain_reg); 4330 val += offset_val; 4331 snd_soc_component_write(comp, gain_reg, val); 4332 break; 4333 } 4334 4335 return 0; 4336 } 4337 4338 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4339 struct snd_kcontrol *kcontrol, int event) 4340 { 4341 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4342 int reg = w->reg; 4343 4344 switch (event) { 4345 case SND_SOC_DAPM_POST_PMU: 4346 /* B1 GAIN */ 4347 snd_soc_component_write(comp, reg, 4348 snd_soc_component_read(comp, reg)); 4349 /* B2 GAIN */ 4350 reg++; 4351 snd_soc_component_write(comp, reg, 4352 snd_soc_component_read(comp, reg)); 4353 /* B3 GAIN */ 4354 reg++; 4355 snd_soc_component_write(comp, reg, 4356 snd_soc_component_read(comp, reg)); 4357 /* B4 GAIN */ 4358 reg++; 4359 snd_soc_component_write(comp, reg, 4360 snd_soc_component_read(comp, reg)); 4361 /* B5 GAIN */ 4362 reg++; 4363 snd_soc_component_write(comp, reg, 4364 snd_soc_component_read(comp, reg)); 4365 break; 4366 default: 4367 break; 4368 } 4369 return 0; 4370 } 4371 4372 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4373 struct snd_kcontrol *kcontrol, 4374 int event) 4375 { 4376 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4377 u16 gain_reg; 4378 4379 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4380 WCD934X_RX_PATH_CTL_OFFSET); 4381 4382 switch (event) { 4383 case SND_SOC_DAPM_POST_PMU: 4384 snd_soc_component_write(comp, gain_reg, 4385 snd_soc_component_read(comp, gain_reg)); 4386 break; 4387 } 4388 4389 return 0; 4390 } 4391 4392 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4393 struct snd_kcontrol *kc, int event) 4394 { 4395 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4396 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4397 4398 switch (event) { 4399 case SND_SOC_DAPM_PRE_PMU: 4400 /* Disable AutoChop timer during power up */ 4401 snd_soc_component_update_bits(comp, 4402 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4403 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4404 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4405 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4406 4407 break; 4408 case SND_SOC_DAPM_POST_PMD: 4409 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4410 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4411 break; 4412 } 4413 4414 return 0; 4415 } 4416 4417 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4418 struct snd_kcontrol *kcontrol, 4419 int event) 4420 { 4421 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4422 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4423 int hph_mode = wcd->hph_mode; 4424 u8 dem_inp; 4425 4426 switch (event) { 4427 case SND_SOC_DAPM_PRE_PMU: 4428 /* Read DEM INP Select */ 4429 dem_inp = snd_soc_component_read(comp, 4430 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4431 4432 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4433 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4434 return -EINVAL; 4435 } 4436 if (hph_mode != CLS_H_LP) 4437 /* Ripple freq control enable */ 4438 snd_soc_component_update_bits(comp, 4439 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4440 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4441 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4442 /* Disable AutoChop timer during power up */ 4443 snd_soc_component_update_bits(comp, 4444 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4445 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4446 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4447 WCD_CLSH_STATE_HPHL, hph_mode); 4448 4449 break; 4450 case SND_SOC_DAPM_POST_PMD: 4451 /* 1000us required as per HW requirement */ 4452 usleep_range(1000, 1100); 4453 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4454 WCD_CLSH_STATE_HPHL, hph_mode); 4455 if (hph_mode != CLS_H_LP) 4456 /* Ripple freq control disable */ 4457 snd_soc_component_update_bits(comp, 4458 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4459 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4460 4461 break; 4462 default: 4463 break; 4464 } 4465 4466 return 0; 4467 } 4468 4469 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4470 struct snd_kcontrol *kcontrol, 4471 int event) 4472 { 4473 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4474 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4475 int hph_mode = wcd->hph_mode; 4476 u8 dem_inp; 4477 4478 switch (event) { 4479 case SND_SOC_DAPM_PRE_PMU: 4480 dem_inp = snd_soc_component_read(comp, 4481 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4482 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4483 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4484 return -EINVAL; 4485 } 4486 if (hph_mode != CLS_H_LP) 4487 /* Ripple freq control enable */ 4488 snd_soc_component_update_bits(comp, 4489 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4490 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4491 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4492 /* Disable AutoChop timer during power up */ 4493 snd_soc_component_update_bits(comp, 4494 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4495 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4496 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4497 WCD_CLSH_STATE_HPHR, 4498 hph_mode); 4499 break; 4500 case SND_SOC_DAPM_POST_PMD: 4501 /* 1000us required as per HW requirement */ 4502 usleep_range(1000, 1100); 4503 4504 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4505 WCD_CLSH_STATE_HPHR, hph_mode); 4506 if (hph_mode != CLS_H_LP) 4507 /* Ripple freq control disable */ 4508 snd_soc_component_update_bits(comp, 4509 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4510 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4511 break; 4512 default: 4513 break; 4514 } 4515 4516 return 0; 4517 } 4518 4519 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4520 struct snd_kcontrol *kc, int event) 4521 { 4522 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4523 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4524 4525 switch (event) { 4526 case SND_SOC_DAPM_PRE_PMU: 4527 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4528 WCD_CLSH_STATE_LO, CLS_AB); 4529 break; 4530 case SND_SOC_DAPM_POST_PMD: 4531 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4532 WCD_CLSH_STATE_LO, CLS_AB); 4533 break; 4534 } 4535 4536 return 0; 4537 } 4538 4539 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4540 struct snd_kcontrol *kcontrol, 4541 int event) 4542 { 4543 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4544 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4545 4546 switch (event) { 4547 case SND_SOC_DAPM_POST_PMU: 4548 /* 4549 * 7ms sleep is required after PA is enabled as per 4550 * HW requirement. If compander is disabled, then 4551 * 20ms delay is needed. 4552 */ 4553 usleep_range(20000, 20100); 4554 4555 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4556 WCD934X_HPH_OCP_DET_MASK, 4557 WCD934X_HPH_OCP_DET_ENABLE); 4558 /* Remove Mute on primary path */ 4559 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4560 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4561 0); 4562 /* Enable GM3 boost */ 4563 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4564 WCD934X_HPH_GM3_BOOST_EN_MASK, 4565 WCD934X_HPH_GM3_BOOST_ENABLE); 4566 /* Enable AutoChop timer at the end of power up */ 4567 snd_soc_component_update_bits(comp, 4568 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4569 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4570 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4571 /* Remove mix path mute */ 4572 snd_soc_component_update_bits(comp, 4573 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4574 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4575 break; 4576 case SND_SOC_DAPM_PRE_PMD: 4577 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4578 /* Enable DSD Mute before PA disable */ 4579 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4580 WCD934X_HPH_OCP_DET_MASK, 4581 WCD934X_HPH_OCP_DET_DISABLE); 4582 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4583 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4584 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4585 snd_soc_component_update_bits(comp, 4586 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4587 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4588 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4589 break; 4590 case SND_SOC_DAPM_POST_PMD: 4591 /* 4592 * 5ms sleep is required after PA disable. If compander is 4593 * disabled, then 20ms delay is needed after PA disable. 4594 */ 4595 usleep_range(20000, 20100); 4596 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4597 break; 4598 } 4599 4600 return 0; 4601 } 4602 4603 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4604 struct snd_kcontrol *kcontrol, 4605 int event) 4606 { 4607 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4608 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4609 4610 switch (event) { 4611 case SND_SOC_DAPM_POST_PMU: 4612 /* 4613 * 7ms sleep is required after PA is enabled as per 4614 * HW requirement. If compander is disabled, then 4615 * 20ms delay is needed. 4616 */ 4617 usleep_range(20000, 20100); 4618 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4619 WCD934X_HPH_OCP_DET_MASK, 4620 WCD934X_HPH_OCP_DET_ENABLE); 4621 /* Remove mute */ 4622 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4623 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4624 0); 4625 /* Enable GM3 boost */ 4626 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4627 WCD934X_HPH_GM3_BOOST_EN_MASK, 4628 WCD934X_HPH_GM3_BOOST_ENABLE); 4629 /* Enable AutoChop timer at the end of power up */ 4630 snd_soc_component_update_bits(comp, 4631 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4632 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4633 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4634 /* Remove mix path mute if it is enabled */ 4635 if ((snd_soc_component_read(comp, 4636 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4637 snd_soc_component_update_bits(comp, 4638 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4639 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4640 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4641 break; 4642 case SND_SOC_DAPM_PRE_PMD: 4643 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4644 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4645 WCD934X_HPH_OCP_DET_MASK, 4646 WCD934X_HPH_OCP_DET_DISABLE); 4647 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4648 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4649 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4650 snd_soc_component_update_bits(comp, 4651 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4652 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4653 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4654 break; 4655 case SND_SOC_DAPM_POST_PMD: 4656 /* 4657 * 5ms sleep is required after PA disable. If compander is 4658 * disabled, then 20ms delay is needed after PA disable. 4659 */ 4660 usleep_range(20000, 20100); 4661 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4662 break; 4663 } 4664 4665 return 0; 4666 } 4667 4668 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4669 unsigned int dmic, 4670 struct wcd934x_codec *wcd) 4671 { 4672 u8 tx_stream_fs; 4673 u8 adc_mux_index = 0, adc_mux_sel = 0; 4674 bool dec_found = false; 4675 u16 adc_mux_ctl_reg, tx_fs_reg; 4676 u32 dmic_fs; 4677 4678 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4679 if (adc_mux_index < 4) { 4680 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4681 (adc_mux_index * 2); 4682 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4683 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4684 adc_mux_index - 4; 4685 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4686 ++adc_mux_index; 4687 continue; 4688 } 4689 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4690 & 0xF8) >> 3) - 1; 4691 4692 if (adc_mux_sel == dmic) { 4693 dec_found = true; 4694 break; 4695 } 4696 4697 ++adc_mux_index; 4698 } 4699 4700 if (dec_found && adc_mux_index <= 8) { 4701 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4702 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4703 if (tx_stream_fs <= 4) { 4704 if (wcd->dmic_sample_rate <= 4705 WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ) 4706 dmic_fs = wcd->dmic_sample_rate; 4707 else 4708 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ; 4709 } else 4710 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4711 } else { 4712 dmic_fs = wcd->dmic_sample_rate; 4713 } 4714 4715 return dmic_fs; 4716 } 4717 4718 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4719 u32 mclk_rate, u32 dmic_clk_rate) 4720 { 4721 u32 div_factor; 4722 u8 dmic_ctl_val; 4723 4724 /* Default value to return in case of error */ 4725 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4726 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4727 else 4728 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4729 4730 if (dmic_clk_rate == 0) { 4731 dev_err(comp->dev, 4732 "%s: dmic_sample_rate cannot be 0\n", 4733 __func__); 4734 goto done; 4735 } 4736 4737 div_factor = mclk_rate / dmic_clk_rate; 4738 switch (div_factor) { 4739 case 2: 4740 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4741 break; 4742 case 3: 4743 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4744 break; 4745 case 4: 4746 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4747 break; 4748 case 6: 4749 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4750 break; 4751 case 8: 4752 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4753 break; 4754 case 16: 4755 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4756 break; 4757 default: 4758 dev_err(comp->dev, 4759 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4760 __func__, div_factor, mclk_rate, dmic_clk_rate); 4761 break; 4762 } 4763 4764 done: 4765 return dmic_ctl_val; 4766 } 4767 4768 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4769 struct snd_kcontrol *kcontrol, int event) 4770 { 4771 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4772 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4773 u8 dmic_clk_en = 0x01; 4774 u16 dmic_clk_reg; 4775 s32 *dmic_clk_cnt; 4776 u8 dmic_rate_val, dmic_rate_shift = 1; 4777 unsigned int dmic; 4778 u32 dmic_sample_rate; 4779 int ret; 4780 char *wname; 4781 4782 wname = strpbrk(w->name, "012345"); 4783 if (!wname) { 4784 dev_err(comp->dev, "%s: widget not found\n", __func__); 4785 return -EINVAL; 4786 } 4787 4788 ret = kstrtouint(wname, 10, &dmic); 4789 if (ret < 0) { 4790 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4791 __func__); 4792 return -EINVAL; 4793 } 4794 4795 switch (dmic) { 4796 case 0: 4797 case 1: 4798 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4799 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4800 break; 4801 case 2: 4802 case 3: 4803 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4804 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4805 break; 4806 case 4: 4807 case 5: 4808 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4809 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4810 break; 4811 default: 4812 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4813 __func__); 4814 return -EINVAL; 4815 } 4816 4817 switch (event) { 4818 case SND_SOC_DAPM_PRE_PMU: 4819 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4820 wcd); 4821 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4822 dmic_sample_rate); 4823 (*dmic_clk_cnt)++; 4824 if (*dmic_clk_cnt == 1) { 4825 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4826 snd_soc_component_update_bits(comp, dmic_clk_reg, 4827 WCD934X_DMIC_RATE_MASK, 4828 dmic_rate_val); 4829 snd_soc_component_update_bits(comp, dmic_clk_reg, 4830 dmic_clk_en, dmic_clk_en); 4831 } 4832 4833 break; 4834 case SND_SOC_DAPM_POST_PMD: 4835 (*dmic_clk_cnt)--; 4836 if (*dmic_clk_cnt == 0) 4837 snd_soc_component_update_bits(comp, dmic_clk_reg, 4838 dmic_clk_en, 0); 4839 break; 4840 } 4841 4842 return 0; 4843 } 4844 4845 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4846 int adc_mux_n) 4847 { 4848 u16 mask, shift, adc_mux_in_reg; 4849 u16 amic_mux_sel_reg; 4850 bool is_amic; 4851 4852 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4853 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4854 return 0; 4855 4856 if (adc_mux_n < 3) { 4857 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4858 adc_mux_n; 4859 mask = 0x03; 4860 shift = 0; 4861 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4862 2 * adc_mux_n; 4863 } else if (adc_mux_n < 4) { 4864 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4865 mask = 0x03; 4866 shift = 0; 4867 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4868 2 * adc_mux_n; 4869 } else if (adc_mux_n < 7) { 4870 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4871 (adc_mux_n - 4); 4872 mask = 0x0C; 4873 shift = 2; 4874 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4875 adc_mux_n - 4; 4876 } else if (adc_mux_n < 8) { 4877 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4878 mask = 0x0C; 4879 shift = 2; 4880 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4881 adc_mux_n - 4; 4882 } else if (adc_mux_n < 12) { 4883 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4884 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4885 (adc_mux_n - 9)); 4886 mask = 0x30; 4887 shift = 4; 4888 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4889 adc_mux_n - 4; 4890 } else if (adc_mux_n < 13) { 4891 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4892 mask = 0x30; 4893 shift = 4; 4894 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4895 adc_mux_n - 4; 4896 } else { 4897 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4898 mask = 0xC0; 4899 shift = 6; 4900 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4901 adc_mux_n - 4; 4902 } 4903 4904 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4905 & mask) >> shift) == 1); 4906 if (!is_amic) 4907 return 0; 4908 4909 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4910 } 4911 4912 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4913 int amic) 4914 { 4915 u16 pwr_level_reg = 0; 4916 4917 switch (amic) { 4918 case 1: 4919 case 2: 4920 pwr_level_reg = WCD934X_ANA_AMIC1; 4921 break; 4922 4923 case 3: 4924 case 4: 4925 pwr_level_reg = WCD934X_ANA_AMIC3; 4926 break; 4927 default: 4928 break; 4929 } 4930 4931 return pwr_level_reg; 4932 } 4933 4934 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4935 struct snd_kcontrol *kcontrol, int event) 4936 { 4937 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4938 unsigned int decimator; 4939 char *dec_adc_mux_name = NULL; 4940 char *widget_name = NULL; 4941 char *wname; 4942 int ret = 0, amic_n; 4943 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4944 u16 tx_gain_ctl_reg; 4945 char *dec; 4946 u8 hpf_coff_freq; 4947 4948 widget_name = kstrndup(w->name, 15, GFP_KERNEL); 4949 if (!widget_name) 4950 return -ENOMEM; 4951 4952 wname = widget_name; 4953 dec_adc_mux_name = strsep(&widget_name, " "); 4954 if (!dec_adc_mux_name) { 4955 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4956 __func__, w->name); 4957 ret = -EINVAL; 4958 goto out; 4959 } 4960 dec_adc_mux_name = widget_name; 4961 4962 dec = strpbrk(dec_adc_mux_name, "012345678"); 4963 if (!dec) { 4964 dev_err(comp->dev, "%s: decimator index not found\n", 4965 __func__); 4966 ret = -EINVAL; 4967 goto out; 4968 } 4969 4970 ret = kstrtouint(dec, 10, &decimator); 4971 if (ret < 0) { 4972 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 4973 __func__, wname); 4974 ret = -EINVAL; 4975 goto out; 4976 } 4977 4978 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 4979 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 4980 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 4981 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 4982 4983 switch (event) { 4984 case SND_SOC_DAPM_PRE_PMU: 4985 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 4986 if (amic_n) 4987 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 4988 amic_n); 4989 4990 if (!pwr_level_reg) 4991 break; 4992 4993 switch ((snd_soc_component_read(comp, pwr_level_reg) & 4994 WCD934X_AMIC_PWR_LVL_MASK) >> 4995 WCD934X_AMIC_PWR_LVL_SHIFT) { 4996 case WCD934X_AMIC_PWR_LEVEL_LP: 4997 snd_soc_component_update_bits(comp, dec_cfg_reg, 4998 WCD934X_DEC_PWR_LVL_MASK, 4999 WCD934X_DEC_PWR_LVL_LP); 5000 break; 5001 case WCD934X_AMIC_PWR_LEVEL_HP: 5002 snd_soc_component_update_bits(comp, dec_cfg_reg, 5003 WCD934X_DEC_PWR_LVL_MASK, 5004 WCD934X_DEC_PWR_LVL_HP); 5005 break; 5006 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 5007 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 5008 default: 5009 snd_soc_component_update_bits(comp, dec_cfg_reg, 5010 WCD934X_DEC_PWR_LVL_MASK, 5011 WCD934X_DEC_PWR_LVL_DF); 5012 break; 5013 } 5014 break; 5015 case SND_SOC_DAPM_POST_PMU: 5016 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5017 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5018 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5019 snd_soc_component_update_bits(comp, dec_cfg_reg, 5020 TX_HPF_CUT_OFF_FREQ_MASK, 5021 CF_MIN_3DB_150HZ << 5); 5022 snd_soc_component_update_bits(comp, hpf_gate_reg, 5023 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5024 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5025 /* 5026 * Minimum 1 clk cycle delay is required as per 5027 * HW spec. 5028 */ 5029 usleep_range(1000, 1010); 5030 snd_soc_component_update_bits(comp, hpf_gate_reg, 5031 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5032 0); 5033 } 5034 /* apply gain after decimator is enabled */ 5035 snd_soc_component_write(comp, tx_gain_ctl_reg, 5036 snd_soc_component_read(comp, 5037 tx_gain_ctl_reg)); 5038 break; 5039 case SND_SOC_DAPM_PRE_PMD: 5040 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5041 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5042 5043 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5044 snd_soc_component_update_bits(comp, dec_cfg_reg, 5045 TX_HPF_CUT_OFF_FREQ_MASK, 5046 hpf_coff_freq << 5); 5047 snd_soc_component_update_bits(comp, hpf_gate_reg, 5048 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5049 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5050 /* 5051 * Minimum 1 clk cycle delay is required as per 5052 * HW spec. 5053 */ 5054 usleep_range(1000, 1010); 5055 snd_soc_component_update_bits(comp, hpf_gate_reg, 5056 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5057 0); 5058 } 5059 break; 5060 case SND_SOC_DAPM_POST_PMD: 5061 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5062 0x10, 0x00); 5063 snd_soc_component_update_bits(comp, dec_cfg_reg, 5064 WCD934X_DEC_PWR_LVL_MASK, 5065 WCD934X_DEC_PWR_LVL_DF); 5066 break; 5067 } 5068 out: 5069 kfree(wname); 5070 return ret; 5071 } 5072 5073 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5074 u16 amic_reg, bool set) 5075 { 5076 u8 mask = 0x20; 5077 u8 val; 5078 5079 if (amic_reg == WCD934X_ANA_AMIC1 || 5080 amic_reg == WCD934X_ANA_AMIC3) 5081 mask = 0x40; 5082 5083 val = set ? mask : 0x00; 5084 5085 switch (amic_reg) { 5086 case WCD934X_ANA_AMIC1: 5087 case WCD934X_ANA_AMIC2: 5088 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5089 mask, val); 5090 break; 5091 case WCD934X_ANA_AMIC3: 5092 case WCD934X_ANA_AMIC4: 5093 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5094 mask, val); 5095 break; 5096 default: 5097 break; 5098 } 5099 } 5100 5101 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5102 struct snd_kcontrol *kcontrol, int event) 5103 { 5104 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5105 5106 switch (event) { 5107 case SND_SOC_DAPM_PRE_PMU: 5108 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5109 break; 5110 default: 5111 break; 5112 } 5113 5114 return 0; 5115 } 5116 5117 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5118 struct snd_kcontrol *kcontrol, 5119 int event) 5120 { 5121 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5122 int micb_num = w->shift; 5123 5124 switch (event) { 5125 case SND_SOC_DAPM_PRE_PMU: 5126 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5127 break; 5128 case SND_SOC_DAPM_POST_PMU: 5129 /* 1 msec delay as per HW requirement */ 5130 usleep_range(1000, 1100); 5131 break; 5132 case SND_SOC_DAPM_POST_PMD: 5133 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5134 break; 5135 } 5136 5137 return 0; 5138 } 5139 5140 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5141 /* Analog Outputs */ 5142 SND_SOC_DAPM_OUTPUT("EAR"), 5143 SND_SOC_DAPM_OUTPUT("HPHL"), 5144 SND_SOC_DAPM_OUTPUT("HPHR"), 5145 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5146 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5147 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5148 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5149 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5150 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5151 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5152 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5153 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5154 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5155 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5156 AIF1_PB, 0, wcd934x_codec_enable_slim, 5157 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5158 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5159 AIF2_PB, 0, wcd934x_codec_enable_slim, 5160 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5161 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5162 AIF3_PB, 0, wcd934x_codec_enable_slim, 5163 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5164 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5165 AIF4_PB, 0, wcd934x_codec_enable_slim, 5166 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5167 5168 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5169 &slim_rx_mux[WCD934X_RX0]), 5170 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5171 &slim_rx_mux[WCD934X_RX1]), 5172 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5173 &slim_rx_mux[WCD934X_RX2]), 5174 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5175 &slim_rx_mux[WCD934X_RX3]), 5176 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5177 &slim_rx_mux[WCD934X_RX4]), 5178 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5179 &slim_rx_mux[WCD934X_RX5]), 5180 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5181 &slim_rx_mux[WCD934X_RX6]), 5182 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5183 &slim_rx_mux[WCD934X_RX7]), 5184 5185 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5186 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5187 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5188 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5189 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5190 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5191 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5192 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5193 5194 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5195 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5196 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5197 SND_SOC_DAPM_POST_PMD), 5198 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5199 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5200 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5201 SND_SOC_DAPM_POST_PMD), 5202 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5203 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5204 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5205 SND_SOC_DAPM_POST_PMD), 5206 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5207 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5208 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5209 SND_SOC_DAPM_POST_PMD), 5210 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5211 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5212 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5213 SND_SOC_DAPM_POST_PMD), 5214 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5215 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5216 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5217 SND_SOC_DAPM_POST_PMD), 5218 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5219 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5220 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5221 SND_SOC_DAPM_POST_PMD), 5222 5223 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5224 &rx_int0_1_mix_inp0_mux), 5225 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5226 &rx_int0_1_mix_inp1_mux), 5227 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5228 &rx_int0_1_mix_inp2_mux), 5229 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5230 &rx_int1_1_mix_inp0_mux), 5231 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5232 &rx_int1_1_mix_inp1_mux), 5233 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5234 &rx_int1_1_mix_inp2_mux), 5235 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5236 &rx_int2_1_mix_inp0_mux), 5237 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5238 &rx_int2_1_mix_inp1_mux), 5239 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5240 &rx_int2_1_mix_inp2_mux), 5241 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5242 &rx_int3_1_mix_inp0_mux), 5243 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5244 &rx_int3_1_mix_inp1_mux), 5245 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5246 &rx_int3_1_mix_inp2_mux), 5247 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5248 &rx_int4_1_mix_inp0_mux), 5249 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5250 &rx_int4_1_mix_inp1_mux), 5251 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5252 &rx_int4_1_mix_inp2_mux), 5253 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5254 &rx_int7_1_mix_inp0_mux), 5255 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5256 &rx_int7_1_mix_inp1_mux), 5257 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5258 &rx_int7_1_mix_inp2_mux), 5259 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5260 &rx_int8_1_mix_inp0_mux), 5261 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5262 &rx_int8_1_mix_inp1_mux), 5263 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5264 &rx_int8_1_mix_inp2_mux), 5265 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5266 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5267 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5268 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5269 rx_int1_asrc_switch, 5270 ARRAY_SIZE(rx_int1_asrc_switch)), 5271 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5272 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5273 rx_int2_asrc_switch, 5274 ARRAY_SIZE(rx_int2_asrc_switch)), 5275 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5276 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5277 rx_int3_asrc_switch, 5278 ARRAY_SIZE(rx_int3_asrc_switch)), 5279 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5280 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5281 rx_int4_asrc_switch, 5282 ARRAY_SIZE(rx_int4_asrc_switch)), 5283 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5284 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5285 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5286 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5287 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5288 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5289 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5290 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5291 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5292 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5293 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5294 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5295 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5296 5297 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5298 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5299 NULL, 0, NULL, 0), 5300 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5301 NULL, 0, NULL, 0), 5302 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5303 0, &rx_int0_mix2_inp_mux, NULL, 5304 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5305 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5306 0, &rx_int1_mix2_inp_mux, NULL, 5307 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5308 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5309 0, &rx_int2_mix2_inp_mux, NULL, 5310 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5311 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5312 0, &rx_int3_mix2_inp_mux, NULL, 5313 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5314 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5315 0, &rx_int4_mix2_inp_mux, NULL, 5316 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5317 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5318 0, &rx_int7_mix2_inp_mux, NULL, 5319 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5320 5321 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5322 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5323 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5324 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5325 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5326 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5327 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5328 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5329 5330 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5331 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5332 SND_SOC_DAPM_POST_PMU), 5333 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5334 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5335 SND_SOC_DAPM_POST_PMU), 5336 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5337 4, 0, NULL, 0), 5338 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5339 4, 0, NULL, 0), 5340 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5341 &rx_int0_dem_inp_mux), 5342 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5343 &rx_int1_dem_inp_mux), 5344 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5345 &rx_int2_dem_inp_mux), 5346 5347 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5348 &rx_int0_1_interp_mux, 5349 wcd934x_codec_enable_main_path, 5350 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5351 SND_SOC_DAPM_POST_PMD), 5352 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5353 &rx_int1_1_interp_mux, 5354 wcd934x_codec_enable_main_path, 5355 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5356 SND_SOC_DAPM_POST_PMD), 5357 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5358 &rx_int2_1_interp_mux, 5359 wcd934x_codec_enable_main_path, 5360 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5361 SND_SOC_DAPM_POST_PMD), 5362 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5363 &rx_int3_1_interp_mux, 5364 wcd934x_codec_enable_main_path, 5365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5366 SND_SOC_DAPM_POST_PMD), 5367 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5368 &rx_int4_1_interp_mux, 5369 wcd934x_codec_enable_main_path, 5370 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5371 SND_SOC_DAPM_POST_PMD), 5372 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5373 &rx_int7_1_interp_mux, 5374 wcd934x_codec_enable_main_path, 5375 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5376 SND_SOC_DAPM_POST_PMD), 5377 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5378 &rx_int8_1_interp_mux, 5379 wcd934x_codec_enable_main_path, 5380 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5381 SND_SOC_DAPM_POST_PMD), 5382 5383 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5384 &rx_int0_2_interp_mux), 5385 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5386 &rx_int1_2_interp_mux), 5387 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5388 &rx_int2_2_interp_mux), 5389 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5390 &rx_int3_2_interp_mux), 5391 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5392 &rx_int4_2_interp_mux), 5393 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5394 &rx_int7_2_interp_mux), 5395 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5396 &rx_int8_2_interp_mux), 5397 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5398 0, 0, wcd934x_codec_ear_dac_event, 5399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5400 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5401 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5402 5, 0, wcd934x_codec_hphl_dac_event, 5403 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5404 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5405 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5406 4, 0, wcd934x_codec_hphr_dac_event, 5407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5408 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5409 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5410 0, 0, wcd934x_codec_lineout_dac_event, 5411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5412 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5413 0, 0, wcd934x_codec_lineout_dac_event, 5414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5415 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5416 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5417 wcd934x_codec_enable_hphl_pa, 5418 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5419 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5420 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5421 wcd934x_codec_enable_hphr_pa, 5422 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5423 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5424 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5425 NULL, 0), 5426 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5427 NULL, 0), 5428 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5430 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5431 0, 0, NULL, 0), 5432 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5433 0, 0, NULL, 0), 5434 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5435 0, 0, NULL, 0), 5436 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5437 0, 0, NULL, 0), 5438 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5439 wcd934x_codec_enable_interp_clk, 5440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5441 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5442 wcd934x_codec_enable_interp_clk, 5443 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5444 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5445 wcd934x_codec_enable_interp_clk, 5446 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5447 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5448 wcd934x_codec_enable_interp_clk, 5449 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5450 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5451 wcd934x_codec_enable_interp_clk, 5452 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5453 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5454 wcd934x_codec_enable_interp_clk, 5455 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5456 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5457 wcd934x_codec_enable_interp_clk, 5458 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5459 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5460 0, 0, NULL, 0), 5461 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5462 0, 0, NULL, 0), 5463 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5464 0, 0, NULL, 0), 5465 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5466 0, 0, NULL, 0), 5467 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5468 0, 0, NULL, 0), 5469 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5470 0, 0, NULL, 0), 5471 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5472 0, 0, NULL, 0), 5473 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5474 wcd934x_codec_enable_mclk, 5475 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5476 5477 /* TX */ 5478 SND_SOC_DAPM_INPUT("AMIC1"), 5479 SND_SOC_DAPM_INPUT("AMIC2"), 5480 SND_SOC_DAPM_INPUT("AMIC3"), 5481 SND_SOC_DAPM_INPUT("AMIC4"), 5482 SND_SOC_DAPM_INPUT("AMIC5"), 5483 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5484 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5485 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5486 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5487 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5488 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5489 5490 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5491 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5492 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5493 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5494 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5495 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5496 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5497 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5498 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5499 5500 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5501 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5502 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5503 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5504 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5505 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5506 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5507 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5508 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5509 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5510 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5511 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5512 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5513 5514 /* Digital Mic Inputs */ 5515 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5516 wcd934x_codec_enable_dmic, 5517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5518 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5519 wcd934x_codec_enable_dmic, 5520 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5521 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5522 wcd934x_codec_enable_dmic, 5523 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5524 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5525 wcd934x_codec_enable_dmic, 5526 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5527 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5528 wcd934x_codec_enable_dmic, 5529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5530 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5531 wcd934x_codec_enable_dmic, 5532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5533 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5534 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5535 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5536 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5537 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5538 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5539 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5540 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5541 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5542 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5543 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5544 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5545 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5546 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5547 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5548 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5549 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5550 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5551 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5552 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5553 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5554 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5555 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5556 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5558 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5559 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5560 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5562 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5563 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5564 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5566 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5567 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5568 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5570 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5571 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5572 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5573 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5574 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5575 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5576 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5577 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5578 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5579 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5580 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5581 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5582 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5583 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5584 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5585 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5586 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5587 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5588 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5589 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5590 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5591 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5592 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5593 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5594 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5595 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5596 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5597 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5598 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5599 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5600 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5601 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5602 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5603 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5604 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5605 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5606 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5607 5608 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5609 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5610 &cdc_if_tx0_mux), 5611 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5612 &cdc_if_tx1_mux), 5613 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5614 &cdc_if_tx2_mux), 5615 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5616 &cdc_if_tx3_mux), 5617 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5618 &cdc_if_tx4_mux), 5619 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5620 &cdc_if_tx5_mux), 5621 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5622 &cdc_if_tx6_mux), 5623 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5624 &cdc_if_tx7_mux), 5625 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5626 &cdc_if_tx8_mux), 5627 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5628 &cdc_if_tx9_mux), 5629 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5630 &cdc_if_tx10_mux), 5631 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5632 &cdc_if_tx11_mux), 5633 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5634 &cdc_if_tx11_inp1_mux), 5635 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5636 &cdc_if_tx13_mux), 5637 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5638 &cdc_if_tx13_inp1_mux), 5639 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5640 aif1_slim_cap_mixer, 5641 ARRAY_SIZE(aif1_slim_cap_mixer)), 5642 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5643 aif2_slim_cap_mixer, 5644 ARRAY_SIZE(aif2_slim_cap_mixer)), 5645 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5646 aif3_slim_cap_mixer, 5647 ARRAY_SIZE(aif3_slim_cap_mixer)), 5648 }; 5649 5650 static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5651 /* RX0-RX7 */ 5652 WCD934X_SLIM_RX_AIF_PATH(0), 5653 WCD934X_SLIM_RX_AIF_PATH(1), 5654 WCD934X_SLIM_RX_AIF_PATH(2), 5655 WCD934X_SLIM_RX_AIF_PATH(3), 5656 WCD934X_SLIM_RX_AIF_PATH(4), 5657 WCD934X_SLIM_RX_AIF_PATH(5), 5658 WCD934X_SLIM_RX_AIF_PATH(6), 5659 WCD934X_SLIM_RX_AIF_PATH(7), 5660 5661 /* RX0 Ear out */ 5662 WCD934X_INTERPOLATOR_PATH(0), 5663 WCD934X_INTERPOLATOR_MIX2(0), 5664 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5665 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5666 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5667 {"EAR PA", NULL, "RX INT0 DAC"}, 5668 {"EAR", NULL, "EAR PA"}, 5669 5670 /* RX1 Headphone left */ 5671 WCD934X_INTERPOLATOR_PATH(1), 5672 WCD934X_INTERPOLATOR_MIX2(1), 5673 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5674 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5675 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5676 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5677 {"HPHL PA", NULL, "RX INT1 DAC"}, 5678 {"HPHL", NULL, "HPHL PA"}, 5679 5680 /* RX2 Headphone right */ 5681 WCD934X_INTERPOLATOR_PATH(2), 5682 WCD934X_INTERPOLATOR_MIX2(2), 5683 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5684 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5685 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5686 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5687 {"HPHR PA", NULL, "RX INT2 DAC"}, 5688 {"HPHR", NULL, "HPHR PA"}, 5689 5690 /* RX3 HIFi LineOut1 */ 5691 WCD934X_INTERPOLATOR_PATH(3), 5692 WCD934X_INTERPOLATOR_MIX2(3), 5693 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5694 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5695 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5696 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5697 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5698 5699 /* RX4 HIFi LineOut2 */ 5700 WCD934X_INTERPOLATOR_PATH(4), 5701 WCD934X_INTERPOLATOR_MIX2(4), 5702 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5703 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5704 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5705 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5706 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5707 5708 /* RX7 Speaker Left Out PA */ 5709 WCD934X_INTERPOLATOR_PATH(7), 5710 WCD934X_INTERPOLATOR_MIX2(7), 5711 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5712 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5713 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5714 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5715 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5716 5717 /* RX8 Speaker Right Out PA */ 5718 WCD934X_INTERPOLATOR_PATH(8), 5719 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5720 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5721 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5722 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5723 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5724 5725 /* Tx */ 5726 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5727 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5728 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5729 5730 WCD934X_SLIM_TX_AIF_PATH(0), 5731 WCD934X_SLIM_TX_AIF_PATH(1), 5732 WCD934X_SLIM_TX_AIF_PATH(2), 5733 WCD934X_SLIM_TX_AIF_PATH(3), 5734 WCD934X_SLIM_TX_AIF_PATH(4), 5735 WCD934X_SLIM_TX_AIF_PATH(5), 5736 WCD934X_SLIM_TX_AIF_PATH(6), 5737 WCD934X_SLIM_TX_AIF_PATH(7), 5738 WCD934X_SLIM_TX_AIF_PATH(8), 5739 5740 WCD934X_ADC_MUX(0), 5741 WCD934X_ADC_MUX(1), 5742 WCD934X_ADC_MUX(2), 5743 WCD934X_ADC_MUX(3), 5744 WCD934X_ADC_MUX(4), 5745 WCD934X_ADC_MUX(5), 5746 WCD934X_ADC_MUX(6), 5747 WCD934X_ADC_MUX(7), 5748 WCD934X_ADC_MUX(8), 5749 5750 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5751 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5752 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5753 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5754 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5755 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5756 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5757 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5758 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5759 5760 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5761 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5762 5763 { "DMIC0", NULL, "DMIC0 Pin" }, 5764 { "DMIC1", NULL, "DMIC1 Pin" }, 5765 { "DMIC2", NULL, "DMIC2 Pin" }, 5766 { "DMIC3", NULL, "DMIC3 Pin" }, 5767 { "DMIC4", NULL, "DMIC4 Pin" }, 5768 { "DMIC5", NULL, "DMIC5 Pin" }, 5769 5770 {"ADC1", NULL, "AMIC1"}, 5771 {"ADC2", NULL, "AMIC2"}, 5772 {"ADC3", NULL, "AMIC3"}, 5773 {"ADC4", NULL, "AMIC4_5 SEL"}, 5774 5775 WCD934X_IIR_INP_MUX(0), 5776 WCD934X_IIR_INP_MUX(1), 5777 5778 {"SRC0", NULL, "IIR0"}, 5779 {"SRC1", NULL, "IIR1"}, 5780 }; 5781 5782 static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5783 struct snd_soc_jack *jack, void *data) 5784 { 5785 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5786 int ret = 0; 5787 5788 if (!wcd->mbhc) 5789 return -ENOTSUPP; 5790 5791 if (jack && !wcd->mbhc_started) { 5792 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5793 wcd->mbhc_started = true; 5794 } else if (wcd->mbhc_started) { 5795 wcd_mbhc_stop(wcd->mbhc); 5796 wcd->mbhc_started = false; 5797 } 5798 5799 return ret; 5800 } 5801 5802 static const struct snd_soc_component_driver wcd934x_component_drv = { 5803 .probe = wcd934x_comp_probe, 5804 .remove = wcd934x_comp_remove, 5805 .set_sysclk = wcd934x_comp_set_sysclk, 5806 .controls = wcd934x_snd_controls, 5807 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5808 .dapm_widgets = wcd934x_dapm_widgets, 5809 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5810 .dapm_routes = wcd934x_audio_map, 5811 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5812 .set_jack = wcd934x_codec_set_jack, 5813 }; 5814 5815 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5816 { 5817 struct device *dev = &wcd->sdev->dev; 5818 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5819 struct device_node *ifc_dev_np; 5820 5821 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5822 if (!ifc_dev_np) { 5823 dev_err(dev, "No Interface device found\n"); 5824 return -EINVAL; 5825 } 5826 5827 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5828 if (!wcd->sidev) { 5829 dev_err(dev, "Unable to get SLIM Interface device\n"); 5830 return -EINVAL; 5831 } 5832 5833 slim_get_logical_addr(wcd->sidev); 5834 wcd->if_regmap = regmap_init_slimbus(wcd->sidev, 5835 &wcd934x_ifc_regmap_config); 5836 if (IS_ERR(wcd->if_regmap)) { 5837 dev_err(dev, "Failed to allocate ifc register map\n"); 5838 return PTR_ERR(wcd->if_regmap); 5839 } 5840 5841 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5842 &wcd->dmic_sample_rate); 5843 5844 cfg->mbhc_micbias = MIC_BIAS_2; 5845 cfg->anc_micbias = MIC_BIAS_2; 5846 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5847 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5848 cfg->micb_mv = wcd->micb2_mv; 5849 cfg->linein_th = 5000; 5850 cfg->hs_thr = 1700; 5851 cfg->hph_thr = 50; 5852 5853 wcd_dt_parse_mbhc_data(dev, cfg); 5854 5855 5856 return 0; 5857 } 5858 5859 static int wcd934x_codec_probe(struct platform_device *pdev) 5860 { 5861 struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent); 5862 struct wcd934x_codec *wcd; 5863 struct device *dev = &pdev->dev; 5864 int ret, irq; 5865 5866 wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL); 5867 if (!wcd) 5868 return -ENOMEM; 5869 5870 wcd->dev = dev; 5871 wcd->regmap = data->regmap; 5872 wcd->extclk = data->extclk; 5873 wcd->sdev = to_slim_device(data->dev); 5874 mutex_init(&wcd->sysclk_mutex); 5875 mutex_init(&wcd->micb_lock); 5876 5877 ret = wcd934x_codec_parse_data(wcd); 5878 if (ret) { 5879 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5880 return ret; 5881 } 5882 5883 /* set default rate 9P6MHz */ 5884 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5885 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5886 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5887 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5888 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5889 5890 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5891 if (irq < 0) { 5892 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5893 return irq; 5894 } 5895 5896 ret = devm_request_threaded_irq(dev, irq, NULL, 5897 wcd934x_slim_irq_handler, 5898 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5899 "slim", wcd); 5900 if (ret) { 5901 dev_err(dev, "Failed to request slimbus irq\n"); 5902 return ret; 5903 } 5904 5905 wcd934x_register_mclk_output(wcd); 5906 platform_set_drvdata(pdev, wcd); 5907 5908 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5909 wcd934x_slim_dais, 5910 ARRAY_SIZE(wcd934x_slim_dais)); 5911 } 5912 5913 static const struct platform_device_id wcd934x_driver_id[] = { 5914 { 5915 .name = "wcd934x-codec", 5916 }, 5917 {}, 5918 }; 5919 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5920 5921 static struct platform_driver wcd934x_codec_driver = { 5922 .probe = &wcd934x_codec_probe, 5923 .id_table = wcd934x_driver_id, 5924 .driver = { 5925 .name = "wcd934x-codec", 5926 } 5927 }; 5928 5929 MODULE_ALIAS("platform:wcd934x-codec"); 5930 module_platform_driver(wcd934x_codec_driver); 5931 MODULE_DESCRIPTION("WCD934x codec driver"); 5932 MODULE_LICENSE("GPL v2"); 5933