120aedafdSSrinivas Kandagatla /* SPDX-License-Identifier: GPL-2.0 */ 220aedafdSSrinivas Kandagatla 320aedafdSSrinivas Kandagatla #ifndef __WCD9335_H__ 420aedafdSSrinivas Kandagatla #define __WCD9335_H__ 520aedafdSSrinivas Kandagatla 620aedafdSSrinivas Kandagatla /* 709e52090SRandy Dunlap * WCD9335 register base can change according to the mode it works in. 809e52090SRandy Dunlap * In slimbus mode the reg base starts from 0x800. 909e52090SRandy Dunlap * In i2s/i2c mode the reg base is 0x0. 1020aedafdSSrinivas Kandagatla */ 11d902e785SSrinivas Kandagatla #define WCD9335_REG(pg, r) ((pg << 8) | (r)) 1220aedafdSSrinivas Kandagatla #define WCD9335_REG_OFFSET(r) (r & 0xFF) 13d902e785SSrinivas Kandagatla #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF) 1420aedafdSSrinivas Kandagatla 1520aedafdSSrinivas Kandagatla /* Page-0 Registers */ 1620aedafdSSrinivas Kandagatla #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000) 1720aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002) 1820aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0) 1920aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003) 2020aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) 2120aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(0) 2220aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0) 2320aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_RST_CTL WCD9335_REG(0x00, 0x009) 2420aedafdSSrinivas Kandagatla #define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL WCD9335_REG(0x00, 0x011) 2520aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 WCD9335_REG(0x00, 0x021) 2620aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL WCD9335_REG(0x00, 0x025) 2720aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1) 2820aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK BIT(0) 2920aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE BIT(0) 3020aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 WCD9335_REG(0x00, 0x029) 3120aedafdSSrinivas Kandagatla #define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS WCD9335_REG(0x00, 0x039) 3220aedafdSSrinivas Kandagatla #define WCD9335_INTR_CFG WCD9335_REG(0x00, 0x081) 3320aedafdSSrinivas Kandagatla #define WCD9335_INTR_CLR_COMMIT WCD9335_REG(0x00, 0x082) 3420aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_MASK0 WCD9335_REG(0x00, 0x089) 3520aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_MASK1 WCD9335_REG(0x00, 0x08a) 3620aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_MASK2 WCD9335_REG(0x00, 0x08b) 3720aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_MASK3 WCD9335_REG(0x00, 0x08c) 3820aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_STATUS0 WCD9335_REG(0x00, 0x091) 3920aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_STATUS1 WCD9335_REG(0x00, 0x092) 4020aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_STATUS2 WCD9335_REG(0x00, 0x093) 4120aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_STATUS3 WCD9335_REG(0x00, 0x094) 4220aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_CLEAR0 WCD9335_REG(0x00, 0x099) 4320aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_CLEAR1 WCD9335_REG(0x00, 0x09a) 4420aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_CLEAR2 WCD9335_REG(0x00, 0x09b) 4520aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN1_CLEAR3 WCD9335_REG(0x00, 0x09c) 4620aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_MASK0 WCD9335_REG(0x00, 0x0a1) 4720aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_MASK1 WCD9335_REG(0x00, 0x0a2) 4820aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_MASK2 WCD9335_REG(0x00, 0x0a3) 4920aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_MASK3 WCD9335_REG(0x00, 0x0a4) 5020aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_STATUS0 WCD9335_REG(0x00, 0x0a9) 5120aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_STATUS1 WCD9335_REG(0x00, 0x0aa) 5220aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_STATUS2 WCD9335_REG(0x00, 0x0ab) 5320aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_STATUS3 WCD9335_REG(0x00, 0x0ac) 5420aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_CLEAR0 WCD9335_REG(0x00, 0x0b1) 5520aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_CLEAR1 WCD9335_REG(0x00, 0x0b2) 5620aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_CLEAR2 WCD9335_REG(0x00, 0x0b3) 5720aedafdSSrinivas Kandagatla #define WCD9335_INTR_PIN2_CLEAR3 WCD9335_REG(0x00, 0x0b4) 5820aedafdSSrinivas Kandagatla #define WCD9335_INTR_LEVEL0 WCD9335_REG(0x00, 0x0e1) 5920aedafdSSrinivas Kandagatla #define WCD9335_INTR_LEVEL1 WCD9335_REG(0x00, 0x0e2) 6020aedafdSSrinivas Kandagatla #define WCD9335_INTR_LEVEL2 WCD9335_REG(0x00, 0x0e3) 6120aedafdSSrinivas Kandagatla #define WCD9335_INTR_LEVEL3 WCD9335_REG(0x00, 0x0e4) 6220aedafdSSrinivas Kandagatla 6320aedafdSSrinivas Kandagatla /* Page-1 Registers */ 6420aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x001) 6520aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x002) 6620aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x003) 6720aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x004) 6820aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x005) 6920aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x006) 7020aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x007) 7120aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x008) 7220aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x009) 7320aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x00a) 7420aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x00b) 7520aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x00c) 7620aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x00d) 7720aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x00e) 7820aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x00f) 7920aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x010) 8020aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x011) 8120aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x012) 8220aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x013) 8320aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x014) 8420aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x015) 8520aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x016) 8620aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x017) 8720aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x018) 8820aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x019) 8920aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x01a) 9020aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x01b) 9120aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x01c) 9220aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x01d) 9320aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x01e) 9420aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x01f) 9520aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x020) 9620aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x021) 9720aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x022) 9820aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x023) 9920aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_FLL_MODE WCD9335_REG(0x01, 0x024) 10020aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_STATUS_0 WCD9335_REG(0x01, 0x025) 10120aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_STATUS_1 WCD9335_REG(0x01, 0x026) 10220aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_STATUS_2 WCD9335_REG(0x01, 0x027) 10320aedafdSSrinivas Kandagatla #define WCD9335_CPE_FLL_STATUS_3 WCD9335_REG(0x01, 0x028) 10420aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x041) 10520aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x042) 10620aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x043) 10720aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x044) 10820aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x045) 10920aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x046) 11020aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x047) 11120aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x048) 11220aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x049) 11320aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x04a) 11420aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x04b) 11520aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x04c) 11620aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x04d) 11720aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x04e) 11820aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x04f) 11920aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x050) 12020aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x051) 12120aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x052) 12220aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x053) 12320aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x054) 12420aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x055) 12520aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x056) 12620aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x057) 12720aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x058) 12820aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x059) 12920aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x05a) 13020aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x05b) 13120aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x05c) 13220aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x05d) 13320aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x05e) 13420aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x05f) 13520aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x060) 13620aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x061) 13720aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x062) 13820aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x063) 13920aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_FLL_MODE WCD9335_REG(0x01, 0x064) 14020aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_STATUS_0 WCD9335_REG(0x01, 0x065) 14120aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_STATUS_1 WCD9335_REG(0x01, 0x066) 14220aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_STATUS_2 WCD9335_REG(0x01, 0x067) 14320aedafdSSrinivas Kandagatla #define WCD9335_I2S_FLL_STATUS_3 WCD9335_REG(0x01, 0x068) 14420aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x081) 14520aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x082) 14620aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x083) 14720aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x084) 14820aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x085) 14920aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x086) 15020aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x087) 15120aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x088) 15220aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x089) 15320aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x08a) 15420aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x08b) 15520aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x08c) 15620aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x08d) 15720aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x08e) 15820aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x08f) 15920aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x090) 16020aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x091) 16120aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x092) 16220aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x093) 16320aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x094) 16420aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x095) 16520aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x096) 16620aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x097) 16720aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x098) 16820aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x099) 16920aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x09a) 17020aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x09b) 17120aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x09c) 17220aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x09d) 17320aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x09e) 17420aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x09f) 17520aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x0a0) 17620aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x0a1) 17720aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x0a2) 17820aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x0a3) 17920aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_FLL_MODE WCD9335_REG(0x01, 0x0a4) 18020aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_STATUS_0 WCD9335_REG(0x01, 0x0a5) 18120aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_STATUS_1 WCD9335_REG(0x01, 0x0a6) 18220aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_STATUS_2 WCD9335_REG(0x01, 0x0a7) 18320aedafdSSrinivas Kandagatla #define WCD9335_SB_FLL_STATUS_3 WCD9335_REG(0x01, 0x0a8) 18420aedafdSSrinivas Kandagatla 18520aedafdSSrinivas Kandagatla /* Page-2 Registers */ 18620aedafdSSrinivas Kandagatla #define WCD9335_PAGE2_PAGE_REGISTER WCD9335_REG(0x02, 0x000) 18720aedafdSSrinivas Kandagatla #define WCD9335_CPE_SS_DMIC0_CTL WCD9335_REG(0x02, 0x063) 18820aedafdSSrinivas Kandagatla #define WCD9335_CPE_SS_DMIC1_CTL WCD9335_REG(0x02, 0x064) 18920aedafdSSrinivas Kandagatla #define WCD9335_CPE_SS_DMIC2_CTL WCD9335_REG(0x02, 0x065) 19020aedafdSSrinivas Kandagatla #define WCD9335_CPE_SS_DMIC_CFG WCD9335_REG(0x02, 0x066) 19120aedafdSSrinivas Kandagatla #define WCD9335_SOC_MAD_AUDIO_CTL_2 WCD9335_REG(0x02, 0x084) 19220aedafdSSrinivas Kandagatla 19320aedafdSSrinivas Kandagatla /* Page-6 Registers */ 19420aedafdSSrinivas Kandagatla #define WCD9335_PAGE6_PAGE_REGISTER WCD9335_REG(0x06, 0x000) 19520aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS WCD9335_REG(0x06, 0x001) 19620aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_EN_MASK BIT(7) 19720aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_ENABLE BIT(7) 19820aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_DISABLE 0 19920aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_EN_MASK BIT(6) 20020aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_ENABLE BIT(6) 20120aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_DISABLE 0 20220aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE BIT(5) 20320aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_AUTO BIT(5) 20420aedafdSSrinivas Kandagatla #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL 0 20520aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_TOP WCD9335_REG(0x06, 0x002) 20620aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_EN_MASK BIT(2) 20720aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_ENABLE BIT(2) 20820aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_DISABLE 0 20920aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_SRC_MASK BIT(3) 21020aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_SRC_RCO BIT(3) 21120aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL 0 21220aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK BIT(7) 21320aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE BIT(7) 21420aedafdSSrinivas Kandagatla #define WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE 0 21520aedafdSSrinivas Kandagatla #define WCD9335_ANA_RCO WCD9335_REG(0x06, 0x003) 21620aedafdSSrinivas Kandagatla #define WCD9335_ANA_RCO_BG_EN_MASK BIT(7) 21720aedafdSSrinivas Kandagatla #define WCD9335_ANA_RCO_BG_ENABLE BIT(7) 21820aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_VOUT_D WCD9335_REG(0x06, 0x005) 21920aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_VOUT_MASK GENMASK(7, 0) 22020aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL WCD9335_REG(0x06, 0x006) 22120aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK BIT(1) 22220aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT BIT(1) 22320aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_INT 0 22420aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK BIT(2) 22520aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT BIT(2) 22620aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_INT 0 22720aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_RAMP_START_MASK BIT(7) 22820aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE BIT(7) 22920aedafdSSrinivas Kandagatla #define WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE 0 23020aedafdSSrinivas Kandagatla #define WCD9335_ANA_RX_SUPPLIES WCD9335_REG(0x06, 0x008) 23120aedafdSSrinivas Kandagatla #define WCD9335_ANA_RX_BIAS_ENABLE_MASK BIT(0) 23220aedafdSSrinivas Kandagatla #define WCD9335_ANA_RX_BIAS_ENABLE BIT(0) 23320aedafdSSrinivas Kandagatla #define WCD9335_ANA_RX_BIAS_DISABLE 0 23420aedafdSSrinivas Kandagatla #define WCD9335_ANA_HPH WCD9335_REG(0x06, 0x009) 23520aedafdSSrinivas Kandagatla #define WCD9335_ANA_EAR WCD9335_REG(0x06, 0x00a) 23620aedafdSSrinivas Kandagatla #define WCD9335_ANA_LO_1_2 WCD9335_REG(0x06, 0x00b) 23720aedafdSSrinivas Kandagatla #define WCD9335_ANA_LO_3_4 WCD9335_REG(0x06, 0x00c) 23820aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC1 WCD9335_REG(0x06, 0x00e) 23920aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC2 WCD9335_REG(0x06, 0x00f) 24020aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC3 WCD9335_REG(0x06, 0x010) 24120aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC4 WCD9335_REG(0x06, 0x011) 24220aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC5 WCD9335_REG(0x06, 0x012) 24320aedafdSSrinivas Kandagatla #define WCD9335_ANA_AMIC6 WCD9335_REG(0x06, 0x013) 24420aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_MECH WCD9335_REG(0x06, 0x014) 24520aedafdSSrinivas Kandagatla #define WCD9335_MBHC_L_DET_EN_MASK BIT(7) 24620aedafdSSrinivas Kandagatla #define WCD9335_MBHC_L_DET_EN BIT(7) 24720aedafdSSrinivas Kandagatla #define WCD9335_MBHC_GND_DET_EN_MASK BIT(6) 24820aedafdSSrinivas Kandagatla #define WCD9335_MBHC_MECH_DETECT_TYPE_MASK BIT(5) 24920aedafdSSrinivas Kandagatla #define WCD9335_MBHC_MECH_DETECT_TYPE_SHIFT 5 25020aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) 25120aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HPHL_PLUG_TYPE_NO BIT(4) 25220aedafdSSrinivas Kandagatla #define WCD9335_MBHC_GND_PLUG_TYPE_MASK BIT(3) 25320aedafdSSrinivas Kandagatla #define WCD9335_MBHC_GND_PLUG_TYPE_NO BIT(3) 25420aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HSL_PULLUP_COMP_EN BIT(2) 25520aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HPHL_100K_TO_GND_EN BIT(0) 25620aedafdSSrinivas Kandagatla 25720aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_ELECT WCD9335_REG(0x06, 0x015) 25820aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4) 25920aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4) 26020aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BD_ISRC_OFF 0 26120aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BIAS_EN_MASK BIT(0) 26220aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BIAS_EN BIT(0) 26320aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_ZDET WCD9335_REG(0x06, 0x016) 26420aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_RESULT_1 WCD9335_REG(0x06, 0x017) 26520aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_RESULT_2 WCD9335_REG(0x06, 0x018) 26620aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_RESULT_3 WCD9335_REG(0x06, 0x019) 26720aedafdSSrinivas Kandagatla #define WCD9335_MBHC_BTN_RESULT_MASK GENMASK(2, 0) 26820aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN0 WCD9335_REG(0x06, 0x01a) 26920aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN1 WCD9335_REG(0x06, 0x01b) 27020aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN2 WCD9335_REG(0x06, 0x01c) 27120aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN3 WCD9335_REG(0x06, 0x01d) 27220aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN4 WCD9335_REG(0x06, 0x01e) 27320aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN5 WCD9335_REG(0x06, 0x01f) 27420aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN6 WCD9335_REG(0x06, 0x020) 27520aedafdSSrinivas Kandagatla #define WCD9335_ANA_MBHC_BTN7 WCD9335_REG(0x06, 0x021) 27620aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB1 WCD9335_REG(0x06, 0x022) 27720aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB2 WCD9335_REG(0x06, 0x023) 27820aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB2_ENABLE BIT(6) 27920aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB2_RAMP WCD9335_REG(0x06, 0x024) 28020aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB3 WCD9335_REG(0x06, 0x025) 28120aedafdSSrinivas Kandagatla #define WCD9335_ANA_MICB4 WCD9335_REG(0x06, 0x026) 28220aedafdSSrinivas Kandagatla #define WCD9335_ANA_VBADC WCD9335_REG(0x06, 0x027) 28320aedafdSSrinivas Kandagatla #define WCD9335_BIAS_VBG_FINE_ADJ WCD9335_REG(0x06, 0x029) 28420aedafdSSrinivas Kandagatla #define WCD9335_RCO_CTRL_2 WCD9335_REG(0x06, 0x02f) 28520aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_2 WCD9335_REG(0x06, 0x042) 28620aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_4 WCD9335_REG(0x06, 0x044) 28720aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_8 WCD9335_REG(0x06, 0x048) 28820aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_10 WCD9335_REG(0x06, 0x04a) 28920aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF 0x2 29020aedafdSSrinivas Kandagatla /* Comparator 1 and 2 Bias current at 1P0UA with start pulse width of C320FF */ 29120aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_CCL_DEF_VALUE 0x6e 29220aedafdSSrinivas Kandagatla #define WCD9335_SIDO_SIDO_TEST_2 WCD9335_REG(0x06, 0x055) 29320aedafdSSrinivas Kandagatla #define WCD9335_MBHC_CTL_1 WCD9335_REG(0x06, 0x056) 29420aedafdSSrinivas Kandagatla #define WCD9335_MBHC_BTN_DBNC_MASK GENMASK(1, 0) 29520aedafdSSrinivas Kandagatla #define WCD9335_MBHC_BTN_DBNC_T_16_MS 0x2 29620aedafdSSrinivas Kandagatla #define WCD9335_MBHC_CTL_RCO_EN_MASK BIT(7) 29720aedafdSSrinivas Kandagatla #define WCD9335_MBHC_CTL_RCO_EN BIT(7) 29820aedafdSSrinivas Kandagatla 29920aedafdSSrinivas Kandagatla #define WCD9335_MBHC_CTL_2 WCD9335_REG(0x06, 0x057) 30020aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0) 30120aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HS_VREF_1P5_V 0x1 30220aedafdSSrinivas Kandagatla #define WCD9335_MBHC_PLUG_DETECT_CTL WCD9335_REG(0x06, 0x058) 30320aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK GENMASK(7, 6) 30420aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HSDET_PULLUP_CTL_SHIFT 6 30520aedafdSSrinivas Kandagatla #define WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA 0x80 30620aedafdSSrinivas Kandagatla #define WCD9335_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6 30720aedafdSSrinivas Kandagatla 30820aedafdSSrinivas Kandagatla #define WCD9335_MBHC_ZDET_RAMP_CTL WCD9335_REG(0x06, 0x05a) 30920aedafdSSrinivas Kandagatla #define WCD9335_VBADC_IBIAS_FE WCD9335_REG(0x06, 0x05e) 31020aedafdSSrinivas Kandagatla #define WCD9335_FLYBACK_CTRL_1 WCD9335_REG(0x06, 0x0b1) 31120aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_HPH_PA WCD9335_REG(0x06, 0x0bb) 31220aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK GENMASK(3, 0) 31320aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2 WCD9335_REG(0x06, 0x0bc) 31420aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_HPH_RDAC_LDO WCD9335_REG(0x06, 0x0bd) 31520aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_FLYB_BUFF WCD9335_REG(0x06, 0x0c7) 31620aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0) 31720aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_FLYB_I_0P0_UA 0 31820aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4) 31920aedafdSSrinivas Kandagatla #define WCD9335_RX_BIAS_FLYB_MID_RST WCD9335_REG(0x06, 0x0c8) 32020aedafdSSrinivas Kandagatla #define WCD9335_HPH_CNP_WG_CTL WCD9335_REG(0x06, 0x0cc) 32120aedafdSSrinivas Kandagatla #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK GENMASK(2, 0) 32220aedafdSSrinivas Kandagatla #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500 0x2 32320aedafdSSrinivas Kandagatla #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000 0x3 32420aedafdSSrinivas Kandagatla #define WCD9335_HPH_OCP_CTL WCD9335_REG(0x06, 0x0ce) 32520aedafdSSrinivas Kandagatla #define WCD9335_HPH_AUTO_CHOP WCD9335_REG(0x06, 0x0cf) 32620aedafdSSrinivas Kandagatla #define WCD9335_HPH_AUTO_CHOP_MASK BIT(5) 32720aedafdSSrinivas Kandagatla #define WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE BIT(5) 32820aedafdSSrinivas Kandagatla #define WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN 0 32920aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL1 WCD9335_REG(0x06, 0x0d1) 33020aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_GM3_IB_SCALE_MASK GENMASK(3, 1) 33120aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2 WCD9335_REG(0x06, 0x0d2) 33220aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK BIT(2) 33320aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE BIT(2) 33420aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE 0 33520aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK BIT(3) 33620aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE BIT(3) 33720aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE 0 33820aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK BIT(5) 33920aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE BIT(5) 34020aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE 0 34120aedafdSSrinivas Kandagatla #define WCD9335_HPH_L_EN WCD9335_REG(0x06, 0x0d3) 34220aedafdSSrinivas Kandagatla #define WCD9335_HPH_CONST_SEL_L_MASK GENMASK(7, 6) 34320aedafdSSrinivas Kandagatla #define WCD9335_HPH_CONST_SEL_L_BYPASS 0 34420aedafdSSrinivas Kandagatla #define WCD9335_HPH_CONST_SEL_L_LP_PATH 0x40 34520aedafdSSrinivas Kandagatla #define WCD9335_HPH_CONST_SEL_L_HQ_PATH 0x80 34620aedafdSSrinivas Kandagatla #define WCD9335_HPH_PA_GAIN_MASK GENMASK(4, 0) 34720aedafdSSrinivas Kandagatla #define WCD9335_HPH_GAIN_SRC_SEL_MASK BIT(5) 34820aedafdSSrinivas Kandagatla #define WCD9335_HPH_GAIN_SRC_SEL_COMPANDER 0 34920aedafdSSrinivas Kandagatla #define WCD9335_HPH_GAIN_SRC_SEL_REGISTER BIT(5) 35020aedafdSSrinivas Kandagatla #define WCD9335_HPH_L_TEST WCD9335_REG(0x06, 0x0d4) 35120aedafdSSrinivas Kandagatla #define WCD9335_HPH_R_EN WCD9335_REG(0x06, 0x0d6) 35220aedafdSSrinivas Kandagatla #define WCD9335_HPH_R_TEST WCD9335_REG(0x06, 0x0d7) 35320aedafdSSrinivas Kandagatla #define WCD9335_HPH_R_ATEST WCD9335_REG(0x06, 0x0d8) 35420aedafdSSrinivas Kandagatla #define WCD9335_HPH_RDAC_LDO_CTL WCD9335_REG(0x06, 0x0db) 35520aedafdSSrinivas Kandagatla #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK GENMASK(2, 0) 35620aedafdSSrinivas Kandagatla #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60 0x1 35720aedafdSSrinivas Kandagatla #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK GENMASK(6, 4) 35820aedafdSSrinivas Kandagatla #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60 0x10 35920aedafdSSrinivas Kandagatla #define WCD9335_HPH_REFBUFF_LP_CTL WCD9335_REG(0x06, 0x0de) 36020aedafdSSrinivas Kandagatla #define WCD9335_HPH_L_DAC_CTL WCD9335_REG(0x06, 0x0df) 36120aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_POWERMODE_MASK BIT(0) 36220aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_POWERMODE_LOWPOWER 0 36320aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_POWERMODE_UHQA BIT(0) 36420aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_UHQA_OV_MASK BIT(1) 36520aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_UHQA_OV_ENABLE BIT(1) 36620aedafdSSrinivas Kandagatla #define WCD9335_HPH_DAC_LDO_UHQA_OV_DISABLE 0 36720aedafdSSrinivas Kandagatla 36820aedafdSSrinivas Kandagatla #define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2) 36920aedafdSSrinivas Kandagatla #define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea) 37020aedafdSSrinivas Kandagatla #define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb) 37120aedafdSSrinivas Kandagatla #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1) 37220aedafdSSrinivas Kandagatla #define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2) 37320aedafdSSrinivas Kandagatla #define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8) 37420aedafdSSrinivas Kandagatla #define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9) 37520aedafdSSrinivas Kandagatla #define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa) 37620aedafdSSrinivas Kandagatla 37720aedafdSSrinivas Kandagatla /* Page-10 Registers */ 37820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX0_TX_PATH_CTL WCD9335_REG(0x0a, 0x031) 37920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0) 38020aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_PATH_CTL(dec) WCD9335_REG(0xa, (0x31 + dec * 0x10)) 38120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX0_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x032) 38220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK BIT(7) 38320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_ADC_DMIC_SEL BIT(7) 38420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_ADC_AMIC_SEL 0 38520aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX0_TX_VOL_CTL WCD9335_REG(0x0a, 0x034) 38620aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX0_TX_PATH_SEC2 WCD9335_REG(0x0a, 0x039) 38720aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX0_TX_PATH_SEC7 WCD9335_REG(0x0a, 0x03e) 38820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX1_TX_PATH_CTL WCD9335_REG(0x0a, 0x041) 38920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX1_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x042) 39020aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX2_TX_PATH_CTL WCD9335_REG(0x0a, 0x051) 39120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX2_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x052) 39220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX2_TX_VOL_CTL WCD9335_REG(0x0a, 0x054) 39320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX3_TX_PATH_CTL WCD9335_REG(0x0a, 0x061) 39420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX3_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x062) 39520aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX3_TX_VOL_CTL WCD9335_REG(0x0a, 0x064) 39620aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX4_TX_PATH_CTL WCD9335_REG(0x0a, 0x071) 39720aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX4_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x072) 39820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX4_TX_VOL_CTL WCD9335_REG(0x0a, 0x074) 39920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX5_TX_PATH_CTL WCD9335_REG(0x0a, 0x081) 40020aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX5_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x082) 40120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX5_TX_VOL_CTL WCD9335_REG(0x0a, 0x084) 40220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX6_TX_PATH_CTL WCD9335_REG(0x0a, 0x091) 40320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX6_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x092) 40420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX6_TX_VOL_CTL WCD9335_REG(0x0a, 0x094) 40520aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX7_TX_PATH_CTL WCD9335_REG(0x0a, 0x0a1) 40620aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX7_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0a2) 40720aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX7_TX_VOL_CTL WCD9335_REG(0x0a, 0x0a4) 40820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX8_TX_PATH_CTL WCD9335_REG(0x0a, 0x0b1) 40920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX8_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0b2) 41020aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX8_TX_VOL_CTL WCD9335_REG(0x0a, 0x0b4) 41120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c3) 41220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c7) 41320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cb) 41420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cf) 41520aedafdSSrinivas Kandagatla 41620aedafdSSrinivas Kandagatla /* Page-11 Registers */ 41720aedafdSSrinivas Kandagatla #define WCD9335_PAGE11_PAGE_REGISTER WCD9335_REG(0x0b, 0x000) 41820aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER1_CTL0 WCD9335_REG(0x0b, 0x001) 41920aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER1_CTL(c) WCD9335_REG(0x0b, (0x001 + c * 0x8)) 42020aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_CLK_EN_MASK BIT(0) 42120aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_CLK_ENABLE BIT(0) 42220aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_CLK_DISABLE 0 42320aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_SOFT_RST_MASK BIT(1) 42420aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE BIT(1) 42520aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE 0 42620aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_HALT_MASK BIT(2) 42720aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_HALT BIT(2) 42820aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER_NOHALT 0 42920aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER7_CTL3 WCD9335_REG(0x0b, 0x034) 43020aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER7_CTL7 WCD9335_REG(0x0b, 0x038) 43120aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER8_CTL3 WCD9335_REG(0x0b, 0x03c) 43220aedafdSSrinivas Kandagatla #define WCD9335_CDC_COMPANDER8_CTL7 WCD9335_REG(0x0b, 0x040) 43320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_CTL WCD9335_REG(0x0b, 0x041) 43420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PGA_MUTE_EN_MASK BIT(4) 43520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PGA_MUTE_ENABLE BIT(4) 43620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PGA_MUTE_DISABLE 0 43720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_CLK_EN_MASK BIT(5) 43820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_CLK_ENABLE BIT(5) 43920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_CLK_DISABLE 0 44020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_RESET_MASK BIT(6) 44120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_RESET_ENABLE BIT(6) 44220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_RESET_DISABLE 0 44320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CTL(rx) WCD9335_REG(0x0b, (0x041 + rx * 0x14)) 44420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x042) 44520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x043) 44620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x044) 44720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_VOL_CTL WCD9335_REG(0x0b, 0x045) 44820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x046) 44920aedafdSSrinivas Kandagatla #define WCD9335_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0) 45020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_MIX_CTL(rx) WCD9335_REG(0x0b, (0x46 + rx * 0x14)) 45120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x047) 45220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x048) 45320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x049) 45420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_SEC7 WCD9335_REG(0x0b, 0x050) 45520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 WCD9335_REG(0x0b, 0x051) 45620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_CTL WCD9335_REG(0x0b, 0x055) 45720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x056) 45820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_CFG(c) WCD9335_REG(0x0b, (0x056 + c * 0x14)) 45920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK BIT(1) 46020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE BIT(1) 46120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE 0 46220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) 46320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) 46420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE 0 46520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK BIT(3) 46620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN BIT(3) 46720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_DISABLE 0 46820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x058) 46920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_VOL_CTL WCD9335_REG(0x0b, 0x059) 47020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x05a) 47120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x05b) 47220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x05c) 47320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x05d) 47420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX1_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x060) 47520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK GENMASK(1, 0) 47620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2 0x1 47720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1 0 47820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2) 47920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500 0x10 48020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0 48120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_CTL WCD9335_REG(0x0b, 0x069) 48220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x06a) 48320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x06c) 48420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_VOL_CTL WCD9335_REG(0x0b, 0x06d) 48520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x06e) 48620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x06f) 48720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x070) 48820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x071) 48920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK GENMASK(1, 0) 49020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX2_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x074) 49120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_PATH_CTL WCD9335_REG(0x0b, 0x07d) 49220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x07e) 49320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x080) 49420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_VOL_CTL WCD9335_REG(0x0b, 0x081) 49520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082) 49620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083) 49720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084) 49820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091) 49920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092) 50020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094) 50120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_VOL_CTL WCD9335_REG(0x0b, 0x095) 50220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096) 50320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097) 50420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098) 50520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5) 50620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6) 50720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8) 50820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_VOL_CTL WCD9335_REG(0x0b, 0x0a9) 50920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa) 51020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab) 51120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac) 51220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9) 51320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba) 51420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc) 51520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_VOL_CTL WCD9335_REG(0x0b, 0x0bd) 51620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be) 51720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf) 51820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0) 51920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd) 52020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce) 52120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf) 52220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0d0) 52320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_VOL_CTL WCD9335_REG(0x0b, 0x0d1) 52420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0d2) 52520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0d3) 52620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX7_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0d4) 52720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_CTL WCD9335_REG(0x0b, 0x0e1) 52820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0e2) 52920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0e3) 53020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0e4) 53120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_VOL_CTL WCD9335_REG(0x0b, 0x0e5) 53220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0e6) 53320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0e7) 53420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX8_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0e8) 53520aedafdSSrinivas Kandagatla 53620aedafdSSrinivas Kandagatla /* Page-12 Registers */ 53720aedafdSSrinivas Kandagatla #define WCD9335_PAGE12_PAGE_REGISTER WCD9335_REG(0x0c, 0x000) 53820aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLSH_K2_MSB WCD9335_REG(0x0c, 0x00a) 53920aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLSH_K2_LSB WCD9335_REG(0x0c, 0x00b) 54020aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST0_BOOST_CTL WCD9335_REG(0x0c, 0x01a) 54120aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST0_BOOST_CFG1 WCD9335_REG(0x0c, 0x01b) 54220aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST0_BOOST_CFG2 WCD9335_REG(0x0c, 0x01c) 54320aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST1_BOOST_CTL WCD9335_REG(0x0c, 0x022) 54420aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST1_BOOST_CFG1 WCD9335_REG(0x0c, 0x023) 54520aedafdSSrinivas Kandagatla #define WCD9335_CDC_BOOST1_BOOST_CFG2 WCD9335_REG(0x0c, 0x024) 54620aedafdSSrinivas Kandagatla 54720aedafdSSrinivas Kandagatla /* Page-13 Registers */ 54820aedafdSSrinivas Kandagatla #define WCD9335_PAGE13_PAGE_REGISTER WCD9335_REG(0x0d, 0x000) 54920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0 WCD9335_REG(0x0d, 0x001) 55020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(i) WCD9335_REG(0xd, (0x1 + i * 0x2)) 55120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1 WCD9335_REG(0xd, 0x002) 55220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0) 55320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(i) WCD9335_REG(0xd, (0x2 + i * 0x2)) 55420aedafdSSrinivas Kandagatla 55520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 WCD9335_REG(0x0d, 0x003) 55620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1 WCD9335_REG(0x0d, 0x004) 55720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0 WCD9335_REG(0x0d, 0x005) 55820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1 WCD9335_REG(0x0d, 0x006) 55920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0 WCD9335_REG(0x0d, 0x007) 56020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1 WCD9335_REG(0x0d, 0x008) 56120aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0 WCD9335_REG(0x0d, 0x009) 56220aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1 WCD9335_REG(0x0d, 0x00a) 56320aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0 WCD9335_REG(0x0d, 0x00b) 56420aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1 WCD9335_REG(0x0d, 0x00c) 56520aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0 WCD9335_REG(0x0d, 0x00d) 56620aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1 WCD9335_REG(0x0d, 0x00e) 56720aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0 WCD9335_REG(0x0d, 0x00f) 56820aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1 WCD9335_REG(0x0d, 0x010) 56920aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0 WCD9335_REG(0x0d, 0x011) 57020aedafdSSrinivas Kandagatla #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1 WCD9335_REG(0x0d, 0x012) 57120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 WCD9335_REG(0x0d, 0x01d) 57220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 WCD9335_REG(0x0d, 0x01e) 57320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0 WCD9335_REG(0x0d, 0x01f) 57420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1 WCD9335_REG(0x0d, 0x020) 57520aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0 WCD9335_REG(0x0d, 0x021) 57620aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1 WCD9335_REG(0x0d, 0x022) 57720aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0 WCD9335_REG(0x0d, 0x023) 57820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1 WCD9335_REG(0x0d, 0x024) 57920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 WCD9335_REG(0x0d, 0x025) 58020aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_SEL_AMIC 0x1 58120aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_SEL_DMIC 0 58220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0 WCD9335_REG(0x0d, 0x026) 58320aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0 WCD9335_REG(0x0d, 0x027) 58420aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0 WCD9335_REG(0x0d, 0x028) 58520aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0 WCD9335_REG(0x0d, 0x029) 58620aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0 WCD9335_REG(0x0d, 0x02b) 58720aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0 WCD9335_REG(0x0d, 0x02c) 58820aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0 WCD9335_REG(0x0d, 0x02d) 58920aedafdSSrinivas Kandagatla #define WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0 WCD9335_REG(0x0d, 0x02e) 59020aedafdSSrinivas Kandagatla #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0 WCD9335_REG(0x0d, 0x03a) 59120aedafdSSrinivas Kandagatla #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1 WCD9335_REG(0x0d, 0x03b) 59220aedafdSSrinivas Kandagatla #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2 WCD9335_REG(0x0d, 0x03c) 59320aedafdSSrinivas Kandagatla #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3 WCD9335_REG(0x0d, 0x03d) 59420aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0x0d, 0x041) 59520aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) 59620aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE BIT(0) 59720aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_MCLK_DISABLE 0 59820aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL WCD9335_REG(0x0d, 0x042) 59920aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK BIT(0) 60020aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE BIT(0) 60120aedafdSSrinivas Kandagatla #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_DISABLE 0 60220aedafdSSrinivas Kandagatla #define WCD9335_CDC_TOP_TOP_CFG1 WCD9335_REG(0x0d, 0x082) 603d902e785SSrinivas Kandagatla #define WCD9335_MAX_REGISTER 0xffff 604d902e785SSrinivas Kandagatla #define WCD9335_SEL_REGISTER 0x800 60520aedafdSSrinivas Kandagatla 60620aedafdSSrinivas Kandagatla /* SLIMBUS Slave Registers */ 60720aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_EN0 WCD9335_REG(0, 0x30) 60820aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0 WCD9335_REG(0, 0x34) 60920aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_1 WCD9335_REG(0, 0x35) 61020aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_0 WCD9335_REG(0, 0x36) 61120aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1 WCD9335_REG(0, 0x37) 61220aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 WCD9335_REG(0, 0x38) 61320aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_1 WCD9335_REG(0, 0x39) 61420aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_0 WCD9335_REG(0, 0x3A) 61520aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_1 WCD9335_REG(0, 0x3B) 61620aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 WCD9335_REG(0, 0x60) 61720aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_TX_SOURCE0 WCD9335_REG(0, 0x70) 61820aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_RX_PORT_CFG(p) WCD9335_REG(0, (0x30 + p)) 61920aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_CFG(p) WCD9335_REG(0, (0x40 + p)) 62020aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_TX_PORT_CFG(p) WCD9335_REG(0, (0x50 + p)) 62120aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_SRC(p) WCD9335_REG(0, (0x60 + p)) 62220aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_PORT_INT_STATUS(p) WCD9335_REG(0, (0x80 + p)) 62320aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x100 + 4 * p)) 62420aedafdSSrinivas Kandagatla /* ports range from 10-16 */ 62520aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) WCD9335_REG(0, (0x101 + 4 * p)) 62620aedafdSSrinivas Kandagatla #define WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x140 + 4 * p)) 62720aedafdSSrinivas Kandagatla 62820aedafdSSrinivas Kandagatla #define WCD9335_IRQ_SLIMBUS 0 62920aedafdSSrinivas Kandagatla #define WCD9335_IRQ_MBHC_SW_DET 8 63020aedafdSSrinivas Kandagatla #define WCD9335_IRQ_MBHC_ELECT_INS_REM_DET 9 63120aedafdSSrinivas Kandagatla #define WCD9335_IRQ_MBHC_BUTTON_PRESS_DET 10 63220aedafdSSrinivas Kandagatla #define WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET 11 63320aedafdSSrinivas Kandagatla #define WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12 63420aedafdSSrinivas Kandagatla 63520aedafdSSrinivas Kandagatla #define SLIM_MANF_ID_QCOM 0x217 63620aedafdSSrinivas Kandagatla #define SLIM_PROD_CODE_WCD9335 0x1a0 63720aedafdSSrinivas Kandagatla 63820aedafdSSrinivas Kandagatla #define WCD9335_VERSION_2_0 2 63920aedafdSSrinivas Kandagatla #define WCD9335_MAX_SUPPLY 5 64020aedafdSSrinivas Kandagatla 64120aedafdSSrinivas Kandagatla #endif /* __WCD9335_H__ */ 642