1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 28 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 29 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 30 /* Fractional Rates */ 31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD9335_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD9335_SLIM_NUM_PORT_REG 3 50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 51 52 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 53 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 54 55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 59 60 #define WCD9335_NUM_INTERPOLATORS 9 61 #define WCD9335_RX_START 16 62 #define WCD9335_SLIM_CH_START 128 63 #define WCD9335_MAX_MICBIAS 4 64 #define WCD9335_MAX_VALID_ADC_MUX 13 65 #define WCD9335_INVALID_ADC_MUX 9 66 67 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 68 #define CF_MIN_3DB_4HZ 0x0 69 #define CF_MIN_3DB_75HZ 0x1 70 #define CF_MIN_3DB_150HZ 0x2 71 #define WCD9335_DMIC_CLK_DIV_2 0x0 72 #define WCD9335_DMIC_CLK_DIV_3 0x1 73 #define WCD9335_DMIC_CLK_DIV_4 0x2 74 #define WCD9335_DMIC_CLK_DIV_6 0x3 75 #define WCD9335_DMIC_CLK_DIV_8 0x4 76 #define WCD9335_DMIC_CLK_DIV_16 0x5 77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 78 #define WCD9335_AMIC_PWR_LEVEL_LP 0 79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 80 #define WCD9335_AMIC_PWR_LEVEL_HP 2 81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 83 84 #define WCD9335_DEC_PWR_LVL_MASK 0x06 85 #define WCD9335_DEC_PWR_LVL_LP 0x02 86 #define WCD9335_DEC_PWR_LVL_HP 0x04 87 #define WCD9335_DEC_PWR_LVL_DF 0x00 88 89 #define WCD9335_SLIM_RX_CH(p) \ 90 {.port = p + WCD9335_RX_START, .shift = p,} 91 92 #define WCD9335_SLIM_TX_CH(p) \ 93 {.port = p, .shift = p,} 94 95 /* vout step value */ 96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 97 98 #define WCD9335_INTERPOLATOR_PATH(id) \ 99 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 100 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 107 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 108 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 115 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 116 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 127 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 128 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 129 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 130 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 131 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 132 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 134 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 135 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 136 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 137 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 138 139 #define WCD9335_ADC_MUX_PATH(id) \ 140 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 141 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 142 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 144 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 145 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 146 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 147 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 148 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 149 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 150 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 151 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 152 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 153 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 154 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 155 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 156 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 157 {"AMIC MUX" #id, "ADC6", "ADC6"} 158 159 enum { 160 WCD9335_RX0 = 0, 161 WCD9335_RX1, 162 WCD9335_RX2, 163 WCD9335_RX3, 164 WCD9335_RX4, 165 WCD9335_RX5, 166 WCD9335_RX6, 167 WCD9335_RX7, 168 WCD9335_RX8, 169 WCD9335_RX9, 170 WCD9335_RX10, 171 WCD9335_RX11, 172 WCD9335_RX12, 173 WCD9335_RX_MAX, 174 }; 175 176 enum { 177 WCD9335_TX0 = 0, 178 WCD9335_TX1, 179 WCD9335_TX2, 180 WCD9335_TX3, 181 WCD9335_TX4, 182 WCD9335_TX5, 183 WCD9335_TX6, 184 WCD9335_TX7, 185 WCD9335_TX8, 186 WCD9335_TX9, 187 WCD9335_TX10, 188 WCD9335_TX11, 189 WCD9335_TX12, 190 WCD9335_TX13, 191 WCD9335_TX14, 192 WCD9335_TX15, 193 WCD9335_TX_MAX, 194 }; 195 196 enum { 197 SIDO_SOURCE_INTERNAL = 0, 198 SIDO_SOURCE_RCO_BG, 199 }; 200 201 enum wcd9335_sido_voltage { 202 SIDO_VOLTAGE_SVS_MV = 950, 203 SIDO_VOLTAGE_NOMINAL_MV = 1100, 204 }; 205 206 enum { 207 AIF1_PB = 0, 208 AIF1_CAP, 209 AIF2_PB, 210 AIF2_CAP, 211 AIF3_PB, 212 AIF3_CAP, 213 AIF4_PB, 214 NUM_CODEC_DAIS, 215 }; 216 217 enum { 218 COMPANDER_1, /* HPH_L */ 219 COMPANDER_2, /* HPH_R */ 220 COMPANDER_3, /* LO1_DIFF */ 221 COMPANDER_4, /* LO2_DIFF */ 222 COMPANDER_5, /* LO3_SE */ 223 COMPANDER_6, /* LO4_SE */ 224 COMPANDER_7, /* SWR SPK CH1 */ 225 COMPANDER_8, /* SWR SPK CH2 */ 226 COMPANDER_MAX, 227 }; 228 229 enum { 230 INTn_2_INP_SEL_ZERO = 0, 231 INTn_2_INP_SEL_RX0, 232 INTn_2_INP_SEL_RX1, 233 INTn_2_INP_SEL_RX2, 234 INTn_2_INP_SEL_RX3, 235 INTn_2_INP_SEL_RX4, 236 INTn_2_INP_SEL_RX5, 237 INTn_2_INP_SEL_RX6, 238 INTn_2_INP_SEL_RX7, 239 INTn_2_INP_SEL_PROXIMITY, 240 }; 241 242 enum { 243 INTn_1_MIX_INP_SEL_ZERO = 0, 244 INTn_1_MIX_INP_SEL_DEC0, 245 INTn_1_MIX_INP_SEL_DEC1, 246 INTn_1_MIX_INP_SEL_IIR0, 247 INTn_1_MIX_INP_SEL_IIR1, 248 INTn_1_MIX_INP_SEL_RX0, 249 INTn_1_MIX_INP_SEL_RX1, 250 INTn_1_MIX_INP_SEL_RX2, 251 INTn_1_MIX_INP_SEL_RX3, 252 INTn_1_MIX_INP_SEL_RX4, 253 INTn_1_MIX_INP_SEL_RX5, 254 INTn_1_MIX_INP_SEL_RX6, 255 INTn_1_MIX_INP_SEL_RX7, 256 257 }; 258 259 enum { 260 INTERP_EAR = 0, 261 INTERP_HPHL, 262 INTERP_HPHR, 263 INTERP_LO1, 264 INTERP_LO2, 265 INTERP_LO3, 266 INTERP_LO4, 267 INTERP_SPKR1, 268 INTERP_SPKR2, 269 }; 270 271 enum wcd_clock_type { 272 WCD_CLK_OFF, 273 WCD_CLK_RCO, 274 WCD_CLK_MCLK, 275 }; 276 277 enum { 278 MIC_BIAS_1 = 1, 279 MIC_BIAS_2, 280 MIC_BIAS_3, 281 MIC_BIAS_4 282 }; 283 284 enum { 285 MICB_PULLUP_ENABLE, 286 MICB_PULLUP_DISABLE, 287 MICB_ENABLE, 288 MICB_DISABLE, 289 }; 290 291 struct wcd9335_slim_ch { 292 u32 ch_num; 293 u16 port; 294 u16 shift; 295 struct list_head list; 296 }; 297 298 struct wcd_slim_codec_dai_data { 299 struct list_head slim_ch_list; 300 struct slim_stream_config sconfig; 301 struct slim_stream_runtime *sruntime; 302 }; 303 304 struct wcd9335_codec { 305 struct device *dev; 306 struct clk *mclk; 307 struct clk *native_clk; 308 u32 mclk_rate; 309 u8 version; 310 311 struct slim_device *slim; 312 struct slim_device *slim_ifc_dev; 313 struct regmap *regmap; 314 struct regmap *if_regmap; 315 struct regmap_irq_chip_data *irq_data; 316 317 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 318 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 319 u32 num_rx_port; 320 u32 num_tx_port; 321 322 int sido_input_src; 323 enum wcd9335_sido_voltage sido_voltage; 324 325 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 326 struct snd_soc_component *component; 327 328 int master_bias_users; 329 int clk_mclk_users; 330 int clk_rco_users; 331 int sido_ccl_cnt; 332 enum wcd_clock_type clk_type; 333 334 struct wcd_clsh_ctrl *clsh_ctrl; 335 u32 hph_mode; 336 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 337 338 int comp_enabled[COMPANDER_MAX]; 339 340 int intr1; 341 int reset_gpio; 342 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 343 344 unsigned int rx_port_value[WCD9335_RX_MAX]; 345 unsigned int tx_port_value; 346 int hph_l_gain; 347 int hph_r_gain; 348 u32 rx_bias_count; 349 350 /*TX*/ 351 int micb_ref[WCD9335_MAX_MICBIAS]; 352 int pullup_ref[WCD9335_MAX_MICBIAS]; 353 354 int dmic_0_1_clk_cnt; 355 int dmic_2_3_clk_cnt; 356 int dmic_4_5_clk_cnt; 357 int dmic_sample_rate; 358 int mad_dmic_sample_rate; 359 360 int native_clk_users; 361 }; 362 363 struct wcd9335_irq { 364 int irq; 365 irqreturn_t (*handler)(int irq, void *data); 366 char *name; 367 }; 368 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 370 WCD9335_SLIM_TX_CH(0), 371 WCD9335_SLIM_TX_CH(1), 372 WCD9335_SLIM_TX_CH(2), 373 WCD9335_SLIM_TX_CH(3), 374 WCD9335_SLIM_TX_CH(4), 375 WCD9335_SLIM_TX_CH(5), 376 WCD9335_SLIM_TX_CH(6), 377 WCD9335_SLIM_TX_CH(7), 378 WCD9335_SLIM_TX_CH(8), 379 WCD9335_SLIM_TX_CH(9), 380 WCD9335_SLIM_TX_CH(10), 381 WCD9335_SLIM_TX_CH(11), 382 WCD9335_SLIM_TX_CH(12), 383 WCD9335_SLIM_TX_CH(13), 384 WCD9335_SLIM_TX_CH(14), 385 WCD9335_SLIM_TX_CH(15), 386 }; 387 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 389 WCD9335_SLIM_RX_CH(0), /* 16 */ 390 WCD9335_SLIM_RX_CH(1), /* 17 */ 391 WCD9335_SLIM_RX_CH(2), 392 WCD9335_SLIM_RX_CH(3), 393 WCD9335_SLIM_RX_CH(4), 394 WCD9335_SLIM_RX_CH(5), 395 WCD9335_SLIM_RX_CH(6), 396 WCD9335_SLIM_RX_CH(7), 397 WCD9335_SLIM_RX_CH(8), 398 WCD9335_SLIM_RX_CH(9), 399 WCD9335_SLIM_RX_CH(10), 400 WCD9335_SLIM_RX_CH(11), 401 WCD9335_SLIM_RX_CH(12), 402 }; 403 404 struct interp_sample_rate { 405 int rate; 406 int rate_val; 407 }; 408 409 static struct interp_sample_rate int_mix_rate_val[] = { 410 {48000, 0x4}, /* 48K */ 411 {96000, 0x5}, /* 96K */ 412 {192000, 0x6}, /* 192K */ 413 }; 414 415 static struct interp_sample_rate int_prim_rate_val[] = { 416 {8000, 0x0}, /* 8K */ 417 {16000, 0x1}, /* 16K */ 418 {24000, -EINVAL},/* 24K */ 419 {32000, 0x3}, /* 32K */ 420 {48000, 0x4}, /* 48K */ 421 {96000, 0x5}, /* 96K */ 422 {192000, 0x6}, /* 192K */ 423 {384000, 0x7}, /* 384K */ 424 {44100, 0x8}, /* 44.1K */ 425 }; 426 427 struct wcd9335_reg_mask_val { 428 u16 reg; 429 u8 mask; 430 u8 val; 431 }; 432 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 434 /* Rbuckfly/R_EAR(32) */ 435 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 436 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 437 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 438 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 439 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 440 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 441 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 442 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 443 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 444 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 445 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 446 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 447 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 448 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 449 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 454 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 455 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 456 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 466 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 467 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 468 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 469 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 470 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 471 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 472 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 473 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 474 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 475 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 476 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 477 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 478 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 479 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 480 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 481 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 482 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 483 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 484 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 485 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 486 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 487 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 488 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 489 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 490 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 491 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 492 }; 493 494 /* Cutoff frequency for high pass filter */ 495 static const char * const cf_text[] = { 496 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 497 }; 498 499 static const char * const rx_cf_text[] = { 500 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 501 "CF_NEG_3DB_0P48HZ" 502 }; 503 504 static const char * const rx_int0_7_mix_mux_text[] = { 505 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 506 "RX6", "RX7", "PROXIMITY" 507 }; 508 509 static const char * const rx_int_mix_mux_text[] = { 510 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 511 "RX6", "RX7" 512 }; 513 514 static const char * const rx_prim_mix_text[] = { 515 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 516 "RX3", "RX4", "RX5", "RX6", "RX7" 517 }; 518 519 static const char * const rx_int_dem_inp_mux_text[] = { 520 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 521 }; 522 523 static const char * const rx_int0_interp_mux_text[] = { 524 "ZERO", "RX INT0 MIX2", 525 }; 526 527 static const char * const rx_int1_interp_mux_text[] = { 528 "ZERO", "RX INT1 MIX2", 529 }; 530 531 static const char * const rx_int2_interp_mux_text[] = { 532 "ZERO", "RX INT2 MIX2", 533 }; 534 535 static const char * const rx_int3_interp_mux_text[] = { 536 "ZERO", "RX INT3 MIX2", 537 }; 538 539 static const char * const rx_int4_interp_mux_text[] = { 540 "ZERO", "RX INT4 MIX2", 541 }; 542 543 static const char * const rx_int5_interp_mux_text[] = { 544 "ZERO", "RX INT5 MIX2", 545 }; 546 547 static const char * const rx_int6_interp_mux_text[] = { 548 "ZERO", "RX INT6 MIX2", 549 }; 550 551 static const char * const rx_int7_interp_mux_text[] = { 552 "ZERO", "RX INT7 MIX2", 553 }; 554 555 static const char * const rx_int8_interp_mux_text[] = { 556 "ZERO", "RX INT8 SEC MIX" 557 }; 558 559 static const char * const rx_hph_mode_mux_text[] = { 560 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 561 "Class-H Hi-Fi Low Power" 562 }; 563 564 static const char *const slim_rx_mux_text[] = { 565 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 566 }; 567 568 static const char * const adc_mux_text[] = { 569 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 570 }; 571 572 static const char * const dmic_mux_text[] = { 573 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 574 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 575 }; 576 577 static const char * const dmic_mux_alt_text[] = { 578 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 579 }; 580 581 static const char * const amic_mux_text[] = { 582 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 583 }; 584 585 static const char * const sb_tx0_mux_text[] = { 586 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 587 }; 588 589 static const char * const sb_tx1_mux_text[] = { 590 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 591 }; 592 593 static const char * const sb_tx2_mux_text[] = { 594 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 595 }; 596 597 static const char * const sb_tx3_mux_text[] = { 598 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 599 }; 600 601 static const char * const sb_tx4_mux_text[] = { 602 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 603 }; 604 605 static const char * const sb_tx5_mux_text[] = { 606 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 607 }; 608 609 static const char * const sb_tx6_mux_text[] = { 610 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 611 }; 612 613 static const char * const sb_tx7_mux_text[] = { 614 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 615 }; 616 617 static const char * const sb_tx8_mux_text[] = { 618 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 619 }; 620 621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 625 626 static const struct soc_enum cf_dec0_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec1_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec2_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec3_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec4_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec5_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_dec6_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 646 647 static const struct soc_enum cf_dec7_enum = 648 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 649 650 static const struct soc_enum cf_dec8_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 652 653 static const struct soc_enum cf_int0_1_enum = 654 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 655 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 657 rx_cf_text); 658 659 static const struct soc_enum cf_int1_1_enum = 660 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 661 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 663 rx_cf_text); 664 665 static const struct soc_enum cf_int2_1_enum = 666 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 667 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 669 rx_cf_text); 670 671 static const struct soc_enum cf_int3_1_enum = 672 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 673 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 675 rx_cf_text); 676 677 static const struct soc_enum cf_int4_1_enum = 678 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 679 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 681 rx_cf_text); 682 683 static const struct soc_enum cf_int5_1_enum = 684 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 685 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 687 rx_cf_text); 688 689 static const struct soc_enum cf_int6_1_enum = 690 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 691 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 693 rx_cf_text); 694 695 static const struct soc_enum cf_int7_1_enum = 696 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 697 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 699 rx_cf_text); 700 701 static const struct soc_enum cf_int8_1_enum = 702 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 703 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 705 rx_cf_text); 706 707 static const struct soc_enum rx_hph_mode_mux_enum = 708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 709 rx_hph_mode_mux_text); 710 711 static const struct soc_enum slim_rx_mux_enum = 712 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 713 714 static const struct soc_enum rx_int0_2_mux_chain_enum = 715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 716 rx_int0_7_mix_mux_text); 717 718 static const struct soc_enum rx_int1_2_mux_chain_enum = 719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 720 rx_int_mix_mux_text); 721 722 static const struct soc_enum rx_int2_2_mux_chain_enum = 723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 724 rx_int_mix_mux_text); 725 726 static const struct soc_enum rx_int3_2_mux_chain_enum = 727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 728 rx_int_mix_mux_text); 729 730 static const struct soc_enum rx_int4_2_mux_chain_enum = 731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 732 rx_int_mix_mux_text); 733 734 static const struct soc_enum rx_int5_2_mux_chain_enum = 735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 736 rx_int_mix_mux_text); 737 738 static const struct soc_enum rx_int6_2_mux_chain_enum = 739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 740 rx_int_mix_mux_text); 741 742 static const struct soc_enum rx_int7_2_mux_chain_enum = 743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 744 rx_int0_7_mix_mux_text); 745 746 static const struct soc_enum rx_int8_2_mux_chain_enum = 747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 748 rx_int_mix_mux_text); 749 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 752 rx_prim_mix_text); 753 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 756 rx_prim_mix_text); 757 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 760 rx_prim_mix_text); 761 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 764 rx_prim_mix_text); 765 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 768 rx_prim_mix_text); 769 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 772 rx_prim_mix_text); 773 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 776 rx_prim_mix_text); 777 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 780 rx_prim_mix_text); 781 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 784 rx_prim_mix_text); 785 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 788 rx_prim_mix_text); 789 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 792 rx_prim_mix_text); 793 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 796 rx_prim_mix_text); 797 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 800 rx_prim_mix_text); 801 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 804 rx_prim_mix_text); 805 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 808 rx_prim_mix_text); 809 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 812 rx_prim_mix_text); 813 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 816 rx_prim_mix_text); 817 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 820 rx_prim_mix_text); 821 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 824 rx_prim_mix_text); 825 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 828 rx_prim_mix_text); 829 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 832 rx_prim_mix_text); 833 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 836 rx_prim_mix_text); 837 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 840 rx_prim_mix_text); 841 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 844 rx_prim_mix_text); 845 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 848 rx_prim_mix_text); 849 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 851 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 852 rx_prim_mix_text); 853 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 856 rx_prim_mix_text); 857 858 static const struct soc_enum rx_int0_dem_inp_mux_enum = 859 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 860 ARRAY_SIZE(rx_int_dem_inp_mux_text), 861 rx_int_dem_inp_mux_text); 862 863 static const struct soc_enum rx_int1_dem_inp_mux_enum = 864 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 865 ARRAY_SIZE(rx_int_dem_inp_mux_text), 866 rx_int_dem_inp_mux_text); 867 868 static const struct soc_enum rx_int2_dem_inp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 870 ARRAY_SIZE(rx_int_dem_inp_mux_text), 871 rx_int_dem_inp_mux_text); 872 873 static const struct soc_enum rx_int0_interp_mux_enum = 874 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 875 rx_int0_interp_mux_text); 876 877 static const struct soc_enum rx_int1_interp_mux_enum = 878 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 879 rx_int1_interp_mux_text); 880 881 static const struct soc_enum rx_int2_interp_mux_enum = 882 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 883 rx_int2_interp_mux_text); 884 885 static const struct soc_enum rx_int3_interp_mux_enum = 886 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 887 rx_int3_interp_mux_text); 888 889 static const struct soc_enum rx_int4_interp_mux_enum = 890 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 891 rx_int4_interp_mux_text); 892 893 static const struct soc_enum rx_int5_interp_mux_enum = 894 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 895 rx_int5_interp_mux_text); 896 897 static const struct soc_enum rx_int6_interp_mux_enum = 898 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 899 rx_int6_interp_mux_text); 900 901 static const struct soc_enum rx_int7_interp_mux_enum = 902 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 903 rx_int7_interp_mux_text); 904 905 static const struct soc_enum rx_int8_interp_mux_enum = 906 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 907 rx_int8_interp_mux_text); 908 909 static const struct soc_enum tx_adc_mux0_chain_enum = 910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 911 adc_mux_text); 912 913 static const struct soc_enum tx_adc_mux1_chain_enum = 914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 915 adc_mux_text); 916 917 static const struct soc_enum tx_adc_mux2_chain_enum = 918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 919 adc_mux_text); 920 921 static const struct soc_enum tx_adc_mux3_chain_enum = 922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 923 adc_mux_text); 924 925 static const struct soc_enum tx_adc_mux4_chain_enum = 926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 927 adc_mux_text); 928 929 static const struct soc_enum tx_adc_mux5_chain_enum = 930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 931 adc_mux_text); 932 933 static const struct soc_enum tx_adc_mux6_chain_enum = 934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 935 adc_mux_text); 936 937 static const struct soc_enum tx_adc_mux7_chain_enum = 938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 939 adc_mux_text); 940 941 static const struct soc_enum tx_adc_mux8_chain_enum = 942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 943 adc_mux_text); 944 945 static const struct soc_enum tx_dmic_mux0_enum = 946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 947 dmic_mux_text); 948 949 static const struct soc_enum tx_dmic_mux1_enum = 950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 951 dmic_mux_text); 952 953 static const struct soc_enum tx_dmic_mux2_enum = 954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 955 dmic_mux_text); 956 957 static const struct soc_enum tx_dmic_mux3_enum = 958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 959 dmic_mux_text); 960 961 static const struct soc_enum tx_dmic_mux4_enum = 962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 963 dmic_mux_alt_text); 964 965 static const struct soc_enum tx_dmic_mux5_enum = 966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 967 dmic_mux_alt_text); 968 969 static const struct soc_enum tx_dmic_mux6_enum = 970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 971 dmic_mux_alt_text); 972 973 static const struct soc_enum tx_dmic_mux7_enum = 974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 975 dmic_mux_alt_text); 976 977 static const struct soc_enum tx_dmic_mux8_enum = 978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 979 dmic_mux_alt_text); 980 981 static const struct soc_enum tx_amic_mux0_enum = 982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 983 amic_mux_text); 984 985 static const struct soc_enum tx_amic_mux1_enum = 986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 987 amic_mux_text); 988 989 static const struct soc_enum tx_amic_mux2_enum = 990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 991 amic_mux_text); 992 993 static const struct soc_enum tx_amic_mux3_enum = 994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 995 amic_mux_text); 996 997 static const struct soc_enum tx_amic_mux4_enum = 998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 999 amic_mux_text); 1000 1001 static const struct soc_enum tx_amic_mux5_enum = 1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 1003 amic_mux_text); 1004 1005 static const struct soc_enum tx_amic_mux6_enum = 1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 1007 amic_mux_text); 1008 1009 static const struct soc_enum tx_amic_mux7_enum = 1010 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1011 amic_mux_text); 1012 1013 static const struct soc_enum tx_amic_mux8_enum = 1014 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1015 amic_mux_text); 1016 1017 static const struct soc_enum sb_tx0_mux_enum = 1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1019 sb_tx0_mux_text); 1020 1021 static const struct soc_enum sb_tx1_mux_enum = 1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1023 sb_tx1_mux_text); 1024 1025 static const struct soc_enum sb_tx2_mux_enum = 1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1027 sb_tx2_mux_text); 1028 1029 static const struct soc_enum sb_tx3_mux_enum = 1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1031 sb_tx3_mux_text); 1032 1033 static const struct soc_enum sb_tx4_mux_enum = 1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1035 sb_tx4_mux_text); 1036 1037 static const struct soc_enum sb_tx5_mux_enum = 1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1039 sb_tx5_mux_text); 1040 1041 static const struct soc_enum sb_tx6_mux_enum = 1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1043 sb_tx6_mux_text); 1044 1045 static const struct soc_enum sb_tx7_mux_enum = 1046 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1047 sb_tx7_mux_text); 1048 1049 static const struct soc_enum sb_tx8_mux_enum = 1050 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1051 sb_tx8_mux_text); 1052 1053 static const struct snd_kcontrol_new rx_int0_2_mux = 1054 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int1_2_mux = 1057 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int2_2_mux = 1060 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int3_2_mux = 1063 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int4_2_mux = 1066 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int5_2_mux = 1069 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int6_2_mux = 1072 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int7_2_mux = 1075 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int8_2_mux = 1078 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1154 1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1156 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1157 1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1159 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1160 1161 static const struct snd_kcontrol_new rx_int0_interp_mux = 1162 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int1_interp_mux = 1165 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int2_interp_mux = 1168 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int3_interp_mux = 1171 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int4_interp_mux = 1174 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int5_interp_mux = 1177 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new rx_int6_interp_mux = 1180 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1181 1182 static const struct snd_kcontrol_new rx_int7_interp_mux = 1183 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1184 1185 static const struct snd_kcontrol_new rx_int8_interp_mux = 1186 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux0 = 1189 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux1 = 1192 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux2 = 1195 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux3 = 1198 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux4 = 1201 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux5 = 1204 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1205 1206 static const struct snd_kcontrol_new tx_dmic_mux6 = 1207 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1208 1209 static const struct snd_kcontrol_new tx_dmic_mux7 = 1210 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1211 1212 static const struct snd_kcontrol_new tx_dmic_mux8 = 1213 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux0 = 1216 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux1 = 1219 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux2 = 1222 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux3 = 1225 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux4 = 1228 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux5 = 1231 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1232 1233 static const struct snd_kcontrol_new tx_amic_mux6 = 1234 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1235 1236 static const struct snd_kcontrol_new tx_amic_mux7 = 1237 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1238 1239 static const struct snd_kcontrol_new tx_amic_mux8 = 1240 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx0_mux = 1243 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx1_mux = 1246 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx2_mux = 1249 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx3_mux = 1252 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx4_mux = 1255 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx5_mux = 1258 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1259 1260 static const struct snd_kcontrol_new sb_tx6_mux = 1261 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1262 1263 static const struct snd_kcontrol_new sb_tx7_mux = 1264 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1265 1266 static const struct snd_kcontrol_new sb_tx8_mux = 1267 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1268 1269 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1273 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1274 u32 port_id = w->shift; 1275 1276 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1277 1278 return 0; 1279 } 1280 1281 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1282 struct snd_ctl_elem_value *ucontrol) 1283 { 1284 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1285 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1286 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1287 struct snd_soc_dapm_update *update = NULL; 1288 u32 port_id = w->shift; 1289 1290 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1291 1292 switch (wcd->rx_port_value[port_id]) { 1293 case 0: 1294 list_del_init(&wcd->rx_chs[port_id].list); 1295 break; 1296 case 1: 1297 list_add_tail(&wcd->rx_chs[port_id].list, 1298 &wcd->dai[AIF1_PB].slim_ch_list); 1299 break; 1300 case 2: 1301 list_add_tail(&wcd->rx_chs[port_id].list, 1302 &wcd->dai[AIF2_PB].slim_ch_list); 1303 break; 1304 case 3: 1305 list_add_tail(&wcd->rx_chs[port_id].list, 1306 &wcd->dai[AIF3_PB].slim_ch_list); 1307 break; 1308 case 4: 1309 list_add_tail(&wcd->rx_chs[port_id].list, 1310 &wcd->dai[AIF4_PB].slim_ch_list); 1311 break; 1312 default: 1313 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1314 goto err; 1315 } 1316 1317 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1318 e, update); 1319 1320 return 0; 1321 err: 1322 return -EINVAL; 1323 } 1324 1325 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1326 struct snd_ctl_elem_value *ucontrol) 1327 { 1328 1329 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1330 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1331 1332 ucontrol->value.integer.value[0] = wcd->tx_port_value; 1333 1334 return 0; 1335 } 1336 1337 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1338 struct snd_ctl_elem_value *ucontrol) 1339 { 1340 1341 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1342 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1343 struct snd_soc_dapm_update *update = NULL; 1344 struct soc_mixer_control *mixer = 1345 (struct soc_mixer_control *)kc->private_value; 1346 int enable = ucontrol->value.integer.value[0]; 1347 int dai_id = widget->shift; 1348 int port_id = mixer->shift; 1349 1350 switch (dai_id) { 1351 case AIF1_CAP: 1352 case AIF2_CAP: 1353 case AIF3_CAP: 1354 /* only add to the list if value not set */ 1355 if (enable && !(wcd->tx_port_value & BIT(port_id))) { 1356 wcd->tx_port_value |= BIT(port_id); 1357 list_add_tail(&wcd->tx_chs[port_id].list, 1358 &wcd->dai[dai_id].slim_ch_list); 1359 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) { 1360 wcd->tx_port_value &= ~BIT(port_id); 1361 list_del_init(&wcd->tx_chs[port_id].list); 1362 } 1363 break; 1364 default: 1365 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1366 return -EINVAL; 1367 } 1368 1369 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1370 1371 return 0; 1372 } 1373 1374 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1375 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1376 slim_rx_mux_get, slim_rx_mux_put), 1377 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1378 slim_rx_mux_get, slim_rx_mux_put), 1379 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1380 slim_rx_mux_get, slim_rx_mux_put), 1381 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1382 slim_rx_mux_get, slim_rx_mux_put), 1383 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1384 slim_rx_mux_get, slim_rx_mux_put), 1385 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1386 slim_rx_mux_get, slim_rx_mux_put), 1387 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1388 slim_rx_mux_get, slim_rx_mux_put), 1389 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1390 slim_rx_mux_get, slim_rx_mux_put), 1391 }; 1392 1393 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1394 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1395 slim_tx_mixer_get, slim_tx_mixer_put), 1396 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1397 slim_tx_mixer_get, slim_tx_mixer_put), 1398 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1399 slim_tx_mixer_get, slim_tx_mixer_put), 1400 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1401 slim_tx_mixer_get, slim_tx_mixer_put), 1402 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1403 slim_tx_mixer_get, slim_tx_mixer_put), 1404 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1405 slim_tx_mixer_get, slim_tx_mixer_put), 1406 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1407 slim_tx_mixer_get, slim_tx_mixer_put), 1408 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1409 slim_tx_mixer_get, slim_tx_mixer_put), 1410 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1411 slim_tx_mixer_get, slim_tx_mixer_put), 1412 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1413 slim_tx_mixer_get, slim_tx_mixer_put), 1414 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1415 slim_tx_mixer_get, slim_tx_mixer_put), 1416 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1417 slim_tx_mixer_get, slim_tx_mixer_put), 1418 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1419 slim_tx_mixer_get, slim_tx_mixer_put), 1420 }; 1421 1422 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1423 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1424 slim_tx_mixer_get, slim_tx_mixer_put), 1425 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1426 slim_tx_mixer_get, slim_tx_mixer_put), 1427 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1428 slim_tx_mixer_get, slim_tx_mixer_put), 1429 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1432 slim_tx_mixer_get, slim_tx_mixer_put), 1433 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1434 slim_tx_mixer_get, slim_tx_mixer_put), 1435 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1436 slim_tx_mixer_get, slim_tx_mixer_put), 1437 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1438 slim_tx_mixer_get, slim_tx_mixer_put), 1439 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1440 slim_tx_mixer_get, slim_tx_mixer_put), 1441 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1442 slim_tx_mixer_get, slim_tx_mixer_put), 1443 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1444 slim_tx_mixer_get, slim_tx_mixer_put), 1445 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1446 slim_tx_mixer_get, slim_tx_mixer_put), 1447 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1448 slim_tx_mixer_get, slim_tx_mixer_put), 1449 }; 1450 1451 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1452 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1453 slim_tx_mixer_get, slim_tx_mixer_put), 1454 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1455 slim_tx_mixer_get, slim_tx_mixer_put), 1456 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1457 slim_tx_mixer_get, slim_tx_mixer_put), 1458 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1461 slim_tx_mixer_get, slim_tx_mixer_put), 1462 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1463 slim_tx_mixer_get, slim_tx_mixer_put), 1464 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1465 slim_tx_mixer_get, slim_tx_mixer_put), 1466 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1467 slim_tx_mixer_get, slim_tx_mixer_put), 1468 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1469 slim_tx_mixer_get, slim_tx_mixer_put), 1470 }; 1471 1472 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1473 struct snd_ctl_elem_value *ucontrol) 1474 { 1475 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1476 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1477 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1478 unsigned int val, reg, sel; 1479 1480 val = ucontrol->value.enumerated.item[0]; 1481 1482 switch (e->reg) { 1483 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1484 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1485 break; 1486 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1487 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1488 break; 1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1490 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1491 break; 1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1493 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1494 break; 1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1496 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1497 break; 1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1499 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1500 break; 1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1502 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1503 break; 1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1505 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1506 break; 1507 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1508 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1509 break; 1510 default: 1511 return -EINVAL; 1512 } 1513 1514 /* AMIC: 0, DMIC: 1 */ 1515 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1516 snd_soc_component_update_bits(component, reg, 1517 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1518 sel); 1519 1520 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1521 } 1522 1523 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1524 struct snd_ctl_elem_value *ucontrol) 1525 { 1526 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1527 struct snd_soc_component *component; 1528 int reg, val; 1529 1530 component = snd_soc_dapm_kcontrol_component(kc); 1531 val = ucontrol->value.enumerated.item[0]; 1532 1533 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1534 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1535 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1536 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1537 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1538 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1539 else 1540 return -EINVAL; 1541 1542 /* Set Look Ahead Delay */ 1543 snd_soc_component_update_bits(component, reg, 1544 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1545 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1546 /* Set DEM INP Select */ 1547 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1548 } 1549 1550 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1551 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1552 snd_soc_dapm_get_enum_double, 1553 wcd9335_int_dem_inp_mux_put); 1554 1555 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1556 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1557 snd_soc_dapm_get_enum_double, 1558 wcd9335_int_dem_inp_mux_put); 1559 1560 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1561 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1562 snd_soc_dapm_get_enum_double, 1563 wcd9335_int_dem_inp_mux_put); 1564 1565 static const struct snd_kcontrol_new tx_adc_mux0 = 1566 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1567 snd_soc_dapm_get_enum_double, 1568 wcd9335_put_dec_enum); 1569 1570 static const struct snd_kcontrol_new tx_adc_mux1 = 1571 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1572 snd_soc_dapm_get_enum_double, 1573 wcd9335_put_dec_enum); 1574 1575 static const struct snd_kcontrol_new tx_adc_mux2 = 1576 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1577 snd_soc_dapm_get_enum_double, 1578 wcd9335_put_dec_enum); 1579 1580 static const struct snd_kcontrol_new tx_adc_mux3 = 1581 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1582 snd_soc_dapm_get_enum_double, 1583 wcd9335_put_dec_enum); 1584 1585 static const struct snd_kcontrol_new tx_adc_mux4 = 1586 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1587 snd_soc_dapm_get_enum_double, 1588 wcd9335_put_dec_enum); 1589 1590 static const struct snd_kcontrol_new tx_adc_mux5 = 1591 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1592 snd_soc_dapm_get_enum_double, 1593 wcd9335_put_dec_enum); 1594 1595 static const struct snd_kcontrol_new tx_adc_mux6 = 1596 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1597 snd_soc_dapm_get_enum_double, 1598 wcd9335_put_dec_enum); 1599 1600 static const struct snd_kcontrol_new tx_adc_mux7 = 1601 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1602 snd_soc_dapm_get_enum_double, 1603 wcd9335_put_dec_enum); 1604 1605 static const struct snd_kcontrol_new tx_adc_mux8 = 1606 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1607 snd_soc_dapm_get_enum_double, 1608 wcd9335_put_dec_enum); 1609 1610 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1611 int rate_val, 1612 u32 rate) 1613 { 1614 struct snd_soc_component *component = dai->component; 1615 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1616 struct wcd9335_slim_ch *ch; 1617 int val, j; 1618 1619 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1620 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1621 val = snd_soc_component_read(component, 1622 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1623 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1624 1625 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1626 snd_soc_component_update_bits(component, 1627 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1628 WCD9335_CDC_MIX_PCM_RATE_MASK, 1629 rate_val); 1630 } 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1637 u8 rate_val, 1638 u32 rate) 1639 { 1640 struct snd_soc_component *comp = dai->component; 1641 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1642 struct wcd9335_slim_ch *ch; 1643 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1644 int inp, j; 1645 1646 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1647 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1648 /* 1649 * Loop through all interpolator MUX inputs and find out 1650 * to which interpolator input, the slim rx port 1651 * is connected 1652 */ 1653 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1654 cfg0 = snd_soc_component_read(comp, 1655 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1656 cfg1 = snd_soc_component_read(comp, 1657 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1658 1659 inp0_sel = cfg0 & 1660 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1661 inp1_sel = (cfg0 >> 4) & 1662 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1663 inp2_sel = (cfg1 >> 4) & 1664 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1665 1666 if ((inp0_sel == inp) || (inp1_sel == inp) || 1667 (inp2_sel == inp)) { 1668 /* rate is in Hz */ 1669 if ((j == 0) && (rate == 44100)) 1670 dev_info(wcd->dev, 1671 "Cannot set 44.1KHz on INT0\n"); 1672 else 1673 snd_soc_component_update_bits(comp, 1674 WCD9335_CDC_RX_PATH_CTL(j), 1675 WCD9335_CDC_MIX_PCM_RATE_MASK, 1676 rate_val); 1677 } 1678 } 1679 } 1680 1681 return 0; 1682 } 1683 1684 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1685 { 1686 int i; 1687 1688 /* set mixing path rate */ 1689 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1690 if (rate == int_mix_rate_val[i].rate) { 1691 wcd9335_set_mix_interpolator_rate(dai, 1692 int_mix_rate_val[i].rate_val, rate); 1693 break; 1694 } 1695 } 1696 1697 /* set primary path sample rate */ 1698 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1699 if (rate == int_prim_rate_val[i].rate) { 1700 wcd9335_set_prim_interpolator_rate(dai, 1701 int_prim_rate_val[i].rate_val, rate); 1702 break; 1703 } 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1710 struct wcd_slim_codec_dai_data *dai_data, 1711 int direction) 1712 { 1713 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1714 struct slim_stream_config *cfg = &dai_data->sconfig; 1715 struct wcd9335_slim_ch *ch; 1716 u16 payload = 0; 1717 int ret, i; 1718 1719 cfg->ch_count = 0; 1720 cfg->direction = direction; 1721 cfg->port_mask = 0; 1722 1723 /* Configure slave interface device */ 1724 list_for_each_entry(ch, slim_ch_list, list) { 1725 cfg->ch_count++; 1726 payload |= 1 << ch->shift; 1727 cfg->port_mask |= BIT(ch->port); 1728 } 1729 1730 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1731 if (!cfg->chs) 1732 return -ENOMEM; 1733 1734 i = 0; 1735 list_for_each_entry(ch, slim_ch_list, list) { 1736 cfg->chs[i++] = ch->ch_num; 1737 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1738 /* write to interface device */ 1739 ret = regmap_write(wcd->if_regmap, 1740 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1741 payload); 1742 1743 if (ret < 0) 1744 goto err; 1745 1746 /* configure the slave port for water mark and enable*/ 1747 ret = regmap_write(wcd->if_regmap, 1748 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1749 WCD9335_SLIM_WATER_MARK_VAL); 1750 if (ret < 0) 1751 goto err; 1752 } else { 1753 ret = regmap_write(wcd->if_regmap, 1754 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1755 payload & 0x00FF); 1756 if (ret < 0) 1757 goto err; 1758 1759 /* ports 8,9 */ 1760 ret = regmap_write(wcd->if_regmap, 1761 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1762 (payload & 0xFF00)>>8); 1763 if (ret < 0) 1764 goto err; 1765 1766 /* configure the slave port for water mark and enable*/ 1767 ret = regmap_write(wcd->if_regmap, 1768 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1769 WCD9335_SLIM_WATER_MARK_VAL); 1770 1771 if (ret < 0) 1772 goto err; 1773 } 1774 } 1775 1776 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1777 1778 return 0; 1779 1780 err: 1781 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1782 kfree(cfg->chs); 1783 cfg->chs = NULL; 1784 1785 return ret; 1786 } 1787 1788 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1789 u8 rate_val, u32 rate) 1790 { 1791 struct snd_soc_component *comp = dai->component; 1792 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1793 u8 shift = 0, shift_val = 0, tx_mux_sel; 1794 struct wcd9335_slim_ch *ch; 1795 int tx_port, tx_port_reg; 1796 int decimator = -1; 1797 1798 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1799 tx_port = ch->port; 1800 if ((tx_port == 12) || (tx_port >= 14)) { 1801 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1802 tx_port, dai->id); 1803 return -EINVAL; 1804 } 1805 /* Find the SB TX MUX input - which decimator is connected */ 1806 if (tx_port < 4) { 1807 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1808 shift = (tx_port << 1); 1809 shift_val = 0x03; 1810 } else if ((tx_port >= 4) && (tx_port < 8)) { 1811 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1812 shift = ((tx_port - 4) << 1); 1813 shift_val = 0x03; 1814 } else if ((tx_port >= 8) && (tx_port < 11)) { 1815 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1816 shift = ((tx_port - 8) << 1); 1817 shift_val = 0x03; 1818 } else if (tx_port == 11) { 1819 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1820 shift = 0; 1821 shift_val = 0x0F; 1822 } else if (tx_port == 13) { 1823 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1824 shift = 4; 1825 shift_val = 0x03; 1826 } else { 1827 return -EINVAL; 1828 } 1829 1830 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1831 (shift_val << shift); 1832 1833 tx_mux_sel = tx_mux_sel >> shift; 1834 if (tx_port <= 8) { 1835 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1836 decimator = tx_port; 1837 } else if (tx_port <= 10) { 1838 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1839 decimator = ((tx_port == 9) ? 7 : 6); 1840 } else if (tx_port == 11) { 1841 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1842 decimator = tx_mux_sel - 1; 1843 } else if (tx_port == 13) { 1844 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1845 decimator = 5; 1846 } 1847 1848 if (decimator >= 0) { 1849 snd_soc_component_update_bits(comp, 1850 WCD9335_CDC_TX_PATH_CTL(decimator), 1851 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1852 rate_val); 1853 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1854 /* Check if the TX Mux input is RX MIX TXn */ 1855 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1856 tx_port, tx_port); 1857 } else { 1858 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1859 decimator); 1860 return -EINVAL; 1861 } 1862 } 1863 1864 return 0; 1865 } 1866 1867 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1868 struct snd_pcm_hw_params *params, 1869 struct snd_soc_dai *dai) 1870 { 1871 struct wcd9335_codec *wcd; 1872 int ret, tx_fs_rate = 0; 1873 1874 wcd = snd_soc_component_get_drvdata(dai->component); 1875 1876 switch (substream->stream) { 1877 case SNDRV_PCM_STREAM_PLAYBACK: 1878 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1879 if (ret) { 1880 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1881 params_rate(params)); 1882 return ret; 1883 } 1884 switch (params_width(params)) { 1885 case 16 ... 24: 1886 wcd->dai[dai->id].sconfig.bps = params_width(params); 1887 break; 1888 default: 1889 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1890 __func__, params_width(params)); 1891 return -EINVAL; 1892 } 1893 break; 1894 1895 case SNDRV_PCM_STREAM_CAPTURE: 1896 switch (params_rate(params)) { 1897 case 8000: 1898 tx_fs_rate = 0; 1899 break; 1900 case 16000: 1901 tx_fs_rate = 1; 1902 break; 1903 case 32000: 1904 tx_fs_rate = 3; 1905 break; 1906 case 48000: 1907 tx_fs_rate = 4; 1908 break; 1909 case 96000: 1910 tx_fs_rate = 5; 1911 break; 1912 case 192000: 1913 tx_fs_rate = 6; 1914 break; 1915 case 384000: 1916 tx_fs_rate = 7; 1917 break; 1918 default: 1919 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1920 __func__, params_rate(params)); 1921 return -EINVAL; 1922 1923 } 1924 1925 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1926 params_rate(params)); 1927 if (ret < 0) { 1928 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1929 return ret; 1930 } 1931 switch (params_width(params)) { 1932 case 16 ... 32: 1933 wcd->dai[dai->id].sconfig.bps = params_width(params); 1934 break; 1935 default: 1936 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1937 __func__, params_width(params)); 1938 return -EINVAL; 1939 } 1940 break; 1941 default: 1942 dev_err(wcd->dev, "Invalid stream type %d\n", 1943 substream->stream); 1944 return -EINVAL; 1945 } 1946 1947 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1948 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1949 1950 return 0; 1951 } 1952 1953 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1954 struct snd_soc_dai *dai) 1955 { 1956 struct wcd_slim_codec_dai_data *dai_data; 1957 struct wcd9335_codec *wcd; 1958 struct slim_stream_config *cfg; 1959 1960 wcd = snd_soc_component_get_drvdata(dai->component); 1961 1962 dai_data = &wcd->dai[dai->id]; 1963 1964 switch (cmd) { 1965 case SNDRV_PCM_TRIGGER_START: 1966 case SNDRV_PCM_TRIGGER_RESUME: 1967 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1968 cfg = &dai_data->sconfig; 1969 slim_stream_prepare(dai_data->sruntime, cfg); 1970 slim_stream_enable(dai_data->sruntime); 1971 break; 1972 case SNDRV_PCM_TRIGGER_STOP: 1973 case SNDRV_PCM_TRIGGER_SUSPEND: 1974 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1975 slim_stream_unprepare(dai_data->sruntime); 1976 slim_stream_disable(dai_data->sruntime); 1977 break; 1978 default: 1979 break; 1980 } 1981 1982 return 0; 1983 } 1984 1985 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1986 unsigned int tx_num, unsigned int *tx_slot, 1987 unsigned int rx_num, unsigned int *rx_slot) 1988 { 1989 struct wcd9335_codec *wcd; 1990 int i; 1991 1992 wcd = snd_soc_component_get_drvdata(dai->component); 1993 1994 if (!tx_slot || !rx_slot) { 1995 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1996 tx_slot, rx_slot); 1997 return -EINVAL; 1998 } 1999 2000 wcd->num_rx_port = rx_num; 2001 for (i = 0; i < rx_num; i++) { 2002 wcd->rx_chs[i].ch_num = rx_slot[i]; 2003 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2004 } 2005 2006 wcd->num_tx_port = tx_num; 2007 for (i = 0; i < tx_num; i++) { 2008 wcd->tx_chs[i].ch_num = tx_slot[i]; 2009 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2010 } 2011 2012 return 0; 2013 } 2014 2015 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2016 unsigned int *tx_num, unsigned int *tx_slot, 2017 unsigned int *rx_num, unsigned int *rx_slot) 2018 { 2019 struct wcd9335_slim_ch *ch; 2020 struct wcd9335_codec *wcd; 2021 int i = 0; 2022 2023 wcd = snd_soc_component_get_drvdata(dai->component); 2024 2025 switch (dai->id) { 2026 case AIF1_PB: 2027 case AIF2_PB: 2028 case AIF3_PB: 2029 case AIF4_PB: 2030 if (!rx_slot || !rx_num) { 2031 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2032 rx_slot, rx_num); 2033 return -EINVAL; 2034 } 2035 2036 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2037 rx_slot[i++] = ch->ch_num; 2038 2039 *rx_num = i; 2040 break; 2041 case AIF1_CAP: 2042 case AIF2_CAP: 2043 case AIF3_CAP: 2044 if (!tx_slot || !tx_num) { 2045 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2046 tx_slot, tx_num); 2047 return -EINVAL; 2048 } 2049 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2050 tx_slot[i++] = ch->ch_num; 2051 2052 *tx_num = i; 2053 break; 2054 default: 2055 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2056 break; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2063 .hw_params = wcd9335_hw_params, 2064 .trigger = wcd9335_trigger, 2065 .set_channel_map = wcd9335_set_channel_map, 2066 .get_channel_map = wcd9335_get_channel_map, 2067 }; 2068 2069 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2070 [0] = { 2071 .name = "wcd9335_rx1", 2072 .id = AIF1_PB, 2073 .playback = { 2074 .stream_name = "AIF1 Playback", 2075 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2076 SNDRV_PCM_RATE_384000, 2077 .formats = WCD9335_FORMATS_S16_S24_LE, 2078 .rate_max = 384000, 2079 .rate_min = 8000, 2080 .channels_min = 1, 2081 .channels_max = 2, 2082 }, 2083 .ops = &wcd9335_dai_ops, 2084 }, 2085 [1] = { 2086 .name = "wcd9335_tx1", 2087 .id = AIF1_CAP, 2088 .capture = { 2089 .stream_name = "AIF1 Capture", 2090 .rates = WCD9335_RATES_MASK, 2091 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2092 .rate_min = 8000, 2093 .rate_max = 192000, 2094 .channels_min = 1, 2095 .channels_max = 4, 2096 }, 2097 .ops = &wcd9335_dai_ops, 2098 }, 2099 [2] = { 2100 .name = "wcd9335_rx2", 2101 .id = AIF2_PB, 2102 .playback = { 2103 .stream_name = "AIF2 Playback", 2104 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2105 SNDRV_PCM_RATE_384000, 2106 .formats = WCD9335_FORMATS_S16_S24_LE, 2107 .rate_min = 8000, 2108 .rate_max = 384000, 2109 .channels_min = 1, 2110 .channels_max = 2, 2111 }, 2112 .ops = &wcd9335_dai_ops, 2113 }, 2114 [3] = { 2115 .name = "wcd9335_tx2", 2116 .id = AIF2_CAP, 2117 .capture = { 2118 .stream_name = "AIF2 Capture", 2119 .rates = WCD9335_RATES_MASK, 2120 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2121 .rate_min = 8000, 2122 .rate_max = 192000, 2123 .channels_min = 1, 2124 .channels_max = 4, 2125 }, 2126 .ops = &wcd9335_dai_ops, 2127 }, 2128 [4] = { 2129 .name = "wcd9335_rx3", 2130 .id = AIF3_PB, 2131 .playback = { 2132 .stream_name = "AIF3 Playback", 2133 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2134 SNDRV_PCM_RATE_384000, 2135 .formats = WCD9335_FORMATS_S16_S24_LE, 2136 .rate_min = 8000, 2137 .rate_max = 384000, 2138 .channels_min = 1, 2139 .channels_max = 2, 2140 }, 2141 .ops = &wcd9335_dai_ops, 2142 }, 2143 [5] = { 2144 .name = "wcd9335_tx3", 2145 .id = AIF3_CAP, 2146 .capture = { 2147 .stream_name = "AIF3 Capture", 2148 .rates = WCD9335_RATES_MASK, 2149 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2150 .rate_min = 8000, 2151 .rate_max = 192000, 2152 .channels_min = 1, 2153 .channels_max = 4, 2154 }, 2155 .ops = &wcd9335_dai_ops, 2156 }, 2157 [6] = { 2158 .name = "wcd9335_rx4", 2159 .id = AIF4_PB, 2160 .playback = { 2161 .stream_name = "AIF4 Playback", 2162 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2163 SNDRV_PCM_RATE_384000, 2164 .formats = WCD9335_FORMATS_S16_S24_LE, 2165 .rate_min = 8000, 2166 .rate_max = 384000, 2167 .channels_min = 1, 2168 .channels_max = 2, 2169 }, 2170 .ops = &wcd9335_dai_ops, 2171 }, 2172 }; 2173 2174 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2175 struct snd_ctl_elem_value *ucontrol) 2176 { 2177 2178 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2179 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2180 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2181 2182 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2183 return 0; 2184 } 2185 2186 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2187 struct snd_ctl_elem_value *ucontrol) 2188 { 2189 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2190 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2191 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2192 int value = ucontrol->value.integer.value[0]; 2193 int sel; 2194 2195 wcd->comp_enabled[comp] = value; 2196 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2197 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2198 2199 /* Any specific register configuration for compander */ 2200 switch (comp) { 2201 case COMPANDER_1: 2202 /* Set Gain Source Select based on compander enable/disable */ 2203 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2204 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2205 break; 2206 case COMPANDER_2: 2207 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2208 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2209 break; 2210 case COMPANDER_5: 2211 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2212 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2213 break; 2214 case COMPANDER_6: 2215 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2216 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2217 break; 2218 default: 2219 break; 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2226 struct snd_ctl_elem_value *ucontrol) 2227 { 2228 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2229 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2230 2231 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2232 2233 return 0; 2234 } 2235 2236 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2237 struct snd_ctl_elem_value *ucontrol) 2238 { 2239 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2241 u32 mode_val; 2242 2243 mode_val = ucontrol->value.enumerated.item[0]; 2244 2245 if (mode_val == 0) { 2246 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2247 mode_val = CLS_H_HIFI; 2248 } 2249 wcd->hph_mode = mode_val; 2250 2251 return 0; 2252 } 2253 2254 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2255 /* -84dB min - 40dB max */ 2256 SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2257 0, -84, 40, digital_gain), 2258 SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2259 0, -84, 40, digital_gain), 2260 SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2261 0, -84, 40, digital_gain), 2262 SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2263 0, -84, 40, digital_gain), 2264 SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2265 0, -84, 40, digital_gain), 2266 SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2267 0, -84, 40, digital_gain), 2268 SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2269 0, -84, 40, digital_gain), 2270 SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2271 0, -84, 40, digital_gain), 2272 SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2273 0, -84, 40, digital_gain), 2274 SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume", 2275 WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2276 0, -84, 40, digital_gain), 2277 SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume", 2278 WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2279 0, -84, 40, digital_gain), 2280 SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume", 2281 WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2282 0, -84, 40, digital_gain), 2283 SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume", 2284 WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2285 0, -84, 40, digital_gain), 2286 SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume", 2287 WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2288 0, -84, 40, digital_gain), 2289 SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume", 2290 WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2291 0, -84, 40, digital_gain), 2292 SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume", 2293 WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2294 0, -84, 40, digital_gain), 2295 SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume", 2296 WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2297 0, -84, 40, digital_gain), 2298 SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume", 2299 WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2300 0, -84, 40, digital_gain), 2301 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2302 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2303 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2304 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2305 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2306 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2307 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2308 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2309 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2310 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2311 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2312 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2313 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2314 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2315 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2316 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2317 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2318 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2319 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2320 wcd9335_get_compander, wcd9335_set_compander), 2321 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2322 wcd9335_get_compander, wcd9335_set_compander), 2323 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2324 wcd9335_get_compander, wcd9335_set_compander), 2325 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2326 wcd9335_get_compander, wcd9335_set_compander), 2327 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2328 wcd9335_get_compander, wcd9335_set_compander), 2329 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2330 wcd9335_get_compander, wcd9335_set_compander), 2331 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2332 wcd9335_get_compander, wcd9335_set_compander), 2333 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2334 wcd9335_get_compander, wcd9335_set_compander), 2335 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2336 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2337 2338 /* Gain Controls */ 2339 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2340 ear_pa_gain), 2341 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2342 line_gain), 2343 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2344 line_gain), 2345 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2346 3, 16, 1, line_gain), 2347 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2348 3, 16, 1, line_gain), 2349 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2350 line_gain), 2351 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2352 line_gain), 2353 2354 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2355 analog_gain), 2356 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2357 analog_gain), 2358 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2359 analog_gain), 2360 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2361 analog_gain), 2362 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2363 analog_gain), 2364 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2365 analog_gain), 2366 2367 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2368 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2369 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2370 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2371 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2372 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2373 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2374 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2375 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2376 }; 2377 2378 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2379 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2380 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2381 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2382 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2383 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2384 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2385 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2386 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2387 2388 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2389 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2390 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2391 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2392 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2393 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2394 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2395 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2396 2397 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2398 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2399 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2400 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2401 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2402 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2403 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2404 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2405 2406 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2407 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2408 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2409 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2410 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2411 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2412 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2413 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2414 2415 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2416 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2417 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2418 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2419 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2420 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2421 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2422 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2423 2424 WCD9335_INTERPOLATOR_PATH(0), 2425 WCD9335_INTERPOLATOR_PATH(1), 2426 WCD9335_INTERPOLATOR_PATH(2), 2427 WCD9335_INTERPOLATOR_PATH(3), 2428 WCD9335_INTERPOLATOR_PATH(4), 2429 WCD9335_INTERPOLATOR_PATH(5), 2430 WCD9335_INTERPOLATOR_PATH(6), 2431 WCD9335_INTERPOLATOR_PATH(7), 2432 WCD9335_INTERPOLATOR_PATH(8), 2433 2434 /* EAR PA */ 2435 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2436 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2437 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2438 {"EAR PA", NULL, "RX INT0 DAC"}, 2439 {"EAR", NULL, "EAR PA"}, 2440 2441 /* HPHL */ 2442 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2443 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2444 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2445 {"HPHL PA", NULL, "RX INT1 DAC"}, 2446 {"HPHL", NULL, "HPHL PA"}, 2447 2448 /* HPHR */ 2449 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2450 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2451 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2452 {"HPHR PA", NULL, "RX INT2 DAC"}, 2453 {"HPHR", NULL, "HPHR PA"}, 2454 2455 /* LINEOUT1 */ 2456 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2457 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2458 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2459 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2460 2461 /* LINEOUT2 */ 2462 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2463 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2464 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2465 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2466 2467 /* LINEOUT3 */ 2468 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2469 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2470 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2471 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2472 2473 /* LINEOUT4 */ 2474 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2475 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2476 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2477 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2478 2479 /* SLIMBUS Connections */ 2480 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2481 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2482 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2483 2484 /* ADC Mux */ 2485 WCD9335_ADC_MUX_PATH(0), 2486 WCD9335_ADC_MUX_PATH(1), 2487 WCD9335_ADC_MUX_PATH(2), 2488 WCD9335_ADC_MUX_PATH(3), 2489 WCD9335_ADC_MUX_PATH(4), 2490 WCD9335_ADC_MUX_PATH(5), 2491 WCD9335_ADC_MUX_PATH(6), 2492 WCD9335_ADC_MUX_PATH(7), 2493 WCD9335_ADC_MUX_PATH(8), 2494 2495 /* ADC Connections */ 2496 {"ADC1", NULL, "AMIC1"}, 2497 {"ADC2", NULL, "AMIC2"}, 2498 {"ADC3", NULL, "AMIC3"}, 2499 {"ADC4", NULL, "AMIC4"}, 2500 {"ADC5", NULL, "AMIC5"}, 2501 {"ADC6", NULL, "AMIC6"}, 2502 }; 2503 2504 static int wcd9335_micbias_control(struct snd_soc_component *component, 2505 int micb_num, int req, bool is_dapm) 2506 { 2507 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2508 int micb_index = micb_num - 1; 2509 u16 micb_reg; 2510 2511 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2512 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2513 micb_index); 2514 return -EINVAL; 2515 } 2516 2517 switch (micb_num) { 2518 case MIC_BIAS_1: 2519 micb_reg = WCD9335_ANA_MICB1; 2520 break; 2521 case MIC_BIAS_2: 2522 micb_reg = WCD9335_ANA_MICB2; 2523 break; 2524 case MIC_BIAS_3: 2525 micb_reg = WCD9335_ANA_MICB3; 2526 break; 2527 case MIC_BIAS_4: 2528 micb_reg = WCD9335_ANA_MICB4; 2529 break; 2530 default: 2531 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2532 __func__, micb_num); 2533 return -EINVAL; 2534 } 2535 2536 switch (req) { 2537 case MICB_PULLUP_ENABLE: 2538 wcd->pullup_ref[micb_index]++; 2539 if ((wcd->pullup_ref[micb_index] == 1) && 2540 (wcd->micb_ref[micb_index] == 0)) 2541 snd_soc_component_update_bits(component, micb_reg, 2542 0xC0, 0x80); 2543 break; 2544 case MICB_PULLUP_DISABLE: 2545 wcd->pullup_ref[micb_index]--; 2546 if ((wcd->pullup_ref[micb_index] == 0) && 2547 (wcd->micb_ref[micb_index] == 0)) 2548 snd_soc_component_update_bits(component, micb_reg, 2549 0xC0, 0x00); 2550 break; 2551 case MICB_ENABLE: 2552 wcd->micb_ref[micb_index]++; 2553 if (wcd->micb_ref[micb_index] == 1) 2554 snd_soc_component_update_bits(component, micb_reg, 2555 0xC0, 0x40); 2556 break; 2557 case MICB_DISABLE: 2558 wcd->micb_ref[micb_index]--; 2559 if ((wcd->micb_ref[micb_index] == 0) && 2560 (wcd->pullup_ref[micb_index] > 0)) 2561 snd_soc_component_update_bits(component, micb_reg, 2562 0xC0, 0x80); 2563 else if ((wcd->micb_ref[micb_index] == 0) && 2564 (wcd->pullup_ref[micb_index] == 0)) { 2565 snd_soc_component_update_bits(component, micb_reg, 2566 0xC0, 0x00); 2567 } 2568 break; 2569 } 2570 2571 return 0; 2572 } 2573 2574 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2575 int event) 2576 { 2577 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2578 int micb_num; 2579 2580 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2581 micb_num = MIC_BIAS_1; 2582 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2583 micb_num = MIC_BIAS_2; 2584 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2585 micb_num = MIC_BIAS_3; 2586 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2587 micb_num = MIC_BIAS_4; 2588 else 2589 return -EINVAL; 2590 2591 switch (event) { 2592 case SND_SOC_DAPM_PRE_PMU: 2593 /* 2594 * MIC BIAS can also be requested by MBHC, 2595 * so use ref count to handle micbias pullup 2596 * and enable requests 2597 */ 2598 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2599 break; 2600 case SND_SOC_DAPM_POST_PMU: 2601 /* wait for cnp time */ 2602 usleep_range(1000, 1100); 2603 break; 2604 case SND_SOC_DAPM_POST_PMD: 2605 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2606 break; 2607 } 2608 2609 return 0; 2610 } 2611 2612 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2613 struct snd_kcontrol *kc, int event) 2614 { 2615 return __wcd9335_codec_enable_micbias(w, event); 2616 } 2617 2618 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2619 u16 amic_reg, bool set) 2620 { 2621 u8 mask = 0x20; 2622 u8 val; 2623 2624 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2625 amic_reg == WCD9335_ANA_AMIC5) 2626 mask = 0x40; 2627 2628 val = set ? mask : 0x00; 2629 2630 switch (amic_reg) { 2631 case WCD9335_ANA_AMIC1: 2632 case WCD9335_ANA_AMIC2: 2633 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2634 val); 2635 break; 2636 case WCD9335_ANA_AMIC3: 2637 case WCD9335_ANA_AMIC4: 2638 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2639 val); 2640 break; 2641 case WCD9335_ANA_AMIC5: 2642 case WCD9335_ANA_AMIC6: 2643 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2644 val); 2645 break; 2646 default: 2647 dev_err(comp->dev, "%s: invalid amic: %d\n", 2648 __func__, amic_reg); 2649 break; 2650 } 2651 } 2652 2653 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2654 struct snd_kcontrol *kc, int event) 2655 { 2656 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2657 2658 switch (event) { 2659 case SND_SOC_DAPM_PRE_PMU: 2660 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2661 break; 2662 default: 2663 break; 2664 } 2665 2666 return 0; 2667 } 2668 2669 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2670 int adc_mux_n) 2671 { 2672 int mux_sel, reg, mreg; 2673 2674 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2675 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2676 return 0; 2677 2678 /* Check whether adc mux input is AMIC or DMIC */ 2679 if (adc_mux_n < 4) { 2680 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2681 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2682 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2683 } else { 2684 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2685 mreg = reg; 2686 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2687 } 2688 2689 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2690 return 0; 2691 2692 return snd_soc_component_read(comp, mreg) & 0x07; 2693 } 2694 2695 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2696 int amic) 2697 { 2698 u16 pwr_level_reg = 0; 2699 2700 switch (amic) { 2701 case 1: 2702 case 2: 2703 pwr_level_reg = WCD9335_ANA_AMIC1; 2704 break; 2705 2706 case 3: 2707 case 4: 2708 pwr_level_reg = WCD9335_ANA_AMIC3; 2709 break; 2710 2711 case 5: 2712 case 6: 2713 pwr_level_reg = WCD9335_ANA_AMIC5; 2714 break; 2715 default: 2716 dev_err(comp->dev, "invalid amic: %d\n", amic); 2717 break; 2718 } 2719 2720 return pwr_level_reg; 2721 } 2722 2723 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2724 struct snd_kcontrol *kc, int event) 2725 { 2726 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2727 unsigned int decimator; 2728 char *dec_adc_mux_name = NULL; 2729 char *widget_name = NULL; 2730 char *wname; 2731 int ret = 0, amic_n; 2732 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2733 u16 tx_gain_ctl_reg; 2734 char *dec; 2735 u8 hpf_coff_freq; 2736 2737 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2738 if (!widget_name) 2739 return -ENOMEM; 2740 2741 wname = widget_name; 2742 dec_adc_mux_name = strsep(&widget_name, " "); 2743 if (!dec_adc_mux_name) { 2744 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2745 __func__, w->name); 2746 ret = -EINVAL; 2747 goto out; 2748 } 2749 dec_adc_mux_name = widget_name; 2750 2751 dec = strpbrk(dec_adc_mux_name, "012345678"); 2752 if (!dec) { 2753 dev_err(comp->dev, "%s: decimator index not found\n", 2754 __func__); 2755 ret = -EINVAL; 2756 goto out; 2757 } 2758 2759 ret = kstrtouint(dec, 10, &decimator); 2760 if (ret < 0) { 2761 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2762 __func__, wname); 2763 ret = -EINVAL; 2764 goto out; 2765 } 2766 2767 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2768 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2769 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2770 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2771 2772 switch (event) { 2773 case SND_SOC_DAPM_PRE_PMU: 2774 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2775 if (amic_n) 2776 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2777 amic_n); 2778 2779 if (pwr_level_reg) { 2780 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2781 WCD9335_AMIC_PWR_LVL_MASK) >> 2782 WCD9335_AMIC_PWR_LVL_SHIFT) { 2783 case WCD9335_AMIC_PWR_LEVEL_LP: 2784 snd_soc_component_update_bits(comp, dec_cfg_reg, 2785 WCD9335_DEC_PWR_LVL_MASK, 2786 WCD9335_DEC_PWR_LVL_LP); 2787 break; 2788 2789 case WCD9335_AMIC_PWR_LEVEL_HP: 2790 snd_soc_component_update_bits(comp, dec_cfg_reg, 2791 WCD9335_DEC_PWR_LVL_MASK, 2792 WCD9335_DEC_PWR_LVL_HP); 2793 break; 2794 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2795 default: 2796 snd_soc_component_update_bits(comp, dec_cfg_reg, 2797 WCD9335_DEC_PWR_LVL_MASK, 2798 WCD9335_DEC_PWR_LVL_DF); 2799 break; 2800 } 2801 } 2802 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2803 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2804 2805 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2806 snd_soc_component_update_bits(comp, dec_cfg_reg, 2807 TX_HPF_CUT_OFF_FREQ_MASK, 2808 CF_MIN_3DB_150HZ << 5); 2809 /* Enable TX PGA Mute */ 2810 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2811 0x10, 0x10); 2812 /* Enable APC */ 2813 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2814 break; 2815 case SND_SOC_DAPM_POST_PMU: 2816 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2817 2818 if (decimator == 0) { 2819 snd_soc_component_write(comp, 2820 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2821 snd_soc_component_write(comp, 2822 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2823 snd_soc_component_write(comp, 2824 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2825 snd_soc_component_write(comp, 2826 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2827 } 2828 2829 snd_soc_component_update_bits(comp, hpf_gate_reg, 2830 0x01, 0x01); 2831 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2832 0x10, 0x00); 2833 snd_soc_component_write(comp, tx_gain_ctl_reg, 2834 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2835 break; 2836 case SND_SOC_DAPM_PRE_PMD: 2837 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2838 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2839 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2840 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2841 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2842 snd_soc_component_update_bits(comp, dec_cfg_reg, 2843 TX_HPF_CUT_OFF_FREQ_MASK, 2844 hpf_coff_freq << 5); 2845 } 2846 break; 2847 case SND_SOC_DAPM_POST_PMD: 2848 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2849 break; 2850 } 2851 out: 2852 kfree(wname); 2853 return ret; 2854 } 2855 2856 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2857 u32 mclk_rate, u32 dmic_clk_rate) 2858 { 2859 u32 div_factor; 2860 u8 dmic_ctl_val; 2861 2862 dev_err(component->dev, 2863 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2864 __func__, mclk_rate, dmic_clk_rate); 2865 2866 /* Default value to return in case of error */ 2867 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2868 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2869 else 2870 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2871 2872 if (dmic_clk_rate == 0) { 2873 dev_err(component->dev, 2874 "%s: dmic_sample_rate cannot be 0\n", 2875 __func__); 2876 goto done; 2877 } 2878 2879 div_factor = mclk_rate / dmic_clk_rate; 2880 switch (div_factor) { 2881 case 2: 2882 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2883 break; 2884 case 3: 2885 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2886 break; 2887 case 4: 2888 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2889 break; 2890 case 6: 2891 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2892 break; 2893 case 8: 2894 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2895 break; 2896 case 16: 2897 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2898 break; 2899 default: 2900 dev_err(component->dev, 2901 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2902 __func__, div_factor, mclk_rate, dmic_clk_rate); 2903 break; 2904 } 2905 2906 done: 2907 return dmic_ctl_val; 2908 } 2909 2910 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2911 struct snd_kcontrol *kc, int event) 2912 { 2913 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2914 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2915 u8 dmic_clk_en = 0x01; 2916 u16 dmic_clk_reg; 2917 s32 *dmic_clk_cnt; 2918 u8 dmic_rate_val, dmic_rate_shift = 1; 2919 unsigned int dmic; 2920 int ret; 2921 char *wname; 2922 2923 wname = strpbrk(w->name, "012345"); 2924 if (!wname) { 2925 dev_err(comp->dev, "%s: widget not found\n", __func__); 2926 return -EINVAL; 2927 } 2928 2929 ret = kstrtouint(wname, 10, &dmic); 2930 if (ret < 0) { 2931 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2932 __func__); 2933 return -EINVAL; 2934 } 2935 2936 switch (dmic) { 2937 case 0: 2938 case 1: 2939 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2940 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2941 break; 2942 case 2: 2943 case 3: 2944 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2945 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2946 break; 2947 case 4: 2948 case 5: 2949 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2950 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2951 break; 2952 default: 2953 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2954 __func__); 2955 return -EINVAL; 2956 } 2957 2958 switch (event) { 2959 case SND_SOC_DAPM_PRE_PMU: 2960 dmic_rate_val = 2961 wcd9335_get_dmic_clk_val(comp, 2962 wcd->mclk_rate, 2963 wcd->dmic_sample_rate); 2964 2965 (*dmic_clk_cnt)++; 2966 if (*dmic_clk_cnt == 1) { 2967 snd_soc_component_update_bits(comp, dmic_clk_reg, 2968 0x07 << dmic_rate_shift, 2969 dmic_rate_val << dmic_rate_shift); 2970 snd_soc_component_update_bits(comp, dmic_clk_reg, 2971 dmic_clk_en, dmic_clk_en); 2972 } 2973 2974 break; 2975 case SND_SOC_DAPM_POST_PMD: 2976 dmic_rate_val = 2977 wcd9335_get_dmic_clk_val(comp, 2978 wcd->mclk_rate, 2979 wcd->mad_dmic_sample_rate); 2980 (*dmic_clk_cnt)--; 2981 if (*dmic_clk_cnt == 0) { 2982 snd_soc_component_update_bits(comp, dmic_clk_reg, 2983 dmic_clk_en, 0); 2984 snd_soc_component_update_bits(comp, dmic_clk_reg, 2985 0x07 << dmic_rate_shift, 2986 dmic_rate_val << dmic_rate_shift); 2987 } 2988 break; 2989 } 2990 2991 return 0; 2992 } 2993 2994 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2995 struct snd_soc_component *component) 2996 { 2997 int port_num = 0; 2998 unsigned short reg = 0; 2999 unsigned int val = 0; 3000 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3001 struct wcd9335_slim_ch *ch; 3002 3003 list_for_each_entry(ch, &dai->slim_ch_list, list) { 3004 if (ch->port >= WCD9335_RX_START) { 3005 port_num = ch->port - WCD9335_RX_START; 3006 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 3007 } else { 3008 port_num = ch->port; 3009 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3010 } 3011 3012 regmap_read(wcd->if_regmap, reg, &val); 3013 if (!(val & BIT(port_num % 8))) 3014 regmap_write(wcd->if_regmap, reg, 3015 val | BIT(port_num % 8)); 3016 } 3017 } 3018 3019 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3020 struct snd_kcontrol *kc, 3021 int event) 3022 { 3023 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3024 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3025 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3026 3027 switch (event) { 3028 case SND_SOC_DAPM_POST_PMU: 3029 wcd9335_codec_enable_int_port(dai, comp); 3030 break; 3031 case SND_SOC_DAPM_POST_PMD: 3032 kfree(dai->sconfig.chs); 3033 3034 break; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3041 struct snd_kcontrol *kc, int event) 3042 { 3043 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3044 u16 gain_reg; 3045 int offset_val = 0; 3046 int val = 0; 3047 3048 switch (w->reg) { 3049 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3050 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3051 break; 3052 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3053 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3054 break; 3055 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3056 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3057 break; 3058 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3059 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3060 break; 3061 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3062 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3063 break; 3064 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3065 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3066 break; 3067 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3068 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3069 break; 3070 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3071 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3072 break; 3073 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3074 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3075 break; 3076 default: 3077 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3078 __func__, w->name); 3079 return 0; 3080 } 3081 3082 switch (event) { 3083 case SND_SOC_DAPM_POST_PMU: 3084 val = snd_soc_component_read(comp, gain_reg); 3085 val += offset_val; 3086 snd_soc_component_write(comp, gain_reg, val); 3087 break; 3088 case SND_SOC_DAPM_POST_PMD: 3089 break; 3090 } 3091 3092 return 0; 3093 } 3094 3095 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3096 { 3097 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3098 3099 switch (reg) { 3100 case WCD9335_CDC_RX0_RX_PATH_CTL: 3101 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3102 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3103 *ind = 0; 3104 break; 3105 case WCD9335_CDC_RX1_RX_PATH_CTL: 3106 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3107 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3108 *ind = 1; 3109 break; 3110 case WCD9335_CDC_RX2_RX_PATH_CTL: 3111 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3112 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3113 *ind = 2; 3114 break; 3115 case WCD9335_CDC_RX3_RX_PATH_CTL: 3116 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3117 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3118 *ind = 3; 3119 break; 3120 case WCD9335_CDC_RX4_RX_PATH_CTL: 3121 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3122 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3123 *ind = 4; 3124 break; 3125 case WCD9335_CDC_RX5_RX_PATH_CTL: 3126 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3127 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3128 *ind = 5; 3129 break; 3130 case WCD9335_CDC_RX6_RX_PATH_CTL: 3131 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3132 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3133 *ind = 6; 3134 break; 3135 case WCD9335_CDC_RX7_RX_PATH_CTL: 3136 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3137 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3138 *ind = 7; 3139 break; 3140 case WCD9335_CDC_RX8_RX_PATH_CTL: 3141 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3142 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3143 *ind = 8; 3144 break; 3145 } 3146 3147 return prim_int_reg; 3148 } 3149 3150 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3151 u16 prim_int_reg, int event) 3152 { 3153 u16 hd2_scale_reg; 3154 u16 hd2_enable_reg = 0; 3155 3156 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3157 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3158 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3159 } 3160 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3161 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3162 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3163 } 3164 3165 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3166 snd_soc_component_update_bits(component, hd2_scale_reg, 3167 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3168 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3169 snd_soc_component_update_bits(component, hd2_scale_reg, 3170 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3171 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3172 snd_soc_component_update_bits(component, hd2_enable_reg, 3173 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3174 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3175 } 3176 3177 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3178 snd_soc_component_update_bits(component, hd2_enable_reg, 3179 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3180 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3181 snd_soc_component_update_bits(component, hd2_scale_reg, 3182 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3183 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3184 snd_soc_component_update_bits(component, hd2_scale_reg, 3185 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3186 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3187 } 3188 } 3189 3190 static int wcd9335_codec_enable_prim_interpolator( 3191 struct snd_soc_component *comp, 3192 u16 reg, int event) 3193 { 3194 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3195 u16 ind = 0; 3196 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3197 3198 switch (event) { 3199 case SND_SOC_DAPM_PRE_PMU: 3200 wcd->prim_int_users[ind]++; 3201 if (wcd->prim_int_users[ind] == 1) { 3202 snd_soc_component_update_bits(comp, prim_int_reg, 3203 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3204 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3205 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3206 snd_soc_component_update_bits(comp, prim_int_reg, 3207 WCD9335_CDC_RX_CLK_EN_MASK, 3208 WCD9335_CDC_RX_CLK_ENABLE); 3209 } 3210 3211 if ((reg != prim_int_reg) && 3212 ((snd_soc_component_read(comp, prim_int_reg)) & 3213 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3214 snd_soc_component_update_bits(comp, reg, 3215 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3216 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3217 break; 3218 case SND_SOC_DAPM_POST_PMD: 3219 wcd->prim_int_users[ind]--; 3220 if (wcd->prim_int_users[ind] == 0) { 3221 snd_soc_component_update_bits(comp, prim_int_reg, 3222 WCD9335_CDC_RX_CLK_EN_MASK, 3223 WCD9335_CDC_RX_CLK_DISABLE); 3224 snd_soc_component_update_bits(comp, prim_int_reg, 3225 WCD9335_CDC_RX_RESET_MASK, 3226 WCD9335_CDC_RX_RESET_ENABLE); 3227 snd_soc_component_update_bits(comp, prim_int_reg, 3228 WCD9335_CDC_RX_RESET_MASK, 3229 WCD9335_CDC_RX_RESET_DISABLE); 3230 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3231 } 3232 break; 3233 } 3234 3235 return 0; 3236 } 3237 3238 static int wcd9335_config_compander(struct snd_soc_component *component, 3239 int interp_n, int event) 3240 { 3241 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3242 int comp; 3243 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3244 3245 /* EAR does not have compander */ 3246 if (!interp_n) 3247 return 0; 3248 3249 comp = interp_n - 1; 3250 if (!wcd->comp_enabled[comp]) 3251 return 0; 3252 3253 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3254 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3255 3256 if (SND_SOC_DAPM_EVENT_ON(event)) { 3257 /* Enable Compander Clock */ 3258 snd_soc_component_update_bits(component, comp_ctl0_reg, 3259 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3260 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3261 /* Reset comander */ 3262 snd_soc_component_update_bits(component, comp_ctl0_reg, 3263 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3264 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3265 snd_soc_component_update_bits(component, comp_ctl0_reg, 3266 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3267 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3268 /* Enables DRE in this path */ 3269 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3270 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3271 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3272 } 3273 3274 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3275 snd_soc_component_update_bits(component, comp_ctl0_reg, 3276 WCD9335_CDC_COMPANDER_HALT_MASK, 3277 WCD9335_CDC_COMPANDER_HALT); 3278 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3279 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3280 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3281 3282 snd_soc_component_update_bits(component, comp_ctl0_reg, 3283 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3284 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3285 snd_soc_component_update_bits(component, comp_ctl0_reg, 3286 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3287 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3288 snd_soc_component_update_bits(component, comp_ctl0_reg, 3289 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3290 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3291 snd_soc_component_update_bits(component, comp_ctl0_reg, 3292 WCD9335_CDC_COMPANDER_HALT_MASK, 3293 WCD9335_CDC_COMPANDER_NOHALT); 3294 } 3295 3296 return 0; 3297 } 3298 3299 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3300 struct snd_kcontrol *kc, int event) 3301 { 3302 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3303 u16 gain_reg; 3304 u16 reg; 3305 int val; 3306 int offset_val = 0; 3307 3308 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3309 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3310 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3311 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3312 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3313 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3314 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3315 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3316 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3317 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3318 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3319 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3320 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3321 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3322 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3323 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3324 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3325 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3326 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3327 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3328 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3329 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3330 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3331 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3332 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3333 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3334 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3335 } else { 3336 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3337 __func__); 3338 return -EINVAL; 3339 } 3340 3341 switch (event) { 3342 case SND_SOC_DAPM_PRE_PMU: 3343 /* Reset if needed */ 3344 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3345 break; 3346 case SND_SOC_DAPM_POST_PMU: 3347 wcd9335_config_compander(comp, w->shift, event); 3348 val = snd_soc_component_read(comp, gain_reg); 3349 val += offset_val; 3350 snd_soc_component_write(comp, gain_reg, val); 3351 break; 3352 case SND_SOC_DAPM_POST_PMD: 3353 wcd9335_config_compander(comp, w->shift, event); 3354 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3355 break; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3362 u8 gain) 3363 { 3364 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3365 u8 hph_l_en, hph_r_en; 3366 u8 l_val, r_val; 3367 u8 hph_pa_status; 3368 bool is_hphl_pa, is_hphr_pa; 3369 3370 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3371 is_hphl_pa = hph_pa_status >> 7; 3372 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3373 3374 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3375 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3376 3377 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3378 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3379 3380 /* 3381 * Set HPH_L & HPH_R gain source selection to REGISTER 3382 * for better click and pop only if corresponding PAs are 3383 * not enabled. Also cache the values of the HPHL/R 3384 * PA gains to be applied after PAs are enabled 3385 */ 3386 if ((l_val != hph_l_en) && !is_hphl_pa) { 3387 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3388 wcd->hph_l_gain = hph_l_en & 0x1F; 3389 } 3390 3391 if ((r_val != hph_r_en) && !is_hphr_pa) { 3392 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3393 wcd->hph_r_gain = hph_r_en & 0x1F; 3394 } 3395 } 3396 3397 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3398 int event) 3399 { 3400 if (SND_SOC_DAPM_EVENT_ON(event)) { 3401 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3402 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3403 0x06); 3404 snd_soc_component_update_bits(comp, 3405 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3406 0xF0, 0x40); 3407 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3408 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3409 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3410 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3411 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3412 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3413 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3414 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3415 0x0C); 3416 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3417 } 3418 3419 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3420 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3421 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3422 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3423 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3424 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3425 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3426 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3427 0x8A); 3428 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3429 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3430 0x0A); 3431 } 3432 } 3433 3434 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3435 int event) 3436 { 3437 if (SND_SOC_DAPM_EVENT_ON(event)) { 3438 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3439 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3440 0x0C); 3441 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3442 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3443 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3444 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3445 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3446 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3447 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3448 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3449 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3450 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3451 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3452 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3453 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3454 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3455 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3456 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3457 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3458 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3459 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3460 snd_soc_component_update_bits(comp, 3461 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3462 snd_soc_component_update_bits(comp, 3463 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3464 } 3465 3466 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3467 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3468 0x88); 3469 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3470 0x33); 3471 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3472 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3473 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3474 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3475 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3476 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3477 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3478 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3479 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3480 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3481 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3482 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3483 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3484 WCD9335_HPH_CONST_SEL_L_MASK, 3485 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3486 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3487 WCD9335_HPH_CONST_SEL_L_MASK, 3488 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3489 } 3490 } 3491 3492 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3493 int event) 3494 { 3495 if (SND_SOC_DAPM_EVENT_ON(event)) { 3496 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3497 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3498 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3499 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3500 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3501 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3502 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3503 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3504 0x0C); 3505 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3506 } 3507 3508 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3509 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3510 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3511 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3512 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3513 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3514 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3515 } 3516 } 3517 3518 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3519 int event, int mode) 3520 { 3521 switch (mode) { 3522 case CLS_H_LP: 3523 wcd9335_codec_hph_lp_config(component, event); 3524 break; 3525 case CLS_H_LOHIFI: 3526 wcd9335_codec_hph_lohifi_config(component, event); 3527 break; 3528 case CLS_H_HIFI: 3529 wcd9335_codec_hph_hifi_config(component, event); 3530 break; 3531 } 3532 } 3533 3534 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3535 struct snd_kcontrol *kc, 3536 int event) 3537 { 3538 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3539 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3540 int hph_mode = wcd->hph_mode; 3541 u8 dem_inp; 3542 3543 switch (event) { 3544 case SND_SOC_DAPM_PRE_PMU: 3545 /* Read DEM INP Select */ 3546 dem_inp = snd_soc_component_read(comp, 3547 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3548 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3549 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3550 dev_err(comp->dev, "Incorrect DEM Input\n"); 3551 return -EINVAL; 3552 } 3553 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3554 WCD_CLSH_STATE_HPHL, 3555 ((hph_mode == CLS_H_LOHIFI) ? 3556 CLS_H_HIFI : hph_mode)); 3557 3558 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3559 3560 break; 3561 case SND_SOC_DAPM_POST_PMU: 3562 usleep_range(1000, 1100); 3563 break; 3564 case SND_SOC_DAPM_PRE_PMD: 3565 break; 3566 case SND_SOC_DAPM_POST_PMD: 3567 /* 1000us required as per HW requirement */ 3568 usleep_range(1000, 1100); 3569 3570 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3571 WCD_CLSH_STATE_HPHR)) 3572 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3573 3574 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3575 WCD_CLSH_STATE_HPHL, 3576 ((hph_mode == CLS_H_LOHIFI) ? 3577 CLS_H_HIFI : hph_mode)); 3578 break; 3579 } 3580 3581 return 0; 3582 } 3583 3584 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3585 struct snd_kcontrol *kc, int event) 3586 { 3587 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3588 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3589 3590 switch (event) { 3591 case SND_SOC_DAPM_PRE_PMU: 3592 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3593 WCD_CLSH_STATE_LO, CLS_AB); 3594 break; 3595 case SND_SOC_DAPM_POST_PMD: 3596 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3597 WCD_CLSH_STATE_LO, CLS_AB); 3598 break; 3599 } 3600 3601 return 0; 3602 } 3603 3604 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3605 struct snd_kcontrol *kc, int event) 3606 { 3607 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3608 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3609 3610 switch (event) { 3611 case SND_SOC_DAPM_PRE_PMU: 3612 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3613 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3614 3615 break; 3616 case SND_SOC_DAPM_POST_PMD: 3617 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3618 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3619 break; 3620 } 3621 3622 return 0; 3623 } 3624 3625 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3626 int mode, int event) 3627 { 3628 u8 scale_val = 0; 3629 3630 switch (event) { 3631 case SND_SOC_DAPM_POST_PMU: 3632 switch (mode) { 3633 case CLS_H_HIFI: 3634 scale_val = 0x3; 3635 break; 3636 case CLS_H_LOHIFI: 3637 scale_val = 0x1; 3638 break; 3639 } 3640 break; 3641 case SND_SOC_DAPM_PRE_PMD: 3642 scale_val = 0x6; 3643 break; 3644 } 3645 3646 if (scale_val) 3647 snd_soc_component_update_bits(wcd->component, 3648 WCD9335_HPH_PA_CTL1, 3649 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3650 scale_val << 1); 3651 if (SND_SOC_DAPM_EVENT_ON(event)) { 3652 if (wcd->comp_enabled[COMPANDER_1] || 3653 wcd->comp_enabled[COMPANDER_2]) { 3654 /* GAIN Source Selection */ 3655 snd_soc_component_update_bits(wcd->component, 3656 WCD9335_HPH_L_EN, 3657 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3658 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3659 snd_soc_component_update_bits(wcd->component, 3660 WCD9335_HPH_R_EN, 3661 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3662 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3663 snd_soc_component_update_bits(wcd->component, 3664 WCD9335_HPH_AUTO_CHOP, 3665 WCD9335_HPH_AUTO_CHOP_MASK, 3666 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3667 } 3668 snd_soc_component_update_bits(wcd->component, 3669 WCD9335_HPH_L_EN, 3670 WCD9335_HPH_PA_GAIN_MASK, 3671 wcd->hph_l_gain); 3672 snd_soc_component_update_bits(wcd->component, 3673 WCD9335_HPH_R_EN, 3674 WCD9335_HPH_PA_GAIN_MASK, 3675 wcd->hph_r_gain); 3676 } 3677 3678 if (SND_SOC_DAPM_EVENT_OFF(event)) 3679 snd_soc_component_update_bits(wcd->component, 3680 WCD9335_HPH_AUTO_CHOP, 3681 WCD9335_HPH_AUTO_CHOP_MASK, 3682 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3683 } 3684 3685 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3686 struct snd_kcontrol *kc, 3687 int event) 3688 { 3689 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3690 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3691 int hph_mode = wcd->hph_mode; 3692 u8 dem_inp; 3693 3694 switch (event) { 3695 case SND_SOC_DAPM_PRE_PMU: 3696 3697 /* Read DEM INP Select */ 3698 dem_inp = snd_soc_component_read(comp, 3699 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3700 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3701 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3702 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3703 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3704 hph_mode); 3705 return -EINVAL; 3706 } 3707 3708 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3709 WCD_CLSH_EVENT_PRE_DAC, 3710 WCD_CLSH_STATE_HPHR, 3711 ((hph_mode == CLS_H_LOHIFI) ? 3712 CLS_H_HIFI : hph_mode)); 3713 3714 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3715 3716 break; 3717 case SND_SOC_DAPM_POST_PMD: 3718 /* 1000us required as per HW requirement */ 3719 usleep_range(1000, 1100); 3720 3721 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3722 WCD_CLSH_STATE_HPHL)) 3723 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3724 3725 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3726 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3727 CLS_H_HIFI : hph_mode)); 3728 break; 3729 } 3730 3731 return 0; 3732 } 3733 3734 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3735 struct snd_kcontrol *kc, 3736 int event) 3737 { 3738 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3739 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3740 int hph_mode = wcd->hph_mode; 3741 3742 switch (event) { 3743 case SND_SOC_DAPM_PRE_PMU: 3744 break; 3745 case SND_SOC_DAPM_POST_PMU: 3746 /* 3747 * 7ms sleep is required after PA is enabled as per 3748 * HW requirement 3749 */ 3750 usleep_range(7000, 7100); 3751 3752 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3753 snd_soc_component_update_bits(comp, 3754 WCD9335_CDC_RX1_RX_PATH_CTL, 3755 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3756 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3757 3758 /* Remove mix path mute if it is enabled */ 3759 if ((snd_soc_component_read(comp, 3760 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3761 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3762 snd_soc_component_update_bits(comp, 3763 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3764 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3765 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3766 3767 break; 3768 case SND_SOC_DAPM_PRE_PMD: 3769 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3770 break; 3771 case SND_SOC_DAPM_POST_PMD: 3772 /* 5ms sleep is required after PA is disabled as per 3773 * HW requirement 3774 */ 3775 usleep_range(5000, 5500); 3776 break; 3777 } 3778 3779 return 0; 3780 } 3781 3782 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3783 struct snd_kcontrol *kc, 3784 int event) 3785 { 3786 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3787 int vol_reg = 0, mix_vol_reg = 0; 3788 3789 if (w->reg == WCD9335_ANA_LO_1_2) { 3790 if (w->shift == 7) { 3791 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3792 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3793 } else if (w->shift == 6) { 3794 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3795 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3796 } 3797 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3798 if (w->shift == 7) { 3799 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3800 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3801 } else if (w->shift == 6) { 3802 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3803 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3804 } 3805 } else { 3806 dev_err(comp->dev, "Error enabling lineout PA\n"); 3807 return -EINVAL; 3808 } 3809 3810 switch (event) { 3811 case SND_SOC_DAPM_POST_PMU: 3812 /* 5ms sleep is required after PA is enabled as per 3813 * HW requirement 3814 */ 3815 usleep_range(5000, 5500); 3816 snd_soc_component_update_bits(comp, vol_reg, 3817 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3818 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3819 3820 /* Remove mix path mute if it is enabled */ 3821 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3822 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3823 snd_soc_component_update_bits(comp, mix_vol_reg, 3824 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3825 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3826 break; 3827 case SND_SOC_DAPM_POST_PMD: 3828 /* 5ms sleep is required after PA is disabled as per 3829 * HW requirement 3830 */ 3831 usleep_range(5000, 5500); 3832 break; 3833 } 3834 3835 return 0; 3836 } 3837 3838 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3839 { 3840 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3841 WCD9335_HPH_CONST_SEL_L_MASK, 3842 WCD9335_HPH_CONST_SEL_L_BYPASS); 3843 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3844 WCD9335_HPH_CONST_SEL_L_MASK, 3845 WCD9335_HPH_CONST_SEL_L_BYPASS); 3846 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3847 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3848 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3849 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3850 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3851 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3852 } 3853 3854 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3855 struct snd_kcontrol *kc, int event) 3856 { 3857 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3858 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3859 3860 switch (event) { 3861 case SND_SOC_DAPM_PRE_PMU: 3862 wcd->rx_bias_count++; 3863 if (wcd->rx_bias_count == 1) { 3864 wcd9335_codec_init_flyback(comp); 3865 snd_soc_component_update_bits(comp, 3866 WCD9335_ANA_RX_SUPPLIES, 3867 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3868 WCD9335_ANA_RX_BIAS_ENABLE); 3869 } 3870 break; 3871 case SND_SOC_DAPM_POST_PMD: 3872 wcd->rx_bias_count--; 3873 if (!wcd->rx_bias_count) 3874 snd_soc_component_update_bits(comp, 3875 WCD9335_ANA_RX_SUPPLIES, 3876 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3877 WCD9335_ANA_RX_BIAS_DISABLE); 3878 break; 3879 } 3880 3881 return 0; 3882 } 3883 3884 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3885 struct snd_kcontrol *kc, int event) 3886 { 3887 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3888 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3889 int hph_mode = wcd->hph_mode; 3890 3891 switch (event) { 3892 case SND_SOC_DAPM_PRE_PMU: 3893 break; 3894 case SND_SOC_DAPM_POST_PMU: 3895 /* 3896 * 7ms sleep is required after PA is enabled as per 3897 * HW requirement 3898 */ 3899 usleep_range(7000, 7100); 3900 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3901 snd_soc_component_update_bits(comp, 3902 WCD9335_CDC_RX2_RX_PATH_CTL, 3903 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3904 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3905 /* Remove mix path mute if it is enabled */ 3906 if ((snd_soc_component_read(comp, 3907 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3908 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3909 snd_soc_component_update_bits(comp, 3910 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3911 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3912 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3913 3914 break; 3915 3916 case SND_SOC_DAPM_PRE_PMD: 3917 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3918 break; 3919 case SND_SOC_DAPM_POST_PMD: 3920 /* 5ms sleep is required after PA is disabled as per 3921 * HW requirement 3922 */ 3923 usleep_range(5000, 5500); 3924 break; 3925 } 3926 3927 return 0; 3928 } 3929 3930 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3931 struct snd_kcontrol *kc, int event) 3932 { 3933 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3934 3935 switch (event) { 3936 case SND_SOC_DAPM_POST_PMU: 3937 /* 5ms sleep is required after PA is enabled as per 3938 * HW requirement 3939 */ 3940 usleep_range(5000, 5500); 3941 snd_soc_component_update_bits(comp, 3942 WCD9335_CDC_RX0_RX_PATH_CTL, 3943 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3944 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3945 /* Remove mix path mute if it is enabled */ 3946 if ((snd_soc_component_read(comp, 3947 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3948 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3949 snd_soc_component_update_bits(comp, 3950 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3951 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3952 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3953 break; 3954 case SND_SOC_DAPM_POST_PMD: 3955 /* 5ms sleep is required after PA is disabled as per 3956 * HW requirement 3957 */ 3958 usleep_range(5000, 5500); 3959 3960 break; 3961 } 3962 3963 return 0; 3964 } 3965 3966 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3967 { 3968 struct wcd9335_codec *wcd = data; 3969 unsigned long status = 0; 3970 int i, j, port_id; 3971 unsigned int val, int_val = 0; 3972 irqreturn_t ret = IRQ_NONE; 3973 bool tx; 3974 unsigned short reg = 0; 3975 3976 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3977 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3978 regmap_read(wcd->if_regmap, i, &val); 3979 status |= ((u32)val << (8 * j)); 3980 } 3981 3982 for_each_set_bit(j, &status, 32) { 3983 tx = (j >= 16); 3984 port_id = (tx ? j - 16 : j); 3985 regmap_read(wcd->if_regmap, 3986 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3987 if (val) { 3988 if (!tx) 3989 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3990 (port_id / 8); 3991 else 3992 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3993 (port_id / 8); 3994 regmap_read( 3995 wcd->if_regmap, reg, &int_val); 3996 /* 3997 * Ignore interrupts for ports for which the 3998 * interrupts are not specifically enabled. 3999 */ 4000 if (!(int_val & (1 << (port_id % 8)))) 4001 continue; 4002 } 4003 4004 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 4005 dev_err_ratelimited(wcd->dev, 4006 "%s: overflow error on %s port %d, value %x\n", 4007 __func__, (tx ? "TX" : "RX"), port_id, val); 4008 4009 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 4010 dev_err_ratelimited(wcd->dev, 4011 "%s: underflow error on %s port %d, value %x\n", 4012 __func__, (tx ? "TX" : "RX"), port_id, val); 4013 4014 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4015 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4016 if (!tx) 4017 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4018 (port_id / 8); 4019 else 4020 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4021 (port_id / 8); 4022 regmap_read( 4023 wcd->if_regmap, reg, &int_val); 4024 if (int_val & (1 << (port_id % 8))) { 4025 int_val = int_val ^ (1 << (port_id % 8)); 4026 regmap_write(wcd->if_regmap, 4027 reg, int_val); 4028 } 4029 } 4030 4031 regmap_write(wcd->if_regmap, 4032 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4033 BIT(j % 8)); 4034 ret = IRQ_HANDLED; 4035 } 4036 4037 return ret; 4038 } 4039 4040 static struct wcd9335_irq wcd9335_irqs[] = { 4041 { 4042 .irq = WCD9335_IRQ_SLIMBUS, 4043 .handler = wcd9335_slimbus_irq, 4044 .name = "SLIM Slave", 4045 }, 4046 }; 4047 4048 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4049 { 4050 int irq, ret, i; 4051 4052 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4053 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4054 if (irq < 0) { 4055 dev_err(wcd->dev, "Failed to get %s\n", 4056 wcd9335_irqs[i].name); 4057 return irq; 4058 } 4059 4060 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4061 wcd9335_irqs[i].handler, 4062 IRQF_TRIGGER_RISING | 4063 IRQF_ONESHOT, 4064 wcd9335_irqs[i].name, wcd); 4065 if (ret) { 4066 dev_err(wcd->dev, "Failed to request %s\n", 4067 wcd9335_irqs[i].name); 4068 return ret; 4069 } 4070 } 4071 4072 /* enable interrupts on all slave ports */ 4073 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4074 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4075 0xFF); 4076 4077 return ret; 4078 } 4079 4080 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4081 { 4082 int i; 4083 4084 /* disable interrupts on all slave ports */ 4085 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4086 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4087 0x00); 4088 } 4089 4090 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4091 bool ccl_flag) 4092 { 4093 struct snd_soc_component *comp = wcd->component; 4094 4095 if (ccl_flag) { 4096 if (++wcd->sido_ccl_cnt == 1) 4097 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4098 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4099 } else { 4100 if (wcd->sido_ccl_cnt == 0) { 4101 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4102 return; 4103 } 4104 if (--wcd->sido_ccl_cnt == 0) 4105 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4106 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4107 } 4108 } 4109 4110 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4111 { 4112 wcd->master_bias_users++; 4113 if (wcd->master_bias_users == 1) { 4114 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4115 WCD9335_ANA_BIAS_EN_MASK, 4116 WCD9335_ANA_BIAS_ENABLE); 4117 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4118 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4119 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4120 /* 4121 * 1ms delay is required after pre-charge is enabled 4122 * as per HW requirement 4123 */ 4124 usleep_range(1000, 1100); 4125 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4126 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4127 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4128 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4129 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4130 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4131 } 4132 4133 return 0; 4134 } 4135 4136 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4137 { 4138 /* Enable mclk requires master bias to be enabled first */ 4139 if (wcd->master_bias_users <= 0) 4140 return -EINVAL; 4141 4142 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4143 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4144 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4145 wcd->clk_type); 4146 return -EINVAL; 4147 } 4148 4149 if (++wcd->clk_mclk_users == 1) { 4150 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4151 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4152 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4153 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4154 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4155 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4156 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4157 WCD9335_ANA_CLK_MCLK_EN_MASK, 4158 WCD9335_ANA_CLK_MCLK_ENABLE); 4159 regmap_update_bits(wcd->regmap, 4160 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4161 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4162 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4163 regmap_update_bits(wcd->regmap, 4164 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4165 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4166 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4167 /* 4168 * 10us sleep is required after clock is enabled 4169 * as per HW requirement 4170 */ 4171 usleep_range(10, 15); 4172 } 4173 4174 wcd->clk_type = WCD_CLK_MCLK; 4175 4176 return 0; 4177 } 4178 4179 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4180 { 4181 if (wcd->clk_mclk_users <= 0) 4182 return -EINVAL; 4183 4184 if (--wcd->clk_mclk_users == 0) { 4185 if (wcd->clk_rco_users > 0) { 4186 /* MCLK to RCO switch */ 4187 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4188 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4189 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4190 wcd->clk_type = WCD_CLK_RCO; 4191 } else { 4192 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4193 WCD9335_ANA_CLK_MCLK_EN_MASK, 4194 WCD9335_ANA_CLK_MCLK_DISABLE); 4195 wcd->clk_type = WCD_CLK_OFF; 4196 } 4197 4198 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4199 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4200 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4201 } 4202 4203 return 0; 4204 } 4205 4206 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4207 { 4208 if (wcd->master_bias_users <= 0) 4209 return -EINVAL; 4210 4211 wcd->master_bias_users--; 4212 if (wcd->master_bias_users == 0) { 4213 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4214 WCD9335_ANA_BIAS_EN_MASK, 4215 WCD9335_ANA_BIAS_DISABLE); 4216 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4217 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4218 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4219 } 4220 return 0; 4221 } 4222 4223 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4224 bool enable) 4225 { 4226 int ret = 0; 4227 4228 if (enable) { 4229 wcd9335_cdc_sido_ccl_enable(wcd, true); 4230 ret = clk_prepare_enable(wcd->mclk); 4231 if (ret) { 4232 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4233 __func__); 4234 goto err; 4235 } 4236 /* get BG */ 4237 wcd9335_enable_master_bias(wcd); 4238 /* get MCLK */ 4239 wcd9335_enable_mclk(wcd); 4240 4241 } else { 4242 /* put MCLK */ 4243 wcd9335_disable_mclk(wcd); 4244 /* put BG */ 4245 wcd9335_disable_master_bias(wcd); 4246 clk_disable_unprepare(wcd->mclk); 4247 wcd9335_cdc_sido_ccl_enable(wcd, false); 4248 } 4249 err: 4250 return ret; 4251 } 4252 4253 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4254 enum wcd9335_sido_voltage req_mv) 4255 { 4256 struct snd_soc_component *comp = wcd->component; 4257 int vout_d_val; 4258 4259 if (req_mv == wcd->sido_voltage) 4260 return; 4261 4262 /* compute the vout_d step value */ 4263 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4264 WCD9335_ANA_BUCK_VOUT_MASK; 4265 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4266 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4267 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4268 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4269 4270 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4271 usleep_range(1000, 1100); 4272 wcd->sido_voltage = req_mv; 4273 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4274 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4275 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4276 } 4277 4278 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4279 enum wcd9335_sido_voltage req_mv) 4280 { 4281 int ret = 0; 4282 4283 /* enable mclk before setting SIDO voltage */ 4284 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4285 if (ret) { 4286 dev_err(wcd->dev, "Ext clk enable failed\n"); 4287 goto err; 4288 } 4289 4290 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4291 wcd9335_cdc_req_mclk_enable(wcd, false); 4292 4293 err: 4294 return ret; 4295 } 4296 4297 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4298 int enable) 4299 { 4300 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4301 int ret; 4302 4303 if (enable) { 4304 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4305 if (ret) 4306 return ret; 4307 4308 wcd9335_codec_apply_sido_voltage(wcd, 4309 SIDO_VOLTAGE_NOMINAL_MV); 4310 } else { 4311 wcd9335_codec_update_sido_voltage(wcd, 4312 wcd->sido_voltage); 4313 wcd9335_cdc_req_mclk_enable(wcd, false); 4314 } 4315 4316 return 0; 4317 } 4318 4319 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4320 struct snd_kcontrol *kc, int event) 4321 { 4322 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4323 4324 switch (event) { 4325 case SND_SOC_DAPM_PRE_PMU: 4326 return _wcd9335_codec_enable_mclk(comp, true); 4327 case SND_SOC_DAPM_POST_PMD: 4328 return _wcd9335_codec_enable_mclk(comp, false); 4329 } 4330 4331 return 0; 4332 } 4333 4334 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4335 /* TODO SPK1 & SPK2 OUT*/ 4336 SND_SOC_DAPM_OUTPUT("EAR"), 4337 SND_SOC_DAPM_OUTPUT("HPHL"), 4338 SND_SOC_DAPM_OUTPUT("HPHR"), 4339 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4340 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4341 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4342 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4343 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4344 AIF1_PB, 0, wcd9335_codec_enable_slim, 4345 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4346 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4347 AIF2_PB, 0, wcd9335_codec_enable_slim, 4348 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4349 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4350 AIF3_PB, 0, wcd9335_codec_enable_slim, 4351 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4352 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4353 AIF4_PB, 0, wcd9335_codec_enable_slim, 4354 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4355 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4356 &slim_rx_mux[WCD9335_RX0]), 4357 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4358 &slim_rx_mux[WCD9335_RX1]), 4359 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4360 &slim_rx_mux[WCD9335_RX2]), 4361 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4362 &slim_rx_mux[WCD9335_RX3]), 4363 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4364 &slim_rx_mux[WCD9335_RX4]), 4365 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4366 &slim_rx_mux[WCD9335_RX5]), 4367 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4368 &slim_rx_mux[WCD9335_RX6]), 4369 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4370 &slim_rx_mux[WCD9335_RX7]), 4371 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4372 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4373 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4374 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4375 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4376 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4377 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4378 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4379 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4380 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4381 SND_SOC_DAPM_POST_PMU), 4382 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4383 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4384 SND_SOC_DAPM_POST_PMU), 4385 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4386 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4387 SND_SOC_DAPM_POST_PMU), 4388 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4389 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4390 SND_SOC_DAPM_POST_PMU), 4391 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4392 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4393 SND_SOC_DAPM_POST_PMU), 4394 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4395 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4396 SND_SOC_DAPM_POST_PMU), 4397 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4398 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4399 SND_SOC_DAPM_POST_PMU), 4400 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4401 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4402 SND_SOC_DAPM_POST_PMU), 4403 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4404 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4405 SND_SOC_DAPM_POST_PMU), 4406 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4407 &rx_int0_1_mix_inp0_mux), 4408 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4409 &rx_int0_1_mix_inp1_mux), 4410 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4411 &rx_int0_1_mix_inp2_mux), 4412 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4413 &rx_int1_1_mix_inp0_mux), 4414 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4415 &rx_int1_1_mix_inp1_mux), 4416 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4417 &rx_int1_1_mix_inp2_mux), 4418 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4419 &rx_int2_1_mix_inp0_mux), 4420 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4421 &rx_int2_1_mix_inp1_mux), 4422 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4423 &rx_int2_1_mix_inp2_mux), 4424 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4425 &rx_int3_1_mix_inp0_mux), 4426 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4427 &rx_int3_1_mix_inp1_mux), 4428 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4429 &rx_int3_1_mix_inp2_mux), 4430 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4431 &rx_int4_1_mix_inp0_mux), 4432 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4433 &rx_int4_1_mix_inp1_mux), 4434 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4435 &rx_int4_1_mix_inp2_mux), 4436 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4437 &rx_int5_1_mix_inp0_mux), 4438 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4439 &rx_int5_1_mix_inp1_mux), 4440 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4441 &rx_int5_1_mix_inp2_mux), 4442 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4443 &rx_int6_1_mix_inp0_mux), 4444 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4445 &rx_int6_1_mix_inp1_mux), 4446 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4447 &rx_int6_1_mix_inp2_mux), 4448 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4449 &rx_int7_1_mix_inp0_mux), 4450 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4451 &rx_int7_1_mix_inp1_mux), 4452 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4453 &rx_int7_1_mix_inp2_mux), 4454 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4455 &rx_int8_1_mix_inp0_mux), 4456 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4457 &rx_int8_1_mix_inp1_mux), 4458 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4459 &rx_int8_1_mix_inp2_mux), 4460 4461 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4467 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4468 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4469 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4477 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4478 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4479 4480 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4481 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4482 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4483 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4484 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4485 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4486 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4487 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4488 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4489 4490 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4491 &rx_int0_dem_inp_mux), 4492 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4493 &rx_int1_dem_inp_mux), 4494 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4495 &rx_int2_dem_inp_mux), 4496 4497 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4498 INTERP_EAR, 0, &rx_int0_interp_mux, 4499 wcd9335_codec_enable_interpolator, 4500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4501 SND_SOC_DAPM_POST_PMD), 4502 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4503 INTERP_HPHL, 0, &rx_int1_interp_mux, 4504 wcd9335_codec_enable_interpolator, 4505 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4506 SND_SOC_DAPM_POST_PMD), 4507 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4508 INTERP_HPHR, 0, &rx_int2_interp_mux, 4509 wcd9335_codec_enable_interpolator, 4510 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4511 SND_SOC_DAPM_POST_PMD), 4512 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4513 INTERP_LO1, 0, &rx_int3_interp_mux, 4514 wcd9335_codec_enable_interpolator, 4515 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4516 SND_SOC_DAPM_POST_PMD), 4517 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4518 INTERP_LO2, 0, &rx_int4_interp_mux, 4519 wcd9335_codec_enable_interpolator, 4520 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4521 SND_SOC_DAPM_POST_PMD), 4522 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4523 INTERP_LO3, 0, &rx_int5_interp_mux, 4524 wcd9335_codec_enable_interpolator, 4525 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4526 SND_SOC_DAPM_POST_PMD), 4527 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4528 INTERP_LO4, 0, &rx_int6_interp_mux, 4529 wcd9335_codec_enable_interpolator, 4530 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4531 SND_SOC_DAPM_POST_PMD), 4532 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4533 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4534 wcd9335_codec_enable_interpolator, 4535 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4536 SND_SOC_DAPM_POST_PMD), 4537 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4538 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4539 wcd9335_codec_enable_interpolator, 4540 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4541 SND_SOC_DAPM_POST_PMD), 4542 4543 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4544 0, 0, wcd9335_codec_ear_dac_event, 4545 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4546 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4547 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4548 5, 0, wcd9335_codec_hphl_dac_event, 4549 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4550 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4551 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4552 4, 0, wcd9335_codec_hphr_dac_event, 4553 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4554 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4555 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4556 0, 0, wcd9335_codec_lineout_dac_event, 4557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4558 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4559 0, 0, wcd9335_codec_lineout_dac_event, 4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4561 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4562 0, 0, wcd9335_codec_lineout_dac_event, 4563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4564 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4565 0, 0, wcd9335_codec_lineout_dac_event, 4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4567 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4568 wcd9335_codec_enable_hphl_pa, 4569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4570 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4571 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4572 wcd9335_codec_enable_hphr_pa, 4573 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4574 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4575 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4576 wcd9335_codec_enable_ear_pa, 4577 SND_SOC_DAPM_POST_PMU | 4578 SND_SOC_DAPM_POST_PMD), 4579 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4580 wcd9335_codec_enable_lineout_pa, 4581 SND_SOC_DAPM_POST_PMU | 4582 SND_SOC_DAPM_POST_PMD), 4583 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4584 wcd9335_codec_enable_lineout_pa, 4585 SND_SOC_DAPM_POST_PMU | 4586 SND_SOC_DAPM_POST_PMD), 4587 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4588 wcd9335_codec_enable_lineout_pa, 4589 SND_SOC_DAPM_POST_PMU | 4590 SND_SOC_DAPM_POST_PMD), 4591 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4592 wcd9335_codec_enable_lineout_pa, 4593 SND_SOC_DAPM_POST_PMU | 4594 SND_SOC_DAPM_POST_PMD), 4595 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4596 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4597 SND_SOC_DAPM_POST_PMD), 4598 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4599 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4600 SND_SOC_DAPM_POST_PMD), 4601 4602 /* TX */ 4603 SND_SOC_DAPM_INPUT("AMIC1"), 4604 SND_SOC_DAPM_INPUT("AMIC2"), 4605 SND_SOC_DAPM_INPUT("AMIC3"), 4606 SND_SOC_DAPM_INPUT("AMIC4"), 4607 SND_SOC_DAPM_INPUT("AMIC5"), 4608 SND_SOC_DAPM_INPUT("AMIC6"), 4609 4610 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4611 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4612 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4613 4614 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4615 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4616 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4617 4618 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4619 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4620 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4621 4622 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4623 wcd9335_codec_enable_micbias, 4624 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4625 SND_SOC_DAPM_POST_PMD), 4626 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4627 wcd9335_codec_enable_micbias, 4628 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4629 SND_SOC_DAPM_POST_PMD), 4630 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4631 wcd9335_codec_enable_micbias, 4632 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4633 SND_SOC_DAPM_POST_PMD), 4634 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4635 wcd9335_codec_enable_micbias, 4636 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4637 SND_SOC_DAPM_POST_PMD), 4638 4639 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4640 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4641 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4642 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4643 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4644 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4645 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4646 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4647 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4648 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4649 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4650 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4651 4652 /* Digital Mic Inputs */ 4653 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4654 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4655 SND_SOC_DAPM_POST_PMD), 4656 4657 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4658 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4659 SND_SOC_DAPM_POST_PMD), 4660 4661 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4662 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4663 SND_SOC_DAPM_POST_PMD), 4664 4665 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4666 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4667 SND_SOC_DAPM_POST_PMD), 4668 4669 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4670 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4671 SND_SOC_DAPM_POST_PMD), 4672 4673 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4674 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4675 SND_SOC_DAPM_POST_PMD), 4676 4677 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4678 &tx_dmic_mux0), 4679 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4680 &tx_dmic_mux1), 4681 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4682 &tx_dmic_mux2), 4683 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4684 &tx_dmic_mux3), 4685 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4686 &tx_dmic_mux4), 4687 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4688 &tx_dmic_mux5), 4689 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4690 &tx_dmic_mux6), 4691 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4692 &tx_dmic_mux7), 4693 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4694 &tx_dmic_mux8), 4695 4696 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4697 &tx_amic_mux0), 4698 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4699 &tx_amic_mux1), 4700 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4701 &tx_amic_mux2), 4702 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4703 &tx_amic_mux3), 4704 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4705 &tx_amic_mux4), 4706 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4707 &tx_amic_mux5), 4708 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4709 &tx_amic_mux6), 4710 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4711 &tx_amic_mux7), 4712 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4713 &tx_amic_mux8), 4714 4715 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4716 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4717 4718 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4719 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4720 4721 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4722 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4723 4724 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4725 &sb_tx0_mux), 4726 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4727 &sb_tx1_mux), 4728 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4729 &sb_tx2_mux), 4730 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4731 &sb_tx3_mux), 4732 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4733 &sb_tx4_mux), 4734 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4735 &sb_tx5_mux), 4736 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4737 &sb_tx6_mux), 4738 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4739 &sb_tx7_mux), 4740 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4741 &sb_tx8_mux), 4742 4743 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4744 &tx_adc_mux0, wcd9335_codec_enable_dec, 4745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4746 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4747 4748 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4749 &tx_adc_mux1, wcd9335_codec_enable_dec, 4750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4751 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4752 4753 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4754 &tx_adc_mux2, wcd9335_codec_enable_dec, 4755 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4756 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4757 4758 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4759 &tx_adc_mux3, wcd9335_codec_enable_dec, 4760 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4761 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4762 4763 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4764 &tx_adc_mux4, wcd9335_codec_enable_dec, 4765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4766 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4767 4768 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4769 &tx_adc_mux5, wcd9335_codec_enable_dec, 4770 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4771 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4772 4773 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4774 &tx_adc_mux6, wcd9335_codec_enable_dec, 4775 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4776 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4777 4778 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4779 &tx_adc_mux7, wcd9335_codec_enable_dec, 4780 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4781 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4782 4783 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4784 &tx_adc_mux8, wcd9335_codec_enable_dec, 4785 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4786 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4787 }; 4788 4789 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4790 { 4791 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4792 4793 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4794 WCD9335_ANA_RCO_BG_EN_MASK, 4795 WCD9335_ANA_RCO_BG_ENABLE); 4796 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4797 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4798 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4799 /* 100us sleep needed after IREF settings */ 4800 usleep_range(100, 110); 4801 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4802 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4803 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4804 /* 100us sleep needed after VREF settings */ 4805 usleep_range(100, 110); 4806 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4807 } 4808 4809 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4810 { 4811 _wcd9335_codec_enable_mclk(comp, true); 4812 snd_soc_component_update_bits(comp, 4813 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4814 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4815 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4816 /* 4817 * 5ms sleep required after enabling efuse control 4818 * before checking the status. 4819 */ 4820 usleep_range(5000, 5500); 4821 4822 if (!(snd_soc_component_read(comp, 4823 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4824 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4825 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4826 4827 wcd9335_enable_sido_buck(comp); 4828 _wcd9335_codec_enable_mclk(comp, false); 4829 4830 return 0; 4831 } 4832 4833 static void wcd9335_codec_init(struct snd_soc_component *component) 4834 { 4835 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4836 int i; 4837 4838 /* ungate MCLK and set clk rate */ 4839 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4840 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4841 4842 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4843 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4844 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4845 4846 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4847 snd_soc_component_update_bits(component, 4848 wcd9335_codec_reg_init[i].reg, 4849 wcd9335_codec_reg_init[i].mask, 4850 wcd9335_codec_reg_init[i].val); 4851 4852 wcd9335_enable_efuse_sensing(component); 4853 } 4854 4855 static int wcd9335_codec_probe(struct snd_soc_component *component) 4856 { 4857 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4858 int ret; 4859 int i; 4860 4861 snd_soc_component_init_regmap(component, wcd->regmap); 4862 /* Class-H Init*/ 4863 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4864 if (IS_ERR(wcd->clsh_ctrl)) 4865 return PTR_ERR(wcd->clsh_ctrl); 4866 4867 /* Default HPH Mode to Class-H HiFi */ 4868 wcd->hph_mode = CLS_H_HIFI; 4869 wcd->component = component; 4870 4871 wcd9335_codec_init(component); 4872 4873 for (i = 0; i < NUM_CODEC_DAIS; i++) 4874 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4875 4876 ret = wcd9335_setup_irqs(wcd); 4877 if (ret) 4878 goto free_clsh_ctrl; 4879 4880 return 0; 4881 4882 free_clsh_ctrl: 4883 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4884 return ret; 4885 } 4886 4887 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4888 { 4889 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4890 4891 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4892 wcd9335_teardown_irqs(wcd); 4893 } 4894 4895 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4896 int clk_id, int source, 4897 unsigned int freq, int dir) 4898 { 4899 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4900 4901 wcd->mclk_rate = freq; 4902 4903 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4904 snd_soc_component_update_bits(comp, 4905 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4906 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4907 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4908 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4909 snd_soc_component_update_bits(comp, 4910 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4911 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4912 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4913 4914 return clk_set_rate(wcd->mclk, freq); 4915 } 4916 4917 static const struct snd_soc_component_driver wcd9335_component_drv = { 4918 .probe = wcd9335_codec_probe, 4919 .remove = wcd9335_codec_remove, 4920 .set_sysclk = wcd9335_codec_set_sysclk, 4921 .controls = wcd9335_snd_controls, 4922 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4923 .dapm_widgets = wcd9335_dapm_widgets, 4924 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4925 .dapm_routes = wcd9335_audio_map, 4926 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4927 .endianness = 1, 4928 }; 4929 4930 static int wcd9335_probe(struct wcd9335_codec *wcd) 4931 { 4932 struct device *dev = wcd->dev; 4933 4934 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4935 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4936 4937 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4938 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4939 4940 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4941 wcd9335_slim_dais, 4942 ARRAY_SIZE(wcd9335_slim_dais)); 4943 } 4944 4945 static const struct regmap_range_cfg wcd9335_ranges[] = { 4946 { 4947 .name = "WCD9335", 4948 .range_min = 0x0, 4949 .range_max = WCD9335_MAX_REGISTER, 4950 .selector_reg = WCD9335_SEL_REGISTER, 4951 .selector_mask = 0xff, 4952 .selector_shift = 0, 4953 .window_start = 0x800, 4954 .window_len = 0x100, 4955 }, 4956 }; 4957 4958 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4959 { 4960 switch (reg) { 4961 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4962 case WCD9335_ANA_MBHC_RESULT_3: 4963 case WCD9335_ANA_MBHC_RESULT_2: 4964 case WCD9335_ANA_MBHC_RESULT_1: 4965 case WCD9335_ANA_MBHC_MECH: 4966 case WCD9335_ANA_MBHC_ELECT: 4967 case WCD9335_ANA_MBHC_ZDET: 4968 case WCD9335_ANA_MICB2: 4969 case WCD9335_ANA_RCO: 4970 case WCD9335_ANA_BIAS: 4971 return true; 4972 default: 4973 return false; 4974 } 4975 } 4976 4977 static struct regmap_config wcd9335_regmap_config = { 4978 .reg_bits = 16, 4979 .val_bits = 8, 4980 .cache_type = REGCACHE_RBTREE, 4981 .max_register = WCD9335_MAX_REGISTER, 4982 .can_multi_write = true, 4983 .ranges = wcd9335_ranges, 4984 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4985 .volatile_reg = wcd9335_is_volatile_register, 4986 }; 4987 4988 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4989 { 4990 .name = "WCD9335-IFC-DEV", 4991 .range_min = 0x0, 4992 .range_max = WCD9335_MAX_REGISTER, 4993 .selector_reg = WCD9335_SEL_REGISTER, 4994 .selector_mask = 0xfff, 4995 .selector_shift = 0, 4996 .window_start = 0x800, 4997 .window_len = 0x400, 4998 }, 4999 }; 5000 5001 static struct regmap_config wcd9335_ifc_regmap_config = { 5002 .reg_bits = 16, 5003 .val_bits = 8, 5004 .can_multi_write = true, 5005 .max_register = WCD9335_MAX_REGISTER, 5006 .ranges = wcd9335_ifc_ranges, 5007 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 5008 }; 5009 5010 static const struct regmap_irq wcd9335_codec_irqs[] = { 5011 /* INTR_REG 0 */ 5012 [WCD9335_IRQ_SLIMBUS] = { 5013 .reg_offset = 0, 5014 .mask = BIT(0), 5015 .type = { 5016 .type_reg_offset = 0, 5017 .types_supported = IRQ_TYPE_EDGE_BOTH, 5018 .type_reg_mask = BIT(0), 5019 }, 5020 }, 5021 }; 5022 5023 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5024 .name = "wcd9335_pin1_irq", 5025 .status_base = WCD9335_INTR_PIN1_STATUS0, 5026 .mask_base = WCD9335_INTR_PIN1_MASK0, 5027 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5028 .type_base = WCD9335_INTR_LEVEL0, 5029 .num_type_reg = 4, 5030 .num_regs = 4, 5031 .irqs = wcd9335_codec_irqs, 5032 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5033 }; 5034 5035 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5036 { 5037 struct device *dev = wcd->dev; 5038 struct device_node *np = dev->of_node; 5039 int ret; 5040 5041 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5042 if (wcd->reset_gpio < 0) { 5043 dev_err(dev, "Reset GPIO missing from DT\n"); 5044 return wcd->reset_gpio; 5045 } 5046 5047 wcd->mclk = devm_clk_get(dev, "mclk"); 5048 if (IS_ERR(wcd->mclk)) { 5049 dev_err(dev, "mclk not found\n"); 5050 return PTR_ERR(wcd->mclk); 5051 } 5052 5053 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5054 if (IS_ERR(wcd->native_clk)) { 5055 dev_err(dev, "slimbus clock not found\n"); 5056 return PTR_ERR(wcd->native_clk); 5057 } 5058 5059 wcd->supplies[0].supply = "vdd-buck"; 5060 wcd->supplies[1].supply = "vdd-buck-sido"; 5061 wcd->supplies[2].supply = "vdd-tx"; 5062 wcd->supplies[3].supply = "vdd-rx"; 5063 wcd->supplies[4].supply = "vdd-io"; 5064 5065 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5066 if (ret) { 5067 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5068 return ret; 5069 } 5070 5071 return 0; 5072 } 5073 5074 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5075 { 5076 struct device *dev = wcd->dev; 5077 int ret; 5078 5079 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5080 if (ret) { 5081 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5082 return ret; 5083 } 5084 5085 /* 5086 * For WCD9335, it takes about 600us for the Vout_A and 5087 * Vout_D to be ready after BUCK_SIDO is powered up. 5088 * SYS_RST_N shouldn't be pulled high during this time 5089 * Toggle the reset line to make sure the reset pulse is 5090 * correctly applied 5091 */ 5092 usleep_range(600, 650); 5093 5094 gpio_direction_output(wcd->reset_gpio, 0); 5095 msleep(20); 5096 gpio_set_value(wcd->reset_gpio, 1); 5097 msleep(20); 5098 5099 return 0; 5100 } 5101 5102 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5103 { 5104 struct regmap *rm = wcd->regmap; 5105 int val, byte0; 5106 5107 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5108 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5109 5110 if ((val < 0) || (byte0 < 0)) { 5111 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5112 return -EINVAL; 5113 } 5114 5115 if (byte0 == 0x1) { 5116 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5117 wcd->version = WCD9335_VERSION_2_0; 5118 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5119 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5120 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5121 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5122 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5123 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5124 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5125 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5126 } else { 5127 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5128 return -EINVAL; 5129 } 5130 5131 return 0; 5132 } 5133 5134 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5135 { 5136 int ret; 5137 5138 /* 5139 * INTR1 consists of all possible interrupt sources Ear OCP, 5140 * HPH OCP, MBHC, MAD, VBAT, and SVA 5141 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5142 */ 5143 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5144 if (wcd->intr1 < 0) { 5145 if (wcd->intr1 != -EPROBE_DEFER) 5146 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5147 5148 return wcd->intr1; 5149 } 5150 5151 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5152 IRQF_TRIGGER_HIGH, 0, 5153 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5154 if (ret) 5155 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5156 5157 return ret; 5158 } 5159 5160 static int wcd9335_slim_probe(struct slim_device *slim) 5161 { 5162 struct device *dev = &slim->dev; 5163 struct wcd9335_codec *wcd; 5164 int ret; 5165 5166 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5167 if (!wcd) 5168 return -ENOMEM; 5169 5170 wcd->dev = dev; 5171 ret = wcd9335_parse_dt(wcd); 5172 if (ret) { 5173 dev_err(dev, "Error parsing DT: %d\n", ret); 5174 return ret; 5175 } 5176 5177 ret = wcd9335_power_on_reset(wcd); 5178 if (ret) 5179 return ret; 5180 5181 dev_set_drvdata(dev, wcd); 5182 5183 return 0; 5184 } 5185 5186 static int wcd9335_slim_status(struct slim_device *sdev, 5187 enum slim_device_status status) 5188 { 5189 struct device *dev = &sdev->dev; 5190 struct device_node *ifc_dev_np; 5191 struct wcd9335_codec *wcd; 5192 int ret; 5193 5194 wcd = dev_get_drvdata(dev); 5195 5196 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5197 if (!ifc_dev_np) { 5198 dev_err(dev, "No Interface device found\n"); 5199 return -EINVAL; 5200 } 5201 5202 wcd->slim = sdev; 5203 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5204 of_node_put(ifc_dev_np); 5205 if (!wcd->slim_ifc_dev) { 5206 dev_err(dev, "Unable to get SLIM Interface device\n"); 5207 return -EINVAL; 5208 } 5209 5210 slim_get_logical_addr(wcd->slim_ifc_dev); 5211 5212 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5213 if (IS_ERR(wcd->regmap)) { 5214 dev_err(dev, "Failed to allocate slim register map\n"); 5215 return PTR_ERR(wcd->regmap); 5216 } 5217 5218 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5219 &wcd9335_ifc_regmap_config); 5220 if (IS_ERR(wcd->if_regmap)) { 5221 dev_err(dev, "Failed to allocate ifc register map\n"); 5222 return PTR_ERR(wcd->if_regmap); 5223 } 5224 5225 ret = wcd9335_bring_up(wcd); 5226 if (ret) { 5227 dev_err(dev, "Failed to bringup WCD9335\n"); 5228 return ret; 5229 } 5230 5231 ret = wcd9335_irq_init(wcd); 5232 if (ret) 5233 return ret; 5234 5235 wcd9335_probe(wcd); 5236 5237 return 0; 5238 } 5239 5240 static const struct slim_device_id wcd9335_slim_id[] = { 5241 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5242 {} 5243 }; 5244 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5245 5246 static struct slim_driver wcd9335_slim_driver = { 5247 .driver = { 5248 .name = "wcd9335-slim", 5249 }, 5250 .probe = wcd9335_slim_probe, 5251 .device_status = wcd9335_slim_status, 5252 .id_table = wcd9335_slim_id, 5253 }; 5254 5255 module_slim_driver(wcd9335_slim_driver); 5256 MODULE_DESCRIPTION("WCD9335 slim driver"); 5257 MODULE_LICENSE("GPL v2"); 5258 MODULE_ALIAS("slim:217:1a0:*"); 5259