1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #include <dt-bindings/sound/qcom,wcd9335.h> 28 29 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 32 /* Fractional Rates */ 33 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 34 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE) 36 37 /* slave port water mark level 38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 39 */ 40 #define SLAVE_PORT_WATER_MARK_6BYTES 0 41 #define SLAVE_PORT_WATER_MARK_9BYTES 1 42 #define SLAVE_PORT_WATER_MARK_12BYTES 2 43 #define SLAVE_PORT_WATER_MARK_15BYTES 3 44 #define SLAVE_PORT_WATER_MARK_SHIFT 1 45 #define SLAVE_PORT_ENABLE 1 46 #define SLAVE_PORT_DISABLE 0 47 #define WCD9335_SLIM_WATER_MARK_VAL \ 48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 49 (SLAVE_PORT_ENABLE)) 50 51 #define WCD9335_SLIM_NUM_PORT_REG 3 52 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 53 54 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 55 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 56 57 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 58 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 59 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 60 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 61 62 #define WCD9335_NUM_INTERPOLATORS 9 63 #define WCD9335_RX_START 16 64 #define WCD9335_SLIM_CH_START 128 65 #define WCD9335_MAX_MICBIAS 4 66 #define WCD9335_MAX_VALID_ADC_MUX 13 67 #define WCD9335_INVALID_ADC_MUX 9 68 69 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 70 #define CF_MIN_3DB_4HZ 0x0 71 #define CF_MIN_3DB_75HZ 0x1 72 #define CF_MIN_3DB_150HZ 0x2 73 #define WCD9335_DMIC_CLK_DIV_2 0x0 74 #define WCD9335_DMIC_CLK_DIV_3 0x1 75 #define WCD9335_DMIC_CLK_DIV_4 0x2 76 #define WCD9335_DMIC_CLK_DIV_6 0x3 77 #define WCD9335_DMIC_CLK_DIV_8 0x4 78 #define WCD9335_DMIC_CLK_DIV_16 0x5 79 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 80 #define WCD9335_AMIC_PWR_LEVEL_LP 0 81 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 82 #define WCD9335_AMIC_PWR_LEVEL_HP 2 83 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 84 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 85 86 #define WCD9335_DEC_PWR_LVL_MASK 0x06 87 #define WCD9335_DEC_PWR_LVL_LP 0x02 88 #define WCD9335_DEC_PWR_LVL_HP 0x04 89 #define WCD9335_DEC_PWR_LVL_DF 0x00 90 91 #define WCD9335_SLIM_RX_CH(p) \ 92 {.port = p + WCD9335_RX_START, .shift = p,} 93 94 #define WCD9335_SLIM_TX_CH(p) \ 95 {.port = p, .shift = p,} 96 97 /* vout step value */ 98 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 99 100 #define WCD9335_INTERPOLATOR_PATH(id) \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 107 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 108 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 115 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 116 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 123 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 124 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 125 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 126 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 127 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 128 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 129 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 130 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 131 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 132 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 136 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 138 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 139 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 140 141 #define WCD9335_ADC_MUX_PATH(id) \ 142 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 144 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 145 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 146 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 147 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 148 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 149 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 150 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 151 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 152 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 153 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 154 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 155 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 156 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 157 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 158 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 159 {"AMIC MUX" #id, "ADC6", "ADC6"} 160 161 enum { 162 WCD9335_RX0 = 0, 163 WCD9335_RX1, 164 WCD9335_RX2, 165 WCD9335_RX3, 166 WCD9335_RX4, 167 WCD9335_RX5, 168 WCD9335_RX6, 169 WCD9335_RX7, 170 WCD9335_RX8, 171 WCD9335_RX9, 172 WCD9335_RX10, 173 WCD9335_RX11, 174 WCD9335_RX12, 175 WCD9335_RX_MAX, 176 }; 177 178 enum { 179 WCD9335_TX0 = 0, 180 WCD9335_TX1, 181 WCD9335_TX2, 182 WCD9335_TX3, 183 WCD9335_TX4, 184 WCD9335_TX5, 185 WCD9335_TX6, 186 WCD9335_TX7, 187 WCD9335_TX8, 188 WCD9335_TX9, 189 WCD9335_TX10, 190 WCD9335_TX11, 191 WCD9335_TX12, 192 WCD9335_TX13, 193 WCD9335_TX14, 194 WCD9335_TX15, 195 WCD9335_TX_MAX, 196 }; 197 198 enum { 199 SIDO_SOURCE_INTERNAL = 0, 200 SIDO_SOURCE_RCO_BG, 201 }; 202 203 enum wcd9335_sido_voltage { 204 SIDO_VOLTAGE_SVS_MV = 950, 205 SIDO_VOLTAGE_NOMINAL_MV = 1100, 206 }; 207 208 enum { 209 COMPANDER_1, /* HPH_L */ 210 COMPANDER_2, /* HPH_R */ 211 COMPANDER_3, /* LO1_DIFF */ 212 COMPANDER_4, /* LO2_DIFF */ 213 COMPANDER_5, /* LO3_SE */ 214 COMPANDER_6, /* LO4_SE */ 215 COMPANDER_7, /* SWR SPK CH1 */ 216 COMPANDER_8, /* SWR SPK CH2 */ 217 COMPANDER_MAX, 218 }; 219 220 enum { 221 INTn_2_INP_SEL_ZERO = 0, 222 INTn_2_INP_SEL_RX0, 223 INTn_2_INP_SEL_RX1, 224 INTn_2_INP_SEL_RX2, 225 INTn_2_INP_SEL_RX3, 226 INTn_2_INP_SEL_RX4, 227 INTn_2_INP_SEL_RX5, 228 INTn_2_INP_SEL_RX6, 229 INTn_2_INP_SEL_RX7, 230 INTn_2_INP_SEL_PROXIMITY, 231 }; 232 233 enum { 234 INTn_1_MIX_INP_SEL_ZERO = 0, 235 INTn_1_MIX_INP_SEL_DEC0, 236 INTn_1_MIX_INP_SEL_DEC1, 237 INTn_1_MIX_INP_SEL_IIR0, 238 INTn_1_MIX_INP_SEL_IIR1, 239 INTn_1_MIX_INP_SEL_RX0, 240 INTn_1_MIX_INP_SEL_RX1, 241 INTn_1_MIX_INP_SEL_RX2, 242 INTn_1_MIX_INP_SEL_RX3, 243 INTn_1_MIX_INP_SEL_RX4, 244 INTn_1_MIX_INP_SEL_RX5, 245 INTn_1_MIX_INP_SEL_RX6, 246 INTn_1_MIX_INP_SEL_RX7, 247 248 }; 249 250 enum { 251 INTERP_EAR = 0, 252 INTERP_HPHL, 253 INTERP_HPHR, 254 INTERP_LO1, 255 INTERP_LO2, 256 INTERP_LO3, 257 INTERP_LO4, 258 INTERP_SPKR1, 259 INTERP_SPKR2, 260 }; 261 262 enum wcd_clock_type { 263 WCD_CLK_OFF, 264 WCD_CLK_RCO, 265 WCD_CLK_MCLK, 266 }; 267 268 enum { 269 MIC_BIAS_1 = 1, 270 MIC_BIAS_2, 271 MIC_BIAS_3, 272 MIC_BIAS_4 273 }; 274 275 enum { 276 MICB_PULLUP_ENABLE, 277 MICB_PULLUP_DISABLE, 278 MICB_ENABLE, 279 MICB_DISABLE, 280 }; 281 282 struct wcd9335_slim_ch { 283 u32 ch_num; 284 u16 port; 285 u16 shift; 286 struct list_head list; 287 }; 288 289 struct wcd_slim_codec_dai_data { 290 struct list_head slim_ch_list; 291 struct slim_stream_config sconfig; 292 struct slim_stream_runtime *sruntime; 293 }; 294 295 struct wcd9335_codec { 296 struct device *dev; 297 struct clk *mclk; 298 struct clk *native_clk; 299 u32 mclk_rate; 300 u8 version; 301 302 struct slim_device *slim; 303 struct slim_device *slim_ifc_dev; 304 struct regmap *regmap; 305 struct regmap *if_regmap; 306 struct regmap_irq_chip_data *irq_data; 307 308 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 309 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 310 u32 num_rx_port; 311 u32 num_tx_port; 312 313 int sido_input_src; 314 enum wcd9335_sido_voltage sido_voltage; 315 316 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 317 struct snd_soc_component *component; 318 319 int master_bias_users; 320 int clk_mclk_users; 321 int clk_rco_users; 322 int sido_ccl_cnt; 323 enum wcd_clock_type clk_type; 324 325 struct wcd_clsh_ctrl *clsh_ctrl; 326 u32 hph_mode; 327 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 328 329 int comp_enabled[COMPANDER_MAX]; 330 331 int intr1; 332 int reset_gpio; 333 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 334 335 unsigned int rx_port_value[WCD9335_RX_MAX]; 336 unsigned int tx_port_value[WCD9335_TX_MAX]; 337 int hph_l_gain; 338 int hph_r_gain; 339 u32 rx_bias_count; 340 341 /*TX*/ 342 int micb_ref[WCD9335_MAX_MICBIAS]; 343 int pullup_ref[WCD9335_MAX_MICBIAS]; 344 345 int dmic_0_1_clk_cnt; 346 int dmic_2_3_clk_cnt; 347 int dmic_4_5_clk_cnt; 348 int dmic_sample_rate; 349 int mad_dmic_sample_rate; 350 351 int native_clk_users; 352 }; 353 354 struct wcd9335_irq { 355 int irq; 356 irqreturn_t (*handler)(int irq, void *data); 357 char *name; 358 }; 359 360 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 361 WCD9335_SLIM_TX_CH(0), 362 WCD9335_SLIM_TX_CH(1), 363 WCD9335_SLIM_TX_CH(2), 364 WCD9335_SLIM_TX_CH(3), 365 WCD9335_SLIM_TX_CH(4), 366 WCD9335_SLIM_TX_CH(5), 367 WCD9335_SLIM_TX_CH(6), 368 WCD9335_SLIM_TX_CH(7), 369 WCD9335_SLIM_TX_CH(8), 370 WCD9335_SLIM_TX_CH(9), 371 WCD9335_SLIM_TX_CH(10), 372 WCD9335_SLIM_TX_CH(11), 373 WCD9335_SLIM_TX_CH(12), 374 WCD9335_SLIM_TX_CH(13), 375 WCD9335_SLIM_TX_CH(14), 376 WCD9335_SLIM_TX_CH(15), 377 }; 378 379 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 380 WCD9335_SLIM_RX_CH(0), /* 16 */ 381 WCD9335_SLIM_RX_CH(1), /* 17 */ 382 WCD9335_SLIM_RX_CH(2), 383 WCD9335_SLIM_RX_CH(3), 384 WCD9335_SLIM_RX_CH(4), 385 WCD9335_SLIM_RX_CH(5), 386 WCD9335_SLIM_RX_CH(6), 387 WCD9335_SLIM_RX_CH(7), 388 WCD9335_SLIM_RX_CH(8), 389 WCD9335_SLIM_RX_CH(9), 390 WCD9335_SLIM_RX_CH(10), 391 WCD9335_SLIM_RX_CH(11), 392 WCD9335_SLIM_RX_CH(12), 393 }; 394 395 struct interp_sample_rate { 396 int rate; 397 int rate_val; 398 }; 399 400 static struct interp_sample_rate int_mix_rate_val[] = { 401 {48000, 0x4}, /* 48K */ 402 {96000, 0x5}, /* 96K */ 403 {192000, 0x6}, /* 192K */ 404 }; 405 406 static struct interp_sample_rate int_prim_rate_val[] = { 407 {8000, 0x0}, /* 8K */ 408 {16000, 0x1}, /* 16K */ 409 {24000, -EINVAL},/* 24K */ 410 {32000, 0x3}, /* 32K */ 411 {48000, 0x4}, /* 48K */ 412 {96000, 0x5}, /* 96K */ 413 {192000, 0x6}, /* 192K */ 414 {384000, 0x7}, /* 384K */ 415 {44100, 0x8}, /* 44.1K */ 416 }; 417 418 struct wcd9335_reg_mask_val { 419 u16 reg; 420 u8 mask; 421 u8 val; 422 }; 423 424 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 425 /* Rbuckfly/R_EAR(32) */ 426 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 427 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 428 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 429 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 430 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 431 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 432 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 433 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 434 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 435 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 436 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 437 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 438 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 439 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 440 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 441 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 442 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 443 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 444 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 445 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 446 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 447 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 448 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 449 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 454 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 455 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 456 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 466 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 467 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 468 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 469 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 470 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 471 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 472 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 473 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 474 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 475 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 476 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 477 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 478 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 479 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 480 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 483 }; 484 485 /* Cutoff frequency for high pass filter */ 486 static const char * const cf_text[] = { 487 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 488 }; 489 490 static const char * const rx_cf_text[] = { 491 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 492 "CF_NEG_3DB_0P48HZ" 493 }; 494 495 static const char * const rx_int0_7_mix_mux_text[] = { 496 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 497 "RX6", "RX7", "PROXIMITY" 498 }; 499 500 static const char * const rx_int_mix_mux_text[] = { 501 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 502 "RX6", "RX7" 503 }; 504 505 static const char * const rx_prim_mix_text[] = { 506 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 507 "RX3", "RX4", "RX5", "RX6", "RX7" 508 }; 509 510 static const char * const rx_int_dem_inp_mux_text[] = { 511 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 512 }; 513 514 static const char * const rx_int0_interp_mux_text[] = { 515 "ZERO", "RX INT0 MIX2", 516 }; 517 518 static const char * const rx_int1_interp_mux_text[] = { 519 "ZERO", "RX INT1 MIX2", 520 }; 521 522 static const char * const rx_int2_interp_mux_text[] = { 523 "ZERO", "RX INT2 MIX2", 524 }; 525 526 static const char * const rx_int3_interp_mux_text[] = { 527 "ZERO", "RX INT3 MIX2", 528 }; 529 530 static const char * const rx_int4_interp_mux_text[] = { 531 "ZERO", "RX INT4 MIX2", 532 }; 533 534 static const char * const rx_int5_interp_mux_text[] = { 535 "ZERO", "RX INT5 MIX2", 536 }; 537 538 static const char * const rx_int6_interp_mux_text[] = { 539 "ZERO", "RX INT6 MIX2", 540 }; 541 542 static const char * const rx_int7_interp_mux_text[] = { 543 "ZERO", "RX INT7 MIX2", 544 }; 545 546 static const char * const rx_int8_interp_mux_text[] = { 547 "ZERO", "RX INT8 SEC MIX" 548 }; 549 550 static const char * const rx_hph_mode_mux_text[] = { 551 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 552 "Class-H Hi-Fi Low Power" 553 }; 554 555 static const char *const slim_rx_mux_text[] = { 556 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 557 }; 558 559 static const char * const adc_mux_text[] = { 560 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 561 }; 562 563 static const char * const dmic_mux_text[] = { 564 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 565 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 566 }; 567 568 static const char * const dmic_mux_alt_text[] = { 569 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 570 }; 571 572 static const char * const amic_mux_text[] = { 573 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 574 }; 575 576 static const char * const sb_tx0_mux_text[] = { 577 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 578 }; 579 580 static const char * const sb_tx1_mux_text[] = { 581 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 582 }; 583 584 static const char * const sb_tx2_mux_text[] = { 585 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 586 }; 587 588 static const char * const sb_tx3_mux_text[] = { 589 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 590 }; 591 592 static const char * const sb_tx4_mux_text[] = { 593 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 594 }; 595 596 static const char * const sb_tx5_mux_text[] = { 597 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 598 }; 599 600 static const char * const sb_tx6_mux_text[] = { 601 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 602 }; 603 604 static const char * const sb_tx7_mux_text[] = { 605 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 606 }; 607 608 static const char * const sb_tx8_mux_text[] = { 609 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 610 }; 611 612 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 613 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 614 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 615 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 616 617 static const struct soc_enum cf_dec0_enum = 618 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 619 620 static const struct soc_enum cf_dec1_enum = 621 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 622 623 static const struct soc_enum cf_dec2_enum = 624 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 625 626 static const struct soc_enum cf_dec3_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec4_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec5_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec6_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec7_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec8_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_int0_1_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 646 647 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 648 rx_cf_text); 649 650 static const struct soc_enum cf_int1_1_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 652 653 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 654 rx_cf_text); 655 656 static const struct soc_enum cf_int2_1_enum = 657 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 658 659 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 660 rx_cf_text); 661 662 static const struct soc_enum cf_int3_1_enum = 663 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 664 665 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 666 rx_cf_text); 667 668 static const struct soc_enum cf_int4_1_enum = 669 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 670 671 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 672 rx_cf_text); 673 674 static const struct soc_enum cf_int5_1_enum = 675 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 676 677 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 678 rx_cf_text); 679 680 static const struct soc_enum cf_int6_1_enum = 681 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 682 683 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 684 rx_cf_text); 685 686 static const struct soc_enum cf_int7_1_enum = 687 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 688 689 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 690 rx_cf_text); 691 692 static const struct soc_enum cf_int8_1_enum = 693 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 694 695 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 696 rx_cf_text); 697 698 static const struct soc_enum rx_hph_mode_mux_enum = 699 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 700 rx_hph_mode_mux_text); 701 702 static const struct soc_enum slim_rx_mux_enum = 703 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 704 705 static const struct soc_enum rx_int0_2_mux_chain_enum = 706 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 707 rx_int0_7_mix_mux_text); 708 709 static const struct soc_enum rx_int1_2_mux_chain_enum = 710 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 711 rx_int_mix_mux_text); 712 713 static const struct soc_enum rx_int2_2_mux_chain_enum = 714 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 715 rx_int_mix_mux_text); 716 717 static const struct soc_enum rx_int3_2_mux_chain_enum = 718 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 719 rx_int_mix_mux_text); 720 721 static const struct soc_enum rx_int4_2_mux_chain_enum = 722 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 723 rx_int_mix_mux_text); 724 725 static const struct soc_enum rx_int5_2_mux_chain_enum = 726 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 727 rx_int_mix_mux_text); 728 729 static const struct soc_enum rx_int6_2_mux_chain_enum = 730 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 731 rx_int_mix_mux_text); 732 733 static const struct soc_enum rx_int7_2_mux_chain_enum = 734 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 735 rx_int0_7_mix_mux_text); 736 737 static const struct soc_enum rx_int8_2_mux_chain_enum = 738 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 739 rx_int_mix_mux_text); 740 741 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 742 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 743 rx_prim_mix_text); 744 745 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 746 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 747 rx_prim_mix_text); 748 749 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 750 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 751 rx_prim_mix_text); 752 753 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 754 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 755 rx_prim_mix_text); 756 757 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 758 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 759 rx_prim_mix_text); 760 761 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 762 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 763 rx_prim_mix_text); 764 765 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 766 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 767 rx_prim_mix_text); 768 769 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 770 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 771 rx_prim_mix_text); 772 773 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 774 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 775 rx_prim_mix_text); 776 777 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 778 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 779 rx_prim_mix_text); 780 781 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 782 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 783 rx_prim_mix_text); 784 785 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 786 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 787 rx_prim_mix_text); 788 789 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 790 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 791 rx_prim_mix_text); 792 793 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 794 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 795 rx_prim_mix_text); 796 797 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 798 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 799 rx_prim_mix_text); 800 801 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 802 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 803 rx_prim_mix_text); 804 805 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 806 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 807 rx_prim_mix_text); 808 809 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 810 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 811 rx_prim_mix_text); 812 813 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 814 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 815 rx_prim_mix_text); 816 817 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 818 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 819 rx_prim_mix_text); 820 821 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 822 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 823 rx_prim_mix_text); 824 825 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 826 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 827 rx_prim_mix_text); 828 829 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 830 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 831 rx_prim_mix_text); 832 833 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 834 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 835 rx_prim_mix_text); 836 837 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 838 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 839 rx_prim_mix_text); 840 841 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 842 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 843 rx_prim_mix_text); 844 845 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 846 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 847 rx_prim_mix_text); 848 849 static const struct soc_enum rx_int0_dem_inp_mux_enum = 850 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 851 ARRAY_SIZE(rx_int_dem_inp_mux_text), 852 rx_int_dem_inp_mux_text); 853 854 static const struct soc_enum rx_int1_dem_inp_mux_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 856 ARRAY_SIZE(rx_int_dem_inp_mux_text), 857 rx_int_dem_inp_mux_text); 858 859 static const struct soc_enum rx_int2_dem_inp_mux_enum = 860 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 861 ARRAY_SIZE(rx_int_dem_inp_mux_text), 862 rx_int_dem_inp_mux_text); 863 864 static const struct soc_enum rx_int0_interp_mux_enum = 865 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 866 rx_int0_interp_mux_text); 867 868 static const struct soc_enum rx_int1_interp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 870 rx_int1_interp_mux_text); 871 872 static const struct soc_enum rx_int2_interp_mux_enum = 873 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 874 rx_int2_interp_mux_text); 875 876 static const struct soc_enum rx_int3_interp_mux_enum = 877 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 878 rx_int3_interp_mux_text); 879 880 static const struct soc_enum rx_int4_interp_mux_enum = 881 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 882 rx_int4_interp_mux_text); 883 884 static const struct soc_enum rx_int5_interp_mux_enum = 885 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 886 rx_int5_interp_mux_text); 887 888 static const struct soc_enum rx_int6_interp_mux_enum = 889 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 890 rx_int6_interp_mux_text); 891 892 static const struct soc_enum rx_int7_interp_mux_enum = 893 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 894 rx_int7_interp_mux_text); 895 896 static const struct soc_enum rx_int8_interp_mux_enum = 897 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 898 rx_int8_interp_mux_text); 899 900 static const struct soc_enum tx_adc_mux0_chain_enum = 901 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 902 adc_mux_text); 903 904 static const struct soc_enum tx_adc_mux1_chain_enum = 905 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 906 adc_mux_text); 907 908 static const struct soc_enum tx_adc_mux2_chain_enum = 909 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 910 adc_mux_text); 911 912 static const struct soc_enum tx_adc_mux3_chain_enum = 913 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 914 adc_mux_text); 915 916 static const struct soc_enum tx_adc_mux4_chain_enum = 917 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 918 adc_mux_text); 919 920 static const struct soc_enum tx_adc_mux5_chain_enum = 921 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 922 adc_mux_text); 923 924 static const struct soc_enum tx_adc_mux6_chain_enum = 925 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 926 adc_mux_text); 927 928 static const struct soc_enum tx_adc_mux7_chain_enum = 929 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 930 adc_mux_text); 931 932 static const struct soc_enum tx_adc_mux8_chain_enum = 933 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 934 adc_mux_text); 935 936 static const struct soc_enum tx_dmic_mux0_enum = 937 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 938 dmic_mux_text); 939 940 static const struct soc_enum tx_dmic_mux1_enum = 941 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 942 dmic_mux_text); 943 944 static const struct soc_enum tx_dmic_mux2_enum = 945 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 946 dmic_mux_text); 947 948 static const struct soc_enum tx_dmic_mux3_enum = 949 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 950 dmic_mux_text); 951 952 static const struct soc_enum tx_dmic_mux4_enum = 953 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 954 dmic_mux_alt_text); 955 956 static const struct soc_enum tx_dmic_mux5_enum = 957 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 958 dmic_mux_alt_text); 959 960 static const struct soc_enum tx_dmic_mux6_enum = 961 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 962 dmic_mux_alt_text); 963 964 static const struct soc_enum tx_dmic_mux7_enum = 965 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 966 dmic_mux_alt_text); 967 968 static const struct soc_enum tx_dmic_mux8_enum = 969 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 970 dmic_mux_alt_text); 971 972 static const struct soc_enum tx_amic_mux0_enum = 973 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 974 amic_mux_text); 975 976 static const struct soc_enum tx_amic_mux1_enum = 977 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 978 amic_mux_text); 979 980 static const struct soc_enum tx_amic_mux2_enum = 981 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 982 amic_mux_text); 983 984 static const struct soc_enum tx_amic_mux3_enum = 985 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 986 amic_mux_text); 987 988 static const struct soc_enum tx_amic_mux4_enum = 989 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 990 amic_mux_text); 991 992 static const struct soc_enum tx_amic_mux5_enum = 993 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 994 amic_mux_text); 995 996 static const struct soc_enum tx_amic_mux6_enum = 997 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 998 amic_mux_text); 999 1000 static const struct soc_enum tx_amic_mux7_enum = 1001 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1002 amic_mux_text); 1003 1004 static const struct soc_enum tx_amic_mux8_enum = 1005 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1006 amic_mux_text); 1007 1008 static const struct soc_enum sb_tx0_mux_enum = 1009 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1010 sb_tx0_mux_text); 1011 1012 static const struct soc_enum sb_tx1_mux_enum = 1013 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1014 sb_tx1_mux_text); 1015 1016 static const struct soc_enum sb_tx2_mux_enum = 1017 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1018 sb_tx2_mux_text); 1019 1020 static const struct soc_enum sb_tx3_mux_enum = 1021 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1022 sb_tx3_mux_text); 1023 1024 static const struct soc_enum sb_tx4_mux_enum = 1025 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1026 sb_tx4_mux_text); 1027 1028 static const struct soc_enum sb_tx5_mux_enum = 1029 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1030 sb_tx5_mux_text); 1031 1032 static const struct soc_enum sb_tx6_mux_enum = 1033 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1034 sb_tx6_mux_text); 1035 1036 static const struct soc_enum sb_tx7_mux_enum = 1037 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1038 sb_tx7_mux_text); 1039 1040 static const struct soc_enum sb_tx8_mux_enum = 1041 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1042 sb_tx8_mux_text); 1043 1044 static const struct snd_kcontrol_new rx_int0_2_mux = 1045 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1046 1047 static const struct snd_kcontrol_new rx_int1_2_mux = 1048 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1049 1050 static const struct snd_kcontrol_new rx_int2_2_mux = 1051 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1052 1053 static const struct snd_kcontrol_new rx_int3_2_mux = 1054 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int4_2_mux = 1057 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int5_2_mux = 1060 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int6_2_mux = 1063 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int7_2_mux = 1066 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int8_2_mux = 1069 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1072 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int0_interp_mux = 1153 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1154 1155 static const struct snd_kcontrol_new rx_int1_interp_mux = 1156 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1157 1158 static const struct snd_kcontrol_new rx_int2_interp_mux = 1159 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1160 1161 static const struct snd_kcontrol_new rx_int3_interp_mux = 1162 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int4_interp_mux = 1165 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int5_interp_mux = 1168 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int6_interp_mux = 1171 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int7_interp_mux = 1174 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int8_interp_mux = 1177 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new tx_dmic_mux0 = 1180 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1181 1182 static const struct snd_kcontrol_new tx_dmic_mux1 = 1183 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1184 1185 static const struct snd_kcontrol_new tx_dmic_mux2 = 1186 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux3 = 1189 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux4 = 1192 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux5 = 1195 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux6 = 1198 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux7 = 1201 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux8 = 1204 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1205 1206 static const struct snd_kcontrol_new tx_amic_mux0 = 1207 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1208 1209 static const struct snd_kcontrol_new tx_amic_mux1 = 1210 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1211 1212 static const struct snd_kcontrol_new tx_amic_mux2 = 1213 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux3 = 1216 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux4 = 1219 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux5 = 1222 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux6 = 1225 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux7 = 1228 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux8 = 1231 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1232 1233 static const struct snd_kcontrol_new sb_tx0_mux = 1234 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1235 1236 static const struct snd_kcontrol_new sb_tx1_mux = 1237 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1238 1239 static const struct snd_kcontrol_new sb_tx2_mux = 1240 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx3_mux = 1243 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx4_mux = 1246 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx5_mux = 1249 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx6_mux = 1252 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx7_mux = 1255 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx8_mux = 1258 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1259 1260 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1261 struct snd_ctl_elem_value *ucontrol) 1262 { 1263 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1264 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1265 u32 port_id = w->shift; 1266 1267 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1268 1269 return 0; 1270 } 1271 1272 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1273 struct snd_ctl_elem_value *ucontrol) 1274 { 1275 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1276 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1277 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1278 struct snd_soc_dapm_update *update = NULL; 1279 u32 port_id = w->shift; 1280 1281 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1282 return 0; 1283 1284 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1285 1286 /* Remove channel from any list it's in before adding it to a new one */ 1287 list_del_init(&wcd->rx_chs[port_id].list); 1288 1289 switch (wcd->rx_port_value[port_id]) { 1290 case 0: 1291 /* Channel already removed from lists. Nothing to do here */ 1292 break; 1293 case 1: 1294 list_add_tail(&wcd->rx_chs[port_id].list, 1295 &wcd->dai[AIF1_PB].slim_ch_list); 1296 break; 1297 case 2: 1298 list_add_tail(&wcd->rx_chs[port_id].list, 1299 &wcd->dai[AIF2_PB].slim_ch_list); 1300 break; 1301 case 3: 1302 list_add_tail(&wcd->rx_chs[port_id].list, 1303 &wcd->dai[AIF3_PB].slim_ch_list); 1304 break; 1305 case 4: 1306 list_add_tail(&wcd->rx_chs[port_id].list, 1307 &wcd->dai[AIF4_PB].slim_ch_list); 1308 break; 1309 default: 1310 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1311 goto err; 1312 } 1313 1314 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1315 e, update); 1316 1317 return 0; 1318 err: 1319 return -EINVAL; 1320 } 1321 1322 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1323 struct snd_ctl_elem_value *ucontrol) 1324 { 1325 1326 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1327 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1328 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1329 struct soc_mixer_control *mixer = 1330 (struct soc_mixer_control *)kc->private_value; 1331 int dai_id = widget->shift; 1332 int port_id = mixer->shift; 1333 1334 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id; 1335 1336 return 0; 1337 } 1338 1339 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1340 struct snd_ctl_elem_value *ucontrol) 1341 { 1342 1343 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1344 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1345 struct snd_soc_dapm_update *update = NULL; 1346 struct soc_mixer_control *mixer = 1347 (struct soc_mixer_control *)kc->private_value; 1348 int enable = ucontrol->value.integer.value[0]; 1349 int dai_id = widget->shift; 1350 int port_id = mixer->shift; 1351 1352 switch (dai_id) { 1353 case AIF1_CAP: 1354 case AIF2_CAP: 1355 case AIF3_CAP: 1356 /* only add to the list if value not set */ 1357 if (enable && wcd->tx_port_value[port_id] != dai_id) { 1358 wcd->tx_port_value[port_id] = dai_id; 1359 list_add_tail(&wcd->tx_chs[port_id].list, 1360 &wcd->dai[dai_id].slim_ch_list); 1361 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) { 1362 wcd->tx_port_value[port_id] = -1; 1363 list_del_init(&wcd->tx_chs[port_id].list); 1364 } 1365 break; 1366 default: 1367 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1368 return -EINVAL; 1369 } 1370 1371 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1372 1373 return 0; 1374 } 1375 1376 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1377 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1378 slim_rx_mux_get, slim_rx_mux_put), 1379 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1380 slim_rx_mux_get, slim_rx_mux_put), 1381 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1382 slim_rx_mux_get, slim_rx_mux_put), 1383 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1384 slim_rx_mux_get, slim_rx_mux_put), 1385 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1386 slim_rx_mux_get, slim_rx_mux_put), 1387 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1388 slim_rx_mux_get, slim_rx_mux_put), 1389 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1390 slim_rx_mux_get, slim_rx_mux_put), 1391 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1392 slim_rx_mux_get, slim_rx_mux_put), 1393 }; 1394 1395 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1396 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1397 slim_tx_mixer_get, slim_tx_mixer_put), 1398 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1399 slim_tx_mixer_get, slim_tx_mixer_put), 1400 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1401 slim_tx_mixer_get, slim_tx_mixer_put), 1402 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1403 slim_tx_mixer_get, slim_tx_mixer_put), 1404 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1405 slim_tx_mixer_get, slim_tx_mixer_put), 1406 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1407 slim_tx_mixer_get, slim_tx_mixer_put), 1408 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1409 slim_tx_mixer_get, slim_tx_mixer_put), 1410 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1411 slim_tx_mixer_get, slim_tx_mixer_put), 1412 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1413 slim_tx_mixer_get, slim_tx_mixer_put), 1414 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1415 slim_tx_mixer_get, slim_tx_mixer_put), 1416 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1417 slim_tx_mixer_get, slim_tx_mixer_put), 1418 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1419 slim_tx_mixer_get, slim_tx_mixer_put), 1420 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1421 slim_tx_mixer_get, slim_tx_mixer_put), 1422 }; 1423 1424 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1425 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1426 slim_tx_mixer_get, slim_tx_mixer_put), 1427 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1428 slim_tx_mixer_get, slim_tx_mixer_put), 1429 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1432 slim_tx_mixer_get, slim_tx_mixer_put), 1433 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1434 slim_tx_mixer_get, slim_tx_mixer_put), 1435 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1436 slim_tx_mixer_get, slim_tx_mixer_put), 1437 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1438 slim_tx_mixer_get, slim_tx_mixer_put), 1439 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1440 slim_tx_mixer_get, slim_tx_mixer_put), 1441 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1442 slim_tx_mixer_get, slim_tx_mixer_put), 1443 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1444 slim_tx_mixer_get, slim_tx_mixer_put), 1445 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1446 slim_tx_mixer_get, slim_tx_mixer_put), 1447 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1448 slim_tx_mixer_get, slim_tx_mixer_put), 1449 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1450 slim_tx_mixer_get, slim_tx_mixer_put), 1451 }; 1452 1453 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1454 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1455 slim_tx_mixer_get, slim_tx_mixer_put), 1456 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1457 slim_tx_mixer_get, slim_tx_mixer_put), 1458 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1461 slim_tx_mixer_get, slim_tx_mixer_put), 1462 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1463 slim_tx_mixer_get, slim_tx_mixer_put), 1464 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1465 slim_tx_mixer_get, slim_tx_mixer_put), 1466 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1467 slim_tx_mixer_get, slim_tx_mixer_put), 1468 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1469 slim_tx_mixer_get, slim_tx_mixer_put), 1470 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1471 slim_tx_mixer_get, slim_tx_mixer_put), 1472 }; 1473 1474 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1475 struct snd_ctl_elem_value *ucontrol) 1476 { 1477 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1478 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1479 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1480 unsigned int val, reg, sel; 1481 1482 val = ucontrol->value.enumerated.item[0]; 1483 1484 switch (e->reg) { 1485 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1486 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1487 break; 1488 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1489 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1490 break; 1491 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1492 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1493 break; 1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1495 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1496 break; 1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1498 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1499 break; 1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1501 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1502 break; 1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1504 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1505 break; 1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1507 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1508 break; 1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1510 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1511 break; 1512 default: 1513 return -EINVAL; 1514 } 1515 1516 /* AMIC: 0, DMIC: 1 */ 1517 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1518 snd_soc_component_update_bits(component, reg, 1519 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1520 sel); 1521 1522 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1523 } 1524 1525 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1526 struct snd_ctl_elem_value *ucontrol) 1527 { 1528 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1529 struct snd_soc_component *component; 1530 int reg, val; 1531 1532 component = snd_soc_dapm_kcontrol_component(kc); 1533 val = ucontrol->value.enumerated.item[0]; 1534 1535 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1536 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1537 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1538 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1539 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1540 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1541 else 1542 return -EINVAL; 1543 1544 /* Set Look Ahead Delay */ 1545 snd_soc_component_update_bits(component, reg, 1546 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1547 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1548 /* Set DEM INP Select */ 1549 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1550 } 1551 1552 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1553 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1554 snd_soc_dapm_get_enum_double, 1555 wcd9335_int_dem_inp_mux_put); 1556 1557 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1558 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1559 snd_soc_dapm_get_enum_double, 1560 wcd9335_int_dem_inp_mux_put); 1561 1562 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1563 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1564 snd_soc_dapm_get_enum_double, 1565 wcd9335_int_dem_inp_mux_put); 1566 1567 static const struct snd_kcontrol_new tx_adc_mux0 = 1568 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1569 snd_soc_dapm_get_enum_double, 1570 wcd9335_put_dec_enum); 1571 1572 static const struct snd_kcontrol_new tx_adc_mux1 = 1573 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1574 snd_soc_dapm_get_enum_double, 1575 wcd9335_put_dec_enum); 1576 1577 static const struct snd_kcontrol_new tx_adc_mux2 = 1578 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1579 snd_soc_dapm_get_enum_double, 1580 wcd9335_put_dec_enum); 1581 1582 static const struct snd_kcontrol_new tx_adc_mux3 = 1583 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1584 snd_soc_dapm_get_enum_double, 1585 wcd9335_put_dec_enum); 1586 1587 static const struct snd_kcontrol_new tx_adc_mux4 = 1588 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1589 snd_soc_dapm_get_enum_double, 1590 wcd9335_put_dec_enum); 1591 1592 static const struct snd_kcontrol_new tx_adc_mux5 = 1593 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1594 snd_soc_dapm_get_enum_double, 1595 wcd9335_put_dec_enum); 1596 1597 static const struct snd_kcontrol_new tx_adc_mux6 = 1598 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1599 snd_soc_dapm_get_enum_double, 1600 wcd9335_put_dec_enum); 1601 1602 static const struct snd_kcontrol_new tx_adc_mux7 = 1603 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1604 snd_soc_dapm_get_enum_double, 1605 wcd9335_put_dec_enum); 1606 1607 static const struct snd_kcontrol_new tx_adc_mux8 = 1608 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1609 snd_soc_dapm_get_enum_double, 1610 wcd9335_put_dec_enum); 1611 1612 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1613 int rate_val, 1614 u32 rate) 1615 { 1616 struct snd_soc_component *component = dai->component; 1617 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1618 struct wcd9335_slim_ch *ch; 1619 int val, j; 1620 1621 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1622 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1623 val = snd_soc_component_read(component, 1624 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1625 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1626 1627 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1628 snd_soc_component_update_bits(component, 1629 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1630 WCD9335_CDC_MIX_PCM_RATE_MASK, 1631 rate_val); 1632 } 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1639 u8 rate_val, 1640 u32 rate) 1641 { 1642 struct snd_soc_component *comp = dai->component; 1643 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1644 struct wcd9335_slim_ch *ch; 1645 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1646 int inp, j; 1647 1648 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1649 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1650 /* 1651 * Loop through all interpolator MUX inputs and find out 1652 * to which interpolator input, the slim rx port 1653 * is connected 1654 */ 1655 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1656 cfg0 = snd_soc_component_read(comp, 1657 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1658 cfg1 = snd_soc_component_read(comp, 1659 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1660 1661 inp0_sel = cfg0 & 1662 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1663 inp1_sel = (cfg0 >> 4) & 1664 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1665 inp2_sel = (cfg1 >> 4) & 1666 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1667 1668 if ((inp0_sel == inp) || (inp1_sel == inp) || 1669 (inp2_sel == inp)) { 1670 /* rate is in Hz */ 1671 if ((j == 0) && (rate == 44100)) 1672 dev_info(wcd->dev, 1673 "Cannot set 44.1KHz on INT0\n"); 1674 else 1675 snd_soc_component_update_bits(comp, 1676 WCD9335_CDC_RX_PATH_CTL(j), 1677 WCD9335_CDC_MIX_PCM_RATE_MASK, 1678 rate_val); 1679 } 1680 } 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1687 { 1688 int i; 1689 1690 /* set mixing path rate */ 1691 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1692 if (rate == int_mix_rate_val[i].rate) { 1693 wcd9335_set_mix_interpolator_rate(dai, 1694 int_mix_rate_val[i].rate_val, rate); 1695 break; 1696 } 1697 } 1698 1699 /* set primary path sample rate */ 1700 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1701 if (rate == int_prim_rate_val[i].rate) { 1702 wcd9335_set_prim_interpolator_rate(dai, 1703 int_prim_rate_val[i].rate_val, rate); 1704 break; 1705 } 1706 } 1707 1708 return 0; 1709 } 1710 1711 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1712 struct wcd_slim_codec_dai_data *dai_data, 1713 int direction) 1714 { 1715 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1716 struct slim_stream_config *cfg = &dai_data->sconfig; 1717 struct wcd9335_slim_ch *ch; 1718 u16 payload = 0; 1719 int ret, i; 1720 1721 cfg->ch_count = 0; 1722 cfg->direction = direction; 1723 cfg->port_mask = 0; 1724 1725 /* Configure slave interface device */ 1726 list_for_each_entry(ch, slim_ch_list, list) { 1727 cfg->ch_count++; 1728 payload |= 1 << ch->shift; 1729 cfg->port_mask |= BIT(ch->port); 1730 } 1731 1732 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1733 if (!cfg->chs) 1734 return -ENOMEM; 1735 1736 i = 0; 1737 list_for_each_entry(ch, slim_ch_list, list) { 1738 cfg->chs[i++] = ch->ch_num; 1739 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1740 /* write to interface device */ 1741 ret = regmap_write(wcd->if_regmap, 1742 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1743 payload); 1744 1745 if (ret < 0) 1746 goto err; 1747 1748 /* configure the slave port for water mark and enable*/ 1749 ret = regmap_write(wcd->if_regmap, 1750 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1751 WCD9335_SLIM_WATER_MARK_VAL); 1752 if (ret < 0) 1753 goto err; 1754 } else { 1755 ret = regmap_write(wcd->if_regmap, 1756 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1757 payload & 0x00FF); 1758 if (ret < 0) 1759 goto err; 1760 1761 /* ports 8,9 */ 1762 ret = regmap_write(wcd->if_regmap, 1763 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1764 (payload & 0xFF00)>>8); 1765 if (ret < 0) 1766 goto err; 1767 1768 /* configure the slave port for water mark and enable*/ 1769 ret = regmap_write(wcd->if_regmap, 1770 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1771 WCD9335_SLIM_WATER_MARK_VAL); 1772 1773 if (ret < 0) 1774 goto err; 1775 } 1776 } 1777 1778 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1779 1780 return 0; 1781 1782 err: 1783 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1784 kfree(cfg->chs); 1785 cfg->chs = NULL; 1786 1787 return ret; 1788 } 1789 1790 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1791 u8 rate_val, u32 rate) 1792 { 1793 struct snd_soc_component *comp = dai->component; 1794 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1795 u8 shift = 0, shift_val = 0, tx_mux_sel; 1796 struct wcd9335_slim_ch *ch; 1797 int tx_port, tx_port_reg; 1798 int decimator = -1; 1799 1800 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1801 tx_port = ch->port; 1802 if ((tx_port == 12) || (tx_port >= 14)) { 1803 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1804 tx_port, dai->id); 1805 return -EINVAL; 1806 } 1807 /* Find the SB TX MUX input - which decimator is connected */ 1808 if (tx_port < 4) { 1809 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1810 shift = (tx_port << 1); 1811 shift_val = 0x03; 1812 } else if (tx_port < 8) { 1813 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1814 shift = ((tx_port - 4) << 1); 1815 shift_val = 0x03; 1816 } else if (tx_port < 11) { 1817 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1818 shift = ((tx_port - 8) << 1); 1819 shift_val = 0x03; 1820 } else if (tx_port == 11) { 1821 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1822 shift = 0; 1823 shift_val = 0x0F; 1824 } else if (tx_port == 13) { 1825 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1826 shift = 4; 1827 shift_val = 0x03; 1828 } else { 1829 return -EINVAL; 1830 } 1831 1832 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1833 (shift_val << shift); 1834 1835 tx_mux_sel = tx_mux_sel >> shift; 1836 if (tx_port <= 8) { 1837 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1838 decimator = tx_port; 1839 } else if (tx_port <= 10) { 1840 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1841 decimator = ((tx_port == 9) ? 7 : 6); 1842 } else if (tx_port == 11) { 1843 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1844 decimator = tx_mux_sel - 1; 1845 } else if (tx_port == 13) { 1846 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1847 decimator = 5; 1848 } 1849 1850 if (decimator >= 0) { 1851 snd_soc_component_update_bits(comp, 1852 WCD9335_CDC_TX_PATH_CTL(decimator), 1853 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1854 rate_val); 1855 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1856 /* Check if the TX Mux input is RX MIX TXn */ 1857 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1858 tx_port, tx_port); 1859 } else { 1860 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1861 decimator); 1862 return -EINVAL; 1863 } 1864 } 1865 1866 return 0; 1867 } 1868 1869 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1870 struct snd_pcm_hw_params *params, 1871 struct snd_soc_dai *dai) 1872 { 1873 struct wcd9335_codec *wcd; 1874 int ret, tx_fs_rate = 0; 1875 1876 wcd = snd_soc_component_get_drvdata(dai->component); 1877 1878 switch (substream->stream) { 1879 case SNDRV_PCM_STREAM_PLAYBACK: 1880 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1881 if (ret) { 1882 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1883 params_rate(params)); 1884 return ret; 1885 } 1886 switch (params_width(params)) { 1887 case 16 ... 24: 1888 wcd->dai[dai->id].sconfig.bps = params_width(params); 1889 break; 1890 default: 1891 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1892 __func__, params_width(params)); 1893 return -EINVAL; 1894 } 1895 break; 1896 1897 case SNDRV_PCM_STREAM_CAPTURE: 1898 switch (params_rate(params)) { 1899 case 8000: 1900 tx_fs_rate = 0; 1901 break; 1902 case 16000: 1903 tx_fs_rate = 1; 1904 break; 1905 case 32000: 1906 tx_fs_rate = 3; 1907 break; 1908 case 48000: 1909 tx_fs_rate = 4; 1910 break; 1911 case 96000: 1912 tx_fs_rate = 5; 1913 break; 1914 case 192000: 1915 tx_fs_rate = 6; 1916 break; 1917 case 384000: 1918 tx_fs_rate = 7; 1919 break; 1920 default: 1921 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1922 __func__, params_rate(params)); 1923 return -EINVAL; 1924 1925 } 1926 1927 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1928 params_rate(params)); 1929 if (ret < 0) { 1930 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1931 return ret; 1932 } 1933 switch (params_width(params)) { 1934 case 16 ... 32: 1935 wcd->dai[dai->id].sconfig.bps = params_width(params); 1936 break; 1937 default: 1938 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1939 __func__, params_width(params)); 1940 return -EINVAL; 1941 } 1942 break; 1943 default: 1944 dev_err(wcd->dev, "Invalid stream type %d\n", 1945 substream->stream); 1946 return -EINVAL; 1947 } 1948 1949 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1950 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1951 1952 return 0; 1953 } 1954 1955 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1956 struct snd_soc_dai *dai) 1957 { 1958 struct wcd_slim_codec_dai_data *dai_data; 1959 struct wcd9335_codec *wcd; 1960 struct slim_stream_config *cfg; 1961 1962 wcd = snd_soc_component_get_drvdata(dai->component); 1963 1964 dai_data = &wcd->dai[dai->id]; 1965 1966 switch (cmd) { 1967 case SNDRV_PCM_TRIGGER_START: 1968 case SNDRV_PCM_TRIGGER_RESUME: 1969 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1970 cfg = &dai_data->sconfig; 1971 slim_stream_prepare(dai_data->sruntime, cfg); 1972 slim_stream_enable(dai_data->sruntime); 1973 break; 1974 case SNDRV_PCM_TRIGGER_STOP: 1975 case SNDRV_PCM_TRIGGER_SUSPEND: 1976 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1977 slim_stream_unprepare(dai_data->sruntime); 1978 slim_stream_disable(dai_data->sruntime); 1979 break; 1980 default: 1981 break; 1982 } 1983 1984 return 0; 1985 } 1986 1987 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1988 unsigned int tx_num, unsigned int *tx_slot, 1989 unsigned int rx_num, unsigned int *rx_slot) 1990 { 1991 struct wcd9335_codec *wcd; 1992 int i; 1993 1994 wcd = snd_soc_component_get_drvdata(dai->component); 1995 1996 if (!tx_slot || !rx_slot) { 1997 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1998 tx_slot, rx_slot); 1999 return -EINVAL; 2000 } 2001 2002 wcd->num_rx_port = rx_num; 2003 for (i = 0; i < rx_num; i++) { 2004 wcd->rx_chs[i].ch_num = rx_slot[i]; 2005 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2006 } 2007 2008 wcd->num_tx_port = tx_num; 2009 for (i = 0; i < tx_num; i++) { 2010 wcd->tx_chs[i].ch_num = tx_slot[i]; 2011 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2012 } 2013 2014 return 0; 2015 } 2016 2017 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2018 unsigned int *tx_num, unsigned int *tx_slot, 2019 unsigned int *rx_num, unsigned int *rx_slot) 2020 { 2021 struct wcd9335_slim_ch *ch; 2022 struct wcd9335_codec *wcd; 2023 int i = 0; 2024 2025 wcd = snd_soc_component_get_drvdata(dai->component); 2026 2027 switch (dai->id) { 2028 case AIF1_PB: 2029 case AIF2_PB: 2030 case AIF3_PB: 2031 case AIF4_PB: 2032 if (!rx_slot || !rx_num) { 2033 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2034 rx_slot, rx_num); 2035 return -EINVAL; 2036 } 2037 2038 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2039 rx_slot[i++] = ch->ch_num; 2040 2041 *rx_num = i; 2042 break; 2043 case AIF1_CAP: 2044 case AIF2_CAP: 2045 case AIF3_CAP: 2046 if (!tx_slot || !tx_num) { 2047 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2048 tx_slot, tx_num); 2049 return -EINVAL; 2050 } 2051 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2052 tx_slot[i++] = ch->ch_num; 2053 2054 *tx_num = i; 2055 break; 2056 default: 2057 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2058 break; 2059 } 2060 2061 return 0; 2062 } 2063 2064 static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2065 .hw_params = wcd9335_hw_params, 2066 .trigger = wcd9335_trigger, 2067 .set_channel_map = wcd9335_set_channel_map, 2068 .get_channel_map = wcd9335_get_channel_map, 2069 }; 2070 2071 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2072 [0] = { 2073 .name = "wcd9335_rx1", 2074 .id = AIF1_PB, 2075 .playback = { 2076 .stream_name = "AIF1 Playback", 2077 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2078 SNDRV_PCM_RATE_384000, 2079 .formats = WCD9335_FORMATS_S16_S24_LE, 2080 .rate_max = 384000, 2081 .rate_min = 8000, 2082 .channels_min = 1, 2083 .channels_max = 2, 2084 }, 2085 .ops = &wcd9335_dai_ops, 2086 }, 2087 [1] = { 2088 .name = "wcd9335_tx1", 2089 .id = AIF1_CAP, 2090 .capture = { 2091 .stream_name = "AIF1 Capture", 2092 .rates = WCD9335_RATES_MASK, 2093 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2094 .rate_min = 8000, 2095 .rate_max = 192000, 2096 .channels_min = 1, 2097 .channels_max = 4, 2098 }, 2099 .ops = &wcd9335_dai_ops, 2100 }, 2101 [2] = { 2102 .name = "wcd9335_rx2", 2103 .id = AIF2_PB, 2104 .playback = { 2105 .stream_name = "AIF2 Playback", 2106 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2107 SNDRV_PCM_RATE_384000, 2108 .formats = WCD9335_FORMATS_S16_S24_LE, 2109 .rate_min = 8000, 2110 .rate_max = 384000, 2111 .channels_min = 1, 2112 .channels_max = 2, 2113 }, 2114 .ops = &wcd9335_dai_ops, 2115 }, 2116 [3] = { 2117 .name = "wcd9335_tx2", 2118 .id = AIF2_CAP, 2119 .capture = { 2120 .stream_name = "AIF2 Capture", 2121 .rates = WCD9335_RATES_MASK, 2122 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2123 .rate_min = 8000, 2124 .rate_max = 192000, 2125 .channels_min = 1, 2126 .channels_max = 4, 2127 }, 2128 .ops = &wcd9335_dai_ops, 2129 }, 2130 [4] = { 2131 .name = "wcd9335_rx3", 2132 .id = AIF3_PB, 2133 .playback = { 2134 .stream_name = "AIF3 Playback", 2135 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2136 SNDRV_PCM_RATE_384000, 2137 .formats = WCD9335_FORMATS_S16_S24_LE, 2138 .rate_min = 8000, 2139 .rate_max = 384000, 2140 .channels_min = 1, 2141 .channels_max = 2, 2142 }, 2143 .ops = &wcd9335_dai_ops, 2144 }, 2145 [5] = { 2146 .name = "wcd9335_tx3", 2147 .id = AIF3_CAP, 2148 .capture = { 2149 .stream_name = "AIF3 Capture", 2150 .rates = WCD9335_RATES_MASK, 2151 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2152 .rate_min = 8000, 2153 .rate_max = 192000, 2154 .channels_min = 1, 2155 .channels_max = 4, 2156 }, 2157 .ops = &wcd9335_dai_ops, 2158 }, 2159 [6] = { 2160 .name = "wcd9335_rx4", 2161 .id = AIF4_PB, 2162 .playback = { 2163 .stream_name = "AIF4 Playback", 2164 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2165 SNDRV_PCM_RATE_384000, 2166 .formats = WCD9335_FORMATS_S16_S24_LE, 2167 .rate_min = 8000, 2168 .rate_max = 384000, 2169 .channels_min = 1, 2170 .channels_max = 2, 2171 }, 2172 .ops = &wcd9335_dai_ops, 2173 }, 2174 }; 2175 2176 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2177 struct snd_ctl_elem_value *ucontrol) 2178 { 2179 2180 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2181 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2182 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2183 2184 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2185 return 0; 2186 } 2187 2188 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2189 struct snd_ctl_elem_value *ucontrol) 2190 { 2191 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2192 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2193 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2194 int value = ucontrol->value.integer.value[0]; 2195 int sel; 2196 2197 wcd->comp_enabled[comp] = value; 2198 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2199 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2200 2201 /* Any specific register configuration for compander */ 2202 switch (comp) { 2203 case COMPANDER_1: 2204 /* Set Gain Source Select based on compander enable/disable */ 2205 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2206 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2207 break; 2208 case COMPANDER_2: 2209 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2210 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2211 break; 2212 case COMPANDER_5: 2213 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2214 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2215 break; 2216 case COMPANDER_6: 2217 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2218 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2219 break; 2220 default: 2221 break; 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2228 struct snd_ctl_elem_value *ucontrol) 2229 { 2230 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2231 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2232 2233 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2234 2235 return 0; 2236 } 2237 2238 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2239 struct snd_ctl_elem_value *ucontrol) 2240 { 2241 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2242 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2243 u32 mode_val; 2244 2245 mode_val = ucontrol->value.enumerated.item[0]; 2246 2247 if (mode_val == 0) { 2248 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2249 mode_val = CLS_H_HIFI; 2250 } 2251 wcd->hph_mode = mode_val; 2252 2253 return 0; 2254 } 2255 2256 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2257 /* -84dB min - 40dB max */ 2258 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2259 -84, 40, digital_gain), 2260 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2261 -84, 40, digital_gain), 2262 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2263 -84, 40, digital_gain), 2264 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2265 -84, 40, digital_gain), 2266 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2267 -84, 40, digital_gain), 2268 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2269 -84, 40, digital_gain), 2270 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2271 -84, 40, digital_gain), 2272 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2273 -84, 40, digital_gain), 2274 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2275 -84, 40, digital_gain), 2276 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2277 -84, 40, digital_gain), 2278 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2279 -84, 40, digital_gain), 2280 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2281 -84, 40, digital_gain), 2282 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2283 -84, 40, digital_gain), 2284 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2285 -84, 40, digital_gain), 2286 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2287 -84, 40, digital_gain), 2288 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2289 -84, 40, digital_gain), 2290 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2291 -84, 40, digital_gain), 2292 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2293 -84, 40, digital_gain), 2294 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2295 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2296 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2297 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2298 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2299 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2300 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2301 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2302 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2303 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2304 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2305 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2306 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2307 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2308 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2309 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2310 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2311 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2312 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2313 wcd9335_get_compander, wcd9335_set_compander), 2314 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2315 wcd9335_get_compander, wcd9335_set_compander), 2316 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2317 wcd9335_get_compander, wcd9335_set_compander), 2318 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2319 wcd9335_get_compander, wcd9335_set_compander), 2320 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2321 wcd9335_get_compander, wcd9335_set_compander), 2322 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2323 wcd9335_get_compander, wcd9335_set_compander), 2324 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2325 wcd9335_get_compander, wcd9335_set_compander), 2326 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2327 wcd9335_get_compander, wcd9335_set_compander), 2328 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2329 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2330 2331 /* Gain Controls */ 2332 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2333 ear_pa_gain), 2334 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2335 line_gain), 2336 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2337 line_gain), 2338 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2339 3, 16, 1, line_gain), 2340 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2341 3, 16, 1, line_gain), 2342 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2343 line_gain), 2344 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2345 line_gain), 2346 2347 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2348 analog_gain), 2349 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2350 analog_gain), 2351 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2352 analog_gain), 2353 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2354 analog_gain), 2355 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2356 analog_gain), 2357 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2358 analog_gain), 2359 2360 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2361 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2362 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2363 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2364 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2365 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2366 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2367 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2368 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2369 }; 2370 2371 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2372 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2373 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2374 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2375 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2376 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2377 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2378 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2379 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2380 2381 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2382 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2383 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2384 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2385 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2386 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2387 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2388 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2389 2390 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2391 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2392 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2393 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2394 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2395 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2396 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2397 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2398 2399 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2400 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2401 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2402 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2403 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2404 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2405 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2406 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2407 2408 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2409 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2410 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2411 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2412 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2413 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2414 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2415 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2416 2417 WCD9335_INTERPOLATOR_PATH(0), 2418 WCD9335_INTERPOLATOR_PATH(1), 2419 WCD9335_INTERPOLATOR_PATH(2), 2420 WCD9335_INTERPOLATOR_PATH(3), 2421 WCD9335_INTERPOLATOR_PATH(4), 2422 WCD9335_INTERPOLATOR_PATH(5), 2423 WCD9335_INTERPOLATOR_PATH(6), 2424 WCD9335_INTERPOLATOR_PATH(7), 2425 WCD9335_INTERPOLATOR_PATH(8), 2426 2427 /* EAR PA */ 2428 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2429 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2430 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2431 {"EAR PA", NULL, "RX INT0 DAC"}, 2432 {"EAR", NULL, "EAR PA"}, 2433 2434 /* HPHL */ 2435 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2436 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2437 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2438 {"HPHL PA", NULL, "RX INT1 DAC"}, 2439 {"HPHL", NULL, "HPHL PA"}, 2440 2441 /* HPHR */ 2442 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2443 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2444 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2445 {"HPHR PA", NULL, "RX INT2 DAC"}, 2446 {"HPHR", NULL, "HPHR PA"}, 2447 2448 /* LINEOUT1 */ 2449 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2450 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2451 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2452 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2453 2454 /* LINEOUT2 */ 2455 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2456 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2457 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2458 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2459 2460 /* LINEOUT3 */ 2461 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2462 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2463 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2464 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2465 2466 /* LINEOUT4 */ 2467 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2468 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2469 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2470 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2471 2472 /* SLIMBUS Connections */ 2473 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2474 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2475 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2476 2477 /* ADC Mux */ 2478 WCD9335_ADC_MUX_PATH(0), 2479 WCD9335_ADC_MUX_PATH(1), 2480 WCD9335_ADC_MUX_PATH(2), 2481 WCD9335_ADC_MUX_PATH(3), 2482 WCD9335_ADC_MUX_PATH(4), 2483 WCD9335_ADC_MUX_PATH(5), 2484 WCD9335_ADC_MUX_PATH(6), 2485 WCD9335_ADC_MUX_PATH(7), 2486 WCD9335_ADC_MUX_PATH(8), 2487 2488 /* ADC Connections */ 2489 {"ADC1", NULL, "AMIC1"}, 2490 {"ADC2", NULL, "AMIC2"}, 2491 {"ADC3", NULL, "AMIC3"}, 2492 {"ADC4", NULL, "AMIC4"}, 2493 {"ADC5", NULL, "AMIC5"}, 2494 {"ADC6", NULL, "AMIC6"}, 2495 }; 2496 2497 static int wcd9335_micbias_control(struct snd_soc_component *component, 2498 int micb_num, int req, bool is_dapm) 2499 { 2500 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2501 int micb_index = micb_num - 1; 2502 u16 micb_reg; 2503 2504 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2505 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2506 micb_index); 2507 return -EINVAL; 2508 } 2509 2510 switch (micb_num) { 2511 case MIC_BIAS_1: 2512 micb_reg = WCD9335_ANA_MICB1; 2513 break; 2514 case MIC_BIAS_2: 2515 micb_reg = WCD9335_ANA_MICB2; 2516 break; 2517 case MIC_BIAS_3: 2518 micb_reg = WCD9335_ANA_MICB3; 2519 break; 2520 case MIC_BIAS_4: 2521 micb_reg = WCD9335_ANA_MICB4; 2522 break; 2523 default: 2524 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2525 __func__, micb_num); 2526 return -EINVAL; 2527 } 2528 2529 switch (req) { 2530 case MICB_PULLUP_ENABLE: 2531 wcd->pullup_ref[micb_index]++; 2532 if ((wcd->pullup_ref[micb_index] == 1) && 2533 (wcd->micb_ref[micb_index] == 0)) 2534 snd_soc_component_update_bits(component, micb_reg, 2535 0xC0, 0x80); 2536 break; 2537 case MICB_PULLUP_DISABLE: 2538 wcd->pullup_ref[micb_index]--; 2539 if ((wcd->pullup_ref[micb_index] == 0) && 2540 (wcd->micb_ref[micb_index] == 0)) 2541 snd_soc_component_update_bits(component, micb_reg, 2542 0xC0, 0x00); 2543 break; 2544 case MICB_ENABLE: 2545 wcd->micb_ref[micb_index]++; 2546 if (wcd->micb_ref[micb_index] == 1) 2547 snd_soc_component_update_bits(component, micb_reg, 2548 0xC0, 0x40); 2549 break; 2550 case MICB_DISABLE: 2551 wcd->micb_ref[micb_index]--; 2552 if ((wcd->micb_ref[micb_index] == 0) && 2553 (wcd->pullup_ref[micb_index] > 0)) 2554 snd_soc_component_update_bits(component, micb_reg, 2555 0xC0, 0x80); 2556 else if ((wcd->micb_ref[micb_index] == 0) && 2557 (wcd->pullup_ref[micb_index] == 0)) { 2558 snd_soc_component_update_bits(component, micb_reg, 2559 0xC0, 0x00); 2560 } 2561 break; 2562 } 2563 2564 return 0; 2565 } 2566 2567 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2568 int event) 2569 { 2570 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2571 int micb_num; 2572 2573 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2574 micb_num = MIC_BIAS_1; 2575 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2576 micb_num = MIC_BIAS_2; 2577 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2578 micb_num = MIC_BIAS_3; 2579 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2580 micb_num = MIC_BIAS_4; 2581 else 2582 return -EINVAL; 2583 2584 switch (event) { 2585 case SND_SOC_DAPM_PRE_PMU: 2586 /* 2587 * MIC BIAS can also be requested by MBHC, 2588 * so use ref count to handle micbias pullup 2589 * and enable requests 2590 */ 2591 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2592 break; 2593 case SND_SOC_DAPM_POST_PMU: 2594 /* wait for cnp time */ 2595 usleep_range(1000, 1100); 2596 break; 2597 case SND_SOC_DAPM_POST_PMD: 2598 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2599 break; 2600 } 2601 2602 return 0; 2603 } 2604 2605 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2606 struct snd_kcontrol *kc, int event) 2607 { 2608 return __wcd9335_codec_enable_micbias(w, event); 2609 } 2610 2611 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2612 u16 amic_reg, bool set) 2613 { 2614 u8 mask = 0x20; 2615 u8 val; 2616 2617 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2618 amic_reg == WCD9335_ANA_AMIC5) 2619 mask = 0x40; 2620 2621 val = set ? mask : 0x00; 2622 2623 switch (amic_reg) { 2624 case WCD9335_ANA_AMIC1: 2625 case WCD9335_ANA_AMIC2: 2626 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2627 val); 2628 break; 2629 case WCD9335_ANA_AMIC3: 2630 case WCD9335_ANA_AMIC4: 2631 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2632 val); 2633 break; 2634 case WCD9335_ANA_AMIC5: 2635 case WCD9335_ANA_AMIC6: 2636 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2637 val); 2638 break; 2639 default: 2640 dev_err(comp->dev, "%s: invalid amic: %d\n", 2641 __func__, amic_reg); 2642 break; 2643 } 2644 } 2645 2646 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2647 struct snd_kcontrol *kc, int event) 2648 { 2649 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2650 2651 switch (event) { 2652 case SND_SOC_DAPM_PRE_PMU: 2653 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2654 break; 2655 default: 2656 break; 2657 } 2658 2659 return 0; 2660 } 2661 2662 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2663 int adc_mux_n) 2664 { 2665 int mux_sel, reg, mreg; 2666 2667 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2668 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2669 return 0; 2670 2671 /* Check whether adc mux input is AMIC or DMIC */ 2672 if (adc_mux_n < 4) { 2673 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2674 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2675 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2676 } else { 2677 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2678 mreg = reg; 2679 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2680 } 2681 2682 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2683 return 0; 2684 2685 return snd_soc_component_read(comp, mreg) & 0x07; 2686 } 2687 2688 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2689 int amic) 2690 { 2691 u16 pwr_level_reg = 0; 2692 2693 switch (amic) { 2694 case 1: 2695 case 2: 2696 pwr_level_reg = WCD9335_ANA_AMIC1; 2697 break; 2698 2699 case 3: 2700 case 4: 2701 pwr_level_reg = WCD9335_ANA_AMIC3; 2702 break; 2703 2704 case 5: 2705 case 6: 2706 pwr_level_reg = WCD9335_ANA_AMIC5; 2707 break; 2708 default: 2709 dev_err(comp->dev, "invalid amic: %d\n", amic); 2710 break; 2711 } 2712 2713 return pwr_level_reg; 2714 } 2715 2716 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2717 struct snd_kcontrol *kc, int event) 2718 { 2719 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2720 unsigned int decimator; 2721 char *dec_adc_mux_name = NULL; 2722 char *widget_name = NULL; 2723 char *wname; 2724 int ret = 0, amic_n; 2725 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2726 u16 tx_gain_ctl_reg; 2727 char *dec; 2728 u8 hpf_coff_freq; 2729 2730 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2731 if (!widget_name) 2732 return -ENOMEM; 2733 2734 wname = widget_name; 2735 dec_adc_mux_name = strsep(&widget_name, " "); 2736 if (!dec_adc_mux_name) { 2737 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2738 __func__, w->name); 2739 ret = -EINVAL; 2740 goto out; 2741 } 2742 dec_adc_mux_name = widget_name; 2743 2744 dec = strpbrk(dec_adc_mux_name, "012345678"); 2745 if (!dec) { 2746 dev_err(comp->dev, "%s: decimator index not found\n", 2747 __func__); 2748 ret = -EINVAL; 2749 goto out; 2750 } 2751 2752 ret = kstrtouint(dec, 10, &decimator); 2753 if (ret < 0) { 2754 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2755 __func__, wname); 2756 ret = -EINVAL; 2757 goto out; 2758 } 2759 2760 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2761 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2762 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2763 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2764 2765 switch (event) { 2766 case SND_SOC_DAPM_PRE_PMU: 2767 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2768 if (amic_n) 2769 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2770 amic_n); 2771 2772 if (pwr_level_reg) { 2773 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2774 WCD9335_AMIC_PWR_LVL_MASK) >> 2775 WCD9335_AMIC_PWR_LVL_SHIFT) { 2776 case WCD9335_AMIC_PWR_LEVEL_LP: 2777 snd_soc_component_update_bits(comp, dec_cfg_reg, 2778 WCD9335_DEC_PWR_LVL_MASK, 2779 WCD9335_DEC_PWR_LVL_LP); 2780 break; 2781 2782 case WCD9335_AMIC_PWR_LEVEL_HP: 2783 snd_soc_component_update_bits(comp, dec_cfg_reg, 2784 WCD9335_DEC_PWR_LVL_MASK, 2785 WCD9335_DEC_PWR_LVL_HP); 2786 break; 2787 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2788 default: 2789 snd_soc_component_update_bits(comp, dec_cfg_reg, 2790 WCD9335_DEC_PWR_LVL_MASK, 2791 WCD9335_DEC_PWR_LVL_DF); 2792 break; 2793 } 2794 } 2795 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2796 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2797 2798 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2799 snd_soc_component_update_bits(comp, dec_cfg_reg, 2800 TX_HPF_CUT_OFF_FREQ_MASK, 2801 CF_MIN_3DB_150HZ << 5); 2802 /* Enable TX PGA Mute */ 2803 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2804 0x10, 0x10); 2805 /* Enable APC */ 2806 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2807 break; 2808 case SND_SOC_DAPM_POST_PMU: 2809 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2810 2811 if (decimator == 0) { 2812 snd_soc_component_write(comp, 2813 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2814 snd_soc_component_write(comp, 2815 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2816 snd_soc_component_write(comp, 2817 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2818 snd_soc_component_write(comp, 2819 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2820 } 2821 2822 snd_soc_component_update_bits(comp, hpf_gate_reg, 2823 0x01, 0x01); 2824 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2825 0x10, 0x00); 2826 snd_soc_component_write(comp, tx_gain_ctl_reg, 2827 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2828 break; 2829 case SND_SOC_DAPM_PRE_PMD: 2830 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2831 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2832 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2833 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2834 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2835 snd_soc_component_update_bits(comp, dec_cfg_reg, 2836 TX_HPF_CUT_OFF_FREQ_MASK, 2837 hpf_coff_freq << 5); 2838 } 2839 break; 2840 case SND_SOC_DAPM_POST_PMD: 2841 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2842 break; 2843 } 2844 out: 2845 kfree(wname); 2846 return ret; 2847 } 2848 2849 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2850 u32 mclk_rate, u32 dmic_clk_rate) 2851 { 2852 u32 div_factor; 2853 u8 dmic_ctl_val; 2854 2855 dev_err(component->dev, 2856 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2857 __func__, mclk_rate, dmic_clk_rate); 2858 2859 /* Default value to return in case of error */ 2860 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2861 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2862 else 2863 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2864 2865 if (dmic_clk_rate == 0) { 2866 dev_err(component->dev, 2867 "%s: dmic_sample_rate cannot be 0\n", 2868 __func__); 2869 goto done; 2870 } 2871 2872 div_factor = mclk_rate / dmic_clk_rate; 2873 switch (div_factor) { 2874 case 2: 2875 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2876 break; 2877 case 3: 2878 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2879 break; 2880 case 4: 2881 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2882 break; 2883 case 6: 2884 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2885 break; 2886 case 8: 2887 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2888 break; 2889 case 16: 2890 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2891 break; 2892 default: 2893 dev_err(component->dev, 2894 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2895 __func__, div_factor, mclk_rate, dmic_clk_rate); 2896 break; 2897 } 2898 2899 done: 2900 return dmic_ctl_val; 2901 } 2902 2903 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2904 struct snd_kcontrol *kc, int event) 2905 { 2906 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2907 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2908 u8 dmic_clk_en = 0x01; 2909 u16 dmic_clk_reg; 2910 s32 *dmic_clk_cnt; 2911 u8 dmic_rate_val, dmic_rate_shift = 1; 2912 unsigned int dmic; 2913 int ret; 2914 char *wname; 2915 2916 wname = strpbrk(w->name, "012345"); 2917 if (!wname) { 2918 dev_err(comp->dev, "%s: widget not found\n", __func__); 2919 return -EINVAL; 2920 } 2921 2922 ret = kstrtouint(wname, 10, &dmic); 2923 if (ret < 0) { 2924 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2925 __func__); 2926 return -EINVAL; 2927 } 2928 2929 switch (dmic) { 2930 case 0: 2931 case 1: 2932 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2933 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2934 break; 2935 case 2: 2936 case 3: 2937 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2938 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2939 break; 2940 case 4: 2941 case 5: 2942 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2943 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2944 break; 2945 default: 2946 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2947 __func__); 2948 return -EINVAL; 2949 } 2950 2951 switch (event) { 2952 case SND_SOC_DAPM_PRE_PMU: 2953 dmic_rate_val = 2954 wcd9335_get_dmic_clk_val(comp, 2955 wcd->mclk_rate, 2956 wcd->dmic_sample_rate); 2957 2958 (*dmic_clk_cnt)++; 2959 if (*dmic_clk_cnt == 1) { 2960 snd_soc_component_update_bits(comp, dmic_clk_reg, 2961 0x07 << dmic_rate_shift, 2962 dmic_rate_val << dmic_rate_shift); 2963 snd_soc_component_update_bits(comp, dmic_clk_reg, 2964 dmic_clk_en, dmic_clk_en); 2965 } 2966 2967 break; 2968 case SND_SOC_DAPM_POST_PMD: 2969 dmic_rate_val = 2970 wcd9335_get_dmic_clk_val(comp, 2971 wcd->mclk_rate, 2972 wcd->mad_dmic_sample_rate); 2973 (*dmic_clk_cnt)--; 2974 if (*dmic_clk_cnt == 0) { 2975 snd_soc_component_update_bits(comp, dmic_clk_reg, 2976 dmic_clk_en, 0); 2977 snd_soc_component_update_bits(comp, dmic_clk_reg, 2978 0x07 << dmic_rate_shift, 2979 dmic_rate_val << dmic_rate_shift); 2980 } 2981 break; 2982 } 2983 2984 return 0; 2985 } 2986 2987 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2988 struct snd_soc_component *component) 2989 { 2990 int port_num = 0; 2991 unsigned short reg = 0; 2992 unsigned int val = 0; 2993 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2994 struct wcd9335_slim_ch *ch; 2995 2996 list_for_each_entry(ch, &dai->slim_ch_list, list) { 2997 if (ch->port >= WCD9335_RX_START) { 2998 port_num = ch->port - WCD9335_RX_START; 2999 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 3000 } else { 3001 port_num = ch->port; 3002 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3003 } 3004 3005 regmap_read(wcd->if_regmap, reg, &val); 3006 if (!(val & BIT(port_num % 8))) 3007 regmap_write(wcd->if_regmap, reg, 3008 val | BIT(port_num % 8)); 3009 } 3010 } 3011 3012 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3013 struct snd_kcontrol *kc, 3014 int event) 3015 { 3016 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3017 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3018 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3019 3020 switch (event) { 3021 case SND_SOC_DAPM_POST_PMU: 3022 wcd9335_codec_enable_int_port(dai, comp); 3023 break; 3024 case SND_SOC_DAPM_POST_PMD: 3025 kfree(dai->sconfig.chs); 3026 3027 break; 3028 } 3029 3030 return 0; 3031 } 3032 3033 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3034 struct snd_kcontrol *kc, int event) 3035 { 3036 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3037 u16 gain_reg; 3038 int offset_val = 0; 3039 int val = 0; 3040 3041 switch (w->reg) { 3042 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3043 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3044 break; 3045 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3046 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3047 break; 3048 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3049 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3050 break; 3051 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3052 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3053 break; 3054 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3055 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3056 break; 3057 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3058 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3059 break; 3060 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3061 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3062 break; 3063 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3064 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3065 break; 3066 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3067 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3068 break; 3069 default: 3070 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3071 __func__, w->name); 3072 return 0; 3073 } 3074 3075 switch (event) { 3076 case SND_SOC_DAPM_POST_PMU: 3077 val = snd_soc_component_read(comp, gain_reg); 3078 val += offset_val; 3079 snd_soc_component_write(comp, gain_reg, val); 3080 break; 3081 case SND_SOC_DAPM_POST_PMD: 3082 break; 3083 } 3084 3085 return 0; 3086 } 3087 3088 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3089 { 3090 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3091 3092 switch (reg) { 3093 case WCD9335_CDC_RX0_RX_PATH_CTL: 3094 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3095 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3096 *ind = 0; 3097 break; 3098 case WCD9335_CDC_RX1_RX_PATH_CTL: 3099 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3100 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3101 *ind = 1; 3102 break; 3103 case WCD9335_CDC_RX2_RX_PATH_CTL: 3104 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3105 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3106 *ind = 2; 3107 break; 3108 case WCD9335_CDC_RX3_RX_PATH_CTL: 3109 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3110 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3111 *ind = 3; 3112 break; 3113 case WCD9335_CDC_RX4_RX_PATH_CTL: 3114 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3115 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3116 *ind = 4; 3117 break; 3118 case WCD9335_CDC_RX5_RX_PATH_CTL: 3119 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3120 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3121 *ind = 5; 3122 break; 3123 case WCD9335_CDC_RX6_RX_PATH_CTL: 3124 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3125 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3126 *ind = 6; 3127 break; 3128 case WCD9335_CDC_RX7_RX_PATH_CTL: 3129 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3130 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3131 *ind = 7; 3132 break; 3133 case WCD9335_CDC_RX8_RX_PATH_CTL: 3134 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3135 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3136 *ind = 8; 3137 break; 3138 } 3139 3140 return prim_int_reg; 3141 } 3142 3143 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3144 u16 prim_int_reg, int event) 3145 { 3146 u16 hd2_scale_reg; 3147 u16 hd2_enable_reg = 0; 3148 3149 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3150 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3151 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3152 } 3153 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3154 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3155 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3156 } 3157 3158 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3159 snd_soc_component_update_bits(component, hd2_scale_reg, 3160 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3161 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3162 snd_soc_component_update_bits(component, hd2_scale_reg, 3163 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3164 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3165 snd_soc_component_update_bits(component, hd2_enable_reg, 3166 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3167 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3168 } 3169 3170 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3171 snd_soc_component_update_bits(component, hd2_enable_reg, 3172 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3173 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3174 snd_soc_component_update_bits(component, hd2_scale_reg, 3175 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3176 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3177 snd_soc_component_update_bits(component, hd2_scale_reg, 3178 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3179 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3180 } 3181 } 3182 3183 static int wcd9335_codec_enable_prim_interpolator( 3184 struct snd_soc_component *comp, 3185 u16 reg, int event) 3186 { 3187 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3188 u16 ind = 0; 3189 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3190 3191 switch (event) { 3192 case SND_SOC_DAPM_PRE_PMU: 3193 wcd->prim_int_users[ind]++; 3194 if (wcd->prim_int_users[ind] == 1) { 3195 snd_soc_component_update_bits(comp, prim_int_reg, 3196 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3197 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3198 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3199 snd_soc_component_update_bits(comp, prim_int_reg, 3200 WCD9335_CDC_RX_CLK_EN_MASK, 3201 WCD9335_CDC_RX_CLK_ENABLE); 3202 } 3203 3204 if ((reg != prim_int_reg) && 3205 ((snd_soc_component_read(comp, prim_int_reg)) & 3206 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3207 snd_soc_component_update_bits(comp, reg, 3208 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3209 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3210 break; 3211 case SND_SOC_DAPM_POST_PMD: 3212 wcd->prim_int_users[ind]--; 3213 if (wcd->prim_int_users[ind] == 0) { 3214 snd_soc_component_update_bits(comp, prim_int_reg, 3215 WCD9335_CDC_RX_CLK_EN_MASK, 3216 WCD9335_CDC_RX_CLK_DISABLE); 3217 snd_soc_component_update_bits(comp, prim_int_reg, 3218 WCD9335_CDC_RX_RESET_MASK, 3219 WCD9335_CDC_RX_RESET_ENABLE); 3220 snd_soc_component_update_bits(comp, prim_int_reg, 3221 WCD9335_CDC_RX_RESET_MASK, 3222 WCD9335_CDC_RX_RESET_DISABLE); 3223 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3224 } 3225 break; 3226 } 3227 3228 return 0; 3229 } 3230 3231 static int wcd9335_config_compander(struct snd_soc_component *component, 3232 int interp_n, int event) 3233 { 3234 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3235 int comp; 3236 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3237 3238 /* EAR does not have compander */ 3239 if (!interp_n) 3240 return 0; 3241 3242 comp = interp_n - 1; 3243 if (!wcd->comp_enabled[comp]) 3244 return 0; 3245 3246 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3247 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3248 3249 if (SND_SOC_DAPM_EVENT_ON(event)) { 3250 /* Enable Compander Clock */ 3251 snd_soc_component_update_bits(component, comp_ctl0_reg, 3252 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3253 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3254 /* Reset comander */ 3255 snd_soc_component_update_bits(component, comp_ctl0_reg, 3256 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3257 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3258 snd_soc_component_update_bits(component, comp_ctl0_reg, 3259 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3260 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3261 /* Enables DRE in this path */ 3262 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3263 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3264 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3265 } 3266 3267 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3268 snd_soc_component_update_bits(component, comp_ctl0_reg, 3269 WCD9335_CDC_COMPANDER_HALT_MASK, 3270 WCD9335_CDC_COMPANDER_HALT); 3271 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3272 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3273 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3274 3275 snd_soc_component_update_bits(component, comp_ctl0_reg, 3276 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3277 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3278 snd_soc_component_update_bits(component, comp_ctl0_reg, 3279 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3280 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3281 snd_soc_component_update_bits(component, comp_ctl0_reg, 3282 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3283 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3284 snd_soc_component_update_bits(component, comp_ctl0_reg, 3285 WCD9335_CDC_COMPANDER_HALT_MASK, 3286 WCD9335_CDC_COMPANDER_NOHALT); 3287 } 3288 3289 return 0; 3290 } 3291 3292 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3293 struct snd_kcontrol *kc, int event) 3294 { 3295 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3296 u16 gain_reg; 3297 u16 reg; 3298 int val; 3299 int offset_val = 0; 3300 3301 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3302 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3303 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3304 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3305 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3306 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3307 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3308 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3309 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3310 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3311 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3312 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3313 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3314 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3315 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3316 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3317 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3318 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3319 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3320 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3321 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3322 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3323 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3324 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3325 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3326 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3327 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3328 } else { 3329 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3330 __func__); 3331 return -EINVAL; 3332 } 3333 3334 switch (event) { 3335 case SND_SOC_DAPM_PRE_PMU: 3336 /* Reset if needed */ 3337 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3338 break; 3339 case SND_SOC_DAPM_POST_PMU: 3340 wcd9335_config_compander(comp, w->shift, event); 3341 val = snd_soc_component_read(comp, gain_reg); 3342 val += offset_val; 3343 snd_soc_component_write(comp, gain_reg, val); 3344 break; 3345 case SND_SOC_DAPM_POST_PMD: 3346 wcd9335_config_compander(comp, w->shift, event); 3347 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3348 break; 3349 } 3350 3351 return 0; 3352 } 3353 3354 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3355 u8 gain) 3356 { 3357 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3358 u8 hph_l_en, hph_r_en; 3359 u8 l_val, r_val; 3360 u8 hph_pa_status; 3361 bool is_hphl_pa, is_hphr_pa; 3362 3363 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3364 is_hphl_pa = hph_pa_status >> 7; 3365 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3366 3367 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3368 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3369 3370 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3371 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3372 3373 /* 3374 * Set HPH_L & HPH_R gain source selection to REGISTER 3375 * for better click and pop only if corresponding PAs are 3376 * not enabled. Also cache the values of the HPHL/R 3377 * PA gains to be applied after PAs are enabled 3378 */ 3379 if ((l_val != hph_l_en) && !is_hphl_pa) { 3380 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3381 wcd->hph_l_gain = hph_l_en & 0x1F; 3382 } 3383 3384 if ((r_val != hph_r_en) && !is_hphr_pa) { 3385 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3386 wcd->hph_r_gain = hph_r_en & 0x1F; 3387 } 3388 } 3389 3390 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3391 int event) 3392 { 3393 if (SND_SOC_DAPM_EVENT_ON(event)) { 3394 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3395 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3396 0x06); 3397 snd_soc_component_update_bits(comp, 3398 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3399 0xF0, 0x40); 3400 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3401 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3402 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3403 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3404 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3405 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3406 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3407 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3408 0x0C); 3409 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3410 } 3411 3412 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3413 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3414 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3415 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3416 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3417 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3418 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3419 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3420 0x8A); 3421 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3422 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3423 0x0A); 3424 } 3425 } 3426 3427 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3428 int event) 3429 { 3430 if (SND_SOC_DAPM_EVENT_ON(event)) { 3431 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3432 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3433 0x0C); 3434 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3435 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3436 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3437 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3438 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3439 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3440 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3441 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3442 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3443 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3444 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3445 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3446 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3447 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3448 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3449 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3450 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3451 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3452 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3453 snd_soc_component_update_bits(comp, 3454 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3455 snd_soc_component_update_bits(comp, 3456 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3457 } 3458 3459 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3460 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3461 0x88); 3462 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3463 0x33); 3464 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3465 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3466 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3467 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3468 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3469 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3470 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3471 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3472 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3473 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3474 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3475 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3476 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3477 WCD9335_HPH_CONST_SEL_L_MASK, 3478 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3479 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3480 WCD9335_HPH_CONST_SEL_L_MASK, 3481 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3482 } 3483 } 3484 3485 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3486 int event) 3487 { 3488 if (SND_SOC_DAPM_EVENT_ON(event)) { 3489 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3490 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3491 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3492 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3493 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3494 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3495 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3496 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3497 0x0C); 3498 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3499 } 3500 3501 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3502 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3503 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3504 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3505 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3506 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3507 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3508 } 3509 } 3510 3511 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3512 int event, int mode) 3513 { 3514 switch (mode) { 3515 case CLS_H_LP: 3516 wcd9335_codec_hph_lp_config(component, event); 3517 break; 3518 case CLS_H_LOHIFI: 3519 wcd9335_codec_hph_lohifi_config(component, event); 3520 break; 3521 case CLS_H_HIFI: 3522 wcd9335_codec_hph_hifi_config(component, event); 3523 break; 3524 } 3525 } 3526 3527 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3528 struct snd_kcontrol *kc, 3529 int event) 3530 { 3531 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3532 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3533 int hph_mode = wcd->hph_mode; 3534 u8 dem_inp; 3535 3536 switch (event) { 3537 case SND_SOC_DAPM_PRE_PMU: 3538 /* Read DEM INP Select */ 3539 dem_inp = snd_soc_component_read(comp, 3540 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3541 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3542 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3543 dev_err(comp->dev, "Incorrect DEM Input\n"); 3544 return -EINVAL; 3545 } 3546 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3547 WCD_CLSH_STATE_HPHL, 3548 ((hph_mode == CLS_H_LOHIFI) ? 3549 CLS_H_HIFI : hph_mode)); 3550 3551 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3552 3553 break; 3554 case SND_SOC_DAPM_POST_PMU: 3555 usleep_range(1000, 1100); 3556 break; 3557 case SND_SOC_DAPM_PRE_PMD: 3558 break; 3559 case SND_SOC_DAPM_POST_PMD: 3560 /* 1000us required as per HW requirement */ 3561 usleep_range(1000, 1100); 3562 3563 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3564 WCD_CLSH_STATE_HPHR)) 3565 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3566 3567 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3568 WCD_CLSH_STATE_HPHL, 3569 ((hph_mode == CLS_H_LOHIFI) ? 3570 CLS_H_HIFI : hph_mode)); 3571 break; 3572 } 3573 3574 return 0; 3575 } 3576 3577 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3578 struct snd_kcontrol *kc, int event) 3579 { 3580 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3581 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3582 3583 switch (event) { 3584 case SND_SOC_DAPM_PRE_PMU: 3585 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3586 WCD_CLSH_STATE_LO, CLS_AB); 3587 break; 3588 case SND_SOC_DAPM_POST_PMD: 3589 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3590 WCD_CLSH_STATE_LO, CLS_AB); 3591 break; 3592 } 3593 3594 return 0; 3595 } 3596 3597 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3598 struct snd_kcontrol *kc, int event) 3599 { 3600 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3601 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3602 3603 switch (event) { 3604 case SND_SOC_DAPM_PRE_PMU: 3605 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3606 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3607 3608 break; 3609 case SND_SOC_DAPM_POST_PMD: 3610 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3611 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3612 break; 3613 } 3614 3615 return 0; 3616 } 3617 3618 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3619 int mode, int event) 3620 { 3621 u8 scale_val = 0; 3622 3623 switch (event) { 3624 case SND_SOC_DAPM_POST_PMU: 3625 switch (mode) { 3626 case CLS_H_HIFI: 3627 scale_val = 0x3; 3628 break; 3629 case CLS_H_LOHIFI: 3630 scale_val = 0x1; 3631 break; 3632 } 3633 break; 3634 case SND_SOC_DAPM_PRE_PMD: 3635 scale_val = 0x6; 3636 break; 3637 } 3638 3639 if (scale_val) 3640 snd_soc_component_update_bits(wcd->component, 3641 WCD9335_HPH_PA_CTL1, 3642 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3643 scale_val << 1); 3644 if (SND_SOC_DAPM_EVENT_ON(event)) { 3645 if (wcd->comp_enabled[COMPANDER_1] || 3646 wcd->comp_enabled[COMPANDER_2]) { 3647 /* GAIN Source Selection */ 3648 snd_soc_component_update_bits(wcd->component, 3649 WCD9335_HPH_L_EN, 3650 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3651 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3652 snd_soc_component_update_bits(wcd->component, 3653 WCD9335_HPH_R_EN, 3654 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3655 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3656 snd_soc_component_update_bits(wcd->component, 3657 WCD9335_HPH_AUTO_CHOP, 3658 WCD9335_HPH_AUTO_CHOP_MASK, 3659 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3660 } 3661 snd_soc_component_update_bits(wcd->component, 3662 WCD9335_HPH_L_EN, 3663 WCD9335_HPH_PA_GAIN_MASK, 3664 wcd->hph_l_gain); 3665 snd_soc_component_update_bits(wcd->component, 3666 WCD9335_HPH_R_EN, 3667 WCD9335_HPH_PA_GAIN_MASK, 3668 wcd->hph_r_gain); 3669 } 3670 3671 if (SND_SOC_DAPM_EVENT_OFF(event)) 3672 snd_soc_component_update_bits(wcd->component, 3673 WCD9335_HPH_AUTO_CHOP, 3674 WCD9335_HPH_AUTO_CHOP_MASK, 3675 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3676 } 3677 3678 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3679 struct snd_kcontrol *kc, 3680 int event) 3681 { 3682 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3683 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3684 int hph_mode = wcd->hph_mode; 3685 u8 dem_inp; 3686 3687 switch (event) { 3688 case SND_SOC_DAPM_PRE_PMU: 3689 3690 /* Read DEM INP Select */ 3691 dem_inp = snd_soc_component_read(comp, 3692 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3693 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3694 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3695 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3696 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3697 hph_mode); 3698 return -EINVAL; 3699 } 3700 3701 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3702 WCD_CLSH_EVENT_PRE_DAC, 3703 WCD_CLSH_STATE_HPHR, 3704 ((hph_mode == CLS_H_LOHIFI) ? 3705 CLS_H_HIFI : hph_mode)); 3706 3707 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3708 3709 break; 3710 case SND_SOC_DAPM_POST_PMD: 3711 /* 1000us required as per HW requirement */ 3712 usleep_range(1000, 1100); 3713 3714 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3715 WCD_CLSH_STATE_HPHL)) 3716 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3717 3718 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3719 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3720 CLS_H_HIFI : hph_mode)); 3721 break; 3722 } 3723 3724 return 0; 3725 } 3726 3727 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3728 struct snd_kcontrol *kc, 3729 int event) 3730 { 3731 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3732 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3733 int hph_mode = wcd->hph_mode; 3734 3735 switch (event) { 3736 case SND_SOC_DAPM_PRE_PMU: 3737 break; 3738 case SND_SOC_DAPM_POST_PMU: 3739 /* 3740 * 7ms sleep is required after PA is enabled as per 3741 * HW requirement 3742 */ 3743 usleep_range(7000, 7100); 3744 3745 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3746 snd_soc_component_update_bits(comp, 3747 WCD9335_CDC_RX1_RX_PATH_CTL, 3748 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3749 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3750 3751 /* Remove mix path mute if it is enabled */ 3752 if ((snd_soc_component_read(comp, 3753 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3754 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3755 snd_soc_component_update_bits(comp, 3756 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3757 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3758 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3759 3760 break; 3761 case SND_SOC_DAPM_PRE_PMD: 3762 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3763 break; 3764 case SND_SOC_DAPM_POST_PMD: 3765 /* 5ms sleep is required after PA is disabled as per 3766 * HW requirement 3767 */ 3768 usleep_range(5000, 5500); 3769 break; 3770 } 3771 3772 return 0; 3773 } 3774 3775 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3776 struct snd_kcontrol *kc, 3777 int event) 3778 { 3779 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3780 int vol_reg = 0, mix_vol_reg = 0; 3781 3782 if (w->reg == WCD9335_ANA_LO_1_2) { 3783 if (w->shift == 7) { 3784 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3785 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3786 } else if (w->shift == 6) { 3787 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3788 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3789 } 3790 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3791 if (w->shift == 7) { 3792 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3793 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3794 } else if (w->shift == 6) { 3795 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3796 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3797 } 3798 } else { 3799 dev_err(comp->dev, "Error enabling lineout PA\n"); 3800 return -EINVAL; 3801 } 3802 3803 switch (event) { 3804 case SND_SOC_DAPM_POST_PMU: 3805 /* 5ms sleep is required after PA is enabled as per 3806 * HW requirement 3807 */ 3808 usleep_range(5000, 5500); 3809 snd_soc_component_update_bits(comp, vol_reg, 3810 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3811 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3812 3813 /* Remove mix path mute if it is enabled */ 3814 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3815 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3816 snd_soc_component_update_bits(comp, mix_vol_reg, 3817 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3818 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3819 break; 3820 case SND_SOC_DAPM_POST_PMD: 3821 /* 5ms sleep is required after PA is disabled as per 3822 * HW requirement 3823 */ 3824 usleep_range(5000, 5500); 3825 break; 3826 } 3827 3828 return 0; 3829 } 3830 3831 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3832 { 3833 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3834 WCD9335_HPH_CONST_SEL_L_MASK, 3835 WCD9335_HPH_CONST_SEL_L_BYPASS); 3836 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3837 WCD9335_HPH_CONST_SEL_L_MASK, 3838 WCD9335_HPH_CONST_SEL_L_BYPASS); 3839 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3840 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3841 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3842 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3843 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3844 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3845 } 3846 3847 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3848 struct snd_kcontrol *kc, int event) 3849 { 3850 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3851 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3852 3853 switch (event) { 3854 case SND_SOC_DAPM_PRE_PMU: 3855 wcd->rx_bias_count++; 3856 if (wcd->rx_bias_count == 1) { 3857 wcd9335_codec_init_flyback(comp); 3858 snd_soc_component_update_bits(comp, 3859 WCD9335_ANA_RX_SUPPLIES, 3860 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3861 WCD9335_ANA_RX_BIAS_ENABLE); 3862 } 3863 break; 3864 case SND_SOC_DAPM_POST_PMD: 3865 wcd->rx_bias_count--; 3866 if (!wcd->rx_bias_count) 3867 snd_soc_component_update_bits(comp, 3868 WCD9335_ANA_RX_SUPPLIES, 3869 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3870 WCD9335_ANA_RX_BIAS_DISABLE); 3871 break; 3872 } 3873 3874 return 0; 3875 } 3876 3877 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3878 struct snd_kcontrol *kc, int event) 3879 { 3880 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3881 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3882 int hph_mode = wcd->hph_mode; 3883 3884 switch (event) { 3885 case SND_SOC_DAPM_PRE_PMU: 3886 break; 3887 case SND_SOC_DAPM_POST_PMU: 3888 /* 3889 * 7ms sleep is required after PA is enabled as per 3890 * HW requirement 3891 */ 3892 usleep_range(7000, 7100); 3893 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3894 snd_soc_component_update_bits(comp, 3895 WCD9335_CDC_RX2_RX_PATH_CTL, 3896 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3897 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3898 /* Remove mix path mute if it is enabled */ 3899 if ((snd_soc_component_read(comp, 3900 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3901 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3902 snd_soc_component_update_bits(comp, 3903 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3904 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3905 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3906 3907 break; 3908 3909 case SND_SOC_DAPM_PRE_PMD: 3910 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3911 break; 3912 case SND_SOC_DAPM_POST_PMD: 3913 /* 5ms sleep is required after PA is disabled as per 3914 * HW requirement 3915 */ 3916 usleep_range(5000, 5500); 3917 break; 3918 } 3919 3920 return 0; 3921 } 3922 3923 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3924 struct snd_kcontrol *kc, int event) 3925 { 3926 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3927 3928 switch (event) { 3929 case SND_SOC_DAPM_POST_PMU: 3930 /* 5ms sleep is required after PA is enabled as per 3931 * HW requirement 3932 */ 3933 usleep_range(5000, 5500); 3934 snd_soc_component_update_bits(comp, 3935 WCD9335_CDC_RX0_RX_PATH_CTL, 3936 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3937 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3938 /* Remove mix path mute if it is enabled */ 3939 if ((snd_soc_component_read(comp, 3940 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3941 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3942 snd_soc_component_update_bits(comp, 3943 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3944 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3945 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3946 break; 3947 case SND_SOC_DAPM_POST_PMD: 3948 /* 5ms sleep is required after PA is disabled as per 3949 * HW requirement 3950 */ 3951 usleep_range(5000, 5500); 3952 3953 break; 3954 } 3955 3956 return 0; 3957 } 3958 3959 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3960 { 3961 struct wcd9335_codec *wcd = data; 3962 unsigned long status = 0; 3963 int i, j, port_id; 3964 unsigned int val, int_val = 0; 3965 irqreturn_t ret = IRQ_NONE; 3966 bool tx; 3967 unsigned short reg = 0; 3968 3969 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3970 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3971 regmap_read(wcd->if_regmap, i, &val); 3972 status |= ((u32)val << (8 * j)); 3973 } 3974 3975 for_each_set_bit(j, &status, 32) { 3976 tx = (j >= 16); 3977 port_id = (tx ? j - 16 : j); 3978 regmap_read(wcd->if_regmap, 3979 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3980 if (val) { 3981 if (!tx) 3982 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3983 (port_id / 8); 3984 else 3985 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3986 (port_id / 8); 3987 regmap_read( 3988 wcd->if_regmap, reg, &int_val); 3989 /* 3990 * Ignore interrupts for ports for which the 3991 * interrupts are not specifically enabled. 3992 */ 3993 if (!(int_val & (1 << (port_id % 8)))) 3994 continue; 3995 } 3996 3997 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 3998 dev_err_ratelimited(wcd->dev, 3999 "%s: overflow error on %s port %d, value %x\n", 4000 __func__, (tx ? "TX" : "RX"), port_id, val); 4001 4002 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 4003 dev_err_ratelimited(wcd->dev, 4004 "%s: underflow error on %s port %d, value %x\n", 4005 __func__, (tx ? "TX" : "RX"), port_id, val); 4006 4007 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4008 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4009 if (!tx) 4010 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4011 (port_id / 8); 4012 else 4013 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4014 (port_id / 8); 4015 regmap_read( 4016 wcd->if_regmap, reg, &int_val); 4017 if (int_val & (1 << (port_id % 8))) { 4018 int_val = int_val ^ (1 << (port_id % 8)); 4019 regmap_write(wcd->if_regmap, 4020 reg, int_val); 4021 } 4022 } 4023 4024 regmap_write(wcd->if_regmap, 4025 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4026 BIT(j % 8)); 4027 ret = IRQ_HANDLED; 4028 } 4029 4030 return ret; 4031 } 4032 4033 static struct wcd9335_irq wcd9335_irqs[] = { 4034 { 4035 .irq = WCD9335_IRQ_SLIMBUS, 4036 .handler = wcd9335_slimbus_irq, 4037 .name = "SLIM Slave", 4038 }, 4039 }; 4040 4041 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4042 { 4043 int irq, ret, i; 4044 4045 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4046 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4047 if (irq < 0) { 4048 dev_err(wcd->dev, "Failed to get %s\n", 4049 wcd9335_irqs[i].name); 4050 return irq; 4051 } 4052 4053 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4054 wcd9335_irqs[i].handler, 4055 IRQF_TRIGGER_RISING | 4056 IRQF_ONESHOT, 4057 wcd9335_irqs[i].name, wcd); 4058 if (ret) { 4059 dev_err(wcd->dev, "Failed to request %s\n", 4060 wcd9335_irqs[i].name); 4061 return ret; 4062 } 4063 } 4064 4065 /* enable interrupts on all slave ports */ 4066 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4067 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4068 0xFF); 4069 4070 return ret; 4071 } 4072 4073 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4074 { 4075 int i; 4076 4077 /* disable interrupts on all slave ports */ 4078 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4079 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4080 0x00); 4081 } 4082 4083 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4084 bool ccl_flag) 4085 { 4086 struct snd_soc_component *comp = wcd->component; 4087 4088 if (ccl_flag) { 4089 if (++wcd->sido_ccl_cnt == 1) 4090 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4091 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4092 } else { 4093 if (wcd->sido_ccl_cnt == 0) { 4094 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4095 return; 4096 } 4097 if (--wcd->sido_ccl_cnt == 0) 4098 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4099 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4100 } 4101 } 4102 4103 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4104 { 4105 wcd->master_bias_users++; 4106 if (wcd->master_bias_users == 1) { 4107 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4108 WCD9335_ANA_BIAS_EN_MASK, 4109 WCD9335_ANA_BIAS_ENABLE); 4110 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4111 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4112 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4113 /* 4114 * 1ms delay is required after pre-charge is enabled 4115 * as per HW requirement 4116 */ 4117 usleep_range(1000, 1100); 4118 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4119 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4120 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4121 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4122 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4123 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4124 } 4125 4126 return 0; 4127 } 4128 4129 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4130 { 4131 /* Enable mclk requires master bias to be enabled first */ 4132 if (wcd->master_bias_users <= 0) 4133 return -EINVAL; 4134 4135 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4136 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4137 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4138 wcd->clk_type); 4139 return -EINVAL; 4140 } 4141 4142 if (++wcd->clk_mclk_users == 1) { 4143 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4144 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4145 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4146 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4147 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4148 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4149 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4150 WCD9335_ANA_CLK_MCLK_EN_MASK, 4151 WCD9335_ANA_CLK_MCLK_ENABLE); 4152 regmap_update_bits(wcd->regmap, 4153 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4154 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4155 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4156 regmap_update_bits(wcd->regmap, 4157 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4158 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4159 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4160 /* 4161 * 10us sleep is required after clock is enabled 4162 * as per HW requirement 4163 */ 4164 usleep_range(10, 15); 4165 } 4166 4167 wcd->clk_type = WCD_CLK_MCLK; 4168 4169 return 0; 4170 } 4171 4172 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4173 { 4174 if (wcd->clk_mclk_users <= 0) 4175 return -EINVAL; 4176 4177 if (--wcd->clk_mclk_users == 0) { 4178 if (wcd->clk_rco_users > 0) { 4179 /* MCLK to RCO switch */ 4180 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4181 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4182 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4183 wcd->clk_type = WCD_CLK_RCO; 4184 } else { 4185 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4186 WCD9335_ANA_CLK_MCLK_EN_MASK, 4187 WCD9335_ANA_CLK_MCLK_DISABLE); 4188 wcd->clk_type = WCD_CLK_OFF; 4189 } 4190 4191 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4192 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4193 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4194 } 4195 4196 return 0; 4197 } 4198 4199 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4200 { 4201 if (wcd->master_bias_users <= 0) 4202 return -EINVAL; 4203 4204 wcd->master_bias_users--; 4205 if (wcd->master_bias_users == 0) { 4206 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4207 WCD9335_ANA_BIAS_EN_MASK, 4208 WCD9335_ANA_BIAS_DISABLE); 4209 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4210 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4211 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4212 } 4213 return 0; 4214 } 4215 4216 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4217 bool enable) 4218 { 4219 int ret = 0; 4220 4221 if (enable) { 4222 wcd9335_cdc_sido_ccl_enable(wcd, true); 4223 ret = clk_prepare_enable(wcd->mclk); 4224 if (ret) { 4225 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4226 __func__); 4227 goto err; 4228 } 4229 /* get BG */ 4230 wcd9335_enable_master_bias(wcd); 4231 /* get MCLK */ 4232 wcd9335_enable_mclk(wcd); 4233 4234 } else { 4235 /* put MCLK */ 4236 wcd9335_disable_mclk(wcd); 4237 /* put BG */ 4238 wcd9335_disable_master_bias(wcd); 4239 clk_disable_unprepare(wcd->mclk); 4240 wcd9335_cdc_sido_ccl_enable(wcd, false); 4241 } 4242 err: 4243 return ret; 4244 } 4245 4246 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4247 enum wcd9335_sido_voltage req_mv) 4248 { 4249 struct snd_soc_component *comp = wcd->component; 4250 int vout_d_val; 4251 4252 if (req_mv == wcd->sido_voltage) 4253 return; 4254 4255 /* compute the vout_d step value */ 4256 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4257 WCD9335_ANA_BUCK_VOUT_MASK; 4258 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4259 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4260 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4261 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4262 4263 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4264 usleep_range(1000, 1100); 4265 wcd->sido_voltage = req_mv; 4266 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4267 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4268 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4269 } 4270 4271 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4272 enum wcd9335_sido_voltage req_mv) 4273 { 4274 int ret = 0; 4275 4276 /* enable mclk before setting SIDO voltage */ 4277 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4278 if (ret) { 4279 dev_err(wcd->dev, "Ext clk enable failed\n"); 4280 goto err; 4281 } 4282 4283 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4284 wcd9335_cdc_req_mclk_enable(wcd, false); 4285 4286 err: 4287 return ret; 4288 } 4289 4290 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4291 int enable) 4292 { 4293 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4294 int ret; 4295 4296 if (enable) { 4297 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4298 if (ret) 4299 return ret; 4300 4301 wcd9335_codec_apply_sido_voltage(wcd, 4302 SIDO_VOLTAGE_NOMINAL_MV); 4303 } else { 4304 wcd9335_codec_update_sido_voltage(wcd, 4305 wcd->sido_voltage); 4306 wcd9335_cdc_req_mclk_enable(wcd, false); 4307 } 4308 4309 return 0; 4310 } 4311 4312 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4313 struct snd_kcontrol *kc, int event) 4314 { 4315 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4316 4317 switch (event) { 4318 case SND_SOC_DAPM_PRE_PMU: 4319 return _wcd9335_codec_enable_mclk(comp, true); 4320 case SND_SOC_DAPM_POST_PMD: 4321 return _wcd9335_codec_enable_mclk(comp, false); 4322 } 4323 4324 return 0; 4325 } 4326 4327 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4328 /* TODO SPK1 & SPK2 OUT*/ 4329 SND_SOC_DAPM_OUTPUT("EAR"), 4330 SND_SOC_DAPM_OUTPUT("HPHL"), 4331 SND_SOC_DAPM_OUTPUT("HPHR"), 4332 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4333 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4334 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4335 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4336 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4337 AIF1_PB, 0, wcd9335_codec_enable_slim, 4338 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4339 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4340 AIF2_PB, 0, wcd9335_codec_enable_slim, 4341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4342 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4343 AIF3_PB, 0, wcd9335_codec_enable_slim, 4344 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4345 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4346 AIF4_PB, 0, wcd9335_codec_enable_slim, 4347 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4348 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4349 &slim_rx_mux[WCD9335_RX0]), 4350 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4351 &slim_rx_mux[WCD9335_RX1]), 4352 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4353 &slim_rx_mux[WCD9335_RX2]), 4354 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4355 &slim_rx_mux[WCD9335_RX3]), 4356 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4357 &slim_rx_mux[WCD9335_RX4]), 4358 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4359 &slim_rx_mux[WCD9335_RX5]), 4360 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4361 &slim_rx_mux[WCD9335_RX6]), 4362 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4363 &slim_rx_mux[WCD9335_RX7]), 4364 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4365 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4366 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4367 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4368 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4369 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4370 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4371 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4372 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4373 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4374 SND_SOC_DAPM_POST_PMU), 4375 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4376 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4377 SND_SOC_DAPM_POST_PMU), 4378 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4379 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4380 SND_SOC_DAPM_POST_PMU), 4381 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4382 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4383 SND_SOC_DAPM_POST_PMU), 4384 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4385 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4386 SND_SOC_DAPM_POST_PMU), 4387 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4388 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4389 SND_SOC_DAPM_POST_PMU), 4390 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4391 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4392 SND_SOC_DAPM_POST_PMU), 4393 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4394 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4395 SND_SOC_DAPM_POST_PMU), 4396 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4397 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4398 SND_SOC_DAPM_POST_PMU), 4399 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4400 &rx_int0_1_mix_inp0_mux), 4401 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4402 &rx_int0_1_mix_inp1_mux), 4403 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4404 &rx_int0_1_mix_inp2_mux), 4405 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4406 &rx_int1_1_mix_inp0_mux), 4407 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4408 &rx_int1_1_mix_inp1_mux), 4409 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4410 &rx_int1_1_mix_inp2_mux), 4411 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4412 &rx_int2_1_mix_inp0_mux), 4413 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4414 &rx_int2_1_mix_inp1_mux), 4415 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4416 &rx_int2_1_mix_inp2_mux), 4417 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4418 &rx_int3_1_mix_inp0_mux), 4419 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4420 &rx_int3_1_mix_inp1_mux), 4421 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4422 &rx_int3_1_mix_inp2_mux), 4423 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4424 &rx_int4_1_mix_inp0_mux), 4425 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4426 &rx_int4_1_mix_inp1_mux), 4427 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4428 &rx_int4_1_mix_inp2_mux), 4429 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4430 &rx_int5_1_mix_inp0_mux), 4431 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4432 &rx_int5_1_mix_inp1_mux), 4433 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4434 &rx_int5_1_mix_inp2_mux), 4435 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4436 &rx_int6_1_mix_inp0_mux), 4437 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4438 &rx_int6_1_mix_inp1_mux), 4439 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4440 &rx_int6_1_mix_inp2_mux), 4441 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4442 &rx_int7_1_mix_inp0_mux), 4443 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4444 &rx_int7_1_mix_inp1_mux), 4445 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4446 &rx_int7_1_mix_inp2_mux), 4447 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4448 &rx_int8_1_mix_inp0_mux), 4449 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4450 &rx_int8_1_mix_inp1_mux), 4451 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4452 &rx_int8_1_mix_inp2_mux), 4453 4454 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4455 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4456 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4457 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4458 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4459 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4460 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4461 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4467 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4468 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4469 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 4473 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4477 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4478 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4479 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4480 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4481 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4482 4483 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4484 &rx_int0_dem_inp_mux), 4485 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4486 &rx_int1_dem_inp_mux), 4487 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4488 &rx_int2_dem_inp_mux), 4489 4490 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4491 INTERP_EAR, 0, &rx_int0_interp_mux, 4492 wcd9335_codec_enable_interpolator, 4493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4494 SND_SOC_DAPM_POST_PMD), 4495 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4496 INTERP_HPHL, 0, &rx_int1_interp_mux, 4497 wcd9335_codec_enable_interpolator, 4498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4499 SND_SOC_DAPM_POST_PMD), 4500 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4501 INTERP_HPHR, 0, &rx_int2_interp_mux, 4502 wcd9335_codec_enable_interpolator, 4503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4504 SND_SOC_DAPM_POST_PMD), 4505 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4506 INTERP_LO1, 0, &rx_int3_interp_mux, 4507 wcd9335_codec_enable_interpolator, 4508 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4509 SND_SOC_DAPM_POST_PMD), 4510 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4511 INTERP_LO2, 0, &rx_int4_interp_mux, 4512 wcd9335_codec_enable_interpolator, 4513 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4514 SND_SOC_DAPM_POST_PMD), 4515 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4516 INTERP_LO3, 0, &rx_int5_interp_mux, 4517 wcd9335_codec_enable_interpolator, 4518 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4519 SND_SOC_DAPM_POST_PMD), 4520 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4521 INTERP_LO4, 0, &rx_int6_interp_mux, 4522 wcd9335_codec_enable_interpolator, 4523 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4524 SND_SOC_DAPM_POST_PMD), 4525 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4526 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4527 wcd9335_codec_enable_interpolator, 4528 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4529 SND_SOC_DAPM_POST_PMD), 4530 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4531 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4532 wcd9335_codec_enable_interpolator, 4533 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4534 SND_SOC_DAPM_POST_PMD), 4535 4536 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4537 0, 0, wcd9335_codec_ear_dac_event, 4538 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4539 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4540 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4541 5, 0, wcd9335_codec_hphl_dac_event, 4542 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4543 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4544 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4545 4, 0, wcd9335_codec_hphr_dac_event, 4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4547 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4548 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4549 0, 0, wcd9335_codec_lineout_dac_event, 4550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4551 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4552 0, 0, wcd9335_codec_lineout_dac_event, 4553 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4554 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4555 0, 0, wcd9335_codec_lineout_dac_event, 4556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4557 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4558 0, 0, wcd9335_codec_lineout_dac_event, 4559 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4560 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4561 wcd9335_codec_enable_hphl_pa, 4562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4563 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4564 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4565 wcd9335_codec_enable_hphr_pa, 4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4567 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4568 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4569 wcd9335_codec_enable_ear_pa, 4570 SND_SOC_DAPM_POST_PMU | 4571 SND_SOC_DAPM_POST_PMD), 4572 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4573 wcd9335_codec_enable_lineout_pa, 4574 SND_SOC_DAPM_POST_PMU | 4575 SND_SOC_DAPM_POST_PMD), 4576 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4577 wcd9335_codec_enable_lineout_pa, 4578 SND_SOC_DAPM_POST_PMU | 4579 SND_SOC_DAPM_POST_PMD), 4580 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4581 wcd9335_codec_enable_lineout_pa, 4582 SND_SOC_DAPM_POST_PMU | 4583 SND_SOC_DAPM_POST_PMD), 4584 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4585 wcd9335_codec_enable_lineout_pa, 4586 SND_SOC_DAPM_POST_PMU | 4587 SND_SOC_DAPM_POST_PMD), 4588 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4589 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4590 SND_SOC_DAPM_POST_PMD), 4591 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4592 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4593 SND_SOC_DAPM_POST_PMD), 4594 4595 /* TX */ 4596 SND_SOC_DAPM_INPUT("AMIC1"), 4597 SND_SOC_DAPM_INPUT("AMIC2"), 4598 SND_SOC_DAPM_INPUT("AMIC3"), 4599 SND_SOC_DAPM_INPUT("AMIC4"), 4600 SND_SOC_DAPM_INPUT("AMIC5"), 4601 SND_SOC_DAPM_INPUT("AMIC6"), 4602 4603 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4604 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4605 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4606 4607 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4608 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4609 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4610 4611 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4612 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4613 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4614 4615 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4616 wcd9335_codec_enable_micbias, 4617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4618 SND_SOC_DAPM_POST_PMD), 4619 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4620 wcd9335_codec_enable_micbias, 4621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4622 SND_SOC_DAPM_POST_PMD), 4623 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4624 wcd9335_codec_enable_micbias, 4625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4626 SND_SOC_DAPM_POST_PMD), 4627 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4628 wcd9335_codec_enable_micbias, 4629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4630 SND_SOC_DAPM_POST_PMD), 4631 4632 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4633 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4634 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4635 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4636 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4637 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4638 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4639 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4640 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4641 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4642 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4643 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4644 4645 /* Digital Mic Inputs */ 4646 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4647 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4648 SND_SOC_DAPM_POST_PMD), 4649 4650 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4651 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4652 SND_SOC_DAPM_POST_PMD), 4653 4654 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4655 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4656 SND_SOC_DAPM_POST_PMD), 4657 4658 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4659 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4660 SND_SOC_DAPM_POST_PMD), 4661 4662 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4663 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4664 SND_SOC_DAPM_POST_PMD), 4665 4666 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4667 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4668 SND_SOC_DAPM_POST_PMD), 4669 4670 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4671 &tx_dmic_mux0), 4672 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4673 &tx_dmic_mux1), 4674 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4675 &tx_dmic_mux2), 4676 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4677 &tx_dmic_mux3), 4678 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4679 &tx_dmic_mux4), 4680 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4681 &tx_dmic_mux5), 4682 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4683 &tx_dmic_mux6), 4684 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4685 &tx_dmic_mux7), 4686 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4687 &tx_dmic_mux8), 4688 4689 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4690 &tx_amic_mux0), 4691 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4692 &tx_amic_mux1), 4693 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4694 &tx_amic_mux2), 4695 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4696 &tx_amic_mux3), 4697 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4698 &tx_amic_mux4), 4699 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4700 &tx_amic_mux5), 4701 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4702 &tx_amic_mux6), 4703 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4704 &tx_amic_mux7), 4705 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4706 &tx_amic_mux8), 4707 4708 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4709 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4710 4711 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4712 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4713 4714 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4715 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4716 4717 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4718 &sb_tx0_mux), 4719 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4720 &sb_tx1_mux), 4721 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4722 &sb_tx2_mux), 4723 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4724 &sb_tx3_mux), 4725 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4726 &sb_tx4_mux), 4727 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4728 &sb_tx5_mux), 4729 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4730 &sb_tx6_mux), 4731 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4732 &sb_tx7_mux), 4733 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4734 &sb_tx8_mux), 4735 4736 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4737 &tx_adc_mux0, wcd9335_codec_enable_dec, 4738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4739 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4740 4741 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4742 &tx_adc_mux1, wcd9335_codec_enable_dec, 4743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4744 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4745 4746 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4747 &tx_adc_mux2, wcd9335_codec_enable_dec, 4748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4749 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4750 4751 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4752 &tx_adc_mux3, wcd9335_codec_enable_dec, 4753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4754 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4755 4756 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4757 &tx_adc_mux4, wcd9335_codec_enable_dec, 4758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4759 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4760 4761 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4762 &tx_adc_mux5, wcd9335_codec_enable_dec, 4763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4764 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4765 4766 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4767 &tx_adc_mux6, wcd9335_codec_enable_dec, 4768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4769 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4770 4771 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4772 &tx_adc_mux7, wcd9335_codec_enable_dec, 4773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4774 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4775 4776 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4777 &tx_adc_mux8, wcd9335_codec_enable_dec, 4778 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4779 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4780 }; 4781 4782 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4783 { 4784 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4785 4786 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4787 WCD9335_ANA_RCO_BG_EN_MASK, 4788 WCD9335_ANA_RCO_BG_ENABLE); 4789 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4790 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4791 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4792 /* 100us sleep needed after IREF settings */ 4793 usleep_range(100, 110); 4794 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4795 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4796 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4797 /* 100us sleep needed after VREF settings */ 4798 usleep_range(100, 110); 4799 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4800 } 4801 4802 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4803 { 4804 _wcd9335_codec_enable_mclk(comp, true); 4805 snd_soc_component_update_bits(comp, 4806 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4807 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4808 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4809 /* 4810 * 5ms sleep required after enabling efuse control 4811 * before checking the status. 4812 */ 4813 usleep_range(5000, 5500); 4814 4815 if (!(snd_soc_component_read(comp, 4816 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4817 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4818 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4819 4820 wcd9335_enable_sido_buck(comp); 4821 _wcd9335_codec_enable_mclk(comp, false); 4822 4823 return 0; 4824 } 4825 4826 static void wcd9335_codec_init(struct snd_soc_component *component) 4827 { 4828 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4829 int i; 4830 4831 /* ungate MCLK and set clk rate */ 4832 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4833 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4834 4835 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4836 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4837 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4838 4839 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4840 snd_soc_component_update_bits(component, 4841 wcd9335_codec_reg_init[i].reg, 4842 wcd9335_codec_reg_init[i].mask, 4843 wcd9335_codec_reg_init[i].val); 4844 4845 wcd9335_enable_efuse_sensing(component); 4846 } 4847 4848 static int wcd9335_codec_probe(struct snd_soc_component *component) 4849 { 4850 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4851 int ret; 4852 int i; 4853 4854 snd_soc_component_init_regmap(component, wcd->regmap); 4855 /* Class-H Init*/ 4856 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4857 if (IS_ERR(wcd->clsh_ctrl)) 4858 return PTR_ERR(wcd->clsh_ctrl); 4859 4860 /* Default HPH Mode to Class-H HiFi */ 4861 wcd->hph_mode = CLS_H_HIFI; 4862 wcd->component = component; 4863 4864 wcd9335_codec_init(component); 4865 4866 for (i = 0; i < NUM_CODEC_DAIS; i++) 4867 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4868 4869 ret = wcd9335_setup_irqs(wcd); 4870 if (ret) 4871 goto free_clsh_ctrl; 4872 4873 return 0; 4874 4875 free_clsh_ctrl: 4876 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4877 return ret; 4878 } 4879 4880 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4881 { 4882 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4883 4884 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4885 wcd9335_teardown_irqs(wcd); 4886 } 4887 4888 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4889 int clk_id, int source, 4890 unsigned int freq, int dir) 4891 { 4892 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4893 4894 wcd->mclk_rate = freq; 4895 4896 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4897 snd_soc_component_update_bits(comp, 4898 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4899 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4900 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4901 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4902 snd_soc_component_update_bits(comp, 4903 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4904 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4905 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4906 4907 return clk_set_rate(wcd->mclk, freq); 4908 } 4909 4910 static const struct snd_soc_component_driver wcd9335_component_drv = { 4911 .probe = wcd9335_codec_probe, 4912 .remove = wcd9335_codec_remove, 4913 .set_sysclk = wcd9335_codec_set_sysclk, 4914 .controls = wcd9335_snd_controls, 4915 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4916 .dapm_widgets = wcd9335_dapm_widgets, 4917 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4918 .dapm_routes = wcd9335_audio_map, 4919 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4920 .endianness = 1, 4921 }; 4922 4923 static int wcd9335_probe(struct wcd9335_codec *wcd) 4924 { 4925 struct device *dev = wcd->dev; 4926 4927 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4928 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4929 4930 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4931 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4932 4933 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4934 wcd9335_slim_dais, 4935 ARRAY_SIZE(wcd9335_slim_dais)); 4936 } 4937 4938 static const struct regmap_range_cfg wcd9335_ranges[] = { 4939 { 4940 .name = "WCD9335", 4941 .range_min = 0x0, 4942 .range_max = WCD9335_MAX_REGISTER, 4943 .selector_reg = WCD9335_SEL_REGISTER, 4944 .selector_mask = 0xff, 4945 .selector_shift = 0, 4946 .window_start = 0x800, 4947 .window_len = 0x100, 4948 }, 4949 }; 4950 4951 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4952 { 4953 switch (reg) { 4954 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4955 case WCD9335_ANA_MBHC_RESULT_3: 4956 case WCD9335_ANA_MBHC_RESULT_2: 4957 case WCD9335_ANA_MBHC_RESULT_1: 4958 case WCD9335_ANA_MBHC_MECH: 4959 case WCD9335_ANA_MBHC_ELECT: 4960 case WCD9335_ANA_MBHC_ZDET: 4961 case WCD9335_ANA_MICB2: 4962 case WCD9335_ANA_RCO: 4963 case WCD9335_ANA_BIAS: 4964 return true; 4965 default: 4966 return false; 4967 } 4968 } 4969 4970 static struct regmap_config wcd9335_regmap_config = { 4971 .reg_bits = 16, 4972 .val_bits = 8, 4973 .cache_type = REGCACHE_RBTREE, 4974 .max_register = WCD9335_MAX_REGISTER, 4975 .can_multi_write = true, 4976 .ranges = wcd9335_ranges, 4977 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4978 .volatile_reg = wcd9335_is_volatile_register, 4979 }; 4980 4981 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4982 { 4983 .name = "WCD9335-IFC-DEV", 4984 .range_min = 0x0, 4985 .range_max = WCD9335_MAX_REGISTER, 4986 .selector_reg = WCD9335_SEL_REGISTER, 4987 .selector_mask = 0xfff, 4988 .selector_shift = 0, 4989 .window_start = 0x800, 4990 .window_len = 0x400, 4991 }, 4992 }; 4993 4994 static struct regmap_config wcd9335_ifc_regmap_config = { 4995 .reg_bits = 16, 4996 .val_bits = 8, 4997 .can_multi_write = true, 4998 .max_register = WCD9335_MAX_REGISTER, 4999 .ranges = wcd9335_ifc_ranges, 5000 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 5001 }; 5002 5003 static const struct regmap_irq wcd9335_codec_irqs[] = { 5004 /* INTR_REG 0 */ 5005 [WCD9335_IRQ_SLIMBUS] = { 5006 .reg_offset = 0, 5007 .mask = BIT(0), 5008 .type = { 5009 .type_reg_offset = 0, 5010 .types_supported = IRQ_TYPE_EDGE_BOTH, 5011 .type_reg_mask = BIT(0), 5012 }, 5013 }, 5014 }; 5015 5016 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5017 .name = "wcd9335_pin1_irq", 5018 .status_base = WCD9335_INTR_PIN1_STATUS0, 5019 .mask_base = WCD9335_INTR_PIN1_MASK0, 5020 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5021 .type_base = WCD9335_INTR_LEVEL0, 5022 .num_type_reg = 4, 5023 .num_regs = 4, 5024 .irqs = wcd9335_codec_irqs, 5025 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5026 }; 5027 5028 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5029 { 5030 struct device *dev = wcd->dev; 5031 struct device_node *np = dev->of_node; 5032 int ret; 5033 5034 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5035 if (wcd->reset_gpio < 0) { 5036 dev_err(dev, "Reset GPIO missing from DT\n"); 5037 return wcd->reset_gpio; 5038 } 5039 5040 wcd->mclk = devm_clk_get(dev, "mclk"); 5041 if (IS_ERR(wcd->mclk)) { 5042 dev_err(dev, "mclk not found\n"); 5043 return PTR_ERR(wcd->mclk); 5044 } 5045 5046 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5047 if (IS_ERR(wcd->native_clk)) { 5048 dev_err(dev, "slimbus clock not found\n"); 5049 return PTR_ERR(wcd->native_clk); 5050 } 5051 5052 wcd->supplies[0].supply = "vdd-buck"; 5053 wcd->supplies[1].supply = "vdd-buck-sido"; 5054 wcd->supplies[2].supply = "vdd-tx"; 5055 wcd->supplies[3].supply = "vdd-rx"; 5056 wcd->supplies[4].supply = "vdd-io"; 5057 5058 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5059 if (ret) { 5060 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5061 return ret; 5062 } 5063 5064 return 0; 5065 } 5066 5067 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5068 { 5069 struct device *dev = wcd->dev; 5070 int ret; 5071 5072 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5073 if (ret) { 5074 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5075 return ret; 5076 } 5077 5078 /* 5079 * For WCD9335, it takes about 600us for the Vout_A and 5080 * Vout_D to be ready after BUCK_SIDO is powered up. 5081 * SYS_RST_N shouldn't be pulled high during this time 5082 * Toggle the reset line to make sure the reset pulse is 5083 * correctly applied 5084 */ 5085 usleep_range(600, 650); 5086 5087 gpio_direction_output(wcd->reset_gpio, 0); 5088 msleep(20); 5089 gpio_set_value(wcd->reset_gpio, 1); 5090 msleep(20); 5091 5092 return 0; 5093 } 5094 5095 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5096 { 5097 struct regmap *rm = wcd->regmap; 5098 int val, byte0; 5099 5100 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5101 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5102 5103 if ((val < 0) || (byte0 < 0)) { 5104 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5105 return -EINVAL; 5106 } 5107 5108 if (byte0 == 0x1) { 5109 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5110 wcd->version = WCD9335_VERSION_2_0; 5111 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5112 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5113 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5114 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5115 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5116 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5117 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5118 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5119 } else { 5120 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5121 return -EINVAL; 5122 } 5123 5124 return 0; 5125 } 5126 5127 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5128 { 5129 int ret; 5130 5131 /* 5132 * INTR1 consists of all possible interrupt sources Ear OCP, 5133 * HPH OCP, MBHC, MAD, VBAT, and SVA 5134 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5135 */ 5136 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5137 if (wcd->intr1 < 0) { 5138 if (wcd->intr1 != -EPROBE_DEFER) 5139 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5140 5141 return wcd->intr1; 5142 } 5143 5144 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5145 IRQF_TRIGGER_HIGH, 0, 5146 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5147 if (ret) 5148 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5149 5150 return ret; 5151 } 5152 5153 static int wcd9335_slim_probe(struct slim_device *slim) 5154 { 5155 struct device *dev = &slim->dev; 5156 struct wcd9335_codec *wcd; 5157 int ret; 5158 5159 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5160 if (!wcd) 5161 return -ENOMEM; 5162 5163 wcd->dev = dev; 5164 ret = wcd9335_parse_dt(wcd); 5165 if (ret) { 5166 dev_err(dev, "Error parsing DT: %d\n", ret); 5167 return ret; 5168 } 5169 5170 ret = wcd9335_power_on_reset(wcd); 5171 if (ret) 5172 return ret; 5173 5174 dev_set_drvdata(dev, wcd); 5175 5176 return 0; 5177 } 5178 5179 static int wcd9335_slim_status(struct slim_device *sdev, 5180 enum slim_device_status status) 5181 { 5182 struct device *dev = &sdev->dev; 5183 struct device_node *ifc_dev_np; 5184 struct wcd9335_codec *wcd; 5185 int ret; 5186 5187 wcd = dev_get_drvdata(dev); 5188 5189 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5190 if (!ifc_dev_np) { 5191 dev_err(dev, "No Interface device found\n"); 5192 return -EINVAL; 5193 } 5194 5195 wcd->slim = sdev; 5196 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5197 of_node_put(ifc_dev_np); 5198 if (!wcd->slim_ifc_dev) { 5199 dev_err(dev, "Unable to get SLIM Interface device\n"); 5200 return -EINVAL; 5201 } 5202 5203 slim_get_logical_addr(wcd->slim_ifc_dev); 5204 5205 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5206 if (IS_ERR(wcd->regmap)) { 5207 dev_err(dev, "Failed to allocate slim register map\n"); 5208 return PTR_ERR(wcd->regmap); 5209 } 5210 5211 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5212 &wcd9335_ifc_regmap_config); 5213 if (IS_ERR(wcd->if_regmap)) { 5214 dev_err(dev, "Failed to allocate ifc register map\n"); 5215 return PTR_ERR(wcd->if_regmap); 5216 } 5217 5218 ret = wcd9335_bring_up(wcd); 5219 if (ret) { 5220 dev_err(dev, "Failed to bringup WCD9335\n"); 5221 return ret; 5222 } 5223 5224 ret = wcd9335_irq_init(wcd); 5225 if (ret) 5226 return ret; 5227 5228 wcd9335_probe(wcd); 5229 5230 return 0; 5231 } 5232 5233 static const struct slim_device_id wcd9335_slim_id[] = { 5234 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5235 {} 5236 }; 5237 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5238 5239 static struct slim_driver wcd9335_slim_driver = { 5240 .driver = { 5241 .name = "wcd9335-slim", 5242 }, 5243 .probe = wcd9335_slim_probe, 5244 .device_status = wcd9335_slim_status, 5245 .id_table = wcd9335_slim_id, 5246 }; 5247 5248 module_slim_driver(wcd9335_slim_driver); 5249 MODULE_DESCRIPTION("WCD9335 slim driver"); 5250 MODULE_LICENSE("GPL v2"); 5251 MODULE_ALIAS("slim:217:1a0:*"); 5252